test/formal: Get rid of wildcard imports

cameel · cameel · commit 4ed86edbc407 · 2021-10-13T16:20:10.000+02:00
diff --git a/test/formal/byte_big.py b/test/formal/byte_big.py
@@ -1,5 +1,6 @@
+from opcodes import BYTE
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 byte(A, X) -> 0
diff --git a/test/formal/byte_equivalence.py b/test/formal/byte_equivalence.py
@@ -1,5 +1,6 @@
+from opcodes import BYTE
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, Concat, Extract
 
 """
 Checks that the byte opcode (implemented using shift) is equivalent to a
diff --git a/test/formal/checked_int_add.py b/test/formal/checked_int_add.py
@@ -1,6 +1,7 @@
+from opcodes import AND, ISZERO, SGT, SLT, SUB
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVSignedMax, BVSignedMin, BVSignedUpCast
+from z3 import BitVec, BVAddNoOverflow, BVAddNoUnderflow, Not
 
 """
 Overflow checked signed integer addition.
diff --git a/test/formal/checked_int_div.py b/test/formal/checked_int_div.py
@@ -1,6 +1,7 @@
+from opcodes import AND, EQ, SUB
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVSignedMin, BVSignedUpCast
+from z3 import BitVec, BVSDivNoOverflow, Not
 
 """
 Overflow checked signed integer division.
diff --git a/test/formal/checked_int_mul_16.py b/test/formal/checked_int_mul_16.py
@@ -1,6 +1,7 @@
+from opcodes import AND, DIV, GT, SDIV, SGT, SLT
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVSignedMax, BVSignedMin, BVSignedUpCast
+from z3 import BVMulNoOverflow, BVMulNoUnderflow, BitVec, Not, Or
 
 """
 Overflow checked signed integer multiplication.
diff --git a/test/formal/checked_int_sub.py b/test/formal/checked_int_sub.py
@@ -1,6 +1,7 @@
+from opcodes import AND, ADD, ISZERO, SLT, SGT
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVSignedMax, BVSignedMin, BVSignedUpCast
+from z3 import BitVec, BVSubNoOverflow, BVSubNoUnderflow, Not
 
 """
 Overflow checked signed integer subtraction.
diff --git a/test/formal/checked_uint_add.py b/test/formal/checked_uint_add.py
@@ -1,6 +1,7 @@
+from opcodes import GT, SUB
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVUnsignedMax, BVUnsignedUpCast
+from z3 import BitVec, BVAddNoOverflow, Not
 
 """
 Overflow checked unsigned integer addition.
diff --git a/test/formal/checked_uint_mul_16.py b/test/formal/checked_uint_mul_16.py
@@ -1,6 +1,7 @@
+from opcodes import AND, ISZERO, GT, DIV
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVUnsignedUpCast, BVUnsignedMax
+from z3 import BitVec, Not, BVMulNoOverflow
 
 """
 Overflow checked unsigned integer multiplication.
diff --git a/test/formal/checked_uint_sub.py b/test/formal/checked_uint_sub.py
@@ -1,6 +1,7 @@
+from opcodes import LT
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVUnsignedMax, BVUnsignedUpCast
+from z3 import BVSubNoUnderflow, BitVec, Not
 
 """
 Overflow checked unsigned integer subtraction.
diff --git a/test/formal/combine_byte_shl.py b/test/formal/combine_byte_shl.py
@@ -1,5 +1,6 @@
+from opcodes import BYTE, SHL
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, ULE
 
 """
 byte(A, shl(B, X))
diff --git a/test/formal/combine_byte_shr_1.py b/test/formal/combine_byte_shr_1.py
@@ -1,5 +1,6 @@
+from opcodes import BYTE, DIV, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, UGE, ULE, ULT
 
 """
 byte(A, shr(B, X))
diff --git a/test/formal/combine_byte_shr_2.py b/test/formal/combine_byte_shr_2.py
@@ -1,5 +1,6 @@
+from opcodes import BYTE, SHR, DIV
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, ULT
 
 """
 byte(A, shr(B, X))
diff --git a/test/formal/combine_div_shl_one_32.py b/test/formal/combine_div_shl_one_32.py
@@ -1,5 +1,6 @@
+from opcodes import DIV, SHL, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 Rule:
diff --git a/test/formal/combine_mul_shl_one_64.py b/test/formal/combine_mul_shl_one_64.py
@@ -1,5 +1,6 @@
+from opcodes import SHL, MUL
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 Rule:
diff --git a/test/formal/combine_shl_shr_by_constant_64.py b/test/formal/combine_shl_shr_by_constant_64.py
@@ -1,5 +1,6 @@
+from opcodes import AND, SHL, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, If, Int2BV, IntVal, UGT, ULT
 
 """
 Rule:
diff --git a/test/formal/combine_shr_shl_by_constant_64.py b/test/formal/combine_shr_shl_by_constant_64.py
@@ -1,5 +1,6 @@
+from opcodes import AND, SHL, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, If, Int2BV, IntVal, UGT, ULT
 
 """
 Rule:
diff --git a/test/formal/eq_sub.py b/test/formal/eq_sub.py
@@ -1,5 +1,6 @@
+from opcodes import EQ, ISZERO, SUB
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 Rule:
diff --git a/test/formal/exp_neg_one.py b/test/formal/exp_neg_one.py
@@ -1,6 +1,7 @@
+from opcodes import AND, ISZERO, MOD, SUB
 from rule import Rule
-from opcodes import *
-from util import *
+from util import BVUnsignedMax
+from z3 import BitVec, BitVecVal, If
 
 """
 Checking conversion of exp(-1, X) to sub(isZero(and(X, 1)), and(X, 1))
diff --git a/test/formal/exp_to_shl.py b/test/formal/exp_to_shl.py
@@ -1,6 +1,6 @@
+from opcodes import SHL
 from rule import Rule
-from opcodes import *
-from util import *
+from z3 import BitVec, If
 
 """
 Checking conversion of exp(2, X) to shl(X, 1)
diff --git a/test/formal/move_and_across_shl_128.py b/test/formal/move_and_across_shl_128.py
@@ -1,5 +1,6 @@
+from opcodes import AND, SHL
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, ULT
 
 """
 Rule:
diff --git a/test/formal/move_and_across_shr_128.py b/test/formal/move_and_across_shr_128.py
@@ -1,5 +1,6 @@
+from opcodes import AND, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, ULT
 
 """
 Rule:
diff --git a/test/formal/move_and_inside_or.py b/test/formal/move_and_inside_or.py
@@ -1,5 +1,7 @@
+from opcodes import AND, OR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
+
 
 """
 Rule:
diff --git a/test/formal/opcodes.py b/test/formal/opcodes.py
@@ -1,4 +1,4 @@
-from z3 import *
+from z3 import BitVecVal, BV2Int, If, LShR, UDiv, ULT, UGT, URem
 
 def ADD(x, y):
 	return x + y
diff --git a/test/formal/repeated_and.py b/test/formal/repeated_and.py
@@ -1,5 +1,6 @@
+from opcodes import AND
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal
 
 """
 Rule:
diff --git a/test/formal/repeated_or.py b/test/formal/repeated_or.py
@@ -1,5 +1,6 @@
+from opcodes import OR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal
 
 """
 Rule:
diff --git a/test/formal/replace_mul_by_shift.py b/test/formal/replace_mul_by_shift.py
@@ -1,5 +1,6 @@
+from opcodes import DIV, MUL, SHL, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 Rule:
diff --git a/test/formal/rule.py b/test/formal/rule.py
@@ -1,6 +1,6 @@
 import sys
 
-from z3 import *
+from z3 import sat, Solver, unknown, unsat
 
 class Rule:
 	def __init__(self):
diff --git a/test/formal/shl_workaround_8.py b/test/formal/shl_workaround_8.py
@@ -1,5 +1,6 @@
+from opcodes import SHL
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BV2Int, Int2BV, IntVal
 
 """
 Shift left workaround that Solidity implements
diff --git a/test/formal/signextend.py b/test/formal/signextend.py
@@ -1,5 +1,6 @@
+from opcodes import SIGNEXTEND
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, If, UGE, ULT
 
 """
 Rule:
diff --git a/test/formal/signextend_and.py b/test/formal/signextend_and.py
@@ -1,5 +1,6 @@
+from opcodes import SIGNEXTEND, AND
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, ULT
 
 """
 Rule:
diff --git a/test/formal/signextend_equivalence.py b/test/formal/signextend_equivalence.py
@@ -1,5 +1,6 @@
+from opcodes import SIGNEXTEND
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal, Extract, SignExt, UGT
 
 """
 Checking the implementation of SIGNEXTEND using Z3's native SignExt and Extract
diff --git a/test/formal/signextend_shl.py b/test/formal/signextend_shl.py
@@ -1,5 +1,6 @@
+from opcodes import SHL, SIGNEXTEND
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, LShR, ULE
 
 """
 Rule:
diff --git a/test/formal/signextend_shr.py b/test/formal/signextend_shr.py
@@ -1,5 +1,6 @@
+from opcodes import SIGNEXTEND, SAR, SHR
 from rule import Rule
-from opcodes import *
+from z3 import BitVec,  BitVecVal, ULE
 
 """
 Rule:
diff --git a/test/formal/sub_not_zero_x_to_not_x_256.py b/test/formal/sub_not_zero_x_to_not_x_256.py
@@ -1,5 +1,6 @@
+from opcodes import NOT, SUB
 from rule import Rule
-from opcodes import *
+from z3 import BitVec, BitVecVal
 
 """
 Rule:
diff --git a/test/formal/sub_sub.py b/test/formal/sub_sub.py
@@ -1,5 +1,6 @@
+from opcodes import ADD, SUB
 from rule import Rule
-from opcodes import *
+from z3 import BitVec
 
 """
 Rules:
diff --git a/test/formal/util.py b/test/formal/util.py
@@ -1,4 +1,4 @@
-from z3 import *
+from z3 import BitVecVal, Concat, If
 
 def BVUnsignedUpCast(x, n_bits):
 	assert x.size() <= n_bits
