From 24cbc21fa052577c101745954200dcc5ef1bbdd9 Mon Sep 17 00:00:00 2001 From: Kondal Kolipaka Date: Tue, 15 Jul 2025 08:56:59 +0530 Subject: [PATCH 01/10] fix: Add python path for build commands (#1269) --- .../com/espressif/idf/core/build/IDFBuildConfiguration.java | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFBuildConfiguration.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFBuildConfiguration.java index e3e8fd541..45220ff0c 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFBuildConfiguration.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFBuildConfiguration.java @@ -432,7 +432,6 @@ private void runCmakeCommand(IConsole console, IProgressMonitor monitor, IProjec infoStream.write(String.format(Messages.CMakeBuildConfiguration_Configuring, buildDir)); List command = new ArrayList<>(); - command.add("cmake"); //$NON-NLS-1$ command.add("-G"); //$NON-NLS-1$ command.add(generator); @@ -442,6 +441,9 @@ private void runCmakeCommand(IConsole console, IProgressMonitor monitor, IProjec command.add("-DCMAKE_TOOLCHAIN_FILE=" + toolChainFile.getPath().toString()); //$NON-NLS-1$ } + command.add("-DPYTHON_DEPS_CHECKED=1"); //$NON-NLS-1$ + command.add("-DPYTHON=" + IDFUtil.getIDFPythonEnvPath()); //$NON-NLS-1$ + command.add("-DESP_PLATFORM=1"); //$NON-NLS-1$ command.add("-DCMAKE_EXPORT_COMPILE_COMMANDS=ON"); //$NON-NLS-1$ IDFEnvironmentVariables envVariables = new IDFEnvironmentVariables(); From d3c42edf24e9ef6ffac0f7115f20a132744df529 Mon Sep 17 00:00:00 2001 From: Denys Almazov Date: Tue, 15 Jul 2025 06:33:10 +0300 Subject: [PATCH 02/10] IEP-1565 ESP32P4: Debugging failure (#1252) * fix: handling esp32p4 svd NPE by adding svd files * fix: avoid URISyntaxException exception --- .../.classpath | 2 +- .../gdbjtag/openocd/SvdPathResolver.java | 14 +- .../svd/esp32.svd | 16669 +- .../svd/esp32c2.svd | 1992 +- .../svd/esp32c3.svd | 4109 +- .../svd/esp32c6-lp.svd | 6367 + .../svd/esp32c6.svd | 3105 +- .../svd/esp32h2.svd | 9641 +- .../svd/esp32p4.svd | 133701 +++++++++++++++ .../svd/esp32s2-ulp.svd | 2681 + .../svd/esp32s2.svd | 11282 +- .../svd/esp32s3-ulp.svd | 4665 + .../svd/esp32s3.svd | 36187 ++-- 13 files changed, 198801 insertions(+), 31614 deletions(-) create mode 100644 bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6-lp.svd create mode 100644 bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32p4.svd create mode 100644 bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2-ulp.svd create mode 100644 bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3-ulp.svd diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/.classpath b/bundles/com.espressif.idf.debug.gdbjtag.openocd/.classpath index 514730d50..f48d93796 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/.classpath +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/.classpath @@ -1,5 +1,6 @@ + @@ -12,7 +13,6 @@ - diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/SvdPathResolver.java b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/SvdPathResolver.java index bec415a02..b91088534 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/SvdPathResolver.java +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/SvdPathResolver.java @@ -61,11 +61,19 @@ public String resolveValue(IDynamicVariable variable, String argument) throws Co private String resolveSvdPath(String target) throws Exception { URL svdUrl = Platform.getBundle(Activator.PLUGIN_ID).getResource("svd/".concat(target.concat(".svd"))); //$NON-NLS-1$ //$NON-NLS-2$ - String jarPath = new File(TabSvdTarget.class.getProtectionDomain().getCodeSource().getLocation().toURI()) - .getPath(); + String jarPath = new File(TabSvdTarget.class.getProtectionDomain().getCodeSource().getLocation().getPath()) + .getAbsolutePath(); + String selectedTargetPath; + + if (svdUrl == null) + { + Logger.log("svd file is missing"); //$NON-NLS-1$ + return StringUtil.EMPTY; + } + if (!jarPath.contains(".jar")) //$NON-NLS-1$ - selectedTargetPath = new File(FileLocator.resolve(svdUrl).toURI()).getPath(); + selectedTargetPath = new File(FileLocator.resolve(svdUrl).getPath()).getAbsolutePath(); else selectedTargetPath = resolveSvdPathFromJar(svdUrl, jarPath); return selectedTargetPath; diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32.svd index 39c4cfdf0..9f243ee77 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32 - ESP32 - 7 + ESP32 Series + 16 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. Xtensa LX6 r0p0 little false true - 3 + 0 false 32 @@ -91,7 +89,7 @@ 8 0x4 - KEY_%s + KEY[%s] 0x10 0x20 @@ -107,7 +105,7 @@ 4 0x4 - TEXT_%s + TEXT[%s] 0x30 0x20 @@ -138,7 +136,7 @@ APB_CTRL - Advanced Peripheral Bus Controller + APB (Advanced Peripheral Bus) Controller APB_CTRL 0x3FF66000 @@ -392,7 +390,10 @@ - APB_SARADC_SAR1_PATT_TAB1 + 4 + 0x4 + 1-4 + APB_SARADC_SAR1_PATT_TAB%s 0x1C 0x20 0x0F0F0F0F @@ -407,52 +408,10 @@ - APB_SARADC_SAR1_PATT_TAB2 - 0x20 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR1_PATT_TAB2 - Item 4 ~ 7 for pattern table 1 (each item one byte) - 0 - 32 - read-write - - - - - APB_SARADC_SAR1_PATT_TAB3 - 0x24 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR1_PATT_TAB3 - Item 8 ~ 11 for pattern table 1 (each item one byte) - 0 - 32 - read-write - - - - - APB_SARADC_SAR1_PATT_TAB4 - 0x28 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR1_PATT_TAB4 - Item 12 ~ 15 for pattern table 1 (each item one byte) - 0 - 32 - read-write - - - - - APB_SARADC_SAR2_PATT_TAB1 + 4 + 0x4 + 1-4 + APB_SARADC_SAR2_PATT_TAB%s 0x2C 0x20 0x0F0F0F0F @@ -466,51 +425,6 @@ - - APB_SARADC_SAR2_PATT_TAB2 - 0x30 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR2_PATT_TAB2 - Item 4 ~ 7 for pattern table 2 (each item one byte) - 0 - 32 - read-write - - - - - APB_SARADC_SAR2_PATT_TAB3 - 0x34 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR2_PATT_TAB3 - Item 8 ~ 11 for pattern table 2 (each item one byte) - 0 - 32 - read-write - - - - - APB_SARADC_SAR2_PATT_TAB4 - 0x38 - 0x20 - 0x0F0F0F0F - - - SARADC_SAR2_PATT_TAB4 - Item 12 ~ 15 for pattern table 2 (each item one byte) - 0 - 32 - read-write - - - APLL_TICK_CONF 0x3C @@ -543,7 +457,7 @@ BB - Peripheral BB + BB Peripheral BB 0x3FF5D000 @@ -588,7 +502,7 @@ DPORT - Peripheral DPORT + DPORT Peripheral DPORT 0x3FF00000 @@ -596,6 +510,86 @@ 0x5C0 registers + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_BB + 2 + + + BT_MAC + 3 + + + BT_BB + 4 + + + BT_BB_NMI + 5 + + + RWBT + 6 + + + RWBLE + 7 + + + RWBT_NMI + 8 + + + RWBLE_NMI + 9 + + + FROM_CPU_INTR0 + 24 + + + FROM_CPU_INTR1 + 25 + + + FROM_CPU_INTR2 + 26 + + + FROM_CPU_INTR3 + 27 + + + SDIO_HOST + 37 + + + ETH_MAC + 38 + + + WDT + 55 + + + MMU_IA + 66 + + + MPU_IA + 67 + + + CACHE_IA + 68 + PRO_BOOT_REMAP_CTRL @@ -1759,168 +1753,170 @@ PERIP_CLK_EN 0xC0 0x20 + 0xF9C1E06F + + TIMERS_CLK_EN + 0 + 1 + read-write + SPI01_CLK_EN - SPI0 and SPI1 module. 1 1 read-write UART_CLK_EN - UART0 module. 2 1 read-write + + WDG_CLK_EN + 3 + 1 + read-write + I2S0_CLK_EN - I2S0 module. 4 1 read-write UART1_CLK_EN - UART1 module. 5 1 read-write SPI2_CLK_EN - SPI2 module. 6 1 read-write I2C0_EXT0_CLK_EN - I2C0 module. 7 1 read-write UHCI0_CLK_EN - UDMA0 module. 8 1 read-write RMT_CLK_EN - RMT module. 9 1 read-write PCNT_CLK_EN - PCNT module. 10 1 read-write LEDC_CLK_EN - LEDC module. 11 1 read-write UHCI1_CLK_EN - UDMA1 module. 12 1 read-write TIMERGROUP_CLK_EN - TIMG0 module. 13 1 read-write EFUSE_CLK_EN - eFuse module. 14 1 read-write TIMERGROUP1_CLK_EN - TIMG1 module. 15 1 read-write SPI3_CLK_EN - SPI3 module. 16 1 read-write PWM0_CLK_EN - PWM0 module. 17 1 read-write I2C_EXT1_CLK_EN - I2C1 module. 18 1 read-write TWAI_CLK_EN - TWAI module. 19 1 read-write PWM1_CLK_EN - PWM1 module. 20 1 read-write I2S1_CLK_EN - I2S1 module. 21 1 read-write SPI_DMA_CLK_EN - SPI_DMA module. 22 1 read-write UART2_CLK_EN - UART2 module. 23 1 read-write UART_MEM_CLK_EN - Shared memory of UART0 ~ 2. 24 1 read-write + + PWM2_CLK_EN + 25 + 1 + read-write + + + PWM3_CLK_EN + 26 + 1 + read-write + @@ -1928,167 +1924,168 @@ 0xC4 0x20 + + TIMERS_RST + 0 + 1 + read-write + SPI01_RST - SPI0 and SPI1 module. 1 1 read-write UART_RST - UART0 module. 2 1 read-write + + WDG_RST + 3 + 1 + read-write + I2S0_RST - I2S0 module. 4 1 read-write UART1_RST - UART1 module. 5 1 read-write SPI2_RST - SPI2 module. 6 1 read-write I2C0_EXT0_RST - I2C0 module. 7 1 read-write UHCI0_RST - UDMA0 module. 8 1 read-write RMT_RST - RMT module. 9 1 read-write PCNT_RST - PCNT module. 10 1 read-write LEDC_RST - LEDC module. 11 1 read-write UHCI1_RST - UDMA1 module. 12 1 read-write TIMERGROUP_RST - TIMG0 module. 13 1 read-write EFUSE_RST - eFuse module. 14 1 read-write TIMERGROUP1_RST - TIMG1 module. 15 1 read-write SPI3_RST - SPI3 module. 16 1 read-write PWM0_RST - PWM0 module. 17 1 read-write I2C_EXT1_RST - I2C1 module. 18 1 read-write TWAI_RST - TWAI module. 19 1 read-write PWM1_RST - PWM1 module. 20 1 read-write I2S1_RST - I2S1 module. 21 1 read-write SPI_DMA_RST - SPI_DMA module. 22 1 read-write UART2_RST - UART2 module. 23 1 read-write UART_MEM_RST - Shared memory of UART0 ~ 2. 24 1 read-write + + PWM2_RST + 25 + 1 + read-write + + + PWM3_RST + 26 + 1 + read-write + @@ -5535,6 +5532,18 @@ 3 read-write + + RECORD_PDEBUGINST_LOOP_REP + 20 + 1 + read-write + + + RECORD_PDEBUGINST_LOOP + 21 + 1 + read-write + RECORD_PDEBUGINST_CINTL 24 @@ -5579,6 +5588,12 @@ 32 read-only + + RECORD_PDEBUGDATA_DEP_OTHER + 0 + 1 + read-write + RECORD_PDEBUGDATA_EXCVEC 0 @@ -5591,18 +5606,174 @@ 8 read-write + + RECORD_PDEBUGDATA_INSNTYPE_RER + 0 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BUFF + 1 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_WER + 1 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BUFFCONFL + 2 + 1 + read-write + RECORD_PDEBUGDATA_INSNTYPE_ER 2 12 read-write + + RECORD_PDEBUGDATA_STALL_DCM + 3 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_LSU + 4 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ICM + 6 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_IRAMBUSY + 7 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_LSU + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_IPIF + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_RSR + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_TIE + 9 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_WSR + 9 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_RUN + 10 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_XSR + 10 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_STR + 11 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP + 12 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BPIFETCH + 12 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_L32R + 13 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_LSPROC + 14 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BPLOAD + 15 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_MEMW + 16 + 1 + read-write + RECORD_PDEBUGDATA_EXCCAUSE 16 6 read-write + + RECORD_PDEBUGDATA_STALL_BANKCONFL + 16 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_HALT + 17 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ITERMUL + 18 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ITERDIV + 19 + 1 + read-write + @@ -5641,6 +5812,42 @@ 4 read-write + + RECORD_PDEBUGLS0STAT_DTLBM + 8 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_DCM + 9 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_DCH + 10 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_UC + 12 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_WB + 13 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_COH + 16 + 1 + read-write + RECORD_PDEBUGLS0STAT_STCOH 17 @@ -6801,84 +7008,84 @@ CACHE_IA_INT_APP_DROM0 - APP CPU invalid access to DROM0 when cache is disabled + APP CPU invalid access to DROM0 when cache is disabled 0 1 read-write CACHE_IA_INT_APP_IRAM0 - APP CPU invalid access to IRAM0 when cache is disabled + APP CPU invalid access to IRAM0 when cache is disabled 1 1 read-write CACHE_IA_INT_APP_IRAM1 - APP CPU invalid access to IRAM1 when cache is disabled + APP CPU invalid access to IRAM1 when cache is disabled 2 1 read-write CACHE_IA_INT_APP_IROM0 - APP CPU invalid access to IROM0 when cache is disabled + APP CPU invalid access to IROM0 when cache is disabled 3 1 read-write CACHE_IA_INT_APP_DRAM1 - APP CPU invalid access to DRAM1 when cache is disabled + APP CPU invalid access to DRAM1 when cache is disabled 4 1 read-write CACHE_IA_INT_APP_OPPOSITE - APP CPU invalid access to APP CPU cache when cache disabled + APP CPU invalid access to APP CPU cache when cache disabled 5 1 read-write CACHE_IA_INT_PRO_DROM0 - PRO CPU invalid access to DROM0 when cache is disabled + PRO CPU invalid access to DROM0 when cache is disabled 14 1 read-write CACHE_IA_INT_PRO_IRAM0 - PRO CPU invalid access to IRAM0 when cache is disabled + PRO CPU invalid access to IRAM0 when cache is disabled 15 1 read-write CACHE_IA_INT_PRO_IRAM1 - PRO CPU invalid access to IRAM1 when cache is disabled + PRO CPU invalid access to IRAM1 when cache is disabled 16 1 read-write CACHE_IA_INT_PRO_IROM0 - PRO CPU invalid access to IROM0 when cache is disabled + PRO CPU invalid access to IROM0 when cache is disabled 17 1 read-write CACHE_IA_INT_PRO_DRAM1 - PRO CPU invalid access to DRAM1 when cache is disabled + PRO CPU invalid access to DRAM1 when cache is disabled 18 1 read-write CACHE_IA_INT_PRO_OPPOSITE - PRO CPU invalid access to APP CPU cache when cache disabled + PRO CPU invalid access to APP CPU cache when cache disabled 19 1 read-write @@ -7013,25 +7220,34 @@ RD_EFUSE_WR_DIS - read for efuse_wr_disable 0 16 read-only RD_EFUSE_RD_DIS - read for efuse_rd_disable 16 4 read-only RD_FLASH_CRYPT_CNT - read for flash_crypt_cnt 20 7 read-only + + RD_UART_DOWNLOAD_DIS + 27 + 1 + read-only + + + RESERVED_0_28 + 28 + 4 + read-only + @@ -7040,8 +7256,7 @@ 0x20 - RD_WIFI_MAC_CRC_LOW - read for low 32bit WIFI_MAC_Address + RD_MAC 0 32 read-only @@ -7054,12 +7269,23 @@ 0x20 - RD_WIFI_MAC_CRC_HIGH - read for high 24bit WIFI_MAC_Address + RD_MAC_1 0 - 24 + 16 + read-only + + + RD_MAC_CRC + 16 + 8 read-only + + RD_RESERVE_0_88 + 24 + 8 + read-write + @@ -7068,72 +7294,71 @@ 0x20 - RD_CHIP_VER_DIS_APP_CPU + RD_DISABLE_APP_CPU 0 1 read-only - RD_CHIP_VER_DIS_BT + RD_DISABLE_BT 1 1 read-only - RD_CHIP_VER_PKG_4BIT - most significant bit of chip package + RD_CHIP_PACKAGE_4BIT 2 1 read-only - RD_CHIP_VER_DIS_CACHE + RD_DIS_CACHE 3 1 read-only RD_SPI_PAD_CONFIG_HD - read for SPI_pad_config_hd 4 5 read-only - RD_CHIP_VER_PKG - least significant bits of chip package + RD_CHIP_PACKAGE 9 3 read-write RD_CHIP_CPU_FREQ_LOW - If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise 12 1 read-write RD_CHIP_CPU_FREQ_RATED - If set, the ESP32's maximum CPU frequency has been rated 13 1 read-write RD_BLK3_PART_RESERVE - If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 14 1 read-write RD_CHIP_VER_REV1 - bit is set to 1 for rev1 silicon 15 1 read-write + + RD_RESERVE_0_112 + 16 + 16 + read-write + @@ -7142,57 +7367,47 @@ 0x20 - RD_CK8M_FREQ + RD_CLK8M_FREQ 0 8 read-only RD_ADC_VREF - True ADC reference voltage 8 5 read-write - RD_SDIO_DREFH - 8 - 2 - read-only - - - RD_SDIO_DREFM - 10 - 2 - read-only - - - RD_SDIO_DREFL - 12 - 2 - read-only + RD_RESERVE_0_141 + 13 + 1 + read-write RD_XPD_SDIO - read for XPD_SDIO_REG 14 1 read-only - RD_SDIO_TIEH - read for SDIO_TIEH + RD_XPD_SDIO_TIEH 15 1 read-only - RD_SDIO_FORCE - read for sdio_force + RD_XPD_SDIO_FORCE 16 1 read-only + + RD_RESERVE_0_145 + 17 + 15 + read-write + @@ -7202,28 +7417,24 @@ RD_SPI_PAD_CONFIG_CLK - read for SPI_pad_config_clk 0 5 read-only RD_SPI_PAD_CONFIG_Q - read for SPI_pad_config_q 5 5 read-only RD_SPI_PAD_CONFIG_D - read for SPI_pad_config_d 10 5 read-only RD_SPI_PAD_CONFIG_CS0 - read for SPI_pad_config_cs0 15 5 read-only @@ -7234,22 +7445,32 @@ 1 read-only + + RD_RESERVE_0_181 + 21 + 1 + read-write + RD_VOL_LEVEL_HP_INV - This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 22 2 read-only - RD_DIG_VOL_L6 + RD_WAFER_VERSION_MINOR 24 - 4 + 2 read-only + + RD_RESERVE_0_186 + 26 + 2 + read-write + RD_FLASH_CRYPT_CONFIG - read for flash_crypt_config 28 4 read-only @@ -7263,14 +7484,12 @@ RD_CODING_SCHEME - read for coding_scheme 0 2 read-only RD_CONSOLE_DEBUG_DISABLE - read for console_debug_disable 2 1 read-only @@ -7283,53 +7502,52 @@ RD_ABS_DONE_0 - read for abstract_done_0 4 1 read-only RD_ABS_DONE_1 - read for abstract_done_1 5 1 read-only - RD_DISABLE_JTAG - read for JTAG_disable + RD_JTAG_DISABLE 6 1 read-only RD_DISABLE_DL_ENCRYPT - read for download_dis_encrypt 7 1 read-only RD_DISABLE_DL_DECRYPT - read for download_dis_decrypt 8 1 read-only RD_DISABLE_DL_CACHE - read for download_dis_cache 9 1 read-only RD_KEY_STATUS - read for key_status 10 1 read-only + + RD_RESERVE_0_203 + 11 + 21 + read-write + @@ -7339,21 +7557,18 @@ WR_DIS - program for efuse_wr_disable 0 16 read-write RD_DIS - program for efuse_rd_disable 16 4 read-write FLASH_CRYPT_CNT - program for flash_crypt_cnt 20 7 read-write @@ -7367,7 +7582,6 @@ WIFI_MAC_CRC_LOW - program for low 32bit WIFI_MAC_Address 0 32 read-write @@ -7381,7 +7595,6 @@ WIFI_MAC_CRC_HIGH - program for high 24bit WIFI_MAC_Address 0 24 read-write @@ -7394,61 +7607,55 @@ 0x20 - CHIP_VER_DIS_APP_CPU + DISABLE_APP_CPU 0 1 - read-write + read-only - CHIP_VER_DIS_BT + DISABLE_BT 1 1 - read-write + read-only - CHIP_VER_PKG_4BIT - most significant bit of chip package + CHIP_PACKAGE_4BIT 2 1 read-only - CHIP_VER_DIS_CACHE + DIS_CACHE 3 1 - read-write + read-only SPI_PAD_CONFIG_HD - program for SPI_pad_config_hd 4 5 - read-write + read-only - CHIP_VER_PKG - least significant bits of chip package + CHIP_PACKAGE 9 3 read-write CHIP_CPU_FREQ_LOW - If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise 12 1 read-write CHIP_CPU_FREQ_RATED - If set, the ESP32's maximum CPU frequency has been rated 13 1 read-write BLK3_PART_RESERVE - If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 14 1 read-write @@ -7459,6 +7666,12 @@ 1 read-write + + RESERVE_0_112 + 16 + 16 + read-write + @@ -7467,55 +7680,45 @@ 0x20 - CK8M_FREQ + CLK8M_FREQ 0 8 - read-write + read-only ADC_VREF - True ADC reference voltage 8 5 read-write - SDIO_DREFH - 8 - 2 - read-write - - - SDIO_DREFM - 10 - 2 - read-write - - - SDIO_DREFL - 12 - 2 + RESERVE_0_141 + 13 + 1 read-write XPD_SDIO - program for XPD_SDIO_REG 14 1 - read-write + read-only - SDIO_TIEH - program for SDIO_TIEH + XPD_SDIO_TIEH 15 1 - read-write + read-only - SDIO_FORCE - program for sdio_force + XPD_SDIO_FORCE 16 1 + read-only + + + RESERVE_0_145 + 17 + 15 read-write @@ -7527,57 +7730,63 @@ SPI_PAD_CONFIG_CLK - program for SPI_pad_config_clk 0 5 - read-write + read-only SPI_PAD_CONFIG_Q - program for SPI_pad_config_q 5 5 - read-write + read-only SPI_PAD_CONFIG_D - program for SPI_pad_config_d 10 5 - read-write + read-only SPI_PAD_CONFIG_CS0 - program for SPI_pad_config_cs0 15 5 - read-write + read-only - INST_CONFIG + CHIP_VER_REV2 20 - 8 + 1 + read-only + + + RESERVE_0_181 + 21 + 1 read-write VOL_LEVEL_HP_INV - This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W) 22 2 - read-write + read-only - DIG_VOL_L6 + WAFER_VERSION_MINOR 24 - 4 + 2 + read-only + + + RESERVE_0_186 + 26 + 2 read-write FLASH_CRYPT_CONFIG - program for flash_crypt_config 28 4 - read-write + read-only @@ -7588,14 +7797,12 @@ CODING_SCHEME - program for coding_scheme 0 2 read-write CONSOLE_DEBUG_DISABLE - program for console_debug_disable 2 1 read-write @@ -7608,49 +7815,42 @@ ABS_DONE_0 - program for abstract_done_0 4 1 read-write ABS_DONE_1 - program for abstract_done_1 5 1 read-write DISABLE_JTAG - program for JTAG_disable 6 1 read-write DISABLE_DL_ENCRYPT - program for download_dis_encrypt 7 1 read-write DISABLE_DL_DECRYPT - program for download_dis_decrypt 8 1 read-write DISABLE_DL_CACHE - program for download_dis_cache 9 1 read-write KEY_STATUS - program for key_status 10 1 read-write @@ -7663,8 +7863,7 @@ 0x20 - BLK1_DOUT0 - read for BLOCK1 + RD_BLOCK1 0 32 read-only @@ -7677,8 +7876,7 @@ 0x20 - BLK1_DOUT1 - read for BLOCK1 + RD_BLOCK1_1 0 32 read-only @@ -7691,8 +7889,7 @@ 0x20 - BLK1_DOUT2 - read for BLOCK1 + RD_BLOCK1_2 0 32 read-only @@ -7705,8 +7902,7 @@ 0x20 - BLK1_DOUT3 - read for BLOCK1 + RD_BLOCK1_3 0 32 read-only @@ -7719,8 +7915,7 @@ 0x20 - BLK1_DOUT4 - read for BLOCK1 + RD_BLOCK1_4 0 32 read-only @@ -7733,8 +7928,7 @@ 0x20 - BLK1_DOUT5 - read for BLOCK1 + RD_BLOCK1_5 0 32 read-only @@ -7747,8 +7941,7 @@ 0x20 - BLK1_DOUT6 - read for BLOCK1 + RD_BLOCK1_6 0 32 read-only @@ -7761,8 +7954,7 @@ 0x20 - BLK1_DOUT7 - read for BLOCK1 + RD_BLOCK1_7 0 32 read-only @@ -7775,8 +7967,7 @@ 0x20 - BLK2_DOUT0 - read for BLOCK2 + RD_BLOCK2 0 32 read-only @@ -7789,8 +7980,7 @@ 0x20 - BLK2_DOUT1 - read for BLOCK2 + RD_BLOCK2_1 0 32 read-only @@ -7803,8 +7993,7 @@ 0x20 - BLK2_DOUT2 - read for BLOCK2 + RD_BLOCK2_2 0 32 read-only @@ -7817,8 +8006,7 @@ 0x20 - BLK2_DOUT3 - read for BLOCK2 + RD_BLOCK2_3 0 32 read-only @@ -7831,8 +8019,7 @@ 0x20 - BLK2_DOUT4 - read for BLOCK2 + RD_BLOCK2_4 0 32 read-only @@ -7845,8 +8032,7 @@ 0x20 - BLK2_DOUT5 - read for BLOCK2 + RD_BLOCK2_5 0 32 read-only @@ -7859,8 +8045,7 @@ 0x20 - BLK2_DOUT6 - read for BLOCK2 + RD_BLOCK2_6 0 32 read-only @@ -7873,8 +8058,7 @@ 0x20 - BLK2_DOUT7 - read for BLOCK2 + RD_BLOCK2_7 0 32 read-only @@ -7887,10 +8071,15 @@ 0x20 - BLK3_DOUT0 - read for BLOCK3 + RD_CUSTOM_MAC_CRC 0 - 32 + 8 + read-only + + + RD_CUSTOM_MAC + 8 + 24 read-only @@ -7901,10 +8090,15 @@ 0x20 - BLK3_DOUT1 - read for BLOCK3 + RD_CUSTOM_MAC_1 0 - 32 + 24 + read-only + + + RESERVED_3_56 + 24 + 8 read-only @@ -7915,8 +8109,7 @@ 0x20 - BLK3_DOUT2 - read for BLOCK3 + RD_BLK3_RESERVED_2 0 32 read-only @@ -7928,37 +8121,26 @@ 0x84 0x20 - - BLK3_DOUT3 - read for BLOCK3 - 0 - 32 - read-only - RD_ADC1_TP_LOW - ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 0 7 read-write RD_ADC1_TP_HIGH - ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 7 9 read-write RD_ADC2_TP_LOW - ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 16 7 read-write RD_ADC2_TP_HIGH - ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 23 9 read-write @@ -7971,19 +8153,11 @@ 0x20 - BLK3_DOUT4 - read for BLOCK3 + RD_SECURE_VERSION 0 32 read-only - - RD_CAL_RESERVED - Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE - 0 - 16 - read-write - @@ -7992,10 +8166,15 @@ 0x20 - BLK3_DOUT5 - read for BLOCK3 + RESERVED_3_160 0 - 32 + 24 + read-only + + + RD_MAC_VERSION + 24 + 8 read-only @@ -8006,8 +8185,7 @@ 0x20 - BLK3_DOUT6 - read for BLOCK3 + RD_BLK3_RESERVED_6 0 32 read-only @@ -8020,8 +8198,7 @@ 0x20 - BLK3_DOUT7 - read for BLOCK3 + RD_BLK3_RESERVED_7 0 32 read-only @@ -8035,7 +8212,6 @@ BLK1_DIN0 - program for BLOCK1 0 32 read-write @@ -8049,7 +8225,6 @@ BLK1_DIN1 - program for BLOCK1 0 32 read-write @@ -8063,7 +8238,6 @@ BLK1_DIN2 - program for BLOCK1 0 32 read-write @@ -8077,7 +8251,6 @@ BLK1_DIN3 - program for BLOCK1 0 32 read-write @@ -8091,7 +8264,6 @@ BLK1_DIN4 - program for BLOCK1 0 32 read-write @@ -8105,7 +8277,6 @@ BLK1_DIN5 - program for BLOCK1 0 32 read-write @@ -8119,7 +8290,6 @@ BLK1_DIN6 - program for BLOCK1 0 32 read-write @@ -8133,7 +8303,6 @@ BLK1_DIN7 - program for BLOCK1 0 32 read-write @@ -8147,7 +8316,6 @@ BLK2_DIN0 - program for BLOCK2 0 32 read-write @@ -8161,7 +8329,6 @@ BLK2_DIN1 - program for BLOCK2 0 32 read-write @@ -8175,7 +8342,6 @@ BLK2_DIN2 - program for BLOCK2 0 32 read-write @@ -8189,7 +8355,6 @@ BLK2_DIN3 - program for BLOCK2 0 32 read-write @@ -8203,7 +8368,6 @@ BLK2_DIN4 - program for BLOCK2 0 32 read-write @@ -8217,7 +8381,6 @@ BLK2_DIN5 - program for BLOCK2 0 32 read-write @@ -8231,7 +8394,6 @@ BLK2_DIN6 - program for BLOCK2 0 32 read-write @@ -8245,7 +8407,6 @@ BLK2_DIN7 - program for BLOCK2 0 32 read-write @@ -8259,7 +8420,6 @@ BLK3_DIN0 - program for BLOCK3 0 32 read-write @@ -8273,7 +8433,6 @@ BLK3_DIN1 - program for BLOCK3 0 32 read-write @@ -8287,7 +8446,6 @@ BLK3_DIN2 - program for BLOCK3 0 32 read-write @@ -8299,37 +8457,26 @@ 0xE4 0x20 - - BLK3_DIN3 - program for BLOCK3 - 0 - 32 - read-write - ADC1_TP_LOW - ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 0 7 read-write ADC1_TP_HIGH - ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 7 9 read-write ADC2_TP_LOW - ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 16 7 read-write ADC2_TP_HIGH - ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 23 9 read-write @@ -8342,18 +8489,10 @@ 0x20 - BLK3_DIN4 - program for BLOCK3 + SECURE_VERSION 0 32 - read-write - - - CAL_RESERVED - Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE - 0 - 16 - read-write + read-only @@ -8364,7 +8503,6 @@ BLK3_DIN5 - program for BLOCK3 0 32 read-write @@ -8378,7 +8516,6 @@ BLK3_DIN6 - program for BLOCK3 0 32 read-write @@ -8392,7 +8529,6 @@ BLK3_DIN7 - program for BLOCK3 0 32 read-write @@ -8407,14 +8543,12 @@ SEL0 - efuse timing configure 0 8 read-write SEL1 - efuse timing configure 8 8 read-write @@ -8435,7 +8569,6 @@ OP_CODE - efuse operation code 0 16 read-write @@ -8468,14 +8601,12 @@ READ_CMD - command for read 0 1 read-write PGM_CMD - command for program 1 1 read-write @@ -8489,14 +8620,12 @@ READ_DONE_INT_RAW - read done interrupt raw status 0 1 read-only PGM_DONE_INT_RAW - program done interrupt raw status 1 1 read-only @@ -8510,14 +8639,12 @@ READ_DONE_INT_ST - read done interrupt status 0 1 read-only PGM_DONE_INT_ST - program done interrupt status 1 1 read-only @@ -8531,14 +8658,12 @@ READ_DONE_INT_ENA - read done interrupt enable 0 1 read-write PGM_DONE_INT_ENA - program done interrupt enable 1 1 read-write @@ -8552,14 +8677,12 @@ READ_DONE_INT_CLR - read done interrupt clear 0 1 write-only PGM_DONE_INT_CLR - program done interrupt clear 1 1 write-only @@ -8574,7 +8697,6 @@ DAC_CLK_DIV - efuse timing configure 0 8 read-write @@ -8594,7 +8716,6 @@ DEC_WARNINGS - the decode result of 3/4 coding scheme has warning 0 12 read-only @@ -8618,1328 +8739,1120 @@ - FLASH_ENCRYPTION - Flash Encryption Peripheral - FLASH_ENCRYPTION - 0x3FF46000 + EMAC_DMA + Ethernet DMA configuration and control registers + EMAC_DMA + 0x3FF69000 0x0 - 0x2C + 0x38 registers - 8 - 0x4 - BUFFER_%s + DMABUSMODE + Bus mode configuration 0x0 0x20 - BUFFER - Data buffers for encryption. + SW_RST + When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit. 0 - 8 - write-only + 1 + read-write - - - - START - 0x20 - 0x20 - - FLASH_START - Set this bit to start encryption operation on data buffer. - 0 - 8 - write-only + DMA_ARB_SCH + This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx). + 1 + 1 + read-write - - - - ADDRESS - 0x24 - 0x20 - - ADDRESS - The physical address on the off-chip flash must be 8-word boundary aligned. - 0 - 8 - write-only + DESC_SKIP_LEN + This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write - - - - DONE - 0x28 - 0x20 - - FLASH_DONE - Set this bit when encryption operation is complete. - 0 + ALT_DESC_SIZE + When set the size of the alternate descriptor increases to 32 bytes. + 7 1 - read-only + read-write - - - - - - FRC_TIMER - Peripheral FRC_TIMER - FRC - 0x3FF47000 - - 0x0 - 0x14 - registers - - - - TIMER_LOAD - 0x0 - 0x20 - - VALUE - 0 - 8 + PROG_BURST_LEN + These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN). + 8 + 6 read-write - - - - TIMER_COUNT - 0x4 - 0x20 - - TIMER_COUNT - 0 - 8 + PRI_RATIO + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1 + 14 + 2 read-write - - - - TIMER_CTRL - 0x8 - 0x20 - - TIMER_PRESCALER - 1 - 8 + FIXED_BURST + This bit controls whether the AHB master interface performs fixed burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations. + 16 + 1 read-write - - - - TIMER_INT - 0xC - 0x20 - - CLR - 0 + RX_DMA_PBL + This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high. + 17 + 6 + read-write + + + USE_SEP_PBL + When set high this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits[13:8] is applicable for both DMA engines. + 23 1 read-write - - - - TIMER_ALARM - 0x10 - 0x20 - - TIMER_ALARM - 0 - 8 + PBLX8_MODE + When set high this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value. + 24 + 1 read-write - - - - - - GPIO - General Purpose Input/Output - GPIO - 0x3FF44000 - - 0x0 - 0x5CC - registers - - - GPIO - 22 - - - GPIO_NMI - 23 - - - - BT_SELECT - 0x0 - 0x20 - - BT_SEL - NA - 0 - 32 + DMAADDRALIBEA + When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + DMAMIXEDBURST + When this bit is set high and the FIXED_BURST bit is low the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 read-write - OUT + DMATXPOLLDEMAND + When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes. 0x4 0x20 - - - DATA - GPIO0~31 output value - 0 - 32 - read-write - - + read-only - OUT_W1TS + DMARXPOLLDEMAND + When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state. 0x8 0x20 - - - OUT_DATA_W1TS - GPIO0~31 output value write 1 to set - 0 - 32 - read-write - - + read-only - OUT_W1TC + DMARXBASEADDR + This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only. 0xC 0x20 - - - OUT_DATA_W1TC - GPIO0~31 output value write 1 to clear - 0 - 32 - read-write - - - OUT1 + DMATXBASEADDR + This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only. 0x10 0x20 - - - DATA - GPIO32~39 output value - 0 - 8 - read-write - - - OUT1_W1TS + DMASTATUS + State of interrupts, errors and other events 0x14 0x20 - OUT1_DATA_W1TS - GPIO32~39 output value write 1 to set + TRANS_INT + This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor. 0 - 8 + 1 read-write - - - - OUT1_W1TC - 0x18 - 0x20 - - OUT1_DATA_W1TC - GPIO32~39 output value write 1 to clear - 0 - 8 + TRANS_PROC_STOP + This bit is set when the transmission is stopped. + 1 + 1 read-write - - - - SDIO_SELECT - 0x1C - 0x20 - - SDIO_SEL - SDIO PADS on/off control from outside - 0 - 8 + TRANS_BUF_UNAVAIL + This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command. + 2 + 1 read-write - - - - ENABLE - 0x20 - 0x20 - - DATA - GPIO0~31 output enable - 0 - 32 + TRANS_JABBER_TO + This bit indicates that the Transmit Jabber Timer expired which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 read-write - - - - ENABLE_W1TS - 0x24 - 0x20 - - ENABLE_DATA_W1TS - GPIO0~31 output enable write 1 to set - 0 - 32 + RECV_OVFLOW + This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0[11]. + 4 + 1 read-write - - - - ENABLE_W1TC - 0x28 - 0x20 - - ENABLE_DATA_W1TC - GPIO0~31 output enable write 1 to clear - 0 - 32 + TRANS_UNDFLOW + This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 read-write - - - - ENABLE1 - 0x2C - 0x20 - - DATA - GPIO32~39 output enable - 0 - 8 + RECV_INT + This bit indicates that the frame reception is complete. When reception is complete the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 read-write - - - - ENABLE1_W1TS - 0x30 - 0x20 - - ENABLE1_DATA_W1TS - GPIO32~39 output enable write 1 to set - 0 - 8 + RECV_BUF_UNAVAIL + This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 read-write - - - - ENABLE1_W1TC - 0x34 - 0x20 - - ENABLE1_DATA_W1TC - GPIO32~39 output enable write 1 to clear - 0 - 8 + RECV_PROC_STOP + This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 read-write - - - - STRAP - 0x38 - 0x20 - - STRAPPING - {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} - 0 - 16 - read-only + RECV_WDT_TO + When set this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write - - - - IN - 0x3C - 0x20 - - DATA_NEXT - GPIO0~31 input value - 0 - 32 + EARLY_TRANS_INT + This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 read-write - - - - IN1 - 0x40 - 0x20 - - DATA_NEXT - GPIO32~39 input value - 0 - 8 + FATAL_BUS_ERR_INT + This bit indicates that a bus error occurred as described in Bits [25:23]. When this bit is set the corresponding DMA engine disables all of its bus accesses. + 13 + 1 read-write - - - - STATUS - 0x44 - 0x20 - - INT - GPIO0~31 interrupt status - 0 - 32 + EARLY_RECV_INT + This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier). + 14 + 1 read-write - - - - STATUS_W1TS - 0x48 - 0x20 - - STATUS_INT_W1TS - GPIO0~31 interrupt status write 1 to set - 0 - 32 + ABN_INT_SUMM + Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive FIFO Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared. + 15 + 1 read-write - - - - STATUS_W1TC - 0x4C - 0x20 - - STATUS_INT_W1TC - GPIO0~31 interrupt status write 1 to clear - 0 - 32 + NORM_INT_SUMM + Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. + 16 + 1 read-write - - - - STATUS1 - 0x50 - 0x20 - - INT - GPIO32~39 interrupt status - 0 - 8 + RECV_PROC_STATE + This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory. + 17 + 3 read-write - - - - STATUS1_W1TS - 0x54 - 0x20 - - STATUS1_INT_W1TS - GPIO32~39 interrupt status write 1 to set - 0 - 8 + TRANS_PROC_STATE + This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory. + 20 + 3 read-write - - - - STATUS1_W1TC - 0x58 - 0x20 - - STATUS1_INT_W1TC - GPIO32~39 interrupt status write 1 to clear - 0 - 8 + ERROR_BITS + This field indicates the type of error that caused a Bus Error for example error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access. + 23 + 3 read-write - - - - ACPU_INT - 0x60 - 0x20 - - APPCPU_INT - GPIO0~31 APP CPU interrupt status - 0 - 32 - read-only + PMT_INT + This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. + 28 + 1 + read-write - - - - ACPU_NMI_INT - 0x64 - 0x20 - - APPCPU_NMI_INT - GPIO0~31 APP CPU non-maskable interrupt status - 0 - 32 - read-only + TS_TRI_INT + This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. + 29 + 1 + read-write - PCPU_INT - 0x68 + DMAOPERATION_MODE + Receive and Transmit operating modes and command + 0x18 0x20 - PROCPU_INT - GPIO0~31 PRO CPU interrupt status - 0 - 32 - read-only + START_STOP_RX + When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame. + 1 + 1 + read-write - - - - PCPU_NMI_INT - 0x6C - 0x20 - - PROCPU_NMI_INT - GPIO0~31 PRO CPU non-maskable interrupt status - 0 - 32 - read-only + OPT_SECOND_FRAME + When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write - - - - CPUSDIO_INT - 0x70 - 0x20 - - SDIO_INT - SDIO's extent GPIO0~31 interrupt - 0 - 32 - read-only + RX_THRESH_CTRL + These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 . + 3 + 2 + read-write - - - - ACPU_INT1 - 0x74 - 0x20 - - APPCPU_INT_H - GPIO32~39 APP CPU interrupt status - 0 - 8 - read-only + DROP_GFRM + When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit. + 5 + 1 + read-write - - - - ACPU_NMI_INT1 - 0x78 - 0x20 - - APPCPU_NMI_INT_H - GPIO32~39 APP CPU non-maskable interrupt status - 0 - 8 - read-only + FWD_UNDER_GF + When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC. + 6 + 1 + read-write - - - - PCPU_INT1 - 0x7C - 0x20 - - PROCPU_INT_H - GPIO32~39 PRO CPU interrupt status - 0 - 8 - read-only + FWD_ERR_FRAME + When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow). + 7 + 1 + read-write - - - - PCPU_NMI_INT1 - 0x80 - 0x20 - - PROCPU_NMI_INT_H - GPIO32~39 PRO CPU non-maskable interrupt status - 0 - 8 - read-only + START_STOP_TRANSMISSION_COMMAND + When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame. + 13 + 1 + read-write - - - - CPUSDIO_INT1 - 0x84 - 0x20 - - SDIO_INT_H - SDIO's extent GPIO32~39 interrupt - 0 - 8 - read-only + TX_THRESH_CTRL + These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 . + 14 + 3 + read-write - PIN_PAD_DRIVER - 2 + FLUSH_TX_FIFO + When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. + 20 1 read-write - PIN_INT_TYPE - 7 - 3 + TX_STR_FWD + When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored. + 21 + 1 read-write - PIN_WAKEUP_ENABLE - 10 + DIS_FLUSH_RECV_FRAMES + When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers. + 24 1 read-write - PIN_CONFIG - 11 - 2 + RX_STORE_FORWARD + When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it. + 25 + 1 read-write - PIN_INT_ENA - 13 - 5 + DIS_DROP_TCPIP_ERR_FRAM + When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset. + 26 + 1 read-write - 40 - 0x4 - PIN%s - 0x88 + DMAIN_EN + 0x1C 0x20 - PIN_PAD_DRIVER - if set to : normal output if set to 1: open drain + DMAIN_TIE + When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + DMAIN_TSE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + DMAIN_TBUE + When this bit is set with Normal Interrupt Summary Enable (Bit 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled. 2 1 read-write - PIN_INT_TYPE - if set to : GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger - 7 - 3 + DMAIN_TJTE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 read-write - PIN_WAKEUP_ENABLE - GPIO wake up enable only available in light sleep - 10 + DMAIN_OIE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled. + 4 1 read-write - PIN_CONFIG - NA - 11 - 2 + DMAIN_UIE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled. + 5 + 1 read-write - PIN_INT_ENA - bit: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable - 13 - 5 + DMAIN_RIE + When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. + 6 + 1 read-write - - - - cali_conf - 0x128 - 0x20 - - CALI_RTC_MAX - 0 - 10 + DMAIN_RBUE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 read-write - CALI_START - 31 + DMAIN_RSE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled. + 8 1 read-write - - - - cali_data - 0x12C - 0x20 - - CALI_VALUE_SYNC2 - 0 - 20 - read-only + DMAIN_RWTE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write - CALI_RDY_REAL - 30 + DMAIN_ETIE + When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled. + 10 1 - read-only + read-write - CALI_RDY_SYNC2 - 31 + DMAIN_FBEE + When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled. + 13 1 - read-only + read-write - - - - 256 - 0x4 - FUNC%s_IN_SEL_CFG - 0x130 - 0x20 - - IN_SEL - select one of the 256 inputs - 0 - 6 + DMAIN_ERIE + When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled. + 14 + 1 read-write - IN_INV_SEL - revert the value of the input if you want to revert please set the value to 1 - 6 + DMAIN_AISE + When this bit is set abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. + 15 1 read-write - SEL - if the slow signal bypass the io matrix or not if you want setting the value to 1 - 7 + DMAIN_NISE + When this bit is set normal interrupt summary is enabled. When this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. + 16 1 read-write - 40 - 0x4 - FUNC%s_OUT_SEL_CFG - 0x530 + DMAMISSEDFR + Missed Frame and Buffer Overflow Counter Register + 0x20 0x20 - OUT_SEL - select one of the 256 output to 4 GPIO + MISSED_FC + This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. 0 - 9 + 16 read-write - INV_SEL - invert the output value if you want to revert the output value setting the value to 1 - 9 + OVERFLOW_BMFC + This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 1 read-write - OEN_SEL - weather using the logical oen signal or not using the value setting by the register - 10 - 1 + OVERFLOW_FC + This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read. + 17 + 11 read-write - OEN_INV_SEL - invert the output enable value if you want to revert the output enable value setting the value to 1 - 11 + OVERFLOW_BFOC + This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 1 read-write + + DMARINTWDTIMER + Watchdog timer count on receive + 0x24 + 0x20 + + + RIWTC + This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMATXCURRDESC + The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + 0x48 + 0x20 + read-only + + + DMARXCURRDESC + The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + 0x4C + 0x20 + read-only + + + DMATXCURRADDR_BUF + The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + 0x50 + 0x20 + read-only + + + DMARXCURRADDR_BUF + The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + 0x54 + 0x20 + read-only + - GPIO_SD - Sigma-Delta Modulation - GPIO_SIGMADELTA - 0x3FF44F00 + EMAC_EXT + Ethernet Clock, PHY type, and SRAM configuration registers + EMAC_EXT + 0x3FF69800 0x0 - 0x2C + 0x18 registers - SIGMADELTA0 + EX_CLKOUT_CONF + RMII clock divider setting 0x0 0x20 - 0x0000FF00 - GPIO_SD0_IN + DIV_NUM 0 - 8 + 4 + read-write + + + H_DIV_NUM + 4 + 4 read-write - GPIO_SD0_PRESCALE + DLY_NUM 8 - 8 + 2 read-write - SIGMADELTA1 + EX_OSCCLK_CONF + RMII clock half and whole divider settings 0x4 0x20 - 0x0000FF00 - GPIO_SD1_IN + DIV_NUM_10M 0 - 8 + 6 read-write - GPIO_SD1_PRESCALE - 8 - 8 + H_DIV_NUM_10M + 6 + 6 read-write - - - - SIGMADELTA2 - 0x8 - 0x20 - 0x0000FF00 - - GPIO_SD2_IN - 0 - 8 + DIV_NUM_100M + 12 + 6 read-write - GPIO_SD2_PRESCALE - 8 - 8 + H_DIV_NUM_100M + 18 + 6 + read-write + + + CLK_SEL + 24 + 1 read-write - SIGMADELTA3 - 0xC + EX_CLK_CTRL + Clock enable and external/internal clock selection + 0x8 0x20 - 0x0000FF00 - GPIO_SD3_IN + EXT_EN 0 - 8 + 1 read-write - GPIO_SD3_PRESCALE - 8 - 8 + INT_EN + 1 + 1 read-write - - - - SIGMADELTA4 - 0x10 - 0x20 - 0x0000FF00 - - GPIO_SD4_IN - 0 - 8 + RX_125_CLK_EN + 2 + 1 read-write - GPIO_SD4_PRESCALE - 8 - 8 + MII_CLK_TX_EN + 3 + 1 read-write - - - - SIGMADELTA5 - 0x14 - 0x20 - 0x0000FF00 - - GPIO_SD5_IN - 0 - 8 + MII_CLK_RX_EN + 4 + 1 read-write - GPIO_SD5_PRESCALE - 8 - 8 + CLK_EN + 5 + 1 read-write - SIGMADELTA6 - 0x18 + EX_PHYINF_CONF + Selection of MII/RMII phy + 0xC 0x20 - 0x0000FF00 - GPIO_SD6_IN + INT_REVMII_RX_CLK_SEL 0 - 8 + 1 read-write - GPIO_SD6_PRESCALE - 8 - 8 + EXT_REVMII_RX_CLK_SEL + 1 + 1 read-write - - - - SIGMADELTA7 - 0x1C - 0x20 - 0x0000FF00 - - GPIO_SD7_IN - 0 - 8 + SBD_FLOWCTRL + 2 + 1 + read-write + + + CORE_PHY_ADDR + 3 + 5 read-write - GPIO_SD7_PRESCALE + REVMII_PHY_ADDR 8 - 8 + 5 read-write - - - - SIGMADELTA_CG - 0x20 - 0x20 - - GPIO_SD_CLK_EN - 31 + PHY_INTF_SEL + 13 + 3 + read-write + + + SS_MODE + 16 1 read-write - - - - SIGMADELTA_MISC - 0x24 - 0x20 - - GPIO_SPI_SWAP - 31 + SBD_CLK_GATING_EN + 17 + 1 + read-write + + + PMT_CTRL_EN + 18 + 1 + read-write + + + SCR_SMI_DLY_RX_SYNC + 19 + 1 + read-write + + + TX_ERR_OUT_EN + 20 1 read-write - SIGMADELTA_VERSION - 0x28 + PD_SEL + Ethernet RAM power-down enable + 0x10 0x20 - 0x01506190 - GPIO_SD_DATE + RAM_PD_EN 0 - 28 + 2 read-write + + EX_DATE + 0xFC + 0x20 + - HINF - Peripheral HINF - HINF - 0x3FF4B000 + EMAC_MAC + Ethernet MAC configuration and control registers + EMAC_MAC + 0x3FF6A000 0x0 - 0x34 + 0x78 registers - CFG_DATA0 + EMACCONFIG + MAC configuration 0x0 0x20 - 0x22226666 - USER_ID_FN1 + PLTF + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble. 0 - 16 + 2 read-write - DEVICE_ID_FN1 - 16 - 16 + RX + When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII. + 2 + 1 read-write - - - - CFG_DATA1 - 0x4 - 0x20 - 0x01110011 - - SDIO_ENABLE - 0 + TX + When this bit is set the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames. + 3 1 read-write - SDIO_IOREADY1 - 1 + DEFERRALCHECK + Deferral Check. + 4 1 read-write - HIGHSPEED_ENABLE - 2 + BACKOFFLIMIT + The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000. + 5 + 2 + read-write + + + PADCRCSTRIP + When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host. + 7 1 read-write - HIGHSPEED_MODE - 3 + RETRY + When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode. + 9 1 - read-only + read-write - SDIO_CD_ENABLE - 4 + RXIPCOFFLOAD + When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled. + 10 1 read-write - SDIO_IOREADY2 - 5 + DUPLEX + When this bit is set the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode. + 11 1 read-write - SDIO_INT_MASK - 6 + LOOPBACK + When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally. + 12 1 read-write - IOENABLE2 - 7 + RXOWN + When this bit is set the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode. + 13 1 - read-only + read-write - CD_DISABLE - 8 + FESPEED + This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps. + 14 1 - read-only + read-write - FUNC1_EPS - 9 + MII + This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1. + 15 1 - read-only + read-write - EMP - 10 + DISABLECRS + When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 1 - read-only + read-write - IOENABLE1 - 11 + INTERFRAMEGAP + These bits control the minimum IFG between frames during transmission. 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. + 17 + 3 + read-write + + + JUMBOFRAME + When this bit is set the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 1 - read-only + read-write - SDIO20_CONF0 - 12 - 4 + JABBER + When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission. + 22 + 1 read-write - SDIO_VER - 16 - 12 + WATCHDOG + When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes. + 23 + 1 read-write - FUNC2_EPS - 28 + ASS2KP + When set the MAC considers all frames with up to 2 000 bytes length as normal packets.When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no effect on Giant Frame status. + 27 1 - read-only + read-write - SDIO20_CONF1 - 29 + SAIRC + This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit[30] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit[30] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames. + 28 3 read-write - CFG_DATA7 - 0x1C + EMACFF + Frame filter settings + 0x4 0x20 - 0x00020000 - PIN_STATE + PMODE + When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set. 0 - 8 + 1 read-write - CHIP_STATE + DAIF + When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed. + 3 + 1 + read-write + + + PAM + When set this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. + 4 + 1 + read-write + + + DBF + When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames. + 5 + 1 + read-write + + + PCF + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. + 6 + 2 + read-write + + + SAIF + When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter. 8 - 8 + 1 read-write - SDIO_RST - 16 + SAFE + When this bit is set the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 1 read-write - SDIO_IOREADY0 - 17 + RECEIVE_ALL + When this bit is set the MAC Receiver module passes all received frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter. + 31 1 read-write - CIS_CONF0 - 0x20 + EMACGMIIADDR + PHY configuration access + 0x10 0x20 - 0xFFFFFFFF - CIS_CONF_W0 + MIIBUSY + This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present. 0 - 32 + 1 read-write - - - - CIS_CONF1 - 0x24 - 0x20 - 0xFFFFFFFF - - CIS_CONF_W1 - 0 - 32 + MIIWRITE + When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register. + 1 + 1 read-write - - - - CIS_CONF2 - 0x28 - 0x20 - 0xFFFFFFFF - - CIS_CONF_W2 - 0 - 32 + MIICSRCLK + CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0011: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26. + 2 + 4 read-write - - - - CIS_CONF3 - 0x2C - 0x20 - 0xFFFFFFFF - - CIS_CONF_W3 - 0 - 32 + MIIREG + These bits select the desired MII register in the selected PHY device. + 6 + 5 read-write - - - - CIS_CONF4 - 0x30 - 0x20 - 0xFFFFFFFF - - CIS_CONF_W4 - 0 - 32 + MIIDEV + This field indicates which of the 32 possible PHY devices are being accessed. + 11 + 5 read-write - CIS_CONF5 - 0x34 + EMACMIIDATA + PHY data read write + 0x14 0x20 - 0xFFFFFFFF - CIS_CONF_W5 + MII_DATA + This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 0 - 32 + 16 read-write - CIS_CONF6 - 0x38 + EMACFC + Frame flow control + 0x18 0x20 - 0xFFFFFFFF - CIS_CONF_W6 + FCBBA + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled. 0 - 32 + 1 read-write - - - - CIS_CONF7 - 0x3C - 0x20 - 0xFFFFFFFF - - CIS_CONF_W7 - 0 - 32 + TFCE + In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled. + 1 + 1 read-write - - - - CFG_DATA16 - 0x40 - 0x20 - 0x33336666 - - USER_ID_FN2 - 0 - 16 + RFCE + When this bit is set the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled. + 2 + 1 read-write - DEVICE_ID_FN2 + UPFD + A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + PLT + This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface. + 4 + 2 + read-write + + + DZPQ + When this bit is set it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PAUSE_TIME + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. 16 16 read-write @@ -9947,912 +9860,974 @@ - DATE - 0xFC + EMACDEBUG + Status debugging bits + 0x24 0x20 - 0x15030200 + read-only - SDIO_DATE + MACRPES + When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state. 0 - 32 + 1 read-write - - - - - - I2C0 - I2C (Inter-Integrated Circuit) Controller - I2C - 0x3FF53000 - - 0x0 - 0x9C - registers - - - I2C_EXT0 - 49 - - - - SCL_LOW_PERIOD - 0x0 - 0x20 - - SCL_LOW_PERIOD - This register is used to configure the low level width of SCL clock. - 0 - 14 + MACRFFCS + When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller. + 1 + 2 + read-write + + + MTLRFWCAS + When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + 4 + 1 + read-write + + + MTLRFRCS + This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status. + 5 + 2 + read-write + + + MTLRFFLS + This field gives the status of the fill-level of the Rx FIFO: 2'b00: Rx FIFO Empty. 2'b01: Rx FIFO fill-level below flow-control deactivate threshold. 2'b10: Rx FIFO fill-level above flow-control activate threshold. 2'b11: Rx FIFO Full. + 8 + 2 + read-write + + + MACTPES + When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + 16 + 1 + read-write + + + MACTFCS + This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring input frame for transmission. + 17 + 2 + read-write + + + MACTP + When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission. + 19 + 1 + read-write + + + MTLTFRCS + This field indicates the state of the Tx FIFO Read Controller: 2'b00: IDLE state. 2'b01: READ state (transferring data to the MAC transmitter). 2'b10: Waiting for TxStatus from the MAC transmitter. 2'b11: Writing the received TxStatus or flushing the Tx FIFO. + 20 + 2 + read-write + + + MTLTFWCS + When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. + 22 + 1 + read-write + + + MTLTFNES + When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission. + 24 + 1 + read-write + + + MTLTSFFS + When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission. + 25 + 1 read-write - CTR - 0x4 + PMT_RWUFFR + The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets + 0x28 0x20 - 0x00000003 + read-only + + + PMT_CSR + PMT Control and Status + 0x2C + 0x20 + read-only - SDA_FORCE_OUT - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal) + PWRDWN + When set the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high. 0 1 read-write - SCL_FORCE_OUT - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal) + MGKPKTEN + When set enables generation of a power management event because of magic packet reception. 1 1 read-write - SAMPLE_SCL_LEVEL - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. + RWKPKTEN + When set enables generation of a power management event because of remote wake-up frame reception 2 1 read-write - MS_MODE - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. - 4 + MGKPRCVD + When set this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 1 read-write - TRANS_START - Set this bit to start sending data in txfifo. - 5 + RWKPRCVD + When set this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 1 read-write - TX_LSB_FIRST - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit - 6 + GLBLUCAST + When set enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame. + 9 1 read-write - RX_LSB_FIRST - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit - 7 - 1 + RWKPTR + The maximum value of the pointer is 7 the detail information please refer to PMT_RWUFFR. + 24 + 5 read-write - CLK_EN - This is the clock gating control bit for reading or writing registers. - 8 + RWKFILTRST + When this bit is set it resets the RWKPTR register to 3’b000. + 31 1 read-write - SR - 0x8 + EMACLPI_CRS + LPI Control and Status + 0x30 0x20 + read-only - ACK_REC - This register stores the value of ACK bit. + TLPIEN + When set this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. 0 1 - read-only + read-write - SLAVE_RW - when in slave mode 1: master read slave 0: master write slave. + TLPIEX + When set this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register. 1 1 - read-only + read-write - TIME_OUT - when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. + RLPIEN + When set this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. 2 1 - read-only + read-write - ARB_LOST - when I2C lost control of SDA line this register changes to high level. + RLPIEX + When set this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register. 3 1 - read-only + read-write - BUS_BUSY - 1:I2C bus is busy transferring data. 0:I2C bus is in idle state. - 4 + TLPIST + When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface. + 8 1 - read-only + read-write - SLAVE_ADDRESSED - when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level. - 5 + RLPIST + When set this bit indicates that the MAC is receiving the LPI pattern on the MII interface. + 9 1 - read-only + read-write - BYTE_TRANS - This register changes to high level when one byte is transferred. - 6 + LPIEN + When set this bit instructs the MAC Transmitter to enter the LPI state. When reset this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 1 - read-only + read-write - RXFIFO_CNT - This register represent the amount of data need to send. - 8 - 6 - read-only + PLS + This bit indicates the link status of the PHY.When set the link is considered to be okay (up) and when reset the link is considered to be down. + 17 + 1 + read-write - TXFIFO_CNT - This register stores the amount of received data in ram. - 18 - 6 - read-only - - - SCL_MAIN_STATE_LAST - This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK - 24 - 3 - read-only - - - SCL_STATE_LAST - This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP - 28 - 3 - read-only + LPITXA + This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write - TO - 0xC + EMACLPITIMERSCONTROL + LPI Timers Control + 0x34 0x20 + read-only - TIME_OUT - This register is used to configure the max clock number of receiving a data. + LPI_TW_TIMER + This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. 0 - 20 + 16 + read-write + + + LPI_LS_TIMER + This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 read-write - SLAVE_ADDR - 0x10 + EMACINTS + Interrupt status + 0x38 0x20 + read-only - SLAVE_ADDR - when configured as i2c slave this register is used to configure slave's address. - 0 - 15 + PMTINTS + This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration. + 3 + 1 read-write - ADDR_10BIT_EN - This register is used to enable slave 10bit address mode. - 31 + LPIIS + When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register). + 10 1 read-write - RXFIFO_ST - 0x14 + EMACINTMASK + Interrupt mask + 0x3C 0x20 - RXFIFO_START_ADDR - This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. - 0 - 5 - read-only - - - RXFIFO_END_ADDR - This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. - 5 - 5 - read-only + PMTINTMASK + When set this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register). + 3 + 1 + read-write - TXFIFO_START_ADDR - This is the offset address of the first sending data as described in nonfifo_tx_thres register. + LPIINTMASK + When set this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register). 10 - 5 - read-only - - - TXFIFO_END_ADDR - This is the offset address of the last sending data as described in nonfifo_tx_thres register. - 15 - 5 - read-only + 1 + read-write - FIFO_CONF - 0x18 + EMACADDR0HIGH + Upper 16 bits of the first 6-byte MAC address + 0x40 0x20 - 0x0155408B - RXFIFO_FULL_THRHD + ADDRESS0_HI + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. 0 - 5 - read-write - - - TXFIFO_EMPTY_THRHD - Config txfifo empty threhd value when using apb fifo access - 5 - 5 + 16 read-write - NONFIFO_EN - Set this bit to enble apb nonfifo access. - 10 + ADDRESS_ENABLE0 + This bit is always set to 1. + 31 1 read-write + + + + EMACADDR0LOW + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0x44 + 0x20 + + + EMACADDR1HIGH + Upper 16 bits of the second 6-byte MAC address + 0x48 + 0x20 + - FIFO_ADDR_CFG_EN - When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. - 11 - 1 + MAC_ADDRESS1_HI + This field contains the upper 16 bits Bits[47:32] of the second 6-byte MAC Address. + 0 + 16 read-write - RX_FIFO_RST - Set this bit to reset rx fifo when using apb fifo access. - 12 - 1 + MASK_BYTE_CONTROL + These bits are mask control bits for comparison of each of the EMACADDR1 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR1 High [15:8]. Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 read-write - TX_FIFO_RST - Set this bit to reset tx fifo when using apb fifo access. - 13 + SOURCE_ADDRESS + When this bit is set the EMACADDR1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR1[47:0] is used to compare with the DA fields of the received frame. + 30 1 read-write - NONFIFO_RX_THRES - when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. - 14 - 6 - read-write - - - NONFIFO_TX_THRES - when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. - 20 - 6 + ADDRESS_ENABLE1 + When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 + 1 read-write - DATA - 0x1C + EMACADDR1LOW + This field contains the lower 32 bits of the second 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + 0x4C 0x20 - - - FIFO_RDATA - The register represent the byte data read from rxfifo when use apb fifo access - 0 - 8 - read-only - - - INT_RAW - 0x20 + EMACADDR2HIGH + Upper 16 bits of the third 6-byte MAC address + 0x50 0x20 - RXFIFO_FULL_INT_RAW - The raw interrupt status bit for rxfifo full when use apb fifo access. + MAC_ADDRESS2_HI + This field contains the upper 16 bits Bits[47:32] of the third 6-byte MAC address. 0 - 1 - read-only - - - TXFIFO_EMPTY_INT_RAW - The raw interrupt status bit for txfifo empty when use apb fifo access. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_RAW - The raw interrupt status bit for receiving data overflow when use apb fifo access. - 2 - 1 - read-only - - - END_DETECT_INT_RAW - The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. - 3 - 1 - read-only - - - SLAVE_TRAN_COMP_INT_RAW - The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_RAW - The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. - 5 - 1 - read-only - - - MASTER_TRAN_COMP_INT_RAW - The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_RAW - The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_RAW - The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_RAW - The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. - 9 - 1 - read-only + 16 + read-write - ACK_ERR_INT_RAW - The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. - 10 - 1 - read-only + MASK_BYTE_CONTROL2 + These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR2 High [15:8]. Bit[28]: EMACADDR2 High [7:0]. Bit[27]: EMACADDR2 Low [31:24]. Bit[24]: EMACADDR2 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write - RX_REC_FULL_INT_RAW - The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. - 11 + SOURCE_ADDRESS2 + When this bit is set the EMACADDR2[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR2[47:0] is used to compare with the DA fields of the received frame. + 30 1 - read-only + read-write - TX_SEND_EMPTY_INT_RAW - The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. - 12 + ADDRESS_ENABLE2 + When this bit is set the address filter module uses the third MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 - read-only + read-write - INT_CLR - 0x24 + EMACADDR2LOW + This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + 0x54 + 0x20 + + + EMACADDR3HIGH + Upper 16 bits of the fourth 6-byte MAC address + 0x58 0x20 - RXFIFO_FULL_INT_CLR - Set this bit to clear the rxfifo_full_int interrupt. + MAC_ADDRESS3_HI + This field contains the upper 16 bits Bits[47:32] of the fourth 6-byte MAC address. 0 - 1 - write-only - - - TXFIFO_EMPTY_INT_CLR - Set this bit to clear the txfifo_empty_int interrupt. - 1 - 1 - write-only + 16 + read-write - RXFIFO_OVF_INT_CLR - Set this bit to clear the rxfifo_ovf_int interrupt. - 2 - 1 - write-only + MASK_BYTE_CONTROL3 + These bits are mask control bits for comparison of each of the EMACADDR3 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR3 High [15:8]. Bit[28]: EMACADDR3 High [7:0]. Bit[27]: EMACADDR3 Low [31:24]. Bit[24]: EMACADDR3 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write - END_DETECT_INT_CLR - Set this bit to clear the end_detect_int interrupt. - 3 + SOURCE_ADDRESS3 + When this bit is set the EMACADDR3[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame. + 30 1 - write-only + read-write - SLAVE_TRAN_COMP_INT_CLR - Set this bit to clear the slave_tran_comp_int interrupt. - 4 + ADDRESS_ENABLE3 + When this bit is set the address filter module uses the fourth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 - write-only + read-write + + + + EMACADDR3LOW + This field contains the lower 32 bits of the fourth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + 0x5C + 0x20 + + + EMACADDR4HIGH + Upper 16 bits of the fifth 6-byte MAC address + 0x60 + 0x20 + - ARBITRATION_LOST_INT_CLR - Set this bit to clear the arbitration_lost_int interrupt. - 5 - 1 - write-only + MAC_ADDRESS4_HI + This field contains the upper 16 bits Bits[47:32] of the fifth 6-byte MAC address. + 0 + 16 + read-write - MASTER_TRAN_COMP_INT_CLR - Set this bit to clear the master_tran_comp interrupt. - 6 - 1 - write-only + MASK_BYTE_CONTROL4 + These bits are mask control bits for comparison of each of the EMACADDR4 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write - TRANS_COMPLETE_INT_CLR - Set this bit to clear the trans_complete_int interrupt. - 7 + SOURCE_ADDRESS4 + When this bit is set the EMACADDR4[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR4[47:0] is used to compare with the DA fields of the received frame. + 30 1 - write-only + read-write - TIME_OUT_INT_CLR - Set this bit to clear the time_out_int interrupt. - 8 + ADDRESS_ENABLE4 + When this bit is set the address filter module uses the fifth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 - write-only + read-write + + + + EMACADDR4LOW + This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + 0x64 + 0x20 + + + EMACADDR5HIGH + Upper 16 bits of the sixth 6-byte MAC address + 0x68 + 0x20 + - TRANS_START_INT_CLR - Set this bit to clear the trans_start_int interrupt. - 9 - 1 - write-only + MAC_ADDRESS5_HI + This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address. + 0 + 16 + read-write - ACK_ERR_INT_CLR - Set this bit to clear the ack_err_int interrupt. - 10 - 1 - write-only + MASK_BYTE_CONTROL5 + These bits are mask control bits for comparison of each of the EMACADDR5 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR5 High [15:8]. Bit[28]: EMACADDR5 High [7:0]. Bit[27]: EMACADDR5 Low [31:24]. Bit[24]: EMACADDR5 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write - RX_REC_FULL_INT_CLR - Set this bit to clear the rx_rec_full_int interrupt. - 11 + SOURCE_ADDRESS5 + When this bit is set the EMACADDR5[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame. + 30 1 - write-only + read-write - TX_SEND_EMPTY_INT_CLR - Set this bit to clear the tx_send_empty_int interrupt. - 12 + ADDRESS_ENABLE5 + When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 - write-only + read-write - INT_ENA - 0x28 + EMACADDR5LOW + This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + 0x6C + 0x20 + + + EMACADDR6HIGH + Upper 16 bits of the seventh 6-byte MAC address + 0x70 0x20 - RXFIFO_FULL_INT_ENA - The enable bit for rxfifo_full_int interrupt. + MAC_ADDRESS6_HI + This field contains the upper 16 bits Bits[47:32] of the seventh 6-byte MAC Address. 0 - 1 + 16 read-write - TXFIFO_EMPTY_INT_ENA - The enable bit for txfifo_empty_int interrupt. - 1 - 1 + MASK_BYTE_CONTROL6 + These bits are mask control bits for comparison of each of the EMACADDR6 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 read-write - RXFIFO_OVF_INT_ENA - The enable bit for rxfifo_ovf_int interrupt. - 2 + SOURCE_ADDRESS6 + When this bit is set the EMACADDR6[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR6[47:0] is used to compare with the DA fields of the received frame. + 30 1 read-write - END_DETECT_INT_ENA - The enable bit for end_detect_int interrupt. - 3 + ADDRESS_ENABLE6 + When this bit is set the address filter module uses the seventh MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 read-write + + + + EMACADDR6LOW + This field contains the lower 32 bits of the seventh 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + 0x74 + 0x20 + + + EMACADDR7HIGH + Upper 16 bits of the eighth 6-byte MAC address + 0x78 + 0x20 + - SLAVE_TRAN_COMP_INT_ENA - The enable bit for slave_tran_comp_int interrupt. - 4 - 1 + MAC_ADDRESS7_HI + This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address. + 0 + 16 read-write - ARBITRATION_LOST_INT_ENA - The enable bit for arbitration_lost_int interrupt. - 5 - 1 + MASK_BYTE_CONTROL7 + These bits are mask control bits for comparison of each of the EMACADDR7 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR7 High [15:8]. Bit[28]: EMACADDR7 High [7:0]. Bit[27]: EMACADDR7 Low [31:24]. Bit[24]: EMACADDR7 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 read-write - MASTER_TRAN_COMP_INT_ENA - The enable bit for master_tran_comp_int interrupt. - 6 + SOURCE_ADDRESS7 + When this bit is set the EMACADDR7[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR7[47:0] is used to compare with the DA fields of the received frame. + 30 1 read-write - TRANS_COMPLETE_INT_ENA - The enable bit for trans_complete_int interrupt. - 7 + ADDRESS_ENABLE7 + When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + 31 1 read-write + + + + EMACADDR7LOW + This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + 0x7C + 0x20 + + + EMACCSTATUS + Link communication status + 0xD8 + 0x20 + read-only + - TIME_OUT_INT_ENA - The enable bit for time_out_int interrupt. - 8 + LINK_MODE + This bit indicates the current mode of operation of the link: 1'b0: Half-duplex mode. 1'b1: Full-duplex mode. + 0 1 read-write - TRANS_START_INT_ENA - The enable bit for trans_start_int interrupt. - 9 - 1 + LINK_SPEED + This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz. + 1 + 2 read-write - ACK_ERR_INT_ENA - The enable bit for ack_err_int interrupt. - 10 + JABBER_TIMEOUT + This bit indicates whether there is jabber timeout error (1'b1) in the received Frame. + 4 1 read-write + + + + EMACWDOGTO + Watchdog timeout control + 0xDC + 0x20 + - RX_REC_FULL_INT_ENA - The enable bit for rx_rec_full_int interrupt. - 11 - 1 + WDOGTO + When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame. + 0 + 14 read-write - TX_SEND_EMPTY_INT_ENA - The enable bit for tx_send_empty_int interrupt. - 12 + PWDOGEN + When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG. + 16 1 read-write + + + + FLASH_ENCRYPTION + FLASH_ENCRYPTION Peripheral + FLASH_ENCRYPTION + 0x3FF46000 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + BUFFER_%s + 0x0 + 0x20 + + + BUFFER + Data buffers for encryption. + 0 + 8 + write-only + + + - INT_STATUS - 0x2C + START + 0x20 0x20 - RXFIFO_FULL_INT_ST - The masked interrupt status for rxfifo_full_int interrupt. + FLASH_START + Set this bit to start encryption operation on data buffer. 0 - 1 - read-only + 8 + write-only + + + + ADDRESS + 0x24 + 0x20 + - TXFIFO_EMPTY_INT_ST - The masked interrupt status for txfifo_empty_int interrupt. - 1 - 1 - read-only + ADDRESS + The physical address on the off-chip flash must be 8-word boundary aligned. + 0 + 8 + write-only + + + + DONE + 0x28 + 0x20 + - RXFIFO_OVF_INT_ST - The masked interrupt status for rxfifo_ovf_int interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_ST - The masked interrupt status for end_detect_int interrupt. - 3 - 1 - read-only - - - SLAVE_TRAN_COMP_INT_ST - The masked interrupt status for slave_tran_comp_int interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_ST - The masked interrupt status for arbitration_lost_int interrupt. - 5 - 1 - read-only - - - MASTER_TRAN_COMP_INT_ST - The masked interrupt status for master_tran_comp_int interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_ST - The masked interrupt status for trans_complete_int interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_ST - The masked interrupt status for time_out_int interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_ST - The masked interrupt status for trans_start_int interrupt. - 9 - 1 - read-only - - - ACK_ERR_INT_ST - The masked interrupt status for ack_err_int interrupt. - 10 - 1 - read-only - - - RX_REC_FULL_INT_ST - The masked interrupt status for rx_rec_full_int interrupt. - 11 - 1 - read-only - - - TX_SEND_EMPTY_INT_ST - The masked interrupt status for tx_send_empty_int interrupt. - 12 + FLASH_DONE + Set this bit when encryption operation is complete. + 0 1 read-only + + + + FRC_TIMER + FRC_TIMER Peripheral + FRC + 0x3FF47000 + + 0x0 + 0x14 + registers + + - SDA_HOLD - 0x30 + TIMER_LOAD + 0x0 0x20 - TIME - This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. + VALUE 0 - 10 + 8 read-write - SDA_SAMPLE - 0x34 + TIMER_COUNT + 0x4 0x20 - TIME - This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL + TIMER_COUNT 0 - 10 + 8 read-write - SCL_HIGH_PERIOD - 0x38 + TIMER_CTRL + 0x8 0x20 - SCL_HIGH_PERIOD - This register is used to configure the clock num during SCL is low level. - 0 - 14 + TIMER_PRESCALER + 1 + 8 read-write - SCL_START_HOLD - 0x40 + TIMER_INT + 0xC 0x20 - 0x00000008 - TIME - This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. + CLR 0 - 10 + 1 read-write - SCL_RSTART_SETUP - 0x44 + TIMER_ALARM + 0x10 0x20 - 0x00000008 - TIME - This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. + TIMER_ALARM 0 - 10 + 8 read-write + + + + GPIO + General Purpose Input/Output + GPIO + 0x3FF44000 + + 0x0 + 0x5CC + registers + + + GPIO + 22 + + + GPIO_NMI + 23 + + - SCL_STOP_HOLD - 0x48 + BT_SELECT + 0x0 0x20 - TIME - This register is used to configure the clock num after the STOP bit's posedge. + BT_SEL + NA 0 - 14 + 32 read-write - SCL_STOP_SETUP - 0x4C + OUT + 0x4 0x20 - TIME - This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. + DATA + GPIO0~31 output value 0 - 10 + 32 read-write - SCL_FILTER_CFG - 0x50 + OUT_W1TS + 0x8 0x20 - 0x00000008 - SCL_FILTER_THRES - When input SCL's pulse width is smaller than this register value I2C ignores this pulse. + OUT_DATA_W1TS + GPIO0~31 output value write 1 to set 0 - 3 + 32 read-write + + + + OUT_W1TC + 0xC + 0x20 + - SCL_FILTER_EN - This is the filter enable bit for SCL. - 3 - 1 + OUT_DATA_W1TC + GPIO0~31 output value write 1 to clear + 0 + 32 read-write - SDA_FILTER_CFG - 0x54 + OUT1 + 0x10 0x20 - 0x00000008 - SDA_FILTER_THRES - When input SCL's pulse width is smaller than this register value I2C ignores this pulse. + DATA + GPIO32~39 output value 0 - 3 + 8 read-write + + + + OUT1_W1TS + 0x14 + 0x20 + - SDA_FILTER_EN - This is the filter enable bit for SDA. - 3 - 1 + OUT1_DATA_W1TS + GPIO32~39 output value write 1 to set + 0 + 8 read-write - 16 - 0x4 - COMD%s - 0x58 + OUT1_W1TC + 0x18 0x20 - COMMAND - This is the content of command. It consists of three part. op_code is the command : RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit. + OUT1_DATA_W1TC + GPIO32~39 output value write 1 to clear 0 - 14 + 8 read-write + + + + SDIO_SELECT + 0x1C + 0x20 + - COMMAND_DONE - When command is done in I2C Master mode this bit changes to high level. - 31 - 1 + SDIO_SEL + SDIO PADS on/off control from outside + 0 + 8 read-write - DATE - 0xF8 + ENABLE + 0x20 0x20 - 0x16042000 - DATE + DATA + GPIO0~31 output enable 0 32 read-write @@ -10860,743 +10835,796 @@ - FIFO_START_ADDR - 0x100 - 0x20 - - - - - I2C1 - I2C (Inter-Integrated Circuit) Controller - 0x3FF67000 - - I2C_EXT1 - 50 - - - - I2S0 - I2S (Inter-IC Sound) Controller - I2S - 0x3FF4F000 - - 0x0 - 0xB4 - registers - - - I2S0 - 32 - - - - CONF - 0x8 + ENABLE_W1TS + 0x24 0x20 - 0x00030300 - TX_RESET + ENABLE_DATA_W1TS + GPIO0~31 output enable write 1 to set 0 - 1 - read-write - - - RX_RESET - 1 - 1 - read-write - - - TX_FIFO_RESET - 2 - 1 - read-write - - - RX_FIFO_RESET - 3 - 1 - read-write - - - TX_START - 4 - 1 - read-write - - - RX_START - 5 - 1 + 32 read-write + + + + ENABLE_W1TC + 0x28 + 0x20 + - TX_SLAVE_MOD - 6 - 1 + ENABLE_DATA_W1TC + GPIO0~31 output enable write 1 to clear + 0 + 32 read-write + + + + ENABLE1 + 0x2C + 0x20 + - RX_SLAVE_MOD - 7 - 1 + DATA + GPIO32~39 output enable + 0 + 8 read-write + + + + ENABLE1_W1TS + 0x30 + 0x20 + - TX_RIGHT_FIRST - 8 - 1 + ENABLE1_DATA_W1TS + GPIO32~39 output enable write 1 to set + 0 + 8 read-write + + + + ENABLE1_W1TC + 0x34 + 0x20 + - RX_RIGHT_FIRST - 9 - 1 + ENABLE1_DATA_W1TC + GPIO32~39 output enable write 1 to clear + 0 + 8 read-write + + + + STRAP + 0x38 + 0x20 + - TX_MSB_SHIFT - 10 - 1 - read-write + STRAPPING + {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} + 0 + 16 + read-only + + + + IN + 0x3C + 0x20 + - RX_MSB_SHIFT - 11 - 1 + DATA_NEXT + GPIO0~31 input value + 0 + 32 read-write + + + + IN1 + 0x40 + 0x20 + - TX_SHORT_SYNC - 12 - 1 + DATA_NEXT + GPIO32~39 input value + 0 + 8 read-write + + + + STATUS + 0x44 + 0x20 + - RX_SHORT_SYNC - 13 - 1 + INT + GPIO0~31 interrupt status + 0 + 32 read-write + + + + STATUS_W1TS + 0x48 + 0x20 + - TX_MONO - 14 - 1 + STATUS_INT_W1TS + GPIO0~31 interrupt status write 1 to set + 0 + 32 read-write + + + + STATUS_W1TC + 0x4C + 0x20 + - RX_MONO - 15 - 1 + STATUS_INT_W1TC + GPIO0~31 interrupt status write 1 to clear + 0 + 32 read-write + + + + STATUS1 + 0x50 + 0x20 + - TX_MSB_RIGHT - 16 - 1 + INT + GPIO32~39 interrupt status + 0 + 8 read-write + + + + STATUS1_W1TS + 0x54 + 0x20 + - RX_MSB_RIGHT - 17 - 1 + STATUS1_INT_W1TS + GPIO32~39 interrupt status write 1 to set + 0 + 8 read-write + + + + STATUS1_W1TC + 0x58 + 0x20 + - SIG_LOOPBACK - 18 - 1 + STATUS1_INT_W1TC + GPIO32~39 interrupt status write 1 to clear + 0 + 8 read-write - INT_RAW - 0xC + ACPU_INT + 0x60 0x20 - RX_TAKE_DATA_INT_RAW + APPCPU_INT + GPIO0~31 APP CPU interrupt status 0 - 1 + 32 read-only + + + + ACPU_NMI_INT + 0x64 + 0x20 + - TX_PUT_DATA_INT_RAW - 1 - 1 + APPCPU_NMI_INT + GPIO0~31 APP CPU non-maskable interrupt status + 0 + 32 read-only + + + + PCPU_INT + 0x68 + 0x20 + - RX_WFULL_INT_RAW - 2 - 1 + PROCPU_INT + GPIO0~31 PRO CPU interrupt status + 0 + 32 read-only + + + + PCPU_NMI_INT + 0x6C + 0x20 + - RX_REMPTY_INT_RAW - 3 - 1 + PROCPU_NMI_INT + GPIO0~31 PRO CPU non-maskable interrupt status + 0 + 32 read-only + + + + CPUSDIO_INT + 0x70 + 0x20 + - TX_WFULL_INT_RAW - 4 - 1 + SDIO_INT + SDIO's extent GPIO0~31 interrupt + 0 + 32 read-only + + + + ACPU_INT1 + 0x74 + 0x20 + - TX_REMPTY_INT_RAW - 5 - 1 + APPCPU_INT_H + GPIO32~39 APP CPU interrupt status + 0 + 8 read-only + + + + ACPU_NMI_INT1 + 0x78 + 0x20 + - RX_HUNG_INT_RAW - 6 - 1 + APPCPU_NMI_INT_H + GPIO32~39 APP CPU non-maskable interrupt status + 0 + 8 read-only + + + + PCPU_INT1 + 0x7C + 0x20 + - TX_HUNG_INT_RAW - 7 - 1 + PROCPU_INT_H + GPIO32~39 PRO CPU interrupt status + 0 + 8 read-only + + + + PCPU_NMI_INT1 + 0x80 + 0x20 + - IN_DONE_INT_RAW - 8 - 1 + PROCPU_NMI_INT_H + GPIO32~39 PRO CPU non-maskable interrupt status + 0 + 8 read-only + + + + CPUSDIO_INT1 + 0x84 + 0x20 + - IN_SUC_EOF_INT_RAW - 9 - 1 + SDIO_INT_H + SDIO's extent GPIO32~39 interrupt + 0 + 8 read-only - IN_ERR_EOF_INT_RAW - 10 + PIN_PAD_DRIVER + 2 1 - read-only + read-write - OUT_DONE_INT_RAW - 11 - 1 - read-only + PIN_INT_TYPE + 7 + 3 + read-write - OUT_EOF_INT_RAW - 12 + PIN_WAKEUP_ENABLE + 10 1 - read-only + read-write - IN_DSCR_ERR_INT_RAW + PIN_CONFIG + 11 + 2 + read-write + + + PIN_INT_ENA 13 - 1 - read-only + 5 + read-write + + + + 40 + 0x4 + 0-39 + PIN%s + 0x88 + 0x20 + - OUT_DSCR_ERR_INT_RAW - 14 + PAD_DRIVER + if set to 0: normal output if set to 1: open drain + 2 1 - read-only + read-write - IN_DSCR_EMPTY_INT_RAW - 15 - 1 - read-only + INT_TYPE + if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger + 7 + 3 + read-write - OUT_TOTAL_EOF_INT_RAW - 16 + WAKEUP_ENABLE + GPIO wake up enable only available in light sleep + 10 1 - read-only + read-write + + + CONFIG + NA + 11 + 2 + read-write + + + INT_ENA + bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable + 13 + 5 + read-write - INT_ST - 0x10 + cali_conf + 0x128 0x20 - RX_TAKE_DATA_INT_ST + CALI_RTC_MAX 0 - 1 - read-only + 10 + read-write - TX_PUT_DATA_INT_ST - 1 + CALI_START + 31 1 - read-only + read-write + + + + cali_data + 0x12C + 0x20 + - RX_WFULL_INT_ST - 2 - 1 + CALI_VALUE_SYNC2 + 0 + 20 read-only - RX_REMPTY_INT_ST - 3 + CALI_RDY_REAL + 30 1 read-only - TX_WFULL_INT_ST - 4 + CALI_RDY_SYNC2 + 31 1 read-only + + + + 256 + 0x4 + 0-255 + FUNC%s_IN_SEL_CFG + 0x130 + 0x20 + - TX_REMPTY_INT_ST - 5 - 1 - read-only + IN_SEL + select one of the 256 inputs + 0 + 6 + read-write - RX_HUNG_INT_ST + IN_INV_SEL + revert the value of the input if you want to revert please set the value to 1 6 1 - read-only + read-write - TX_HUNG_INT_ST + SEL + if the slow signal bypass the io matrix or not if you want setting the value to 1 7 1 - read-only + read-write + + + + 40 + 0x4 + 0-39 + FUNC%s_OUT_SEL_CFG + 0x530 + 0x20 + - IN_DONE_INT_ST - 8 - 1 - read-only + OUT_SEL + select one of the 256 output to 40 GPIO + 0 + 9 + read-write - IN_SUC_EOF_INT_ST + INV_SEL + invert the output value if you want to revert the output value setting the value to 1 9 1 - read-only + read-write - IN_ERR_EOF_INT_ST + OEN_SEL + weather using the logical oen signal or not using the value setting by the register 10 1 - read-only + read-write - OUT_DONE_INT_ST + OEN_INV_SEL + invert the output enable value if you want to revert the output enable value setting the value to 1 11 1 - read-only + read-write + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIO_SIGMADELTA + 0x3FF44F00 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + 0-7 + SIGMADELTA%s + 0x0 + 0x20 + 0x0000FF00 + - OUT_EOF_INT_ST - 12 - 1 - read-only + SD0_IN + 0 + 8 + read-write - IN_DSCR_ERR_INT_ST - 13 - 1 - read-only + SD0_PRESCALE + 8 + 8 + read-write + + + + CG + 0x20 + 0x20 + - OUT_DSCR_ERR_INT_ST - 14 + SD_CLK_EN + 31 1 - read-only + read-write + + + + MISC + 0x24 + 0x20 + - IN_DSCR_EMPTY_INT_ST - 15 + SPI_SWAP + 31 1 - read-only + read-write + + + + VERSION + 0x28 + 0x20 + 0x01506190 + - OUT_TOTAL_EOF_INT_ST + SD_DATE + 0 + 28 + read-write + + + + + + + HINF + HINF Peripheral + HINF + 0x3FF4B000 + + 0x0 + 0x34 + registers + + + + CFG_DATA0 + 0x0 + 0x20 + 0x22226666 + + + USER_ID_FN1 + 0 + 16 + read-write + + + DEVICE_ID_FN1 16 - 1 - read-only + 16 + read-write - INT_ENA - 0x14 + CFG_DATA1 + 0x4 0x20 + 0x01110011 - RX_TAKE_DATA_INT_ENA + SDIO_ENABLE 0 1 read-write - TX_PUT_DATA_INT_ENA + SDIO_IOREADY1 1 1 read-write - RX_WFULL_INT_ENA + HIGHSPEED_ENABLE 2 1 read-write - RX_REMPTY_INT_ENA + HIGHSPEED_MODE 3 1 - read-write + read-only - TX_WFULL_INT_ENA + SDIO_CD_ENABLE 4 1 read-write - TX_REMPTY_INT_ENA + SDIO_IOREADY2 5 1 read-write - RX_HUNG_INT_ENA + SDIO_INT_MASK 6 1 read-write - TX_HUNG_INT_ENA + IOENABLE2 7 1 - read-write + read-only - IN_DONE_INT_ENA + CD_DISABLE 8 1 - read-write + read-only - IN_SUC_EOF_INT_ENA + FUNC1_EPS 9 1 - read-write + read-only - IN_ERR_EOF_INT_ENA + EMP 10 1 - read-write + read-only - OUT_DONE_INT_ENA + IOENABLE1 11 1 - read-write + read-only - OUT_EOF_INT_ENA + SDIO20_CONF0 12 - 1 - read-write - - - IN_DSCR_ERR_INT_ENA - 13 - 1 + 4 read-write - OUT_DSCR_ERR_INT_ENA - 14 - 1 + SDIO_VER + 16 + 12 read-write - IN_DSCR_EMPTY_INT_ENA - 15 + FUNC2_EPS + 28 1 - read-write + read-only - OUT_TOTAL_EOF_INT_ENA - 16 - 1 + SDIO20_CONF1 + 29 + 3 read-write - INT_CLR - 0x18 + CFG_DATA7 + 0x1C 0x20 + 0x00020000 - TAKE_DATA_INT_CLR + PIN_STATE 0 - 1 - write-only + 8 + read-write - PUT_DATA_INT_CLR - 1 - 1 - write-only + CHIP_STATE + 8 + 8 + read-write - RX_WFULL_INT_CLR - 2 + SDIO_RST + 16 1 - write-only + read-write - RX_REMPTY_INT_CLR - 3 + SDIO_IOREADY0 + 17 1 - write-only + read-write + + + + CIS_CONF0 + 0x20 + 0x20 + 0xFFFFFFFF + - TX_WFULL_INT_CLR - 4 - 1 - write-only - - - TX_REMPTY_INT_CLR - 5 - 1 - write-only - - - RX_HUNG_INT_CLR - 6 - 1 - write-only - - - TX_HUNG_INT_CLR - 7 - 1 - write-only - - - IN_DONE_INT_CLR - 8 - 1 - write-only - - - IN_SUC_EOF_INT_CLR - 9 - 1 - write-only - - - IN_ERR_EOF_INT_CLR - 10 - 1 - write-only - - - OUT_DONE_INT_CLR - 11 - 1 - write-only - - - OUT_EOF_INT_CLR - 12 - 1 - write-only - - - IN_DSCR_ERR_INT_CLR - 13 - 1 - write-only - - - OUT_DSCR_ERR_INT_CLR - 14 - 1 - write-only - - - IN_DSCR_EMPTY_INT_CLR - 15 - 1 - write-only - - - OUT_TOTAL_EOF_INT_CLR - 16 - 1 - write-only - - - - - TIMING - 0x1C - 0x20 - - - TX_BCK_IN_DELAY - 0 - 2 - read-write - - - TX_WS_IN_DELAY - 2 - 2 - read-write - - - RX_BCK_IN_DELAY - 4 - 2 - read-write - - - RX_WS_IN_DELAY - 6 - 2 - read-write - - - RX_SD_IN_DELAY - 8 - 2 - read-write - - - TX_BCK_OUT_DELAY - 10 - 2 - read-write - - - TX_WS_OUT_DELAY - 12 - 2 - read-write - - - TX_SD_OUT_DELAY - 14 - 2 - read-write - - - RX_WS_OUT_DELAY - 16 - 2 - read-write - - - RX_BCK_OUT_DELAY - 18 - 2 - read-write - - - TX_DSYNC_SW - 20 - 1 - read-write - - - RX_DSYNC_SW - 21 - 1 - read-write - - - DATA_ENABLE_DELAY - 22 - 2 - read-write - - - TX_BCK_IN_INV - 24 - 1 - read-write - - - - - FIFO_CONF - 0x20 - 0x20 - 0x00001820 - - - RX_DATA_NUM + CIS_CONF_W0 0 - 6 - read-write - - - TX_DATA_NUM - 6 - 6 - read-write - - - DSCR_EN - 12 - 1 - read-write - - - TX_FIFO_MOD - 13 - 3 - read-write - - - RX_FIFO_MOD - 16 - 3 - read-write - - - TX_FIFO_MOD_FORCE_EN - 19 - 1 - read-write - - - RX_FIFO_MOD_FORCE_EN - 20 - 1 + 32 read-write - RXEOF_NUM + CIS_CONF1 0x24 0x20 - 0x00000040 + 0xFFFFFFFF - RX_EOF_NUM + CIS_CONF_W1 0 32 read-write @@ -11604,12 +11632,13 @@ - CONF_SIGLE_DATA + CIS_CONF2 0x28 0x20 + 0xFFFFFFFF - SIGLE_DATA + CIS_CONF_W2 0 32 read-write @@ -11617,3092 +11646,2837 @@ - CONF_CHAN + CIS_CONF3 0x2C 0x20 + 0xFFFFFFFF - TX_CHAN_MOD + CIS_CONF_W3 0 - 3 - read-write - - - RX_CHAN_MOD - 3 - 2 + 32 read-write - OUT_LINK + CIS_CONF4 0x30 0x20 + 0xFFFFFFFF - OUTLINK_ADDR + CIS_CONF_W4 0 - 20 - read-write - - - OUTLINK_STOP - 28 - 1 - read-write - - - OUTLINK_START - 29 - 1 - read-write - - - OUTLINK_RESTART - 30 - 1 + 32 read-write - - OUTLINK_PARK - 31 - 1 - read-only - - IN_LINK + CIS_CONF5 0x34 0x20 + 0xFFFFFFFF - INLINK_ADDR + CIS_CONF_W5 0 - 20 - read-write - - - INLINK_STOP - 28 - 1 - read-write - - - INLINK_START - 29 - 1 - read-write - - - INLINK_RESTART - 30 - 1 + 32 read-write - - INLINK_PARK - 31 - 1 - read-only - - OUT_EOF_DES_ADDR + CIS_CONF6 0x38 0x20 + 0xFFFFFFFF - OUT_EOF_DES_ADDR + CIS_CONF_W6 0 32 - read-only + read-write - IN_EOF_DES_ADDR + CIS_CONF7 0x3C 0x20 + 0xFFFFFFFF - IN_SUC_EOF_DES_ADDR + CIS_CONF_W7 0 32 - read-only + read-write - OUT_EOF_BFR_DES_ADDR + CFG_DATA16 0x40 0x20 + 0x33336666 - OUT_EOF_BFR_DES_ADDR - 0 - 32 - read-only - - - - - AHB_TEST - 0x44 - 0x20 - - - AHB_TESTMODE + USER_ID_FN2 0 - 3 + 16 read-write - AHB_TESTADDR - 4 - 2 + DEVICE_ID_FN2 + 16 + 16 read-write - INLINK_DSCR - 0x48 - 0x20 - - - INLINK_DSCR - 0 - 32 - read-only - - - - - INLINK_DSCR_BF0 - 0x4C - 0x20 - - - INLINK_DSCR_BF0 - 0 - 32 - read-only - - - - - INLINK_DSCR_BF1 - 0x50 - 0x20 - - - INLINK_DSCR_BF1 - 0 - 32 - read-only - - - - - OUTLINK_DSCR - 0x54 - 0x20 - - - OUTLINK_DSCR - 0 - 32 - read-only - - - - - OUTLINK_DSCR_BF0 - 0x58 + DATE + 0xFC 0x20 + 0x15030200 - OUTLINK_DSCR_BF0 + SDIO_DATE 0 32 - read-only + read-write + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x3FF53000 + + 0x0 + 0x9C + registers + + + I2C_EXT0 + 49 + + - OUTLINK_DSCR_BF1 - 0x5C + SCL_LOW_PERIOD + 0x0 0x20 - OUTLINK_DSCR_BF1 + SCL_LOW_PERIOD + This register is used to configure the low level width of SCL clock. 0 - 32 - read-only + 14 + read-write - LC_CONF - 0x60 + CTR + 0x4 0x20 - 0x00000100 + 0x00000003 - IN_RST + SDA_FORCE_OUT + 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal) 0 1 read-write - OUT_RST + SCL_FORCE_OUT + 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal) 1 1 read-write - AHBM_FIFO_RST + SAMPLE_SCL_LEVEL + Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. 2 1 read-write - AHBM_RST - 3 - 1 - read-write - - - OUT_LOOP_TEST + MS_MODE + Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. 4 1 read-write - IN_LOOP_TEST + TRANS_START + Set this bit to start sending data in txfifo. 5 1 read-write - OUT_AUTO_WRBACK + TX_LSB_FIRST + This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit 6 1 read-write - OUT_NO_RESTART_CLR + RX_LSB_FIRST + This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit 7 1 read-write - OUT_EOF_MODE + CLK_EN + This is the clock gating control bit for reading or writing registers. 8 1 read-write + + + + SR + 0x8 + 0x20 + - OUTDSCR_BURST_EN - 9 + ACK_REC + This register stores the value of ACK bit. + 0 1 - read-write + read-only - INDSCR_BURST_EN - 10 + SLAVE_RW + when in slave mode 1: master read slave 0: master write slave. + 1 1 - read-write + read-only - OUT_DATA_BURST_EN - 11 + TIME_OUT + when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. + 2 1 - read-write + read-only - CHECK_OWNER - 12 + ARB_LOST + when I2C lost control of SDA line this register changes to high level. + 3 1 - read-write + read-only - MEM_TRANS_EN - 13 + BUS_BUSY + 1:I2C bus is busy transferring data. 0:I2C bus is in idle state. + 4 1 - read-write - - - - - OUTFIFO_PUSH - 0x64 - 0x20 - - - OUTFIFO_WDATA - 0 - 9 - read-write + read-only - OUTFIFO_PUSH - 16 + SLAVE_ADDRESSED + when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level. + 5 1 - read-write - - - - - INFIFO_POP - 0x68 - 0x20 - - - INFIFO_RDATA - 0 - 12 read-only - INFIFO_POP - 16 + BYTE_TRANS + This register changes to high level when one byte is transferred. + 6 1 - read-write - - - - - LC_STATE0 - 0x6C - 0x20 - - - LC_STATE0 - 0 - 32 read-only - - - - LC_STATE1 - 0x70 - 0x20 - - LC_STATE1 - 0 - 32 + RXFIFO_CNT + This register represent the amount of data need to send. + 8 + 6 read-only - - - - LC_HUNG_CONF - 0x74 - 0x20 - 0x00000810 - - LC_FIFO_TIMEOUT - 0 - 8 - read-write + TXFIFO_CNT + This register stores the amount of received data in ram. + 18 + 6 + read-only - LC_FIFO_TIMEOUT_SHIFT - 8 + SCL_MAIN_STATE_LAST + This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK + 24 3 - read-write + read-only - LC_FIFO_TIMEOUT_ENA - 11 - 1 - read-write + SCL_STATE_LAST + This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP + 28 + 3 + read-only - CVSD_CONF0 - 0x80 + TO + 0xC 0x20 - 0x80007FFF - CVSD_Y_MAX + TIME_OUT + This register is used to configure the max clock number of receiving a data. 0 - 16 - read-write - - - CVSD_Y_MIN - 16 - 16 + 20 read-write - CVSD_CONF1 - 0x84 + SLAVE_ADDR + 0x10 0x20 - 0x000A0500 - CVSD_SIGMA_MAX + SLAVE_ADDR + when configured as i2c slave this register is used to configure slave's address. 0 - 16 + 15 read-write - CVSD_SIGMA_MIN - 16 - 16 + ADDR_10BIT_EN + This register is used to enable slave 10bit address mode. + 31 + 1 read-write - CVSD_CONF2 - 0x88 + RXFIFO_ST + 0x14 0x20 - 0x000502A4 - CVSD_K + RXFIFO_START_ADDR + This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. 0 - 3 - read-write + 5 + read-only - CVSD_J - 3 - 3 - read-write + RXFIFO_END_ADDR + This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. + 5 + 5 + read-only - CVSD_BETA - 6 - 10 - read-write + TXFIFO_START_ADDR + This is the offset address of the first sending data as described in nonfifo_tx_thres register. + 10 + 5 + read-only - CVSD_H - 16 - 3 - read-write + TXFIFO_END_ADDR + This is the offset address of the last sending data as described in nonfifo_tx_thres register. + 15 + 5 + read-only - PLC_CONF0 - 0x8C + FIFO_CONF + 0x18 0x20 - 0x08A80339 + 0x0155408B - GOOD_PACK_MAX + RXFIFO_FULL_THRHD 0 - 6 - read-write - - - N_ERR_SEG - 6 - 3 - read-write - - - SHIFT_RATE - 9 - 3 - read-write - - - MAX_SLIDE_SAMPLE - 12 - 8 + 5 read-write - PACK_LEN_8K - 20 + TXFIFO_EMPTY_THRHD + Config txfifo empty threhd value when using apb fifo access + 5 5 read-write - N_MIN_ERR - 25 - 3 + NONFIFO_EN + Set this bit to enble apb nonfifo access. + 10 + 1 read-write - - - - PLC_CONF1 - 0x90 - 0x20 - 0xA0178A05 - - BAD_CEF_ATTEN_PARA - 0 - 8 + FIFO_ADDR_CFG_EN + When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. + 11 + 1 read-write - BAD_CEF_ATTEN_PARA_SHIFT - 8 - 4 + RX_FIFO_RST + Set this bit to reset rx fifo when using apb fifo access. + 12 + 1 read-write - BAD_OLA_WIN2_PARA_SHIFT - 12 - 4 + TX_FIFO_RST + Set this bit to reset tx fifo when using apb fifo access. + 13 + 1 read-write - BAD_OLA_WIN2_PARA - 16 - 8 + NONFIFO_RX_THRES + when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. + 14 + 6 read-write - SLIDE_WIN_LEN - 24 - 8 + NONFIFO_TX_THRES + when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. + 20 + 6 read-write - PLC_CONF2 - 0x94 + DATA + 0x1C 0x20 - 0x00000028 - CVSD_SEG_MOD + FIFO_RDATA + The register represent the byte data read from rxfifo when use apb fifo access 0 - 2 - read-write - - - MIN_PERIOD - 2 - 5 - read-write + 8 + read-only - ESCO_CONF0 - 0x98 + INT_RAW + 0x20 0x20 - ESCO_EN + RXFIFO_FULL_INT_RAW + The raw interrupt status bit for rxfifo full when use apb fifo access. 0 1 - read-write + read-only - ESCO_CHAN_MOD + TXFIFO_EMPTY_INT_RAW + The raw interrupt status bit for txfifo empty when use apb fifo access. 1 1 - read-write + read-only - ESCO_CVSD_DEC_PACK_ERR + RXFIFO_OVF_INT_RAW + The raw interrupt status bit for receiving data overflow when use apb fifo access. 2 1 - read-write + read-only - ESCO_CVSD_PACK_LEN_8K + END_DETECT_INT_RAW + The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. 3 - 5 - read-write + 1 + read-only - ESCO_CVSD_INF_EN + SLAVE_TRAN_COMP_INT_RAW + The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. + 5 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. 8 1 - read-write + read-only - CVSD_DEC_START + TRANS_START_INT_RAW + The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. 9 1 - read-write + read-only - CVSD_DEC_RESET + ACK_ERR_INT_RAW + The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. 10 1 - read-write + read-only - PLC_EN + RX_REC_FULL_INT_RAW + The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. 11 1 - read-write + read-only - PLC2DMA_EN + TX_SEND_EMPTY_INT_RAW + The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. 12 1 - read-write + read-only - SCO_CONF0 - 0x9C + INT_CLR + 0x24 0x20 - SCO_WITH_I2S_EN + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int interrupt. 0 1 - read-write + write-only - SCO_NO_I2S_EN + TXFIFO_EMPTY_INT_CLR + Set this bit to clear the txfifo_empty_int interrupt. 1 1 - read-write + write-only - CVSD_ENC_START + RXFIFO_OVF_INT_CLR + Set this bit to clear the rxfifo_ovf_int interrupt. 2 1 - read-write + write-only - CVSD_ENC_RESET + END_DETECT_INT_CLR + Set this bit to clear the end_detect_int interrupt. 3 1 - read-write + write-only - - - - CONF1 - 0xA0 - 0x20 - 0x00000089 - - TX_PCM_CONF - 0 - 3 - read-write + SLAVE_TRAN_COMP_INT_CLR + Set this bit to clear the slave_tran_comp_int interrupt. + 4 + 1 + write-only - TX_PCM_BYPASS - 3 + ARBITRATION_LOST_INT_CLR + Set this bit to clear the arbitration_lost_int interrupt. + 5 1 - read-write + write-only - RX_PCM_CONF - 4 - 3 - read-write + MASTER_TRAN_COMP_INT_CLR + Set this bit to clear the master_tran_comp interrupt. + 6 + 1 + write-only - RX_PCM_BYPASS + TRANS_COMPLETE_INT_CLR + Set this bit to clear the trans_complete_int interrupt. 7 1 - read-write + write-only - TX_STOP_EN + TIME_OUT_INT_CLR + Set this bit to clear the time_out_int interrupt. 8 1 - read-write + write-only - TX_ZEROS_RM_EN + TRANS_START_INT_CLR + Set this bit to clear the trans_start_int interrupt. 9 1 - read-write - - - - - PD_CONF - 0xA4 - 0x20 - 0x0000000A - - - FIFO_FORCE_PD - 0 - 1 - read-write + write-only - FIFO_FORCE_PU - 1 + ACK_ERR_INT_CLR + Set this bit to clear the ack_err_int interrupt. + 10 1 - read-write + write-only - PLC_MEM_FORCE_PD - 2 + RX_REC_FULL_INT_CLR + Set this bit to clear the rx_rec_full_int interrupt. + 11 1 - read-write + write-only - PLC_MEM_FORCE_PU - 3 + TX_SEND_EMPTY_INT_CLR + Set this bit to clear the tx_send_empty_int interrupt. + 12 1 - read-write + write-only - CONF2 - 0xA8 + INT_ENA + 0x28 0x20 - CAMERA_EN + RXFIFO_FULL_INT_ENA + The enable bit for rxfifo_full_int interrupt. 0 1 read-write - LCD_TX_WRX2_EN + TXFIFO_EMPTY_INT_ENA + The enable bit for txfifo_empty_int interrupt. 1 1 read-write - LCD_TX_SDX2_EN + RXFIFO_OVF_INT_ENA + The enable bit for rxfifo_ovf_int interrupt. 2 1 read-write - DATA_ENABLE_TEST_EN + END_DETECT_INT_ENA + The enable bit for end_detect_int interrupt. 3 1 read-write - DATA_ENABLE + SLAVE_TRAN_COMP_INT_ENA + The enable bit for slave_tran_comp_int interrupt. 4 1 read-write - LCD_EN + ARBITRATION_LOST_INT_ENA + The enable bit for arbitration_lost_int interrupt. 5 1 read-write - EXT_ADC_START_EN + MASTER_TRAN_COMP_INT_ENA + The enable bit for master_tran_comp_int interrupt. 6 1 read-write - INTER_VALID_EN + TRANS_COMPLETE_INT_ENA + The enable bit for trans_complete_int interrupt. 7 1 read-write - - - - CLKM_CONF - 0xAC - 0x20 - 0x00000004 - - CLKM_DIV_NUM - 0 - 8 + TIME_OUT_INT_ENA + The enable bit for time_out_int interrupt. + 8 + 1 read-write - CLKM_DIV_B - 8 - 6 + TRANS_START_INT_ENA + The enable bit for trans_start_int interrupt. + 9 + 1 read-write - CLKM_DIV_A - 14 - 6 + ACK_ERR_INT_ENA + The enable bit for ack_err_int interrupt. + 10 + 1 read-write - CLK_EN - 20 + RX_REC_FULL_INT_ENA + The enable bit for rx_rec_full_int interrupt. + 11 1 read-write - CLKA_ENA - 21 + TX_SEND_EMPTY_INT_ENA + The enable bit for tx_send_empty_int interrupt. + 12 1 read-write - SAMPLE_RATE_CONF - 0xB0 + INT_STATUS + 0x2C 0x20 - 0x00410186 - TX_BCK_DIV_NUM + RXFIFO_FULL_INT_ST + The masked interrupt status for rxfifo_full_int interrupt. 0 - 6 - read-write + 1 + read-only - RX_BCK_DIV_NUM + TXFIFO_EMPTY_INT_ST + The masked interrupt status for txfifo_empty_int interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status for rxfifo_ovf_int interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status for end_detect_int interrupt. + 3 + 1 + read-only + + + SLAVE_TRAN_COMP_INT_ST + The masked interrupt status for slave_tran_comp_int interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status for arbitration_lost_int interrupt. + 5 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + The masked interrupt status for master_tran_comp_int interrupt. 6 - 6 - read-write + 1 + read-only - TX_BITS_MOD - 12 - 6 - read-write + TRANS_COMPLETE_INT_ST + The masked interrupt status for trans_complete_int interrupt. + 7 + 1 + read-only - RX_BITS_MOD - 18 - 6 - read-write + TIME_OUT_INT_ST + The masked interrupt status for time_out_int interrupt. + 8 + 1 + read-only - - - - PDM_CONF - 0xB4 - 0x20 - 0x01550020 - - TX_PDM_EN - 0 + TRANS_START_INT_ST + The masked interrupt status for trans_start_int interrupt. + 9 1 - read-write + read-only - RX_PDM_EN - 1 + ACK_ERR_INT_ST + The masked interrupt status for ack_err_int interrupt. + 10 1 - read-write + read-only - PCM2PDM_CONV_EN - 2 + RX_REC_FULL_INT_ST + The masked interrupt status for rx_rec_full_int interrupt. + 11 1 - read-write + read-only - PDM2PCM_CONV_EN - 3 + TX_SEND_EMPTY_INT_ST + The masked interrupt status for tx_send_empty_int interrupt. + 12 1 + read-only + + + + + SDA_HOLD + 0x30 + 0x20 + + + TIME + This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. + 0 + 10 read-write + + + + SDA_SAMPLE + 0x34 + 0x20 + - TX_PDM_SINC_OSR2 - 4 - 4 + TIME + This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL + 0 + 10 read-write + + + + SCL_HIGH_PERIOD + 0x38 + 0x20 + - TX_PDM_PRESCALE - 8 - 8 + SCL_HIGH_PERIOD + This register is used to configure the clock num during SCL is low level. + 0 + 14 read-write + + + + SCL_START_HOLD + 0x40 + 0x20 + 0x00000008 + - TX_PDM_HP_IN_SHIFT - 16 - 2 + TIME + This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. + 0 + 10 read-write + + + + SCL_RSTART_SETUP + 0x44 + 0x20 + 0x00000008 + - TX_PDM_LP_IN_SHIFT - 18 - 2 + TIME + This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. + 0 + 10 read-write + + + + SCL_STOP_HOLD + 0x48 + 0x20 + - TX_PDM_SINC_IN_SHIFT - 20 - 2 + TIME + This register is used to configure the clock num after the STOP bit's posedge. + 0 + 14 read-write + + + + SCL_STOP_SETUP + 0x4C + 0x20 + - TX_PDM_SIGMADELTA_IN_SHIFT - 22 - 2 + TIME + This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. + 0 + 10 read-write + + + + SCL_FILTER_CFG + 0x50 + 0x20 + 0x00000008 + - RX_PDM_SINC_DSR_16_EN - 24 - 1 + SCL_FILTER_THRES + When input SCL's pulse width is smaller than this register value I2C ignores this pulse. + 0 + 3 read-write - TX_PDM_HP_BYPASS - 25 + SCL_FILTER_EN + This is the filter enable bit for SCL. + 3 1 read-write - PDM_FREQ_CONF - 0xB8 + SDA_FILTER_CFG + 0x54 0x20 - 0x000F01E0 + 0x00000008 - TX_PDM_FS + SDA_FILTER_THRES + When input SCL's pulse width is smaller than this register value I2C ignores this pulse. 0 - 10 + 3 read-write - TX_PDM_FP - 10 - 10 + SDA_FILTER_EN + This is the filter enable bit for SDA. + 3 + 1 read-write - STATE - 0xBC + 16 + 0x4 + 0-15 + COMD%s + 0x58 0x20 - 0x00000007 - TX_IDLE + COMMAND + This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit. 0 - 1 - read-only - - - TX_FIFO_RESET_BACK - 1 - 1 - read-only + 14 + read-write - RX_FIFO_RESET_BACK - 2 + COMMAND_DONE + When command0 is done in I2C Master mode this bit changes to high level. + 31 1 - read-only + read-write DATE - 0xFC + 0xF8 0x20 - 0x01604201 + 0x16042000 - I2SDATE + DATE 0 32 read-write + + FIFO_START_ADDR + 0x100 + 0x20 + - - I2S1 - I2S (Inter-IC Sound) Controller - 0x3FF6D000 + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x3FF67000 - I2S1 - 33 + I2C_EXT1 + 50 - IO_MUX - Input/Output Multiplexer - IO_MUX - 0x3FF49000 + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x3FF4F000 0x0 - 0x94 + 0xB4 registers + + I2S0 + 32 + - PIN_CTRL - 0x0 - 0x20 - - - CLK1 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. - 0 - 4 - read-write - - - CLK2 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. - 4 - 4 - read-write - - - CLK3 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. - 8 - 4 - read-write - - - - - GPIO36 - 0x4 + CONF + 0x8 0x20 + 0x00030300 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + TX_RESET 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + RX_RESET 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + TX_FIFO_RESET 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + RX_FIFO_RESET 3 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_START 4 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + RX_START 5 - 2 + 1 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + TX_SLAVE_MOD + 6 + 1 + read-write + + + RX_SLAVE_MOD 7 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + TX_RIGHT_FIRST 8 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + RX_RIGHT_FIRST 9 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + TX_MSB_SHIFT 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write - - - - - GPIO37 - 0x8 - 0x20 - - - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. - 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 + RX_MSB_SHIFT + 11 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 + TX_SHORT_SYNC + 12 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 + RX_SHORT_SYNC + 13 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + TX_MONO + 14 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + RX_MONO + 15 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + TX_MSB_RIGHT + 16 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + RX_MSB_RIGHT + 17 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + SIG_LOOPBACK + 18 + 1 read-write - GPIO38 + INT_RAW 0xC 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + RX_TAKE_DATA_INT_RAW 0 1 - read-write + read-only - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + TX_PUT_DATA_INT_RAW 1 1 - read-write + read-only - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + RX_WFULL_INT_RAW 2 1 - read-write + read-only - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + RX_REMPTY_INT_RAW 3 1 - read-write + read-only - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_WFULL_INT_RAW 4 1 - read-write + read-only - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + TX_REMPTY_INT_RAW 5 - 2 - read-write + 1 + read-only - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + RX_HUNG_INT_RAW + 6 + 1 + read-only + + + TX_HUNG_INT_RAW 7 1 - read-write + read-only - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + IN_DONE_INT_RAW 8 1 - read-write + read-only - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + IN_SUC_EOF_INT_RAW 9 1 - read-write + read-only - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + IN_ERR_EOF_INT_RAW 10 - 2 - read-write + 1 + read-only - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + OUT_DONE_INT_RAW + 11 + 1 + read-only + + + OUT_EOF_INT_RAW 12 - 3 - read-write + 1 + read-only + + + IN_DSCR_ERR_INT_RAW + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_RAW + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_RAW + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + 16 + 1 + read-only - GPIO39 + INT_ST 0x10 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + RX_TAKE_DATA_INT_ST 0 1 - read-write + read-only - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + TX_PUT_DATA_INT_ST 1 1 - read-write + read-only - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + RX_WFULL_INT_ST 2 1 - read-write + read-only - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + RX_REMPTY_INT_ST 3 1 - read-write + read-only - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_WFULL_INT_ST 4 1 - read-write + read-only - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + TX_REMPTY_INT_ST 5 - 2 - read-write + 1 + read-only - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + RX_HUNG_INT_ST + 6 + 1 + read-only + + + TX_HUNG_INT_ST 7 1 - read-write + read-only - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + IN_DONE_INT_ST 8 1 - read-write + read-only - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + IN_SUC_EOF_INT_ST 9 1 - read-write + read-only - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + IN_ERR_EOF_INT_ST 10 - 2 - read-write + 1 + read-only - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + OUT_DONE_INT_ST + 11 + 1 + read-only + + + OUT_EOF_INT_ST 12 - 3 - read-write + 1 + read-only + + + IN_DSCR_ERR_INT_ST + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_ST + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_ST + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + 16 + 1 + read-only - GPIO34 + INT_ENA 0x14 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + RX_TAKE_DATA_INT_ENA 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + TX_PUT_DATA_INT_ENA 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + RX_WFULL_INT_ENA 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + RX_REMPTY_INT_ENA 3 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_WFULL_INT_ENA 4 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + TX_REMPTY_INT_ENA 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + RX_HUNG_INT_ENA + 6 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + TX_HUNG_INT_ENA + 7 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write - - - - - GPIO35 - 0x18 - 0x20 - - - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. - 0 + IN_DONE_INT_ENA + 8 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 + IN_SUC_EOF_INT_ENA + 9 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 + IN_ERR_EOF_INT_ENA + 10 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 + OUT_DONE_INT_ENA + 11 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + OUT_EOF_INT_ENA + 12 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + IN_DSCR_ERR_INT_ENA + 13 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + OUT_DSCR_ERR_INT_ENA + 14 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + IN_DSCR_EMPTY_INT_ENA + 15 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + OUT_TOTAL_EOF_INT_ENA + 16 + 1 read-write - GPIO32 - 0x1C + INT_CLR + 0x18 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + TAKE_DATA_INT_CLR 0 1 - read-write + write-only - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + PUT_DATA_INT_CLR 1 1 - read-write + write-only - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + RX_WFULL_INT_CLR 2 1 - read-write + write-only - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + RX_REMPTY_INT_CLR 3 1 - read-write + write-only - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_WFULL_INT_CLR 4 1 - read-write + write-only - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + TX_REMPTY_INT_CLR 5 - 2 - read-write + 1 + write-only - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + RX_HUNG_INT_CLR + 6 + 1 + write-only + + + TX_HUNG_INT_CLR 7 1 - read-write + write-only - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + IN_DONE_INT_CLR 8 1 - read-write + write-only - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + IN_SUC_EOF_INT_CLR 9 1 - read-write + write-only - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + IN_ERR_EOF_INT_CLR 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write - - - - - GPIO33 - 0x20 - 0x20 - - - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. - 0 1 - read-write + write-only - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 + OUT_DONE_INT_CLR + 11 1 - read-write + write-only - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 + OUT_EOF_INT_CLR + 12 1 - read-write + write-only - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 + IN_DSCR_ERR_INT_CLR + 13 1 - read-write + write-only - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + OUT_DSCR_ERR_INT_CLR + 14 1 - read-write - - - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write + write-only - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + IN_DSCR_EMPTY_INT_CLR + 15 1 - read-write + write-only - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + OUT_TOTAL_EOF_INT_CLR + 16 1 - read-write + write-only + + + + TIMING + 0x1C + 0x20 + - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + TX_BCK_IN_DELAY + 0 + 2 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 + TX_WS_IN_DELAY + 2 2 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + RX_BCK_IN_DELAY + 4 + 2 read-write - - - - GPIO25 - 0x24 - 0x20 - - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. - 0 - 1 + RX_WS_IN_DELAY + 6 + 2 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 + RX_SD_IN_DELAY + 8 + 2 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 + TX_BCK_OUT_DELAY + 10 + 2 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 + TX_WS_OUT_DELAY + 12 + 2 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 + TX_SD_OUT_DELAY + 14 + 2 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 + RX_WS_OUT_DELAY + 16 2 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + RX_BCK_OUT_DELAY + 18 + 2 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + TX_DSYNC_SW + 20 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + RX_DSYNC_SW + 21 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 + DATA_ENABLE_DELAY + 22 2 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + TX_BCK_IN_INV + 24 + 1 read-write - GPIO26 - 0x28 + FIFO_CONF + 0x20 0x20 + 0x00001820 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + RX_DATA_NUM 0 - 1 + 6 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 + TX_DATA_NUM + 6 + 6 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 + DSCR_EN + 12 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 + TX_FIFO_MOD + 13 + 3 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 + RX_FIFO_MOD + 16 + 3 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + TX_FIFO_MOD_FORCE_EN + 19 + 1 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + RX_FIFO_MOD_FORCE_EN + 20 1 read-write + + + + RXEOF_NUM + 0x24 + 0x20 + 0x00000040 + - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 + RX_EOF_NUM + 0 + 32 read-write + + + + CONF_SIGLE_DATA + 0x28 + 0x20 + - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + SIGLE_DATA + 0 + 32 read-write + + + + CONF_CHAN + 0x2C + 0x20 + - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 + TX_CHAN_MOD + 0 + 3 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + RX_CHAN_MOD + 3 + 2 read-write - GPIO27 - 0x2C + OUT_LINK + 0x30 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + OUTLINK_ADDR 0 - 1 + 20 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 + OUTLINK_STOP + 28 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 + OUTLINK_START + 29 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 + OUTLINK_RESTART + 30 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + OUTLINK_PARK + 31 1 - read-write + read-only + + + + IN_LINK + 0x34 + 0x20 + - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + INLINK_ADDR + 0 + 20 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + INLINK_STOP + 28 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + INLINK_START + 29 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + INLINK_RESTART + 30 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write + INLINK_PARK + 31 + 1 + read-only - GPIO14 - 0x30 + OUT_EOF_DES_ADDR + 0x38 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + OUT_EOF_DES_ADDR 0 - 1 - read-write + 32 + read-only + + + + IN_EOF_DES_ADDR + 0x3C + 0x20 + - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 - read-write + IN_SUC_EOF_DES_ADDR + 0 + 32 + read-only + + + + OUT_EOF_BFR_DES_ADDR + 0x40 + 0x20 + - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 - read-write + OUT_EOF_BFR_DES_ADDR + 0 + 32 + read-only + + + + AHB_TEST + 0x44 + 0x20 + - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 + AHB_TESTMODE + 0 + 3 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + AHB_TESTADDR 4 - 1 + 2 read-write + + + + INLINK_DSCR + 0x48 + 0x20 + - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write + INLINK_DSCR + 0 + 32 + read-only + + + + INLINK_DSCR_BF0 + 0x4C + 0x20 + - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 - read-write + INLINK_DSCR_BF0 + 0 + 32 + read-only + + + + INLINK_DSCR_BF1 + 0x50 + 0x20 + - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 - read-write + INLINK_DSCR_BF1 + 0 + 32 + read-only + + + + OUTLINK_DSCR + 0x54 + 0x20 + - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 - read-write + OUTLINK_DSCR + 0 + 32 + read-only + + + + OUTLINK_DSCR_BF0 + 0x58 + 0x20 + - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write + OUTLINK_DSCR_BF0 + 0 + 32 + read-only + + + + OUTLINK_DSCR_BF1 + 0x5C + 0x20 + - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write + OUTLINK_DSCR_BF1 + 0 + 32 + read-only - GPIO12 - 0x34 + LC_CONF + 0x60 0x20 + 0x00000100 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + IN_RST 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + OUT_RST 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + AHBM_FIFO_RST 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + AHBM_RST 3 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + OUT_LOOP_TEST 4 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + IN_LOOP_TEST 5 - 2 + 1 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + OUT_AUTO_WRBACK + 6 + 1 + read-write + + + OUT_NO_RESTART_CLR 7 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + OUT_EOF_MODE 8 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + OUTDSCR_BURST_EN 9 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + INDSCR_BURST_EN 10 - 2 + 1 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + OUT_DATA_BURST_EN + 11 + 1 + read-write + + + CHECK_OWNER 12 - 3 + 1 + read-write + + + MEM_TRANS_EN + 13 + 1 read-write - GPIO13 - 0x38 + OUTFIFO_PUSH + 0x64 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + OUTFIFO_WDATA 0 - 1 + 9 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 + OUTFIFO_PUSH + 16 1 read-write + + + + INFIFO_POP + 0x68 + 0x20 + - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 - read-write + INFIFO_RDATA + 0 + 12 + read-only - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 + INFIFO_POP + 16 1 read-write + + + + LC_STATE0 + 0x6C + 0x20 + - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 - read-write + LC_STATE0 + 0 + 32 + read-only + + + + LC_STATE1 + 0x70 + 0x20 + - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write + LC_STATE1 + 0 + 32 + read-only + + + + LC_HUNG_CONF + 0x74 + 0x20 + 0x00000810 + - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + LC_FIFO_TIMEOUT + 0 + 8 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + LC_FIFO_TIMEOUT_SHIFT 8 - 1 + 3 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + LC_FIFO_TIMEOUT_ENA + 11 1 read-write + + + + CVSD_CONF0 + 0x80 + 0x20 + 0x80007FFF + - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 + CVSD_Y_MAX + 0 + 16 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + CVSD_Y_MIN + 16 + 16 read-write - GPIO15 - 0x3C + CVSD_CONF1 + 0x84 0x20 + 0x000A0500 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + CVSD_SIGMA_MAX 0 - 1 + 16 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 + CVSD_SIGMA_MIN + 16 + 16 read-write - - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 + + + + CVSD_CONF2 + 0x88 + 0x20 + 0x000502A4 + + + CVSD_K + 0 + 3 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + CVSD_J 3 - 1 + 3 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 + CVSD_BETA + 6 + 10 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + CVSD_H + 16 + 3 read-write + + + + PLC_CONF0 + 0x8C + 0x20 + 0x08A80339 + - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + GOOD_PACK_MAX + 0 + 6 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 + N_ERR_SEG + 6 + 3 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + SHIFT_RATE 9 - 1 + 3 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 + MAX_SLIDE_SAMPLE + 12 + 8 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 + PACK_LEN_8K + 20 + 5 + read-write + + + N_MIN_ERR + 25 3 read-write - GPIO2 - 0x40 + PLC_CONF1 + 0x90 0x20 + 0xA0178A05 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + BAD_CEF_ATTEN_PARA 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 - read-write - - - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 - read-write - - - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 - read-write - - - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 + 8 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + BAD_CEF_ATTEN_PARA_SHIFT + 8 + 4 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + BAD_OLA_WIN2_PARA_SHIFT + 12 + 4 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 + BAD_OLA_WIN2_PARA + 16 + 8 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + SLIDE_WIN_LEN + 24 + 8 read-write + + + + PLC_CONF2 + 0x94 + 0x20 + 0x00000028 + - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 + CVSD_SEG_MOD + 0 2 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + MIN_PERIOD + 2 + 5 read-write - GPIO0 - 0x44 + ESCO_CONF0 + 0x98 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + ESCO_EN 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + ESCO_CHAN_MOD 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + ESCO_CVSD_DEC_PACK_ERR 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + ESCO_CVSD_PACK_LEN_8K 3 - 1 + 5 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + ESCO_CVSD_INF_EN + 8 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + CVSD_DEC_START + 9 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + CVSD_DEC_RESET + 10 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + PLC_EN + 11 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + PLC2DMA_EN 12 - 3 + 1 read-write - GPIO4 - 0x48 + SCO_CONF0 + 0x9C 0x20 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + SCO_WITH_I2S_EN 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + SCO_NO_I2S_EN 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + CVSD_ENC_START 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + CVSD_ENC_RESET 3 1 read-write + + + + CONF1 + 0xA0 + 0x20 + 0x00000089 + + + TX_PCM_CONF + 0 + 3 + read-write + - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + TX_PCM_BYPASS + 3 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + RX_PCM_CONF + 4 + 3 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + RX_PCM_BYPASS 7 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + TX_STOP_EN 8 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. + TX_ZEROS_RM_EN 9 1 read-write - - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write - - GPIO16 - 0x4C + PD_CONF + 0xA4 0x20 + 0x0000000A - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + FIFO_FORCE_PD 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + FIFO_FORCE_PU 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + PLC_MEM_FORCE_PD 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + PLC_MEM_FORCE_PU 3 1 read-write + + + + CONF2 + 0xA8 + 0x20 + - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + CAMERA_EN + 0 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + LCD_TX_WRX2_EN + 1 + 1 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + LCD_TX_SDX2_EN + 2 1 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 + DATA_ENABLE_TEST_EN + 3 1 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 + DATA_ENABLE + 4 1 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 + LCD_EN + 5 + 1 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + EXT_ADC_START_EN + 6 + 1 + read-write + + + INTER_VALID_EN + 7 + 1 read-write - GPIO17 - 0x50 + CLKM_CONF + 0xAC 0x20 + 0x00000004 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + CLKM_DIV_NUM 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 + 8 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 + CLKM_DIV_B + 8 + 6 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 + CLKM_DIV_A + 14 + 6 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 + CLK_EN + 20 1 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 + CLKA_ENA + 21 1 read-write + + + + SAMPLE_RATE_CONF + 0xB0 + 0x20 + 0x00410186 + - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 + TX_BCK_DIV_NUM + 0 + 6 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + RX_BCK_DIV_NUM + 6 + 6 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 + TX_BITS_MOD + 12 + 6 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + RX_BITS_MOD + 18 + 6 read-write - GPIO9 - 0x54 + PDM_CONF + 0xB4 0x20 + 0x01550020 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + TX_PDM_EN 0 1 read-write - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + RX_PDM_EN 1 1 read-write - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + PCM2PDM_CONV_EN 2 1 read-write - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + PDM2PCM_CONV_EN 3 1 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + TX_PDM_SINC_OSR2 4 - 1 + 4 read-write - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 + TX_PDM_PRESCALE + 8 + 8 read-write - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + TX_PDM_HP_IN_SHIFT + 16 + 2 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 + TX_PDM_LP_IN_SHIFT + 18 + 2 read-write - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + TX_PDM_SINC_IN_SHIFT + 20 + 2 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 + TX_PDM_SIGMADELTA_IN_SHIFT + 22 2 read-write - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + RX_PDM_SINC_DSR_16_EN + 24 + 1 + read-write + + + TX_PDM_HP_BYPASS + 25 + 1 read-write - GPIO10 - 0x58 + PDM_FREQ_CONF + 0xB8 0x20 + 0x000F01E0 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + TX_PDM_FS 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 - read-write - - - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 - read-write - - - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 - read-write - - - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 - read-write - - - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 - read-write - - - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 - read-write - - - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 + 10 read-write - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + TX_PDM_FP 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + 10 read-write - GPIO11 - 0x5C + STATE + 0xBC 0x20 + 0x00000007 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + TX_IDLE 0 1 - read-write + read-only - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + TX_FIFO_RESET_BACK 1 1 - read-write + read-only - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + RX_FIFO_RESET_BACK 2 1 - read-write - - - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 - read-write - - - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. - 4 - 1 - read-write - - - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 - read-write - - - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. - 8 - 1 - read-write - - - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 - read-write - - - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 - read-write + read-only - GPIO6 - 0x60 + DATE + 0xFC 0x20 + 0x01604201 - MCU_OE - Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + I2SDATE 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. - 1 - 1 - read-write - - - MCU_WPD - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. - 2 - 1 + 32 read-write + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + 0x3FF6D000 + + I2S1 + 33 + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x3FF49000 + + 0x0 + 0x94 + registers + + + + PIN_CTRL + 0x0 + 0x20 + - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. - 3 - 1 + CLK1 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. + 0 + 4 read-write - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + CLK2 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. 4 - 1 - read-write - - - MCU_DRV - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. - 5 - 2 - read-write - - - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. - 7 - 1 + 4 read-write - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + CLK3 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. 8 - 1 - read-write - - - FUN_IE - Input enable of the pad. 1: input enabled; 0: input disabled. - 9 - 1 - read-write - - - FUN_DRV - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. - 10 - 2 - read-write - - - MCU_SEL - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. - 12 - 3 + 4 read-write - GPIO7 - 0x64 + GPIO36 + 0x4 0x20 @@ -14785,8 +14559,8 @@ - GPIO8 - 0x68 + GPIO37 + 0x8 0x20 @@ -14869,8 +14643,8 @@ - GPIO5 - 0x6C + GPIO38 + 0xC 0x20 @@ -14953,8 +14727,8 @@ - GPIO18 - 0x70 + GPIO39 + 0x10 0x20 @@ -15037,8 +14811,8 @@ - GPIO19 - 0x74 + GPIO34 + 0x14 0x20 @@ -15121,8 +14895,8 @@ - GPIO20 - 0x78 + GPIO35 + 0x18 0x20 @@ -15205,8 +14979,8 @@ - GPIO21 - 0x7C + GPIO32 + 0x1C 0x20 @@ -15289,8 +15063,8 @@ - GPIO22 - 0x80 + GPIO33 + 0x20 0x20 @@ -15373,8 +15147,8 @@ - GPIO3 - 0x84 + GPIO25 + 0x24 0x20 @@ -15457,8 +15231,8 @@ - GPIO1 - 0x88 + GPIO26 + 0x28 0x20 @@ -15541,8 +15315,8 @@ - GPIO23 - 0x8C + GPIO27 + 0x2C 0x20 @@ -15625,8 +15399,8 @@ - GPIO24 - 0x90 + GPIO14 + 0x30 0x20 @@ -15708,4037 +15482,3611 @@ - - - - LEDC - LED Control PWM (Pulse Width Modulation) - LEDC - 0x3FF59000 - - 0x0 - 0x198 - registers - - - LEDC - 43 - - - TIMER1 - 56 - - - TIMER2 - 57 - - - HSCH0_CONF0 - 0x0 + GPIO12 + 0x34 0x20 - TIMER_SEL_HSCH0 - There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 read-write - SIG_OUT_EN_HSCH0 - This is the output enable control bit for high speed channel0 - 2 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 1 read-write - IDLE_LV_HSCH0 - This bit is used to control the output value when high speed channel0 is off. - 3 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 1 read-write - CLK_EN - This bit is clock gating control signal. when software config LED_PWM internal registers it controls the register clock. - 31 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - - - - HSCH0_HPOINT - 0x4 - 0x20 - - HPOINT_HSCH0 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0] - 0 - 20 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - - - - HSCH0_DUTY - 0x8 - 0x20 - - DUTY_HSCH0 - This register represents the current duty of the output signal for high speed channel0. - 0 - 25 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - - - - HSCH0_CONF1 - 0xC - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH0 - This register controls the increase or decrease step scale for high speed channel0. - 0 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_CYCLE_HSCH0 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. - 10 - 10 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 read-write - DUTY_NUM_HSCH0 - This register is used to control the num of increased or decreased times for high speed channel0. - 20 - 10 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DUTY_INC_HSCH0 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. - 30 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - DUTY_START_HSCH0 - When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware. - 31 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH0_DUTY_R - 0x10 - 0x20 - - - HSCH1_CONF0 - 0x14 + GPIO13 + 0x38 0x20 - TIMER_SEL_HSCH1 - There are four high speed timers the two bits are used to select one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - SIG_OUT_EN_HSCH1 - This is the output enable control bit for high speed channel1 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write - IDLE_LV_HSCH1 - This bit is used to control the output value when high speed channel1 is off. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write - - - - HSCH1_HPOINT - 0x18 - 0x20 - - HPOINT_HSCH1 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel1 has reached reg_hpoint_hsch1[19:0] - 0 - 20 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - - - - HSCH1_DUTY - 0x1C - 0x20 - - DUTY_HSCH1 - This register represents the current duty of the output signal for high speed channel1. - 0 - 25 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - - - - HSCH1_CONF1 - 0x20 - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH1 - This register controls the increase or decrease step scale for high speed channel1. - 0 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_CYCLE_HSCH1 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch1 cycles for high speed channel1. - 10 - 10 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 read-write - DUTY_NUM_HSCH1 - This register is used to control the num of increased or decreased times for high speed channel1. - 20 - 10 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DUTY_INC_HSCH1 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel1. - 30 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - DUTY_START_HSCH1 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH1_DUTY_R - 0x24 - 0x20 - - - HSCH2_CONF0 - 0x28 + GPIO15 + 0x3C 0x20 - TIMER_SEL_HSCH2 - There are four high speed timers the two bits are used to select one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - SIG_OUT_EN_HSCH2 - This is the output enable control bit for high speed channel2 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write - IDLE_LV_HSCH2 - This bit is used to control the output value when high speed channel2 is off. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write - - - - HSCH2_HPOINT - 0x2C - 0x20 - - HPOINT_HSCH2 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel2 has reached reg_hpoint_hsch2[19:0] - 0 - 20 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - - - - HSCH2_DUTY - 0x30 - 0x20 - - DUTY_HSCH2 - This register represents the current duty of the output signal for high speed channel2. - 0 - 25 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - - - - HSCH2_CONF1 - 0x34 - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH2 - This register controls the increase or decrease step scale for high speed channel2. - 0 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_CYCLE_HSCH2 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch2 cycles for high speed channel2. - 10 - 10 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 read-write - DUTY_NUM_HSCH2 - This register is used to control the num of increased or decreased times for high speed channel2. - 20 - 10 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DUTY_INC_HSCH2 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel2. - 30 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - DUTY_START_HSCH2 - When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware. - 31 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH2_DUTY_R - 0x38 - 0x20 - - - HSCH3_CONF0 - 0x3C + GPIO2 + 0x40 0x20 - TIMER_SEL_HSCH3 - There are four high speed timers the two bits are used to select one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - SIG_OUT_EN_HSCH3 - This is the output enable control bit for high speed channel3 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write - IDLE_LV_HSCH3 - This bit is used to control the output value when high speed channel3 is off. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write - - - - HSCH3_HPOINT - 0x40 - 0x20 - - HPOINT_HSCH3 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel3 has reached reg_hpoint_hsch3[19:0] - 0 - 20 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - - - - HSCH3_DUTY - 0x44 - 0x20 - - DUTY_HSCH3 - This register represents the current duty of the output signal for high speed channel3. - 0 - 25 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - - - - HSCH3_CONF1 - 0x48 - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH3 - This register controls the increase or decrease step scale for high speed channel3. - 0 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_CYCLE_HSCH3 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch3 cycles for high speed channel3. - 10 - 10 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 read-write - DUTY_NUM_HSCH3 - This register is used to control the num of increased or decreased times for high speed channel3. - 20 - 10 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DUTY_INC_HSCH3 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel3. - 30 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - DUTY_START_HSCH3 - When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware. - 31 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH3_DUTY_R - 0x4C - 0x20 - - - HSCH4_CONF0 - 0x50 + GPIO0 + 0x44 0x20 - TIMER_SEL_HSCH4 - There are four high speed timers the two bits are used to select one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - SIG_OUT_EN_HSCH4 - This is the output enable control bit for high speed channel4 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write - IDLE_LV_HSCH4 - This bit is used to control the output value when high speed channel4 is off. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write - - - - HSCH4_HPOINT - 0x54 - 0x20 - - HPOINT_HSCH4 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel4 has reached reg_hpoint_hsch4[19:0] - 0 - 20 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - - - - HSCH4_DUTY - 0x58 - 0x20 - - DUTY_HSCH4 - This register represents the current duty of the output signal for high speed channel4. - 0 - 25 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - - - - HSCH4_CONF1 - 0x5C - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH4 - This register controls the increase or decrease step scale for high speed channel4. - 0 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_CYCLE_HSCH4 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch4 cycles for high speed channel4. - 10 - 10 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 read-write - DUTY_NUM_HSCH4 - This register is used to control the num of increased or decreased times for high speed channel1. - 20 - 10 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DUTY_INC_HSCH4 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel4. - 30 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - DUTY_START_HSCH4 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH4_DUTY_R - 0x60 - 0x20 - - - HSCH5_CONF0 - 0x64 + GPIO4 + 0x48 0x20 - TIMER_SEL_HSCH5 - There are four high speed timers the two bits are used to select one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 2 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - SIG_OUT_EN_HSCH5 - This is the output enable control bit for high speed channel5. + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write - IDLE_LV_HSCH5 - This bit is used to control the output value when high speed channel5 is off. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write - - - - HSCH5_HPOINT - 0x68 - 0x20 - - HPOINT_HSCH5 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel5 has reached reg_hpoint_hsch5[19:0] - 0 - 20 - read-write - - - - - HSCH5_DUTY - 0x6C - 0x20 - - - DUTY_HSCH5 - This register represents the current duty of the output signal for high speed channel5. - 0 - 25 - read-only - - - - - HSCH5_CONF1 - 0x70 - 0x20 - 0x40000000 - - - DUTY_SCALE_HSCH5 - This register controls the increase or decrease step scale for high speed channel5. - 0 - 10 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - DUTY_CYCLE_HSCH5 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch5 cycles for high speed channel5. - 10 - 10 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 read-write - DUTY_NUM_HSCH5 - This register is used to control the num of increased or decreased times for high speed channel5. - 20 - 10 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - DUTY_INC_HSCH5 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel5. - 30 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - DUTY_START_HSCH5 - When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware. - 31 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - HSCH5_DUTY_R - 0x74 - 0x20 - - - HSCH6_CONF0 - 0x78 - 0x20 - - TIMER_SEL_HSCH6 - There are four high speed timers the two bits are used to select one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. - 0 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 2 read-write - SIG_OUT_EN_HSCH6 - This is the output enable control bit for high speed channel6 - 2 - 1 - read-write - - - IDLE_LV_HSCH6 - This bit is used to control the output value when high speed channel6 is off. - 3 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSCH6_HPOINT - 0x7C + GPIO16 + 0x4C 0x20 - HPOINT_HSCH6 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel6 has reached reg_hpoint_hsch6[19:0] + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 20 + 1 read-write - - - - HSCH6_DUTY - 0x80 - 0x20 - - - DUTY_HSCH6 - This register represents the current duty of the output signal for high speed channel6. - 0 - 25 - read-only - - - - - HSCH6_CONF1 - 0x84 - 0x20 - 0x40000000 - - DUTY_SCALE_HSCH6 - This register controls the increase or decrease step scale for high speed channel6. - 0 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_CYCLE_HSCH6 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch6 cycles for high speed channel6. - 10 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_NUM_HSCH6 - This register is used to control the num of increased or decreased times for high speed channel6. - 20 - 10 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 read-write - DUTY_INC_HSCH6 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel6. - 30 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - DUTY_START_HSCH6 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 - 1 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 read-write - - - - HSCH6_DUTY_R - 0x88 - 0x20 - - - HSCH7_CONF0 - 0x8C - 0x20 - - TIMER_SEL_HSCH7 - There are four high speed timers the two bits are used to select one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. - 0 - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - SIG_OUT_EN_HSCH7 - This is the output enable control bit for high speed channel7. - 2 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - IDLE_LV_HSCH7 - This bit is used to control the output value when high speed channel7 is off. - 3 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - HSCH7_HPOINT - 0x90 - 0x20 - - HPOINT_HSCH7 - The output value changes to high when htimerx(x=[0 3]) selected by high speed channel7 has reached reg_hpoint_hsch7[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - HSCH7_DUTY - 0x94 - 0x20 - - DUTY_HSCH7 - This register represents the current duty of the output signal for high speed channel7. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - HSCH7_CONF1 - 0x98 + GPIO17 + 0x50 0x20 - 0x40000000 - DUTY_SCALE_HSCH7 - This register controls the increase or decrease step scale for high speed channel7. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_HSCH7 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch7 cycles for high speed channel7. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_HSCH7 - This register is used to control the num of increased or decreased times for high speed channel6. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_HSCH7 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel6. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_HSCH7 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - HSCH7_DUTY_R - 0x9C - 0x20 - - - LSCH0_CONF0 - 0xA0 - 0x20 - - TIMER_SEL_LSCH0 - There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH0 - This is the output enable control bit for low speed channel0. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH0 - This bit is used to control the output value when low speed channel0 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH0 - This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH0_HPOINT - 0xA4 - 0x20 - - HPOINT_LSCH0 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH0_DUTY - 0xA8 - 0x20 - - DUTY_LSCH0 - This register represents the current duty of the output signal for low speed channel0. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH0_CONF1 - 0xAC + GPIO9 + 0x54 0x20 - 0x40000000 - DUTY_SCALE_LSCH0 - This register controls the increase or decrease step scale for low speed channel0. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH0 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH0 - This register is used to control the num of increased or decreased times for low speed channel6. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH0 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH0 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH0_DUTY_R - 0xB0 - 0x20 - - - LSCH1_CONF0 - 0xB4 - 0x20 - - TIMER_SEL_LSCH1 - There are four low speed timers the two bits are used to select one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH1 - This is the output enable control bit for low speed channel1. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH1 - This bit is used to control the output value when low speed channel1 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH1 - This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY for low speed channel1. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH1_HPOINT - 0xB8 - 0x20 - - HPOINT_LSCH1 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel1 has reached reg_hpoint_lsch1[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH1_DUTY - 0xBC - 0x20 - - DUTY_LSCH1 - This register represents the current duty of the output signal for low speed channel1. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH1_CONF1 - 0xC0 + GPIO10 + 0x58 0x20 - 0x40000000 - DUTY_SCALE_LSCH1 - This register controls the increase or decrease step scale for low speed channel1. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH1 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch1 cycles for low speed channel1. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH1 - This register is used to control the num of increased or decreased times for low speed channel1. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH1 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel1. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH1 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH1_DUTY_R - 0xC4 - 0x20 - - - LSCH2_CONF0 - 0xC8 - 0x20 - - TIMER_SEL_LSCH2 - There are four low speed timers the two bits are used to select one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH2 - This is the output enable control bit for low speed channel2. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH2 - This bit is used to control the output value when low speed channel2 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH2 - This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY for low speed channel2. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH2_HPOINT - 0xCC - 0x20 - - HPOINT_LSCH2 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel2 has reached reg_hpoint_lsch2[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH2_DUTY - 0xD0 - 0x20 - - DUTY_LSCH2 - This register represents the current duty of the output signal for low speed channel2. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH2_CONF1 - 0xD4 + GPIO11 + 0x5C 0x20 - 0x40000000 - DUTY_SCALE_LSCH2 - This register controls the increase or decrease step scale for low speed channel2. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH2 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch2 cycles for low speed channel2. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH2 - This register is used to control the num of increased or decreased times for low speed channel2. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH2 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel2. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH2 - When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH2_DUTY_R - 0xD8 - 0x20 - - - LSCH3_CONF0 - 0xDC - 0x20 - - TIMER_SEL_LSCH3 - There are four low speed timers the two bits are used to select one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH3 - This is the output enable control bit for low speed channel3. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH3 - This bit is used to control the output value when low speed channel3 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH3 - This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY for low speed channel3. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH3_HPOINT - 0xE0 - 0x20 - - HPOINT_LSCH3 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel3 has reached reg_hpoint_lsch3[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - LSCH3_DUTY - 0xE4 + GPIO6 + 0x60 0x20 - DUTY_LSCH3 - This register represents the current duty of the output signal for low speed channel3. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 25 - read-only - - - - - LSCH3_CONF1 - 0xE8 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH3 - This register controls the increase or decrease step scale for low speed channel3. - 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH3 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch3 cycles for low speed channel3. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH3 - This register is used to control the num of increased or decreased times for low speed channel3. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH3 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel3. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH3 - When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH3_DUTY_R - 0xEC - 0x20 - - - LSCH4_CONF0 - 0xF0 - 0x20 - - TIMER_SEL_LSCH4 - There are four low speed timers the two bits are used to select one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH4 - This is the output enable control bit for low speed channel4. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH4 - This bit is used to control the output value when low speed channel4 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH4 - This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY for low speed channel4. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH4_HPOINT - 0xF4 - 0x20 - - HPOINT_LSCH4 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel4 has reached reg_hpoint_lsch4[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH4_DUTY - 0xF8 - 0x20 - - DUTY_LSCH4 - This register represents the current duty of the output signal for low speed channel4. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH4_CONF1 - 0xFC + GPIO7 + 0x64 0x20 - 0x40000000 - DUTY_SCALE_LSCH4 - This register controls the increase or decrease step scale for low speed channel4. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH4 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch4 cycles for low speed channel4. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH4 - This register is used to control the num of increased or decreased times for low speed channel4. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH4 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel4. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH4 - When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH4_DUTY_R - 0x100 - 0x20 - - - LSCH5_CONF0 - 0x104 - 0x20 - - TIMER_SEL_LSCH5 - There are four low speed timers the two bits are used to select one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH5 - This is the output enable control bit for low speed channel5. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH5 - This bit is used to control the output value when low speed channel5 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH5 - This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY for low speed channel5. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH5_HPOINT - 0x108 - 0x20 - - HPOINT_LSCH5 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel5 has reached reg_hpoint_lsch5[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH5_DUTY - 0x10C - 0x20 - - DUTY_LSCH5 - This register represents the current duty of the output signal for low speed channel5. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH5_CONF1 - 0x110 + GPIO8 + 0x68 0x20 - 0x40000000 - DUTY_SCALE_LSCH5 - This register controls the increase or decrease step scale for low speed channel5. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH5 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch5 cycles for low speed channel4. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH5 - This register is used to control the num of increased or decreased times for low speed channel5. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH5 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel5. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH5 - When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH5_DUTY_R - 0x114 - 0x20 - - - LSCH6_CONF0 - 0x118 - 0x20 - - TIMER_SEL_LSCH6 - There are four low speed timers the two bits are used to select one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH6 - This is the output enable control bit for low speed channel6. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH6 - This bit is used to control the output value when low speed channel6 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH6 - This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY for low speed channel6. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH6_HPOINT - 0x11C - 0x20 - - HPOINT_LSCH6 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel6 has reached reg_hpoint_lsch6[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH6_DUTY - 0x120 - 0x20 - - DUTY_LSCH6 - This register represents the current duty of the output signal for low speed channel6. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH6_CONF1 - 0x124 + GPIO5 + 0x6C 0x20 - 0x40000000 - DUTY_SCALE_LSCH6 - This register controls the increase or decrease step scale for low speed channel6. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH6 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch6 cycles for low speed channel6. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH6 - This register is used to control the num of increased or decreased times for low speed channel6. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH6 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH6 - When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH6_DUTY_R - 0x128 - 0x20 - - - LSCH7_CONF0 - 0x12C - 0x20 - - TIMER_SEL_LSCH7 - There are four low speed timers the two bits are used to select one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. - 0 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 2 read-write - SIG_OUT_EN_LSCH7 - This is the output enable control bit for low speed channel7. - 2 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - IDLE_LV_LSCH7 - This bit is used to control the output value when low speed channel7 is off. - 3 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - PARA_UP_LSCH7 - This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY for low speed channel7. - 4 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - - - - LSCH7_HPOINT - 0x130 - 0x20 - - HPOINT_LSCH7 - The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel7 has reached reg_hpoint_lsch7[19:0] - 0 - 20 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - LSCH7_DUTY - 0x134 - 0x20 - - DUTY_LSCH7 - This register represents the current duty of the output signal for low speed channel7. - 0 - 25 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSCH7_CONF1 - 0x138 + GPIO18 + 0x70 0x20 - 0x40000000 - DUTY_SCALE_LSCH7 - This register controls the increase or decrease step scale for low speed channel7. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 10 + 1 read-write - DUTY_CYCLE_LSCH7 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch7 cycles for low speed channel7. - 10 - 10 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DUTY_NUM_LSCH7 - This register is used to control the num of increased or decreased times for low speed channel4. - 20 - 10 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - DUTY_INC_LSCH7 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel4. - 30 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - DUTY_START_LSCH7 - When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware. - 31 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - - - - LSCH7_DUTY_R - 0x13C - 0x20 - - - HSTIMER0_CONF - 0x140 - 0x20 - 0x01000000 - - HSTIMER0_DUTY_RES - This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20. - 0 - 5 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 read-write - DIV_NUM_HSTIMER0 - This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. - 5 - 18 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - HSTIMER0_PAUSE - This bit is used to pause the counter in high speed timer0 - 23 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - HSTIMER0_RST - This bit is used to reset high speed timer0 the counter will be 0 after reset. - 24 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - TICK_SEL_HSTIMER0 - This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick - 25 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - HSTIMER0_LIM - 31 - 5 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - HSTIMER0_VALUE - 0x144 + GPIO19 + 0x74 0x20 - HSTIMER0_CNT - software can read this register to get the current counter value in high speed timer0 + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 20 - read-only + 1 + read-write - - - - HSTIMER1_CONF - 0x148 - 0x20 - 0x01000000 - - HSTIMER1_DUTY_RES - This register controls the range of the counter in high speed timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20. - 0 - 5 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - DIV_NUM_HSTIMER1 - This register is used to configure parameter for divider in high speed timer1 the least significant eight bits represent the decimal part. + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 - 18 + 2 read-write - HSTIMER1_PAUSE - This bit is used to pause the counter in high speed timer1 - 23 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - HSTIMER1_RST - This bit is used to reset high speed timer1 the counter will be 0 after reset. - 24 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - TICK_SEL_HSTIMER1 - This bit is used to choose apb_clk or ref_tick for high speed timer1. 1'b1:apb_clk 0:ref_tick - 25 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - HSTIMER1_LIM - 31 - 5 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - HSTIMER1_VALUE - 0x14C - 0x20 - - HSTIMER1_CNT - software can read this register to get the current counter value in high speed timer1. - 0 - 20 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - HSTIMER2_CONF - 0x150 + GPIO20 + 0x78 0x20 - 0x01000000 - HSTIMER2_DUTY_RES - This register controls the range of the counter in high speed timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 5 + 1 read-write - DIV_NUM_HSTIMER2 - This register is used to configure parameter for divider in high speed timer2 the least significant eight bits represent the decimal part. - 5 - 18 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - HSTIMER2_PAUSE - This bit is used to pause the counter in high speed timer2 - 23 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 1 read-write - HSTIMER2_RST - This bit is used to reset high speed timer2 the counter will be 0 after reset. - 24 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - TICK_SEL_HSTIMER2 - This bit is used to choose apb_clk or ref_tick for high speed timer2. 1'b1:apb_clk 0:ref_tick - 25 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - HSTIMER2_LIM - 31 - 5 - read-write - - - - - HSTIMER2_VALUE - 0x154 - 0x20 - - - HSTIMER2_CNT - software can read this register to get the current counter value in high speed timer2 - 0 - 20 - read-only - - - - - HSTIMER3_CONF - 0x158 - 0x20 - 0x01000000 - - - HSTIMER3_DUTY_RES - This register controls the range of the counter in high speed timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20. - 0 - 5 - read-write - - - DIV_NUM_HSTIMER3 - This register is used to configure parameter for divider in high speed timer3 the least significant eight bits represent the decimal part. + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 - 18 + 2 read-write - HSTIMER3_PAUSE - This bit is used to pause the counter in high speed timer3 - 23 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - HSTIMER3_RST - This bit is used to reset high speed timer3 the counter will be 0 after reset. - 24 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - TICK_SEL_HSTIMER3 - This bit is used to choose apb_clk or ref_tick for high speed timer3. 1'b1:apb_clk 0:ref_tick - 25 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - HSTIMER3_LIM - 31 - 5 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - - - - HSTIMER3_VALUE - 0x15C - 0x20 - - HSTIMER3_CNT - software can read this register to get the current counter value in high speed timer3 - 0 - 20 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - LSTIMER0_CONF - 0x160 + GPIO21 + 0x7C 0x20 - 0x01000000 - LSTIMER0_DUTY_RES - This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 5 + 1 read-write - DIV_NUM_LSTIMER0 - This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. - 5 - 18 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - LSTIMER0_PAUSE - This bit is used to pause the counter in low speed timer0. - 23 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 1 read-write - LSTIMER0_RST - This bit is used to reset low speed timer0 the counter will be 0 after reset. - 24 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - TICK_SEL_LSTIMER0 - This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick - 25 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - LSTIMER0_PARA_UP - Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. - 26 - 1 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 read-write - LSTIMER0_LIM - 31 - 5 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 read-write - - - - LSTIMER0_VALUE - 0x164 - 0x20 - - LSTIMER0_CNT - software can read this register to get the current counter value in low speed timer0. - 0 - 20 - read-only + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write - - - - LSTIMER1_CONF - 0x168 - 0x20 - 0x01000000 - - LSTIMER1_DUTY_RES - This register controls the range of the counter in low speed timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20. - 0 - 5 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - DIV_NUM_LSTIMER1 - This register is used to configure parameter for divider in low speed timer1 the least significant eight bits represent the decimal part. - 5 - 18 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - LSTIMER1_PAUSE - This bit is used to pause the counter in low speed timer1. - 23 - 1 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write + + + + GPIO22 + 0x80 + 0x20 + - LSTIMER1_RST - This bit is used to reset low speed timer1 the counter will be 0 after reset. - 24 + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 1 read-write - TICK_SEL_LSTIMER1 - This bit is used to choose slow_clk or ref_tick for low speed timer1. 1'b1:slow_clk 0:ref_tick - 25 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 1 read-write - LSTIMER1_PARA_UP - Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim. - 26 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 1 read-write - LSTIMER1_LIM - 31 - 5 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 read-write - - - - LSTIMER1_VALUE - 0x16C - 0x20 - - - LSTIMER1_CNT - software can read this register to get the current counter value in low speed timer1. - 0 - 20 - read-only - - - - - LSTIMER2_CONF - 0x170 - 0x20 - 0x01000000 - - LSTIMER2_DUTY_RES - This register controls the range of the counter in low speed timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20. - 0 - 5 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 read-write - DIV_NUM_LSTIMER2 - This register is used to configure parameter for divider in low speed timer2 the least significant eight bits represent the decimal part. + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 - 18 + 2 read-write - LSTIMER2_PAUSE - This bit is used to pause the counter in low speed timer2. - 23 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - LSTIMER2_RST - This bit is used to reset low speed timer2 the counter will be 0 after reset. - 24 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - TICK_SEL_LSTIMER2 - This bit is used to choose slow_clk or ref_tick for low speed timer2. 1'b1:slow_clk 0:ref_tick - 25 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 read-write - LSTIMER2_PARA_UP - Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim. - 26 - 1 + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 read-write - LSTIMER2_LIM - 31 - 5 + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 read-write - LSTIMER2_VALUE - 0x174 + GPIO3 + 0x84 0x20 - LSTIMER2_CNT - software can read this register to get the current counter value in low speed timer2. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 - 20 - read-only + 1 + read-write - - - - LSTIMER3_CONF - 0x178 - 0x20 - 0x01000000 - - LSTIMER3_DUTY_RES - This register controls the range of the counter in low speed timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20. - 0 - 5 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 read-write - DIV_NUM_LSTIMER3 - This register is used to configure parameter for divider in low speed timer3 the least significant eight bits represent the decimal part. - 5 - 18 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 read-write - LSTIMER3_PAUSE - This bit is used to pause the counter in low speed timer3. - 23 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 read-write - LSTIMER3_RST - This bit is used to reset low speed timer3 the counter will be 0 after reset. - 24 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 read-write - TICK_SEL_LSTIMER3 - This bit is used to choose slow_clk or ref_tick for low speed timer3. 1'b1:slow_clk 0:ref_tick - 25 + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 read-write - LSTIMER3_PARA_UP - Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim. - 26 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 read-write - LSTIMER3_LIM - 31 - 5 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 read-write - - - - LSTIMER3_VALUE - 0x17C - 0x20 - - LSTIMER3_CNT - software can read this register to get the current counter value in low speed timer3. - 0 - 20 - read-only + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - INT_RAW - 0x180 + GPIO1 + 0x88 0x20 - HSTIMER0_OVF_INT_RAW - The interrupt raw bit for high speed channel0 counter overflow. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 - read-only + read-write - HSTIMER1_OVF_INT_RAW - The interrupt raw bit for high speed channel1 counter overflow. + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 - read-only + read-write - HSTIMER2_OVF_INT_RAW - The interrupt raw bit for high speed channel2 counter overflow. + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 - read-only + read-write - HSTIMER3_OVF_INT_RAW - The interrupt raw bit for high speed channel3 counter overflow. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 - read-only + read-write - LSTIMER0_OVF_INT_RAW - The interrupt raw bit for low speed channel0 counter overflow. + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 - read-only + read-write - LSTIMER1_OVF_INT_RAW - The interrupt raw bit for low speed channel1 counter overflow. + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 - 1 - read-only - - - LSTIMER2_OVF_INT_RAW - The interrupt raw bit for low speed channel2 counter overflow. - 6 - 1 - read-only + 2 + read-write - LSTIMER3_OVF_INT_RAW - The interrupt raw bit for low speed channel3 counter overflow. + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 - read-only + read-write - DUTY_CHNG_END_HSCH0_INT_RAW - The interrupt raw bit for high speed channel 0 duty change done. + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 - read-only + read-write - DUTY_CHNG_END_HSCH1_INT_RAW - The interrupt raw bit for high speed channel 1 duty change done. + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 - read-only + read-write - DUTY_CHNG_END_HSCH2_INT_RAW - The interrupt raw bit for high speed channel 2 duty change done. + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 - 1 - read-only - - - DUTY_CHNG_END_HSCH3_INT_RAW - The interrupt raw bit for high speed channel 3 duty change done. - 11 - 1 - read-only + 2 + read-write - DUTY_CHNG_END_HSCH4_INT_RAW - The interrupt raw bit for high speed channel 4 duty change done. + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 - 1 - read-only + 3 + read-write + + + + GPIO23 + 0x8C + 0x20 + - DUTY_CHNG_END_HSCH5_INT_RAW - The interrupt raw bit for high speed channel 5 duty change done. - 13 + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 1 - read-only + read-write - DUTY_CHNG_END_HSCH6_INT_RAW - The interrupt raw bit for high speed channel 6 duty change done. - 14 + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 1 - read-only + read-write - DUTY_CHNG_END_HSCH7_INT_RAW - The interrupt raw bit for high speed channel 7 duty change done. - 15 + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 1 - read-only + read-write - DUTY_CHNG_END_LSCH0_INT_RAW - The interrupt raw bit for low speed channel 0 duty change done. - 16 + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 1 - read-only + read-write - DUTY_CHNG_END_LSCH1_INT_RAW - The interrupt raw bit for low speed channel 1 duty change done. - 17 + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 1 - read-only + read-write - DUTY_CHNG_END_LSCH2_INT_RAW - The interrupt raw bit for low speed channel 2 duty change done. - 18 - 1 - read-only + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write - DUTY_CHNG_END_LSCH3_INT_RAW - The interrupt raw bit for low speed channel 3 duty change done. - 19 + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 1 - read-only + read-write - DUTY_CHNG_END_LSCH4_INT_RAW - The interrupt raw bit for low speed channel 4 duty change done. - 20 + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 1 - read-only + read-write - DUTY_CHNG_END_LSCH5_INT_RAW - The interrupt raw bit for low speed channel 5 duty change done. - 21 + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 1 - read-only + read-write - DUTY_CHNG_END_LSCH6_INT_RAW - The interrupt raw bit for low speed channel 6 duty change done. - 22 - 1 - read-only + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write - DUTY_CHNG_END_LSCH7_INT_RAW - The interrupt raw bit for low speed channel 7 duty change done. - 23 - 1 - read-only + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write - INT_ST - 0x184 + GPIO24 + 0x90 0x20 - HSTIMER0_OVF_INT_ST - The interrupt status bit for high speed channel0 counter overflow event. + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 - read-only + read-write - HSTIMER1_OVF_INT_ST - The interrupt status bit for high speed channel1 counter overflow event. + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 - read-only + read-write - HSTIMER2_OVF_INT_ST - The interrupt status bit for high speed channel2 counter overflow event. + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 - read-only + read-write - HSTIMER3_OVF_INT_ST - The interrupt status bit for high speed channel3 counter overflow event. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 - read-only + read-write - LSTIMER0_OVF_INT_ST - The interrupt status bit for low speed channel0 counter overflow event. + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 - read-only + read-write - LSTIMER1_OVF_INT_ST - The interrupt status bit for low speed channel1 counter overflow event. + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 - 1 - read-only - - - LSTIMER2_OVF_INT_ST - The interrupt status bit for low speed channel2 counter overflow event. - 6 - 1 - read-only + 2 + read-write - LSTIMER3_OVF_INT_ST - The interrupt status bit for low speed channel3 counter overflow event. + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 - read-only + read-write - DUTY_CHNG_END_HSCH0_INT_ST - The interrupt status bit for high speed channel 0 duty change done event. + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 - read-only + read-write - DUTY_CHNG_END_HSCH1_INT_ST - The interrupt status bit for high speed channel 1 duty change done event. + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 - read-only + read-write - DUTY_CHNG_END_HSCH2_INT_ST - The interrupt status bit for high speed channel 2 duty change done event. + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 - 1 - read-only - - - DUTY_CHNG_END_HSCH3_INT_ST - The interrupt status bit for high speed channel 3 duty change done event. - 11 - 1 - read-only + 2 + read-write - DUTY_CHNG_END_HSCH4_INT_ST - The interrupt status bit for high speed channel 4 duty change done event. + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 - 1 - read-only + 3 + read-write + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x3FF59000 + + 0x0 + 0x198 + registers + + + LEDC + 43 + + + TIMER1 + 56 + + + TIMER2 + 57 + + + + 8 + 0x14 + 0-7 + HSCH%s_CONF0 + 0x0 + 0x20 + - DUTY_CHNG_END_HSCH5_INT_ST - The interrupt status bit for high speed channel 5 duty change done event. - 13 - 1 - read-only + TIMER_SEL + There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + 0 + 2 + read-write - DUTY_CHNG_END_HSCH6_INT_ST - The interrupt status bit for high speed channel 6 duty change done event. - 14 + SIG_OUT_EN + This is the output enable control bit for high speed channel0 + 2 1 - read-only + read-write - DUTY_CHNG_END_HSCH7_INT_ST - The interrupt status bit for high speed channel 7 duty change done event. - 15 + IDLE_LV + This bit is used to control the output value when high speed channel0 is off. + 3 1 - read-only + read-write + + + + 8 + 0x14 + 0-7 + HSCH%s_HPOINT + 0x4 + 0x20 + - DUTY_CHNG_END_LSCH0_INT_ST - The interrupt status bit for low speed channel 0 duty change done event. - 16 - 1 - read-only + HPOINT + The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0] + 0 + 20 + read-write + + + + 8 + 0x14 + 0-7 + HSCH%s_DUTY + 0x8 + 0x20 + - DUTY_CHNG_END_LSCH1_INT_ST - The interrupt status bit for low speed channel 1 duty change done event. - 17 - 1 - read-only + DUTY + This register represents the current duty of the output signal for high speed channel0. + 0 + 25 + read-write + + + + 8 + 0x14 + 0-7 + HSCH%s_CONF1 + 0xC + 0x20 + 0x40000000 + - DUTY_CHNG_END_LSCH2_INT_ST - The interrupt status bit for low speed channel 2 duty change done event. - 18 - 1 - read-only + DUTY_SCALE + This register controls the increase or decrease step scale for high speed channel0. + 0 + 10 + read-write - DUTY_CHNG_END_LSCH3_INT_ST - The interrupt status bit for low speed channel 3 duty change done event. - 19 - 1 - read-only + DUTY_CYCLE + This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. + 10 + 10 + read-write - DUTY_CHNG_END_LSCH4_INT_ST - The interrupt status bit for low speed channel 4 duty change done event. + DUTY_NUM + This register is used to control the num of increased or decreased times for high speed channel0. 20 - 1 - read-only + 10 + read-write - DUTY_CHNG_END_LSCH5_INT_ST - The interrupt status bit for low speed channel 5 duty change done event. - 21 + DUTY_INC + This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. + 30 1 - read-only + read-write - DUTY_CHNG_END_LSCH6_INT_ST - The interrupt status bit for low speed channel 6 duty change done event. - 22 + DUTY_START + When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware. + 31 1 - read-only + read-write + + + + 8 + 0x14 + 0-7 + HSCH%s_DUTY_R + 0x10 + 0x20 + - DUTY_CHNG_END_LSCH7_INT_ST - The interrupt status bit for low speed channel 7 duty change done event - 23 - 1 + DUTY_R + This register represents the current duty cycle of the output signal for high-speed channel %s + 0 + 25 read-only - INT_ENA - 0x188 + 8 + 0x14 + 0-7 + LSCH%s_CONF0 + 0xA0 0x20 - HSTIMER0_OVF_INT_ENA - The interrupt enable bit for high speed channel0 counter overflow interrupt. + TIMER_SEL + There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. 0 - 1 - read-write - - - HSTIMER1_OVF_INT_ENA - The interrupt enable bit for high speed channel1 counter overflow interrupt. - 1 - 1 + 2 read-write - HSTIMER2_OVF_INT_ENA - The interrupt enable bit for high speed channel2 counter overflow interrupt. + SIG_OUT_EN + This is the output enable control bit for low speed channel0. 2 1 read-write - HSTIMER3_OVF_INT_ENA - The interrupt enable bit for high speed channel3 counter overflow interrupt. + IDLE_LV + This bit is used to control the output value when low speed channel0 is off. 3 1 read-write - LSTIMER0_OVF_INT_ENA - The interrupt enable bit for low speed channel0 counter overflow interrupt. + PARA_UP + This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. 4 1 read-write + + + + 8 + 0x14 + 0-7 + LSCH%s_HPOINT + 0xA4 + 0x20 + - LSTIMER1_OVF_INT_ENA - The interrupt enable bit for low speed channel1 counter overflow interrupt. - 5 - 1 + HPOINT + The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0] + 0 + 20 read-write + + + + 8 + 0x14 + 0-7 + LSCH%s_DUTY + 0xA8 + 0x20 + read-write + - LSTIMER2_OVF_INT_ENA - The interrupt enable bit for low speed channel2 counter overflow interrupt. - 6 - 1 + DUTY + This register represents the current duty of the output signal for low speed channel0. + 0 + 25 read-write + + + + 8 + 0x14 + 0-7 + LSCH%s_CONF1 + 0xAC + 0x20 + 0x40000000 + - LSTIMER3_OVF_INT_ENA - The interrupt enable bit for low speed channel3 counter overflow interrupt. - 7 - 1 + DUTY_SCALE + This register controls the increase or decrease step scale for low speed channel0. + 0 + 10 read-write - DUTY_CHNG_END_HSCH0_INT_ENA - The interrupt enable bit for high speed channel 0 duty change done interrupt. - 8 - 1 + DUTY_CYCLE + This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. + 10 + 10 read-write - DUTY_CHNG_END_HSCH1_INT_ENA - The interrupt enable bit for high speed channel 1 duty change done interrupt. - 9 - 1 + DUTY_NUM + This register is used to control the num of increased or decreased times for low speed channel6. + 20 + 10 read-write - DUTY_CHNG_END_HSCH2_INT_ENA - The interrupt enable bit for high speed channel 2 duty change done interrupt. - 10 + DUTY_INC + This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. + 30 1 read-write - DUTY_CHNG_END_HSCH3_INT_ENA - The interrupt enable bit for high speed channel 3 duty change done interrupt. - 11 + DUTY_START + When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. + 31 1 read-write + + + + 8 + 0x14 + 0-7 + LSCH%s_DUTY_R + 0xB0 + 0x20 + - DUTY_CHNG_END_HSCH4_INT_ENA - The interrupt enable bit for high speed channel 4 duty change done interrupt. - 12 - 1 - read-write + DUTY_R + This register represents the current duty cycle of the output signal for low-speed channel %s + 0 + 25 + read-only + + + + 4 + 0x8 + 0-3 + HSTIMER%s_CONF + 0x140 + 0x20 + 0x01000000 + - DUTY_CHNG_END_HSCH5_INT_ENA - The interrupt enable bit for high speed channel 5 duty change done interrupt. - 13 - 1 + DUTY_RES + This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20. + 0 + 5 read-write - DUTY_CHNG_END_HSCH6_INT_ENA - The interrupt enable bit for high speed channel 6 duty change done interrupt. - 14 - 1 + DIV_NUM + This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. + 5 + 18 read-write - DUTY_CHNG_END_HSCH7_INT_ENA - The interrupt enable bit for high speed channel 7 duty change done interrupt. - 15 + PAUSE + This bit is used to pause the counter in high speed timer0 + 23 1 read-write - DUTY_CHNG_END_LSCH0_INT_ENA - The interrupt enable bit for low speed channel 0 duty change done interrupt. - 16 + RST + This bit is used to reset high speed timer0 the counter will be 0 after reset. + 24 1 read-write - DUTY_CHNG_END_LSCH1_INT_ENA - The interrupt enable bit for low speed channel 1 duty change done interrupt. - 17 + TICK_SEL + This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick + 25 1 read-write + + + + 4 + 0x8 + 0-3 + HSTIMER%s_VALUE + 0x144 + 0x20 + - DUTY_CHNG_END_LSCH2_INT_ENA - The interrupt enable bit for low speed channel 2 duty change done interrupt. - 18 - 1 + CNT + software can read this register to get the current counter value in high speed timer0 + 0 + 20 + read-only + + + + + 4 + 0x8 + 0-3 + LSTIMER%s_CONF + 0x160 + 0x20 + 0x01000000 + + + DUTY_RES + This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20. + 0 + 5 read-write - DUTY_CHNG_END_LSCH3_INT_ENA - The interrupt enable bit for low speed channel 3 duty change done interrupt. - 19 - 1 + DIV_NUM + This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. + 5 + 18 read-write - DUTY_CHNG_END_LSCH4_INT_ENA - The interrupt enable bit for low speed channel 4 duty change done interrupt. - 20 + PAUSE + This bit is used to pause the counter in low speed timer0. + 23 1 read-write - DUTY_CHNG_END_LSCH5_INT_ENA - The interrupt enable bit for low speed channel 5 duty change done interrupt. - 21 + RST + This bit is used to reset low speed timer0 the counter will be 0 after reset. + 24 1 read-write - DUTY_CHNG_END_LSCH6_INT_ENA - The interrupt enable bit for low speed channel 6 duty change done interrupt. - 22 + TICK_SEL + This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick + 25 1 read-write - DUTY_CHNG_END_LSCH7_INT_ENA - The interrupt enable bit for low speed channel 7 duty change done interrupt. - 23 + PARA_UP + Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. + 26 1 read-write - INT_CLR - 0x18C + 4 + 0x8 + 0-3 + LSTIMER%s_VALUE + 0x164 0x20 - HSTIMER0_OVF_INT_CLR - Set this bit to clear high speed channel0 counter overflow interrupt. + CNT + software can read this register to get the current counter value in low speed timer0. + 0 + 20 + read-only + + + + + INT_RAW + 0x180 + 0x20 + + + HSTIMER0_OVF_INT_RAW + The interrupt raw bit for high speed channel0 counter overflow. 0 1 - write-only + read-only - HSTIMER1_OVF_INT_CLR - Set this bit to clear high speed channel1 counter overflow interrupt. + HSTIMER1_OVF_INT_RAW + The interrupt raw bit for high speed channel1 counter overflow. 1 1 - write-only + read-only - HSTIMER2_OVF_INT_CLR - Set this bit to clear high speed channel2 counter overflow interrupt. + HSTIMER2_OVF_INT_RAW + The interrupt raw bit for high speed channel2 counter overflow. 2 1 - write-only + read-only - HSTIMER3_OVF_INT_CLR - Set this bit to clear high speed channel3 counter overflow interrupt. + HSTIMER3_OVF_INT_RAW + The interrupt raw bit for high speed channel3 counter overflow. 3 1 - write-only + read-only - LSTIMER0_OVF_INT_CLR - Set this bit to clear low speed channel0 counter overflow interrupt. + LSTIMER0_OVF_INT_RAW + The interrupt raw bit for low speed channel0 counter overflow. 4 1 - write-only + read-only - LSTIMER1_OVF_INT_CLR - Set this bit to clear low speed channel1 counter overflow interrupt. + LSTIMER1_OVF_INT_RAW + The interrupt raw bit for low speed channel1 counter overflow. 5 1 - write-only + read-only - LSTIMER2_OVF_INT_CLR - Set this bit to clear low speed channel2 counter overflow interrupt. + LSTIMER2_OVF_INT_RAW + The interrupt raw bit for low speed channel2 counter overflow. 6 1 - write-only + read-only - LSTIMER3_OVF_INT_CLR - Set this bit to clear low speed channel3 counter overflow interrupt. + LSTIMER3_OVF_INT_RAW + The interrupt raw bit for low speed channel3 counter overflow. 7 1 - write-only + read-only - DUTY_CHNG_END_HSCH0_INT_CLR - Set this bit to clear high speed channel 0 duty change done interrupt. + DUTY_CHNG_END_HSCH0_INT_RAW + The interrupt raw bit for high speed channel 0 duty change done. 8 1 - write-only + read-only - DUTY_CHNG_END_HSCH1_INT_CLR - Set this bit to clear high speed channel 1 duty change done interrupt. + DUTY_CHNG_END_HSCH1_INT_RAW + The interrupt raw bit for high speed channel 1 duty change done. 9 1 - write-only + read-only - DUTY_CHNG_END_HSCH2_INT_CLR - Set this bit to clear high speed channel 2 duty change done interrupt. + DUTY_CHNG_END_HSCH2_INT_RAW + The interrupt raw bit for high speed channel 2 duty change done. 10 1 - write-only + read-only - DUTY_CHNG_END_HSCH3_INT_CLR - Set this bit to clear high speed channel 3 duty change done interrupt. + DUTY_CHNG_END_HSCH3_INT_RAW + The interrupt raw bit for high speed channel 3 duty change done. 11 1 - write-only + read-only - DUTY_CHNG_END_HSCH4_INT_CLR - Set this bit to clear high speed channel 4 duty change done interrupt. + DUTY_CHNG_END_HSCH4_INT_RAW + The interrupt raw bit for high speed channel 4 duty change done. 12 1 - write-only + read-only - DUTY_CHNG_END_HSCH5_INT_CLR - Set this bit to clear high speed channel 5 duty change done interrupt. + DUTY_CHNG_END_HSCH5_INT_RAW + The interrupt raw bit for high speed channel 5 duty change done. 13 1 - write-only + read-only - DUTY_CHNG_END_HSCH6_INT_CLR - Set this bit to clear high speed channel 6 duty change done interrupt. + DUTY_CHNG_END_HSCH6_INT_RAW + The interrupt raw bit for high speed channel 6 duty change done. 14 1 - write-only + read-only - DUTY_CHNG_END_HSCH7_INT_CLR - Set this bit to clear high speed channel 7 duty change done interrupt. + DUTY_CHNG_END_HSCH7_INT_RAW + The interrupt raw bit for high speed channel 7 duty change done. 15 1 - write-only + read-only - DUTY_CHNG_END_LSCH0_INT_CLR - Set this bit to clear low speed channel 0 duty change done interrupt. + DUTY_CHNG_END_LSCH0_INT_RAW + The interrupt raw bit for low speed channel 0 duty change done. 16 1 - write-only + read-only - DUTY_CHNG_END_LSCH1_INT_CLR - Set this bit to clear low speed channel 1 duty change done interrupt. + DUTY_CHNG_END_LSCH1_INT_RAW + The interrupt raw bit for low speed channel 1 duty change done. 17 1 - write-only + read-only - DUTY_CHNG_END_LSCH2_INT_CLR - Set this bit to clear low speed channel 2 duty change done interrupt. + DUTY_CHNG_END_LSCH2_INT_RAW + The interrupt raw bit for low speed channel 2 duty change done. 18 1 - write-only + read-only - DUTY_CHNG_END_LSCH3_INT_CLR - Set this bit to clear low speed channel 3 duty change done interrupt. + DUTY_CHNG_END_LSCH3_INT_RAW + The interrupt raw bit for low speed channel 3 duty change done. 19 1 - write-only + read-only - DUTY_CHNG_END_LSCH4_INT_CLR - Set this bit to clear low speed channel 4 duty change done interrupt. + DUTY_CHNG_END_LSCH4_INT_RAW + The interrupt raw bit for low speed channel 4 duty change done. 20 1 - write-only + read-only - DUTY_CHNG_END_LSCH5_INT_CLR - Set this bit to clear low speed channel 5 duty change done interrupt. + DUTY_CHNG_END_LSCH5_INT_RAW + The interrupt raw bit for low speed channel 5 duty change done. 21 1 - write-only + read-only - DUTY_CHNG_END_LSCH6_INT_CLR - Set this bit to clear low speed channel 6 duty change done interrupt. + DUTY_CHNG_END_LSCH6_INT_RAW + The interrupt raw bit for low speed channel 6 duty change done. 22 1 - write-only + read-only - DUTY_CHNG_END_LSCH7_INT_CLR - Set this bit to clear low speed channel 7 duty change done interrupt. + DUTY_CHNG_END_LSCH7_INT_RAW + The interrupt raw bit for low speed channel 7 duty change done. 23 1 - write-only - - - - - CONF - 0x190 - 0x20 - - - APB_CLK_SEL - This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz - 0 - 1 - read-write - - - - - DATE - 0x1FC - 0x20 - 0x16031700 - - - DATE - This register represents the version . - 0 - 32 - read-write - - - - - - - PWM0 - Motor Control Pulse-Width Modulation - MCPWM - 0x3FF5E000 - - 0x0 - 0x128 - registers - - - PWM0 - 39 - - - - CLK_CFG - 0x0 - 0x20 - - - CLK_PRESCALE - 0 - 8 - read-write - - - - - TIMER0_CFG0 - 0x4 - 0x20 - 0x0000FF00 - - - TIMER0_PRESCALE - 0 - 8 - read-write - - - TIMER0_PERIOD - 8 - 16 - read-write - - - TIMER0_PERIOD_UPMETHOD - 24 - 2 - read-write - - - - - TIMER0_CFG1 - 0x8 - 0x20 - - - TIMER0_START - 0 - 3 - read-write - - - TIMER0_MOD - 3 - 2 - read-write + read-only - TIMER0_SYNC - 0xC + INT_ST + 0x184 0x20 - TIMER0_SYNCI_EN + HSTIMER0_OVF_INT_ST + The interrupt status bit for high speed channel0 counter overflow event. 0 1 - read-write + read-only - SW + HSTIMER1_OVF_INT_ST + The interrupt status bit for high speed channel1 counter overflow event. 1 1 - read-write + read-only - TIMER0_SYNCO_SEL + HSTIMER2_OVF_INT_ST + The interrupt status bit for high speed channel2 counter overflow event. 2 - 2 - read-write + 1 + read-only - TIMER0_PHASE - 4 - 16 - read-write + HSTIMER3_OVF_INT_ST + The interrupt status bit for high speed channel3 counter overflow event. + 3 + 1 + read-only - TIMER0_PHASE_DIRECTION - 20 + LSTIMER0_OVF_INT_ST + The interrupt status bit for low speed channel0 counter overflow event. + 4 1 - read-write + read-only - - - - TIMER0_STATUS - 0x10 - 0x20 - - TIMER0_VALUE - 0 - 16 + LSTIMER1_OVF_INT_ST + The interrupt status bit for low speed channel1 counter overflow event. + 5 + 1 read-only - TIMER0_DIRECTION - 16 + LSTIMER2_OVF_INT_ST + The interrupt status bit for low speed channel2 counter overflow event. + 6 1 read-only - - - - TIMER1_CFG0 - 0x14 - 0x20 - 0x0000FF00 - - TIMER1_PRESCALE - 0 - 8 - read-write + LSTIMER3_OVF_INT_ST + The interrupt status bit for low speed channel3 counter overflow event. + 7 + 1 + read-only - TIMER1_PERIOD + DUTY_CHNG_END_HSCH0_INT_ST + The interrupt status bit for high speed channel 0 duty change done event. 8 - 16 - read-write + 1 + read-only - TIMER1_PERIOD_UPMETHOD - 24 - 2 - read-write + DUTY_CHNG_END_HSCH1_INT_ST + The interrupt status bit for high speed channel 1 duty change done event. + 9 + 1 + read-only - - - - TIMER1_CFG1 - 0x18 - 0x20 - - TIMER1_START - 0 - 3 - read-write + DUTY_CHNG_END_HSCH2_INT_ST + The interrupt status bit for high speed channel 2 duty change done event. + 10 + 1 + read-only - TIMER1_MOD - 3 - 2 - read-write + DUTY_CHNG_END_HSCH3_INT_ST + The interrupt status bit for high speed channel 3 duty change done event. + 11 + 1 + read-only - - - - TIMER1_SYNC - 0x1C - 0x20 - - TIMER1_SYNCI_EN - 0 + DUTY_CHNG_END_HSCH4_INT_ST + The interrupt status bit for high speed channel 4 duty change done event. + 12 1 - read-write + read-only - SW - 1 + DUTY_CHNG_END_HSCH5_INT_ST + The interrupt status bit for high speed channel 5 duty change done event. + 13 1 - read-write + read-only - TIMER1_SYNCO_SEL - 2 - 2 - read-write + DUTY_CHNG_END_HSCH6_INT_ST + The interrupt status bit for high speed channel 6 duty change done event. + 14 + 1 + read-only - TIMER1_PHASE - 4 - 16 - read-write + DUTY_CHNG_END_HSCH7_INT_ST + The interrupt status bit for high speed channel 7 duty change done event. + 15 + 1 + read-only - TIMER1_PHASE_DIRECTION - 20 + DUTY_CHNG_END_LSCH0_INT_ST + The interrupt status bit for low speed channel 0 duty change done event. + 16 1 - read-write + read-only - - - - TIMER1_STATUS - 0x20 - 0x20 - - TIMER1_VALUE - 0 - 16 + DUTY_CHNG_END_LSCH1_INT_ST + The interrupt status bit for low speed channel 1 duty change done event. + 17 + 1 read-only - TIMER1_DIRECTION - 16 + DUTY_CHNG_END_LSCH2_INT_ST + The interrupt status bit for low speed channel 2 duty change done event. + 18 1 read-only - - - - TIMER2_CFG0 - 0x24 - 0x20 - 0x0000FF00 - - TIMER2_PRESCALE - 0 - 8 - read-write + DUTY_CHNG_END_LSCH3_INT_ST + The interrupt status bit for low speed channel 3 duty change done event. + 19 + 1 + read-only - TIMER2_PERIOD - 8 - 16 - read-write + DUTY_CHNG_END_LSCH4_INT_ST + The interrupt status bit for low speed channel 4 duty change done event. + 20 + 1 + read-only - TIMER2_PERIOD_UPMETHOD - 24 - 2 - read-write + DUTY_CHNG_END_LSCH5_INT_ST + The interrupt status bit for low speed channel 5 duty change done event. + 21 + 1 + read-only - - - - TIMER2_CFG1 - 0x28 - 0x20 - - TIMER2_START - 0 - 3 - read-write + DUTY_CHNG_END_LSCH6_INT_ST + The interrupt status bit for low speed channel 6 duty change done event. + 22 + 1 + read-only - TIMER2_MOD - 3 - 2 - read-write + DUTY_CHNG_END_LSCH7_INT_ST + The interrupt status bit for low speed channel 7 duty change done event + 23 + 1 + read-only - TIMER2_SYNC - 0x2C + INT_ENA + 0x188 0x20 - TIMER2_SYNCI_EN + HSTIMER0_OVF_INT_ENA + The interrupt enable bit for high speed channel0 counter overflow interrupt. 0 1 read-write - SW + HSTIMER1_OVF_INT_ENA + The interrupt enable bit for high speed channel1 counter overflow interrupt. 1 1 read-write - TIMER2_SYNCO_SEL + HSTIMER2_OVF_INT_ENA + The interrupt enable bit for high speed channel2 counter overflow interrupt. 2 - 2 + 1 read-write - TIMER2_PHASE - 4 - 16 + HSTIMER3_OVF_INT_ENA + The interrupt enable bit for high speed channel3 counter overflow interrupt. + 3 + 1 read-write - TIMER2_PHASE_DIRECTION - 20 + LSTIMER0_OVF_INT_ENA + The interrupt enable bit for low speed channel0 counter overflow interrupt. + 4 1 read-write - - - - TIMER2_STATUS - 0x30 - 0x20 - - - TIMER2_VALUE - 0 - 16 - read-only - - TIMER2_DIRECTION - 16 + LSTIMER1_OVF_INT_ENA + The interrupt enable bit for low speed channel1 counter overflow interrupt. + 5 1 - read-only + read-write - - - - TIMER_SYNCI_CFG - 0x34 - 0x20 - - TIMER0_SYNCISEL - 0 - 3 + LSTIMER2_OVF_INT_ENA + The interrupt enable bit for low speed channel2 counter overflow interrupt. + 6 + 1 read-write - TIMER1_SYNCISEL - 3 - 3 + LSTIMER3_OVF_INT_ENA + The interrupt enable bit for low speed channel3 counter overflow interrupt. + 7 + 1 read-write - TIMER2_SYNCISEL - 6 - 3 + DUTY_CHNG_END_HSCH0_INT_ENA + The interrupt enable bit for high speed channel 0 duty change done interrupt. + 8 + 1 read-write - EXTERNAL_SYNCI0_INVERT + DUTY_CHNG_END_HSCH1_INT_ENA + The interrupt enable bit for high speed channel 1 duty change done interrupt. 9 1 read-write - EXTERNAL_SYNCI1_INVERT + DUTY_CHNG_END_HSCH2_INT_ENA + The interrupt enable bit for high speed channel 2 duty change done interrupt. 10 1 read-write - EXTERNAL_SYNCI2_INVERT + DUTY_CHNG_END_HSCH3_INT_ENA + The interrupt enable bit for high speed channel 3 duty change done interrupt. 11 1 read-write - - - - OPERATOR_TIMERSEL - 0x38 - 0x20 - - OPERATOR0_TIMERSEL - 0 - 2 + DUTY_CHNG_END_HSCH4_INT_ENA + The interrupt enable bit for high speed channel 4 duty change done interrupt. + 12 + 1 read-write - OPERATOR1_TIMERSEL - 2 - 2 + DUTY_CHNG_END_HSCH5_INT_ENA + The interrupt enable bit for high speed channel 5 duty change done interrupt. + 13 + 1 read-write - OPERATOR2_TIMERSEL - 4 - 2 + DUTY_CHNG_END_HSCH6_INT_ENA + The interrupt enable bit for high speed channel 6 duty change done interrupt. + 14 + 1 read-write - - - - GEN0_STMP_CFG - 0x3C - 0x20 - - GEN0_A_UPMETHOD - 0 - 4 + DUTY_CHNG_END_HSCH7_INT_ENA + The interrupt enable bit for high speed channel 7 duty change done interrupt. + 15 + 1 read-write - GEN0_B_UPMETHOD - 4 - 4 + DUTY_CHNG_END_LSCH0_INT_ENA + The interrupt enable bit for low speed channel 0 duty change done interrupt. + 16 + 1 read-write - GEN0_A_SHDW_FULL - 8 + DUTY_CHNG_END_LSCH1_INT_ENA + The interrupt enable bit for low speed channel 1 duty change done interrupt. + 17 1 read-write - GEN0_B_SHDW_FULL - 9 + DUTY_CHNG_END_LSCH2_INT_ENA + The interrupt enable bit for low speed channel 2 duty change done interrupt. + 18 1 read-write - - - - GEN0_TSTMP_A - 0x40 - 0x20 - - GEN0_A - 0 - 16 + DUTY_CHNG_END_LSCH3_INT_ENA + The interrupt enable bit for low speed channel 3 duty change done interrupt. + 19 + 1 read-write - - - - GEN0_TSTMP_B - 0x44 - 0x20 - - GEN0_B - 0 - 16 + DUTY_CHNG_END_LSCH4_INT_ENA + The interrupt enable bit for low speed channel 4 duty change done interrupt. + 20 + 1 read-write - - - - GEN0_CFG0 - 0x48 - 0x20 - - GEN0_CFG_UPMETHOD - 0 - 4 + DUTY_CHNG_END_LSCH5_INT_ENA + The interrupt enable bit for low speed channel 5 duty change done interrupt. + 21 + 1 read-write - GEN0_T0_SEL - 4 - 3 + DUTY_CHNG_END_LSCH6_INT_ENA + The interrupt enable bit for low speed channel 6 duty change done interrupt. + 22 + 1 read-write - GEN0_T1_SEL - 7 - 3 + DUTY_CHNG_END_LSCH7_INT_ENA + The interrupt enable bit for low speed channel 7 duty change done interrupt. + 23 + 1 read-write - GEN0_FORCE - 0x4C + INT_CLR + 0x18C 0x20 - 0x00000020 - GEN0_CNTUFORCE_UPMETHOD + HSTIMER0_OVF_INT_CLR + Set this bit to clear high speed channel0 counter overflow interrupt. 0 - 6 - read-write - - - GEN0_A_CNTUFORCE_MODE - 6 - 2 - read-write - - - GEN0_B_CNTUFORCE_MODE - 8 - 2 - read-write - - - GEN0_A_NCIFORCE - 10 1 - read-write - - - GEN0_A_NCIFORCE_MODE - 11 - 2 - read-write + write-only - GEN0_B_NCIFORCE - 13 + HSTIMER1_OVF_INT_CLR + Set this bit to clear high speed channel1 counter overflow interrupt. + 1 1 - read-write + write-only - GEN0_B_NCIFORCE_MODE - 14 - 2 - read-write - - - - - GEN0_A - 0x50 - 0x20 - - - UTEZ - 0 - 2 - read-write + HSTIMER2_OVF_INT_CLR + Set this bit to clear high speed channel2 counter overflow interrupt. + 2 + 1 + write-only - UTEP - 2 - 2 - read-write + HSTIMER3_OVF_INT_CLR + Set this bit to clear high speed channel3 counter overflow interrupt. + 3 + 1 + write-only - UTEA + LSTIMER0_OVF_INT_CLR + Set this bit to clear low speed channel0 counter overflow interrupt. 4 - 2 - read-write + 1 + write-only - UTEB - 6 - 2 - read-write + LSTIMER1_OVF_INT_CLR + Set this bit to clear low speed channel1 counter overflow interrupt. + 5 + 1 + write-only - UT0 - 8 - 2 - read-write + LSTIMER2_OVF_INT_CLR + Set this bit to clear low speed channel2 counter overflow interrupt. + 6 + 1 + write-only - UT1 - 10 - 2 - read-write + LSTIMER3_OVF_INT_CLR + Set this bit to clear low speed channel3 counter overflow interrupt. + 7 + 1 + write-only - DTEZ - 12 - 2 - read-write + DUTY_CHNG_END_HSCH0_INT_CLR + Set this bit to clear high speed channel 0 duty change done interrupt. + 8 + 1 + write-only - DTEP - 14 - 2 - read-write + DUTY_CHNG_END_HSCH1_INT_CLR + Set this bit to clear high speed channel 1 duty change done interrupt. + 9 + 1 + write-only - DTEA - 16 - 2 - read-write + DUTY_CHNG_END_HSCH2_INT_CLR + Set this bit to clear high speed channel 2 duty change done interrupt. + 10 + 1 + write-only - DTEB - 18 - 2 - read-write + DUTY_CHNG_END_HSCH3_INT_CLR + Set this bit to clear high speed channel 3 duty change done interrupt. + 11 + 1 + write-only - DT0 - 20 - 2 - read-write + DUTY_CHNG_END_HSCH4_INT_CLR + Set this bit to clear high speed channel 4 duty change done interrupt. + 12 + 1 + write-only - DT1 - 22 - 2 - read-write + DUTY_CHNG_END_HSCH5_INT_CLR + Set this bit to clear high speed channel 5 duty change done interrupt. + 13 + 1 + write-only - - - - GEN0_B - 0x54 - 0x20 - - UTEZ - 0 - 2 - read-write + DUTY_CHNG_END_HSCH6_INT_CLR + Set this bit to clear high speed channel 6 duty change done interrupt. + 14 + 1 + write-only - UTEP - 2 - 2 - read-write + DUTY_CHNG_END_HSCH7_INT_CLR + Set this bit to clear high speed channel 7 duty change done interrupt. + 15 + 1 + write-only - UTEA - 4 - 2 - read-write + DUTY_CHNG_END_LSCH0_INT_CLR + Set this bit to clear low speed channel 0 duty change done interrupt. + 16 + 1 + write-only - UTEB - 6 - 2 - read-write + DUTY_CHNG_END_LSCH1_INT_CLR + Set this bit to clear low speed channel 1 duty change done interrupt. + 17 + 1 + write-only - UT0 - 8 - 2 - read-write + DUTY_CHNG_END_LSCH2_INT_CLR + Set this bit to clear low speed channel 2 duty change done interrupt. + 18 + 1 + write-only - UT1 - 10 - 2 - read-write + DUTY_CHNG_END_LSCH3_INT_CLR + Set this bit to clear low speed channel 3 duty change done interrupt. + 19 + 1 + write-only - DTEZ - 12 - 2 - read-write + DUTY_CHNG_END_LSCH4_INT_CLR + Set this bit to clear low speed channel 4 duty change done interrupt. + 20 + 1 + write-only - DTEP - 14 - 2 - read-write + DUTY_CHNG_END_LSCH5_INT_CLR + Set this bit to clear low speed channel 5 duty change done interrupt. + 21 + 1 + write-only - DTEA - 16 - 2 - read-write + DUTY_CHNG_END_LSCH6_INT_CLR + Set this bit to clear low speed channel 6 duty change done interrupt. + 22 + 1 + write-only - DTEB - 18 - 2 - read-write + DUTY_CHNG_END_LSCH7_INT_CLR + Set this bit to clear low speed channel 7 duty change done interrupt. + 23 + 1 + write-only + + + + CONF + 0x190 + 0x20 + - DT0 - 20 - 2 + APB_CLK_SEL + This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz + 0 + 1 read-write + + + + DATE + 0x1FC + 0x20 + 0x16031700 + - DT1 - 22 - 2 + DATE + This register represents the version . + 0 + 32 read-write + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + MCPWM + 0x3FF5E000 + + 0x0 + 0x128 + registers + + + MCPWM0 + 39 + + + MCPWM1 + 40 + + + MCPWM2 + 41 + + + MCPWM3 + 42 + + - DT0_CFG - 0x58 + CLK_CFG + 0x0 0x20 - 0x00018000 - DT0_FED_UPMETHOD + CLK_PRESCALE 0 - 4 + 8 read-write + + + + TIMER0_CFG0 + 0x4 + 0x20 + 0x0000FF00 + - DT0_RED_UPMETHOD - 4 - 4 + TIMER0_PRESCALE + 0 + 8 read-write - DT0_DEB_MODE + TIMER0_PERIOD 8 - 1 - read-write - - - DT0_A_OUTSWAP - 9 - 1 + 16 read-write - DT0_B_OUTSWAP - 10 - 1 + TIMER0_PERIOD_UPMETHOD + 24 + 2 read-write + + + + TIMER0_CFG1 + 0x8 + 0x20 + - DT0_RED_INSEL - 11 - 1 + TIMER0_START + 0 + 3 read-write - DT0_FED_INSEL - 12 - 1 + TIMER0_MOD + 3 + 2 read-write + + + + TIMER0_SYNC + 0xC + 0x20 + - DT0_RED_OUTINVERT - 13 + TIMER0_SYNCI_EN + 0 1 read-write - DT0_FED_OUTINVERT - 14 + SW + 1 1 read-write - DT0_A_OUTBYPASS - 15 - 1 + TIMER0_SYNCO_SEL + 2 + 2 read-write - DT0_B_OUTBYPASS - 16 - 1 + TIMER0_PHASE + 4 + 16 read-write - DT0_CLK_SEL - 17 + TIMER0_PHASE_DIRECTION + 20 1 read-write - DT0_FED_CFG - 0x5C + TIMER0_STATUS + 0x10 0x20 - DT0_FED + TIMER0_VALUE 0 16 - read-write + read-only - - - - DT0_RED_CFG - 0x60 - 0x20 - - DT0_RED - 0 - 16 - read-write + TIMER0_DIRECTION + 16 + 1 + read-only - CARRIER0_CFG - 0x64 + TIMER1_CFG0 + 0x14 0x20 + 0x0000FF00 - CARRIER0_EN + TIMER1_PRESCALE 0 - 1 - read-write - - - CARRIER0_PRESCALE - 1 - 4 + 8 read-write - CARRIER0_DUTY - 5 - 3 + TIMER1_PERIOD + 8 + 16 read-write - CARRIER0_OSHTWTH - 8 - 4 + TIMER1_PERIOD_UPMETHOD + 24 + 2 read-write + + + + TIMER1_CFG1 + 0x18 + 0x20 + - CARRIER0_OUT_INVERT - 12 - 1 + TIMER1_START + 0 + 3 read-write - CARRIER0_IN_INVERT - 13 - 1 + TIMER1_MOD + 3 + 2 read-write - FH0_CFG0 - 0x68 + TIMER1_SYNC + 0x1C 0x20 - FH0_SW_CBC + TIMER1_SYNCI_EN 0 1 read-write - FH0_F2_CBC + SW 1 1 read-write - FH0_F1_CBC + TIMER1_SYNCO_SEL 2 - 1 + 2 read-write - FH0_F0_CBC - 3 - 1 + TIMER1_PHASE + 4 + 16 read-write - FH0_SW_OST - 4 + TIMER1_PHASE_DIRECTION + 20 1 read-write + + + + TIMER1_STATUS + 0x20 + 0x20 + - FH0_F2_OST - 5 - 1 - read-write + TIMER1_VALUE + 0 + 16 + read-only - FH0_F1_OST - 6 + TIMER1_DIRECTION + 16 1 - read-write + read-only + + + + TIMER2_CFG0 + 0x24 + 0x20 + 0x0000FF00 + - FH0_F0_OST - 7 - 1 + TIMER2_PRESCALE + 0 + 8 read-write - FH0_A_CBC_D + TIMER2_PERIOD 8 - 2 + 16 read-write - FH0_A_CBC_U - 10 + TIMER2_PERIOD_UPMETHOD + 24 2 read-write + + + + TIMER2_CFG1 + 0x28 + 0x20 + - FH0_A_OST_D - 12 - 2 + TIMER2_START + 0 + 3 read-write - FH0_A_OST_U - 14 + TIMER2_MOD + 3 2 read-write + + + + TIMER2_SYNC + 0x2C + 0x20 + - FH0_B_CBC_D - 16 - 2 + TIMER2_SYNCI_EN + 0 + 1 read-write - FH0_B_CBC_U - 18 - 2 + SW + 1 + 1 read-write - FH0_B_OST_D - 20 + TIMER2_SYNCO_SEL + 2 2 read-write - FH0_B_OST_U - 22 - 2 + TIMER2_PHASE + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + 20 + 1 read-write - FH0_CFG1 - 0x6C + TIMER2_STATUS + 0x30 0x20 - FH0_CLR_OST + TIMER2_VALUE 0 + 16 + read-only + + + TIMER2_DIRECTION + 16 1 - read-write + read-only + + + + TIMER_SYNCI_CFG + 0x34 + 0x20 + - FH0_CBCPULSE - 1 - 2 + TIMER0_SYNCISEL + 0 + 3 read-write - FH0_FORCE_CBC + TIMER1_SYNCISEL 3 + 3 + read-write + + + TIMER2_SYNCISEL + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + 9 1 read-write - FH0_FORCE_OST - 4 + EXTERNAL_SYNCI1_INVERT + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + 11 1 read-write - FH0_STATUS - 0x70 + OPERATOR_TIMERSEL + 0x38 0x20 - FH0_CBC_ON + OPERATOR0_TIMERSEL 0 - 1 - read-only + 2 + read-write - FH0_OST_ON - 1 - 1 - read-only + OPERATOR1_TIMERSEL + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + 4 + 2 + read-write - GEN1_STMP_CFG - 0x74 + GEN0_STMP_CFG + 0x3C 0x20 - GEN1_A_UPMETHOD + GEN0_A_UPMETHOD 0 4 read-write - GEN1_B_UPMETHOD + GEN0_B_UPMETHOD 4 4 read-write - GEN1_A_SHDW_FULL + GEN0_A_SHDW_FULL 8 1 read-write - GEN1_B_SHDW_FULL + GEN0_B_SHDW_FULL 9 1 read-write @@ -19746,12 +19094,12 @@ - GEN1_TSTMP_A - 0x78 + GEN0_TSTMP_A + 0x40 0x20 - GEN1_A + GEN0_A 0 16 read-write @@ -19759,12 +19107,12 @@ - GEN1_TSTMP_B - 0x7C + GEN0_TSTMP_B + 0x44 0x20 - GEN1_B + GEN0_B 0 16 read-write @@ -19772,24 +19120,24 @@ - GEN1_CFG0 - 0x80 + GEN0_CFG0 + 0x48 0x20 - GEN1_CFG_UPMETHOD + GEN0_CFG_UPMETHOD 0 4 read-write - GEN1_T0_SEL + GEN0_T0_SEL 4 3 read-write - GEN1_T1_SEL + GEN0_T1_SEL 7 3 read-write @@ -19797,49 +19145,49 @@ - GEN1_FORCE - 0x84 + GEN0_FORCE + 0x4C 0x20 0x00000020 - GEN1_CNTUFORCE_UPMETHOD + GEN0_CNTUFORCE_UPMETHOD 0 6 read-write - GEN1_A_CNTUFORCE_MODE + GEN0_A_CNTUFORCE_MODE 6 2 read-write - GEN1_B_CNTUFORCE_MODE + GEN0_B_CNTUFORCE_MODE 8 2 read-write - GEN1_A_NCIFORCE + GEN0_A_NCIFORCE 10 1 read-write - GEN1_A_NCIFORCE_MODE + GEN0_A_NCIFORCE_MODE 11 2 read-write - GEN1_B_NCIFORCE + GEN0_B_NCIFORCE 13 1 read-write - GEN1_B_NCIFORCE_MODE + GEN0_B_NCIFORCE_MODE 14 2 read-write @@ -19847,8 +19195,8 @@ - GEN1_A - 0x88 + GEN0_A + 0x50 0x20 @@ -19926,8 +19274,8 @@ - GEN1_B - 0x8C + GEN0_B + 0x54 0x20 @@ -20005,79 +19353,79 @@ - DT1_CFG - 0x90 + DT0_CFG + 0x58 0x20 0x00018000 - DT1_FED_UPMETHOD + DT0_FED_UPMETHOD 0 4 read-write - DT1_RED_UPMETHOD + DT0_RED_UPMETHOD 4 4 read-write - DT1_DEB_MODE + DT0_DEB_MODE 8 1 read-write - DT1_A_OUTSWAP + DT0_A_OUTSWAP 9 1 read-write - DT1_B_OUTSWAP + DT0_B_OUTSWAP 10 1 read-write - DT1_RED_INSEL + DT0_RED_INSEL 11 1 read-write - DT1_FED_INSEL + DT0_FED_INSEL 12 1 read-write - DT1_RED_OUTINVERT + DT0_RED_OUTINVERT 13 1 read-write - DT1_FED_OUTINVERT + DT0_FED_OUTINVERT 14 1 read-write - DT1_A_OUTBYPASS + DT0_A_OUTBYPASS 15 1 read-write - DT1_B_OUTBYPASS + DT0_B_OUTBYPASS 16 1 read-write - DT1_CLK_SEL + DT0_CLK_SEL 17 1 read-write @@ -20085,12 +19433,12 @@ - DT1_FED_CFG - 0x94 + DT0_FED_CFG + 0x5C 0x20 - DT1_FED + DT0_FED 0 16 read-write @@ -20098,12 +19446,12 @@ - DT1_RED_CFG - 0x98 + DT0_RED_CFG + 0x60 0x20 - DT1_RED + DT0_RED 0 16 read-write @@ -20111,42 +19459,42 @@ - CARRIER1_CFG - 0x9C + CARRIER0_CFG + 0x64 0x20 - CARRIER1_EN + CARRIER0_EN 0 1 read-write - CARRIER1_PRESCALE + CARRIER0_PRESCALE 1 4 read-write - CARRIER1_DUTY + CARRIER0_DUTY 5 3 read-write - CARRIER1_OSHTWTH + CARRIER0_OSHTWTH 8 4 read-write - CARRIER1_OUT_INVERT + CARRIER0_OUT_INVERT 12 1 read-write - CARRIER1_IN_INVERT + CARRIER0_IN_INVERT 13 1 read-write @@ -20154,102 +19502,102 @@ - FH1_CFG0 - 0xA0 + FH0_CFG0 + 0x68 0x20 - FH1_SW_CBC + FH0_SW_CBC 0 1 read-write - FH1_F2_CBC + FH0_F2_CBC 1 1 read-write - FH1_F1_CBC + FH0_F1_CBC 2 1 read-write - FH1_F0_CBC + FH0_F0_CBC 3 1 read-write - FH1_SW_OST + FH0_SW_OST 4 1 read-write - FH1_F2_OST + FH0_F2_OST 5 1 read-write - FH1_F1_OST + FH0_F1_OST 6 1 read-write - FH1_F0_OST + FH0_F0_OST 7 1 read-write - FH1_A_CBC_D + FH0_A_CBC_D 8 2 read-write - FH1_A_CBC_U + FH0_A_CBC_U 10 2 read-write - FH1_A_OST_D + FH0_A_OST_D 12 2 read-write - FH1_A_OST_U + FH0_A_OST_U 14 2 read-write - FH1_B_CBC_D + FH0_B_CBC_D 16 2 read-write - FH1_B_CBC_U + FH0_B_CBC_U 18 2 read-write - FH1_B_OST_D + FH0_B_OST_D 20 2 read-write - FH1_B_OST_U + FH0_B_OST_U 22 2 read-write @@ -20257,30 +19605,30 @@ - FH1_CFG1 - 0xA4 + FH0_CFG1 + 0x6C 0x20 - FH1_CLR_OST + FH0_CLR_OST 0 1 read-write - FH1_CBCPULSE + FH0_CBCPULSE 1 2 read-write - FH1_FORCE_CBC + FH0_FORCE_CBC 3 1 read-write - FH1_FORCE_OST + FH0_FORCE_OST 4 1 read-write @@ -20288,18 +19636,18 @@ - FH1_STATUS - 0xA8 + FH0_STATUS + 0x70 0x20 - FH1_CBC_ON + FH0_CBC_ON 0 1 read-only - FH1_OST_ON + FH0_OST_ON 1 1 read-only @@ -20307,30 +19655,30 @@ - GEN2_STMP_CFG - 0xAC + GEN1_STMP_CFG + 0x74 0x20 - GEN2_A_UPMETHOD + GEN1_A_UPMETHOD 0 4 read-write - GEN2_B_UPMETHOD + GEN1_B_UPMETHOD 4 4 read-write - GEN2_A_SHDW_FULL + GEN1_A_SHDW_FULL 8 1 read-write - GEN2_B_SHDW_FULL + GEN1_B_SHDW_FULL 9 1 read-write @@ -20338,12 +19686,12 @@ - GEN2_TSTMP_A - 0xB0 + GEN1_TSTMP_A + 0x78 0x20 - GEN2_A + GEN1_A 0 16 read-write @@ -20351,12 +19699,12 @@ - GEN2_TSTMP_B - 0xB4 + GEN1_TSTMP_B + 0x7C 0x20 - GEN2_B + GEN1_B 0 16 read-write @@ -20364,24 +19712,24 @@ - GEN2_CFG0 - 0xB8 + GEN1_CFG0 + 0x80 0x20 - GEN2_CFG_UPMETHOD + GEN1_CFG_UPMETHOD 0 4 read-write - GEN2_T0_SEL + GEN1_T0_SEL 4 3 read-write - GEN2_T1_SEL + GEN1_T1_SEL 7 3 read-write @@ -20389,49 +19737,49 @@ - GEN2_FORCE - 0xBC + GEN1_FORCE + 0x84 0x20 0x00000020 - GEN2_CNTUFORCE_UPMETHOD + GEN1_CNTUFORCE_UPMETHOD 0 6 read-write - GEN2_A_CNTUFORCE_MODE + GEN1_A_CNTUFORCE_MODE 6 2 read-write - GEN2_B_CNTUFORCE_MODE + GEN1_B_CNTUFORCE_MODE 8 2 read-write - GEN2_A_NCIFORCE + GEN1_A_NCIFORCE 10 1 read-write - GEN2_A_NCIFORCE_MODE + GEN1_A_NCIFORCE_MODE 11 2 read-write - GEN2_B_NCIFORCE + GEN1_B_NCIFORCE 13 1 read-write - GEN2_B_NCIFORCE_MODE + GEN1_B_NCIFORCE_MODE 14 2 read-write @@ -20439,8 +19787,8 @@ - GEN2_A - 0xC0 + GEN1_A + 0x88 0x20 @@ -20518,8 +19866,8 @@ - GEN2_B - 0xC4 + GEN1_B + 0x8C 0x20 @@ -20597,79 +19945,79 @@ - DT2_CFG - 0xC8 + DT1_CFG + 0x90 0x20 0x00018000 - DT2_FED_UPMETHOD + DT1_FED_UPMETHOD 0 4 read-write - DT2_RED_UPMETHOD + DT1_RED_UPMETHOD 4 4 read-write - DT2_DEB_MODE + DT1_DEB_MODE 8 1 read-write - DT2_A_OUTSWAP + DT1_A_OUTSWAP 9 1 read-write - DT2_B_OUTSWAP + DT1_B_OUTSWAP 10 1 read-write - DT2_RED_INSEL + DT1_RED_INSEL 11 1 read-write - DT2_FED_INSEL + DT1_FED_INSEL 12 1 read-write - DT2_RED_OUTINVERT + DT1_RED_OUTINVERT 13 1 read-write - DT2_FED_OUTINVERT + DT1_FED_OUTINVERT 14 1 read-write - DT2_A_OUTBYPASS + DT1_A_OUTBYPASS 15 1 read-write - DT2_B_OUTBYPASS + DT1_B_OUTBYPASS 16 1 read-write - DT2_CLK_SEL + DT1_CLK_SEL 17 1 read-write @@ -20677,12 +20025,12 @@ - DT2_FED_CFG - 0xCC + DT1_FED_CFG + 0x94 0x20 - DT2_FED + DT1_FED 0 16 read-write @@ -20690,12 +20038,12 @@ - DT2_RED_CFG - 0xD0 + DT1_RED_CFG + 0x98 0x20 - DT2_RED + DT1_RED 0 16 read-write @@ -20703,42 +20051,42 @@ - CARRIER2_CFG - 0xD4 + CARRIER1_CFG + 0x9C 0x20 - CARRIER2_EN + CARRIER1_EN 0 1 read-write - CARRIER2_PRESCALE + CARRIER1_PRESCALE 1 4 read-write - CARRIER2_DUTY + CARRIER1_DUTY 5 3 read-write - CARRIER2_OSHTWTH + CARRIER1_OSHTWTH 8 4 read-write - CARRIER2_OUT_INVERT + CARRIER1_OUT_INVERT 12 1 read-write - CARRIER2_IN_INVERT + CARRIER1_IN_INVERT 13 1 read-write @@ -20746,102 +20094,102 @@ - FH2_CFG0 - 0xD8 + FH1_CFG0 + 0xA0 0x20 - FH2_SW_CBC + FH1_SW_CBC 0 1 read-write - FH2_F2_CBC + FH1_F2_CBC 1 1 read-write - FH2_F1_CBC + FH1_F1_CBC 2 1 read-write - FH2_F0_CBC + FH1_F0_CBC 3 1 read-write - FH2_SW_OST + FH1_SW_OST 4 1 read-write - FH2_F2_OST + FH1_F2_OST 5 1 read-write - FH2_F1_OST + FH1_F1_OST 6 1 read-write - FH2_F0_OST + FH1_F0_OST 7 1 read-write - FH2_A_CBC_D + FH1_A_CBC_D 8 2 read-write - FH2_A_CBC_U + FH1_A_CBC_U 10 2 read-write - FH2_A_OST_D + FH1_A_OST_D 12 2 read-write - FH2_A_OST_U + FH1_A_OST_U 14 2 read-write - FH2_B_CBC_D + FH1_B_CBC_D 16 2 read-write - FH2_B_CBC_U + FH1_B_CBC_U 18 2 read-write - FH2_B_OST_D + FH1_B_OST_D 20 2 read-write - FH2_B_OST_U + FH1_B_OST_U 22 2 read-write @@ -20849,30 +20197,30 @@ - FH2_CFG1 - 0xDC + FH1_CFG1 + 0xA4 0x20 - FH2_CLR_OST + FH1_CLR_OST 0 1 read-write - FH2_CBCPULSE + FH1_CBCPULSE 1 2 read-write - FH2_FORCE_CBC + FH1_FORCE_CBC 3 1 read-write - FH2_FORCE_OST + FH1_FORCE_OST 4 1 read-write @@ -20880,18 +20228,18 @@ - FH2_STATUS - 0xE0 + FH1_STATUS + 0xA8 0x20 - FH2_CBC_ON + FH1_CBC_ON 0 1 read-only - FH2_OST_ON + FH1_OST_ON 1 1 read-only @@ -20899,2403 +20247,1909 @@ - FAULT_DETECT - 0xE4 + GEN2_STMP_CFG + 0xAC 0x20 - F0_EN + GEN2_A_UPMETHOD 0 - 1 - read-write - - - F1_EN - 1 - 1 - read-write - - - F2_EN - 2 - 1 - read-write - - - F0_POLE - 3 - 1 + 4 read-write - F1_POLE + GEN2_B_UPMETHOD 4 - 1 - read-write - - - F2_POLE - 5 - 1 + 4 read-write - EVENT_F0 - 6 - 1 - read-only - - - EVENT_F1 - 7 - 1 - read-only - - - EVENT_F2 + GEN2_A_SHDW_FULL 8 1 - read-only - - - - - CAP_TIMER_CFG - 0xE8 - 0x20 - - - CAP_TIMER_EN - 0 - 1 - read-write - - - CAP_SYNCI_EN - 1 - 1 - read-write - - - CAP_SYNCI_SEL - 2 - 3 - read-write - - - CAP_SYNC_SW - 5 - 1 - write-only - - - - - CAP_TIMER_PHASE - 0xEC - 0x20 - - - CAP_TIMER_PHASE - 0 - 32 - read-write - - - - - CAP_CH0_CFG - 0xF0 - 0x20 - - - CAP0_EN - 0 - 1 - read-write - - - CAP0_MODE - 1 - 2 - read-write - - - CAP0_PRESCALE - 3 - 8 read-write - CAP0_IN_INVERT - 11 + GEN2_B_SHDW_FULL + 9 1 read-write - - CAP0_SW - 12 - 1 - write-only - - CAP_CH1_CFG - 0xF4 + GEN2_TSTMP_A + 0xB0 0x20 - CAP1_EN + GEN2_A 0 - 1 - read-write - - - CAP1_MODE - 1 - 2 - read-write - - - CAP1_PRESCALE - 3 - 8 - read-write - - - CAP1_IN_INVERT - 11 - 1 + 16 read-write - - CAP1_SW - 12 - 1 - write-only - - CAP_CH2_CFG - 0xF8 + GEN2_TSTMP_B + 0xB4 0x20 - CAP2_EN + GEN2_B 0 - 1 - read-write - - - CAP2_MODE - 1 - 2 - read-write - - - CAP2_PRESCALE - 3 - 8 - read-write - - - CAP2_IN_INVERT - 11 - 1 + 16 read-write - - CAP2_SW - 12 - 1 - write-only - - - - - CAP_CH0 - 0xFC - 0x20 - - - CAP0_VALUE - 0 - 32 - read-only - - - - - CAP_CH1 - 0x100 - 0x20 - - - CAP1_VALUE - 0 - 32 - read-only - - - - - CAP_CH2 - 0x104 - 0x20 - - - CAP2_VALUE - 0 - 32 - read-only - - - - - CAP_STATUS - 0x108 - 0x20 - - - CAP0_EDGE - 0 - 1 - read-only - - - CAP1_EDGE - 1 - 1 - read-only - - - CAP2_EDGE - 2 - 1 - read-only - - UPDATE_CFG - 0x10C + GEN2_CFG0 + 0xB8 0x20 - 0x00000055 - GLOBAL_UP_EN + GEN2_CFG_UPMETHOD 0 - 1 - read-write - - - GLOBAL_FORCE_UP - 1 - 1 - read-write - - - OP0_UP_EN - 2 - 1 - read-write - - - OP0_FORCE_UP - 3 - 1 + 4 read-write - OP1_UP_EN + GEN2_T0_SEL 4 - 1 - read-write - - - OP1_FORCE_UP - 5 - 1 - read-write - - - OP2_UP_EN - 6 - 1 + 3 read-write - OP2_FORCE_UP + GEN2_T1_SEL 7 - 1 + 3 read-write - - - INT_ENA - 0x110 - 0x20 - - - TIMER0_STOP_INT_ENA - 0 - 1 - read-write - - - TIMER1_STOP_INT_ENA - 1 - 1 - read-write - - - TIMER2_STOP_INT_ENA - 2 - 1 - read-write - - - TIMER0_TEZ_INT_ENA - 3 - 1 - read-write - - - TIMER1_TEZ_INT_ENA - 4 - 1 - read-write - - - TIMER2_TEZ_INT_ENA - 5 - 1 - read-write - - - TIMER0_TEP_INT_ENA - 6 - 1 - read-write - - - TIMER1_TEP_INT_ENA - 7 - 1 - read-write - - - TIMER2_TEP_INT_ENA - 8 - 1 - read-write - - - FAULT0_INT_ENA - 9 - 1 - read-write - - - FAULT1_INT_ENA - 10 - 1 - read-write - + + + GEN2_FORCE + 0xBC + 0x20 + 0x00000020 + - FAULT2_INT_ENA - 11 - 1 + GEN2_CNTUFORCE_UPMETHOD + 0 + 6 read-write - FAULT0_CLR_INT_ENA - 12 - 1 + GEN2_A_CNTUFORCE_MODE + 6 + 2 read-write - FAULT1_CLR_INT_ENA - 13 - 1 + GEN2_B_CNTUFORCE_MODE + 8 + 2 read-write - FAULT2_CLR_INT_ENA - 14 + GEN2_A_NCIFORCE + 10 1 read-write - OP0_TEA_INT_ENA - 15 - 1 + GEN2_A_NCIFORCE_MODE + 11 + 2 read-write - OP1_TEA_INT_ENA - 16 + GEN2_B_NCIFORCE + 13 1 read-write - OP2_TEA_INT_ENA - 17 - 1 + GEN2_B_NCIFORCE_MODE + 14 + 2 read-write + + + + GEN2_A + 0xC0 + 0x20 + - OP0_TEB_INT_ENA - 18 - 1 + UTEZ + 0 + 2 read-write - OP1_TEB_INT_ENA - 19 - 1 + UTEP + 2 + 2 read-write - OP2_TEB_INT_ENA - 20 - 1 + UTEA + 4 + 2 read-write - FH0_CBC_INT_ENA - 21 - 1 + UTEB + 6 + 2 read-write - FH1_CBC_INT_ENA - 22 - 1 + UT0 + 8 + 2 read-write - FH2_CBC_INT_ENA - 23 - 1 + UT1 + 10 + 2 read-write - FH0_OST_INT_ENA - 24 - 1 + DTEZ + 12 + 2 read-write - FH1_OST_INT_ENA - 25 - 1 + DTEP + 14 + 2 read-write - FH2_OST_INT_ENA - 26 - 1 + DTEA + 16 + 2 read-write - CAP0_INT_ENA - 27 - 1 + DTEB + 18 + 2 read-write - CAP1_INT_ENA - 28 - 1 + DT0 + 20 + 2 read-write - CAP2_INT_ENA - 29 - 1 + DT1 + 22 + 2 read-write - INT_RAW - 0x114 + GEN2_B + 0xC4 0x20 - TIMER0_STOP_INT_RAW + UTEZ 0 - 1 - read-only - - - TIMER1_STOP_INT_RAW - 1 - 1 - read-only + 2 + read-write - TIMER2_STOP_INT_RAW + UTEP 2 - 1 - read-only - - - TIMER0_TEZ_INT_RAW - 3 - 1 - read-only + 2 + read-write - TIMER1_TEZ_INT_RAW + UTEA 4 - 1 - read-only - - - TIMER2_TEZ_INT_RAW - 5 - 1 - read-only + 2 + read-write - TIMER0_TEP_INT_RAW + UTEB 6 - 1 - read-only - - - TIMER1_TEP_INT_RAW - 7 - 1 - read-only + 2 + read-write - TIMER2_TEP_INT_RAW + UT0 8 - 1 - read-only - - - FAULT0_INT_RAW - 9 - 1 - read-only + 2 + read-write - FAULT1_INT_RAW + UT1 10 - 1 - read-only - - - FAULT2_INT_RAW - 11 - 1 - read-only + 2 + read-write - FAULT0_CLR_INT_RAW + DTEZ 12 - 1 - read-only - - - FAULT1_CLR_INT_RAW - 13 - 1 - read-only + 2 + read-write - FAULT2_CLR_INT_RAW + DTEP 14 - 1 - read-only - - - OP0_TEA_INT_RAW - 15 - 1 - read-only + 2 + read-write - OP1_TEA_INT_RAW + DTEA 16 - 1 - read-only - - - OP2_TEA_INT_RAW - 17 - 1 - read-only + 2 + read-write - OP0_TEB_INT_RAW + DTEB 18 - 1 - read-only - - - OP1_TEB_INT_RAW - 19 - 1 - read-only + 2 + read-write - OP2_TEB_INT_RAW + DT0 20 - 1 - read-only - - - FH0_CBC_INT_RAW - 21 - 1 - read-only + 2 + read-write - FH1_CBC_INT_RAW + DT1 22 - 1 - read-only - - - FH2_CBC_INT_RAW - 23 - 1 - read-only - - - FH0_OST_INT_RAW - 24 - 1 - read-only - - - FH1_OST_INT_RAW - 25 - 1 - read-only - - - FH2_OST_INT_RAW - 26 - 1 - read-only - - - CAP0_INT_RAW - 27 - 1 - read-only - - - CAP1_INT_RAW - 28 - 1 - read-only - - - CAP2_INT_RAW - 29 - 1 - read-only + 2 + read-write - INT_ST - 0x118 + DT2_CFG + 0xC8 0x20 + 0x00018000 - TIMER0_STOP_INT_ST + DT2_FED_UPMETHOD 0 - 1 - read-only - - - TIMER1_STOP_INT_ST - 1 - 1 - read-only - - - TIMER2_STOP_INT_ST - 2 - 1 - read-only - - - TIMER0_TEZ_INT_ST - 3 - 1 - read-only + 4 + read-write - TIMER1_TEZ_INT_ST + DT2_RED_UPMETHOD 4 - 1 - read-only - - - TIMER2_TEZ_INT_ST - 5 - 1 - read-only - - - TIMER0_TEP_INT_ST - 6 - 1 - read-only - - - TIMER1_TEP_INT_ST - 7 - 1 - read-only + 4 + read-write - TIMER2_TEP_INT_ST + DT2_DEB_MODE 8 1 - read-only + read-write - FAULT0_INT_ST + DT2_A_OUTSWAP 9 1 - read-only + read-write - FAULT1_INT_ST + DT2_B_OUTSWAP 10 1 - read-only + read-write - FAULT2_INT_ST + DT2_RED_INSEL 11 1 - read-only + read-write - FAULT0_CLR_INT_ST + DT2_FED_INSEL 12 1 - read-only + read-write - FAULT1_CLR_INT_ST + DT2_RED_OUTINVERT 13 1 - read-only + read-write - FAULT2_CLR_INT_ST + DT2_FED_OUTINVERT 14 1 - read-only + read-write - OP0_TEA_INT_ST + DT2_A_OUTBYPASS 15 1 - read-only + read-write - OP1_TEA_INT_ST + DT2_B_OUTBYPASS 16 1 - read-only + read-write - OP2_TEA_INT_ST + DT2_CLK_SEL 17 1 - read-only - - - OP0_TEB_INT_ST - 18 - 1 - read-only - - - OP1_TEB_INT_ST - 19 - 1 - read-only - - - OP2_TEB_INT_ST - 20 - 1 - read-only - - - FH0_CBC_INT_ST - 21 - 1 - read-only + read-write + + + + DT2_FED_CFG + 0xCC + 0x20 + - FH1_CBC_INT_ST - 22 - 1 - read-only + DT2_FED + 0 + 16 + read-write + + + + DT2_RED_CFG + 0xD0 + 0x20 + - FH2_CBC_INT_ST - 23 - 1 - read-only + DT2_RED + 0 + 16 + read-write + + + + CARRIER2_CFG + 0xD4 + 0x20 + - FH0_OST_INT_ST - 24 + CARRIER2_EN + 0 1 - read-only + read-write - FH1_OST_INT_ST - 25 - 1 - read-only + CARRIER2_PRESCALE + 1 + 4 + read-write - FH2_OST_INT_ST - 26 - 1 - read-only + CARRIER2_DUTY + 5 + 3 + read-write - CAP0_INT_ST - 27 - 1 - read-only + CARRIER2_OSHTWTH + 8 + 4 + read-write - CAP1_INT_ST - 28 + CARRIER2_OUT_INVERT + 12 1 - read-only + read-write - CAP2_INT_ST - 29 + CARRIER2_IN_INVERT + 13 1 - read-only + read-write - INT_CLR - 0x11C + FH2_CFG0 + 0xD8 0x20 - TIMER0_STOP_INT_CLR + FH2_SW_CBC 0 1 - write-only + read-write - TIMER1_STOP_INT_CLR + FH2_F2_CBC 1 1 - write-only + read-write - TIMER2_STOP_INT_CLR + FH2_F1_CBC 2 1 - write-only + read-write - TIMER0_TEZ_INT_CLR + FH2_F0_CBC 3 1 - write-only + read-write - TIMER1_TEZ_INT_CLR + FH2_SW_OST 4 1 - write-only + read-write - TIMER2_TEZ_INT_CLR + FH2_F2_OST 5 1 - write-only + read-write - TIMER0_TEP_INT_CLR + FH2_F1_OST 6 1 - write-only + read-write - TIMER1_TEP_INT_CLR + FH2_F0_OST 7 1 - write-only + read-write - TIMER2_TEP_INT_CLR + FH2_A_CBC_D 8 - 1 - write-only - - - FAULT0_INT_CLR - 9 - 1 - write-only + 2 + read-write - FAULT1_INT_CLR + FH2_A_CBC_U 10 - 1 - write-only - - - FAULT2_INT_CLR - 11 - 1 - write-only + 2 + read-write - FAULT0_CLR_INT_CLR + FH2_A_OST_D 12 - 1 - write-only - - - FAULT1_CLR_INT_CLR - 13 - 1 - write-only + 2 + read-write - FAULT2_CLR_INT_CLR + FH2_A_OST_U 14 - 1 - write-only - - - OP0_TEA_INT_CLR - 15 - 1 - write-only + 2 + read-write - OP1_TEA_INT_CLR + FH2_B_CBC_D 16 - 1 - write-only - - - OP2_TEA_INT_CLR - 17 - 1 - write-only + 2 + read-write - OP0_TEB_INT_CLR + FH2_B_CBC_U 18 - 1 - write-only - - - OP1_TEB_INT_CLR - 19 - 1 - write-only + 2 + read-write - OP2_TEB_INT_CLR + FH2_B_OST_D 20 - 1 - write-only - - - FH0_CBC_INT_CLR - 21 - 1 - write-only + 2 + read-write - FH1_CBC_INT_CLR + FH2_B_OST_U 22 - 1 - write-only - - - FH2_CBC_INT_CLR - 23 - 1 - write-only - - - FH0_OST_INT_CLR - 24 - 1 - write-only - - - FH1_OST_INT_CLR - 25 - 1 - write-only + 2 + read-write + + + + FH2_CFG1 + 0xDC + 0x20 + - FH2_OST_INT_CLR - 26 + FH2_CLR_OST + 0 1 - write-only + read-write - CAP0_INT_CLR - 27 - 1 - write-only + FH2_CBCPULSE + 1 + 2 + read-write - CAP1_INT_CLR - 28 + FH2_FORCE_CBC + 3 1 - write-only + read-write - CAP2_INT_CLR - 29 + FH2_FORCE_OST + 4 1 - write-only + read-write - CLK - 0x120 + FH2_STATUS + 0xE0 0x20 - EN + FH2_CBC_ON 0 1 - read-write + read-only - - - - VERSION - 0x124 - 0x20 - 0x02107230 - - DATE - 0 - 28 - read-write + FH2_OST_ON + 1 + 1 + read-only - - - - PWM1 - Motor Control Pulse-Width Modulation - 0x3FF6C000 - - PWM1 - 40 - - - - NRX - Peripheral NRX - NRX - 0x3FF5CC00 - - 0x0 - 0x4 - registers - - - NRXPD_CTRL - WiFi RX control register - 0xD4 + FAULT_DETECT + 0xE4 0x20 - DEMAP_FORCE_PD + F0_EN 0 1 read-write - DEMAP_FORCE_PU + F1_EN 1 1 read-write - VIT_FORCE_PD + F2_EN 2 1 read-write - VIT_FORCE_PU + F0_POLE 3 1 read-write - RX_ROT_FORCE_PD + F1_POLE 4 1 read-write - RX_ROT_FORCE_PU + F2_POLE 5 1 read-write - CHAN_EST_FORCE_PD + EVENT_F0 6 1 - read-write + read-only - CHAN_EST_FORCE_PU + EVENT_F1 7 1 - read-write + read-only + + + EVENT_F2 + 8 + 1 + read-only - - - - PCNT - Pulse Count Controller - PCNT - 0x3FF57000 - - 0x0 - 0xB8 - registers - - - PCNT - 48 - - - U0_CONF0 - 0x0 + CAP_TIMER_CFG + 0xE8 0x20 - 0x00003C10 - FILTER_THRES_U0 - This register is used to filter pluse whose width is smaller than this value for unit0. + CAP_TIMER_EN 0 - 10 + 1 read-write - FILTER_EN_U0 - This is the enable bit for filtering input signals for unit0. - 10 + CAP_SYNCI_EN + 1 1 read-write - THR_ZERO_EN_U0 - This is the enable bit for comparing unit0's count with 0 value. - 11 - 1 + CAP_SYNCI_SEL + 2 + 3 read-write - THR_H_LIM_EN_U0 - This is the enable bit for comparing unit0's count with thr_h_lim value. - 12 + CAP_SYNC_SW + 5 1 + write-only + + + + + CAP_TIMER_PHASE + 0xEC + 0x20 + + + CAP_TIMER_PHASE + 0 + 32 read-write + + + + CAP_CH0_CFG + 0xF0 + 0x20 + - THR_L_LIM_EN_U0 - This is the enable bit for comparing unit0's count with thr_l_lim value. - 13 + CAP0_EN + 0 1 read-write - THR_THRES0_EN_U0 - This is the enable bit for comparing unit0's count with thres0 value. - 14 - 1 + CAP0_MODE + 1 + 2 read-write - THR_THRES1_EN_U0 - This is the enable bit for comparing unit0's count with thres1 value . - 15 + CAP0_PRESCALE + 3 + 8 + read-write + + + CAP0_IN_INVERT + 11 1 read-write - CH0_NEG_MODE_U0 - This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 + CAP0_SW + 12 + 1 + write-only + + + + + CAP_CH1_CFG + 0xF4 + 0x20 + + + CAP1_EN + 0 + 1 read-write - CH0_POS_MODE_U0 - This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 + CAP1_MODE + 1 2 read-write - CH0_HCTRL_MODE_U0 - This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 + CAP1_PRESCALE + 3 + 8 read-write - CH0_LCTRL_MODE_U0 - This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 + CAP1_IN_INVERT + 11 + 1 read-write - CH1_NEG_MODE_U0 - This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 + CAP1_SW + 12 + 1 + write-only + + + + + CAP_CH2_CFG + 0xF8 + 0x20 + + + CAP2_EN + 0 + 1 read-write - CH1_POS_MODE_U0 - This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 + CAP2_MODE + 1 2 read-write - CH1_HCTRL_MODE_U0 - This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 + CAP2_PRESCALE + 3 + 8 read-write - CH1_LCTRL_MODE_U0 - This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 + CAP2_IN_INVERT + 11 + 1 read-write + + CAP2_SW + 12 + 1 + write-only + - U0_CONF1 - 0x4 + CAP_CH0 + 0xFC 0x20 - CNT_THRES0_U0 - This register is used to configure thres0 value for unit0. + CAP0_VALUE 0 - 16 - read-write - - - CNT_THRES1_U0 - This register is used to configure thres1 value for unit0. - 16 - 16 - read-write + 32 + read-only - U0_CONF2 - 0x8 + CAP_CH1 + 0x100 0x20 - CNT_H_LIM_U0 - This register is used to configure thr_h_lim value for unit0. + CAP1_VALUE 0 - 16 - read-write + 32 + read-only + + + + CAP_CH2 + 0x104 + 0x20 + - CNT_L_LIM_U0 - This register is used to confiugre thr_l_lim value for unit0. - 16 - 16 - read-write + CAP2_VALUE + 0 + 32 + read-only - U1_CONF0 - 0xC + CAP_STATUS + 0x108 0x20 - 0x00003C10 - FILTER_THRES_U1 - This register is used to filter pluse whose width is smaller than this value for unit1. + CAP0_EDGE 0 - 10 - read-write + 1 + read-only - FILTER_EN_U1 - This is the enable bit for filtering input signals for unit1. - 10 + CAP1_EDGE + 1 1 - read-write + read-only - THR_ZERO_EN_U1 - This is the enable bit for comparing unit1's count with 0 value. - 11 + CAP2_EDGE + 2 + 1 + read-only + + + + + UPDATE_CFG + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + 0 1 read-write - THR_H_LIM_EN_U1 - This is the enable bit for comparing unit1's count with thr_h_lim value. - 12 + GLOBAL_FORCE_UP + 1 1 read-write - THR_L_LIM_EN_U1 - This is the enable bit for comparing unit1's count with thr_l_lim value. - 13 + OP0_UP_EN + 2 1 read-write - THR_THRES0_EN_U1 - This is the enable bit for comparing unit1's count with thres0 value. - 14 + OP0_FORCE_UP + 3 1 read-write - THR_THRES1_EN_U1 - This is the enable bit for comparing unit1's count with thres1 value . - 15 + OP1_UP_EN + 4 1 read-write - CH0_NEG_MODE_U1 - This register is used to control the mode of channel0's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 + OP1_FORCE_UP + 5 + 1 read-write - CH0_POS_MODE_U1 - This register is used to control the mode of channel0's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 + OP2_UP_EN + 6 + 1 read-write - CH0_HCTRL_MODE_U1 - This register is used to control the mode of channel0's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 + OP2_FORCE_UP + 7 + 1 read-write + + + + INT_ENA + 0x110 + 0x20 + - CH0_LCTRL_MODE_U1 - This register is used to control the mode of channel0's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 + TIMER0_STOP_INT_ENA + 0 + 1 read-write - CH1_NEG_MODE_U1 - This register is used to control the mode of channel1's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 + TIMER1_STOP_INT_ENA + 1 + 1 read-write - CH1_POS_MODE_U1 - This register is used to control the mode of channel1's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 + TIMER2_STOP_INT_ENA + 2 + 1 read-write - CH1_HCTRL_MODE_U1 - This register is used to control the mode of channel1's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 + TIMER0_TEZ_INT_ENA + 3 + 1 read-write - CH1_LCTRL_MODE_U1 - This register is used to control the mode of channel1's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 + TIMER1_TEZ_INT_ENA + 4 + 1 read-write - - - - U1_CONF1 - 0x10 - 0x20 - - CNT_THRES0_U1 - This register is used to configure thres0 value for unit1. - 0 - 16 + TIMER2_TEZ_INT_ENA + 5 + 1 read-write - CNT_THRES1_U1 - This register is used to configure thres1 value for unit1. - 16 - 16 + TIMER0_TEP_INT_ENA + 6 + 1 read-write - - - - U1_CONF2 - 0x14 - 0x20 - - CNT_H_LIM_U1 - This register is used to configure thr_h_lim value for unit1. - 0 - 16 + TIMER1_TEP_INT_ENA + 7 + 1 read-write - CNT_L_LIM_U1 - This register is used to confiugre thr_l_lim value for unit1. - 16 - 16 + TIMER2_TEP_INT_ENA + 8 + 1 read-write - - - - U2_CONF0 - 0x18 - 0x20 - 0x00003C10 - - FILTER_THRES_U2 - This register is used to filter pluse whose width is smaller than this value for unit2. - 0 - 10 + FAULT0_INT_ENA + 9 + 1 read-write - FILTER_EN_U2 - This is the enable bit for filtering input signals for unit2. + FAULT1_INT_ENA 10 1 read-write - THR_ZERO_EN_U2 - This is the enable bit for comparing unit2's count with 0 value. + FAULT2_INT_ENA 11 1 read-write - THR_H_LIM_EN_U2 - This is the enable bit for comparing unit2's count with thr_h_lim value. + FAULT0_CLR_INT_ENA 12 1 read-write - THR_L_LIM_EN_U2 - This is the enable bit for comparing unit2's count with thr_l_lim value. + FAULT1_CLR_INT_ENA 13 1 read-write - THR_THRES0_EN_U2 - This is the enable bit for comparing unit2's count with thres0 value. + FAULT2_CLR_INT_ENA 14 1 read-write - THR_THRES1_EN_U2 - This is the enable bit for comparing unit2's count with thres1 value . + OP0_TEA_INT_ENA 15 1 read-write - CH0_NEG_MODE_U2 - This register is used to control the mode of channel0's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + OP1_TEA_INT_ENA 16 - 2 + 1 + read-write + + + OP2_TEA_INT_ENA + 17 + 1 read-write - CH0_POS_MODE_U2 - This register is used to control the mode of channel0's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + OP0_TEB_INT_ENA 18 - 2 + 1 + read-write + + + OP1_TEB_INT_ENA + 19 + 1 read-write - CH0_HCTRL_MODE_U2 - This register is used to control the mode of channel0's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + OP2_TEB_INT_ENA 20 - 2 + 1 read-write - CH0_LCTRL_MODE_U2 - This register is used to control the mode of channel0's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 + FH0_CBC_INT_ENA + 21 + 1 read-write - CH1_NEG_MODE_U2 - This register is used to control the mode of channel1's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 + FH1_CBC_INT_ENA + 22 + 1 read-write - CH1_POS_MODE_U2 - This register is used to control the mode of channel1's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 + FH2_CBC_INT_ENA + 23 + 1 read-write - CH1_HCTRL_MODE_U2 - This register is used to control the mode of channel1's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 + FH0_OST_INT_ENA + 24 + 1 read-write - CH1_LCTRL_MODE_U2 - This register is used to control the mode of channel1's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 + FH1_OST_INT_ENA + 25 + 1 read-write - - - - U2_CONF1 - 0x1C - 0x20 - - CNT_THRES0_U2 - This register is used to configure thres0 value for unit2. - 0 - 16 + FH2_OST_INT_ENA + 26 + 1 read-write - CNT_THRES1_U2 - This register is used to configure thres1 value for unit2. - 16 - 16 + CAP0_INT_ENA + 27 + 1 read-write - - - - U2_CONF2 - 0x20 - 0x20 - - CNT_H_LIM_U2 - This register is used to configure thr_h_lim value for unit2. - 0 - 16 + CAP1_INT_ENA + 28 + 1 read-write - CNT_L_LIM_U2 - This register is used to confiugre thr_l_lim value for unit2. - 16 - 16 + CAP2_INT_ENA + 29 + 1 read-write - U3_CONF0 - 0x24 + INT_RAW + 0x114 0x20 - 0x00003C10 - FILTER_THRES_U3 - This register is used to filter pluse whose width is smaller than this value for unit3. + TIMER0_STOP_INT_RAW 0 - 10 - read-write + 1 + read-only + + + TIMER1_STOP_INT_RAW + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + 7 + 1 + read-only - FILTER_EN_U3 - This is the enable bit for filtering input signals for unit3. + TIMER2_TEP_INT_RAW + 8 + 1 + read-only + + + FAULT0_INT_RAW + 9 + 1 + read-only + + + FAULT1_INT_RAW 10 1 - read-write + read-only - THR_ZERO_EN_U3 - This is the enable bit for comparing unit3's count with 0 value. + FAULT2_INT_RAW 11 1 - read-write + read-only - THR_H_LIM_EN_U3 - This is the enable bit for comparing unit3's count with thr_h_lim value. + FAULT0_CLR_INT_RAW 12 1 - read-write + read-only - THR_L_LIM_EN_U3 - This is the enable bit for comparing unit3's count with thr_l_lim value. + FAULT1_CLR_INT_RAW 13 1 - read-write + read-only - THR_THRES0_EN_U3 - This is the enable bit for comparing unit3's count with thres0 value. + FAULT2_CLR_INT_RAW 14 1 - read-write + read-only - THR_THRES1_EN_U3 - This is the enable bit for comparing unit3's count with thres1 value . + OP0_TEA_INT_RAW 15 1 - read-write + read-only - CH0_NEG_MODE_U3 - This register is used to control the mode of channel0's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + OP1_TEA_INT_RAW 16 - 2 - read-write + 1 + read-only + + + OP2_TEA_INT_RAW + 17 + 1 + read-only - CH0_POS_MODE_U3 - This register is used to control the mode of channel0's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + OP0_TEB_INT_RAW 18 - 2 - read-write + 1 + read-only + + + OP1_TEB_INT_RAW + 19 + 1 + read-only - CH0_HCTRL_MODE_U3 - This register is used to control the mode of channel0's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + OP2_TEB_INT_RAW 20 - 2 - read-write + 1 + read-only + + + FH0_CBC_INT_RAW + 21 + 1 + read-only - CH0_LCTRL_MODE_U3 - This register is used to control the mode of channel0's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + FH1_CBC_INT_RAW 22 - 2 - read-write + 1 + read-only + + + FH2_CBC_INT_RAW + 23 + 1 + read-only - CH1_NEG_MODE_U3 - This register is used to control the mode of channel1's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + FH0_OST_INT_RAW 24 - 2 - read-write + 1 + read-only + + + FH1_OST_INT_RAW + 25 + 1 + read-only - CH1_POS_MODE_U3 - This register is used to control the mode of channel1's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + FH2_OST_INT_RAW 26 - 2 - read-write + 1 + read-only + + + CAP0_INT_RAW + 27 + 1 + read-only - CH1_HCTRL_MODE_U3 - This register is used to control the mode of channel1's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CAP1_INT_RAW 28 - 2 - read-write + 1 + read-only - CH1_LCTRL_MODE_U3 - This register is used to control the mode of channel1's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write + CAP2_INT_RAW + 29 + 1 + read-only - U3_CONF1 - 0x28 + INT_ST + 0x118 0x20 - CNT_THRES0_U3 - This register is used to configure thres0 value for unit3. + TIMER0_STOP_INT_ST 0 - 16 - read-write + 1 + read-only - CNT_THRES1_U3 - This register is used to configure thres1 value for unit3. - 16 - 16 - read-write + TIMER1_STOP_INT_ST + 1 + 1 + read-only - - - - U3_CONF2 - 0x2C - 0x20 - - CNT_H_LIM_U3 - This register is used to configure thr_h_lim value for unit3. - 0 - 16 - read-write + TIMER2_STOP_INT_ST + 2 + 1 + read-only - CNT_L_LIM_U3 - This register is used to confiugre thr_l_lim value for unit3. - 16 - 16 - read-write + TIMER0_TEZ_INT_ST + 3 + 1 + read-only - - - - U4_CONF0 - 0x30 - 0x20 - 0x00003C10 - - FILTER_THRES_U4 - This register is used to filter pluse whose width is smaller than this value for unit4. - 0 - 10 - read-write + TIMER1_TEZ_INT_ST + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + 8 + 1 + read-only + + + FAULT0_INT_ST + 9 + 1 + read-only - FILTER_EN_U4 - This is the enable bit for filtering input signals for unit4. + FAULT1_INT_ST 10 1 - read-write + read-only - THR_ZERO_EN_U4 - This is the enable bit for comparing unit4's count with 0 value. + FAULT2_INT_ST 11 1 - read-write + read-only - THR_H_LIM_EN_U4 - This is the enable bit for comparing unit4's count with thr_h_lim value. + FAULT0_CLR_INT_ST 12 1 - read-write + read-only - THR_L_LIM_EN_U4 - This is the enable bit for comparing unit4's count with thr_l_lim value. + FAULT1_CLR_INT_ST 13 1 - read-write + read-only - THR_THRES0_EN_U4 - This is the enable bit for comparing unit4's count with thres0 value. + FAULT2_CLR_INT_ST 14 1 - read-write + read-only - THR_THRES1_EN_U4 - This is the enable bit for comparing unit4's count with thres1 value . + OP0_TEA_INT_ST 15 1 - read-write + read-only - CH0_NEG_MODE_U4 - This register is used to control the mode of channel0's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + OP1_TEA_INT_ST 16 - 2 - read-write + 1 + read-only + + + OP2_TEA_INT_ST + 17 + 1 + read-only - CH0_POS_MODE_U4 - This register is used to control the mode of channel0's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + OP0_TEB_INT_ST 18 - 2 - read-write + 1 + read-only + + + OP1_TEB_INT_ST + 19 + 1 + read-only - CH0_HCTRL_MODE_U4 - This register is used to control the mode of channel0's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + OP2_TEB_INT_ST 20 - 2 - read-write + 1 + read-only - CH0_LCTRL_MODE_U4 - This register is used to control the mode of channel0's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + FH0_CBC_INT_ST + 21 + 1 + read-only + + + FH1_CBC_INT_ST 22 - 2 - read-write + 1 + read-only + + + FH2_CBC_INT_ST + 23 + 1 + read-only - CH1_NEG_MODE_U4 - This register is used to control the mode of channel1's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + FH0_OST_INT_ST 24 - 2 - read-write + 1 + read-only + + + FH1_OST_INT_ST + 25 + 1 + read-only - CH1_POS_MODE_U4 - This register is used to control the mode of channel1's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + FH2_OST_INT_ST 26 - 2 - read-write + 1 + read-only + + + CAP0_INT_ST + 27 + 1 + read-only - CH1_HCTRL_MODE_U4 - This register is used to control the mode of channel1's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CAP1_INT_ST 28 - 2 - read-write + 1 + read-only - CH1_LCTRL_MODE_U4 - This register is used to control the mode of channel1's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write + CAP2_INT_ST + 29 + 1 + read-only - U4_CONF1 - 0x34 + INT_CLR + 0x11C 0x20 - CNT_THRES0_U4 - This register is used to configure thres0 value for unit4. + TIMER0_STOP_INT_CLR 0 - 16 - read-write + 1 + write-only + + + TIMER1_STOP_INT_CLR + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + 5 + 1 + write-only - CNT_THRES1_U4 - This register is used to configure thres1 value for unit4. - 16 - 16 - read-write + TIMER0_TEP_INT_CLR + 6 + 1 + write-only - - - - U4_CONF2 - 0x38 - 0x20 - - CNT_H_LIM_U4 - This register is used to configure thr_h_lim value for unit4. - 0 - 16 - read-write + TIMER1_TEP_INT_CLR + 7 + 1 + write-only - CNT_L_LIM_U4 - This register is used to confiugre thr_l_lim value for unit4. - 16 - 16 - read-write + TIMER2_TEP_INT_CLR + 8 + 1 + write-only - - - - U5_CONF0 - 0x3C - 0x20 - 0x00003C10 - - FILTER_THRES_U5 - This register is used to filter pluse whose width is smaller than this value for unit5. - 0 - 10 - read-write + FAULT0_INT_CLR + 9 + 1 + write-only - FILTER_EN_U5 - This is the enable bit for filtering input signals for unit5. + FAULT1_INT_CLR 10 1 - read-write + write-only - THR_ZERO_EN_U5 - This is the enable bit for comparing unit5's count with 0 value. + FAULT2_INT_CLR 11 1 - read-write + write-only - THR_H_LIM_EN_U5 - This is the enable bit for comparing unit5's count with thr_h_lim value. + FAULT0_CLR_INT_CLR 12 1 - read-write + write-only - THR_L_LIM_EN_U5 - This is the enable bit for comparing unit5's count with thr_l_lim value. + FAULT1_CLR_INT_CLR 13 1 - read-write + write-only - THR_THRES0_EN_U5 - This is the enable bit for comparing unit5's count with thres0 value. + FAULT2_CLR_INT_CLR 14 1 - read-write + write-only - THR_THRES1_EN_U5 - This is the enable bit for comparing unit5's count with thres1 value . + OP0_TEA_INT_CLR 15 1 - read-write + write-only - CH0_NEG_MODE_U5 - This register is used to control the mode of channel0's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + OP1_TEA_INT_CLR 16 - 2 - read-write + 1 + write-only + + + OP2_TEA_INT_CLR + 17 + 1 + write-only - CH0_POS_MODE_U5 - This register is used to control the mode of channel0's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + OP0_TEB_INT_CLR 18 - 2 - read-write + 1 + write-only + + + OP1_TEB_INT_CLR + 19 + 1 + write-only - CH0_HCTRL_MODE_U5 - This register is used to control the mode of channel0's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + OP2_TEB_INT_CLR 20 - 2 - read-write + 1 + write-only + + + FH0_CBC_INT_CLR + 21 + 1 + write-only - CH0_LCTRL_MODE_U5 - This register is used to control the mode of channel0's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + FH1_CBC_INT_CLR 22 - 2 - read-write + 1 + write-only + + + FH2_CBC_INT_CLR + 23 + 1 + write-only - CH1_NEG_MODE_U5 - This register is used to control the mode of channel1's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + FH0_OST_INT_CLR 24 - 2 - read-write + 1 + write-only + + + FH1_OST_INT_CLR + 25 + 1 + write-only - CH1_POS_MODE_U5 - This register is used to control the mode of channel1's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + FH2_OST_INT_CLR 26 - 2 - read-write + 1 + write-only - CH1_HCTRL_MODE_U5 - This register is used to control the mode of channel1's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CAP0_INT_CLR + 27 + 1 + write-only + + + CAP1_INT_CLR 28 - 2 - read-write + 1 + write-only - CH1_LCTRL_MODE_U5 - This register is used to control the mode of channel1's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write + CAP2_INT_CLR + 29 + 1 + write-only - U5_CONF1 - 0x40 + CLK + 0x120 0x20 - CNT_THRES0_U5 - This register is used to configure thres0 value for unit5. + EN 0 - 16 - read-write - - - CNT_THRES1_U5 - This register is used to configure thres1 value for unit5. - 16 - 16 + 1 read-write - U5_CONF2 - 0x44 + VERSION + 0x124 0x20 + 0x02107230 - CNT_H_LIM_U5 - This register is used to configure thr_h_lim value for unit5. + DATE 0 - 16 - read-write - - - CNT_L_LIM_U5 - This register is used to confiugre thr_l_lim value for unit5. - 16 - 16 + 28 read-write + + + + MCPWM1 + Motor Control Pulse-Width Modulation 1 + 0x3FF6C000 + + + NRX + NRX Peripheral + NRX + 0x3FF5CC00 + + 0x0 + 0x4 + registers + + - U6_CONF0 - 0x48 + NRXPD_CTRL + WiFi RX control register + 0xD4 0x20 - 0x00003C10 - FILTER_THRES_U6 - This register is used to filter pluse whose width is smaller than this value for unit6. + DEMAP_FORCE_PD 0 - 10 - read-write - - - FILTER_EN_U6 - This is the enable bit for filtering input signals for unit6. - 10 1 read-write - THR_ZERO_EN_U6 - This is the enable bit for comparing unit6's count with 0 value. - 11 + DEMAP_FORCE_PU + 1 1 read-write - THR_H_LIM_EN_U6 - This is the enable bit for comparing unit6's count with thr_h_lim value. - 12 + VIT_FORCE_PD + 2 1 read-write - THR_L_LIM_EN_U6 - This is the enable bit for comparing unit6's count with thr_l_lim value. - 13 + VIT_FORCE_PU + 3 1 read-write - THR_THRES0_EN_U6 - This is the enable bit for comparing unit6's count with thres0 value. - 14 + RX_ROT_FORCE_PD + 4 1 read-write - THR_THRES1_EN_U6 - This is the enable bit for comparing unit6's count with thres1 value . - 15 + RX_ROT_FORCE_PU + 5 1 read-write - CH0_NEG_MODE_U6 - This register is used to control the mode of channel0's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U6 - This register is used to control the mode of channel0's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U6 - This register is used to control the mode of channel0's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U6 - This register is used to control the mode of channel0's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U6 - This register is used to control the mode of channel1's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U6 - This register is used to control the mode of channel1's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U6 - This register is used to control the mode of channel1's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U6 - This register is used to control the mode of channel1's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U6_CONF1 - 0x4C - 0x20 - - - CNT_THRES0_U6 - This register is used to configure thres0 value for unit6. - 0 - 16 - read-write - - - CNT_THRES1_U6 - This register is used to configure thres1 value for unit6. - 16 - 16 - read-write - - - - - U6_CONF2 - 0x50 - 0x20 - - - CNT_H_LIM_U6 - This register is used to configure thr_h_lim value for unit6. - 0 - 16 + CHAN_EST_FORCE_PD + 6 + 1 read-write - CNT_L_LIM_U6 - This register is used to confiugre thr_l_lim value for unit6. - 16 - 16 + CHAN_EST_FORCE_PU + 7 + 1 read-write + + + + PCNT + Pulse Count Controller + PCNT + 0x3FF57000 + + 0x0 + 0xB8 + registers + + + PCNT + 48 + + - U7_CONF0 - 0x54 + 8 + 0xC + 0-7 + U%s_CONF0 + 0x0 0x20 0x00003C10 - FILTER_THRES_U7 - This register is used to filter pluse whose width is smaller than this value for unit7. + FILTER_THRES + This register is used to filter pluse whose width is smaller than this value for unit0. 0 10 read-write - FILTER_EN_U7 - This is the enable bit for filtering input signals for unit7. + FILTER_EN + This is the enable bit for filtering input signals for unit0. 10 1 read-write - THR_ZERO_EN_U7 - This is the enable bit for comparing unit7's count with 0 value. + THR_ZERO_EN + This is the enable bit for comparing unit0's count with 0 value. 11 1 read-write - THR_H_LIM_EN_U7 - This is the enable bit for comparing unit7's count with thr_h_lim value. + THR_H_LIM_EN + This is the enable bit for comparing unit0's count with thr_h_lim value. 12 1 read-write - THR_L_LIM_EN_U7 - This is the enable bit for comparing unit7's count with thr_l_lim value. + THR_L_LIM_EN + This is the enable bit for comparing unit0's count with thr_l_lim value. 13 1 read-write - THR_THRES0_EN_U7 - This is the enable bit for comparing unit7's count with thres0 value. + THR_THRES0_EN + This is the enable bit for comparing unit0's count with thres0 value. 14 1 read-write - THR_THRES1_EN_U7 - This is the enable bit for comparing unit7's count with thres1 value . + THR_THRES1_EN + This is the enable bit for comparing unit0's count with thres1 value . 15 1 read-write - CH0_NEG_MODE_U7 - This register is used to control the mode of channel0's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + CH0_NEG_MODE + This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write - CH0_POS_MODE_U7 - This register is used to control the mode of channel0's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + CH0_POS_MODE + This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write - CH0_HCTRL_MODE_U7 - This register is used to control the mode of channel0's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CH0_HCTRL_MODE + This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write - CH0_LCTRL_MODE_U7 - This register is used to control the mode of channel0's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CH0_LCTRL_MODE + This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write - CH1_NEG_MODE_U7 - This register is used to control the mode of channel1's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + CH1_NEG_MODE + This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write - CH1_POS_MODE_U7 - This register is used to control the mode of channel1's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + CH1_POS_MODE + This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write - CH1_HCTRL_MODE_U7 - This register is used to control the mode of channel1's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CH1_HCTRL_MODE + This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write - CH1_LCTRL_MODE_U7 - This register is used to control the mode of channel1's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + CH1_LCTRL_MODE + This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write @@ -23303,20 +22157,23 @@ - U7_CONF1 - 0x58 + 8 + 0xC + 0-7 + U%s_CONF1 + 0x4 0x20 - CNT_THRES0_U7 - This register is used to configure thres0 value for unit7. + CNT_THRES0 + This register is used to configure thres0 value for unit0. 0 16 read-write - CNT_THRES1_U7 - This register is used to configure thres1 value for unit7. + CNT_THRES1 + This register is used to configure thres1 value for unit0. 16 16 read-write @@ -23324,20 +22181,23 @@ - U7_CONF2 - 0x5C + 8 + 0xC + 0-7 + U%s_CONF2 + 0x8 0x20 - CNT_H_LIM_U7 - This register is used to configure thr_h_lim value for unit7. + CNT_H_LIM + This register is used to configure thr_h_lim value for unit0. 0 16 read-write - CNT_L_LIM_U7 - This register is used to confiugre thr_l_lim value for unit7. + CNT_L_LIM + This register is used to confiugre thr_l_lim value for unit0. 16 16 read-write @@ -23345,12 +22205,15 @@ - U0_CNT + 8 + 0x4 + 0-7 + U%s_CNT 0x60 0x20 - PLUS_CNT_U0 + CNT This register stores the current pulse count value for unit0. 0 16 @@ -23358,160 +22221,62 @@ - - U1_CNT - 0x64 - 0x20 - - - PLUS_CNT_U1 - This register stores the current pulse count value for unit1. - 0 - 16 - read-only - - - - - U2_CNT - 0x68 - 0x20 - - - PLUS_CNT_U2 - This register stores the current pulse count value for unit2. - 0 - 16 - read-only - - - - - U3_CNT - 0x6C - 0x20 - - - PLUS_CNT_U3 - This register stores the current pulse count value for unit3. - 0 - 16 - read-only - - - - - U4_CNT - 0x70 - 0x20 - - - PLUS_CNT_U4 - This register stores the current pulse count value for unit4. - 0 - 16 - read-only - - - - - U5_CNT - 0x74 - 0x20 - - - PLUS_CNT_U5 - This register stores the current pulse count value for unit5. - 0 - 16 - read-only - - - - - U6_CNT - 0x78 - 0x20 - - - PLUS_CNT_U6 - This register stores the current pulse count value for unit6. - 0 - 16 - read-only - - - - - U7_CNT - 0x7C - 0x20 - - - PLUS_CNT_U7 - This register stores the current pulse count value for unit7. - 0 - 16 - read-only - - - INT_RAW 0x80 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 This is the interrupt raw bit for channel0 event. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 This is the interrupt raw bit for channel1 event. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 This is the interrupt raw bit for channel2 event. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 This is the interrupt raw bit for channel3 event. 3 1 read-only - CNT_THR_EVENT_U4_INT_RAW + CNT_THR_EVENT_U4 This is the interrupt raw bit for channel4 event. 4 1 read-only - CNT_THR_EVENT_U5_INT_RAW + CNT_THR_EVENT_U5 This is the interrupt raw bit for channel5 event. 5 1 read-only - CNT_THR_EVENT_U6_INT_RAW + CNT_THR_EVENT_U6 This is the interrupt raw bit for channel6 event. 6 1 read-only - CNT_THR_EVENT_U7_INT_RAW + CNT_THR_EVENT_U7 This is the interrupt raw bit for channel7 event. 7 1 @@ -23525,56 +22290,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 This is the interrupt status bit for channel0 event. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 This is the interrupt status bit for channel1 event. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 This is the interrupt status bit for channel2 event. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 This is the interrupt status bit for channel3 event. 3 1 read-only - CNT_THR_EVENT_U4_INT_ST + CNT_THR_EVENT_U4 This is the interrupt status bit for channel4 event. 4 1 read-only - CNT_THR_EVENT_U5_INT_ST + CNT_THR_EVENT_U5 This is the interrupt status bit for channel5 event. 5 1 read-only - CNT_THR_EVENT_U6_INT_ST + CNT_THR_EVENT_U6 This is the interrupt status bit for channel6 event. 6 1 read-only - CNT_THR_EVENT_U7_INT_ST + CNT_THR_EVENT_U7 This is the interrupt status bit for channel7 event. 7 1 @@ -23588,56 +22353,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 This is the interrupt enable bit for channel0 event. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 This is the interrupt enable bit for channel1 event. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 This is the interrupt enable bit for channel2 event. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 This is the interrupt enable bit for channel3 event. 3 1 read-write - CNT_THR_EVENT_U4_INT_ENA + CNT_THR_EVENT_U4 This is the interrupt enable bit for channel4 event. 4 1 read-write - CNT_THR_EVENT_U5_INT_ENA + CNT_THR_EVENT_U5 This is the interrupt enable bit for channel5 event. 5 1 read-write - CNT_THR_EVENT_U6_INT_ENA + CNT_THR_EVENT_U6 This is the interrupt enable bit for channel6 event. 6 1 read-write - CNT_THR_EVENT_U7_INT_ENA + CNT_THR_EVENT_U7 This is the interrupt enable bit for channel7 event. 7 1 @@ -23651,56 +22416,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear channel0 event interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear channel1 event interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear channel2 event interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear channel3 event interrupt. 3 1 write-only - CNT_THR_EVENT_U4_INT_CLR + CNT_THR_EVENT_U4 Set this bit to clear channel4 event interrupt. 4 1 write-only - CNT_THR_EVENT_U5_INT_CLR + CNT_THR_EVENT_U5 Set this bit to clear channel5 event interrupt. 5 1 write-only - CNT_THR_EVENT_U6_INT_CLR + CNT_THR_EVENT_U6 Set this bit to clear channel6 event interrupt. 6 1 write-only - CNT_THR_EVENT_U7_INT_CLR + CNT_THR_EVENT_U7 Set this bit to clear channel7 event interrupt. 7 1 @@ -23709,7 +22474,10 @@ - U0_STATUS + 8 + 0x4 + 0-7 + U%s_STATUS 0x90 0x20 @@ -23720,134 +22488,43 @@ read-only - STATUS_CNT_MODE + ZERO_MODE 0 2 read-write - STATUS_THRES1 + THRES1 2 1 read-write - STATUS_THRES0 + THRES0 3 1 read-write - STATUS_L_LIM + L_LIM 4 1 read-write - STATUS_H_LIM + H_LIM 5 1 read-write - STATUS_ZERO + ZERO 6 1 read-write - - U1_STATUS - 0x94 - 0x20 - - - CORE_STATUS_U1 - 0 - 32 - read-only - - - - - U2_STATUS - 0x98 - 0x20 - - - CORE_STATUS_U2 - 0 - 32 - read-only - - - - - U3_STATUS - 0x9C - 0x20 - - - CORE_STATUS_U3 - 0 - 32 - read-only - - - - - U4_STATUS - 0xA0 - 0x20 - - - CORE_STATUS_U4 - 0 - 32 - read-only - - - - - U5_STATUS - 0xA4 - 0x20 - - - CORE_STATUS_U5 - 0 - 32 - read-only - - - - - U6_STATUS - 0xA8 - 0x20 - - - CORE_STATUS_U6 - 0 - 32 - read-only - - - - - U7_STATUS - 0xAC - 0x20 - - - CORE_STATUS_U7 - 0 - 32 - read-only - - - CTRL 0xB0 @@ -23855,7 +22532,7 @@ 0x00005555 - PLUS_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit0's counter. 0 1 @@ -23869,7 +22546,7 @@ read-write - PLUS_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit1's counter. 2 1 @@ -23883,7 +22560,7 @@ read-write - PLUS_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit2's counter. 4 1 @@ -23897,7 +22574,7 @@ read-write - PLUS_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit3's counter. 6 1 @@ -23911,7 +22588,7 @@ read-write - PLUS_CNT_RST_U4 + CNT_RST_U4 Set this bit to clear unit4's counter. 8 1 @@ -23925,7 +22602,7 @@ read-write - PLUS_CNT_RST_U5 + CNT_RST_U5 Set this bit to clear unit5's counter. 10 1 @@ -23939,7 +22616,7 @@ read-write - PLUS_CNT_RST_U6 + CNT_RST_U6 Set this bit to clear unit6's counter. 12 1 @@ -23953,7 +22630,7 @@ read-write - PLUS_CNT_RST_U7 + CNT_RST_U7 Set this bit to clear unit7's counter. 14 1 @@ -23992,7 +22669,7 @@ RMT - Remote Control Peripheral + Remote Control RMT 0x3FF56000 @@ -24006,43 +22683,11 @@ - CH0DATA - 0x0 - 0x20 - - - CH1DATA - 0x4 - 0x20 - - - CH2DATA - 0x8 - 0x20 - - - CH3DATA - 0xC - 0x20 - - - CH4DATA - 0x10 - 0x20 - - - CH5DATA - 0x14 - 0x20 - - - CH6DATA - 0x18 - 0x20 - - - CH7DATA - 0x1C + 8 + 0x4 + 0-7 + CH%sDATA + 0x0 0x20 @@ -24208,7 +22853,10 @@ - CH0STATUS + 8 + 0x4 + 0-7 + CH%sSTATUS 0x60 0x20 @@ -24278,497 +22926,10 @@ - CH1STATUS - 0x64 - 0x20 - - - STATUS - The status for channel1 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel1. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel1. - 12 - 10 - read-only - - - STATE - The channel1 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel1 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel1 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel1. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel1 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel1 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH2STATUS - 0x68 - 0x20 - - - STATUS - The status for channel2 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel2. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel2. - 12 - 10 - read-only - - - STATE - The channel2 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel2 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel2 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel2. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel2 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel2 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH3STATUS - 0x6C - 0x20 - - - STATUS - The status for channel3 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel3. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel3. - 12 - 10 - read-only - - - STATE - The channel3 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel3 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel3 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel3. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel3 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel3 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH4STATUS - 0x70 - 0x20 - - - STATUS - The status for channel4 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel4. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel4. - 12 - 10 - read-only - - - STATE - The channel4 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel4 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel4 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel4. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel4 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel4 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH5STATUS - 0x74 - 0x20 - - - STATUS - The status for channel5 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel5. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel5. - 12 - 10 - read-only - - - STATE - The channel5 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel5 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel5 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel5. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel5 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel5 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH6STATUS - 0x78 - 0x20 - - - STATUS - The status for channel6 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel6. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel6. - 12 - 10 - read-only - - - STATE - The channel6 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel6 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel6 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel6. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel6 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel6 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH7STATUS - 0x7C - 0x20 - - - STATUS - The status for channel7 - 0 - 32 - read-only - - - MEM_WADDR_EX - The current memory read address of channel7. - 0 - 10 - read-only - - - MEM_RADDR_EX - The current memory write address of channel7. - 12 - 10 - read-only - - - STATE - The channel7 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. - 24 - 3 - read-only - - - MEM_OWNER_ERR - When channel7 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. - 27 - 1 - read-only - - - MEM_FULL - The memory full status bit for channel7 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. - 28 - 1 - read-only - - - MEM_EMPTY - The memory empty status bit for channel7. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. - 29 - 1 - read-only - - - APB_MEM_WR_ERR - The apb write memory status bit for channel7 turns to high level when the apb write address exceeds the configuration range. - 30 - 1 - read-only - - - APB_MEM_RD_ERR - The apb read memory status bit for channel7 turns to high level when the apb read address exceeds the configuration range. - 31 - 1 - read-only - - - - - CH0ADDR + 8 + 0x4 + 0-7 + CH%sADDR 0x80 0x20 @@ -24781,104 +22942,6 @@ - - CH1ADDR - 0x84 - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel1 by apb fifo access - 0 - 32 - read-only - - - - - CH2ADDR - 0x88 - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel2 by apb fifo access - 0 - 32 - read-only - - - - - CH3ADDR - 0x8C - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel3 by apb fifo access - 0 - 32 - read-only - - - - - CH4ADDR - 0x90 - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel4 by apb fifo access - 0 - 32 - read-only - - - - - CH5ADDR - 0x94 - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel5 by apb fifo access - 0 - 32 - read-only - - - - - CH6ADDR - 0x98 - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel6 by apb fifo access - 0 - 32 - read-only - - - - - CH7ADDR - 0x9C - 0x20 - - - APB_MEM_ADDR - The ram relative address in channel7 by apb fifo access - 0 - 32 - read-only - - - INT_RAW 0xA0 @@ -24888,7 +22951,7 @@ 8 0x3 0-7 - CH%s_TX_END_INT_RAW + CH%s_TX_END The interrupt raw bit for channel %s turns to high level when the transmit process is done. 0 1 @@ -24898,7 +22961,7 @@ 8 0x3 0-7 - CH%s_RX_END_INT_RAW + CH%s_RX_END The interrupt raw bit for channel %s turns to high level when the receive process is done. 1 1 @@ -24908,7 +22971,7 @@ 8 0x3 0-7 - CH%s_ERR_INT_RAW + CH%s_ERR The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. 2 1 @@ -24918,7 +22981,7 @@ 8 0x1 0-7 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. 24 1 @@ -24935,7 +22998,7 @@ 8 0x3 0-7 - CH%s_TX_END_INT_ST + CH%s_TX_END The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. 0 1 @@ -24945,7 +23008,7 @@ 8 0x3 0-7 - CH%s_RX_END_INT_ST + CH%s_RX_END The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. 1 1 @@ -24955,7 +23018,7 @@ 8 0x3 0-7 - CH%s_ERR_INT_ST + CH%s_ERR The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. 2 1 @@ -24965,7 +23028,7 @@ 8 0x1 0-7 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. 24 1 @@ -24982,7 +23045,7 @@ 8 0x3 0-7 - CH%s_TX_END_INT_ENA + CH%s_TX_END Set this bit to enable rmt_ch%s_tx_end_int_st. 0 1 @@ -24992,7 +23055,7 @@ 8 0x3 0-7 - CH%s_RX_END_INT_ENA + CH%s_RX_END Set this bit to enable rmt_ch%s_rx_end_int_st. 1 1 @@ -25002,7 +23065,7 @@ 8 0x3 0-7 - CH%s_ERR_INT_ENA + CH%s_ERR Set this bit to enable rmt_ch%s_err_int_st. 2 1 @@ -25012,7 +23075,7 @@ 8 0x1 0-7 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT Set this bit to enable rmt_ch%s_tx_thr_event_int_st. 24 1 @@ -25029,7 +23092,7 @@ 8 0x3 0-7 - CH%s_TX_END_INT_CLR + CH%s_TX_END Set this bit to clear the rmt_ch%s_rx_end_int_raw.. 0 1 @@ -25039,7 +23102,7 @@ 8 0x3 0-7 - CH%s_RX_END_INT_CLR + CH%s_RX_END Set this bit to clear the rmt_ch%s_tx_end_int_raw. 1 1 @@ -25049,7 +23112,7 @@ 8 0x3 0-7 - CH%s_ERR_INT_CLR + CH%s_ERR Set this bit to clear the rmt_ch%s_err_int_raw. 2 1 @@ -25059,7 +23122,7 @@ 8 0x1 0-7 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. 24 1 @@ -25068,7 +23131,10 @@ - CH0CARRIER_DUTY + 8 + 0x4 + 0-7 + CH%sCARRIER_DUTY 0xB0 0x20 0x00400040 @@ -25089,160 +23155,6 @@ - - CH1CARRIER_DUTY - 0xB4 - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel1. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel1. - 16 - 16 - read-write - - - - - CH2CARRIER_DUTY - 0xB8 - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel2. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel2. - 16 - 16 - read-write - - - - - CH3CARRIER_DUTY - 0xBC - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel3. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel3. - 16 - 16 - read-write - - - - - CH4CARRIER_DUTY - 0xC0 - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel4. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel4. - 16 - 16 - read-write - - - - - CH5CARRIER_DUTY - 0xC4 - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel5. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel5. - 16 - 16 - read-write - - - - - CH6CARRIER_DUTY - 0xC8 - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel6. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel6. - 16 - 16 - read-write - - - - - CH7CARRIER_DUTY - 0xCC - 0x20 - 0x00400040 - - - CARRIER_LOW - This register is used to configure carrier wave's low level value for channel7. - 0 - 16 - read-write - - - CARRIER_HIGH - This register is used to configure carrier wave's high level value for channel7. - 16 - 16 - read-write - - - 8 0x4 @@ -25301,7 +23213,7 @@ RNG - Hardware random number generator + Hardware Random Number Generator RNG 0x60035000 @@ -25315,6 +23227,7 @@ Random number data 0x144 0x20 + read-only @@ -25335,7 +23248,7 @@ M_PRIME - 0x0 + 0x800 0x20 @@ -25349,21 +23262,21 @@ MODEXP_MODE - 0x4 + 0x804 0x20 MODEXP_MODE This register contains the mode of modular exponentiation. 0 - 2 + 3 read-write MODEXP_START - 0x8 + 0x808 0x20 @@ -25377,21 +23290,21 @@ MULT_MODE - 0xC + 0x80C 0x20 MULT_MODE This register contains the mode of modular multiplication and multiplication. 0 - 1 + 4 read-write MULT_START - 0x10 + 0x810 0x20 @@ -25405,7 +23318,7 @@ INTERRUPT - 0x14 + 0x814 0x20 @@ -25419,7 +23332,7 @@ CLEAN - 0x18 + 0x818 0x20 @@ -25431,6 +23344,42 @@ + + 32 + 0x4 + M_MEM[%s] + Represents M + 0x0 + 0x20 + read-write + + + 32 + 0x4 + Z_MEM[%s] + Represents Z + 0x200 + 0x20 + read-write + + + 32 + 0x4 + Y_MEM[%s] + Represents Y + 0x400 + 0x20 + read-write + + + 32 + 0x4 + X_MEM[%s] + Represents X + 0x600 + 0x20 + read-write + @@ -26573,20 +24522,26 @@ 2 read-write + CK8M_DIV + read-write DIV128 + DIV128 0 DIV256 + DIV256 1 DIV512 + DIV512 2 DIV1024 + DIV1024 3 @@ -26605,12 +24560,16 @@ 1 read-write + ENB_CK8M_DIV + read-write CK8M_DIV_256 + CK8M_DIV_256 0 CK8M + CK8M 1 @@ -26691,20 +24650,26 @@ 2 read-write + SOC_CLK_SEL + read-write XTAL + XTAL 0 PLL + PLL 1 CK8M + CK8M 2 APLL + APLL 3 @@ -26716,12 +24681,16 @@ 1 read-write + FAST_CLK_RTC_SEL + read-write XTAL_DIV_4 + XTAL_DIV_4 0 CK8M + CK8M 1 @@ -26733,16 +24702,21 @@ 2 read-write + ANA_CLK_RTC_SEL + read-write SLOW_CK + SLOW_CK 0 CK_XTAL_32K + CK_XTAL_32K 1 CK8M_D256_OUT + CK8M_D256_OUT 2 @@ -27766,7 +25740,7 @@ RDY_FOR_WAKEUP - 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise + 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise 19 1 read-only @@ -28040,8 +26014,8 @@ - RTCIO - Peripheral RTCIO + RTC_IO + Low-power Input/Output RTC_GPIO 0x3FF48400 @@ -28193,26 +26167,27 @@ 18 0x4 + 0-17 PIN%s 0x28 0x20 - PIN_PAD_DRIVER - if set to : normal output if set to 1: open drain + PAD_DRIVER + if set to 0: normal output if set to 1: open drain 2 1 read-write - PIN_INT_TYPE - if set to : GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger + INT_TYPE + if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE GPIO wake up enable only available in light sleep 10 1 @@ -30044,7 +28019,7 @@ RTC_I2C - Peripheral RTC_I2C + Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x3FF48C00 @@ -30060,7 +28035,7 @@ SCL_LOW_PERIOD - number of cycles that scl == 0 + number of cycles that scl == 0 0 25 read-write @@ -30074,42 +28049,42 @@ SDA_FORCE_OUT - SDA is push-pull (1) or open-drain (0) + SDA is push-pull (1) or open-drain (0) 0 1 read-write SCL_FORCE_OUT - SCL is push-pull (1) or open-drain (0) + SCL is push-pull (1) or open-drain (0) 1 1 read-write MS_MODE - Master (1) or slave (0) + Master (1) or slave (0) 4 1 read-write TRANS_START - Force to generate start condition + Force to generate start condition 5 1 read-write TX_LSB_FIRST - Send LSB first + Send LSB first 6 1 read-write RX_LSB_FIRST - Receive LSB first + Receive LSB first 7 1 read-write @@ -30123,63 +28098,63 @@ ACK_VAL - The value of an acknowledge signal on the bus + The value of an acknowledge signal on the bus 0 1 read-write SLAVE_RW - When working as a slave, the value of R/W bit received + When working as a slave, the value of R/W bit received 1 1 read-write TIMED_OUT - Transfer has timed out + Transfer has timed out 2 1 read-write ARB_LOST - When working as a master, lost control of I2C bus + When working as a master, lost control of I2C bus 3 1 read-write BUS_BUSY - operation is in progress + operation is in progress 4 1 read-write SLAVE_ADDR_MATCH - When working as a slave, whether address was matched + When working as a slave, whether address was matched 5 1 read-write BYTE_TRANS - 8 bit transmit done + 8 bit transmit done 6 1 read-write MAIN_STATE - state of the main state machine + state of the main state machine 25 3 read-write SCL_STATE - state of SCL state machine + state of SCL state machine 28 3 read-write @@ -30193,7 +28168,7 @@ TIMEOUT - Maximum number of FAST_CLK cycles that the transmission can take + Maximum number of FAST_CLK cycles that the transmission can take 0 20 read-write @@ -30207,14 +28182,14 @@ SLAVE_ADDR - local slave address + local slave address 0 15 read-write _10BIT - Set if local slave address is 10-bit + Set if local slave address is 10-bit 31 1 read-write @@ -30233,14 +28208,14 @@ SLAVE_TRANS_COMPLETE_INT_RAW - Slave accepted 1 byte and address matched + Slave accepted 1 byte and address matched 3 1 read-write ARBITRATION_LOST_INT_RAW - Master lost arbitration + Master lost arbitration 4 1 read-write @@ -30253,14 +28228,14 @@ TRANS_COMPLETE_INT_RAW - Stop condition has been detected interrupt raw status + Stop condition has been detected interrupt raw status 6 1 read-write TIME_OUT_INT_RAW - time out interrupt raw status + time out interrupt raw status 7 1 read-only @@ -30321,7 +28296,7 @@ SDA_DUTY - Number of FAST_CLK cycles SDA will switch after falling edge of SCL + Number of FAST_CLK cycles SDA will switch after falling edge of SCL 0 20 read-write @@ -30335,7 +28310,7 @@ SCL_HIGH_PERIOD - Number of FAST_CLK cycles for SCL to be high + Number of FAST_CLK cycles for SCL to be high 0 20 read-write @@ -30349,7 +28324,7 @@ SCL_START_PERIOD - Number of FAST_CLK cycles to wait before generating start condition + Number of FAST_CLK cycles to wait before generating start condition 0 20 read-write @@ -30363,7 +28338,7 @@ SCL_STOP_PERIOD - Number of FAST_CLK cycles to wait before generating stop condition + Number of FAST_CLK cycles to wait before generating stop condition 0 20 read-write @@ -30377,14 +28352,14 @@ VAL - Command content + Command content 0 14 read-write DONE - Bit is set by HW when command is done + Bit is set by HW when command is done 31 1 read-write @@ -30394,7 +28369,7 @@ - SDMMC + SDHOST SD/MMC Host Controller SDHOST 0x3FF68000 @@ -31767,7 +29742,7 @@ IDINTEN[4]: DU Interrupt. SENS - Peripheral SENS + SENS Peripheral SENS 0x3FF48800 @@ -33128,7 +31103,7 @@ IDINTEN[4]: DU Interrupt. 32 0x4 - TEXT_%s + TEXT%s 0x0 0x20 @@ -33136,7 +31111,7 @@ IDINTEN[4]: DU Interrupt. TEXT SHA Message block and hash result register. 0 - 8 + 32 read-write @@ -33157,7 +31132,7 @@ IDINTEN[4]: DU Interrupt. SHA1_CONTINUE - 0x80 + 0x84 0x20 @@ -33193,7 +31168,7 @@ IDINTEN[4]: DU Interrupt. SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 - write-only + read-only @@ -33213,7 +31188,7 @@ IDINTEN[4]: DU Interrupt. SHA256_LOAD - 0x90 + 0x98 0x20 @@ -33369,7 +31344,7 @@ IDINTEN[4]: DU Interrupt. SLC - Peripheral SLC + SLC Peripheral SLC 0x3FF58000 @@ -37030,7 +35005,7 @@ IDINTEN[4]: DU Interrupt. SLCHOST - Peripheral SLCHOST + SLCHOST Peripheral SLCHOST 0x3FF55000 @@ -40494,7 +38469,7 @@ IDINTEN[4]: DU Interrupt. SPI0 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 0 SPI 0x3FF43000 @@ -42715,7 +40690,7 @@ IDINTEN[4]: DU Interrupt. SPI1 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 1 0x3FF42000 SPI1 @@ -42728,7 +40703,7 @@ IDINTEN[4]: DU Interrupt. SPI2 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 2 0x3FF64000 SPI2 @@ -42741,7 +40716,7 @@ IDINTEN[4]: DU Interrupt. SPI3 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 3 0x3FF65000 SPI3 @@ -42754,7 +40729,7 @@ IDINTEN[4]: DU Interrupt. TIMG0 - Timer Group + Timer Group 0 TIMG 0x3FF5F000 @@ -42802,49 +40777,49 @@ IDINTEN[4]: DU Interrupt. 0x60002000 - T0_ALARM_EN + ALARM_EN When set alarm is enabled 10 1 read-write - T0_LEVEL_INT_EN + LEVEL_INT_EN When set level type interrupt will be generated during alarm 11 1 read-write - T0_EDGE_INT_EN + EDGE_INT_EN When set edge type interrupt will be generated during alarm 12 1 read-write - T0_DIVIDER + DIVIDER Timer 0 clock (T0_clk) prescale value. 13 16 read-write - T0_AUTORELOAD + AUTORELOAD When set timer 0 auto-reload at alarming is enabled 29 1 read-write - T0_INCREASE + INCREASE When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement. 30 1 read-write - T0_EN + EN When set timer 0 time-base counter is enabled 31 1 @@ -42858,7 +40833,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_LO + LO Register to store timer 0 time-base counter current value lower 32 bits. 0 32 @@ -42872,7 +40847,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_HI + HI Register to store timer 0 time-base counter current value higher 32 bits. 0 32 @@ -42886,7 +40861,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_UPDATE + UPDATE Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above) 0 32 @@ -42900,7 +40875,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_ALARM_LO + ALARM_LO Timer 0 time-base counter value lower 32 bits that will trigger the alarm 0 32 @@ -42914,7 +40889,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_ALARM_HI + ALARM_HI Timer 0 time-base counter value higher 32 bits that will trigger the alarm 0 32 @@ -42928,7 +40903,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_LOAD_LO + LOAD_LO Lower 32 bits of the value that will load into timer 0 time-base counter 0 32 @@ -42942,7 +40917,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_LOAD_HI + LOAD_HI higher 32 bits of the value that will load into timer 0 time-base counter 0 32 @@ -42956,7 +40931,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T0_LOAD + LOAD Write any value will trigger timer 0 time-base counter reload 0 32 @@ -42971,49 +40946,49 @@ IDINTEN[4]: DU Interrupt. 0x60002000 - T1_ALARM_EN + ALARM_EN When set alarm is enabled 10 1 read-write - T1_LEVEL_INT_EN + LEVEL_INT_EN When set level type interrupt will be generated during alarm 11 1 read-write - T1_EDGE_INT_EN + EDGE_INT_EN When set edge type interrupt will be generated during alarm 12 1 read-write - T1_DIVIDER + DIVIDER Timer 1 clock (T1_clk) prescale value. 13 16 read-write - T1_AUTORELOAD + AUTORELOAD When set timer 1 auto-reload at alarming is enabled 29 1 read-write - T1_INCREASE + INCREASE When set timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement. 30 1 read-write - T1_EN + EN When set timer 1 time-base counter is enabled 31 1 @@ -43027,7 +41002,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_LO + LO Register to store timer 1 time-base counter current value lower 32 bits. 0 32 @@ -43041,7 +41016,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_HI + HI Register to store timer 1 time-base counter current value higher 32 bits. 0 32 @@ -43055,7 +41030,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_UPDATE + UPDATE Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above) 0 32 @@ -43069,7 +41044,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_ALARM_LO + ALARM_LO Timer 1 time-base counter value lower 32 bits that will trigger the alarm 0 32 @@ -43083,7 +41058,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_ALARM_HI + ALARM_HI Timer 1 time-base counter value higher 32 bits that will trigger the alarm 0 32 @@ -43097,7 +41072,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_LOAD_LO + LOAD_LO Lower 32 bits of the value that will load into timer 1 time-base counter 0 32 @@ -43111,7 +41086,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_LOAD_HI + LOAD_HI higher 32 bits of the value that will load into timer 1 time-base counter 0 32 @@ -43125,7 +41100,7 @@ IDINTEN[4]: DU Interrupt. 0x20 - T1_LOAD + LOAD Write any value will trigger timer 1 time-base counter reload 0 32 @@ -43152,6 +41127,50 @@ IDINTEN[4]: DU Interrupt. 15 3 read-write + + WDT_SYS_RESET_LENGTH + read-write + + NS100 + 100ns + 0 + + + NS200 + 200ns + 1 + + + NS300 + 300ns + 2 + + + NS400 + 400ns + 3 + + + NS500 + 500ns + 4 + + + NS800 + 800ns + 5 + + + NS1600 + 1.6us + 6 + + + NS3200 + 3.2us + 7 + + WDT_CPU_RESET_LENGTH @@ -43159,6 +41178,50 @@ IDINTEN[4]: DU Interrupt. 18 3 read-write + + WDT_CPU_RESET_LENGTH + read-write + + NS100 + 100ns + 0 + + + NS200 + 200ns + 1 + + + NS300 + 300ns + 2 + + + NS400 + 400ns + 3 + + + NS500 + 500ns + 4 + + + NS800 + 800ns + 5 + + + NS1600 + 1.6us + 6 + + + NS3200 + 3.2us + 7 + + WDT_LEVEL_INT_EN @@ -43180,6 +41243,30 @@ IDINTEN[4]: DU Interrupt. 23 2 read-write + + WDT_STG3 + read-write + + OFF + Off + 0 + + + INTERRUPT + Interrupt + 1 + + + RESET + Reset CPU + 2 + + + RESET_SYS + Reset system + 3 + + WDT_STG2 @@ -43187,6 +41274,7 @@ IDINTEN[4]: DU Interrupt. 25 2 read-write + WDT_STG1 @@ -43194,6 +41282,7 @@ IDINTEN[4]: DU Interrupt. 27 2 read-write + WDT_STG0 @@ -43201,6 +41290,7 @@ IDINTEN[4]: DU Interrupt. 29 2 read-write + WDT_EN @@ -43720,7 +41810,7 @@ IDINTEN[4]: DU Interrupt. TIMG1 - Timer Group + Timer Group 1 0x3FF60000 TG1_T0_LEVEL @@ -43756,7 +41846,7 @@ IDINTEN[4]: DU Interrupt. - TWAI + TWAI0 Two-Wire Automotive Interface TWAI 0x3FF6B000 @@ -43766,7 +41856,7 @@ IDINTEN[4]: DU Interrupt. registers - TWAI + TWAI0 45 @@ -43912,6 +42002,13 @@ IDINTEN[4]: DU Interrupt. 1 read-only + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + @@ -44039,12 +42136,14 @@ IDINTEN[4]: DU Interrupt. Baud Rate Prescaler, determines the frequency dividing ratio. 0 6 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 6 2 + read-write @@ -44059,18 +42158,21 @@ IDINTEN[4]: DU Interrupt. The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 - 4 + 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -44130,6 +42232,7 @@ IDINTEN[4]: DU Interrupt. Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -44144,7 +42247,7 @@ IDINTEN[4]: DU Interrupt. The RX error counter register, reflects value changes under reception status. 0 8 - read-only + read-write @@ -44159,6 +42262,7 @@ IDINTEN[4]: DU Interrupt. The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -44173,7 +42277,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44188,7 +42292,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44203,7 +42307,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44218,7 +42322,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44233,7 +42337,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44248,7 +42352,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44263,7 +42367,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44278,7 +42382,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44293,7 +42397,7 @@ IDINTEN[4]: DU Interrupt. Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44308,7 +42412,7 @@ IDINTEN[4]: DU Interrupt. Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44323,7 +42427,7 @@ IDINTEN[4]: DU Interrupt. Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44338,7 +42442,7 @@ IDINTEN[4]: DU Interrupt. Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44353,7 +42457,7 @@ IDINTEN[4]: DU Interrupt. Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -44382,20 +42486,15 @@ IDINTEN[4]: DU Interrupt. CD These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. 0 - 3 + 8 read-write CLOCK_OFF This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin - 3 - 1 - - - EXT_MODE - This bit can be configured under reset mode. 1: Extended mode, compatible with CAN2.0B; 0: Basic mode - 7 + 8 1 + read-write @@ -44403,7 +42502,7 @@ IDINTEN[4]: DU Interrupt. UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x3FF40000 @@ -45676,42 +43775,42 @@ IDINTEN[4]: DU Interrupt. RX_FLOW_THRHD_H3 - refer to the rx_flow_thrhd's describtion. + Refer to the rx_flow_thrhd's description. 15 3 read-write RX_TOUT_THRHD_H3 - refer to the rx_tout_thrhd's describtion. + Refer to the rx_tout_thrhd's description. 18 3 read-write XON_THRESHOLD_H2 - refer to the uart_xon_threshold's describtion. + Refer to the uart_xon_threshold's description. 21 2 read-write XOFF_THRESHOLD_H2 - refer to the uart_xoff_threshold's describtion. + Refer to the uart_xoff_threshold's description. 23 2 read-write RX_MEM_FULL_THRHD - refer to the rxfifo_full_thrhd's describtion. + Refer to the rxfifo_full_thrhd's description. 25 3 read-write TX_MEM_EMPTY_THRHD - refer to txfifo_empty_thrhd 's describtion. + Refer to txfifo_empty_thrhd's description. 28 3 read-write @@ -45738,21 +43837,21 @@ IDINTEN[4]: DU Interrupt. MEM_RX_STATUS - This register stores the current uart rx mem read address and rx mem write address + This register stores the current uart rx mem read address and rx mem write address 0 24 read-only MEM_RX_RD_ADDR - This register stores the rx mem read address + This register stores the rx mem read address 2 11 read-only MEM_RX_WR_ADDR - This register stores the rx mem write address + This register stores the rx mem write address 13 11 read-only @@ -45766,14 +43865,14 @@ IDINTEN[4]: DU Interrupt. RX_MEM_CNT - refer to the rxfifo_cnt's describtion. + Refer to the rxfifo_cnt's description. 0 3 read-only TX_MEM_CNT - refer to the txfifo_cnt's describtion. + Refer to the txfifo_cnt's description. 3 3 read-only @@ -45842,7 +43941,7 @@ IDINTEN[4]: DU Interrupt. UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x3FF50000 UART1 @@ -45851,7 +43950,7 @@ IDINTEN[4]: DU Interrupt. UART2 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 0x3FF6E000 UART2 @@ -45860,7 +43959,7 @@ IDINTEN[4]: DU Interrupt. UHCI0 - Universal Host Controller Interface + Universal Host Controller Interface 0 UHCI 0x3FF54000 @@ -47462,7 +45561,7 @@ IDINTEN[4]: DU Interrupt. UHCI1 - Universal Host Controller Interface + Universal Host Controller Interface 1 0x3FF4C000 UHCI1 diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c2.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c2.svd index 5fd918345..325e7120c 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c2.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c2.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C2 - ESP32-C2 - 2 - 32-bit RISC-V MCU - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + ESP32 C-Series + 10 + 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. RV32IMC r0p0 little false false - 4 + 0 false 32 @@ -37,7 +35,7 @@ APB_CTRL - Advanced Peripheral Bus Controller + APB (Advanced Peripheral Bus) Controller APB_CTRL 0x60026000 @@ -545,7 +543,7 @@ - REDCY_SIG0_REG + REDCY_SIG0 APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 @@ -567,7 +565,7 @@ - REDCY_SIG1_REG + REDCY_SIG1 APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 @@ -760,7 +758,7 @@ - PERI_BACKUP_CONFIG_REG + PERI_BACKUP_CONFIG APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 @@ -818,7 +816,7 @@ - PERI_BACKUP_APB_ADDR_REG + PERI_BACKUP_APB_ADDR APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 @@ -833,7 +831,7 @@ - PERI_BACKUP_MEM_ADDR_REG + PERI_BACKUP_MEM_ADDR APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 @@ -955,7 +953,7 @@ APB_SARADC - Successive Approximation Register Analog to Digital Converter + SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x60040000 @@ -1862,22 +1860,27 @@ 0x38 registers + + ASSIST_DEBUG + Assist debug interrupt + 40 + - CORE_0_INTR_ENA + CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 - CORE_0_AREA_DRAM0_0_RD_ENA + CORE_0_SP_SPILL_MIN_ENA enbale sp underlow monitor 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_ENA + CORE_0_SP_SPILL_MAX_ENA enbale sp overflow monitor 1 1 @@ -1892,14 +1895,14 @@ 0x20 - CORE_0_AREA_DRAM0_0_RD_RAW + CORE_0_SP_SPILL_MIN_RAW sp underlow monitor interrupt status register 0 1 read-only - CORE_0_AREA_DRAM0_0_WR_RAW + CORE_0_SP_SPILL_MAX_RAW sp overflow monitor interupt status register 1 1 @@ -1908,20 +1911,20 @@ - CORE_0_INTR_RLS + CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS + CORE_0_SP_SPILL_MIN_INTR_ENA enbale sp underlow monitor interrupt 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_RLS + CORE_0_SP_SPILL_MAX_INTR_ENA enbale sp overflow monitor interrupt 1 1 @@ -1936,14 +1939,14 @@ 0x20 - CORE_0_AREA_DRAM0_0_RD_CLR + CORE_0_SP_SPILL_MIN_CLR clr sp underlow monitor interrupt 0 1 write-only - CORE_0_AREA_DRAM0_0_WR_CLR + CORE_0_SP_SPILL_MAX_CLR clr sp overflow monitor interrupt 1 1 @@ -2120,6 +2123,51 @@ + + BB + BB Peripheral + BB + 0x6001D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + DMA DMA (Direct Memory Access) Controller @@ -2136,101 +2184,104 @@ - INT_RAW_CH0 - DMA_INT_RAW_CH0_REG. + 1 + 0x4 + 0-0 + INT_RAW_CH%s + DMA_INT_RAW_CH%s_REG. 0x0 0x20 - IN_DONE_CH0_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 - read-only + read-write - IN_SUC_EOF_CH0_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 - read-only + read-write - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 - read-only + read-write - OUT_DONE_CH0_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 - read-only + read-write - OUT_EOF_CH0_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 - read-only + read-write - IN_DSCR_ERR_CH0_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 - read-only + read-write - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 - read-only + read-write - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 - read-only + read-write - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 - read-only + read-write - INFIFO_OVF_CH0_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 - read-only + read-write - INFIFO_UDF_CH0_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 - read-only + read-write - OUTFIFO_OVF_CH0_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 - read-only + read-write - OUTFIFO_UDF_CH0_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 - read-only + read-write @@ -2241,91 +2292,91 @@ 0x20 - IN_DONE_CH0_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH0_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH0_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH0_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH0_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH0_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2334,97 +2385,100 @@ - INT_ENA_CH0 - DMA_INT_ENA_CH0_REG. + 1 + 0x4 + 0-0 + INT_ENA_CH%s + DMA_INT_ENA_CH%s_REG. 0x8 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH0_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH0_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH0_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH0_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH0_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2433,97 +2487,100 @@ - INT_CLR_CH0 - DMA_INT_CLR_CH0_REG. + 1 + 0x4 + 0-0 + INT_CLR_CH%s + DMA_INT_CLR_CH%s_REG. 0xC 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH0_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH0_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH0_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH0_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH0_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2599,41 +2656,44 @@ - IN_CONF0_CH0 - DMA_IN_CONF0_CH0_REG. + 1 + 0x4 + 0-0 + IN_CONF0_CH%s + DMA_IN_CONF%s_CH%s_REG. 0x70 0x20 - IN_RST_CH0 + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH0 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH0 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH0 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -2648,7 +2708,7 @@ 0x20 - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -2664,56 +2724,56 @@ 0x07800003 - INFIFO_FULL_CH0 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_CH0 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_CNT_CH0 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only - IN_REMAIN_UNDER_1B_CH0 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH0 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH0 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH0 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH0 + IN_BUF_HUNGRY reserved 27 1 @@ -2729,14 +2789,14 @@ 0x00000800 - INFIFO_RDATA_CH0 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH0 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -2745,49 +2805,52 @@ - IN_LINK_CH0 - DMA_IN_LINK_CH0_REG. + 1 + 0x4 + 0-0 + IN_LINK_CH%s + DMA_IN_LINK_CH%s_REG. 0x80 0x20 0x01100000 - INLINK_ADDR_CH0 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -2802,21 +2865,21 @@ 0x20 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH0 + IN_STATE reserved 20 3 @@ -2831,7 +2894,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -2846,7 +2909,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -2861,7 +2924,7 @@ 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -2870,13 +2933,16 @@ - IN_DSCR_BF0_CH0 - DMA_IN_DSCR_BF0_CH0_REG. + 1 + 0x4 + 0-0 + IN_DSCR_BF0_CH%s + DMA_IN_DSCR_BF%s_CH%s_REG. 0x94 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -2891,7 +2957,7 @@ 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -2900,13 +2966,16 @@ - IN_PRI_CH0 - DMA_IN_PRI_CH0_REG. + 1 + 0x4 + 0-0 + IN_PRI_CH%s + DMA_IN_PRI_CH%s_REG. 0x9C 0x20 - RX_PRI_CH0 + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -2915,14 +2984,17 @@ - IN_PERI_SEL_CH0 - DMA_IN_PERI_SEL_CH0_REG. + 1 + 0x4 + 0-0 + IN_PERI_SEL_CH%s + DMA_IN_PERI_SEL_CH%s_REG. 0xA0 0x20 0x0000003F - PERI_IN_SEL_CH0 + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -2931,49 +3003,52 @@ - OUT_CONF0_CH0 - DMA_OUT_CONF0_CH0_REG. + 1 + 0x4 + 0-0 + OUT_CONF0_CH%s + DMA_OUT_CONF%s_CH%s_REG. 0xD0 0x20 0x00000008 - OUT_RST_CH0 + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH0 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH0 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -2982,13 +3057,16 @@ - OUT_CONF1_CH0 - DMA_OUT_CONF1_CH0_REG. + 1 + 0x4 + 0-0 + OUT_CONF1_CH%s + DMA_OUT_CONF1_CH%s_REG. 0xD4 0x20 - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -3004,49 +3082,49 @@ 0x07800002 - OUTFIFO_FULL_CH0 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_CH0 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_CNT_CH0 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH0 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH0 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH0 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH0 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -3061,14 +3139,14 @@ 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -3077,42 +3155,45 @@ - OUT_LINK_CH0 - DMA_OUT_LINK_CH0_REG. + 1 + 0x4 + 0-0 + OUT_LINK_CH%s + DMA_OUT_LINK_CH%s_REG. 0xE0 0x20 0x00800000 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH0 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -3127,21 +3208,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH0 + OUT_STATE reserved 20 3 @@ -3150,13 +3231,16 @@ - OUT_EOF_DES_ADDR_CH0 - DMA_OUT_EOF_DES_ADDR_CH0_REG. + 1 + 0x4 + 0-0 + OUT_EOF_DES_ADDR_CH%s + DMA_OUT_EOF_DES_ADDR_CH%s_REG. 0xE8 0x20 - OUT_EOF_DES_ADDR_CH0 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -3171,7 +3255,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH0 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -3186,7 +3270,7 @@ 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -3201,7 +3285,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -3216,7 +3300,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -3225,13 +3309,16 @@ - OUT_PRI_CH0 - DMA_OUT_PRI_CH0_REG. + 1 + 0x4 + 0-0 + OUT_PRI_CH%s + DMA_OUT_PRI_CH%s_REG. 0xFC 0x20 - TX_PRI_CH0 + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -3240,14 +3327,17 @@ - OUT_PERI_SEL_CH0 - DMA_OUT_PERI_SEL_CH0_REG. + 1 + 0x4 + 0-0 + OUT_PERI_SEL_CH%s + DMA_OUT_PERI_SEL_CH%s_REG. 0x100 0x20 0x0000003F - PERI_OUT_SEL_CH0 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -3401,6 +3491,30 @@ + + 8 + 0x4 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x20 + + + 8 + 0x4 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x20 + + + 8 + 0x4 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x20 + @@ -4371,14 +4485,14 @@ The raw bit signal for read_done interrupt. 0 1 - read-only + read-write PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. 1 1 - read-only + read-write @@ -5561,11 +5675,11 @@ registers - GPIO_INTR_PRO + GPIO 13 - GPIO_INTR_PRO_NMI + GPIO_NMI 14 @@ -5826,7 +5940,7 @@ read-write - PIN_PAD_DRIVER + PAD_DRIVER set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 @@ -5840,14 +5954,14 @@ read-write - PIN_INT_TYPE + INT_TYPE set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 @@ -5861,7 +5975,7 @@ read-write - PIN_INT_ENA + INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 @@ -5957,7 +6071,7 @@ - CLOCK_GATE_REG + CLOCK_GATE GPIO clock gate register 0x62C 0x20 @@ -5973,7 +6087,7 @@ - REG_DATE_REG + REG_DATE GPIO version register 0x6FC 0x20 @@ -5992,7 +6106,7 @@ I2C0 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 0 I2C 0x60013000 @@ -7130,6 +7244,7 @@ level. This is the I2C txfifo first address. 0 32 + read-only @@ -7144,6 +7259,7 @@ level. This is the I2C rxfifo first address. 0 32 + read-only @@ -7151,7 +7267,7 @@ level. INTERRUPT_CORE0 - Interrupt Core + Interrupt Controller (Core 0) INTERRUPT_CORE0 0x600C2000 @@ -7159,6 +7275,86 @@ level. 0x150 registers + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + LP_TIMER + 7 + + + COEX + 8 + + + BLE_TIMER + 9 + + + BLE_SEC + 10 + + + CACHE_IA + 25 + + + ICACHE_PRELOAD0 + 30 + + + ICACHE_SYNC0 + 31 + + + ECC + 35 + + + FROM_CPU_INTR0 + 36 + + + FROM_CPU_INTR1 + 37 + + + FROM_CPU_INTR2 + 38 + + + FROM_CPU_INTR3 + 39 + + + ETS_CORE0_PIF_PMS_SIZE + 41 + MAC_INTR_MAP @@ -8573,7 +8769,7 @@ level. LEDC - LED PWM (Pulse Width Modulation) Controller + LED Control PWM (Pulse Width Modulation) LEDC 0x60019000 @@ -8595,7 +8791,7 @@ level. 0x20 - TIMER_SEL_CH0 + TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3 @@ -8604,28 +8800,28 @@ level. read-write - SIG_OUT_EN_CH0 + SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write - IDLE_LV_CH0 + IDLE_LV This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write - PARA_UP_CH0 + PARA_UP This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only - OVF_NUM_CH0 + OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. @@ -8634,14 +8830,14 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows read-write - OVF_CNT_EN_CH0 + OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write - OVF_CNT_RESET_CH0 + OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 @@ -8658,7 +8854,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - HPOINT_CH0 + HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 @@ -8675,7 +8871,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - DUTY_CH0 + DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. @@ -8695,35 +8891,35 @@ The output value turns to low when the selected timers has reached the Lpoint.0x40000000 - DUTY_SCALE_CH0 + DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write - DUTY_CYCLE_CH0 + DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write - DUTY_NUM_CH0 + DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write - DUTY_INC_CH0 + DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. 30 1 read-write - DUTY_START_CH0 + DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 @@ -8758,14 +8954,14 @@ The output value turns to low when the selected timers has reached the Lpoint.0x00800000 - TIMER0_DUTY_RES + DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write - CLK_DIV_TIMER0 + CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. @@ -8774,21 +8970,21 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PAUSE + PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write - TIMER0_RST + RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write - TICK_SEL_TIMER0 + TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK @@ -8797,7 +8993,7 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PARA_UP + PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 @@ -8814,7 +9010,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_CNT + CNT This register stores the current counter value of timer %s. 0 14 @@ -8829,116 +9025,116 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_RAW + OVF_INT_RAW Triggered when the timer0 has reached its maximum counter value. 0 1 - read-only + read-write TIMER1_OVF_INT_RAW Triggered when the timer1 has reached its maximum counter value. 1 1 - read-only + read-write TIMER2_OVF_INT_RAW Triggered when the timer2 has reached its maximum counter value. 2 1 - read-only + read-write TIMER3_OVF_INT_RAW Triggered when the timer3 has reached its maximum counter value. 3 1 - read-only + read-write DUTY_CHNG_END_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 - read-only + read-write DUTY_CHNG_END_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 - read-only + read-write DUTY_CHNG_END_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. 6 1 - read-only + read-write DUTY_CHNG_END_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. 7 1 - read-only + read-write DUTY_CHNG_END_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. 8 1 - read-only + read-write DUTY_CHNG_END_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. 9 1 - read-only + read-write OVF_CNT_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 10 1 - read-only + read-write OVF_CNT_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 11 1 - read-only + read-write OVF_CNT_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. 12 1 - read-only + read-write OVF_CNT_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. 13 1 - read-only + read-write OVF_CNT_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. 14 1 - read-only + read-write OVF_CNT_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. 15 1 - read-only + read-write @@ -8949,7 +9145,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_ST + OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. 0 1 @@ -9069,7 +9265,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_ENA + OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 @@ -9189,7 +9385,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_CLR + OVF_INT_CLR Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. 0 1 @@ -9347,98 +9543,268 @@ The least significant eight bits represent the fractional part. - RNG - Hardware random number generator - RNG - 0x60026000 + MODEM_CLKRST + MODEM_CLKRST Peripheral + MODEM_CLKRST + 0x6004D800 0x0 - 0x4 + 0x18 registers - DATA - Random number data - 0xB0 + CLK_CONF + 0x0 0x20 + + + CLK_EN + . + 0 + 1 + read-write + + - - - - RTC_CNTL - Real Time Controller - RTC_CNTL - 0x60008000 - - 0x0 - 0x114 - registers - - - RTC_CORE - 21 - - - OPTIONS0 - register description - 0x0 + MODEM_LP_TIMER_CONF + 0x4 0x20 - 0x1000A000 - SW_STALL_PROCPU_C0 - {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU - 2 - 2 + LP_TIMER_SEL_RTC_SLOW + . + 0 + 1 read-write - SW_PROCPU_RST - PRO CPU SW reset - 5 + LP_TIMER_SEL_8M + . + 1 1 read-write - BB_I2C_FORCE_PD - BB_I2C force power down - 6 + LP_TIMER_SEL_XTAL + . + 2 1 read-write - BB_I2C_FORCE_PU - BB_I2C force power up - 7 + LP_TIMER_SEL_XTAL32K + . + 3 1 read-write - BBPLL_I2C_FORCE_PD - BB_PLL _I2C force power down - 8 - 1 + LP_TIMER_CLK_DIV_NUM + . + 4 + 8 read-write + + + + COEX_LP_CLK_CONF + 0x8 + 0x20 + - BBPLL_I2C_FORCE_PU - BB_PLL_I2C force power up - 9 + COEX_LPCLK_SEL_RTC_SLOW + . + 0 1 read-write - BBPLL_FORCE_PD - BB_PLL force power down - 10 + COEX_LPCLK_SEL_8M + . + 1 1 read-write - BBPLL_FORCE_PU - BB_PLL force power up + COEX_LPCLK_SEL_XTAL + . + 2 + 1 + read-write + + + COEX_LPCLK_SEL_XTAL32K + . + 3 + 1 + read-write + + + COEX_LPCLK_DIV_NUM + . + 4 + 8 + read-write + + + + + BLE_TIMER_CLK_CONF + 0xC + 0x20 + 0x00000003 + + + BLETIMER_USE_XTAL + . + 0 + 1 + read-write + + + BLETIMER_CLK_IS_ACTIVE + . + 1 + 1 + read-write + + + + + DATE + 0xC + 0x20 + 0x02107270 + + + DATE + . + 0 + 28 + read-write + + + + + ETM_CLK_CONF + 0x10 + 0x20 + + + ETM_CLK_SEL + . + 0 + 1 + read-write + + + ETM_CLK_ACTIVE + . + 1 + 1 + read-write + + + + + + + RNG + Hardware Random Number Generator + RNG + 0x60026000 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0xB0 + 0x20 + read-only + + + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x60008000 + + 0x0 + 0x114 + registers + + + RTC_CORE + 21 + + + + OPTIONS0 + register description + 0x0 + 0x20 + 0x1000A000 + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + read-write + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up 11 1 read-write @@ -9537,7 +9903,7 @@ The least significant eight bits represent the fractional part. read-write - RTC_MAIN_TIMER_ALARM_EN + MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 @@ -9573,7 +9939,7 @@ The least significant eight bits represent the fractional part. read-write - RTC_TIME_UPDATE + TIME_UPDATE Set 1: to update register with RTC timer 31 1 @@ -9588,7 +9954,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_TIMER_VALUE0_LOW + TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 @@ -9603,7 +9969,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_TIMER_VALUE0_HIGH + TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 @@ -9618,14 +9984,14 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SW_CPU_INT + SW_CPU_INT rtc software interrupt to main cpu 0 1 read-write - RTC_SLP_REJECT_CAUSE_CLR + SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 @@ -9830,6 +10196,20 @@ The least significant eight bits represent the fractional part. 1 read-write + + PLLA_FORCE_PD + PLLA force power down + 23 + 1 + read-write + + + PLLA_FORCE_PU + PLLA force power up + 24 + 1 + read-write + @@ -9861,7 +10241,7 @@ The least significant eight bits represent the fractional part. read-write - RTC_DRESET_MASK_PROCPU + DRESET_MASK_PROCPU Need add desc 20 1 @@ -9877,7 +10257,7 @@ The least significant eight bits represent the fractional part. 0x00060000 - RTC_WAKEUP_ENA + WAKEUP_ENA wakeup enable bitmap 15 17 @@ -9904,31 +10284,31 @@ The least significant eight bits represent the fractional part. 1 - RTC_WDT_INT_ENA + WDT_INT_ENA enable RTC WDT interrupt 3 1 - RTC_BROWN_OUT_INT_ENA + BROWN_OUT_INT_ENA enable brown out interrupt 9 1 - RTC_MAIN_TIMER_INT_ENA + MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 - RTC_SWD_INT_ENA + SWD_INT_ENA enable super watch dog interrupt 15 1 - RTC_BBPLL_CAL_INT_ENA + BBPLL_CAL_INT_ENA Need add desc 20 1 @@ -9956,35 +10336,35 @@ The least significant eight bits represent the fractional part. read-write - RTC_WDT_INT_RAW + WDT_INT_RAW RTC WDT interrupt raw 3 1 read-write - RTC_BROWN_OUT_INT_RAW + BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-write - RTC_MAIN_TIMER_INT_RAW + MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-write - RTC_SWD_INT_RAW + SWD_INT_RAW super watch dog interrupt raw 15 1 read-write - RTC_BBPLL_CAL_INT_RAW + BBPLL_CAL_INT_RAW Need add desc 20 1 @@ -10013,35 +10393,35 @@ The least significant eight bits represent the fractional part. read-write - RTC_WDT_INT_ST + WDT_INT_ST RTC WDT interrupt state 3 1 read-write - RTC_BROWN_OUT_INT_ST + BROWN_OUT_INT_ST brown out interrupt state 9 1 read-write - RTC_MAIN_TIMER_INT_ST + MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-write - RTC_SWD_INT_ST + SWD_INT_ST super watch dog interrupt state 15 1 read-write - RTC_BBPLL_CAL_INT_ST + BBPLL_CAL_INT_ST Need add desc 20 1 @@ -10070,35 +10450,35 @@ The least significant eight bits represent the fractional part. read-write - RTC_WDT_INT_CLR + WDT_INT_CLR Clear RTC WDT interrupt state 3 1 read-write - RTC_BROWN_OUT_INT_CLR + BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 read-write - RTC_MAIN_TIMER_INT_CLR + MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 read-write - RTC_SWD_INT_CLR + SWD_INT_CLR Clear super watch dog interrupt state 15 1 read-write - RTC_BBPLL_CAL_INT_CLR + BBPLL_CAL_INT_CLR Need add desc 20 1 @@ -10113,7 +10493,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH0 + SCRATCH0 Need add desc 0 32 @@ -10128,7 +10508,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH1 + SCRATCH1 Need add desc 0 32 @@ -10143,7 +10523,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH2 + SCRATCH2 Need add desc 0 32 @@ -10158,7 +10538,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH3 + SCRATCH3 Need add desc 0 32 @@ -10210,7 +10590,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SLEEP_REJECT_ENA + SLEEP_REJECT_ENA sleep reject enable 12 18 @@ -10239,14 +10619,14 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_CPUSEL_CONF + CPUSEL_CONF CPU sel option 29 1 read-write - RTC_CPUPERIOD_SEL + CPUPERIOD_SEL Need add desc 30 2 @@ -10404,21 +10784,21 @@ The least significant eight bits represent the fractional part. 0x00400000 - RTC_ANA_CLK_DIV_VLD + ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div 22 1 read-write - RTC_ANA_CLK_DIV + ANA_CLK_DIV Need add desc 23 8 read-write - RTC_SLOW_CLK_NEXT_EDGE + SLOW_CLK_NEXT_EDGE Need add desc 31 1 @@ -10527,7 +10907,7 @@ The least significant eight bits represent the fractional part. - RTC + RTC_CNTL register description 0x74 0x20 @@ -10570,7 +10950,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_PAD_FORCE_HOLD + PAD_FORCE_HOLD rtc pad force hold 21 1 @@ -10893,7 +11273,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_WDT_FEED + WDT_FEED Need add desc 31 1 @@ -11018,7 +11398,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH4 + SCRATCH4 Need add desc 0 32 @@ -11033,7 +11413,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH5 + SCRATCH5 Need add desc 0 32 @@ -11048,7 +11428,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH6 + SCRATCH6 Need add desc 0 32 @@ -11063,7 +11443,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_SCRATCH7 + SCRATCH7 Need add desc 0 32 @@ -11085,140 +11465,140 @@ The least significant eight bits represent the fractional part. read-write - RTC_TOUCH_STATE_START + TOUCH_STATE_START touch should start to work 9 1 read-write - RTC_TOUCH_STATE_SWITCH + TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-write - RTC_TOUCH_STATE_SLP + TOUCH_STATE_SLP touch is in sleep state 11 1 read-write - RTC_TOUCH_STATE_DONE + TOUCH_STATE_DONE touch is done 12 1 read-write - RTC_COCPU_STATE_START + COCPU_STATE_START ulp/cocpu should start to work 13 1 read-write - RTC_COCPU_STATE_SWITCH + COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-write - RTC_COCPU_STATE_SLP + COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-write - RTC_COCPU_STATE_DONE + COCPU_STATE_DONE ulp/cocpu is done 16 1 read-write - RTC_MAIN_STATE_XTAL_ISO + MAIN_STATE_XTAL_ISO no use any more 17 1 read-write - RTC_MAIN_STATE_PLL_ON + MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-write - RTC_RDY_FOR_WAKEUP + RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-write - RTC_MAIN_STATE_WAIT_END + MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-write - RTC_IN_WAKEUP_STATE + IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-write - RTC_IN_LOW_POWER_STATE + IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-write - RTC_MAIN_STATE_IN_WAIT_8M + MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-write - RTC_MAIN_STATE_IN_WAIT_PLL + MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-write - RTC_MAIN_STATE_IN_WAIT_XTL + MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-write - RTC_MAIN_STATE_IN_SLP + MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-write - RTC_MAIN_STATE_IN_IDLE + MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-write - RTC_MAIN_STATE + MAIN_STATE rtc main state machine status 28 4 @@ -11233,7 +11613,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_LOW_POWER_DIAG1 + LOW_POWER_DIAG1 Need add desc 0 32 @@ -11248,42 +11628,42 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_GPIO_PIN0_HOLD + GPIO_PIN0_HOLD Need add desc 0 1 read-write - RTC_GPIO_PIN1_HOLD + GPIO_PIN1_HOLD Need add desc 1 1 read-write - RTC_GPIO_PIN2_HOLD + GPIO_PIN2_HOLD Need add desc 2 1 read-write - RTC_GPIO_PIN3_HOLD + GPIO_PIN3_HOLD Need add desc 3 1 read-write - RTC_GPIO_PIN4_HOLD + GPIO_PIN4_HOLD Need add desc 4 1 read-write - RTC_GPIO_PIN5_HOLD + GPIO_PIN5_HOLD Need add desc 5 1 @@ -11392,7 +11772,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_TIMER_VALUE1_LOW + TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 @@ -11407,7 +11787,7 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_TIMER_VALUE1_HIGH + TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 @@ -11512,35 +11892,35 @@ The least significant eight bits represent the fractional part. read-write - RTC_WDT_INT_ENA_W1TS + WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 read-write - RTC_BROWN_OUT_INT_ENA_W1TS + BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 read-write - RTC_MAIN_TIMER_INT_ENA_W1TS + MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 read-write - RTC_SWD_INT_ENA_W1TS + SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 read-write - RTC_BBPLL_CAL_INT_ENA_W1TS + BBPLL_CAL_INT_ENA_W1TS Need add desc 20 1 @@ -11569,35 +11949,35 @@ The least significant eight bits represent the fractional part. read-write - RTC_WDT_INT_ENA_W1TC + WDT_INT_ENA_W1TC enable RTC WDT interrupt 3 1 read-write - RTC_BROWN_OUT_INT_ENA_W1TC + BROWN_OUT_INT_ENA_W1TC enable brown out interrupt 9 1 read-write - RTC_MAIN_TIMER_INT_ENA_W1TC + MAIN_TIMER_INT_ENA_W1TC enable RTC main timer interrupt 10 1 read-write - RTC_SWD_INT_ENA_W1TC + SWD_INT_ENA_W1TC enable super watch dog interrupt 15 1 read-write - RTC_BBPLL_CAL_INT_ENA_W1TC + BBPLL_CAL_INT_ENA_W1TC Need add desc 20 1 @@ -11657,7 +12037,7 @@ The least significant eight bits represent the fractional part. 0x00000007 - RTC_FIB_SEL + FIB_SEL select use analog fib signal 0 3 @@ -11672,105 +12052,105 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_GPIO_WAKEUP_STATUS + GPIO_WAKEUP_STATUS Need add desc 0 6 read-write - RTC_GPIO_WAKEUP_STATUS_CLR + GPIO_WAKEUP_STATUS_CLR Need add desc 6 1 read-write - RTC_GPIO_PIN_CLK_GATE + GPIO_PIN_CLK_GATE Need add desc 7 1 read-write - RTC_GPIO_PIN5_INT_TYPE + GPIO_PIN5_INT_TYPE Need add desc 8 3 read-write - RTC_GPIO_PIN4_INT_TYPE + GPIO_PIN4_INT_TYPE Need add desc 11 3 read-write - RTC_GPIO_PIN3_INT_TYPE + GPIO_PIN3_INT_TYPE Need add desc 14 3 read-write - RTC_GPIO_PIN2_INT_TYPE + GPIO_PIN2_INT_TYPE Need add desc 17 3 read-write - RTC_GPIO_PIN1_INT_TYPE + GPIO_PIN1_INT_TYPE Need add desc 20 3 read-write - RTC_GPIO_PIN0_INT_TYPE + GPIO_PIN0_INT_TYPE Need add desc 23 3 read-write - RTC_GPIO_PIN5_WAKEUP_ENABLE + GPIO_PIN5_WAKEUP_ENABLE Need add desc 26 1 read-write - RTC_GPIO_PIN4_WAKEUP_ENABLE + GPIO_PIN4_WAKEUP_ENABLE Need add desc 27 1 read-write - RTC_GPIO_PIN3_WAKEUP_ENABLE + GPIO_PIN3_WAKEUP_ENABLE Need add desc 28 1 read-write - RTC_GPIO_PIN2_WAKEUP_ENABLE + GPIO_PIN2_WAKEUP_ENABLE Need add desc 29 1 read-write - RTC_GPIO_PIN1_WAKEUP_ENABLE + GPIO_PIN1_WAKEUP_ENABLE Need add desc 30 1 read-write - RTC_GPIO_PIN0_WAKEUP_ENABLE + GPIO_PIN0_WAKEUP_ENABLE Need add desc 31 1 @@ -11785,49 +12165,49 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_DEBUG_12M_NO_GATING + DEBUG_12M_NO_GATING Need add desc 1 1 read-write - RTC_DEBUG_BIT_SEL + DEBUG_BIT_SEL Need add desc 2 5 read-write - RTC_DEBUG_SEL0 + DEBUG_SEL0 Need add desc 7 5 read-write - RTC_DEBUG_SEL1 + DEBUG_SEL1 Need add desc 12 5 read-write - RTC_DEBUG_SEL2 + DEBUG_SEL2 Need add desc 17 5 read-write - RTC_DEBUG_SEL3 + DEBUG_SEL3 Need add desc 22 5 read-write - RTC_DEBUG_SEL4 + DEBUG_SEL4 Need add desc 27 5 @@ -11842,84 +12222,84 @@ The least significant eight bits represent the fractional part. 0x20 - RTC_GPIO_PIN5_MUX_SEL + GPIO_PIN5_MUX_SEL Need add desc 2 1 read-write - RTC_GPIO_PIN4_MUX_SEL + GPIO_PIN4_MUX_SEL Need add desc 3 1 read-write - RTC_GPIO_PIN3_MUX_SEL + GPIO_PIN3_MUX_SEL Need add desc 4 1 read-write - RTC_GPIO_PIN2_MUX_SEL + GPIO_PIN2_MUX_SEL Need add desc 5 1 read-write - RTC_GPIO_PIN1_MUX_SEL + GPIO_PIN1_MUX_SEL Need add desc 6 1 read-write - RTC_GPIO_PIN0_MUX_SEL + GPIO_PIN0_MUX_SEL Need add desc 7 1 read-write - RTC_GPIO_PIN5_FUN_SEL + GPIO_PIN5_FUN_SEL Need add desc 8 4 read-write - RTC_GPIO_PIN4_FUN_SEL + GPIO_PIN4_FUN_SEL Need add desc 12 4 read-write - RTC_GPIO_PIN3_FUN_SEL + GPIO_PIN3_FUN_SEL Need add desc 16 4 read-write - RTC_GPIO_PIN2_FUN_SEL + GPIO_PIN2_FUN_SEL Need add desc 20 4 read-write - RTC_GPIO_PIN1_FUN_SEL + GPIO_PIN1_FUN_SEL Need add desc 24 4 read-write - RTC_GPIO_PIN0_FUN_SEL + GPIO_PIN0_FUN_SEL Need add desc 28 4 @@ -11972,7 +12352,7 @@ The least significant eight bits represent the fractional part. 0x02107190 - RTC_CNTL_DATE + CNTL_DATE Need add desc 0 28 @@ -11984,7 +12364,7 @@ The least significant eight bits represent the fractional part. SENSITIVE - Sensitive + SENSITIVE Peripheral SENSITIVE 0x600C1000 @@ -12414,7 +12794,7 @@ The least significant eight bits represent the fractional part. Reserved. 1 31 - read-only + write-only @@ -12429,7 +12809,7 @@ The least significant eight bits represent the fractional part. Reserved. 1 31 - read-only + write-only @@ -12525,26 +12905,26 @@ The least significant eight bits represent the fractional part. - 64 - 0x1 + 8 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 SPI0 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 0 SPI0 0x60003000 @@ -12558,84 +12938,84 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL + CTRL SPI0 control register. 0x8 0x20 0x002C2000 - SPI_MEM_FDUMMY_OUT + FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write - SPI_MEM_FCMD_DUAL + FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write - SPI_MEM_FCMD_QUAD + FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write - SPI_MEM_FASTRD_MODE + FASTRD_MODE This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. 13 1 read-write - SPI_MEM_FREAD_DUAL + FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write - SPI_MEM_Q_POL + Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write - SPI_MEM_D_POL + D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write - SPI_MEM_FREAD_QUAD + FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write - SPI_MEM_WP + WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write - SPI_MEM_FREAD_DIO + FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write - SPI_MEM_FREAD_QIO + FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 @@ -12644,20 +13024,20 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL1 + CTRL1 SPI0 control1 register. 0xC 0x20 - SPI_MEM_CLK_MODE + CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write - SPI_MEM_RXFIFO_RST + RXFIFO_RST SPI0 RX FIFO reset signal. 30 1 @@ -12666,35 +13046,35 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL2 + CTRL2 SPI0 control2 register. 0x10 0x20 0x00000021 - SPI_MEM_CS_SETUP_TIME + CS_SETUP_TIME (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. 0 5 read-write - SPI_MEM_CS_HOLD_TIME + CS_HOLD_TIME Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. 5 5 read-write - SPI_MEM_CS_HOLD_DELAY + CS_HOLD_DELAY These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. 25 6 read-write - SPI_MEM_SYNC_RESET + SYNC_RESET The FSM will be reset. 31 1 @@ -12703,35 +13083,35 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CLOCK + CLOCK SPI clock division control register. 0x14 0x20 0x00030103 - SPI_MEM_CLKCNT_L + CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write - SPI_MEM_CLKCNT_H + CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write - SPI_MEM_CLKCNT_N + CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write - SPI_MEM_CLK_EQU_SYSCLK + CLK_EQU_SYSCLK Set this bit in 1-division mode. 31 1 @@ -12740,41 +13120,41 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER + USER SPI0 user register. 0x18 0x20 - SPI_MEM_CS_HOLD + CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. 6 1 read-write - SPI_MEM_CS_SETUP + CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. 7 1 read-write - SPI_MEM_CK_OUT_EDGE + CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write - SPI_MEM_USR_DUMMY_IDLE + USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. 26 1 read-write - SPI_MEM_USR_DUMMY + USR_DUMMY This bit enable the dummy phase of an operation. 29 1 @@ -12783,21 +13163,21 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER1 + USER1 SPI0 user1 register. 0x1C 0x20 0x5C000007 - SPI_MEM_USR_DUMMY_CYCLELEN + USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write - SPI_MEM_USR_ADDR_BITLEN + USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 @@ -12806,21 +13186,21 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER2 + USER2 SPI0 user2 register. 0x20 0x20 0x70000000 - SPI_MEM_USR_COMMAND_VALUE + USR_COMMAND_VALUE The value of command. 0 16 read-write - SPI_MEM_USR_COMMAND_BITLEN + USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 @@ -12829,13 +13209,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_RD_STATUS + RD_STATUS SPI0 read control register. 0x2C 0x20 - SPI_MEM_WB_MODE + WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 @@ -12844,48 +13224,48 @@ The least significant eight bits represent the fractional part. - SPI_MEM_MISC + MISC SPI0 misc register 0x34 0x20 - SPI_MEM_TRANS_END + TRANS_END The bit is used to indicate the spi0_mst_st controlled transmitting is done. 3 1 read-write - SPI_MEM_TRANS_END_INT_ENA + TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. 4 1 read-write - SPI_MEM_CSPI_ST_TRANS_END + CSPI_ST_TRANS_END The bit is used to indicate the spi0_slv_st controlled transmitting is done. 5 1 read-write - SPI_MEM_CSPI_ST_TRANS_END_INT_ENA + CSPI_ST_TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. 6 1 read-write - SPI_MEM_CK_IDLE_EDGE + CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write - SPI_MEM_CS_KEEP_ACTIVE + CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 @@ -12894,69 +13274,69 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CACHE_FCTRL + CACHE_FCTRL SPI0 bit mode control register. 0x3C 0x20 - SPI_MEM_CACHE_REQ_EN + CACHE_REQ_EN For SPI0, Cache access enable, 1: enable, 0:disable. 0 1 read-write - SPI_MEM_CACHE_USR_ADDR_4BYTE + CACHE_USR_ADDR_4BYTE For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write - SPI_MEM_CACHE_FLASH_USR_CMD + CACHE_FLASH_USR_CMD For SPI0, cache read flash for user define command, 1: enable, 0:disable. 2 1 read-write - SPI_MEM_FDIN_DUAL + FDIN_DUAL For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write - SPI_MEM_FDOUT_DUAL + FDOUT_DUAL For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write - SPI_MEM_FADDR_DUAL + FADDR_DUAL For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write - SPI_MEM_FDIN_QUAD + FDIN_QUAD For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write - SPI_MEM_FDOUT_QUAD + FDOUT_QUAD For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write - SPI_MEM_FADDR_QUAD + FADDR_QUAD For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 @@ -12965,28 +13345,28 @@ The least significant eight bits represent the fractional part. - SPI_MEM_FSM + FSM SPI0 FSM status register 0x54 0x20 0x00000200 - SPI_MEM_CSPI_ST + CSPI_ST The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 0 4 read-only - SPI_MEM_EM_ST + EM_ST The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. 4 3 read-only - SPI_MEM_CSPI_LOCK_DELAY_TIME + CSPI_LOCK_DELAY_TIME The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. 7 5 @@ -12995,136 +13375,151 @@ The least significant eight bits represent the fractional part. - SPI_MEM_TIMING_CALI + TIMING_CALI SPI0 timing calibration register 0xA8 0x20 - SPI_MEM_TIMING_CLK_ENA + TIMING_CLK_ENA The bit is used to enable timing adjust clock for all reading operations. 0 1 + read-only - SPI_MEM_TIMING_CALI + TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 + read-only - SPI_MEM_EXTRA_DUMMY_CYCLELEN + EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 + read-only - SPI_MEM_DIN_MODE + DIN_MODE SPI0 input delay mode control register 0xAC 0x20 - SPI_MEM_DIN0_MODE + DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 2 + read-only - SPI_MEM_DIN1_MODE + DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 2 2 + read-only - SPI_MEM_DIN2_MODE + DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 4 2 + read-only - SPI_MEM_DIN3_MODE + DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 2 + read-only - SPI_MEM_DIN_NUM + DIN_NUM SPI0 input delay number control register 0xB0 0x20 - SPI_MEM_DIN0_NUM + DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 1 + read-only - SPI_MEM_DIN1_NUM + DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 1 1 + read-only - SPI_MEM_DIN2_NUM + DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 1 + read-only - SPI_MEM_DIN3_NUM + DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 3 1 + read-only - SPI_MEM_DOUT_MODE + DOUT_MODE SPI0 output delay mode control register 0xB4 0x20 - SPI_MEM_DOUT0_MODE + DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 + read-only - SPI_MEM_DOUT1_MODE + DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 + read-only - SPI_MEM_DOUT2_MODE + DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 + read-only - SPI_MEM_DOUT3_MODE + DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 + read-only - SPI_MEM_CLOCK_GATE + CLOCK_GATE SPI0 clk_gate register 0xDC 0x20 0x00000001 - SPI_MEM_CLK_EN + CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 @@ -13133,13 +13528,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CORE_CLK_SEL + CORE_CLK_SEL SPI0 module clock select register 0xE0 0x20 - SPI_MEM_SPI01_CLK_SEL + SPI01_CLK_SEL When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. 0 2 @@ -13148,14 +13543,14 @@ The least significant eight bits represent the fractional part. - SPI_MEM_DATE + DATE Version control register 0x3FC 0x20 0x02106191 - SPI_MEM_DATE + DATE SPI register version. 0 28 @@ -13167,7 +13562,7 @@ The least significant eight bits represent the fractional part. SPI1 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 1 SPI1 0x60002000 @@ -13177,125 +13572,125 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CMD + CMD SPI1 memory command register 0x0 0x20 - SPI_MEM_SPI1_MST_ST + SPI1_MST_ST The current status of SPI1 master FSM. 0 4 read-only - SPI_MEM_MSPI_ST + MSPI_ST The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 4 4 read-only - SPI_MEM_FLASH_PE + FLASH_PE In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. 17 1 read-write - SPI_MEM_USR + USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-write - SPI_MEM_FLASH_HPM + FLASH_HPM Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. 19 1 read-write - SPI_MEM_FLASH_RES + FLASH_RES This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. 20 1 read-write - SPI_MEM_FLASH_DP + FLASH_DP Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 21 1 read-write - SPI_MEM_FLASH_CE + FLASH_CE Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 22 1 read-write - SPI_MEM_FLASH_BE + FLASH_BE Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 23 1 read-write - SPI_MEM_FLASH_SE + FLASH_SE Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 24 1 read-write - SPI_MEM_FLASH_PP + FLASH_PP Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. 25 1 read-write - SPI_MEM_FLASH_WRSR + FLASH_WRSR Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 26 1 read-write - SPI_MEM_FLASH_RDSR + FLASH_RDSR Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 27 1 read-write - SPI_MEM_FLASH_RDID + FLASH_RDID Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 28 1 read-write - SPI_MEM_FLASH_WRDI + FLASH_WRDI Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 29 1 read-write - SPI_MEM_FLASH_WREN + FLASH_WREN Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 30 1 read-write - SPI_MEM_FLASH_READ + FLASH_READ Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 31 1 @@ -13304,13 +13699,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_ADDR + ADDR SPI1 address register 0x4 0x20 - SPI_MEM_USR_ADDR_VALUE + USR_ADDR_VALUE In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. 0 32 @@ -13319,112 +13714,112 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL + CTRL SPI1 control register. 0x8 0x20 0x002CA000 - SPI_MEM_FDUMMY_OUT + FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write - SPI_MEM_FCMD_DUAL + FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write - SPI_MEM_FCMD_QUAD + FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write - SPI_MEM_FCS_CRC_EN + FCS_CRC_EN For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. 10 1 read-write - SPI_MEM_TX_CRC_EN + TX_CRC_EN For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable 11 1 read-write - SPI_MEM_FASTRD_MODE + FASTRD_MODE This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. 13 1 read-write - SPI_MEM_FREAD_DUAL + FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write - SPI_MEM_RESANDRES + RESANDRES The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. 15 1 read-write - SPI_MEM_Q_POL + Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write - SPI_MEM_D_POL + D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write - SPI_MEM_FREAD_QUAD + FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write - SPI_MEM_WP + WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write - SPI_MEM_WRSR_2B + WRSR_2B two bytes data will be written to status register when it is set. 1: enable 0: disable. 22 1 read-write - SPI_MEM_FREAD_DIO + FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write - SPI_MEM_FREAD_QIO + FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 @@ -13433,21 +13828,21 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL1 + CTRL1 SPI1 control1 register. 0xC 0x20 0x00000FFC - SPI_MEM_CLK_MODE + CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write - SPI_MEM_CS_HOLD_DLY_RES + CS_HOLD_DLY_RES After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. 2 10 @@ -13456,13 +13851,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CTRL2 + CTRL2 SPI1 control2 register. 0x10 0x20 - SPI_MEM_SYNC_RESET + SYNC_RESET The FSM will be reset. 31 1 @@ -13471,35 +13866,35 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CLOCK + CLOCK SPI1 clock division control register. 0x14 0x20 0x00030103 - SPI_MEM_CLKCNT_L + CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write - SPI_MEM_CLKCNT_H + CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write - SPI_MEM_CLKCNT_N + CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write - SPI_MEM_CLK_EQU_SYSCLK + CLK_EQU_SYSCLK reserved 31 1 @@ -13508,98 +13903,98 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER + USER SPI1 user register. 0x18 0x20 0x80000000 - SPI_MEM_CK_OUT_EDGE + CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write - SPI_MEM_FWRITE_DUAL + FWRITE_DUAL In the write operations read-data phase apply 2 signals 12 1 read-write - SPI_MEM_FWRITE_QUAD + FWRITE_QUAD In the write operations read-data phase apply 4 signals 13 1 read-write - SPI_MEM_FWRITE_DIO + FWRITE_DIO In the write operations address phase and read-data phase apply 2 signals. 14 1 read-write - SPI_MEM_FWRITE_QIO + FWRITE_QIO In the write operations address phase and read-data phase apply 4 signals. 15 1 read-write - SPI_MEM_USR_MISO_HIGHPART + USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 24 1 read-write - SPI_MEM_USR_MOSI_HIGHPART + USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 25 1 read-write - SPI_MEM_USR_DUMMY_IDLE + USR_DUMMY_IDLE SPI clock is disable in dummy phase when the bit is enable. 26 1 read-write - SPI_MEM_USR_MOSI + USR_MOSI This bit enable the write-data phase of an operation. 27 1 read-write - SPI_MEM_USR_MISO + USR_MISO This bit enable the read-data phase of an operation. 28 1 read-write - SPI_MEM_USR_DUMMY + USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write - SPI_MEM_USR_ADDR + USR_ADDR This bit enable the address phase of an operation. 30 1 read-write - SPI_MEM_USR_COMMAND + USR_COMMAND This bit enable the command phase of an operation. 31 1 @@ -13608,21 +14003,21 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER1 + USER1 SPI1 user1 register. 0x1C 0x20 0x5C000007 - SPI_MEM_USR_DUMMY_CYCLELEN + USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write - SPI_MEM_USR_ADDR_BITLEN + USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 @@ -13631,21 +14026,21 @@ The least significant eight bits represent the fractional part. - SPI_MEM_USER2 + USER2 SPI1 user2 register. 0x20 0x20 0x70000000 - SPI_MEM_USR_COMMAND_VALUE + USR_COMMAND_VALUE The value of command. 0 16 read-write - SPI_MEM_USR_COMMAND_BITLEN + USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 @@ -13654,13 +14049,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_MOSI_DLEN + MOSI_DLEN SPI1 send data bit length control register. 0x24 0x20 - SPI_MEM_USR_MOSI_DBITLEN + USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). 0 10 @@ -13669,13 +14064,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_MISO_DLEN + MISO_DLEN SPI1 receive data bit length control register. 0x28 0x20 - SPI_MEM_USR_MISO_DBITLEN + USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). 0 10 @@ -13684,20 +14079,20 @@ The least significant eight bits represent the fractional part. - SPI_MEM_RD_STATUS + RD_STATUS SPI1 status register. 0x2C 0x20 - SPI_MEM_STATUS + STATUS The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. 0 16 read-write - SPI_MEM_WB_MODE + WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 @@ -13706,35 +14101,35 @@ The least significant eight bits represent the fractional part. - SPI_MEM_MISC + MISC SPI1 misc register 0x34 0x20 0x00000002 - SPI_MEM_CS0_DIS + CS0_DIS SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. 0 1 read-write - SPI_MEM_CS1_DIS + CS1_DIS SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. 1 1 read-write - SPI_MEM_CK_IDLE_EDGE + CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write - SPI_MEM_CS_KEEP_ACTIVE + CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 @@ -13743,7 +14138,7 @@ The least significant eight bits represent the fractional part. - SPI_MEM_TX_CRC + TX_CRC SPI1 TX CRC data register. 0x38 0x20 @@ -13759,55 +14154,55 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CACHE_FCTRL + CACHE_FCTRL SPI1 bit mode control register. 0x3C 0x20 - SPI_MEM_CACHE_USR_ADDR_4BYTE + CACHE_USR_ADDR_4BYTE For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write - SPI_MEM_FDIN_DUAL + FDIN_DUAL For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write - SPI_MEM_FDOUT_DUAL + FDOUT_DUAL For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write - SPI_MEM_FADDR_DUAL + FADDR_DUAL For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write - SPI_MEM_FDIN_QUAD + FDIN_QUAD For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write - SPI_MEM_FDOUT_QUAD + FDOUT_QUAD For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write - SPI_MEM_FADDR_QUAD + FADDR_QUAD For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 @@ -13816,13 +14211,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W0 + W0 SPI1 memory data buffer0 0x58 0x20 - SPI_MEM_BUF0 + BUF0 data buffer 0 32 @@ -13831,13 +14226,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W1 + W1 SPI1 memory data buffer1 0x5C 0x20 - SPI_MEM_BUF1 + BUF1 data buffer 0 32 @@ -13846,13 +14241,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W2 + W2 SPI1 memory data buffer2 0x60 0x20 - SPI_MEM_BUF2 + BUF2 data buffer 0 32 @@ -13861,13 +14256,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W3 + W3 SPI1 memory data buffer3 0x64 0x20 - SPI_MEM_BUF3 + BUF3 data buffer 0 32 @@ -13876,13 +14271,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W4 + W4 SPI1 memory data buffer4 0x68 0x20 - SPI_MEM_BUF4 + BUF4 data buffer 0 32 @@ -13891,13 +14286,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W5 + W5 SPI1 memory data buffer5 0x6C 0x20 - SPI_MEM_BUF5 + BUF5 data buffer 0 32 @@ -13906,13 +14301,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W6 + W6 SPI1 memory data buffer6 0x70 0x20 - SPI_MEM_BUF6 + BUF6 data buffer 0 32 @@ -13921,13 +14316,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W7 + W7 SPI1 memory data buffer7 0x74 0x20 - SPI_MEM_BUF7 + BUF7 data buffer 0 32 @@ -13936,13 +14331,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W8 + W8 SPI1 memory data buffer8 0x78 0x20 - SPI_MEM_BUF8 + BUF8 data buffer 0 32 @@ -13951,13 +14346,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W9 + W9 SPI1 memory data buffer9 0x7C 0x20 - SPI_MEM_BUF9 + BUF9 data buffer 0 32 @@ -13966,13 +14361,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W10 + W10 SPI1 memory data buffer10 0x80 0x20 - SPI_MEM_BUF10 + BUF10 data buffer 0 32 @@ -13981,13 +14376,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W11 + W11 SPI1 memory data buffer11 0x84 0x20 - SPI_MEM_BUF11 + BUF11 data buffer 0 32 @@ -13996,13 +14391,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W12 + W12 SPI1 memory data buffer12 0x88 0x20 - SPI_MEM_BUF12 + BUF12 data buffer 0 32 @@ -14011,13 +14406,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W13 + W13 SPI1 memory data buffer13 0x8C 0x20 - SPI_MEM_BUF13 + BUF13 data buffer 0 32 @@ -14026,13 +14421,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W14 + W14 SPI1 memory data buffer14 0x90 0x20 - SPI_MEM_BUF14 + BUF14 data buffer 0 32 @@ -14041,13 +14436,13 @@ The least significant eight bits represent the fractional part. - SPI_MEM_W15 + W15 SPI1 memory data buffer15 0x94 0x20 - SPI_MEM_BUF15 + BUF15 data buffer 0 32 @@ -14056,28 +14451,28 @@ The least significant eight bits represent the fractional part. - SPI_MEM_FLASH_WAITI_CTRL + FLASH_WAITI_CTRL SPI1 wait idle control register 0x98 0x20 0x00000014 - SPI_MEM_WAITI_DUMMY + WAITI_DUMMY The dummy phase enable when wait flash idle (RDSR) 1 1 read-write - SPI_MEM_WAITI_CMD + WAITI_CMD The command to wait flash idle(RDSR). 2 8 read-write - SPI_MEM_WAITI_DUMMY_CYCLELEN + WAITI_DUMMY_CYCLELEN The dummy cycle length when wait flash idle(RDSR). 10 6 @@ -14086,56 +14481,56 @@ The least significant eight bits represent the fractional part. - SPI_MEM_FLASH_SUS_CTRL + FLASH_SUS_CTRL SPI1 flash suspend control register 0x9C 0x20 0x08002000 - SPI_MEM_FLASH_PER + FLASH_PER program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 0 1 read-write - SPI_MEM_FLASH_PES + FLASH_PES program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 1 1 read-write - SPI_MEM_FLASH_PER_WAIT_EN + FLASH_PER_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. 2 1 read-write - SPI_MEM_FLASH_PES_WAIT_EN + FLASH_PES_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. 3 1 read-write - SPI_MEM_PES_PER_EN + PES_PER_EN Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. 4 1 read-write - SPI_MEM_FLASH_PES_EN + FLASH_PES_EN Set this bit to enable Auto-suspending function. 5 1 read-write - SPI_MEM_PESR_END_MSK + PESR_END_MSK The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. 6 16 @@ -14149,21 +14544,21 @@ The least significant eight bits represent the fractional part. read-write - SPI_MEM_PER_END_EN + PER_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. 23 1 read-write - SPI_MEM_PES_END_EN + PES_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. 24 1 read-write - SPI_MEM_SUS_TIMEOUT_CNT + SUS_TIMEOUT_CNT When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. 25 7 @@ -14172,28 +14567,28 @@ The least significant eight bits represent the fractional part. - SPI_MEM_FLASH_SUS_CMD + FLASH_SUS_CMD SPI1 flash suspend command register 0xA0 0x20 0x0005757A - SPI_MEM_FLASH_PER_COMMAND + FLASH_PER_COMMAND Program/Erase resume command. 0 8 read-write - SPI_MEM_FLASH_PES_COMMAND + FLASH_PES_COMMAND Program/Erase suspend command. 8 8 read-write - SPI_MEM_WAIT_PESR_COMMAND + WAIT_PESR_COMMAND Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. 16 16 @@ -14202,62 +14597,62 @@ The least significant eight bits represent the fractional part. - SPI_MEM_SUS_STATUS + SUS_STATUS SPI1 flash suspend status register 0xA4 0x20 - SPI_MEM_FLASH_SUS + FLASH_SUS The status of flash suspend, only used in SPI1. 0 1 read-write - SPI_MEM_WAIT_PESR_CMD_2B + WAIT_PESR_CMD_2B 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. 1 1 read-write - SPI_MEM_FLASH_HPM_DLY_128 + FLASH_HPM_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. 2 1 read-write - SPI_MEM_FLASH_RES_DLY_128 + FLASH_RES_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. 3 1 read-write - SPI_MEM_FLASH_DP_DLY_128 + FLASH_DP_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. 4 1 read-write - SPI_MEM_FLASH_PER_DLY_128 + FLASH_PER_DLY_128 Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. 5 1 read-write - SPI_MEM_FLASH_PES_DLY_128 + FLASH_PES_DLY_128 Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. 6 1 read-write - SPI_MEM_SPI0_LOCK_EN + SPI0_LOCK_EN 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. 7 1 @@ -14266,68 +14661,70 @@ The least significant eight bits represent the fractional part. - SPI_MEM_TIMING_CALI + TIMING_CALI SPI1 timing control register 0xA8 0x20 - SPI_MEM_TIMING_CALI + TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 + read-only - SPI_MEM_EXTRA_DUMMY_CYCLELEN + EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 + read-only - SPI_MEM_INT_ENA + INT_ENA SPI1 interrupt enable register 0xC0 0x20 - SPI_MEM_PER_END_INT_ENA + PER_END_INT_ENA The enable bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-write - SPI_MEM_PES_END_INT_ENA + PES_END_INT_ENA The enable bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-write - SPI_MEM_WPE_END_INT_ENA + WPE_END_INT_ENA The enable bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-write - SPI_MEM_SLV_ST_END_INT_ENA + SLV_ST_END_INT_ENA The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-write - SPI_MEM_MST_ST_END_INT_ENA + MST_ST_END_INT_ENA The enable bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-write - SPI_MEM_BROWN_OUT_INT_ENA + BROWN_OUT_INT_ENA The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 @@ -14336,48 +14733,48 @@ The least significant eight bits represent the fractional part. - SPI_MEM_INT_CLR + INT_CLR SPI1 interrupt clear register 0xC4 0x20 - SPI_MEM_PER_END_INT_CLR + PER_END_INT_CLR The clear bit for SPI_MEM_PER_END_INT interrupt. 0 1 write-only - SPI_MEM_PES_END_INT_CLR + PES_END_INT_CLR The clear bit for SPI_MEM_PES_END_INT interrupt. 1 1 write-only - SPI_MEM_WPE_END_INT_CLR + WPE_END_INT_CLR The clear bit for SPI_MEM_WPE_END_INT interrupt. 2 1 write-only - SPI_MEM_SLV_ST_END_INT_CLR + SLV_ST_END_INT_CLR The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 write-only - SPI_MEM_MST_ST_END_INT_CLR + MST_ST_END_INT_CLR The clear bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 write-only - SPI_MEM_BROWN_OUT_INT_CLR + BROWN_OUT_INT_CLR The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 @@ -14386,98 +14783,98 @@ The least significant eight bits represent the fractional part. - SPI_MEM_INT_RAW + INT_RAW SPI1 interrupt raw register 0xC8 0x20 - SPI_MEM_PER_END_INT_RAW + PER_END_INT_RAW The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. 0 1 - read-only + read-write - SPI_MEM_PES_END_INT_RAW + PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. 1 1 - read-only + read-write - SPI_MEM_WPE_END_INT_RAW + WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 - read-only + read-write - SPI_MEM_SLV_ST_END_INT_RAW + SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 - read-only + read-write - SPI_MEM_MST_ST_END_INT_RAW + MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 - read-only + read-write - SPI_MEM_BROWN_OUT_INT_RAW + BROWN_OUT_INT_RAW The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. 5 1 - read-only + read-write - SPI_MEM_INT_ST + INT_ST SPI1 interrupt status register 0xCC 0x20 - SPI_MEM_PER_END_INT_ST + PER_END_INT_ST The status bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-only - SPI_MEM_PES_END_INT_ST + PES_END_INT_ST The status bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-only - SPI_MEM_WPE_END_INT_ST + WPE_END_INT_ST The status bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-only - SPI_MEM_SLV_ST_END_INT_ST + SLV_ST_END_INT_ST The status bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-only - SPI_MEM_MST_ST_END_INT_ST + MST_ST_END_INT_ST The status bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-only - SPI_MEM_BROWN_OUT_INT_ST + BROWN_OUT_INT_ST The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 @@ -14486,14 +14883,14 @@ The least significant eight bits represent the fractional part. - SPI_MEM_CLOCK_GATE + CLOCK_GATE SPI1 clk_gate register 0xDC 0x20 0x00000001 - SPI_MEM_CLK_EN + CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 @@ -14502,14 +14899,14 @@ The least significant eight bits represent the fractional part. - SPI_MEM_DATE + DATE Version control register 0x3FC 0x20 0x02107013 - SPI_MEM_DATE + DATE Version control register 0 28 @@ -14521,7 +14918,7 @@ The least significant eight bits represent the fractional part. SPI2 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 2 SPI2 0x60024000 @@ -14615,6 +15012,7 @@ The least significant eight bits represent the fractional part. Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 + read-only FCMD_DUAL @@ -14635,6 +15033,7 @@ The least significant eight bits represent the fractional part. Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 + read-only FREAD_DUAL @@ -14655,6 +15054,7 @@ The least significant eight bits represent the fractional part. In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. 16 1 + read-only Q_POL @@ -14770,6 +15170,7 @@ The least significant eight bits represent the fractional part. Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. 4 1 + read-only TSCK_I_EDGE @@ -14825,6 +15226,7 @@ The least significant eight bits represent the fractional part. In the write operations read-data phase apply 8 signals. Can be configured in CONF state. 14 1 + read-only USR_CONF_NXT @@ -15055,24 +15457,28 @@ The least significant eight bits represent the fractional part. 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 + read-only DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 + read-only ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 + read-only CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 + read-only SLAVE_CS_POL @@ -15086,6 +15492,7 @@ The least significant eight bits represent the fractional part. The default value of spi_dqs. Can be configured in CONF state. 24 1 + read-only CK_IDLE_EDGE @@ -15121,54 +15528,63 @@ The least significant eight bits represent the fractional part. the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 + read-only DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 + read-only DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 + read-only DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 + read-only DIN4_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 8 2 + read-only DIN5_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 10 2 + read-only DIN6_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 12 2 + read-only DIN7_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 14 2 + read-only TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 + read-only @@ -15183,48 +15599,56 @@ The least significant eight bits represent the fractional part. the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 + read-only DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 + read-only DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 + read-only DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 + read-only DIN4_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 + read-only DIN5_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 + read-only DIN6_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 + read-only DIN7_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 + read-only @@ -15239,54 +15663,63 @@ The least significant eight bits represent the fractional part. The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 + read-only DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 + read-only DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 + read-only DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 + read-only DOUT4_MODE The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 4 1 + read-only DOUT5_MODE The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 5 1 + read-only DOUT6_MODE The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 6 1 + read-only DOUT7_MODE The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 7 1 + read-only D_DQS_MODE The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 8 1 + read-only @@ -15697,147 +16130,147 @@ The least significant eight bits represent the fractional part. 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. 0 1 - read-only + read-write DMA_OUTFIFO_EMPTY_ERR_INT_RAW 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. 1 1 - read-only + read-write SLV_EX_QPI_INT_RAW The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. 2 1 - read-only + read-write SLV_EN_QPI_INT_RAW The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. 3 1 - read-only + read-write SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. 4 1 - read-only + read-write SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. 5 1 - read-only + read-write SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. 6 1 - read-only + read-write SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. 7 1 - read-only + read-write SLV_RD_DMA_DONE_INT_RAW The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. 8 1 - read-only + read-write SLV_WR_DMA_DONE_INT_RAW The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. 9 1 - read-only + read-write SLV_RD_BUF_DONE_INT_RAW The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. 10 1 - read-only + read-write SLV_WR_BUF_DONE_INT_RAW The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. 11 1 - read-only + read-write TRANS_DONE_INT_RAW The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. 12 1 - read-only + read-write DMA_SEG_TRANS_DONE_INT_RAW The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. 13 1 - read-only + read-write SEG_MAGIC_ERR_INT_RAW The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. 14 1 - read-only + read-write SLV_BUF_ADDR_ERR_INT_RAW The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. 15 1 - read-only + read-write SLV_CMD_ERR_INT_RAW The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. 16 1 - read-only + read-write MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. 17 1 - read-only + read-write MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 18 1 - read-only + read-write APP2_INT_RAW The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. 19 1 - read-only + read-write APP1_INT_RAW The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. 20 1 - read-only + read-write @@ -16555,7 +16988,7 @@ The least significant eight bits represent the fractional part. SYSTEM - System + System Configuration Registers SYSTEM 0x600C0000 @@ -17636,15 +18069,15 @@ The least significant eight bits represent the fractional part. registers - SYSTIMER_TARGET0_EDGE + SYSTIMER_TARGET0 26 - SYSTIMER_TARGET1_EDGE + SYSTIMER_TARGET1 27 - SYSTIMER_TARGET2_EDGE + SYSTIMER_TARGET2 28 @@ -18190,21 +18623,21 @@ The least significant eight bits represent the fractional part. interupt0 raw 0 1 - read-only + read-write TARGET1_INT_RAW interupt1 raw 1 1 - read-only + read-write TARGET2_INT_RAW interupt2 raw 2 1 - read-only + read-write @@ -18286,7 +18719,7 @@ The least significant eight bits represent the fractional part. TIMG0 - Timer Group + Timer Group 0 TIMG 0x6001F000 @@ -18305,7 +18738,7 @@ The least significant eight bits represent the fractional part. T0CONFIG - Timer $x configuration register + Timer %s configuration register 0x0 0x20 0x60002000 @@ -18327,36 +18760,36 @@ alarm occurs. DIVCNT_RST - When set, Timer 12 's clock divider counter will be reset. + When set, Timer %s 's clock divider counter will be reset. 12 1 write-only DIVIDER - Timer 13 clock (T13_clk) prescaler value. + Timer %s clock (T%s_clk) prescaler value. 13 16 read-write AUTORELOAD - When set, timer 29 auto-reload at alarm is enabled. + When set, timer %s auto-reload at alarm is enabled. 29 1 read-write INCREASE - When set, the timer 30 time-base counter will increment every clock tick. When -cleared, the timer 30 time-base counter will decrement. + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. 30 1 read-write EN - When set, the timer 31 time-base counter is enabled. + When set, the timer %s time-base counter is enabled. 31 1 read-write @@ -18365,14 +18798,14 @@ cleared, the timer 30 time-base counter will decrement. T0LO - Timer $x current value, low 32 bits + Timer %s current value, low 32 bits 0x4 0x20 LO - After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter -of timer 0 can be read here. + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. 0 32 read-only @@ -18381,14 +18814,14 @@ of timer 0 can be read here. T0HI - Timer $x current value, high 22 bits + Timer %s current value, high 22 bits 0x8 0x20 T0_HI - After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter -of timer 0 can be read here. + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. 0 22 read-only @@ -18397,13 +18830,13 @@ of timer 0 can be read here. T0UPDATE - Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG 0xC 0x20 T0_UPDATE - After writing 0 or 1 to TIMG_T31UPDATE_REG, the counter value is latched. + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 read-write @@ -18412,13 +18845,13 @@ of timer 0 can be read here. T0ALARMLO - Timer $x alarm value, low 32 bits + Timer %s alarm value, low 32 bits 0x10 0x20 ALARM_LO - Timer 0 alarm trigger time-base counter value, low 32 bits. + Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 read-write @@ -18427,13 +18860,13 @@ of timer 0 can be read here. T0ALARMHI - Timer $x alarm value, high bits + Timer %s alarm value, high bits 0x14 0x20 ALARM_HI - Timer 0 alarm trigger time-base counter value, high 22 bits. + Timer %s alarm trigger time-base counter value, high 22 bits. 0 22 read-write @@ -18442,13 +18875,13 @@ of timer 0 can be read here. T0LOADLO - Timer $x reload value, low 32 bits + Timer %s reload value, low 32 bits 0x18 0x20 LOAD_LO - Low 32 bits of the value that a reload will load onto timer 0 time-base + Low 32 bits of the value that a reload will load onto timer %s time-base Counter. 0 32 @@ -18458,13 +18891,13 @@ Counter. T0LOADHI - Timer $x reload value, high 22 bits + Timer %s reload value, high 22 bits 0x1C 0x20 LOAD_HI - High 22 bits of the value that a reload will load onto timer 0 time-base + High 22 bits of the value that a reload will load onto timer %s time-base counter. 0 22 @@ -18474,14 +18907,13 @@ counter. T0LOAD - Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG 0x20 0x20 LOAD - -Write any value to trigger a timer 0 time-base counter reload. + Write any value to trigger a timer %s time-base counter reload. 0 32 write-only @@ -18548,32 +18980,28 @@ Write any value to trigger a timer 0 time-base counter reload. WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write @@ -18941,7 +19369,7 @@ protection is enabled. UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x60000000 @@ -18981,140 +19409,140 @@ protection is enabled. This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 - read-only + read-write TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 - read-only + read-write PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 - read-only + read-write FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 - read-only + read-write RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 - read-only + read-write DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 - read-only + read-write CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 - read-only + read-write BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 - read-only + read-write RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 - read-only + read-write SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 - read-only + read-write SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 - read-only + read-write GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 - read-only + read-write TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. 12 1 - read-only + read-write TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 - read-only + read-write TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 - read-only + read-write RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 - read-only + read-write RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 - read-only + read-write RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 - read-only + read-write AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 - read-only + read-write WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 - read-only + read-write @@ -20527,7 +20955,7 @@ protection is enabled. UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x60010000 UART1 @@ -20546,12 +20974,12 @@ protection is enabled. - 16 - 0x1 + 4 + 0x4 PLAIN_MEM[%s] The memory that stores plaintext 0x0 - 0x8 + 0x20 LINESIZE diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c3.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c3.svd index ab064fa93..3d49163c5 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c3.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c3.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C3 - ESP32-C3 - 8 + ESP32 C-Series + 18 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. RV32IMC r0p0 little false false - 4 + 0 false 32 @@ -351,36 +349,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -552,7 +550,7 @@ APB_CTRL - Advanced Peripheral Bus Controller + APB (Advanced Peripheral Bus) Controller APB_CTRL 0x60026000 @@ -560,6 +558,10 @@ 0xA0 registers + + APB_CTRL + 14 + SYSCLK_CONF @@ -1057,7 +1059,7 @@ REDCY_SIG0 - APB_CTRL_REDCY_SIG0_REG + APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 @@ -1079,7 +1081,7 @@ REDCY_SIG1 - APB_CTRL_REDCY_SIG1_REG + APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 @@ -1257,7 +1259,7 @@ PERI_BACKUP_CONFIG - APB_CTRL_PERI_BACKUP_CONFIG_REG + APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 0x00006480 @@ -1315,7 +1317,7 @@ PERI_BACKUP_APB_ADDR - APB_CTRL_PERI_BACKUP_APB_ADDR_REG + APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 @@ -1330,7 +1332,7 @@ PERI_BACKUP_MEM_ADDR - APB_CTRL_PERI_BACKUP_MEM_ADDR_REG + APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 @@ -1451,7 +1453,7 @@ APB_SARADC - Successive Approximation Register Analog to Digital Converter + SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x60040000 @@ -2348,7 +2350,7 @@ - C0RE_0_MONTR_ENA + CORE_0_MONTR_ENA ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG 0x0 0x20 @@ -3355,6 +3357,51 @@ + + BB + BB Peripheral + BB + 0x6001D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + DMA DMA (Direct Memory Access) Controller @@ -3377,103 +3424,110 @@ DMA_CH2 46 + + DMA_APBPERI_PMS + 55 + - INT_RAW_CH0 - DMA_INT_RAW_CH0_REG. + 3 + 0x10 + 0-2 + INT_RAW_CH%s + DMA_INT_RAW_CH%s_REG. 0x0 0x20 - IN_DONE_CH0_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 - read-only + read-write - IN_SUC_EOF_CH0_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 - read-only + read-write - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 - read-only + read-write - OUT_DONE_CH0_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 - read-only + read-write - OUT_EOF_CH0_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 - read-only + read-write - IN_DSCR_ERR_CH0_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 - read-only + read-write - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 - read-only + read-write - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 - read-only + read-write - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 - read-only + read-write - INFIFO_OVF_CH0_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 - read-only + read-write - INFIFO_UDF_CH0_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 - read-only + read-write - OUTFIFO_OVF_CH0_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 - read-only + read-write - OUTFIFO_UDF_CH0_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 - read-only + read-write @@ -3484,91 +3538,91 @@ 0x20 - IN_DONE_CH0_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH0_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH0_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH0_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH0_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH0_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3577,97 +3631,100 @@ - INT_ENA_CH0 - DMA_INT_ENA_CH0_REG. + 3 + 0x10 + 0-2 + INT_ENA_CH%s + DMA_INT_ENA_CH%s_REG. 0x8 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH0_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH0_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH0_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH0_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH0_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3676,97 +3733,100 @@ - INT_CLR_CH0 - DMA_INT_CLR_CH0_REG. + 3 + 0x10 + 0-2 + INT_CLR_CH%s + DMA_INT_CLR_CH%s_REG. 0xC 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH0_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH0_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH0_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH0_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH0_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3774,105 +3834,6 @@ - - INT_RAW_CH1 - DMA_INT_RAW_CH1_REG. - 0x10 - 0x20 - - - IN_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. - 0 - 1 - read-only - - - IN_SUC_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-only - - - IN_ERR_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved. - 2 - 1 - read-only - - - OUT_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1. - 3 - 1 - read-only - - - OUT_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1. - 4 - 1 - read-only - - - IN_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 5 - 1 - read-only - - - OUT_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1. - 6 - 1 - read-only - - - IN_DSCR_EMPTY_CH1_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1. - 7 - 1 - read-only - - - OUT_TOTAL_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1. - 8 - 1 - read-only - - - INFIFO_OVF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow. - 9 - 1 - read-only - - - INFIFO_UDF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow. - 10 - 1 - read-only - - - OUTFIFO_OVF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow. - 11 - 1 - read-only - - - OUTFIFO_UDF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow. - 12 - 1 - read-only - - - INT_ST_CH1 DMA_INT_ST_CH1_REG. @@ -3880,91 +3841,91 @@ 0x20 - IN_DONE_CH1_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH1_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH1_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH1_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH1_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH1_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH1_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH1_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH1_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH1_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH1_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH1_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH1_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3972,303 +3933,6 @@ - - INT_ENA_CH1 - DMA_INT_ENA_CH1_REG. - 0x18 - 0x20 - - - IN_DONE_CH1_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_DONE_CH1_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 3 - 1 - read-write - - - OUT_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 4 - 1 - read-write - - - IN_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - read-write - - - OUT_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_TOTAL_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - read-write - - - INFIFO_OVF_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - read-write - - - INFIFO_UDF_CH1_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - read-write - - - OUTFIFO_OVF_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - read-write - - - OUTFIFO_UDF_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - read-write - - - - - INT_CLR_CH1 - DMA_INT_CLR_CH1_REG. - 0x1C - 0x20 - - - IN_DONE_CH1_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH1_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH1_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_DONE_CH1_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 3 - 1 - write-only - - - OUT_EOF_CH1_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 4 - 1 - write-only - - - IN_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - write-only - - - OUT_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - write-only - - - IN_DSCR_EMPTY_CH1_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_TOTAL_EOF_CH1_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - write-only - - - INFIFO_OVF_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - write-only - - - INFIFO_UDF_CH1_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - write-only - - - OUTFIFO_OVF_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - write-only - - - OUTFIFO_UDF_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - write-only - - - - - INT_RAW_CH2 - DMA_INT_RAW_CH2_REG. - 0x20 - 0x20 - - - IN_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. - 0 - 1 - read-only - - - IN_SUC_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2. - 1 - 1 - read-only - - - IN_ERR_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved. - 2 - 1 - read-only - - - OUT_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2. - 3 - 1 - read-only - - - OUT_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2. - 4 - 1 - read-only - - - IN_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2. - 5 - 1 - read-only - - - OUT_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2. - 6 - 1 - read-only - - - IN_DSCR_EMPTY_CH2_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2. - 7 - 1 - read-only - - - OUT_TOTAL_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2. - 8 - 1 - read-only - - - INFIFO_OVF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow. - 9 - 1 - read-only - - - INFIFO_UDF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow. - 10 - 1 - read-only - - - OUTFIFO_OVF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow. - 11 - 1 - read-only - - - OUTFIFO_UDF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow. - 12 - 1 - read-only - - - INT_ST_CH2 DMA_INT_ST_CH2_REG. @@ -4276,91 +3940,91 @@ 0x20 - IN_DONE_CH2_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH2_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH2_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH2_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH2_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH2_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH2_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH2_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH2_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH2_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH2_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH2_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH2_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4368,204 +4032,6 @@ - - INT_ENA_CH2 - DMA_INT_ENA_CH2_REG. - 0x28 - 0x20 - - - IN_DONE_CH2_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_DONE_CH2_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 3 - 1 - read-write - - - OUT_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 4 - 1 - read-write - - - IN_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - read-write - - - OUT_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - read-write - - - IN_DSCR_EMPTY_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_TOTAL_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - read-write - - - INFIFO_OVF_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - read-write - - - INFIFO_UDF_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - read-write - - - OUTFIFO_OVF_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - read-write - - - OUTFIFO_UDF_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - read-write - - - - - INT_CLR_CH2 - DMA_INT_CLR_CH2_REG. - 0x2C - 0x20 - - - IN_DONE_CH2_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH2_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH2_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_DONE_CH2_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 3 - 1 - write-only - - - OUT_EOF_CH2_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 4 - 1 - write-only - - - IN_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - write-only - - - OUT_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - write-only - - - IN_DSCR_EMPTY_CH2_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_TOTAL_EOF_CH2_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - write-only - - - INFIFO_OVF_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - write-only - - - INFIFO_UDF_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - write-only - - - OUTFIFO_OVF_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - write-only - - - OUTFIFO_UDF_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - write-only - - - AHB_TEST DMA_AHB_TEST_REG. @@ -4634,41 +4100,44 @@ - IN_CONF0_CH0 - DMA_IN_CONF0_CH0_REG. + 3 + 0xC0 + 0-2 + IN_CONF0_CH%s + DMA_IN_CONF%s_CH%s_REG. 0x70 0x20 - IN_RST_CH0 + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH0 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH0 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH0 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -4683,7 +4152,7 @@ 0x20 - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -4699,56 +4168,56 @@ 0x07800003 - INFIFO_FULL_CH0 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_CH0 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_CNT_CH0 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only - IN_REMAIN_UNDER_1B_CH0 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH0 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH0 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH0 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH0 + IN_BUF_HUNGRY reserved 27 1 @@ -4764,14 +4233,14 @@ 0x00000800 - INFIFO_RDATA_CH0 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH0 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -4780,49 +4249,52 @@ - IN_LINK_CH0 - DMA_IN_LINK_CH0_REG. + 3 + 0xC0 + 0-2 + IN_LINK_CH%s + DMA_IN_LINK_CH%s_REG. 0x80 0x20 0x01100000 - INLINK_ADDR_CH0 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -4837,21 +4309,21 @@ 0x20 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH0 + IN_STATE reserved 20 3 @@ -4866,7 +4338,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -4881,7 +4353,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -4896,7 +4368,7 @@ 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -4905,13 +4377,16 @@ - IN_DSCR_BF0_CH0 - DMA_IN_DSCR_BF0_CH0_REG. + 3 + 0xC0 + 0-2 + IN_DSCR_BF0_CH%s + DMA_IN_DSCR_BF%s_CH%s_REG. 0x94 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -4926,7 +4401,7 @@ 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -4935,13 +4410,16 @@ - IN_PRI_CH0 - DMA_IN_PRI_CH0_REG. + 3 + 0xC0 + 0-2 + IN_PRI_CH%s + DMA_IN_PRI_CH%s_REG. 0x9C 0x20 - RX_PRI_CH0 + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -4950,14 +4428,17 @@ - IN_PERI_SEL_CH0 - DMA_IN_PERI_SEL_CH0_REG. + 3 + 0xC0 + 0-2 + IN_PERI_SEL_CH%s + DMA_IN_PERI_SEL_CH%s_REG. 0xA0 0x20 0x0000003F - PERI_IN_SEL_CH0 + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -4966,49 +4447,52 @@ - OUT_CONF0_CH0 - DMA_OUT_CONF0_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_CONF0_CH%s + DMA_OUT_CONF%s_CH%s_REG. 0xD0 0x20 0x00000008 - OUT_RST_CH0 + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH0 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH0 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -5017,13 +4501,16 @@ - OUT_CONF1_CH0 - DMA_OUT_CONF1_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_CONF1_CH%s + DMA_OUT_CONF1_CH%s_REG. 0xD4 0x20 - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5039,49 +4526,49 @@ 0x07800002 - OUTFIFO_FULL_CH0 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_CH0 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_CNT_CH0 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH0 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH0 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH0 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH0 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5096,14 +4583,14 @@ 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5112,42 +4599,45 @@ - OUT_LINK_CH0 - DMA_OUT_LINK_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_LINK_CH%s + DMA_OUT_LINK_CH%s_REG. 0xE0 0x20 0x00800000 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH0 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5162,21 +4652,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH0 + OUT_STATE reserved 20 3 @@ -5185,13 +4675,16 @@ - OUT_EOF_DES_ADDR_CH0 - DMA_OUT_EOF_DES_ADDR_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_EOF_DES_ADDR_CH%s + DMA_OUT_EOF_DES_ADDR_CH%s_REG. 0xE8 0x20 - OUT_EOF_DES_ADDR_CH0 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5206,7 +4699,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH0 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5221,7 +4714,7 @@ 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5236,7 +4729,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5251,7 +4744,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5260,13 +4753,16 @@ - OUT_PRI_CH0 - DMA_OUT_PRI_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_PRI_CH%s + DMA_OUT_PRI_CH%s_REG. 0xFC 0x20 - TX_PRI_CH0 + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5275,14 +4771,17 @@ - OUT_PERI_SEL_CH0 - DMA_OUT_PERI_SEL_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_PERI_SEL_CH%s + DMA_OUT_PERI_SEL_CH%s_REG. 0x100 0x20 0x0000003F - PERI_OUT_SEL_CH0 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -5290,49 +4789,6 @@ - - IN_CONF0_CH1 - DMA_IN_CONF0_CH1_REG. - 0x130 - 0x20 - - - IN_RST_CH1 - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH1 - reserved - 1 - 1 - read-write - - - INDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - IN_DATA_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM. - 3 - 1 - read-write - - - MEM_TRANS_EN_CH1 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - 4 - 1 - read-write - - - IN_CONF1_CH1 DMA_IN_CONF1_CH1_REG. @@ -5340,7 +4796,7 @@ 0x20 - IN_CHECK_OWNER_CH1 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5356,56 +4812,56 @@ 0x07800003 - INFIFO_FULL_CH1 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 1. 0 1 read-only - INFIFO_EMPTY_CH1 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 1. 1 1 read-only - INFIFO_CNT_CH1 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. 2 6 read-only - IN_REMAIN_UNDER_1B_CH1 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH1 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH1 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH1 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH1 + IN_BUF_HUNGRY reserved 27 1 @@ -5421,14 +4877,14 @@ 0x00000800 - INFIFO_RDATA_CH1 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH1 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -5436,57 +4892,6 @@ - - IN_LINK_CH1 - DMA_IN_LINK_CH1_REG. - 0x140 - 0x20 - 0x01100000 - - - INLINK_ADDR_CH1 - This register stores the 20 least significant bits of the first inlink descriptor's address. - 0 - 20 - read-write - - - INLINK_AUTO_RET_CH1 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH1 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH1 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH1 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH1 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - IN_STATE_CH1 DMA_IN_STATE_CH1_REG. @@ -5494,21 +4899,21 @@ 0x20 - INLINK_DSCR_ADDR_CH1 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH1 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH1 + IN_STATE reserved 20 3 @@ -5523,7 +4928,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH1 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5538,7 +4943,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH1 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -5553,7 +4958,7 @@ 0x20 - INLINK_DSCR_CH1 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -5561,21 +4966,6 @@ - - IN_DSCR_BF0_CH1 - DMA_IN_DSCR_BF0_CH1_REG. - 0x154 - 0x20 - - - INLINK_DSCR_BF0_CH1 - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - IN_DSCR_BF1_CH1 DMA_IN_DSCR_BF1_CH1_REG. @@ -5583,7 +4973,7 @@ 0x20 - INLINK_DSCR_BF1_CH1 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5591,103 +4981,6 @@ - - IN_PRI_CH1 - DMA_IN_PRI_CH1_REG. - 0x15C - 0x20 - - - RX_PRI_CH1 - The priority of Rx channel 1. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - IN_PERI_SEL_CH1 - DMA_IN_PERI_SEL_CH1_REG. - 0x160 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH1 - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - OUT_CONF0_CH1 - DMA_OUT_CONF0_CH1_REG. - 0x190 - 0x20 - 0x00000008 - - - OUT_RST_CH1 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH1 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH1 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - - - OUT_CONF1_CH1 - DMA_OUT_CONF1_CH1_REG. - 0x194 - 0x20 - - - OUT_CHECK_OWNER_CH1 - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - OUTFIFO_STATUS_CH1 DMA_OUTFIFO_STATUS_CH1_REG. @@ -5696,49 +4989,49 @@ 0x07800002 - OUTFIFO_FULL_CH1 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 1. 0 1 read-only - OUTFIFO_EMPTY_CH1 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 1. 1 1 read-only - OUTFIFO_CNT_CH1 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH1 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH1 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH1 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH1 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5753,14 +5046,14 @@ 0x20 - OUTFIFO_WDATA_CH1 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH1 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5768,50 +5061,6 @@ - - OUT_LINK_CH1 - DMA_OUT_LINK_CH1_REG. - 0x1A0 - 0x20 - 0x00800000 - - - OUTLINK_ADDR_CH1 - This register stores the 20 least significant bits of the first outlink descriptor's address. - 0 - 20 - read-write - - - OUTLINK_STOP_CH1 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH1 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH1 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH1 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - OUT_STATE_CH1 DMA_OUT_STATE_CH1_REG. @@ -5819,21 +5068,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH1 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH1 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH1 + OUT_STATE reserved 20 3 @@ -5841,21 +5090,6 @@ - - OUT_EOF_DES_ADDR_CH1 - DMA_OUT_EOF_DES_ADDR_CH1_REG. - 0x1A8 - 0x20 - - - OUT_EOF_DES_ADDR_CH1 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - OUT_EOF_BFR_DES_ADDR_CH1 DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. @@ -5863,7 +5097,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH1 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5878,7 +5112,7 @@ 0x20 - OUTLINK_DSCR_CH1 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5893,7 +5127,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH1 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5908,7 +5142,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH1 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5916,80 +5150,6 @@ - - OUT_PRI_CH1 - DMA_OUT_PRI_CH1_REG. - 0x1BC - 0x20 - - - TX_PRI_CH1 - The priority of Tx channel 1. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - OUT_PERI_SEL_CH1 - DMA_OUT_PERI_SEL_CH1_REG. - 0x1C0 - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH1 - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - IN_CONF0_CH2 - DMA_IN_CONF0_CH2_REG. - 0x1F0 - 0x20 - - - IN_RST_CH2 - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH2 - reserved - 1 - 1 - read-write - - - INDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - IN_DATA_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM. - 3 - 1 - read-write - - - MEM_TRANS_EN_CH2 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - 4 - 1 - read-write - - - IN_CONF1_CH2 DMA_IN_CONF1_CH2_REG. @@ -5997,7 +5157,7 @@ 0x20 - IN_CHECK_OWNER_CH2 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -6013,56 +5173,56 @@ 0x07800003 - INFIFO_FULL_CH2 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 2. 0 1 read-only - INFIFO_EMPTY_CH2 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 2. 1 1 read-only - INFIFO_CNT_CH2 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. 2 6 read-only - IN_REMAIN_UNDER_1B_CH2 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH2 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH2 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH2 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH2 + IN_BUF_HUNGRY reserved 27 1 @@ -6078,14 +5238,14 @@ 0x00000800 - INFIFO_RDATA_CH2 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH2 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -6093,57 +5253,6 @@ - - IN_LINK_CH2 - DMA_IN_LINK_CH2_REG. - 0x200 - 0x20 - 0x01100000 - - - INLINK_ADDR_CH2 - This register stores the 20 least significant bits of the first inlink descriptor's address. - 0 - 20 - read-write - - - INLINK_AUTO_RET_CH2 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH2 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH2 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH2 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH2 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - IN_STATE_CH2 DMA_IN_STATE_CH2_REG. @@ -6151,21 +5260,21 @@ 0x20 - INLINK_DSCR_ADDR_CH2 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH2 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH2 + IN_STATE reserved 20 3 @@ -6180,7 +5289,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH2 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -6195,7 +5304,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH2 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -6210,7 +5319,7 @@ 0x20 - INLINK_DSCR_CH2 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -6218,21 +5327,6 @@ - - IN_DSCR_BF0_CH2 - DMA_IN_DSCR_BF0_CH2_REG. - 0x214 - 0x20 - - - INLINK_DSCR_BF0_CH2 - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - IN_DSCR_BF1_CH2 DMA_IN_DSCR_BF1_CH2_REG. @@ -6240,7 +5334,7 @@ 0x20 - INLINK_DSCR_BF1_CH2 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6248,103 +5342,6 @@ - - IN_PRI_CH2 - DMA_IN_PRI_CH2_REG. - 0x21C - 0x20 - - - RX_PRI_CH2 - The priority of Rx channel 2. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - IN_PERI_SEL_CH2 - DMA_IN_PERI_SEL_CH2_REG. - 0x220 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH2 - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - OUT_CONF0_CH2 - DMA_OUT_CONF0_CH2_REG. - 0x250 - 0x20 - 0x00000008 - - - OUT_RST_CH2 - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH2 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH2 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - - - OUT_CONF1_CH2 - DMA_OUT_CONF1_CH2_REG. - 0x254 - 0x20 - - - OUT_CHECK_OWNER_CH2 - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - OUTFIFO_STATUS_CH2 DMA_OUTFIFO_STATUS_CH2_REG. @@ -6353,49 +5350,49 @@ 0x07800002 - OUTFIFO_FULL_CH2 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 2. 0 1 read-only - OUTFIFO_EMPTY_CH2 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 2. 1 1 read-only - OUTFIFO_CNT_CH2 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH2 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH2 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH2 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH2 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -6410,14 +5407,14 @@ 0x20 - OUTFIFO_WDATA_CH2 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH2 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -6425,50 +5422,6 @@ - - OUT_LINK_CH2 - DMA_OUT_LINK_CH2_REG. - 0x260 - 0x20 - 0x00800000 - - - OUTLINK_ADDR_CH2 - This register stores the 20 least significant bits of the first outlink descriptor's address. - 0 - 20 - read-write - - - OUTLINK_STOP_CH2 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH2 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH2 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH2 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - OUT_STATE_CH2 DMA_OUT_STATE_CH2_REG. @@ -6476,21 +5429,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH2 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH2 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH2 + OUT_STATE reserved 20 3 @@ -6498,21 +5451,6 @@ - - OUT_EOF_DES_ADDR_CH2 - DMA_OUT_EOF_DES_ADDR_CH2_REG. - 0x268 - 0x20 - - - OUT_EOF_DES_ADDR_CH2 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - OUT_EOF_BFR_DES_ADDR_CH2 DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. @@ -6520,7 +5458,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH2 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -6535,7 +5473,7 @@ 0x20 - OUTLINK_DSCR_CH2 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -6550,7 +5488,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH2 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -6565,7 +5503,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH2 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6573,37 +5511,6 @@ - - OUT_PRI_CH2 - DMA_OUT_PRI_CH2_REG. - 0x27C - 0x20 - - - TX_PRI_CH2 - The priority of Tx channel 2. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - OUT_PERI_SEL_CH2 - DMA_OUT_PERI_SEL_CH2_REG. - 0x280 - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH2 - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - @@ -6613,57 +5520,57 @@ 0x6003D000 0x0 - 0xA4C + 0x108C registers - 512 - 0x1 + 128 + 0x4 Y_MEM[%s] memory that stores Y 0x0 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 M_MEM[%s] memory that stores M 0x200 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 RB_MEM[%s] memory that stores Rb 0x400 - 0x8 + 0x20 - 48 - 0x1 + 12 + 0x4 BOX_MEM[%s] memory that stores BOX 0x600 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 X_MEM[%s] memory that stores X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] memory that stores Z 0xA00 - 0x8 + 0x20 SET_START @@ -9125,7 +8032,7 @@ CLK - eFuse clcok configuration register. + eFuse clock configuration register. 0x1C8 0x20 0x00000002 @@ -9162,7 +8069,7 @@ CONF - eFuse operation mode configuraiton register; + eFuse operation mode configuration register. 0x1CC 0x20 @@ -9411,7 +8318,7 @@ WR_TIM_CONF1 - Configurarion register 1 of eFuse programming timing parameters. + Configuration register 1 of eFuse programming timing parameters. 0x1F0 0x20 0x00288000 @@ -9427,7 +8334,7 @@ WR_TIM_CONF2 - Configurarion register 2 of eFuse programming timing parameters. + Configuration register 2 of eFuse programming timing parameters. 0x1F4 0x20 0x00000190 @@ -11190,55 +10097,56 @@ 26 0x4 + 0-25 PIN%s GPIO pin configuration register 0x74 0x20 - PIN_SYNC2_BYPASS - set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write - PIN_PAD_DRIVER - set this bit to select pad driver. 1:open-drain. :normal. + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write - PIN_SYNC1_BYPASS - set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write - PIN_INT_TYPE - set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write - PIN_CONFIG + CONFIG reserved 11 2 read-write - PIN_INT_ENA + INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 @@ -11264,6 +10172,7 @@ 128 0x4 + 0-127 FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 @@ -11271,21 +10180,21 @@ IN_SEL - set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level. + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 5 read-write IN_INV_SEL - set this bit to invert input signal. 1:invert. :not invert. + set this bit to invert input signal. 1:invert. 0:not invert. 5 1 read-write SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO. + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 6 1 read-write @@ -11295,6 +10204,7 @@ 26 0x4 + 0-25 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 @@ -11303,28 +10213,28 @@ OUT_SEL - The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write INV_SEL - set this bit to invert output signal.1:invert.:not invert. + set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal. + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write OEN_INV_SEL - set this bit to invert output enable signal.1:invert.:not invert. + set this bit to invert output enable signal.1:invert.0:not invert. 10 1 read-write @@ -11366,7 +10276,7 @@ - GPIOSD + GPIO_SD Sigma-Delta Modulation GPIOSD 0x60004F00 @@ -11463,7 +10373,7 @@ 0x6003E000 0x0 - 0xA0 + 0xA4 registers @@ -11624,7 +10534,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 @@ -11648,20 +10558,20 @@ - 64 - 0x1 + 16 + 0x4 WR_MESSAGE_MEM[%s] Message block memory. 0x80 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 RD_RESULT_MEM[%s] Result from upstream. 0xC0 - 0x8 + 0x20 SET_MESSAGE_PAD @@ -11727,7 +10637,7 @@ I2C0 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 0 I2C 0x60013000 @@ -11735,6 +10645,10 @@ 0x90 registers + + I2C_MASTER + 11 + I2C_EXT0 29 @@ -12846,6 +11760,7 @@ 8 0x4 + 0-7 COMD%s I2C_COMD%s_REG 0x58 @@ -13027,8 +11942,8 @@ - I2S - I2S (Inter-IC Sound) Controller + I2S0 + I2S (Inter-IC Sound) Controller 0 I2S 0x6002D000 @@ -13037,7 +11952,7 @@ registers - I2S + I2S0 20 @@ -14302,7 +13217,7 @@ INTERRUPT_CORE0 - Interrupt Core + Interrupt Controller (Core 0) INTERRUPT_CORE0 0x600C2000 @@ -14310,6 +13225,110 @@ 0x19C registers + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SLC0 + 12 + + + SLC1 + 13 + + + CACHE_IA + 36 + + + ICACHE_PRELOAD0 + 41 + + + ICACHE_SYNC0 + 42 + + + FROM_CPU_INTR0 + 50 + + + FROM_CPU_INTR1 + 51 + + + FROM_CPU_INTR2 + 52 + + + FROM_CPU_INTR3 + 53 + + + CORE0_IRAM0_PMS + 56 + + + CORE0_DRAM0_PMS + 57 + + + CORE0_PIF_PMS + 58 + + + CORE0_PIF_PMS_SIZE + 59 + + + BAK_PMS_VIOLATE + 60 + + + CACHE_CORE0_ACS + 61 + MAC_INTR_MAP @@ -16021,57 +15040,68 @@ LEDC 23 + + TIMER1 + 30 + + + TIMER2 + 31 + - LSCH0_CONF0 - LEDC_LSCH0_CONF0. + 6 + 0x14 + 0-5 + CH%s_CONF0 + LEDC_LSCH%s_CONF%s. 0x0 0x20 - TIMER_SEL_LSCH0 + TIMER_SEL reg_timer_sel_lsch0. 0 2 read-write - SIG_OUT_EN_LSCH0 + SIG_OUT_EN reg_sig_out_en_lsch0. 2 1 read-write - IDLE_LV_LSCH0 + IDLE_LV reg_idle_lv_lsch0. 3 1 read-write - PARA_UP_LSCH0 + PARA_UP reg_para_up_lsch0. 4 1 write-only - OVF_NUM_LSCH0 + OVF_NUM reg_ovf_num_lsch0. 5 10 read-write - OVF_CNT_EN_LSCH0 + OVF_CNT_EN reg_ovf_cnt_en_lsch0. 15 1 read-write - OVF_CNT_RESET_LSCH0 + OVF_CNT_RESET reg_ovf_cnt_reset_lsch0. 16 1 @@ -16080,13 +15110,16 @@ - LSCH0_HPOINT - LEDC_LSCH0_HPOINT. + 6 + 0x14 + 0-5 + CH%s_HPOINT + LEDC_LSCH%s_HPOINT. 0x4 0x20 - HPOINT_LSCH0 + HPOINT reg_hpoint_lsch0. 0 14 @@ -16095,13 +15128,16 @@ - LSCH0_DUTY - LEDC_LSCH0_DUTY. + 6 + 0x14 + 0-5 + CH%s_DUTY + LEDC_LSCH%s_DUTY. 0x8 0x20 - DUTY_LSCH0 + DUTY reg_duty_lsch0. 0 19 @@ -16110,42 +15146,45 @@ - LSCH0_CONF1 - LEDC_LSCH0_CONF1. + 6 + 0x14 + 0-5 + CH%s_CONF1 + LEDC_LSCH%s_CONF1. 0xC 0x20 0x40000000 - DUTY_SCALE_LSCH0 + DUTY_SCALE reg_duty_scale_lsch0. 0 10 read-write - DUTY_CYCLE_LSCH0 + DUTY_CYCLE reg_duty_cycle_lsch0. 10 10 read-write - DUTY_NUM_LSCH0 + DUTY_NUM reg_duty_num_lsch0. 20 10 read-write - DUTY_INC_LSCH0 + DUTY_INC reg_duty_inc_lsch0. 30 1 read-write - DUTY_START_LSCH0 + DUTY_START reg_duty_start_lsch0. 31 1 @@ -16154,13 +15193,16 @@ - LSCH0_DUTY_R - LEDC_LSCH0_DUTY_R. + 6 + 0x14 + 0-5 + CH%s_DUTY_R + LEDC_LSCH%s_DUTY_R. 0x10 0x20 - DUTY_LSCH0_R + DUTY_R reg_duty_lsch0_r. 0 19 @@ -16169,779 +15211,52 @@ - LSCH1_CONF0 - LEDC_LSCH1_CONF0. - 0x14 - 0x20 - - - TIMER_SEL_LSCH1 - reg_timer_sel_lsch1. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH1 - reg_sig_out_en_lsch1. - 2 - 1 - read-write - - - IDLE_LV_LSCH1 - reg_idle_lv_lsch1. - 3 - 1 - read-write - - - PARA_UP_LSCH1 - reg_para_up_lsch1. - 4 - 1 - write-only - - - OVF_NUM_LSCH1 - reg_ovf_num_lsch1. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH1 - reg_ovf_cnt_en_lsch1. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH1 - reg_ovf_cnt_reset_lsch1. - 16 - 1 - write-only - - - - - LSCH1_HPOINT - LEDC_LSCH1_HPOINT. - 0x18 - 0x20 - - - HPOINT_LSCH1 - reg_hpoint_lsch1. - 0 - 14 - read-write - - - - - LSCH1_DUTY - LEDC_LSCH1_DUTY. - 0x1C - 0x20 - - - DUTY_LSCH1 - reg_duty_lsch1. - 0 - 19 - read-write - - - - - LSCH1_CONF1 - LEDC_LSCH1_CONF1. - 0x20 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH1 - reg_duty_scale_lsch1. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH1 - reg_duty_cycle_lsch1. - 10 - 10 - read-write - - - DUTY_NUM_LSCH1 - reg_duty_num_lsch1. - 20 - 10 - read-write - - - DUTY_INC_LSCH1 - reg_duty_inc_lsch1. - 30 - 1 - read-write - - - DUTY_START_LSCH1 - reg_duty_start_lsch1. - 31 - 1 - read-write - - - - - LSCH1_DUTY_R - LEDC_LSCH1_DUTY_R. - 0x24 - 0x20 - - - DUTY_LSCH1_R - reg_duty_lsch1_r. - 0 - 19 - read-only - - - - - LSCH2_CONF0 - LEDC_LSCH2_CONF0. - 0x28 - 0x20 - - - TIMER_SEL_LSCH2 - reg_timer_sel_lsch2. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH2 - reg_sig_out_en_lsch2. - 2 - 1 - read-write - - - IDLE_LV_LSCH2 - reg_idle_lv_lsch2. - 3 - 1 - read-write - - - PARA_UP_LSCH2 - reg_para_up_lsch2. - 4 - 1 - write-only - - - OVF_NUM_LSCH2 - reg_ovf_num_lsch2. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH2 - reg_ovf_cnt_en_lsch2. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH2 - reg_ovf_cnt_reset_lsch2. - 16 - 1 - write-only - - - - - LSCH2_HPOINT - LEDC_LSCH2_HPOINT. - 0x2C - 0x20 - - - HPOINT_LSCH2 - reg_hpoint_lsch2. - 0 - 14 - read-write - - - - - LSCH2_DUTY - LEDC_LSCH2_DUTY. - 0x30 - 0x20 - - - DUTY_LSCH2 - reg_duty_lsch2. - 0 - 19 - read-write - - - - - LSCH2_CONF1 - LEDC_LSCH2_CONF1. - 0x34 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH2 - reg_duty_scale_lsch2. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH2 - reg_duty_cycle_lsch2. - 10 - 10 - read-write - - - DUTY_NUM_LSCH2 - reg_duty_num_lsch2. - 20 - 10 - read-write - - - DUTY_INC_LSCH2 - reg_duty_inc_lsch2. - 30 - 1 - read-write - - - DUTY_START_LSCH2 - reg_duty_start_lsch2. - 31 - 1 - read-write - - - - - LSCH2_DUTY_R - LEDC_LSCH2_DUTY_R. - 0x38 - 0x20 - - - DUTY_LSCH2_R - reg_duty_lsch2_r. - 0 - 19 - read-only - - - - - LSCH3_CONF0 - LEDC_LSCH3_CONF0. - 0x3C - 0x20 - - - TIMER_SEL_LSCH3 - reg_timer_sel_lsch3. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH3 - reg_sig_out_en_lsch3. - 2 - 1 - read-write - - - IDLE_LV_LSCH3 - reg_idle_lv_lsch3. - 3 - 1 - read-write - - - PARA_UP_LSCH3 - reg_para_up_lsch3. - 4 - 1 - write-only - - - OVF_NUM_LSCH3 - reg_ovf_num_lsch3. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH3 - reg_ovf_cnt_en_lsch3. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH3 - reg_ovf_cnt_reset_lsch3. - 16 - 1 - write-only - - - - - LSCH3_HPOINT - LEDC_LSCH3_HPOINT. - 0x40 - 0x20 - - - HPOINT_LSCH3 - reg_hpoint_lsch3. - 0 - 14 - read-write - - - - - LSCH3_DUTY - LEDC_LSCH3_DUTY. - 0x44 - 0x20 - - - DUTY_LSCH3 - reg_duty_lsch3. - 0 - 19 - read-write - - - - - LSCH3_CONF1 - LEDC_LSCH3_CONF1. - 0x48 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH3 - reg_duty_scale_lsch3. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH3 - reg_duty_cycle_lsch3. - 10 - 10 - read-write - - - DUTY_NUM_LSCH3 - reg_duty_num_lsch3. - 20 - 10 - read-write - - - DUTY_INC_LSCH3 - reg_duty_inc_lsch3. - 30 - 1 - read-write - - - DUTY_START_LSCH3 - reg_duty_start_lsch3. - 31 - 1 - read-write - - - - - LSCH3_DUTY_R - LEDC_LSCH3_DUTY_R. - 0x4C - 0x20 - - - DUTY_LSCH3_R - reg_duty_lsch3_r. - 0 - 19 - read-only - - - - - LSCH4_CONF0 - LEDC_LSCH4_CONF0. - 0x50 - 0x20 - - - TIMER_SEL_LSCH4 - reg_timer_sel_lsch4. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH4 - reg_sig_out_en_lsch4. - 2 - 1 - read-write - - - IDLE_LV_LSCH4 - reg_idle_lv_lsch4. - 3 - 1 - read-write - - - PARA_UP_LSCH4 - reg_para_up_lsch4. - 4 - 1 - write-only - - - OVF_NUM_LSCH4 - reg_ovf_num_lsch4. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH4 - reg_ovf_cnt_en_lsch4. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH4 - reg_ovf_cnt_reset_lsch4. - 16 - 1 - write-only - - - - - LSCH4_HPOINT - LEDC_LSCH4_HPOINT. - 0x54 - 0x20 - - - HPOINT_LSCH4 - reg_hpoint_lsch4. - 0 - 14 - read-write - - - - - LSCH4_DUTY - LEDC_LSCH4_DUTY. - 0x58 - 0x20 - - - DUTY_LSCH4 - reg_duty_lsch4. - 0 - 19 - read-write - - - - - LSCH4_CONF1 - LEDC_LSCH4_CONF1. - 0x5C - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH4 - reg_duty_scale_lsch4. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH4 - reg_duty_cycle_lsch4. - 10 - 10 - read-write - - - DUTY_NUM_LSCH4 - reg_duty_num_lsch4. - 20 - 10 - read-write - - - DUTY_INC_LSCH4 - reg_duty_inc_lsch4. - 30 - 1 - read-write - - - DUTY_START_LSCH4 - reg_duty_start_lsch4. - 31 - 1 - read-write - - - - - LSCH4_DUTY_R - LEDC_LSCH4_DUTY_R. - 0x60 - 0x20 - - - DUTY_LSCH4_R - reg_duty_lsch4_r. - 0 - 19 - read-only - - - - - LSCH5_CONF0 - LEDC_LSCH5_CONF0. - 0x64 - 0x20 - - - TIMER_SEL_LSCH5 - reg_timer_sel_lsch5. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH5 - reg_sig_out_en_lsch5. - 2 - 1 - read-write - - - IDLE_LV_LSCH5 - reg_idle_lv_lsch5. - 3 - 1 - read-write - - - PARA_UP_LSCH5 - reg_para_up_lsch5. - 4 - 1 - write-only - - - OVF_NUM_LSCH5 - reg_ovf_num_lsch5. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH5 - reg_ovf_cnt_en_lsch5. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH5 - reg_ovf_cnt_reset_lsch5. - 16 - 1 - write-only - - - - - LSCH5_HPOINT - LEDC_LSCH5_HPOINT. - 0x68 - 0x20 - - - HPOINT_LSCH5 - reg_hpoint_lsch5. - 0 - 14 - read-write - - - - - LSCH5_DUTY - LEDC_LSCH5_DUTY. - 0x6C - 0x20 - - - DUTY_LSCH5 - reg_duty_lsch5. - 0 - 19 - read-write - - - - - LSCH5_CONF1 - LEDC_LSCH5_CONF1. - 0x70 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH5 - reg_duty_scale_lsch5. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH5 - reg_duty_cycle_lsch5. - 10 - 10 - read-write - - - DUTY_NUM_LSCH5 - reg_duty_num_lsch5. - 20 - 10 - read-write - - - DUTY_INC_LSCH5 - reg_duty_inc_lsch5. - 30 - 1 - read-write - - - DUTY_START_LSCH5 - reg_duty_start_lsch5. - 31 - 1 - read-write - - - - - LSCH5_DUTY_R - LEDC_LSCH5_DUTY_R. - 0x74 - 0x20 - - - DUTY_LSCH5_R - reg_duty_lsch5_r. - 0 - 19 - read-only - - - - - LSTIMER0_CONF - LEDC_LSTIMER0_CONF. + 4 + 0x8 + 0-3 + TIMER%s_CONF + LEDC_LSTIMER%s_CONF. 0xA0 0x20 0x00800000 - LSTIMER0_DUTY_RES + DUTY_RES reg_lstimer0_duty_res. 0 4 read-write - CLK_DIV_LSTIMER0 + CLK_DIV reg_clk_div_lstimer0. 4 18 read-write - LSTIMER0_PAUSE + PAUSE reg_lstimer0_pause. 22 1 read-write - LSTIMER0_RST + RST reg_lstimer0_rst. 23 1 read-write - TICK_SEL_LSTIMER0 + TICK_SEL reg_tick_sel_lstimer0. 24 1 read-write - LSTIMER0_PARA_UP + PARA_UP reg_lstimer0_para_up. 25 1 @@ -16950,13 +15265,16 @@ - LSTIMER0_VALUE - LEDC_LSTIMER0_VALUE. + 4 + 0x8 + 0-3 + TIMER%s_VALUE + LEDC_LSTIMER%s_VALUE. 0xA4 0x20 - LSTIMER0_CNT + CNT reg_lstimer0_cnt. 0 14 @@ -16964,204 +15282,6 @@ - - LSTIMER1_CONF - LEDC_LSTIMER1_CONF. - 0xA8 - 0x20 - 0x00800000 - - - LSTIMER1_DUTY_RES - reg_lstimer1_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER1 - reg_clk_div_lstimer1. - 4 - 18 - read-write - - - LSTIMER1_PAUSE - reg_lstimer1_pause. - 22 - 1 - read-write - - - LSTIMER1_RST - reg_lstimer1_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER1 - reg_tick_sel_lstimer1. - 24 - 1 - read-write - - - LSTIMER1_PARA_UP - reg_lstimer1_para_up. - 25 - 1 - write-only - - - - - LSTIMER1_VALUE - LEDC_LSTIMER1_VALUE. - 0xAC - 0x20 - - - LSTIMER1_CNT - reg_lstimer1_cnt. - 0 - 14 - read-only - - - - - LSTIMER2_CONF - LEDC_LSTIMER2_CONF. - 0xB0 - 0x20 - 0x00800000 - - - LSTIMER2_DUTY_RES - reg_lstimer2_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER2 - reg_clk_div_lstimer2. - 4 - 18 - read-write - - - LSTIMER2_PAUSE - reg_lstimer2_pause. - 22 - 1 - read-write - - - LSTIMER2_RST - reg_lstimer2_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER2 - reg_tick_sel_lstimer2. - 24 - 1 - read-write - - - LSTIMER2_PARA_UP - reg_lstimer2_para_up. - 25 - 1 - write-only - - - - - LSTIMER2_VALUE - LEDC_LSTIMER2_VALUE. - 0xB4 - 0x20 - - - LSTIMER2_CNT - reg_lstimer2_cnt. - 0 - 14 - read-only - - - - - LSTIMER3_CONF - LEDC_LSTIMER3_CONF. - 0xB8 - 0x20 - 0x00800000 - - - LSTIMER3_DUTY_RES - reg_lstimer3_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER3 - reg_clk_div_lstimer3. - 4 - 18 - read-write - - - LSTIMER3_PAUSE - reg_lstimer3_pause. - 22 - 1 - read-write - - - LSTIMER3_RST - reg_lstimer3_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER3 - reg_tick_sel_lstimer3. - 24 - 1 - read-write - - - LSTIMER3_PARA_UP - reg_lstimer3_para_up. - 25 - 1 - write-only - - - - - LSTIMER3_VALUE - LEDC_LSTIMER3_VALUE. - 0xBC - 0x20 - - - LSTIMER3_CNT - reg_lstimer3_cnt. - 0 - 14 - read-only - - - INT_RAW LEDC_INT_RAW. @@ -17173,112 +15293,112 @@ reg_lstimer0_ovf_int_raw. 0 1 - read-only + read-write LSTIMER1_OVF_INT_RAW reg_lstimer1_ovf_int_raw. 1 1 - read-only + read-write LSTIMER2_OVF_INT_RAW reg_lstimer2_ovf_int_raw. 2 1 - read-only + read-write LSTIMER3_OVF_INT_RAW reg_lstimer3_ovf_int_raw. 3 1 - read-only + read-write DUTY_CHNG_END_LSCH0_INT_RAW reg_duty_chng_end_lsch0_int_raw. 4 1 - read-only + read-write DUTY_CHNG_END_LSCH1_INT_RAW reg_duty_chng_end_lsch1_int_raw. 5 1 - read-only + read-write DUTY_CHNG_END_LSCH2_INT_RAW reg_duty_chng_end_lsch2_int_raw. 6 1 - read-only + read-write DUTY_CHNG_END_LSCH3_INT_RAW reg_duty_chng_end_lsch3_int_raw. 7 1 - read-only + read-write DUTY_CHNG_END_LSCH4_INT_RAW reg_duty_chng_end_lsch4_int_raw. 8 1 - read-only + read-write DUTY_CHNG_END_LSCH5_INT_RAW reg_duty_chng_end_lsch5_int_raw. 9 1 - read-only + read-write OVF_CNT_LSCH0_INT_RAW reg_ovf_cnt_lsch0_int_raw. 10 1 - read-only + read-write OVF_CNT_LSCH1_INT_RAW reg_ovf_cnt_lsch1_int_raw. 11 1 - read-only + read-write OVF_CNT_LSCH2_INT_RAW reg_ovf_cnt_lsch2_int_raw. 12 1 - read-only + read-write OVF_CNT_LSCH3_INT_RAW reg_ovf_cnt_lsch3_int_raw. 13 1 - read-only + read-write OVF_CNT_LSCH4_INT_RAW reg_ovf_cnt_lsch4_int_raw. 14 1 - read-only + read-write OVF_CNT_LSCH5_INT_RAW reg_ovf_cnt_lsch5_int_raw. 15 1 - read-only + read-write @@ -17684,7 +15804,7 @@ RMT - Remote Control Peripheral + Remote Control RMT 0x60016000 @@ -17698,8 +15818,11 @@ - CH0DATA - RMT_CH0DATA_REG. + 4 + 0x4 + 0-3 + CH%sDATA + RMT_CH%sDATA_REG. 0x0 0x20 @@ -17712,51 +15835,6 @@ - - CH1DATA - RMT_CH1DATA_REG. - 0x4 - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - - - CH2DATA - RMT_CH2DATA_REG. - 0x8 - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - - - CH3DATA - RMT_CH3DATA_REG. - 0xC - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - 2 0x4 @@ -17922,7 +16000,10 @@ - CH2CONF1 + 2 + 0x8 + 2-3 + CH%s_RX_CONF1 RMT_CH2CONF1_REG. 0x1C 0x20 @@ -17994,80 +16075,11 @@ - CH3CONF1 - RMT_CH3CONF1_REG. - 0x24 - 0x20 - 0x000001E8 - - - RX_EN - reg_rx_en_ch3. - 0 - 1 - read-write - - - MEM_WR_RST - reg_mem_wr_rst_ch3. - 1 - 1 - write-only - - - APB_MEM_RST - reg_apb_mem_rst_ch3. - 2 - 1 - write-only - - - MEM_OWNER - reg_mem_owner_ch3. - 3 - 1 - read-write - - - RX_FILTER_EN - reg_rx_filter_en_ch3. - 4 - 1 - read-write - - - RX_FILTER_THRES - reg_rx_filter_thres_ch3. - 5 - 8 - read-write - - - MEM_RX_WRAP_EN - reg_mem_rx_wrap_en_ch3. - 13 - 1 - read-write - - - AFIFO_RST - reg_afifo_rst_ch3. - 14 - 1 - write-only - - - CONF_UPDATE - reg_conf_update_ch3. - 15 - 1 - write-only - - - - - CH0STATUS - RMT_CH0STATUS_REG. + 2 + 0x4 + 0-1 + CH%s_TX_STATUS + RMT_CH%sSTATUS_REG. 0x28 0x20 @@ -18123,64 +16135,10 @@ - CH1STATUS - RMT_CH1STATUS_REG. - 0x2C - 0x20 - - - MEM_RADDR_EX - reg_mem_raddr_ex_ch1. - 0 - 9 - read-only - - - STATE - reg_state_ch1. - 9 - 3 - read-only - - - APB_MEM_WADDR - reg_apb_mem_waddr_ch1. - 12 - 9 - read-only - - - APB_MEM_RD_ERR - reg_apb_mem_rd_err_ch1. - 21 - 1 - read-only - - - MEM_EMPTY - reg_mem_empty_ch1. - 22 - 1 - read-only - - - APB_MEM_WR_ERR - reg_apb_mem_wr_err_ch1. - 23 - 1 - read-only - - - APB_MEM_RADDR - reg_apb_mem_raddr_ch1. - 24 - 8 - read-only - - - - - CH2STATUS + 2 + 0x4 + 2-3 + CH%s_RX_STATUS RMT_CH2STATUS_REG. 0x30 0x20 @@ -18229,56 +16187,6 @@ - - CH3STATUS - RMT_CH3STATUS_REG. - 0x34 - 0x20 - - - MEM_WADDR_EX - reg_mem_waddr_ex_ch3. - 0 - 9 - read-only - - - APB_MEM_RADDR - reg_apb_mem_raddr_ch3. - 12 - 9 - read-only - - - STATE - reg_state_ch3. - 22 - 3 - read-only - - - MEM_OWNER_ERR - reg_mem_owner_err_ch3. - 25 - 1 - read-only - - - MEM_FULL - reg_mem_full_ch3. - 26 - 1 - read-only - - - APB_MEM_RD_ERR - reg_apb_mem_rd_err_ch3. - 27 - 1 - read-only - - - INT_RAW RMT_INT_RAW_REG. @@ -18289,75 +16197,71 @@ 2 0x1 0-1 - CH%s_TX_END_INT_RAW + CH%s_TX_END reg_ch%s_tx_end_int_raw. 0 1 - read-only + read-write 2 0x1 2-3 - CH%s_RX_END_INT_RAW + CH%s_RX_END reg_ch2_rx_end_int_raw. 2 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_ERR_INT_RAW + CH%s_TX_ERR reg_ch%s_err_int_raw. 4 1 - read-only + read-write 2 0x1 2-3 - CH%s_RX_ERR_INT_RAW + CH%s_RX_ERR reg_ch2_err_int_raw. 6 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_raw. 8 1 - read-only + read-write - CH2_RX_THR_EVENT_INT_RAW + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_raw. 10 1 - read-only - - - CH3_RX_THR_EVENT_INT_RAW - reg_ch3_rx_thr_event_int_raw. - 11 - 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP reg_ch%s_tx_loop_int_raw. 12 1 - read-only + read-write @@ -18371,7 +16275,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_ST + CH%s_TX_END reg_ch%s_tx_end_int_st. 0 1 @@ -18381,7 +16285,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_ST + CH%s_RX_END reg_ch2_rx_end_int_st. 2 1 @@ -18391,7 +16295,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_ST + CH%s_TX_ERR reg_ch%s_err_int_st. 4 1 @@ -18401,7 +16305,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_ST + CH%s_RX_ERR reg_ch2_err_int_st. 6 1 @@ -18411,31 +16315,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_st. 8 1 read-only - CH2_RX_THR_EVENT_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_st. 10 1 read-only - - CH3_RX_THR_EVENT_INT_ST - reg_ch3_rx_thr_event_int_st. - 11 - 1 - read-only - 2 0x1 0-1 - CH%s_TX_LOOP_INT_ST + CH%s_TX_LOOP reg_ch%s_tx_loop_int_st. 12 1 @@ -18453,7 +16353,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_ENA + CH%s_TX_END reg_ch%s_tx_end_int_ena. 0 1 @@ -18463,7 +16363,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_ENA + CH%s_RX_END reg_ch2_rx_end_int_ena. 2 1 @@ -18473,7 +16373,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_ENA + CH%s_TX_ERR reg_ch%s_err_int_ena. 4 1 @@ -18483,7 +16383,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_ENA + CH%s_RX_ERR reg_ch2_err_int_ena. 6 1 @@ -18493,31 +16393,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_ena. 8 1 read-write - CH2_RX_THR_EVENT_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_ena. 10 1 read-write - - CH3_RX_THR_EVENT_INT_ENA - reg_ch3_rx_thr_event_int_ena. - 11 - 1 - read-write - 2 0x1 0-1 - CH%s_TX_LOOP_INT_ENA + CH%s_TX_LOOP reg_ch%s_tx_loop_int_ena. 12 1 @@ -18535,7 +16431,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_CLR + CH%s_TX_END reg_ch%s_tx_end_int_clr. 0 1 @@ -18545,7 +16441,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_CLR + CH%s_RX_END reg_ch2_rx_end_int_clr. 2 1 @@ -18555,7 +16451,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_CLR + CH%s_TX_ERR reg_ch%s_err_int_clr. 4 1 @@ -18565,7 +16461,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_CLR + CH%s_RX_ERR reg_ch2_err_int_clr. 6 1 @@ -18575,31 +16471,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_clr. 8 1 write-only - CH2_RX_THR_EVENT_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_clr. 10 1 write-only - - CH3_RX_THR_EVENT_INT_CLR - reg_ch3_rx_thr_event_int_clr. - 11 - 1 - write-only - 2 0x1 0-1 - CH%s_TX_LOOP_INT_CLR + CH%s_TX_LOOP reg_ch%s_tx_loop_int_clr. 12 1 @@ -18608,8 +16500,11 @@ - CH0CARRIER_DUTY - RMT_CH0CARRIER_DUTY_REG. + 2 + 0x4 + 0-1 + CH%sCARRIER_DUTY + RMT_CH%sCARRIER_DUTY_REG. 0x48 0x20 0x00400040 @@ -18631,30 +16526,10 @@ - CH1CARRIER_DUTY - RMT_CH1CARRIER_DUTY_REG. - 0x4C - 0x20 - 0x00400040 - - - CARRIER_LOW - reg_carrier_low_ch1. - 0 - 16 - read-write - - - CARRIER_HIGH - reg_carrier_high_ch1. - 16 - 16 - read-write - - - - - CH2_RX_CARRIER_RM + 2 + 0x4 + 2-3 + CH%s_RX_CARRIER_RM RMT_CH2_RX_CARRIER_RM_REG. 0x50 0x20 @@ -18675,28 +16550,6 @@ - - CH3_RX_CARRIER_RM - RMT_CH3_RX_CARRIER_RM_REG. - 0x54 - 0x20 - - - CARRIER_LOW_THRES - reg_carrier_low_thres_ch3. - 0 - 16 - read-write - - - CARRIER_HIGH_THRES - reg_carrier_high_thres_ch3. - 16 - 16 - read-write - - - 2 0x4 @@ -18920,7 +16773,7 @@ RNG - Hardware random number generator + Hardware Random Number Generator RNG 0x60026000 @@ -18934,6 +16787,7 @@ Random number data 0xB0 0x20 + read-only @@ -18953,36 +16807,40 @@ - 16 - 0x1 + 96 + 0x4 M_MEM[%s] The memory that stores M 0x0 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 Z_MEM[%s] The memory that stores Z 0x200 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 Y_MEM[%s] The memory that stores Y 0x400 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 X_MEM[%s] The memory that stores X 0x600 - 0x8 + 0x20 + read-write M_PRIME @@ -19397,7 +17255,7 @@ read-write - RTC_MAIN_TIMER_ALARM_EN + MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 @@ -19433,7 +17291,7 @@ read-write - RTC_TIME_UPDATE + TIME_UPDATE Set 1: to update register with RTC timer 31 1 @@ -19448,7 +17306,7 @@ 0x20 - RTC_TIMER_VALUE0_LOW + TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 @@ -19463,7 +17321,7 @@ 0x20 - RTC_TIMER_VALUE0_HIGH + TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 @@ -19478,14 +17336,14 @@ 0x20 - RTC_SW_CPU_INT + SW_CPU_INT rtc software interrupt to main cpu 0 1 write-only - RTC_SLP_REJECT_CAUSE_CLR + SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 @@ -19900,14 +17758,14 @@ write-only - RTC_DRESET_MASK_APPCPU + DRESET_MASK_APPCPU configure dreset configure 24 1 read-write - RTC_DRESET_MASK_PROCPU + DRESET_MASK_PROCPU configure dreset configure 25 1 @@ -19923,7 +17781,7 @@ 0x00060000 - RTC_WAKEUP_ENA + WAKEUP_ENA wakeup enable bitmap 15 17 @@ -19952,49 +17810,49 @@ read-write - RTC_WDT_INT_ENA + WDT_INT_ENA enable RTC WDT interrupt 3 1 read-write - RTC_BROWN_OUT_INT_ENA + BROWN_OUT_INT_ENA enable brown out interrupt 9 1 read-write - RTC_MAIN_TIMER_INT_ENA + MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 read-write - RTC_SWD_INT_ENA + SWD_INT_ENA enable super watch dog interrupt 15 1 read-write - RTC_XTAL32K_DEAD_INT_ENA + XTAL32K_DEAD_INT_ENA enable xtal32k_dead interrupt 16 1 read-write - RTC_GLITCH_DET_INT_ENA + GLITCH_DET_INT_ENA enbale gitch det interrupt 19 1 read-write - RTC_BBPLL_CAL_INT_ENA + BBPLL_CAL_INT_ENA enbale bbpll cal end interrupt 20 1 @@ -20023,49 +17881,49 @@ read-only - RTC_WDT_INT_RAW + WDT_INT_RAW RTC WDT interrupt raw 3 1 read-only - RTC_BROWN_OUT_INT_RAW + BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-only - RTC_MAIN_TIMER_INT_RAW + MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-only - RTC_SWD_INT_RAW + SWD_INT_RAW super watch dog interrupt raw 15 1 read-only - RTC_XTAL32K_DEAD_INT_RAW + XTAL32K_DEAD_INT_RAW xtal32k dead detection interrupt raw 16 1 read-only - RTC_GLITCH_DET_INT_RAW + GLITCH_DET_INT_RAW glitch_det_interrupt_raw 19 1 read-only - RTC_BBPLL_CAL_INT_RAW + BBPLL_CAL_INT_RAW bbpll cal end interrupt state 20 1 @@ -20094,49 +17952,49 @@ read-only - RTC_WDT_INT_ST + WDT_INT_ST RTC WDT interrupt state 3 1 read-only - RTC_BROWN_OUT_INT_ST + BROWN_OUT_INT_ST brown out interrupt state 9 1 read-only - RTC_MAIN_TIMER_INT_ST + MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-only - RTC_SWD_INT_ST + SWD_INT_ST super watch dog interrupt state 15 1 read-only - RTC_XTAL32K_DEAD_INT_ST + XTAL32K_DEAD_INT_ST xtal32k dead detection interrupt state 16 1 read-only - RTC_GLITCH_DET_INT_ST + GLITCH_DET_INT_ST glitch_det_interrupt state 19 1 read-only - RTC_BBPLL_CAL_INT_ST + BBPLL_CAL_INT_ST bbpll cal end interrupt state 20 1 @@ -20165,49 +18023,49 @@ write-only - RTC_WDT_INT_CLR + WDT_INT_CLR Clear RTC WDT interrupt state 3 1 write-only - RTC_BROWN_OUT_INT_CLR + BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 write-only - RTC_MAIN_TIMER_INT_CLR + MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 write-only - RTC_SWD_INT_CLR + SWD_INT_CLR Clear super watch dog interrupt state 15 1 write-only - RTC_XTAL32K_DEAD_INT_CLR + XTAL32K_DEAD_INT_CLR Clear RTC WDT interrupt state 16 1 write-only - RTC_GLITCH_DET_INT_CLR + GLITCH_DET_INT_CLR Clear glitch det interrupt state 19 1 write-only - RTC_BBPLL_CAL_INT_CLR + BBPLL_CAL_INT_CLR clear bbpll cal end interrupt state 20 1 @@ -20222,7 +18080,7 @@ 0x20 - RTC_SCRATCH0 + SCRATCH0 reserved register 0 32 @@ -20237,7 +18095,7 @@ 0x20 - RTC_SCRATCH1 + SCRATCH1 reserved register 0 32 @@ -20252,7 +18110,7 @@ 0x20 - RTC_SCRATCH2 + SCRATCH2 reserved register 0 32 @@ -20267,7 +18125,7 @@ 0x20 - RTC_SCRATCH3 + SCRATCH3 reserved register 0 32 @@ -20381,14 +18239,14 @@ read-write - RTC_WDT_STATE + WDT_STATE state of 32k_wdt 20 3 read-only - RTC_XTAL32K_GPIO_SEL + XTAL32K_GPIO_SEL XTAL_32K sel. 0: external XTAL_32K 23 1 @@ -20432,7 +18290,7 @@ 0x20 - RTC_SLEEP_REJECT_ENA + SLEEP_REJECT_ENA sleep reject enable 12 18 @@ -20461,14 +18319,14 @@ 0x20 - RTC_CPUSEL_CONF + CPUSEL_CONF CPU sel option 29 1 read-write - RTC_CPUPERIOD_SEL + CPUPERIOD_SEL CPU clk sel option 30 2 @@ -20626,21 +18484,21 @@ 0x00400000 - RTC_ANA_CLK_DIV_VLD + ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div 22 1 read-write - RTC_ANA_CLK_DIV + ANA_CLK_DIV the clk divider num of RTC_CLK 23 8 read-write - RTC_SLOW_CLK_NEXT_EDGE + SLOW_CLK_NEXT_EDGE flag rtc_slow_clk_next_edge 31 1 @@ -20917,7 +18775,7 @@ 0x20 - RTC_PAD_FORCE_HOLD + PAD_FORCE_HOLD rtc pad force hold 21 1 @@ -20989,14 +18847,14 @@ read-write - RTC_FASTMEM_FORCE_LPD + FASTMEM_FORCE_LPD fastmemory retention mode in sleep 15 1 read-write - RTC_FASTMEM_FORCE_LPU + FASTMEM_FORCE_LPU fastmemory donlt entry retention mode in sleep 16 1 @@ -21394,7 +19252,7 @@ 0x20 - RTC_WDT_FEED + WDT_FEED sw feed rtc wdt 31 1 @@ -21526,7 +19384,7 @@ 0x20 - RTC_SCRATCH4 + SCRATCH4 reserved register 0 32 @@ -21541,7 +19399,7 @@ 0x20 - RTC_SCRATCH5 + SCRATCH5 reserved register 0 32 @@ -21556,7 +19414,7 @@ 0x20 - RTC_SCRATCH6 + SCRATCH6 reserved register 0 32 @@ -21571,7 +19429,7 @@ 0x20 - RTC_SCRATCH7 + SCRATCH7 reserved register 0 32 @@ -21600,7 +19458,7 @@ read-only - RTC_PERI_ISO + PERI_ISO rtc peripheral iso 3 1 @@ -21642,140 +19500,140 @@ read-only - RTC_TOUCH_STATE_START + TOUCH_STATE_START touch should start to work 9 1 read-only - RTC_TOUCH_STATE_SWITCH + TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-only - RTC_TOUCH_STATE_SLP + TOUCH_STATE_SLP touch is in sleep state 11 1 read-only - RTC_TOUCH_STATE_DONE + TOUCH_STATE_DONE touch is done 12 1 read-only - RTC_COCPU_STATE_START + COCPU_STATE_START ulp/cocpu should start to work 13 1 read-only - RTC_COCPU_STATE_SWITCH + COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-only - RTC_COCPU_STATE_SLP + COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-only - RTC_COCPU_STATE_DONE + COCPU_STATE_DONE ulp/cocpu is done 16 1 read-only - RTC_MAIN_STATE_XTAL_ISO + MAIN_STATE_XTAL_ISO no use any more 17 1 read-only - RTC_MAIN_STATE_PLL_ON + MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-only - RTC_RDY_FOR_WAKEUP + RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-only - RTC_MAIN_STATE_WAIT_END + MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-only - RTC_IN_WAKEUP_STATE + IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-only - RTC_IN_LOW_POWER_STATE + IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-only - RTC_MAIN_STATE_IN_WAIT_8M + MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-only - RTC_MAIN_STATE_IN_WAIT_PLL + MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-only - RTC_MAIN_STATE_IN_WAIT_XTL + MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-only - RTC_MAIN_STATE_IN_SLP + MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-only - RTC_MAIN_STATE_IN_IDLE + MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-only - RTC_MAIN_STATE + MAIN_STATE rtc main state machine status 28 4 @@ -21790,7 +19648,7 @@ 0x20 - RTC_LOW_POWER_DIAG1 + LOW_POWER_DIAG1 0 32 read-only @@ -21804,42 +19662,42 @@ 0x20 - RTC_GPIO_PIN0_HOLD + GPIO_PIN0_HOLD the hold configure of rtc gpio0 0 1 read-write - RTC_GPIO_PIN1_HOLD + GPIO_PIN1_HOLD the hold configure of rtc gpio1 1 1 read-write - RTC_GPIO_PIN2_HOLD + GPIO_PIN2_HOLD the hold configure of rtc gpio2 2 1 read-write - RTC_GPIO_PIN3_HOLD + GPIO_PIN3_HOLD the hold configure of rtc gpio3 3 1 read-write - RTC_GPIO_PIN4_HOLD + GPIO_PIN4_HOLD the hold configure of rtc gpio4 4 1 read-write - RTC_GPIO_PIN5_HOLD + GPIO_PIN5_HOLD the hold configure of rtc gpio5 5 1 @@ -21870,63 +19728,63 @@ 0x43FF0010 - INT_WAIT + BROWN_OUT_INT_WAIT brown out interrupt wait cycles 4 10 read-write - CLOSE_FLASH_ENA + BROWN_OUT_CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write - PD_RF_ENA + BROWN_OUT_PD_RF_ENA enable power down RF when brown out happens 15 1 read-write - RST_WAIT + BROWN_OUT_RST_WAIT brown out reset wait cycles 16 10 read-write - RST_ENA + BROWN_OUT_RST_ENA enable brown out reset 26 1 read-write - RST_SEL + BROWN_OUT_RST_SEL 1: 4-pos reset 27 1 read-write - ANA_RST_EN + BROWN_OUT_ANA_RST_EN brown_out origin reset enable 28 1 read-write - CNT_CLR + BROWN_OUT_CNT_CLR clear brown out counter 29 1 write-only - ENA + BROWN_OUT_ENA enable brown out 30 1 @@ -21948,7 +19806,7 @@ 0x20 - RTC_TIMER_VALUE1_LOW + TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 @@ -21963,7 +19821,7 @@ 0x20 - RTC_TIMER_VALUE1_HIGH + TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 @@ -22120,49 +19978,49 @@ write-only - RTC_WDT_INT_ENA_W1TS + WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TS + BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TS + MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 write-only - RTC_SWD_INT_ENA_W1TS + SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TS + XTAL32K_DEAD_INT_ENA_W1TS enable xtal32k_dead interrupt 16 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TS + GLITCH_DET_INT_ENA_W1TS enbale gitch det interrupt 19 1 write-only - RTC_BBPLL_CAL_INT_ENA_W1TS + BBPLL_CAL_INT_ENA_W1TS enbale bbpll cal interrupt 20 1 @@ -22191,49 +20049,49 @@ write-only - RTC_WDT_INT_ENA_W1TC + WDT_INT_ENA_W1TC clear RTC WDT interrupt enable 3 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TC + BROWN_OUT_INT_ENA_W1TC clear brown out interrupt enable 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TC + MAIN_TIMER_INT_ENA_W1TC Clear RTC main timer interrupt enable 10 1 write-only - RTC_SWD_INT_ENA_W1TC + SWD_INT_ENA_W1TC clear super watch dog interrupt enable 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TC + XTAL32K_DEAD_INT_ENA_W1TC clear xtal32k_dead interrupt enable 16 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TC + GLITCH_DET_INT_ENA_W1TC clear gitch det interrupt enable 19 1 write-only - RTC_BBPLL_CAL_INT_ENA_W1TC + BBPLL_CAL_INT_ENA_W1TC clear bbpll cal interrupt enable 20 1 @@ -22293,7 +20151,7 @@ 0x00000007 - RTC_FIB_SEL + FIB_SEL select use analog fib signal 0 3 @@ -22308,105 +20166,105 @@ 0x20 - RTC_GPIO_WAKEUP_STATUS + GPIO_WAKEUP_STATUS rtc gpio wakeup flag 0 6 read-only - RTC_GPIO_WAKEUP_STATUS_CLR + GPIO_WAKEUP_STATUS_CLR clear rtc gpio wakeup flag 6 1 read-write - RTC_GPIO_PIN_CLK_GATE + GPIO_PIN_CLK_GATE enable rtc io clk gate 7 1 read-write - RTC_GPIO_PIN5_INT_TYPE + GPIO_PIN5_INT_TYPE configure gpio wakeup type 8 3 read-write - RTC_GPIO_PIN4_INT_TYPE + GPIO_PIN4_INT_TYPE configure gpio wakeup type 11 3 read-write - RTC_GPIO_PIN3_INT_TYPE + GPIO_PIN3_INT_TYPE configure gpio wakeup type 14 3 read-write - RTC_GPIO_PIN2_INT_TYPE + GPIO_PIN2_INT_TYPE configure gpio wakeup type 17 3 read-write - RTC_GPIO_PIN1_INT_TYPE + GPIO_PIN1_INT_TYPE configure gpio wakeup type 20 3 read-write - RTC_GPIO_PIN0_INT_TYPE + GPIO_PIN0_INT_TYPE configure gpio wakeup type 23 3 read-write - RTC_GPIO_PIN5_WAKEUP_ENABLE + GPIO_PIN5_WAKEUP_ENABLE enable wakeup from rtc gpio5 26 1 read-write - RTC_GPIO_PIN4_WAKEUP_ENABLE + GPIO_PIN4_WAKEUP_ENABLE enable wakeup from rtc gpio4 27 1 read-write - RTC_GPIO_PIN3_WAKEUP_ENABLE + GPIO_PIN3_WAKEUP_ENABLE enable wakeup from rtc gpio3 28 1 read-write - RTC_GPIO_PIN2_WAKEUP_ENABLE + GPIO_PIN2_WAKEUP_ENABLE enable wakeup from rtc gpio2 29 1 read-write - RTC_GPIO_PIN1_WAKEUP_ENABLE + GPIO_PIN1_WAKEUP_ENABLE enable wakeup from rtc gpio1 30 1 read-write - RTC_GPIO_PIN0_WAKEUP_ENABLE + GPIO_PIN0_WAKEUP_ENABLE enable wakeup from rtc gpio0 31 1 @@ -22421,49 +20279,49 @@ 0x20 - RTC_DEBUG_12M_NO_GATING + DEBUG_12M_NO_GATING use for debug 1 1 read-write - RTC_DEBUG_BIT_SEL + DEBUG_BIT_SEL use for debug 2 5 read-write - RTC_DEBUG_SEL0 + DEBUG_SEL0 use for debug 7 5 read-write - RTC_DEBUG_SEL1 + DEBUG_SEL1 use for debug 12 5 read-write - RTC_DEBUG_SEL2 + DEBUG_SEL2 use for debug 17 5 read-write - RTC_DEBUG_SEL3 + DEBUG_SEL3 use for debug 22 5 read-write - RTC_DEBUG_SEL4 + DEBUG_SEL4 use for debug 27 5 @@ -22478,84 +20336,84 @@ 0x20 - RTC_GPIO_PIN5_MUX_SEL + GPIO_PIN5_MUX_SEL use for debug 2 1 read-write - RTC_GPIO_PIN4_MUX_SEL + GPIO_PIN4_MUX_SEL use for debug 3 1 read-write - RTC_GPIO_PIN3_MUX_SEL + GPIO_PIN3_MUX_SEL use for debug 4 1 read-write - RTC_GPIO_PIN2_MUX_SEL + GPIO_PIN2_MUX_SEL use for debug 5 1 read-write - RTC_GPIO_PIN1_MUX_SEL + GPIO_PIN1_MUX_SEL use for debug 6 1 read-write - RTC_GPIO_PIN0_MUX_SEL + GPIO_PIN0_MUX_SEL use for debug 7 1 read-write - RTC_GPIO_PIN5_FUN_SEL + GPIO_PIN5_FUN_SEL use for debug 8 4 read-write - RTC_GPIO_PIN4_FUN_SEL + GPIO_PIN4_FUN_SEL use for debug 12 4 read-write - RTC_GPIO_PIN3_FUN_SEL + GPIO_PIN3_FUN_SEL use for debug 16 4 read-write - RTC_GPIO_PIN2_FUN_SEL + GPIO_PIN2_FUN_SEL use for debug 20 4 read-write - RTC_GPIO_PIN1_FUN_SEL + GPIO_PIN1_FUN_SEL use for debug 24 4 read-write - RTC_GPIO_PIN0_FUN_SEL + GPIO_PIN0_FUN_SEL use for debug 28 4 @@ -22651,7 +20509,7 @@ 0x02007270 - RTC_CNTL_DATE + DATE verision 0 28 @@ -22663,7 +20521,7 @@ SENSITIVE - Sensitive + SENSITIVE Peripheral SENSITIVE 0x600C1000 @@ -25870,7 +23728,7 @@ CLOCK_GATE - SENSITIVE_CLOCK_GATE_REG + SENSITIVE_CLOCK_GATE_REG_REG 0x170 0x20 0x00000001 @@ -25988,7 +23846,7 @@ Reserved. 1 31 - read-only + write-only @@ -26003,7 +23861,7 @@ Reserved. 1 31 - read-only + write-only @@ -26099,26 +23957,26 @@ - 64 - 0x1 + 8 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 SPI0 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 0 SPI0 0x60003000 @@ -26126,6 +23984,10 @@ 0x48 registers + + SPI_MEM_REJECT_CACHE + 40 + CTRL @@ -26753,7 +24615,7 @@ SPI1 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 1 SPI1 0x60002000 @@ -26761,6 +24623,10 @@ 0xA8 registers + + SPI1 + 18 + CMD @@ -27970,35 +25836,35 @@ The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. 0 1 - read-only + read-write PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. 1 1 - read-only + read-write WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 - read-only + read-write SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 - read-only + read-write MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 - read-only + read-write @@ -28081,7 +25947,7 @@ SPI2 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 2 SPI2 0x60024000 @@ -29816,7 +27682,7 @@ SYSTEM - System + System Configuration Registers SYSTEM 0x600C0000 @@ -30064,7 +27930,7 @@ read-write - CAN_CLK_EN + TWAI_CLK_EN reg_can_clk_en 19 1 @@ -30375,7 +28241,7 @@ read-write - CAN_RST + TWAI_RST reg_can_rst 19 1 @@ -30712,7 +28578,7 @@ EDMA_CTRL - edma clcok and reset register + EDMA clock and reset register 0x3C 0x20 0x00000001 @@ -31830,21 +29696,21 @@ interupt0 raw 0 1 - read-only + read-write TARGET1_INT_RAW interupt1 raw 1 1 - read-only + read-write TARGET2_INT_RAW interupt2 raw 2 1 - read-only + read-write @@ -31926,7 +29792,7 @@ TIMG0 - Timer Group + Timer Group 0 TIMG 0x6001F000 @@ -31951,49 +29817,49 @@ 0x60002000 - T0_USE_XTAL + USE_XTAL reg_t0_use_xtal. 9 1 read-write - T0_ALARM_EN + ALARM_EN reg_t0_alarm_en. 10 1 read-write - T0_DIVCNT_RST + DIVCNT_RST reg_t0_divcnt_rst. 12 1 write-only - T0_DIVIDER + DIVIDER reg_t0_divider. 13 16 read-write - T0_AUTORELOAD + AUTORELOAD reg_t0_autoreload. 29 1 read-write - T0_INCREASE + INCREASE reg_t0_increase. 30 1 read-write - T0_EN + EN reg_t0_en. 31 1 @@ -32008,7 +29874,7 @@ 0x20 - T0_LO + LO t0_lo 0 32 @@ -32023,7 +29889,7 @@ 0x20 - T0_HI + HI t0_hi 0 22 @@ -32038,7 +29904,7 @@ 0x20 - T0_UPDATE + UPDATE t0_update 31 1 @@ -32053,7 +29919,7 @@ 0x20 - T0_ALARM_LO + ALARM_LO reg_t0_alarm_lo. 0 32 @@ -32068,7 +29934,7 @@ 0x20 - T0_ALARM_HI + ALARM_HI reg_t0_alarm_hi. 0 22 @@ -32083,7 +29949,7 @@ 0x20 - T0_LOAD_LO + LOAD_LO reg_t0_load_lo. 0 32 @@ -32098,7 +29964,7 @@ 0x20 - T0_LOAD_HI + LOAD_HI reg_t0_load_hi. 0 22 @@ -32113,7 +29979,7 @@ 0x20 - T0_LOAD + LOAD t0_load 0 32 @@ -32566,7 +30432,7 @@ TIMG1 - Timer Group + Timer Group 1 0x60020000 TG1_T0_LEVEL @@ -32578,7 +30444,7 @@ - TWAI + TWAI0 Two-Wire Automotive Interface TWAI 0x6002B000 @@ -32588,7 +30454,7 @@ registers - TWAI + TWAI0 25 @@ -32867,13 +30733,15 @@ BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. 0 - 13 + 14 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 + read-write @@ -32888,18 +30756,21 @@ The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -32959,6 +30830,7 @@ Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -32973,6 +30845,7 @@ The RX error counter register, reflects value changes under reception status. 0 8 + read-write @@ -32987,6 +30860,7 @@ The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -32998,10 +30872,10 @@ TX_BYTE_0 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33013,10 +30887,10 @@ TX_BYTE_1 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33028,10 +30902,10 @@ TX_BYTE_2 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33043,10 +30917,10 @@ TX_BYTE_3 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33058,10 +30932,10 @@ TX_BYTE_4 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33073,10 +30947,10 @@ TX_BYTE_5 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33088,10 +30962,10 @@ TX_BYTE_6 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33103,10 +30977,10 @@ TX_BYTE_7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33118,10 +30992,10 @@ TX_BYTE_8 - Stored the 8th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33133,10 +31007,10 @@ TX_BYTE_9 - Stored the 9th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33148,10 +31022,10 @@ TX_BYTE_10 - Stored the 10th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33163,10 +31037,10 @@ TX_BYTE_11 - Stored the 11th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33178,10 +31052,10 @@ TX_BYTE_12 - Stored the 12th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33218,6 +31092,7 @@ This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 + read-write @@ -33225,7 +31100,7 @@ UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x60000000 @@ -33265,140 +31140,140 @@ This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 - read-only + read-write TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 - read-only + read-write PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 - read-only + read-write FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 - read-only + read-write RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 - read-only + read-write DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 - read-only + read-write CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 - read-only + read-write BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 - read-only + read-write RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 - read-only + read-write SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 - read-only + read-write SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 - read-only + read-write GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 - read-only + read-write TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. 12 1 - read-only + read-write TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 - read-only + read-write TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 - read-only + read-write RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 - read-only + read-write RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 - read-only + read-write RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 - read-only + read-write AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 - read-only + read-write WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 - read-only + read-write @@ -34811,7 +32686,7 @@ UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x60010000 UART1 @@ -34820,7 +32695,7 @@ UHCI0 - Universal Host Controller Interface + Universal Host Controller Interface 0 UHCI 0x60014000 @@ -34937,49 +32812,49 @@ a 0 1 - read-only + read-write TX_START_INT_RAW a 1 1 - read-only + read-write RX_HUNG_INT_RAW a 2 1 - read-only + read-write TX_HUNG_INT_RAW a 3 1 - read-only + read-write SEND_S_REG_Q_INT_RAW a 4 1 - read-only + read-write SEND_A_REG_Q_INT_RAW a 5 1 - read-only + read-write OUT_EOF_INT_RAW This is the interrupt raw bit. Triggered when there are some errors in EOF in the 6 1 - read-only + read-write APP_CTRL0_INT_RAW @@ -35868,7 +33743,7 @@ UHCI1 - Universal Host Controller Interface + Universal Host Controller Interface 1 0x6000C000 @@ -35882,7 +33757,7 @@ registers - USB_SERIAL_JTAG + USB_DEVICE 26 @@ -35943,84 +33818,84 @@ The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 - read-only + read-write SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 - read-only + read-write SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 - read-only + read-write SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 - read-only + read-write PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 - read-only + read-write CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 - read-only + read-write CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 - read-only + read-write STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 - read-only + read-write IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 - read-only + read-write USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 - read-only + read-write OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 - read-only + read-write OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 - read-only + read-write @@ -36798,12 +34673,12 @@ - 16 - 0x1 + 4 + 0x4 PLAIN_MEM[%s] The memory that stores plaintext 0x0 - 0x8 + 0x20 LINESIZE diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6-lp.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6-lp.svd new file mode 100644 index 000000000..32cf80ee2 --- /dev/null +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6-lp.svd @@ -0,0 +1,6367 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-C6-LP + ESP32 Series + 2 + 32-bit RISC-V MCU + Copyright 2024 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + RV32IMAC + r0p0 + little + false + false + 0 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + LP_I2C0 + Low-power I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x600B1800 + + 0x0 + 0x88 + registers + + + LP_I2C + 17 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 5 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 5 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 4 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 4 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 4 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND0_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + This is the content of command 1. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND1_DONE + When command 1 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + This is the content of command 2. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND2_DONE + When command 2 is done in I2C Master mode, this bit changes to high +Level. + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + This is the content of command 3. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND3_DONE + When command 3 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + This is the content of command 4. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND4_DONE + When command 4 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + This is the content of command 5. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND5_DONE + When command 5 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + This is the content of command 6. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND6_DONE + When command 6 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + This is the content of command 7. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND7_DONE + When command 7 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_PERI + LP_PERI Peripheral + LPPERI + 0x600B2800 + + 0x0 + 0x28 + registers + + + LP_PERI_TIMEOUT + 19 + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7F800000 + + + LP_TOUCH_CK_EN + need_des + 23 + 1 + read-write + + + RNG_CK_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_CK_EN + need_des + 25 + 1 + read-write + + + LP_UART_CK_EN + need_des + 26 + 1 + read-write + + + LP_IO_CK_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_CK_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_CK_EN + need_des + 29 + 1 + read-write + + + EFUSE_CK_EN + need_des + 30 + 1 + read-write + + + LP_CPU_CK_EN + need_des + 31 + 1 + read-write + + + + + RESET_EN + need_des + 0x4 + 0x20 + + + BUS_RESET_EN + need_des + 23 + 1 + write-only + + + LP_TOUCH_RESET_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_RESET_EN + need_des + 25 + 1 + read-write + + + LP_UART_RESET_EN + need_des + 26 + 1 + read-write + + + LP_IO_RESET_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_RESET_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_RESET_EN + need_des + 29 + 1 + read-write + + + EFUSE_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_RESET_EN + need_des + 31 + 1 + write-only + + + + + RNG_DATA + need_des + 0x8 + 0x20 + + + RND_DATA + need_des + 0 + 32 + read-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVALIABLE + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT + need_des + 0x10 + 0x20 + 0xBFFFC000 + + + LP_PERI_TIMEOUT_THRES + need_des + 14 + 16 + read-write + + + LP_PERI_TIMEOUT_INT_CLEAR + need_des + 30 + 1 + write-only + + + LP_PERI_TIMEOUT_PROTECT_EN + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT_ADDR + need_des + 0x14 + 0x20 + + + LP_PERI_TIMEOUT_ADDR + need_des + 0 + 32 + read-only + + + + + BUS_TIMEOUT_UID + need_des + 0x18 + 0x20 + + + LP_PERI_TIMEOUT_UID + need_des + 0 + 7 + read-only + + + + + MEM_CTRL + need_des + 0x1C + 0x20 + 0x80000000 + + + UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + UART_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + INTERRUPT_SOURCE + need_des + 0x20 + 0x20 + + + LP_INTERRUPT_SOURCE + BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int + 0 + 6 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206130 + + + LPPERI_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_ANA_PERI + LP_ANA_PERI Peripheral + LP_ANA + 0x600B2C00 + + 0x0 + 0x34 + registers + + + + BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + CK_GLITCH_CNTL + need_des + 0x8 + 0x20 + + + CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + FIB_ENABLE + need_des + 0xC + 0x20 + 0xFFFFFFFF + + + ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x10 + 0x20 + + + BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x14 + 0x20 + + + BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x18 + 0x20 + + + BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x1C + 0x20 + + + BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x20 + 0x20 + + + BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x24 + 0x20 + + + BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x28 + 0x20 + + + BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x2C + 0x20 + + + BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02202260 + + + LP_ANA_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON + LP_AON Peripheral + LP_AON + 0x600B1000 + + 0x0 + 0x5C + registers + + + + STORE0 + need_des + 0x0 + 0x20 + + + LP_AON_STORE0 + need_des + 0 + 32 + read-write + + + + + STORE1 + need_des + 0x4 + 0x20 + + + LP_AON_STORE1 + need_des + 0 + 32 + read-write + + + + + STORE2 + need_des + 0x8 + 0x20 + + + LP_AON_STORE2 + need_des + 0 + 32 + read-write + + + + + STORE3 + need_des + 0xC + 0x20 + + + LP_AON_STORE3 + need_des + 0 + 32 + read-write + + + + + STORE4 + need_des + 0x10 + 0x20 + + + LP_AON_STORE4 + need_des + 0 + 32 + read-write + + + + + STORE5 + need_des + 0x14 + 0x20 + + + LP_AON_STORE5 + need_des + 0 + 32 + read-write + + + + + STORE6 + need_des + 0x18 + 0x20 + + + LP_AON_STORE6 + need_des + 0 + 32 + read-write + + + + + STORE7 + need_des + 0x1C + 0x20 + + + LP_AON_STORE7 + need_des + 0 + 32 + read-write + + + + + STORE8 + need_des + 0x20 + 0x20 + + + LP_AON_STORE8 + need_des + 0 + 32 + read-write + + + + + STORE9 + need_des + 0x24 + 0x20 + + + LP_AON_STORE9 + need_des + 0 + 32 + read-write + + + + + GPIO_MUX + need_des + 0x28 + 0x20 + + + SEL + need_des + 0 + 8 + read-write + + + + + GPIO_HOLD0 + need_des + 0x2C + 0x20 + + + GPIO_HOLD0 + need_des + 0 + 32 + read-write + + + + + GPIO_HOLD1 + need_des + 0x30 + 0x20 + + + GPIO_HOLD1 + need_des + 0 + 32 + read-write + + + + + SYS_CFG + need_des + 0x34 + 0x20 + + + FORCE_DOWNLOAD_BOOT + need_des + 30 + 1 + read-write + + + HPSYS_SW_RESET + need_des + 31 + 1 + write-only + + + + + CPUCORE0_CFG + need_des + 0x38 + 0x20 + 0x40000000 + + + CPU_CORE0_SW_STALL + need_des + 0 + 8 + read-write + + + CPU_CORE0_SW_RESET + need_des + 28 + 1 + write-only + + + CPU_CORE0_OCD_HALT_ON_RESET + need_des + 29 + 1 + read-write + + + CPU_CORE0_STAT_VECTOR_SEL + need_des + 30 + 1 + read-write + + + CPU_CORE0_DRESET_MASK + need_des + 31 + 1 + read-write + + + + + IO_MUX + need_des + 0x3C + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + EXT_WAKEUP_CNTL + need_des + 0x40 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 8 + read-only + + + EXT_WAKEUP_STATUS_CLR + need_des + 14 + 1 + write-only + + + EXT_WAKEUP_SEL + need_des + 15 + 8 + read-write + + + EXT_WAKEUP_LV + need_des + 23 + 8 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + USB + need_des + 0x44 + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + LPBUS + need_des + 0x48 + 0x20 + 0xB0200000 + + + FAST_MEM_WPULSE + This field controls fast memory WPULSE parameter. + 16 + 3 + read-write + + + FAST_MEM_WA + This field controls fast memory WA parameter. + 19 + 3 + read-write + + + FAST_MEM_RA + This field controls fast memory RA parameter. + 22 + 2 + read-write + + + FAST_MEM_MUX_FSM_IDLE + need_des + 28 + 1 + read-only + + + FAST_MEM_MUX_SEL_STATUS + need_des + 29 + 1 + read-only + + + FAST_MEM_MUX_SEL_UPDATE + need_des + 30 + 1 + write-only + + + FAST_MEM_MUX_SEL + need_des + 31 + 1 + read-write + + + + + SDIO_ACTIVE + need_des + 0x4C + 0x20 + 0x02800000 + + + SDIO_ACT_DNUM + need_des + 22 + 10 + read-write + + + + + LPCORE + need_des + 0x50 + 0x20 + + + ETM_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + ETM_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + DISABLE + need_des + 31 + 1 + read-write + + + + + SAR_CCT + need_des + 0x54 + 0x20 + + + SAR2_PWDET_CCT + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02205280 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_APM + Low-power Access Permission Management Controller + LP_APM + 0x600B3800 + + 0x0 + 0x64 + registers + + + LP_APM_M0 + 20 + + + LP_APM_M1 + 21 + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 4 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000003 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + M1_PMS_FUNC_EN + PMS M1 function enable + 1 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xE8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xEC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_CLKRST + LP_CLKRST Peripheral + LP_CLKRST + 0x600B0400 + + 0x0 + 0x34 + registers + + + + LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + FAST_CLK_SEL + need_des + 2 + 1 + read-write + + + LP_PERI_DIV_NUM + need_des + 3 + 8 + read-write + + + + + LP_CLK_PO_EN + need_des + 0x4 + 0x20 + 0x000007FF + + + AON_SLOW_OEN + need_des + 0 + 1 + read-write + + + AON_FAST_OEN + need_des + 1 + 1 + read-write + + + SOSC_OEN + need_des + 2 + 1 + read-write + + + FOSC_OEN + need_des + 3 + 1 + read-write + + + OSC32K_OEN + need_des + 4 + 1 + read-write + + + XTAL32K_OEN + need_des + 5 + 1 + read-write + + + CORE_EFUSE_OEN + need_des + 6 + 1 + read-write + + + SLOW_OEN + need_des + 7 + 1 + read-write + + + FAST_OEN + need_des + 8 + 1 + read-write + + + RNG_OEN + need_des + 9 + 1 + read-write + + + LPBUS_OEN + need_des + 10 + 1 + read-write + + + + + LP_CLK_EN + need_des + 0x8 + 0x20 + + + FAST_ORI_GATE + need_des + 31 + 1 + read-write + + + + + LP_RST_EN + need_des + 0xC + 0x20 + + + AON_EFUSE_CORE_RESET_EN + need_des + 28 + 1 + read-write + + + LP_TIMER_RESET_EN + need_des + 29 + 1 + read-write + + + WDT_RESET_EN + need_des + 30 + 1 + read-write + + + ANA_PERI_RESET_EN + need_des + 31 + 1 + read-write + + + + + RESET_CAUSE + need_des + 0x10 + 0x20 + 0x00000020 + + + RESET_CAUSE + need_des + 0 + 5 + read-only + + + CORE0_RESET_FLAG + need_des + 5 + 1 + read-only + + + CORE0_RESET_CAUSE_CLR + need_des + 29 + 1 + write-only + + + CORE0_RESET_FLAG_SET + need_des + 30 + 1 + write-only + + + CORE0_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + CPU_RESET + need_des + 0x14 + 0x20 + 0x04400000 + + + RTC_WDT_CPU_RESET_LENGTH + need_des + 22 + 3 + read-write + + + RTC_WDT_CPU_RESET_EN + need_des + 25 + 1 + read-write + + + CPU_STALL_WAIT + need_des + 26 + 5 + read-write + + + CPU_STALL_EN + need_des + 31 + 1 + read-write + + + + + FOSC_CNTL + need_des + 0x18 + 0x20 + 0x2B000000 + + + FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + RC32K_CNTL + need_des + 0x1C + 0x20 + 0x2B000000 + + + RC32K_DFREQ + need_des + 22 + 10 + read-write + + + + + CLK_TO_HP + need_des + 0x20 + 0x20 + 0xF0000000 + + + ICG_HP_XTAL32K + need_des + 28 + 1 + read-write + + + ICG_HP_SOSC + need_des + 29 + 1 + read-write + + + ICG_HP_OSC32K + need_des + 30 + 1 + read-write + + + ICG_HP_FOSC + need_des + 31 + 1 + read-write + + + + + LPMEM_FORCE + need_des + 0x24 + 0x20 + + + LPMEM_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LPPERI + need_des + 0x28 + 0x20 + + + LP_I2C_CLK_SEL + need_des + 30 + 1 + read-write + + + LP_UART_CLK_SEL + need_des + 31 + 1 + read-write + + + + + XTAL32K + need_des + 0x2C + 0x20 + 0x66C00000 + + + DRES_XTAL32K + need_des + 22 + 3 + read-write + + + DGM_XTAL32K + need_des + 25 + 3 + read-write + + + DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206090 + + + CLKRST_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + LP_I2C_ANA_MST + 0x600B2400 + + 0x0 + 0x1C + registers + + + + I2C0_CTRL + need_des + 0x0 + 0x20 + + + LP_I2C_ANA_MAST_I2C0_CTRL + need_des + 0 + 25 + read-write + + + LP_I2C_ANA_MAST_I2C0_BUSY + need_des + 25 + 1 + read-only + + + + + I2C0_CONF + need_des + 0x4 + 0x20 + 0x07000000 + + + LP_I2C_ANA_MAST_I2C0_CONF + need_des + 0 + 24 + read-write + + + LP_I2C_ANA_MAST_I2C0_STATUS + reserved + 24 + 8 + read-only + + + + + I2C0_DATA + need_des + 0x8 + 0x20 + 0x00000900 + + + LP_I2C_ANA_MAST_I2C0_RDATA + need_des + 0 + 8 + read-only + + + LP_I2C_ANA_MAST_I2C0_CLK_SEL + need_des + 8 + 3 + read-write + + + LP_I2C_ANA_MAST_I2C_MST_SEL + need des + 11 + 1 + read-write + + + + + ANA_CONF1 + need_des + 0xC + 0x20 + + + LP_I2C_ANA_MAST_ANA_CONF1 + need_des + 0 + 24 + read-write + + + + + NOUSE + need_des + 0x10 + 0x20 + + + LP_I2C_ANA_MAST_I2C_MST_NOUSE + need_des + 0 + 32 + read-write + + + + + DEVICE_EN + need_des + 0x14 + 0x20 + + + LP_I2C_ANA_MAST_I2C_DEVICE_EN + need_des + 0 + 12 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02007301 + + + LP_I2C_ANA_MAST_I2C_MAT_DATE + need_des + 0 + 28 + read-write + + + LP_I2C_ANA_MAST_I2C_MAT_CLK_EN + need_des + 28 + 1 + read-write + + + + + + + LP_IO + LP_IO Peripheral + LP_IO + 0x600B2000 + + 0x0 + 0x7C + registers + + + + OUT + need des + 0x0 + 0x20 + + + OUT_DATA + set lp gpio output data + 0 + 8 + read-write + + + + + OUT_W1TS + need des + 0x4 + 0x20 + + + OUT_DATA_W1TS + set one time output data + 0 + 8 + write-only + + + + + OUT_W1TC + need des + 0x8 + 0x20 + + + OUT_DATA_W1TC + clear one time output data + 0 + 8 + write-only + + + + + ENABLE + need des + 0xC + 0x20 + + + ENABLE + set lp gpio output data + 0 + 8 + read-write + + + + + ENABLE_W1TS + need des + 0x10 + 0x20 + + + ENABLE_W1TS + set one time output data + 0 + 8 + write-only + + + + + ENABLE_W1TC + need des + 0x14 + 0x20 + + + ENABLE_W1TC + clear one time output data + 0 + 8 + write-only + + + + + STATUS + need des + 0x18 + 0x20 + + + INTERRUPT + set lp gpio output data + 0 + 8 + read-write + + + + + STATUS_W1TS + need des + 0x1C + 0x20 + + + STATUS_W1TS + set one time output data + 0 + 8 + write-only + + + + + STATUS_W1TC + need des + 0x20 + 0x20 + + + STATUS_W1TC + clear one time output data + 0 + 8 + write-only + + + + + IN + need des + 0x24 + 0x20 + + + DATA_NEXT + need des + 0 + 8 + read-only + + + + + 8 + 0x4 + 0-7 + PIN%s + need des + 0x28 + 0x20 + + + SYNC_BYPASS + need des + 0 + 2 + read-write + + + PAD_DRIVER + need des + 2 + 1 + read-write + + + EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + INT_TYPE + need des + 7 + 3 + read-write + + + WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + FILTER_EN + need des + 11 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + GPIO%s + need des + 0x48 + 0x20 + + + MCU_OE + need des + 0 + 1 + read-write + + + SLP_SEL + need des + 1 + 1 + read-write + + + MCU_WPD + need des + 2 + 1 + read-write + + + MCU_WPU + need des + 3 + 1 + read-write + + + MCU_IE + need des + 4 + 1 + read-write + + + MCU_DRV + need des + 5 + 2 + read-write + + + FUN_WPD + need des + 7 + 1 + read-write + + + FUN_WPU + need des + 8 + 1 + read-write + + + FUN_IE + need des + 9 + 1 + read-write + + + FUN_DRV + need des + 10 + 2 + read-write + + + FUN_SEL + need des + 12 + 3 + read-write + + + + + STATUS_INT + need des + 0x68 + 0x20 + + + NEXT + need des + 0 + 8 + read-only + + + + + DATE + need des + 0x3FC + 0x20 + 0x02202100 + + + LP_IO_DATE + need des + 0 + 31 + read-write + + + CLK_EN + need des + 31 + 1 + read-write + + + + + + + LP_TEE + Low-power Trusted Execution Environment + LP_TEE + 0x600B3400 + + 0x0 + 0x10 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + 0x00000003 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x4 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + FORCE_ACC_HP + need_des + 0x90 + 0x20 + + + LP_AON_FORCE_ACC_HPMEM_EN + need_des + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205270 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + LP_TIMER + Low-power Timer + LP_TIMER + 0x600B0C00 + + 0x0 + 0x4C + registers + + + LP_TIMER + 7 + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_UART + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART + 0x600B1400 + + 0x0 + 0x84 + registers + + + LP_UART + 16 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + Configuration register 0 + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit to reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02201260 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + LP_WDT + Low-power Watchdog Timer + LP_WDT + 0x600B1C00 + + 0x0 + 0x38 + registers + + + LP_WDT + 18 + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + FEED + need_des + 0x14 + 0x20 + + + RTC_WDT_FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-write + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + \ No newline at end of file diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6.svd index 7694ae15d..1f79f8844 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32c6.svd @@ -4,10 +4,9 @@ ESPRESSIF ESP32-C6 ESP32 C-Series - 5 + 11 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 - - Copyright 2023 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. RV32IMAC r0p0 little false false - 4 + 0 false 32 @@ -351,36 +349,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -1555,7 +1553,7 @@ - C0RE_0_INTR_ENA + CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 @@ -1739,90 +1737,90 @@ - CORE_0_INTR_RLS + CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS + CORE_0_AREA_DRAM0_0_RD_INTR_ENA Core0 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_RLS + CORE_0_AREA_DRAM0_0_WR_INTR_ENA Core0 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_0_AREA_DRAM0_1_RD_RLS + CORE_0_AREA_DRAM0_1_RD_INTR_ENA Core0 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_0_AREA_DRAM0_1_WR_RLS + CORE_0_AREA_DRAM0_1_WR_INTR_ENA Core0 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_0_AREA_PIF_0_RD_RLS + CORE_0_AREA_PIF_0_RD_INTR_ENA Core0 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_0_AREA_PIF_0_WR_RLS + CORE_0_AREA_PIF_0_WR_INTR_ENA Core0 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_0_AREA_PIF_1_RD_RLS + CORE_0_AREA_PIF_1_RD_INTR_ENA Core0 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_0_AREA_PIF_1_WR_RLS + CORE_0_AREA_PIF_1_WR_INTR_ENA Core0 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_0_SP_SPILL_MIN_RLS + CORE_0_SP_SPILL_MIN_INTR_ENA Core0 stackpoint underflow monitor interrupt enable 8 1 read-write - CORE_0_SP_SPILL_MAX_RLS + CORE_0_SP_SPILL_MAX_INTR_ENA Core0 stackpoint overflow monitor interrupt enable 9 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -3792,60 +3790,60 @@ - 512 - 0x1 + 128 + 0x4 Y_MEM[%s] memory that stores Y 0x0 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 M_MEM[%s] memory that stores M 0x200 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 RB_MEM[%s] memory that stores Rb 0x400 - 0x8 + 0x20 - 48 - 0x1 + 12 + 0x4 BOX_MEM[%s] memory that stores BOX 0x600 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] memory that stores IV 0x630 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 X_MEM[%s] memory that stores X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] memory that stores Z 0xA00 - 0x8 + 0x20 SET_START @@ -4119,28 +4117,28 @@ - 32 - 0x1 + 8 + 0x4 K_MEM[%s] The memory that stores k. 0x100 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 PX_MEM[%s] The memory that stores Px. 0x120 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 PY_MEM[%s] The memory that stores Py. 0x140 - 0x8 + 0x20 @@ -4816,17 +4814,59 @@ 0x20 - MAC_SPI_RESERVED - Reserved. + ACTIVE_HP_DBIAS + Stores the active hp dbias. 0 - 14 + 5 + read-only + + + ACTIVE_LP_DBIAS + Stores the active lp dbias. + 5 + 5 + read-only + + + LSLP_HP_DBG + Stores the lslp hp dbg. + 10 + 2 + read-only + + + LSLP_HP_DBIAS + Stores the lslp hp dbias. + 12 + 4 + read-only + + + DSLP_LP_DBG + Stores the dslp lp dbg. + 16 + 3 + read-only + + + DSLP_LP_DBIAS + Stores the dslp lp dbias. + 19 + 4 + read-only + + + DBIAS_VOL_GAP + Stores the hp and lp dbias vol gap. + 23 + 5 read-only SPI_PAD_CONF_1 - Stores the first part of SPI_PAD_CONF. - 14 - 18 + Reserved. + 28 + 4 read-only @@ -14168,7 +14208,7 @@ GPIO_SD Sigma-Delta Modulation GPIOSD - 0x60004F00 + 0x60091F00 0x0 0x7C @@ -15702,7 +15742,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 @@ -15726,20 +15766,20 @@ - 64 - 0x1 + 16 + 0x4 WR_MESSAGE_MEM[%s] Message block memory. 0x80 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 RD_RESULT_MEM[%s] Result from upstream. 0xC0 - 0x8 + 0x20 SET_MESSAGE_PAD @@ -19754,7 +19794,7 @@ level. registers - I2S1 + I2S0 41 @@ -21041,382 +21081,372 @@ level. - INTERRUPT_CORE0 - Interrupt Controller (Core 0) - INTMTX_CORE0 - 0x60010000 + IEEE802154 + IEEE802154 Peripheral + IEEE802154 + 0x600A3000 0x0 - 0x148 + 0x174 registers - - WIFI_MAC - 0 - - - WIFI_MAC_NMI - 1 - - - WIFI_PWR - 2 - - - WIFI_BB - 3 - - - BT_MAC - 4 - - - BT_BB - 5 - - - BT_BB_NMI - 6 - - - LP_TIMER - 7 - - - COEX - 8 - - - BLE_TIMER - 9 - - - BLE_SEC - 10 - - - ZB_MAC - 12 - - - FROM_CPU_INTR0 - 22 - - - FROM_CPU_INTR1 - 23 - - - FROM_CPU_INTR2 - 24 - - - FROM_CPU_INTR3 - 25 - - - CACHE - 28 - - - CPU_PERI_TIMEOUT - 29 - - WIFI_MAC_INTR_MAP - register description + COMMAND 0x0 0x20 - WIFI_MAC_INTR_MAP - Need add description + OPCODE 0 - 5 + 8 read-write - WIFI_MAC_NMI_MAP - register description + CTRL_CFG 0x4 0x20 - WIFI_MAC_NMI_MAP - Need add description + HW_AUTO_ACK_TX_EN 0 + 1 + read-write + + + HW_ENHANCE_ACK_TX_EN + 1 + 1 + read-write + + + HW_AUTO_ACK_RX_EN + 3 + 1 + read-write + + + DIS_IFS_CONTROL + 5 + 1 + read-write + + + PAN_COORDINATOR + 6 + 1 + read-write + + + PROMISCUOUS_MODE + 7 + 1 + read-write + + + DIS_FRAME_VERSION_RSV_FILTER + 11 + 1 + read-write + + + AUTOPEND_ENHANCE + 12 + 1 + read-write + + + FILTER_ENHANCE + 14 + 1 + read-write + + + COEX_ARB_DELAY + 16 5 read-write + + BIT_ORDER + 24 + 1 + read-write + + + NO_RSS_TRK_ENB + 25 + 1 + read-write + + + FORCE_RX_ENB + 26 + 1 + read-write + + + RX_DONE_TRIGGER_IDLE + 27 + 1 + read-write + + + MAC_INF0_ENABLE + 28 + 1 + read-write + + + MAC_INF1_ENABLE + 29 + 1 + read-write + + + MAC_INF2_ENABLE + 30 + 1 + read-write + + + MAC_INF3_ENABLE + 31 + 1 + read-write + - WIFI_PWR_INTR_MAP - register description + INF0_SHORT_ADDR 0x8 0x20 - WIFI_PWR_INTR_MAP - Need add description + MAC_INF0_SHORT_ADDR 0 - 5 + 16 read-write - WIFI_BB_INTR_MAP - register description + INF0_PAN_ID 0xC 0x20 - WIFI_BB_INTR_MAP - Need add description + MAC_INF0_PAN_ID 0 - 5 + 16 read-write - BT_MAC_INTR_MAP - register description + INF0_EXTEND_ADDR0 0x10 0x20 - BT_MAC_INTR_MAP - Need add description + MAC_INF0_EXTEND_ADDR0 0 - 5 + 32 read-write - BT_BB_INTR_MAP - register description + INF0_EXTEND_ADDR1 0x14 0x20 - BT_BB_INTR_MAP - Need add description + MAC_INF0_EXTEND_ADDR1 0 - 5 + 32 read-write - BT_BB_NMI_MAP - register description + INF1_SHORT_ADDR 0x18 0x20 - BT_BB_NMI_MAP - Need add description + MAC_INF1_SHORT_ADDR 0 - 5 + 16 read-write - LP_TIMER_INTR_MAP - register description + INF1_PAN_ID 0x1C 0x20 - LP_TIMER_INTR_MAP - Need add description + MAC_INF1_PAN_ID 0 - 5 + 16 read-write - COEX_INTR_MAP - register description + INF1_EXTEND_ADDR0 0x20 0x20 - COEX_INTR_MAP - Need add description + MAC_INF1_EXTEND_ADDR0 0 - 5 + 32 read-write - BLE_TIMER_INTR_MAP - register description + INF1_EXTEND_ADDR1 0x24 0x20 - BLE_TIMER_INTR_MAP - Need add description + MAC_INF1_EXTEND_ADDR1 0 - 5 + 32 read-write - BLE_SEC_INTR_MAP - register description + INF2_SHORT_ADDR 0x28 0x20 - BLE_SEC_INTR_MAP - Need add description + MAC_INF2_SHORT_ADDR 0 - 5 + 16 read-write - I2C_MST_INTR_MAP - register description + INF2_PAN_ID 0x2C 0x20 - I2C_MST_INTR_MAP - Need add description + MAC_INF2_PAN_ID 0 - 5 + 16 read-write - ZB_MAC_INTR_MAP - register description + INF2_EXTEND_ADDR0 0x30 0x20 - ZB_MAC_INTR_MAP - Need add description + MAC_INF2_EXTEND_ADDR0 0 - 5 + 32 read-write - PMU_INTR_MAP - register description + INF2_EXTEND_ADDR1 0x34 0x20 - PMU_INTR_MAP - Need add description + MAC_INF2_EXTEND_ADDR1 0 - 5 + 32 read-write - EFUSE_INTR_MAP - register description + INF3_SHORT_ADDR 0x38 0x20 - EFUSE_INTR_MAP - Need add description + MAC_INF3_SHORT_ADDR 0 - 5 + 16 read-write - LP_RTC_TIMER_INTR_MAP - register description + INF3_PAN_ID 0x3C 0x20 - LP_RTC_TIMER_INTR_MAP - Need add description + MAC_INF3_PAN_ID 0 - 5 + 16 read-write - LP_UART_INTR_MAP - register description + INF3_EXTEND_ADDR0 0x40 0x20 - LP_UART_INTR_MAP - Need add description + MAC_INF3_EXTEND_ADDR0 0 - 5 + 32 read-write - LP_I2C_INTR_MAP - register description + INF3_EXTEND_ADDR1 0x44 0x20 - LP_I2C_INTR_MAP - Need add description + MAC_INF3_EXTEND_ADDR1 0 - 5 + 32 read-write - LP_WDT_INTR_MAP - register description + CHANNEL 0x48 0x20 - LP_WDT_INTR_MAP - Need add description + HOP 0 - 5 + 7 read-write - LP_PERI_TIMEOUT_INTR_MAP - register description + TX_POWER 0x4C 0x20 - LP_PERI_TIMEOUT_INTR_MAP - Need add description + TX_POWER 0 5 read-write @@ -21424,217 +21454,1905 @@ level. - LP_APM_M0_INTR_MAP - register description + ED_SCAN_DURATION 0x50 0x20 - LP_APM_M0_INTR_MAP - Need add description + ED_SCAN_DURATION 0 - 5 + 24 + read-write + + + ED_SCAN_WAIT_DLY + 24 + 4 read-write - LP_APM_M1_INTR_MAP - register description + ED_SCAN_CFG 0x54 0x20 - LP_APM_M1_INTR_MAP - Need add description + CCA_ED_THRESHOLD 0 - 5 + 8 + read-write + + + ED_SAMPLE_MODE + 11 + 2 + read-write + + + DIS_ED_POWER_SEL + 13 + 1 + read-write + + + CCA_MODE + 14 + 2 + read-write + + + ED_RSS + 16 + 8 + read-write + + + CCA_BUSY + 24 + 1 read-write - CPU_INTR_FROM_CPU_0_MAP - register description + IFS 0x58 0x20 - CPU_INTR_FROM_CPU_0_MAP - Need add description + SIFS 0 - 5 + 8 + read-write + + + LIFS + 16 + 10 read-write - CPU_INTR_FROM_CPU_1_MAP - register description + ACK_TIMEOUT 0x5C 0x20 - CPU_INTR_FROM_CPU_1_MAP - Need add description + ACK_TIMEOUT 0 - 5 + 16 read-write - CPU_INTR_FROM_CPU_2_MAP - register description + EVENT_EN 0x60 0x20 - CPU_INTR_FROM_CPU_2_MAP - Need add description + EVENT_EN 0 - 5 + 13 read-write - CPU_INTR_FROM_CPU_3_MAP - register description + EVENT_STATUS 0x64 0x20 - CPU_INTR_FROM_CPU_3_MAP - Need add description + EVENT_STATUS 0 - 5 + 13 read-write - ASSIST_DEBUG_INTR_MAP - register description + RX_ABORT_INTR_CTRL 0x68 0x20 - ASSIST_DEBUG_INTR_MAP - Need add description + RX_ABORT_INTR_CTRL 0 - 5 + 31 read-write - TRACE_INTR_MAP - register description + ACK_FRAME_PENDING_EN 0x6C 0x20 - TRACE_INTR_MAP - Need add description + ACK_FRAME_PENDING_EN 0 - 5 + 1 + read-write + + + ACK_TX_ACK_TIMEOUT + 16 + 16 read-write - CACHE_INTR_MAP - register description + COEX_PTI 0x70 0x20 - CACHE_INTR_MAP - Need add description + COEX_PTI 0 - 5 + 4 + read-write + + + COEX_ACK_PTI + 4 + 4 + read-write + + + CLOSE_RF_SEL + 8 + 1 read-write - CPU_PERI_TIMEOUT_INTR_MAP - register description + CORE_DUMMY_DATA 0x74 0x20 - CPU_PERI_TIMEOUT_INTR_MAP - Need add description + CORE_DUMMY_DATA 0 - 5 + 32 read-write - GPIO_INTERRUPT_PRO_MAP - register description + TX_ABORT_INTERRUPT_CONTROL 0x78 0x20 - GPIO_INTERRUPT_PRO_MAP - Need add description + TX_ABORT_INTERRUPT_CONTROL 0 - 5 + 31 read-write - GPIO_INTERRUPT_PRO_NMI_MAP - register description + ENHANCE_ACK_CFG 0x7C 0x20 - GPIO_INTERRUPT_PRO_NMI_MAP - Need add description + TX_ENH_ACK_GENERATE_DONE_NOTIFY 0 - 5 + 32 read-write - PAU_INTR_MAP - register description + RX_STATUS 0x80 0x20 - PAU_INTR_MAP - Need add description + FILTER_FAIL_STATUS 0 - 5 + 4 read-write - - - - HP_PERI_TIMEOUT_INTR_MAP - register description - 0x84 - 0x20 - - HP_PERI_TIMEOUT_INTR_MAP - Need add description - 0 + RX_ABORT_STATUS + 4 5 read-write - - - - MODEM_PERI_TIMEOUT_INTR_MAP + + RX_STATE + 16 + 3 + read-write + + + PREAMBLE_MATCH + 20 + 1 + read-write + + + SFD_MATCH + 21 + 1 + read-write + + + + + TX_STATUS + 0x84 + 0x20 + + + TX_STATE + 0 + 4 + read-write + + + TX_ABORT_STATUS + 4 + 5 + read-write + + + TX_SEC_ERROR_CODE + 16 + 4 + read-write + + + + + TXRX_STATUS + 0x88 + 0x20 + + + TXRX_STATE + 0 + 4 + read-write + + + TX_PROC + 8 + 1 + read-write + + + RX_PROC + 9 + 1 + read-write + + + ED_PROC + 10 + 1 + read-write + + + ED_TRIGGER_TX_PROC + 11 + 1 + read-write + + + RF_CTRL_STATE + 16 + 4 + read-write + + + + + TX_CCM_SCHEDULE_STATUS + 0x8C + 0x20 + + + TX_CCM_SCHEDULE_STATUS + 0 + 31 + read-write + + + + + CORE_GCK_CFG + 0x90 + 0x20 + + + DIS_PKT_GCK + 0 + 1 + read-write + + + DIS_CTRL_GCK + 1 + 1 + read-write + + + + + TEST_CONTROL + 0x94 + 0x20 + + + WRONG_CRC + 0 + 1 + read-write + + + + + DTM_CONFIG + 0x98 + 0x20 + + + DTMCH_TX_LENGTH + 0 + 8 + read-write + + + DTM_TX_PLD_TYPE + 8 + 4 + read-write + + + DTM_HOP_FREQ + 16 + 6 + read-write + + + DTM_CONTRX_EN + 24 + 1 + read-write + + + DTM_ON + 25 + 1 + read-write + + + + + DTM_TX_PKT_CONFIG + 0x9C + 0x20 + + + DTM_TX_PKT_THRESHOLD + 0 + 16 + read-write + + + + + DTM_PKT_COUNTER + 0xA0 + 0x20 + + + DTM_TXRX_PKT_COUNT + 0 + 16 + read-write + + + DTM_CRC_ERR_PKT_COUNT + 16 + 16 + read-write + + + + + RX_LENGTH + 0xA4 + 0x20 + + + RX_LENGTH + 0 + 7 + read-write + + + + + TIME0_THRESHOLD + 0xA8 + 0x20 + + + TIMER0_THRESHOLD + 0 + 32 + read-write + + + + + TIME0_VALUE + 0xAC + 0x20 + + + TIMER0_VALUE + 0 + 32 + read-write + + + + + TIME1_THRESHOLD + 0xB0 + 0x20 + + + TIMER1_THRESHOLD + 0 + 32 + read-write + + + + + TIME1_VALUE + 0xB4 + 0x20 + + + TIMER1_VALUE + 0 + 32 + read-write + + + + + CLK_COUNTER_MATCH_VAL + 0xB8 + 0x20 + + + CLK_COUNT_MATCH_VAL + 0 + 16 + read-write + + + + + CLK_COUNTER + 0xBC + 0x20 + + + CLK_625US_CNT + 0 + 16 + read-write + + + + + IFS_COUNTER + 0xC0 + 0x20 + + + IFS_COUNTER + 0 + 10 + read-write + + + EN + 16 + 1 + read-write + + + + + SFD_WAIT_SYMBOL + 0xC4 + 0x20 + + + NUM + 0 + 4 + read-write + + + + + TXRX_PATH_DELAY + 0xC8 + 0x20 + + + TX_PATH_DELAY + 0 + 6 + read-write + + + RX_PATH_DELAY + 16 + 6 + read-write + + + + + BB_CLK + 0xCC + 0x20 + + + FREQ_MINUS_1 + 0 + 5 + read-write + + + + + TXDMA_ADDR + 0xD0 + 0x20 + + + TXDMA_ADDR + 0 + 32 + read-write + + + + + TXDMA_CTRL_STATE + 0xD4 + 0x20 + + + TXDMA_WATER_LEVEL + 0 + 3 + read-write + + + TXDMA_FILL_ENTRY + 4 + 3 + read-write + + + TXDMA_STATE + 16 + 5 + read-write + + + TXDMA_FETCH_BYTE_CNT + 24 + 7 + read-write + + + + + TXDMA_ERR + 0xD8 + 0x20 + + + TXDMA_ERR + 0 + 4 + read-write + + + + + RXDMA_ADDR + 0xE0 + 0x20 + + + RXDMA_ADDR + 0 + 32 + read-write + + + + + RXDMA_CTRL_STATE + 0xE4 + 0x20 + + + RXDMA_WATER_LEVEL + 0 + 3 + read-write + + + RXDMA_STATE + 16 + 5 + read-write + + + RXDMA_APPEND_LQI_OFFSET + 24 + 1 + read-write + + + RXDMA_APPEND_FREQ_OFFSET + 25 + 1 + read-write + + + + + RXDMA_ERR + 0xE8 + 0x20 + + + RXDMA_ERR + 0 + 4 + read-write + + + + + DMA_GCK_CFG + 0xF0 + 0x20 + + + DMA_GCK_CFG + 0 + 1 + read-write + + + + + DMA_DUMMY + 0xF4 + 0x20 + + + DATA + 0 + 32 + read-write + + + + + PAON_DELAY + 0x100 + 0x20 + + + PAON_DELAY + 0 + 10 + read-write + + + + + TXON_DELAY + 0x104 + 0x20 + + + TXON_DELAY + 0 + 10 + read-write + + + + + TXEN_STOP_DELAY + 0x108 + 0x20 + + + TXEN_STOP_DLY + 0 + 6 + read-write + + + + + TXOFF_DELAY + 0x10C + 0x20 + + + TXOFF_DELAY + 0 + 6 + read-write + + + + + RXON_DELAY + 0x110 + 0x20 + + + RXON_DELAY + 0 + 11 + read-write + + + + + TXRX_SWITCH_DELAY + 0x114 + 0x20 + + + TXRX_SWITCH_DELAY + 0 + 10 + read-write + + + + + CONT_RX_DELAY + 0x118 + 0x20 + + + CONT_RX_DELAY + 0 + 6 + read-write + + + + + DCDC_CTRL + 0x11C + 0x20 + + + DCDC_PRE_UP_DELAY + 0 + 8 + read-write + + + DCDC_DOWN_DELAY + 8 + 8 + read-write + + + EN + 16 + 1 + read-write + + + TX_DCDC_UP + 31 + 1 + read-write + + + + + DEBUG_CTRL + 0x120 + 0x20 + + + DEBUG_SIGNAL_SEL + 0 + 3 + read-write + + + DEBUG_TRIGGER_STATE_SELECT + 8 + 4 + read-write + + + DEBUG_SER_DEBUG_SEL + 12 + 4 + read-write + + + DEBUG_TRIGGER_STATE_MATCH_VALUE + 16 + 5 + read-write + + + DEBUG_TRIGGER_PULSE_SELECT + 24 + 3 + read-write + + + DEBUG_STATE_MATCH_DUMP_EN + 30 + 1 + read-write + + + DEBUG_TRIGGER_DUMP_EN + 31 + 1 + read-write + + + + + SEC_CTRL + 0x128 + 0x20 + + + SEC_EN + 0 + 1 + read-write + + + SEC_PAYLOAD_OFFSET + 8 + 7 + read-write + + + + + SEC_EXTEND_ADDRESS0 + 0x12C + 0x20 + + + SEC_EXTEND_ADDRESS0 + 0 + 32 + read-write + + + + + SEC_EXTEND_ADDRESS1 + 0x130 + 0x20 + + + SEC_EXTEND_ADDRESS1 + 0 + 32 + read-write + + + + + SEC_KEY0 + 0x134 + 0x20 + + + SEC_KEY0 + 0 + 32 + read-write + + + + + SEC_KEY1 + 0x138 + 0x20 + + + SEC_KEY1 + 0 + 32 + read-write + + + + + SEC_KEY2 + 0x13C + 0x20 + + + SEC_KEY2 + 0 + 32 + read-write + + + + + SEC_KEY3 + 0x140 + 0x20 + + + SEC_KEY3 + 0 + 32 + read-write + + + + + SFD_TIMEOUT_CNT + 0x144 + 0x20 + + + SFD_TIMEOUT_CNT + 0 + 16 + read-write + + + + + CRC_ERROR_CNT + 0x148 + 0x20 + + + CRC_ERROR_CNT + 0 + 16 + read-write + + + + + ED_ABORT_CNT + 0x14C + 0x20 + + + ED_ABORT_CNT + 0 + 16 + read-write + + + + + CCA_FAIL_CNT + 0x150 + 0x20 + + + CCA_FAIL_CNT + 0 + 16 + read-write + + + + + RX_FILTER_FAIL_CNT + 0x154 + 0x20 + + + RX_FILTER_FAIL_CNT + 0 + 16 + read-write + + + + + NO_RSS_DETECT_CNT + 0x158 + 0x20 + + + NO_RSS_DETECT_CNT + 0 + 16 + read-write + + + + + RX_ABORT_COEX_CNT + 0x15C + 0x20 + + + RX_ABORT_COEX_CNT + 0 + 16 + read-write + + + + + RX_RESTART_CNT + 0x160 + 0x20 + + + RX_RESTART_CNT + 0 + 16 + read-write + + + + + TX_ACK_ABORT_COEX_CNT + 0x164 + 0x20 + + + TX_ACK_ABORT_COEX_CNT + 0 + 16 + read-write + + + + + ED_SCAN_COEX_CNT + 0x168 + 0x20 + + + ED_SCAN_COEX_CNT + 0 + 16 + read-write + + + + + RX_ACK_ABORT_COEX_CNT + 0x16C + 0x20 + + + RX_ACK_ABORT_COEX_CNT + 0 + 16 + read-write + + + + + RX_ACK_TIMEOUT_CNT + 0x170 + 0x20 + + + RX_ACK_TIMEOUT_CNT + 0 + 16 + read-write + + + + + TX_BREAK_COEX_CNT + 0x174 + 0x20 + + + TX_BREAK_COEX_CNT + 0 + 16 + read-write + + + + + TX_SECURITY_ERROR_CNT + 0x178 + 0x20 + + + TX_SECURITY_ERROR_CNT + 0 + 16 + read-write + + + + + CCA_BUSY_CNT + 0x17C + 0x20 + + + CCA_BUSY_CNT + 0 + 16 + read-write + + + + + ERROR_CNT_CLEAR + 0x180 + 0x20 + + + CCA_BUSY_CNT_CLEAR + 0 + 1 + read-write + + + TX_SECURITY_ERROR_CNT_CLEAR + 1 + 1 + read-write + + + TX_BREAK_COEX_CNT_CLEAR + 2 + 1 + read-write + + + RX_ACK_TIMEOUT_CNT_CLEAR + 3 + 1 + read-write + + + RX_ACK_ABORT_COEX_CNT_CLEAR + 4 + 1 + read-write + + + ED_SCAN_COEX_CNT_CLEAR + 5 + 1 + read-write + + + TX_ACK_ABORT_COEX_CNT_CLEAR + 6 + 1 + read-write + + + RX_RESTART_CNT_CLEAR + 7 + 1 + read-write + + + RX_ABORT_COEX_CNT_CLEAR + 8 + 1 + read-write + + + NO_RSS_DETECT_CNT_CLEAR + 9 + 1 + read-write + + + RX_FILTER_FAIL_CNT_CLEAR + 10 + 1 + read-write + + + CCA_FAIL_CNT_CLEAR + 11 + 1 + read-write + + + ED_ABORT_CNT_CLEAR + 12 + 1 + read-write + + + CRC_ERROR_CNT_CLEAR + 13 + 1 + read-write + + + SFD_TIMEOUT_CNT_CLEAR + 14 + 1 + read-write + + + + + MAC_DATE + 0x184 + 0x20 + + + MAC_DATE + 0 + 32 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + INTMTX_CORE0 + 0x60010000 + + 0x0 + 0x148 + registers + + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + LP_TIMER + 7 + + + COEX + 8 + + + BLE_TIMER + 9 + + + BLE_SEC + 10 + + + ZB_MAC + 12 + + + FROM_CPU_INTR0 + 22 + + + FROM_CPU_INTR1 + 23 + + + FROM_CPU_INTR2 + 24 + + + FROM_CPU_INTR3 + 25 + + + CACHE + 28 + + + CPU_PERI_TIMEOUT + 29 + + + + WIFI_MAC_INTR_MAP + register description + 0x0 + 0x20 + + + WIFI_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_MAC_NMI_MAP + register description + 0x4 + 0x20 + + + WIFI_MAC_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_PWR_INTR_MAP + register description + 0x8 + 0x20 + + + WIFI_PWR_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_BB_INTR_MAP + register description + 0xC + 0x20 + + + WIFI_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_MAC_INTR_MAP + register description + 0x10 + 0x20 + + + BT_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_INTR_MAP + register description + 0x14 + 0x20 + + + BT_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + register description + 0x18 + 0x20 + + + BT_BB_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + LP_TIMER_INTR_MAP + register description + 0x1C + 0x20 + + + LP_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + COEX_INTR_MAP + register description + 0x20 + 0x20 + + + COEX_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_TIMER_INTR_MAP + register description + 0x24 + 0x20 + + + BLE_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_SEC_INTR_MAP + register description + 0x28 + 0x20 + + + BLE_SEC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_MST_INTR_MAP + register description + 0x2C + 0x20 + + + I2C_MST_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ZB_MAC_INTR_MAP + register description + 0x30 + 0x20 + + + ZB_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PMU_INTR_MAP + register description + 0x34 + 0x20 + + + PMU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + EFUSE_INTR_MAP + register description + 0x38 + 0x20 + + + EFUSE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_RTC_TIMER_INTR_MAP + register description + 0x3C + 0x20 + + + LP_RTC_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_UART_INTR_MAP + register description + 0x40 + 0x20 + + + LP_UART_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_I2C_INTR_MAP + register description + 0x44 + 0x20 + + + LP_I2C_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_WDT_INTR_MAP + register description + 0x48 + 0x20 + + + LP_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_PERI_TIMEOUT_INTR_MAP + register description + 0x4C + 0x20 + + + LP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M0_INTR_MAP + register description + 0x50 + 0x20 + + + LP_APM_M0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M1_INTR_MAP + register description + 0x54 + 0x20 + + + LP_APM_M1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + register description + 0x58 + 0x20 + + + CPU_INTR_FROM_CPU_0_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + register description + 0x5C + 0x20 + + + CPU_INTR_FROM_CPU_1_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + register description + 0x60 + 0x20 + + + CPU_INTR_FROM_CPU_2_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + register description + 0x64 + 0x20 + + + CPU_INTR_FROM_CPU_3_MAP + Need add description + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + register description + 0x68 + 0x20 + + + ASSIST_DEBUG_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TRACE_INTR_MAP + register description + 0x6C + 0x20 + + + TRACE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CACHE_INTR_MAP + register description + 0x70 + 0x20 + + + CACHE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_PERI_TIMEOUT_INTR_MAP + register description + 0x74 + 0x20 + + + CPU_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + register description + 0x78 + 0x20 + + + GPIO_INTERRUPT_PRO_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + register description + 0x7C + 0x20 + + + GPIO_INTERRUPT_PRO_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + PAU_INTR_MAP + register description + 0x80 + 0x20 + + + PAU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_PERI_TIMEOUT_INTR_MAP + register description + 0x84 + 0x20 + + + HP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + MODEM_PERI_TIMEOUT_INTR_MAP register description 0x88 0x20 @@ -24743,8 +26461,15 @@ The least significant eight bits represent the fractional part. need_des 0x0 0x20 - 0x7F000000 + 0x7F800000 + + LP_TOUCH_CK_EN + need_des + 23 + 1 + read-write + RNG_CK_EN need_des @@ -24816,6 +26541,13 @@ The least significant eight bits represent the fractional part. 1 write-only + + LP_TOUCH_RESET_EN + need_des + 24 + 1 + read-write + OTP_DBG_RESET_EN need_des @@ -25799,7 +27531,7 @@ The least significant eight bits represent the fractional part. LP_APM - LP_APM Peripheral + Low-power Access Permission Management Controller LP_APM 0x600B3800 @@ -27474,7 +29206,7 @@ The least significant eight bits represent the fractional part. LP_I2C0 - LP_I2C0 Peripheral + Low-power I2C (Inter-Integrated Circuit) Controller 0 LP_I2C0 0x600B1800 @@ -28971,7 +30703,7 @@ Information. 0x20 - LP_GPIO_OUT_DATA + OUT_DATA set lp gpio output data 0 8 @@ -28986,7 +30718,7 @@ Information. 0x20 - LP_GPIO_OUT_DATA_W1TS + OUT_DATA_W1TS set one time output data 0 8 @@ -29001,7 +30733,7 @@ Information. 0x20 - LP_GPIO_OUT_DATA_W1TC + OUT_DATA_W1TC clear one time output data 0 8 @@ -29016,7 +30748,7 @@ Information. 0x20 - LP_GPIO_ENABLE + ENABLE set lp gpio output data 0 8 @@ -29031,7 +30763,7 @@ Information. 0x20 - LP_GPIO_ENABLE_W1TS + ENABLE_W1TS set one time output data 0 8 @@ -29046,7 +30778,7 @@ Information. 0x20 - LP_GPIO_ENABLE_W1TC + ENABLE_W1TC clear one time output data 0 8 @@ -29061,7 +30793,7 @@ Information. 0x20 - LP_GPIO_STATUS_INTERRUPT + INTERRUPT set lp gpio output data 0 8 @@ -29076,7 +30808,7 @@ Information. 0x20 - LP_GPIO_STATUS_W1TS + STATUS_W1TS set one time output data 0 8 @@ -29091,7 +30823,7 @@ Information. 0x20 - LP_GPIO_STATUS_W1TC + STATUS_W1TC clear one time output data 0 8 @@ -29106,7 +30838,7 @@ Information. 0x20 - LP_GPIO_IN_DATA_NEXT + DATA_NEXT need des 0 8 @@ -29121,42 +30853,42 @@ Information. 0x20 - LP_GPIO0_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO0_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO0_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO0_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO0_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO0_FILTER_EN + FILTER_EN need des 11 1 @@ -29171,42 +30903,42 @@ Information. 0x20 - LP_GPIO1_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO1_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO1_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO1_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO1_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO1_FILTER_EN + FILTER_EN need des 11 1 @@ -29221,42 +30953,42 @@ Information. 0x20 - LP_GPIO2_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO2_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO2_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO2_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO2_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO2_FILTER_EN + FILTER_EN need des 11 1 @@ -29271,42 +31003,42 @@ Information. 0x20 - LP_GPIO3_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO3_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO3_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO3_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO3_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO3_FILTER_EN + FILTER_EN need des 11 1 @@ -29321,42 +31053,42 @@ Information. 0x20 - LP_GPIO4_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO4_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO4_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO4_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO4_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO4_FILTER_EN + FILTER_EN need des 11 1 @@ -29371,42 +31103,42 @@ Information. 0x20 - LP_GPIO5_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO5_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO5_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO5_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO5_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO5_FILTER_EN + FILTER_EN need des 11 1 @@ -29421,42 +31153,42 @@ Information. 0x20 - LP_GPIO6_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO6_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO6_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO6_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO6_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO6_FILTER_EN + FILTER_EN need des 11 1 @@ -29471,42 +31203,42 @@ Information. 0x20 - LP_GPIO7_SYNC_BYPASS + SYNC_BYPASS need des 0 2 read-write - LP_GPIO7_PAD_DRIVER + PAD_DRIVER need des 2 1 read-write - LP_GPIO7_EDGE_WAKEUP_CLR + EDGE_WAKEUP_CLR need des 3 1 write-only - LP_GPIO7_INT_TYPE + INT_TYPE need des 7 3 read-write - LP_GPIO7_WAKEUP_ENABLE + WAKEUP_ENABLE need des 10 1 read-write - LP_GPIO7_FILTER_EN + FILTER_EN need des 11 1 @@ -29521,77 +31253,77 @@ Information. 0x20 - LP_GPIO0_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO0_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO0_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO0_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO0_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO0_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO0_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO0_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO0_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO0_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO0_MCU_SEL + MCU_SEL need des 12 3 @@ -29606,77 +31338,77 @@ Information. 0x20 - LP_GPIO1_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO1_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO1_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO1_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO1_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO1_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO1_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO1_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO1_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO1_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO1_MCU_SEL + MCU_SEL need des 12 3 @@ -29691,77 +31423,77 @@ Information. 0x20 - LP_GPIO2_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO2_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO2_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO2_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO2_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO2_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO2_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO2_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO2_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO2_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO2_MCU_SEL + MCU_SEL need des 12 3 @@ -29776,77 +31508,77 @@ Information. 0x20 - LP_GPIO3_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO3_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO3_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO3_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO3_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO3_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO3_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO3_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO3_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO3_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO3_MCU_SEL + MCU_SEL need des 12 3 @@ -29861,77 +31593,77 @@ Information. 0x20 - LP_GPIO4_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO4_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO4_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO4_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO4_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO4_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO4_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO4_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO4_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO4_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO4_MCU_SEL + MCU_SEL need des 12 3 @@ -29946,77 +31678,77 @@ Information. 0x20 - LP_GPIO5_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO5_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO5_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO5_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO5_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO5_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO5_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO5_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO5_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO5_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO5_MCU_SEL + MCU_SEL need des 12 3 @@ -30031,77 +31763,77 @@ Information. 0x20 - LP_GPIO6_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO6_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO6_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO6_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO6_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO6_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO6_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO6_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO6_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO6_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO6_MCU_SEL + MCU_SEL need des 12 3 @@ -30116,77 +31848,77 @@ Information. 0x20 - LP_GPIO7_MCU_OE + MCU_OE need des 0 1 read-write - LP_GPIO7_SLP_SEL + SLP_SEL need des 1 1 read-write - LP_GPIO7_MCU_WPD + MCU_WPD need des 2 1 read-write - LP_GPIO7_MCU_WPU + MCU_WPU need des 3 1 read-write - LP_GPIO7_MCU_IE + MCU_IE need des 4 1 read-write - LP_GPIO7_MCU_DRV + MCU_DRV need des 5 2 read-write - LP_GPIO7_FUN_WPD + FUN_WPD need des 7 1 read-write - LP_GPIO7_FUN_WPU + FUN_WPU need des 8 1 read-write - LP_GPIO7_FUN_IE + FUN_IE need des 9 1 read-write - LP_GPIO7_FUN_DRV + FUN_DRV need des 10 2 read-write - LP_GPIO7_MCU_SEL + MCU_SEL need des 12 3 @@ -30201,7 +31933,7 @@ Information. 0x20 - LP_GPIO_STATUS_INTERRUPT_NEXT + NEXT need des 0 8 @@ -30310,7 +32042,7 @@ Information. LP_TEE - LP_TEE Peripheral + Low-power Trusted Execution Environment LP_TEE 0x600B3400 @@ -30386,7 +32118,7 @@ Information. LP_TIMER - LP_TIMER Peripheral + Low-power Timer LP_TIMER 0x600B0C00 @@ -30787,7 +32519,7 @@ Information. LP_UART - LP_UART Peripheral + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller LP_UART 0x600B1400 @@ -32244,7 +33976,7 @@ Information. LP_WDT - LP_WDT Peripheral + Low-power Watchdog Timer LP_WDT 0x600B1C00 @@ -40144,7 +41876,7 @@ Information. PARL_IO - PARL_IO Peripheral + Parallel IO Controller PARL_IO 0x60015000 @@ -41709,21 +43441,21 @@ Any pulses with width less than this will be ignored when the filter is enabled. - I2C_CONF + I2C0_CONF I2C configuration register 0x20 0x20 0x00000001 - I2C_CLK_EN + I2C0_CLK_EN Set 1 to enable i2c apb clock 0 1 read-write - I2C_RST_EN + I2C0_RST_EN Set 0 to reset i2c module 1 1 @@ -47546,17 +49278,17 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x4 - TX_CH%sDATA + CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 - CHDATA + DATA Read and write data for channel %s via APB FIFO. 0 32 - read-only + read-write @@ -47683,42 +49415,43 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x8 - RX_CH%sCONF0 + 2-3 + CH%s_RX_CONF0 Channel %s configure register 0 0x18 0x20 0x30FFFF02 - DIV_CNT_CH2 + DIV_CNT This register is used to configure the divider for clock of CHANNEL%s. 0 8 read-write - IDLE_THRES_CH2 + IDLE_THRES When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. 8 15 read-write - MEM_SIZE_CH2 + MEM_SIZE This register is used to configure the maximum size of memory allocated to CHANNEL%s. 23 3 read-write - CARRIER_EN_CH2 + CARRIER_EN This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 28 1 read-write - CARRIER_OUT_LV_CH2 + CARRIER_OUT_LV This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. @@ -47733,35 +49466,36 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x8 - RX_CH%sCONF1 + 2-3 + CH%s_RX_CONF1 Channel %s configure register 1 0x1C 0x20 0x000001E8 - RX_EN_CH2 + RX_EN Set this bit to enable receiver to receive data on CHANNEL%s. 0 1 read-write - MEM_WR_RST_CH2 + MEM_WR_RST Set this bit to reset write ram address for CHANNEL%s by accessing receiver. 1 1 write-only - APB_MEM_RST_CH2 + APB_MEM_RST Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 2 1 write-only - MEM_OWNER_CH2 + MEM_OWNER This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. @@ -47772,35 +49506,35 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RX_FILTER_EN_CH2 + RX_FILTER_EN This is the receive filter's enable bit for CHANNEL%s. 4 1 read-write - RX_FILTER_THRES_CH2 + RX_FILTER_THRES Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). 5 8 read-write - MEM_RX_WRAP_EN_CH2 + MEM_RX_WRAP_EN This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. 13 1 read-write - AFIFO_RST_CH2 + AFIFO_RST Reserved 14 1 write-only - CONF_UPDATE_CH2 + CONF_UPDATE synchronization bit for CHANNEL%s 15 1 @@ -47811,55 +49545,55 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x4 - TX_CH%sSTATUS + CH%s_TX_STATUS Channel %s status register 0x28 0x20 - MEM_RADDR_EX_CH0 + MEM_RADDR_EX This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. 0 9 read-only - STATE_CH0 + STATE This register records the FSM status of CHANNEL%s. 9 3 read-only - APB_MEM_WADDR_CH0 + APB_MEM_WADDR This register records the memory address offset when writes RAM over APB bus. 12 9 read-only - APB_MEM_RD_ERR_CH0 + APB_MEM_RD_ERR This status bit will be set if the offset address out of memory size when reading via APB bus. 21 1 read-only - MEM_EMPTY_CH0 + MEM_EMPTY This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. 22 1 read-only - APB_MEM_WR_ERR_CH0 + APB_MEM_WR_ERR This status bit will be set if the offset address out of memory size when writes via APB bus. 23 1 read-only - APB_MEM_RADDR_CH0 + APB_MEM_RADDR This register records the memory address offset when reading RAM over APB bus. 24 8 @@ -47870,48 +49604,48 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x4 - RX_CH%sSTATUS + CH%s_RX_STATUS Channel %s status register 0x30 0x20 - MEM_WADDR_EX_CH2 + MEM_WADDR_EX This register records the memory address offset when receiver of CHANNEL%s is using the RAM. 0 9 read-only - APB_MEM_RADDR_CH2 + APB_MEM_RADDR This register records the memory address offset when reads RAM over APB bus. 12 9 read-only - STATE_CH2 + STATE This register records the FSM status of CHANNEL%s. 22 3 read-only - MEM_OWNER_ERR_CH2 + MEM_OWNER_ERR This status bit will be set when the ownership of memory block is wrong. 25 1 read-only - MEM_FULL_CH2 + MEM_FULL This status bit will be set if the receiver receives more data than the memory size. 26 1 read-only - APB_MEM_RD_ERR_CH2 + APB_MEM_RD_ERR This status bit will be set if the offset address out of memory size when reads via APB bus. 27 1 @@ -47929,7 +49663,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 0-1 - CH%s_TX_END_INT_RAW + CH%s_TX_END The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 @@ -47939,27 +49673,37 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 2-3 - CH%s_RX_END_INT_RAW + CH%s_RX_END The interrupt raw bit for CHANNEL2. Triggered when reception done. 2 1 read-write - 4 + 2 0x1 - 0-3 - CH%s_TX_ERR_INT_RAW + 0-1 + CH%s_TX_ERR The interrupt raw bit for CHANNEL4. Triggered when error occurs. 4 1 read-write + + 2 + 0x1 + 2-3 + CH%s_RX_ERR + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 6 + 1 + read-write + 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 8 1 @@ -47969,7 +49713,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 2-3 - CH%s_RX_THR_EVENT_INT_RAW + CH%s_RX_THR_EVENT The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. 10 1 @@ -47979,7 +49723,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 0-1 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 12 1 @@ -47994,103 +49738,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_ST - The masked interrupt status bit for CH0_TX_END_INT. + 2 + 0x1 + 0-1 + CH%s_TX_END + The masked interrupt status bit for CH%s_TX_END_INT. 0 1 read-only - CH1_TX_END_INT_ST - The masked interrupt status bit for CH1_TX_END_INT. - 1 - 1 - read-only - - - CH2_RX_END_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_END The masked interrupt status bit for CH2_RX_END_INT. 2 1 read-only - CH3_RX_END_INT_ST - The masked interrupt status bit for CH3_RX_END_INT. - 3 - 1 - read-only - - - RX_CH0_ERR_INT_ST + 2 + 0x1 + 0-1 + CH%s_TX_ERR The masked interrupt status bit for CH4_ERR_INT. 4 1 read-only - RX_CH1_ERR_INT_ST - The masked interrupt status bit for CH5_ERR_INT. - 5 - 1 - read-only - - - RX_CH2_ERR_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_ERR The masked interrupt status bit for CH6_ERR_INT. 6 1 read-only - RX_CH3_ERR_INT_ST - The masked interrupt status bit for CH7_ERR_INT. - 7 - 1 - read-only - - - CH0_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 8 1 read-only - CH1_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-only - - - CH2_RX_THR_EVENT_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT The masked interrupt status bit for CH2_RX_THR_EVENT_INT. 10 1 read-only - CH3_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH3_RX_THR_EVENT_INT. - 11 - 1 - read-only - - - CH0_TX_LOOP_INT_ST - The masked interrupt status bit for CH0_TX_LOOP_INT. + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The masked interrupt status bit for CH%s_TX_LOOP_INT. 12 1 read-only - - CH1_TX_LOOP_INT_ST - The masked interrupt status bit for CH1_TX_LOOP_INT. - 13 - 1 - read-only - @@ -48100,103 +49816,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_ENA - The interrupt enable bit for CH0_TX_END_INT. + 2 + 0x1 + 0-1 + CH%s_TX_END + The interrupt enable bit for CH%s_TX_END_INT. 0 1 read-write - CH1_TX_END_INT_ENA - The interrupt enable bit for CH1_TX_END_INT. - 1 - 1 - read-write - - - CH2_RX_END_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_END The interrupt enable bit for CH2_RX_END_INT. 2 1 read-write - CH3_RX_END_INT_ENA - The interrupt enable bit for CH3_RX_END_INT. - 3 - 1 - read-write - - - CH0_ERR_INT_ENA + 2 + 0x1 + 0-1 + CH%s_TX_ERR The interrupt enable bit for CH4_ERR_INT. 4 1 read-write - CH1_ERR_INT_ENA - The interrupt enable bit for CH5_ERR_INT. - 5 - 1 - read-write - - - CH2_ERR_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_ERR The interrupt enable bit for CH6_ERR_INT. 6 1 read-write - CH3_ERR_INT_ENA - The interrupt enable bit for CH7_ERR_INT. - 7 - 1 - read-write - - - CH0_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. 8 1 read-write - CH1_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-write - - - CH2_RX_THR_EVENT_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT The interrupt enable bit for CH2_RX_THR_EVENT_INT. 10 1 read-write - CH3_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH3_RX_THR_EVENT_INT. - 11 - 1 - read-write - - - CH0_TX_LOOP_INT_ENA - The interrupt enable bit for CH0_TX_LOOP_INT. + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The interrupt enable bit for CH%s_TX_LOOP_INT. 12 1 read-write - - CH1_TX_LOOP_INT_ENA - The interrupt enable bit for CH1_TX_LOOP_INT. - 13 - 1 - read-write - @@ -48209,7 +49897,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 0-1 - CH%s_TX_END_INT_CLR + CH%s_TX_END Set this bit to clear theCH%s_TX_END_INT interrupt. 0 1 @@ -48219,45 +49907,37 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 2-3 - CH%s_RX_END_INT_CLR + CH%s_RX_END Set this bit to clear theCH2_RX_END_INT interrupt. 2 1 write-only - CH0_TX_ERR_INT_CLR + 2 + 0x1 + 0-1 + CH%s_TX_ERR Set this bit to clear theCH4_ERR_INT interrupt. 4 1 write-only - CH1_TX_ERR_INT_CLR - Set this bit to clear theCH5_ERR_INT interrupt. - 5 - 1 - write-only - - - CH0_RX_ERR_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_ERR Set this bit to clear theCH6_ERR_INT interrupt. 6 1 write-only - - CH1_RX_ERR_INT_CLR - Set this bit to clear theCH7_ERR_INT interrupt. - 7 - 1 - write-only - 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. 8 1 @@ -48267,26 +49947,22 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x1 2-3 - CH%s_RX_THR_EVENT_INT_CLR + CH%s_RX_THR_EVENT Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. 10 1 write-only - CH0_TX_LOOP_INT_CLR - Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 2 + 0x1 + 0-1 + CH%s_TX_LOOP + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. 12 1 write-only - - CH1_TX_LOOP_INT_CLR - Set this bit to clear theCH1_TX_LOOP_INT interrupt. - 13 - 1 - write-only - @@ -48299,14 +49975,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00400040 - CARRIER_LOW_CH0 + CARRIER_LOW This register is used to configure carrier wave 's low level clock period for CHANNEL%s. 0 16 read-write - CARRIER_HIGH_CH0 + CARRIER_HIGH This register is used to configure carrier wave 's high level clock period for CHANNEL%s. 16 16 @@ -48323,14 +49999,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CARRIER_LOW_THRES_CH2 + CARRIER_LOW_THRES The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. 0 16 read-write - CARRIER_HIGH_THRES_CH2 + CARRIER_HIGH_THRES The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. 16 16 @@ -48394,7 +50070,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000080 - RMT_RX_LIM_CH2 + RMT_RX_LIM This register is used to configure the maximum entries that CHANNEL%s can receive. 0 9 @@ -48517,7 +50193,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - TX_REF_CNT_RST_CH0 + TX_REF_CNT_RST This register is used to reset the clock divider of CHANNEL0. 0 1 @@ -48600,39 +50276,39 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 384 - 0x1 + 96 + 0x4 M_MEM[%s] The memory that stores M 0x0 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 Z_MEM[%s] The memory that stores Z 0x200 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 Y_MEM[%s] The memory that stores Y 0x400 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 X_MEM[%s] The memory that stores X 0x600 - 0x8 + 0x20 read-write @@ -49031,20 +50707,20 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 64 - 0x1 + 8 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 @@ -53141,7 +54817,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. SOC_ETM - SOC_ETM Peripheral + Event Task Matrix SOC_ETM 0x60013000 @@ -63553,8 +65229,7 @@ counter. LOAD - -Write any value to trigger a timer %s time-base counter reload. + Write any value to trigger a timer %s time-base counter reload. 0 32 write-only @@ -63621,32 +65296,28 @@ Write any value to trigger a timer %s time-base counter reload. WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write @@ -64038,7 +65709,7 @@ protection is enabled. TRACE - TRACE Peripheral + RISC-V Trace Encoder TRACE 0x600C0000 @@ -64058,7 +65729,7 @@ protection is enabled. 0x20 - MEM_STAET_ADDR + MEM_START_ADDR The start address of trace memory 0 32 @@ -67837,7 +69508,7 @@ protection is enabled. registers - USB + USB_DEVICE 48 diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32h2.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32h2.svd index bed963865..2531f72af 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32h2.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32h2.svd @@ -4,10 +4,9 @@ ESPRESSIF ESP32-H2 ESP32 H-Series - 5 + 11 32-bit RISC-V MCU & Bluetooth 5 (LE) & IEEE 802.15.4 - - Copyright 2023 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. RV32IMAC r0p0 little false false - 4 + 0 false 32 @@ -351,36 +349,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -1543,7 +1541,7 @@ ASSIST_DEBUG Debug Assist ASSIST_DEBUG - 0x600CE000 + 0x600C2000 0x0 0x80 @@ -1555,7 +1553,7 @@ - C0RE_0_INTR_ENA + CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 @@ -1739,90 +1737,90 @@ - CORE_0_INTR_RLS + CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS + CORE_0_AREA_DRAM0_0_RD_INTR_ENA Core0 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_RLS + CORE_0_AREA_DRAM0_0_WR_INTR_ENA Core0 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_0_AREA_DRAM0_1_RD_RLS + CORE_0_AREA_DRAM0_1_RD_INTR_ENA Core0 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_0_AREA_DRAM0_1_WR_RLS + CORE_0_AREA_DRAM0_1_WR_INTR_ENA Core0 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_0_AREA_PIF_0_RD_RLS + CORE_0_AREA_PIF_0_RD_INTR_ENA Core0 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_0_AREA_PIF_0_WR_RLS + CORE_0_AREA_PIF_0_WR_INTR_ENA Core0 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_0_AREA_PIF_1_RD_RLS + CORE_0_AREA_PIF_1_RD_INTR_ENA Core0 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_0_AREA_PIF_1_WR_RLS + CORE_0_AREA_PIF_1_WR_INTR_ENA Core0 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_0_SP_SPILL_MIN_RLS + CORE_0_SP_SPILL_MIN_INTR_ENA Core0 stackpoint underflow monitor interrupt enable 8 1 read-write - CORE_0_SP_SPILL_MAX_RLS + CORE_0_SP_SPILL_MAX_INTR_ENA Core0 stackpoint overflow monitor interrupt enable 9 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -2422,8 +2420,8 @@ - GDMA - GDMA Peripheral + DMA + DMA (Direct Memory Access) Controller DMA 0x60080000 @@ -2524,49 +2522,49 @@ 0x20 - IN_DONE_CH_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - IN_DSCR_ERR_CH_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - IN_DSCR_EMPTY_CH_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-only - INFIFO_OVF_CH_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 5 1 read-only - INFIFO_UDF_CH_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 6 1 @@ -2583,49 +2581,49 @@ 0x20 - IN_DONE_CH_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - IN_DSCR_ERR_CH_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - IN_DSCR_EMPTY_CH_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-write - INFIFO_OVF_CH_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 5 1 read-write - INFIFO_UDF_CH_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 6 1 @@ -2753,42 +2751,42 @@ 0x20 - OUT_DONE_CH_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_CH_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_CH_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 @@ -2805,42 +2803,42 @@ 0x20 - OUT_DONE_CH_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_CH_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_CH_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 @@ -3704,60 +3702,60 @@ - 512 - 0x1 + 128 + 0x4 Y_MEM[%s] memory that stores Y 0x0 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 M_MEM[%s] memory that stores M 0x200 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 RB_MEM[%s] memory that stores Rb 0x400 - 0x8 + 0x20 - 48 - 0x1 + 12 + 0x4 BOX_MEM[%s] memory that stores BOX 0x600 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] memory that stores IV 0x630 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 X_MEM[%s] memory that stores X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] memory that stores Z 0xA00 - 0x8 + 0x20 SET_START @@ -4038,28 +4036,55 @@ - 32 - 0x1 + 8 + 0x4 K_MEM[%s] The memory that stores k. 0x100 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 PX_MEM[%s] The memory that stores Px. 0x120 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 PY_MEM[%s] The memory that stores Py. 0x140 - 0x8 + 0x20 + + + 8 + 0x4 + QX_MEM%s + The memory that stores Qx + 0x160 + 0x20 + read-write + + + 8 + 0x4 + QY_MEM%s + The memory that stores Qy + 0x180 + 0x20 + read-write + + + 8 + 0x4 + QZ_MEM%s + The memory that stores Qz + 0x1A0 + 0x20 + read-write @@ -4714,17 +4739,52 @@ 0x20 - MAC_RESERVED_1 - Reserved. + RXIQ_VERSION + Stores RF Calibration data. RXIQ version. 0 - 14 + 3 read-only - MAC_RESERVED_0 - Reserved. - 14 - 18 + RXIQ_0 + Stores RF Calibration data. RXIQ data 0. + 3 + 7 + read-only + + + RXIQ_1 + Stores RF Calibration data. RXIQ data 1. + 10 + 7 + read-only + + + ACTIVE_HP_DBIAS + Stores the PMU active hp dbias. + 17 + 5 + read-only + + + ACTIVE_LP_DBIAS + Stores the PMU active lp dbias. + 22 + 5 + read-only + + + DSLP_DBIAS + Stores the PMU sleep dbias. + 27 + 4 + read-only + + + DBIAS_VOL_GAP_VALUE1 + Stores the low 1 bit of dbias_vol_gap. + 31 + 1 read-only @@ -4735,18 +4795,67 @@ 0x50 0x20 + + DBIAS_VOL_GAP_VALUE2 + Stores the high 3 bits of dbias_vol_gap. + 0 + 3 + read-only + + + DBIAS_VOL_GAP_SIGN + Stores the sign bit of dbias_vol_gap. + 3 + 1 + read-only + MAC_RESERVED_2 Reserved. - 0 - 18 + 4 + 14 read-only - SYS_DATA_PART0_0 - Stores the first 14 bits of the zeroth part of system data. + WAFER_VERSION_MINOR + Stores the wafer version minor. 18 - 14 + 3 + read-only + + + WAFER_VERSION_MAJOR + Stores the wafer version major. + 21 + 2 + read-only + + + DISABLE_WAFER_VERSION_MAJOR + Disables check of wafer version major. + 23 + 1 + read-only + + + FLASH_CAP + Stores the flash cap. + 24 + 3 + read-only + + + FLASH_TEMP + Stores the flash temp. + 27 + 2 + read-only + + + FLASH_VENDOR + Stores the flash vendor. + 29 + 3 read-only @@ -7297,1056 +7406,1054 @@ - HMAC - HMAC (Hash-based Message Authentication Code) Accelerator - HMAC - 0x6008D000 + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x60091F00 0x0 - 0xA4 + 0x90 registers - SET_START - Process control register 0. - 0x40 + 4 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 0x20 + 0x0000FF00 - SET_START - Start hmac operation. + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. 0 - 1 - write-only + 8 + read-write - - - - SET_PARA_PURPOSE - Configure purpose. - 0x44 - 0x20 - - PURPOSE_SET - Set hmac parameter purpose. - 0 - 4 - write-only + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write - SET_PARA_KEY - Configure key. - 0x48 + CLOCK_GATE + Clock Gating Configure Register + 0x20 0x20 - KEY_SET - Set hmac parameter key. + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. 0 - 3 - write-only + 1 + read-write - SET_PARA_FINISH - Finish initial configuration. - 0x4C + SIGMADELTA_MISC + MISC Register + 0x24 0x20 - SET_PARA_END - Finish hmac configuration. - 0 + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 1 - write-only + read-write - - - - SET_MESSAGE_ONE - Process control register 1. - 0x50 - 0x20 - - SET_TEXT_ONE - Call SHA to calculate one message block. - 0 + SPI_SWAP + Reserved. + 31 1 - write-only + read-write - SET_MESSAGE_ING - Process control register 2. - 0x54 + PAD_COMP_CONFIG + PAD Compare configure Register + 0x28 0x20 - SET_TEXT_ING - Continue typical hmac. + XPD_COMP + Pad compare enable bit. 0 1 - write-only + read-write - - - - SET_MESSAGE_END - Process control register 3. - 0x58 - 0x20 - - SET_TEXT_END - Start hardware padding. - 0 + MODE_COMP + 1 to enable external reference from PAD[0]. 0 to enable internal reference, meanwhile PAD[0] can be used as a regular GPIO. + 1 1 - write-only + read-write - - - - SET_RESULT_FINISH - Process control register 4. - 0x5C - 0x20 - - SET_RESULT_END - After read result from upstream, then let hmac back to idle. - 0 - 1 - write-only + DREF_COMP + internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + 2 + 3 + read-write - - - - SET_INVALIDATE_JTAG - Invalidate register 0. - 0x60 - 0x20 - - SET_INVALIDATE_JTAG - Clear result from hmac downstream JTAG. - 0 - 1 - write-only + ZERO_DET_MODE + Zero Detect mode select. + 5 + 2 + read-write - SET_INVALIDATE_DS - Invalidate register 1. - 0x64 + PAD_COMP_FILTER + Zero Detect filter Register + 0x2C 0x20 - SET_INVALIDATE_DS - Clear result from hmac downstream DS. + ZERO_DET_FILTER_CNT + Zero Detect filter cycle length 0 - 1 - write-only + 32 + read-write - QUERY_ERROR - Error register. - 0x68 + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 0x20 - QUREY_CHECK - Hmac configuration state. 0: key are agree with purpose. 1: error + FILTER_CH0_EN + Glitch Filter channel enable bit. 0 1 - read-only + read-write - - - - QUERY_BUSY - Busy register. - 0x6C - 0x20 - - BUSY_STATE - Hmac state. 1'b0: idle. 1'b1: busy - 0 - 1 - read-only + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write - 64 - 0x1 - WR_MESSAGE_MEM[%s] - Message block memory. - 0x80 - 0x8 - - - 32 - 0x1 - RD_RESULT_MEM[%s] - Result from upstream. - 0xC0 - 0x8 - - - SET_MESSAGE_PAD - Process control register 5. - 0xF0 + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 0x20 - SET_TEXT_PAD - Start software padding. + ETM_CH0_EVENT_SEL + Etm event channel select gpio. 0 + 5 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 1 - write-only + read-write - ONE_BLOCK - Process control register 6. - 0xF4 + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 0x20 - SET_ONE_BLOCK - Don't have to do padding. + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. 0 1 - write-only + read-write - - - - SOFT_JTAG_CTRL - Jtag register 0. - 0xF8 - 0x20 - - SOFT_JTAG_CTRL - Turn on JTAG verification. - 0 + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 1 - write-only + read-write - - - - WR_JTAG - Jtag register 1. - 0xFC - 0x20 - - WR_JTAG - 32-bit of key to be compared. - 0 - 32 - write-only + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write - - - - DATE - Date register. - 0x1FC - 0x20 - 0x20200618 - - DATE - Hmac date information/ hmac version information. - 0 - 30 + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 read-write - - - - - - HP_APM - HP_APM Peripheral - HP_APM - 0x60099000 - - 0x0 - 0x114 - registers - - - HP_APM_M0 - 26 - - - HP_APM_M1 - 27 - - - HP_APM_M2 - 28 - - - HP_APM_M3 - 29 - - - - REGION_FILTER_EN - Region filter enable register - 0x0 - 0x20 - 0x00000001 - - REGION_FILTER_EN - Region filter enable - 0 - 16 + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - - - - REGION0_ADDR_START - Region address register - 0x4 - 0x20 - - REGION0_ADDR_START - Start address of region0 - 0 - 32 + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 read-write - - - - REGION0_ADDR_END - Region address register - 0x8 - 0x20 - 0xFFFFFFFF - - REGION0_ADDR_END - End address of region0 - 0 - 32 + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION0_PMS_ATTR - Region access authority attribute register - 0xC + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 0x20 - REGION0_R0_PMS_X - Region execute authority in REE_MODE0 + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. 0 1 read-write - REGION0_R0_PMS_W - Region write authority in REE_MODE0 + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. 1 - 1 + 3 read-write - REGION0_R0_PMS_R - Region read authority in REE_MODE0 - 2 + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 1 read-write - REGION0_R1_PMS_X - Region execute authority in REE_MODE1 - 4 - 1 - read-write - - - REGION0_R1_PMS_W - Region write authority in REE_MODE1 - 5 - 1 - read-write - - - REGION0_R1_PMS_R - Region read authority in REE_MODE1 - 6 - 1 + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - REGION0_R2_PMS_X - Region execute authority in REE_MODE2 - 8 + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 1 read-write - REGION0_R2_PMS_W - Region write authority in REE_MODE2 - 9 - 1 + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - REGION0_R2_PMS_R - Region read authority in REE_MODE2 - 10 + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 1 read-write - - - - REGION1_ADDR_START - Region address register - 0x10 - 0x20 - - - REGION1_ADDR_START - Start address of region1 - 0 - 32 - read-write - - - - - REGION1_ADDR_END - Region address register - 0x14 - 0x20 - 0xFFFFFFFF - - REGION1_ADDR_END - End address of region1 - 0 - 32 + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION1_PMS_ATTR - Region access authority attribute register - 0x18 + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 0x20 - REGION1_R0_PMS_X - Region execute authority in REE_MODE0 + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. 0 1 read-write - REGION1_R0_PMS_W - Region write authority in REE_MODE0 + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. 1 - 1 - read-write - - - REGION1_R0_PMS_R - Region read authority in REE_MODE0 - 2 - 1 - read-write - - - REGION1_R1_PMS_X - Region execute authority in REE_MODE1 - 4 - 1 + 3 read-write - REGION1_R1_PMS_W - Region write authority in REE_MODE1 - 5 + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 1 read-write - REGION1_R1_PMS_R - Region read authority in REE_MODE1 - 6 - 1 + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - REGION1_R2_PMS_X - Region execute authority in REE_MODE2 - 8 + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 1 read-write - REGION1_R2_PMS_W - Region write authority in REE_MODE2 - 9 - 1 + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - REGION1_R2_PMS_R - Region read authority in REE_MODE2 - 10 + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 1 read-write - - - - REGION2_ADDR_START - Region address register - 0x1C - 0x20 - - - REGION2_ADDR_START - Start address of region2 - 0 - 32 - read-write - - - - - REGION2_ADDR_END - Region address register - 0x20 - 0x20 - 0xFFFFFFFF - - REGION2_ADDR_END - End address of region2 - 0 - 32 + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION2_PMS_ATTR - Region access authority attribute register - 0x24 + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC 0x20 - REGION2_R0_PMS_X - Region execute authority in REE_MODE0 + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. 0 1 read-write - REGION2_R0_PMS_W - Region write authority in REE_MODE0 + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. 1 - 1 - read-write - - - REGION2_R0_PMS_R - Region read authority in REE_MODE0 - 2 - 1 + 3 read-write - REGION2_R1_PMS_X - Region execute authority in REE_MODE1 - 4 + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 1 read-write - REGION2_R1_PMS_W - Region write authority in REE_MODE1 - 5 - 1 + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - REGION2_R1_PMS_R - Region read authority in REE_MODE1 - 6 + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 1 read-write - REGION2_R2_PMS_X - Region execute authority in REE_MODE2 - 8 - 1 + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - REGION2_R2_PMS_W - Region write authority in REE_MODE2 - 9 + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 1 read-write - REGION2_R2_PMS_R - Region read authority in REE_MODE2 - 10 - 1 + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION3_ADDR_START - Region address register - 0x28 + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 0x20 - REGION3_ADDR_START - Start address of region3 + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. 0 - 32 + 1 read-write - - - - REGION3_ADDR_END - Region address register - 0x2C - 0x20 - 0xFFFFFFFF - - REGION3_ADDR_END - End address of region3 - 0 - 32 + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - - - - REGION3_PMS_ATTR - Region access authority attribute register - 0x30 - 0x20 - - REGION3_R0_PMS_X - Region execute authority in REE_MODE0 - 0 + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 1 read-write - REGION3_R0_PMS_W - Region write authority in REE_MODE0 - 1 - 1 + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - REGION3_R0_PMS_R - Region read authority in REE_MODE0 - 2 + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 1 read-write - REGION3_R1_PMS_X - Region execute authority in REE_MODE1 - 4 - 1 + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - REGION3_R1_PMS_W - Region write authority in REE_MODE1 - 5 + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 1 read-write - REGION3_R1_PMS_R - Region read authority in REE_MODE1 - 6 + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 1 read-write - REGION3_R2_PMS_X - Region execute authority in REE_MODE2 + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. 8 1 read-write - REGION3_R2_PMS_W - Region write authority in REE_MODE2 + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. 9 - 1 + 3 read-write - REGION3_R2_PMS_R - Region read authority in REE_MODE2 - 10 + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 1 read-write - - - - REGION4_ADDR_START - Region address register - 0x34 - 0x20 - - REGION4_ADDR_START - Start address of region4 - 0 - 32 + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - - - - REGION4_ADDR_END - Region address register - 0x38 - 0x20 - 0xFFFFFFFF - - REGION4_ADDR_END - End address of region4 - 0 - 32 + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION4_PMS_ATTR - Region access authority attribute register - 0x3C + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 0x20 - REGION4_R0_PMS_X - Region execute authority in REE_MODE0 + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. 0 1 read-write - REGION4_R0_PMS_W - Region write authority in REE_MODE0 + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. 1 - 1 - read-write - - - REGION4_R0_PMS_R - Region read authority in REE_MODE0 - 2 - 1 + 3 read-write - REGION4_R1_PMS_X - Region execute authority in REE_MODE1 - 4 + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 1 read-write - REGION4_R1_PMS_W - Region write authority in REE_MODE1 - 5 - 1 + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - REGION4_R1_PMS_R - Region read authority in REE_MODE1 - 6 + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 1 read-write - REGION4_R2_PMS_X - Region execute authority in REE_MODE2 - 8 - 1 + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - REGION4_R2_PMS_W - Region write authority in REE_MODE2 - 9 + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 1 read-write - REGION4_R2_PMS_R - Region read authority in REE_MODE2 - 10 - 1 + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - REGION5_ADDR_START - Region address register - 0x40 + INT_RAW + GPIOSD interrupt raw register + 0xE0 0x20 - REGION5_ADDR_START - Start address of region5 + PAD_COMP_INT_RAW + Pad compare raw interrupt 0 - 32 - read-write + 1 + read-only - REGION5_ADDR_END - Region address register - 0x44 + INT_ST + GPIOSD interrupt masked register + 0xE4 0x20 - 0xFFFFFFFF - REGION5_ADDR_END - End address of region5 + PAD_COMP_INT_ST + Pad compare masked interrupt 0 - 32 - read-write + 1 + read-only - REGION5_PMS_ATTR - Region access authority attribute register - 0x48 + INT_ENA + GPIOSD interrupt enable register + 0xE8 0x20 - REGION5_R0_PMS_X - Region execute authority in REE_MODE0 + PAD_COMP_INT_ENA + Pad compare interrupt enable 0 1 read-write + + + + INT_CLR + GPIOSD interrupt clear register + 0xEC + 0x20 + - REGION5_R0_PMS_W - Region write authority in REE_MODE0 - 1 - 1 - read-write - - - REGION5_R0_PMS_R - Region read authority in REE_MODE0 - 2 - 1 - read-write - - - REGION5_R1_PMS_X - Region execute authority in REE_MODE1 - 4 - 1 - read-write - - - REGION5_R1_PMS_W - Region write authority in REE_MODE1 - 5 - 1 - read-write - - - REGION5_R1_PMS_R - Region read authority in REE_MODE1 - 6 - 1 - read-write - - - REGION5_R2_PMS_X - Region execute authority in REE_MODE2 - 8 + PAD_COMP_INT_CLR + Pad compare interrupt clear + 0 1 - read-write + write-only + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02208120 + - REGION5_R2_PMS_W - Region write authority in REE_MODE2 - 9 - 1 + GPIO_SD_DATE + Version control register. + 0 + 28 read-write + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6008D000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + - REGION5_R2_PMS_R - Region read authority in REE_MODE2 - 10 + SET_START + Start hmac operation. + 0 1 - read-write + write-only - REGION6_ADDR_START - Region address register - 0x4C + SET_PARA_PURPOSE + Configure purpose. + 0x44 0x20 - REGION6_ADDR_START - Start address of region6 + PURPOSE_SET + Set hmac parameter purpose. 0 - 32 - read-write + 4 + write-only - REGION6_ADDR_END - Region address register - 0x50 + SET_PARA_KEY + Configure key. + 0x48 0x20 - 0xFFFFFFFF - REGION6_ADDR_END - End address of region6 + KEY_SET + Set hmac parameter key. 0 - 32 - read-write + 3 + write-only - REGION6_PMS_ATTR - Region access authority attribute register - 0x54 + SET_PARA_FINISH + Finish initial configuration. + 0x4C 0x20 - REGION6_R0_PMS_X - Region execute authority in REE_MODE0 + SET_PARA_END + Finish hmac configuration. 0 1 - read-write + write-only + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + - REGION6_R0_PMS_W - Region write authority in REE_MODE0 - 1 + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 1 - read-write + write-only + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + - REGION6_R0_PMS_R - Region read authority in REE_MODE0 - 2 + SET_TEXT_ING + Continue typical hmac. + 0 1 - read-write + write-only + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + - REGION6_R1_PMS_X - Region execute authority in REE_MODE1 - 4 + SET_TEXT_END + Start hardware padding. + 0 1 - read-write + write-only + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + - REGION6_R1_PMS_W - Region write authority in REE_MODE1 - 5 + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 1 - read-write + write-only + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + - REGION6_R1_PMS_R - Region read authority in REE_MODE1 - 6 + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 1 - read-write + write-only + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + - REGION6_R2_PMS_X - Region execute authority in REE_MODE2 - 8 + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 1 - read-write + write-only + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + - REGION6_R2_PMS_W - Region write authority in REE_MODE2 - 9 + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 1 - read-write + read-only + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + - REGION6_R2_PMS_R - Region read authority in REE_MODE2 - 10 + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 16 + 0x4 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x20 + + + 8 + 0x4 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x20 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 read-write + + + + HP_APM + HP_APM Peripheral + HP_APM + 0x60099000 + + 0x0 + 0x114 + registers + + + HP_APM_M0 + 26 + + + HP_APM_M1 + 27 + + + HP_APM_M2 + 28 + + + HP_APM_M3 + 29 + + - REGION7_ADDR_START + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 16 + read-write + + + + + REGION0_ADDR_START Region address register - 0x58 + 0x4 0x20 - REGION7_ADDR_START - Start address of region7 + REGION0_ADDR_START + Start address of region0 0 32 read-write @@ -8354,15 +8461,15 @@ - REGION7_ADDR_END + REGION0_ADDR_END Region address register - 0x5C + 0x8 0x20 0xFFFFFFFF - REGION7_ADDR_END - End address of region7 + REGION0_ADDR_END + End address of region0 0 32 read-write @@ -8370,69 +8477,69 @@ - REGION7_PMS_ATTR + REGION0_PMS_ATTR Region access authority attribute register - 0x60 + 0xC 0x20 - REGION7_R0_PMS_X + REGION0_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION7_R0_PMS_W + REGION0_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION7_R0_PMS_R + REGION0_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION7_R1_PMS_X + REGION0_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION7_R1_PMS_W + REGION0_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION7_R1_PMS_R + REGION0_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION7_R2_PMS_X + REGION0_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION7_R2_PMS_W + REGION0_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION7_R2_PMS_R + REGION0_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8441,14 +8548,14 @@ - REGION8_ADDR_START + REGION1_ADDR_START Region address register - 0x64 + 0x10 0x20 - REGION8_ADDR_START - Start address of region8 + REGION1_ADDR_START + Start address of region1 0 32 read-write @@ -8456,15 +8563,15 @@ - REGION8_ADDR_END + REGION1_ADDR_END Region address register - 0x68 + 0x14 0x20 0xFFFFFFFF - REGION8_ADDR_END - End address of region8 + REGION1_ADDR_END + End address of region1 0 32 read-write @@ -8472,69 +8579,69 @@ - REGION8_PMS_ATTR + REGION1_PMS_ATTR Region access authority attribute register - 0x6C + 0x18 0x20 - REGION8_R0_PMS_X + REGION1_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION8_R0_PMS_W + REGION1_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION8_R0_PMS_R + REGION1_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION8_R1_PMS_X + REGION1_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION8_R1_PMS_W + REGION1_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION8_R1_PMS_R + REGION1_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION8_R2_PMS_X + REGION1_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION8_R2_PMS_W + REGION1_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION8_R2_PMS_R + REGION1_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8543,14 +8650,14 @@ - REGION9_ADDR_START + REGION2_ADDR_START Region address register - 0x70 + 0x1C 0x20 - REGION9_ADDR_START - Start address of region9 + REGION2_ADDR_START + Start address of region2 0 32 read-write @@ -8558,15 +8665,15 @@ - REGION9_ADDR_END + REGION2_ADDR_END Region address register - 0x74 + 0x20 0x20 0xFFFFFFFF - REGION9_ADDR_END - End address of region9 + REGION2_ADDR_END + End address of region2 0 32 read-write @@ -8574,69 +8681,69 @@ - REGION9_PMS_ATTR + REGION2_PMS_ATTR Region access authority attribute register - 0x78 + 0x24 0x20 - REGION9_R0_PMS_X + REGION2_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION9_R0_PMS_W + REGION2_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION9_R0_PMS_R + REGION2_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION9_R1_PMS_X + REGION2_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION9_R1_PMS_W + REGION2_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION9_R1_PMS_R + REGION2_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION9_R2_PMS_X + REGION2_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION9_R2_PMS_W + REGION2_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION9_R2_PMS_R + REGION2_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8645,14 +8752,14 @@ - REGION10_ADDR_START + REGION3_ADDR_START Region address register - 0x7C + 0x28 0x20 - REGION10_ADDR_START - Start address of region10 + REGION3_ADDR_START + Start address of region3 0 32 read-write @@ -8660,15 +8767,15 @@ - REGION10_ADDR_END + REGION3_ADDR_END Region address register - 0x80 + 0x2C 0x20 0xFFFFFFFF - REGION10_ADDR_END - End address of region10 + REGION3_ADDR_END + End address of region3 0 32 read-write @@ -8676,69 +8783,69 @@ - REGION10_PMS_ATTR + REGION3_PMS_ATTR Region access authority attribute register - 0x84 + 0x30 0x20 - REGION10_R0_PMS_X + REGION3_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION10_R0_PMS_W + REGION3_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION10_R0_PMS_R + REGION3_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION10_R1_PMS_X + REGION3_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION10_R1_PMS_W + REGION3_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION10_R1_PMS_R + REGION3_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION10_R2_PMS_X + REGION3_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION10_R2_PMS_W + REGION3_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION10_R2_PMS_R + REGION3_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8747,14 +8854,14 @@ - REGION11_ADDR_START + REGION4_ADDR_START Region address register - 0x88 + 0x34 0x20 - REGION11_ADDR_START - Start address of region11 + REGION4_ADDR_START + Start address of region4 0 32 read-write @@ -8762,15 +8869,15 @@ - REGION11_ADDR_END + REGION4_ADDR_END Region address register - 0x8C + 0x38 0x20 0xFFFFFFFF - REGION11_ADDR_END - End address of region11 + REGION4_ADDR_END + End address of region4 0 32 read-write @@ -8778,69 +8885,69 @@ - REGION11_PMS_ATTR + REGION4_PMS_ATTR Region access authority attribute register - 0x90 + 0x3C 0x20 - REGION11_R0_PMS_X + REGION4_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION11_R0_PMS_W + REGION4_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION11_R0_PMS_R + REGION4_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION11_R1_PMS_X + REGION4_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION11_R1_PMS_W + REGION4_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION11_R1_PMS_R + REGION4_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION11_R2_PMS_X + REGION4_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION11_R2_PMS_W + REGION4_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION11_R2_PMS_R + REGION4_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8849,14 +8956,14 @@ - REGION12_ADDR_START + REGION5_ADDR_START Region address register - 0x94 + 0x40 0x20 - REGION12_ADDR_START - Start address of region12 + REGION5_ADDR_START + Start address of region5 0 32 read-write @@ -8864,15 +8971,15 @@ - REGION12_ADDR_END + REGION5_ADDR_END Region address register - 0x98 + 0x44 0x20 0xFFFFFFFF - REGION12_ADDR_END - End address of region12 + REGION5_ADDR_END + End address of region5 0 32 read-write @@ -8880,69 +8987,69 @@ - REGION12_PMS_ATTR + REGION5_PMS_ATTR Region access authority attribute register - 0x9C + 0x48 0x20 - REGION12_R0_PMS_X + REGION5_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION12_R0_PMS_W + REGION5_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION12_R0_PMS_R + REGION5_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION12_R1_PMS_X + REGION5_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION12_R1_PMS_W + REGION5_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION12_R1_PMS_R + REGION5_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION12_R2_PMS_X + REGION5_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION12_R2_PMS_W + REGION5_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION12_R2_PMS_R + REGION5_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -8951,14 +9058,14 @@ - REGION13_ADDR_START + REGION6_ADDR_START Region address register - 0xA0 + 0x4C 0x20 - REGION13_ADDR_START - Start address of region13 + REGION6_ADDR_START + Start address of region6 0 32 read-write @@ -8966,15 +9073,15 @@ - REGION13_ADDR_END + REGION6_ADDR_END Region address register - 0xA4 + 0x50 0x20 0xFFFFFFFF - REGION13_ADDR_END - End address of region13 + REGION6_ADDR_END + End address of region6 0 32 read-write @@ -8982,69 +9089,69 @@ - REGION13_PMS_ATTR + REGION6_PMS_ATTR Region access authority attribute register - 0xA8 + 0x54 0x20 - REGION13_R0_PMS_X + REGION6_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION13_R0_PMS_W + REGION6_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION13_R0_PMS_R + REGION6_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION13_R1_PMS_X + REGION6_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION13_R1_PMS_W + REGION6_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION13_R1_PMS_R + REGION6_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION13_R2_PMS_X + REGION6_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION13_R2_PMS_W + REGION6_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION13_R2_PMS_R + REGION6_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -9053,14 +9160,14 @@ - REGION14_ADDR_START + REGION7_ADDR_START Region address register - 0xAC + 0x58 0x20 - REGION14_ADDR_START - Start address of region14 + REGION7_ADDR_START + Start address of region7 0 32 read-write @@ -9068,15 +9175,15 @@ - REGION14_ADDR_END + REGION7_ADDR_END Region address register - 0xB0 + 0x5C 0x20 0xFFFFFFFF - REGION14_ADDR_END - End address of region14 + REGION7_ADDR_END + End address of region7 0 32 read-write @@ -9084,69 +9191,69 @@ - REGION14_PMS_ATTR + REGION7_PMS_ATTR Region access authority attribute register - 0xB4 + 0x60 0x20 - REGION14_R0_PMS_X + REGION7_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION14_R0_PMS_W + REGION7_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION14_R0_PMS_R + REGION7_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION14_R1_PMS_X + REGION7_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION14_R1_PMS_W + REGION7_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION14_R1_PMS_R + REGION7_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION14_R2_PMS_X + REGION7_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION14_R2_PMS_W + REGION7_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION14_R2_PMS_R + REGION7_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -9155,14 +9262,14 @@ - REGION15_ADDR_START + REGION8_ADDR_START Region address register - 0xB8 + 0x64 0x20 - REGION15_ADDR_START - Start address of region15 + REGION8_ADDR_START + Start address of region8 0 32 read-write @@ -9170,15 +9277,15 @@ - REGION15_ADDR_END + REGION8_ADDR_END Region address register - 0xBC + 0x68 0x20 0xFFFFFFFF - REGION15_ADDR_END - End address of region15 + REGION8_ADDR_END + End address of region8 0 32 read-write @@ -9186,69 +9293,69 @@ - REGION15_PMS_ATTR + REGION8_PMS_ATTR Region access authority attribute register - 0xC0 + 0x6C 0x20 - REGION15_R0_PMS_X + REGION8_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write - REGION15_R0_PMS_W + REGION8_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write - REGION15_R0_PMS_R + REGION8_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write - REGION15_R1_PMS_X + REGION8_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write - REGION15_R1_PMS_W + REGION8_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write - REGION15_R1_PMS_R + REGION8_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write - REGION15_R2_PMS_X + REGION8_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write - REGION15_R2_PMS_W + REGION8_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write - REGION15_R2_PMS_R + REGION8_R2_PMS_R Region read authority in REE_MODE2 10 1 @@ -9257,3451 +9364,5905 @@ - FUNC_CTRL - PMS function control register - 0xC4 + REGION9_ADDR_START + Region address register + 0x70 0x20 - 0x0000000F - M0_PMS_FUNC_EN - PMS M0 function enable + REGION9_ADDR_START + Start address of region9 + 0 + 32 + read-write + + + + + REGION9_ADDR_END + Region address register + 0x74 + 0x20 + 0xFFFFFFFF + + + REGION9_ADDR_END + End address of region9 + 0 + 32 + read-write + + + + + REGION9_PMS_ATTR + Region access authority attribute register + 0x78 + 0x20 + + + REGION9_R0_PMS_X + Region execute authority in REE_MODE0 0 1 read-write - M1_PMS_FUNC_EN - PMS M1 function enable + REGION9_R0_PMS_W + Region write authority in REE_MODE0 1 1 read-write - M2_PMS_FUNC_EN - PMS M2 function enable + REGION9_R0_PMS_R + Region read authority in REE_MODE0 2 1 read-write - M3_PMS_FUNC_EN - PMS M3 function enable - 3 + REGION9_R1_PMS_X + Region execute authority in REE_MODE1 + 4 1 read-write - - - - M0_STATUS - M0 status register - 0xC8 - 0x20 - - M0_EXCEPTION_STATUS - Exception status - 0 - 2 - read-only + REGION9_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write - - - - M0_STATUS_CLR - M0 status clear register - 0xCC - 0x20 - - M0_REGION_STATUS_CLR - Clear exception status - 0 + REGION9_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 - write-only + read-write - - - - M0_EXCEPTION_INFO0 - M0 exception_info0 register - 0xD0 - 0x20 - - M0_EXCEPTION_REGION - Exception region - 0 - 16 - read-only + REGION9_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write - M0_EXCEPTION_MODE - Exception mode - 16 - 2 - read-only + REGION9_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write - M0_EXCEPTION_ID - Exception id information - 18 - 5 - read-only + REGION9_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write - M0_EXCEPTION_INFO1 - M0 exception_info1 register - 0xD4 + REGION10_ADDR_START + Region address register + 0x7C 0x20 - M0_EXCEPTION_ADDR - Exception addr + REGION10_ADDR_START + Start address of region10 0 32 - read-only + read-write - M1_STATUS - M1 status register - 0xD8 + REGION10_ADDR_END + Region address register + 0x80 0x20 + 0xFFFFFFFF - M1_EXCEPTION_STATUS - Exception status + REGION10_ADDR_END + End address of region10 0 - 2 - read-only + 32 + read-write - M1_STATUS_CLR - M1 status clear register - 0xDC + REGION10_PMS_ATTR + Region access authority attribute register + 0x84 0x20 - M1_REGION_STATUS_CLR - Clear exception status + REGION10_R0_PMS_X + Region execute authority in REE_MODE0 0 1 - write-only + read-write - - - - M1_EXCEPTION_INFO0 - M1 exception_info0 register - 0xE0 - 0x20 - - M1_EXCEPTION_REGION - Exception region - 0 - 16 - read-only + REGION10_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write - M1_EXCEPTION_MODE - Exception mode - 16 - 2 - read-only + REGION10_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write - M1_EXCEPTION_ID - Exception id information - 18 - 5 - read-only + REGION10_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION10_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION10_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION10_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION10_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION10_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write - M1_EXCEPTION_INFO1 - M1 exception_info1 register - 0xE4 + REGION11_ADDR_START + Region address register + 0x88 0x20 - M1_EXCEPTION_ADDR - Exception addr + REGION11_ADDR_START + Start address of region11 0 32 - read-only + read-write - M2_STATUS - M2 status register - 0xE8 + REGION11_ADDR_END + Region address register + 0x8C 0x20 + 0xFFFFFFFF - M2_EXCEPTION_STATUS - Exception status + REGION11_ADDR_END + End address of region11 0 - 2 - read-only + 32 + read-write - M2_STATUS_CLR - M2 status clear register - 0xEC + REGION11_PMS_ATTR + Region access authority attribute register + 0x90 0x20 - M2_REGION_STATUS_CLR - Clear exception status + REGION11_R0_PMS_X + Region execute authority in REE_MODE0 0 1 - write-only + read-write - - - - M2_EXCEPTION_INFO0 - M2 exception_info0 register - 0xF0 - 0x20 - - M2_EXCEPTION_REGION - Exception region - 0 - 16 - read-only + REGION11_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write - M2_EXCEPTION_MODE - Exception mode - 16 - 2 - read-only + REGION11_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write - M2_EXCEPTION_ID - Exception id information - 18 - 5 - read-only + REGION11_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION11_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION11_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION11_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION11_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION11_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write - M2_EXCEPTION_INFO1 - M2 exception_info1 register - 0xF4 + REGION12_ADDR_START + Region address register + 0x94 0x20 - M2_EXCEPTION_ADDR - Exception addr + REGION12_ADDR_START + Start address of region12 0 32 - read-only + read-write - M3_STATUS - M3 status register - 0xF8 + REGION12_ADDR_END + Region address register + 0x98 0x20 + 0xFFFFFFFF - M3_EXCEPTION_STATUS - Exception status + REGION12_ADDR_END + End address of region12 0 - 2 - read-only + 32 + read-write - M3_STATUS_CLR - M3 status clear register - 0xFC + REGION12_PMS_ATTR + Region access authority attribute register + 0x9C 0x20 - M3_REGION_STATUS_CLR - Clear exception status + REGION12_R0_PMS_X + Region execute authority in REE_MODE0 0 1 - write-only + read-write - - - - M3_EXCEPTION_INFO0 - M3 exception_info0 register - 0x100 - 0x20 - - M3_EXCEPTION_REGION - Exception region - 0 - 16 - read-only + REGION12_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write - M3_EXCEPTION_MODE - Exception mode - 16 - 2 - read-only + REGION12_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write - M3_EXCEPTION_ID - Exception id information - 18 - 5 - read-only + REGION12_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write - - - - M3_EXCEPTION_INFO1 - M3 exception_info1 register - 0x104 - 0x20 - - M3_EXCEPTION_ADDR - Exception addr - 0 - 32 - read-only + REGION12_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write - - - - INT_EN - APM interrupt enable register - 0x108 - 0x20 - - M0_APM_INT_EN - APM M0 interrupt enable - 0 + REGION12_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - M1_APM_INT_EN - APM M1 interrupt enable - 1 + REGION12_R2_PMS_X + Region execute authority in REE_MODE2 + 8 1 read-write - M2_APM_INT_EN - APM M2 interrupt enable - 2 + REGION12_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - M3_APM_INT_EN - APM M3 interrupt enable - 3 + REGION12_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - CLOCK_GATE - clock gating register - 0x10C + REGION13_ADDR_START + Region address register + 0xA0 0x20 - 0x00000001 - CLK_EN - reg_clk_en + REGION13_ADDR_START + Start address of region13 0 - 1 + 32 read-write - DATE - Version register - 0x7FC + REGION13_ADDR_END + Region address register + 0xA4 0x20 - 0x02205240 + 0xFFFFFFFF - DATE - reg_date + REGION13_ADDR_END + End address of region13 0 - 28 + 32 read-write - - - - HP_SYS - High-Power System - HP_SYS - 0x60095000 - - 0x0 - 0x44 - registers - - - HP_PERI_TIMEOUT - 25 - - - EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL - EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register - 0x0 + REGION13_PMS_ATTR + Region access authority attribute register + 0xA8 0x20 - ENABLE_SPI_MANUAL_ENCRYPT - Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + REGION13_R0_PMS_X + Region execute authority in REE_MODE0 0 1 read-write - ENABLE_DOWNLOAD_DB_ENCRYPT - reserved + REGION13_R0_PMS_W + Region write authority in REE_MODE0 1 1 - read-only + read-write - ENABLE_DOWNLOAD_G0CB_DECRYPT - Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + REGION13_R0_PMS_R + Region read authority in REE_MODE0 2 1 read-write - ENABLE_DOWNLOAD_MANUAL_ENCRYPT - Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. - 3 + REGION13_R1_PMS_X + Region execute authority in REE_MODE1 + 4 1 read-write - - - - SRAM_USAGE_CONF - HP memory usage configuration register - 0x4 - 0x20 - - SRAM_USAGE - 0: cpu use hp-memory. 1: mac-dump accessing hp-memory. - 10 - 5 + REGION13_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 read-write - MAC_DUMP_ALLOC - reserved. - 20 - 5 + REGION13_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 read-write - CACHE_USAGE - reserved - 31 + REGION13_R2_PMS_X + Region execute authority in REE_MODE2 + 8 1 - read-only + read-write - - - - SEC_DPA_CONF - HP anti-DPA security configuration register - 0x8 - 0x20 - - SEC_DPA_LEVEL - 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. - 0 - 2 + REGION13_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 read-write - SEC_DPA_CFG_SEL - This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. - 2 + REGION13_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - CPU_PERI_TIMEOUT_CONF - CPU_PERI_TIMEOUT configuration register - 0xC + REGION14_ADDR_START + Region address register + 0xAC 0x20 - 0x0002FFFF - CPU_PERI_TIMEOUT_THRES - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + REGION14_ADDR_START + Start address of region14 0 - 16 - read-write - - - CPU_PERI_TIMEOUT_INT_CLEAR - Set this bit as 1 to clear timeout interrupt - 16 - 1 - write-only - - - CPU_PERI_TIMEOUT_PROTECT_EN - Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers - 17 - 1 + 32 read-write - CPU_PERI_TIMEOUT_ADDR - CPU_PERI_TIMEOUT_ADDR register - 0x10 + REGION14_ADDR_END + Region address register + 0xB0 0x20 + 0xFFFFFFFF - CPU_PERI_TIMEOUT_ADDR - Record the address information of abnormal access + REGION14_ADDR_END + End address of region14 0 32 - read-only + read-write - CPU_PERI_TIMEOUT_UID - CPU_PERI_TIMEOUT_UID register - 0x14 + REGION14_PMS_ATTR + Region access authority attribute register + 0xB4 0x20 - CPU_PERI_TIMEOUT_UID - Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + REGION14_R0_PMS_X + Region execute authority in REE_MODE0 0 - 7 - read-only + 1 + read-write - - - - HP_PERI_TIMEOUT_CONF - HP_PERI_TIMEOUT configuration register - 0x18 - 0x20 - 0x0002FFFF - - HP_PERI_TIMEOUT_THRES - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. - 0 - 16 + REGION14_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 read-write - HP_PERI_TIMEOUT_INT_CLEAR - Set this bit as 1 to clear timeout interrupt - 16 + REGION14_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 - write-only + read-write - HP_PERI_TIMEOUT_PROTECT_EN - Set this bit as 1 to enable timeout protection for accessing hp peripheral registers - 17 + REGION14_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION14_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION14_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION14_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION14_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION14_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - HP_PERI_TIMEOUT_ADDR - HP_PERI_TIMEOUT_ADDR register - 0x1C + REGION15_ADDR_START + Region address register + 0xB8 0x20 - HP_PERI_TIMEOUT_ADDR - Record the address information of abnormal access + REGION15_ADDR_START + Start address of region15 0 32 - read-only + read-write - HP_PERI_TIMEOUT_UID - HP_PERI_TIMEOUT_UID register - 0x20 + REGION15_ADDR_END + Region address register + 0xBC 0x20 + 0xFFFFFFFF - HP_PERI_TIMEOUT_UID - Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + REGION15_ADDR_END + End address of region15 0 - 7 - read-only + 32 + read-write - ROM_TABLE_LOCK - Rom-Table lock register - 0x24 + REGION15_PMS_ATTR + Region access authority attribute register + 0xC0 0x20 - ROM_TABLE_LOCK - XXXX + REGION15_R0_PMS_X + Region execute authority in REE_MODE0 0 1 read-write - - - - ROM_TABLE - Rom-Table register - 0x28 - 0x20 - - ROM_TABLE - XXXX - 0 - 32 + REGION15_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 read-write - - - - MEM_TEST_CONF - MEM_TEST configuration register - 0x2C - 0x20 - 0x00002228 - - HP_MEM_WPULSE - This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. - 0 - 3 + REGION15_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 read-write - HP_MEM_WA - This field controls hp system memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V. - 3 - 3 + REGION15_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - HP_MEM_RA - This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V. + REGION15_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION15_R1_PMS_R + Region read authority in REE_MODE1 6 - 2 + 1 read-write - HP_MEM_RM - This field controls hp system memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + REGION15_R2_PMS_X + Region execute authority in REE_MODE2 8 - 4 + 1 read-write - ROM_RM - This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V. - 12 - 4 + REGION15_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION15_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 read-write - RND_ECO - redcy eco register. - 0x3E0 + FUNC_CTRL + PMS function control register + 0xC4 0x20 + 0x0000000F - REDCY_ENA - Only reserved for ECO. + M0_PMS_FUNC_EN + PMS M0 function enable 0 1 read-write - REDCY_RESULT - Only reserved for ECO. + M1_PMS_FUNC_EN + PMS M1 function enable 1 1 - read-only + read-write - - - - RND_ECO_LOW - redcy eco low register. - 0x3E4 - 0x20 - - REDCY_LOW - Only reserved for ECO. - 0 - 32 + M2_PMS_FUNC_EN + PMS M2 function enable + 2 + 1 + read-write + + + M3_PMS_FUNC_EN + PMS M3 function enable + 3 + 1 read-write - RND_ECO_HIGH - redcy eco high register. - 0x3E8 + M0_STATUS + M0 status register + 0xC8 0x20 - 0xFFFFFFFF - REDCY_HIGH - Only reserved for ECO. + M0_EXCEPTION_STATUS + Exception status 0 - 32 - read-write + 2 + read-only - CLOCK_GATE - HP-SYSTEM clock gating configure register - 0x3F8 + M0_STATUS_CLR + M0 status clear register + 0xCC 0x20 - CLK_EN - Set this bit as 1 to force on clock gating. + M0_REGION_STATUS_CLR + Clear exception status 0 1 - read-write + write-only - DATE - Date register. - 0x3FC + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 0x20 - 0x02209271 - DATE - HP-SYSTEM date information/ HP-SYSTEM version information. + M0_EXCEPTION_REGION + Exception region 0 - 28 - read-write + 16 + read-only - - - - - - I2C0 - I2C (Inter-Integrated Circuit) Controller 0 - I2C - 0x60004000 + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M2_STATUS + M2 status register + 0xE8 + 0x20 + + + M2_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M2_STATUS_CLR + M2 status clear register + 0xEC + 0x20 + + + M2_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M2_EXCEPTION_INFO0 + M2 exception_info0 register + 0xF0 + 0x20 + + + M2_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M2_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M2_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M2_EXCEPTION_INFO1 + M2 exception_info1 register + 0xF4 + 0x20 + + + M2_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M3_STATUS + M3 status register + 0xF8 + 0x20 + + + M3_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M3_STATUS_CLR + M3 status clear register + 0xFC + 0x20 + + + M3_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M3_EXCEPTION_INFO0 + M3 exception_info0 register + 0x100 + 0x20 + + + M3_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M3_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M3_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M3_EXCEPTION_INFO1 + M3 exception_info1 register + 0x104 + 0x20 + + + M3_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0x108 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + M2_APM_INT_EN + APM M2 interrupt enable + 2 + 1 + read-write + + + M3_APM_INT_EN + APM M3 interrupt enable + 3 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0x10C + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0x7FC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + HP_SYS + High-Power System + HP_SYS + 0x60095000 0x0 - 0x90 + 0x44 registers - I2C_EXT0 - 39 + HP_PERI_TIMEOUT + 25 - SCL_LOW_PERIOD - Configures the low level width of the SCL -Clock + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register 0x0 0x20 - SCL_LOW_PERIOD - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + ENABLE_SPI_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. 0 - 9 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + reserved + 1 + 1 + read-only + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + 3 + 1 + read-write + + + + + SRAM_USAGE_CONF + HP memory usage configuration register + 0x4 + 0x20 + + + SRAM_USAGE + 0: cpu use hp-memory. 1: mac-dump accessing hp-memory. + 10 + 5 + read-write + + + MAC_DUMP_ALLOC + reserved. + 20 + 5 + read-write + + + CACHE_USAGE + reserved + 31 + 1 + read-only + + + + + SEC_DPA_CONF + HP anti-DPA security configuration register + 0x8 + 0x20 + + + SEC_DPA_LEVEL + 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + 0 + 2 + read-write + + + SEC_DPA_CFG_SEL + This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + 2 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_CONF + CPU_PERI_TIMEOUT configuration register + 0xC + 0x20 + 0x0002FFFF + + + CPU_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + CPU_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + CPU_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + 17 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_ADDR + CPU_PERI_TIMEOUT_ADDR register + 0x10 + 0x20 + + + CPU_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + CPU_PERI_TIMEOUT_UID + CPU_PERI_TIMEOUT_UID register + 0x14 + 0x20 + + + CPU_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + HP_PERI_TIMEOUT_CONF + HP_PERI_TIMEOUT configuration register + 0x18 + 0x20 + 0x0002FFFF + + + HP_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + HP_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + HP_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + 17 + 1 read-write - CTR - Transmission setting - 0x4 + HP_PERI_TIMEOUT_ADDR + HP_PERI_TIMEOUT_ADDR register + 0x1C + 0x20 + + + HP_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + HP_PERI_TIMEOUT_UID + HP_PERI_TIMEOUT_UID register + 0x20 + 0x20 + + + HP_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + ROM_TABLE_LOCK + Rom-Table lock register + 0x24 + 0x20 + + + ROM_TABLE_LOCK + XXXX + 0 + 1 + read-write + + + + + ROM_TABLE + Rom-Table register + 0x28 + 0x20 + + + ROM_TABLE + XXXX + 0 + 32 + read-write + + + + + MEM_TEST_CONF + MEM_TEST configuration register + 0x2C + 0x20 + 0x00002228 + + + HP_MEM_WPULSE + This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. + 0 + 3 + read-write + + + HP_MEM_WA + This field controls hp system memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V. + 3 + 3 + read-write + + + HP_MEM_RA + This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V. + 6 + 2 + read-write + + + HP_MEM_RM + This field controls hp system memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + 8 + 4 + read-write + + + ROM_RM + This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V. + 12 + 4 + read-write + + + + + RND_ECO + redcy eco register. + 0x3E0 + 0x20 + + + REDCY_ENA + Only reserved for ECO. + 0 + 1 + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only + + + + + RND_ECO_LOW + redcy eco low register. + 0x3E4 + 0x20 + + + REDCY_LOW + Only reserved for ECO. + 0 + 32 + read-write + + + + + RND_ECO_HIGH + redcy eco high register. + 0x3E8 + 0x20 + 0xFFFFFFFF + + + REDCY_HIGH + Only reserved for ECO. + 0 + 32 + read-write + + + + + CLOCK_GATE + HP-SYSTEM clock gating configure register + 0x3F8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02209271 + + + DATE + HP-SYSTEM date information/ HP-SYSTEM version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x60004000 + + 0x0 + 0x90 + registers + + + I2C_EXT0 + 39 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave, 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x60005000 + + I2C_EXT1 + 40 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x6000D000 + + 0x0 + 0x60 + registers + + + I2S0 + 31 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 0x20 - 0x00000208 + 0x00C0B600 - SDA_FORCE_OUT - 1: direct output, 0: open drain output. + RX_RESET + Set this bit to reset receiver 0 1 - read-write + write-only - SCL_FORCE_OUT - 1: direct output, 0: open drain output. + RX_FIFO_RESET + Set this bit to reset Rx AFIFO 1 1 - read-write + write-only - SAMPLE_SCL_LEVEL - This register is used to select the sample mode. -1: sample SDA data on the SCL low level. -0: sample SDA data on the SCL high level. + RX_START + Set this bit to start receiving data 2 1 read-write - RX_FULL_ACK_LEVEL - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + RX_SLAVE_MOD + Set this bit to enable slave receiver mode 3 1 read-write - MS_MODE - Set this bit to configure the module as an I2C Master. Clear this bit to configure the -module as an I2C Slave. + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 4 - 1 + 2 read-write - TRANS_START - Set this bit to start sending the data in txfifo. - 5 - 1 - write-only - - - TX_LSB_FIRST - This bit is used to control the sending mode for data needing to be sent. -1: send data from the least significant bit, -0: send data from the most significant bit. + RX_MONO + Set this bit to enable receiver in mono mode 6 1 read-write - RX_LSB_FIRST - This bit is used to control the storage mode for received data. -1: receive data from the least significant bit, -0: receive data from the most significant bit. + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - CLK_EN - Reserved + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - ARBITRATION_EN - This is the enable bit for arbitration_lost. + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write - FSM_RST - This register is used to reset the scl FMS. + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 1 - write-only + read-write - CONF_UPGATE - synchronization bit - 11 + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 1 - write-only + read-write - SLV_TX_AUTO_START_EN - This is the enable bit for slave to send data automatically - 12 + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 1 read-write - ADDR_10BIT_RW_CHECK_EN - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol - 13 + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 1 read-write - ADDR_BROADCASTING_EN - This is the enable bit to support the 7bit general call function. - 14 + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 1 read-write + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 + read-write + - SR - Describe I2C work status. - 0x8 + TX_CONF + I2S TX configure register + 0x24 0x20 - 0x0000C000 + 0x00C0F210 - RESP_REC - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + TX_RESET + Set this bit to reset transmitter 0 1 - read-only + write-only - SLAVE_RW - When in slave mode, 1: master reads from slave, 0: master writes to slave. + TX_FIFO_RESET + Set this bit to reset Tx AFIFO 1 1 - read-only + write-only - ARB_LOST - When the I2C controller loses control of SCL line, this register changes to 1. + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode 3 1 - read-only + read-write - BUS_BUSY - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 4 1 - read-only + read-write - SLAVE_ADDRESSED - When configured as an I2C Slave, and the address sent by the master is -equal to the address of the slave, then this bit will be of high level. + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 5 1 - read-only + read-write - RXFIFO_CNT - This field represents the amount of data needed to be sent. + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 - 6 - read-only + 1 + read-write - STRETCH_CAUSE - The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. - 14 + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 2 - read-only + read-write - TXFIFO_CNT - This field stores the amount of received data in RAM. + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 6 - read-only + read-write - SCL_MAIN_STATE_LAST - This field indicates the states of the I2C module state machine. -0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK - 24 + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 3 - read-only + read-write - SCL_STATE_LAST - This field indicates the states of the state machine used to produce SCL. -0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop - 28 - 3 - read-only + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 + 1 + read-write - TO - Setting time out control for receiving data. - 0xC + RX_CONF1 + I2S RX configure register 1 + 0x28 0x20 - 0x00000010 + 0x787BC000 - TIME_OUT_VALUE - This register is used to configure the timeout for receiving a data bit in APB -clock cycles. + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck 0 + 9 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 5 read-write - TIME_OUT_EN - This is the enable bit for time out control. - 5 + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 1 read-write - SLAVE_ADDR - Local slave address setting - 0x10 + TX_CLKM_CONF + I2S TX clock configure register + 0x34 0x20 + 0x00000002 - SLAVE_ADDR - When configured as an I2C Slave, this field is used to configure the slave address. + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. 0 - 15 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 read-write - ADDR_10BIT_EN - This field is used to enable the slave 10-bit addressing mode in master mode. - 31 + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 1 read-write - FIFO_ST - FIFO status register. - 0x14 + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 0x20 + 0x004AA004 - RXFIFO_RADDR - This is the offset address of the APB reading from rxfifo + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. 0 - 5 - read-only + 1 + read-write - RXFIFO_WADDR - This is the offset address of i2c module receiving data and writing to rxfifo. - 5 - 5 - read-only + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write - TXFIFO_RADDR - This is the offset address of i2c module reading from txfifo. - 10 - 5 - read-only + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write - TXFIFO_WADDR - This is the offset address of APB bus writing to txfifo. - 15 - 5 - read-only + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write - SLAVE_RW_POINT - The received data in I2C slave mode. - 22 - 8 - read-only + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write - - - - FIFO_CONF - FIFO configuration register. - 0x18 - 0x20 - 0x0000408B - - RXFIFO_WM_THRHD - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. - 0 - 5 + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 read-write - TXFIFO_WM_THRHD - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. - 5 - 5 + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 read-write - NONFIFO_EN - Set this bit to enable APB nonfifo access. - 10 + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 1 read-write - FIFO_ADDR_CFG_EN - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. - 11 + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 1 read-write - RX_FIFO_RST - Set this bit to reset rx-fifo. - 12 + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 1 read-write - TX_FIFO_RST - Set this bit to reset tx-fifo. - 13 + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 1 read-write - FIFO_PRT_EN - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. - 14 + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 1 read-write - DATA - Rx FIFO read data. - 0x1C + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 0x20 + 0x03F783C0 - FIFO_RDATA - The value of rx FIFO read data. + TX_PDM_FP + I2S TX PDM Fp 0 - 8 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 read-write - INT_RAW - Raw interrupt status - 0x20 + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 0x20 - 0x00000002 + 0x0000FFFF - RXFIFO_WM_INT_RAW - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 - read-only + read-write - TXFIFO_WM_INT_RAW - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 - read-only + read-write - RXFIFO_OVF_INT_RAW - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 - read-only + read-write - END_DETECT_INT_RAW - The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 - read-only + read-write - BYTE_TRANS_DONE_INT_RAW - The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 - read-only + read-write - ARBITRATION_LOST_INT_RAW - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 1 - read-only + read-write - MST_TXFIFO_UDF_INT_RAW - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. 6 1 - read-only + read-write - TRANS_COMPLETE_INT_RAW - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 - read-only + read-write - TIME_OUT_INT_RAW - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 - read-only + read-write - TRANS_START_INT_RAW - The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 - read-only + read-write - NACK_INT_RAW - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 1 - read-only + read-write - TXFIFO_OVF_INT_RAW - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. 11 1 - read-only + read-write - RXFIFO_UDF_INT_RAW - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 1 - read-only + read-write - SCL_ST_TO_INT_RAW - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. 13 1 - read-only + read-write - SCL_MAIN_ST_TO_INT_RAW - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. 14 1 - read-only + read-write - DET_START_INT_RAW - The raw interrupt bit for I2C_DET_START_INT interrupt. + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 - read-only + read-write - SLAVE_STRETCH_INT_RAW - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. 16 - 1 - read-only - - - GENERAL_CALL_INT_RAW - The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-only - - - SLAVE_ADDR_UNMATCH_INT_RAW - The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 - 1 - read-only + 4 + read-write - INT_CLR - Interrupt clear bits - 0x24 + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 0x20 + 0x0000FFFF - RXFIFO_WM_INT_CLR - Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 - write-only + read-write - TXFIFO_WM_INT_CLR - Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 - write-only + read-write - RXFIFO_OVF_INT_CLR - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 - write-only + read-write - END_DETECT_INT_CLR - Set this bit to clear the I2C_END_DETECT_INT interrupt. + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 - write-only + read-write - BYTE_TRANS_DONE_INT_CLR - Set this bit to clear the I2C_END_DETECT_INT interrupt. + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 - write-only + read-write - ARBITRATION_LOST_INT_CLR - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 1 - write-only + read-write - MST_TXFIFO_UDF_INT_CLR - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. 6 1 - write-only + read-write - TRANS_COMPLETE_INT_CLR - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 - write-only + read-write - TIME_OUT_INT_CLR - Set this bit to clear the I2C_TIME_OUT_INT interrupt. + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 - write-only + read-write - TRANS_START_INT_CLR - Set this bit to clear the I2C_TRANS_START_INT interrupt. + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 - write-only + read-write - NACK_INT_CLR - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 1 - write-only + read-write - TXFIFO_OVF_INT_CLR - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. 11 1 - write-only + read-write - RXFIFO_UDF_INT_CLR - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. 12 1 - write-only + read-write - SCL_ST_TO_INT_CLR - Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. 13 1 - write-only + read-write - SCL_MAIN_ST_TO_INT_CLR - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. 14 1 - write-only + read-write - DET_START_INT_CLR - Set this bit to clear I2C_DET_START_INT interrupt. + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. 15 1 - write-only + read-write - SLAVE_STRETCH_INT_CLR - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. 16 - 1 - write-only - - - GENERAL_CALL_INT_CLR - Set this bit to clear I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - write-only + 4 + read-write - SLAVE_ADDR_UNMATCH_INT_CLR - Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 1 - write-only + read-write - INT_ENA - Interrupt enable bits - 0x28 + RX_TIMING + I2S RX timing control register + 0x58 0x20 - RXFIFO_WM_INT_ENA - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 - 1 + 2 read-write - TXFIFO_WM_INT_ENA - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. - 1 - 1 + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 read-write - RXFIFO_OVF_INT_ENA - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 read-write - END_DETECT_INT_ENA - The interrupt enable bit for the I2C_END_DETECT_INT interrupt. - 3 - 1 + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 read-write - BYTE_TRANS_DONE_INT_ENA - The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 - 1 + 2 read-write - ARBITRATION_LOST_INT_ENA - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 read-write - MST_TXFIFO_UDF_INT_ENA - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 read-write - TRANS_COMPLETE_INT_ENA - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 read-write - TIME_OUT_INT_ENA - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. - 8 - 1 + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 read-write + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + - TRANS_START_INT_ENA - The interrupt enable bit for the I2C_TRANS_START_INT interrupt. - 9 - 1 + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 read-write - NACK_INT_ENA - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 read-write - TXFIFO_OVF_INT_ENA - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout 11 1 read-write + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + - RXFIFO_UDF_INT_ENA - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 read-write + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + - SCL_ST_TO_INT_ENA - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. - 13 - 1 + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 read-write + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + - SCL_MAIN_ST_TO_INT_ENA - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 1 - read-write + read-only + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + - DET_START_INT_ENA - The interrupt enable bit for I2C_DET_START_INT interrupt. - 15 - 1 + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 read-write - SLAVE_STRETCH_INT_ENA - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 read-write + + + + DATE + Version control register + 0x80 + 0x20 + 0x02208250 + - GENERAL_CALL_INT_ENA - The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. - 17 - 1 + DATE + I2S version control register + 0 + 28 read-write + + + + + + IEEE802154 + IEEE802154 Peripheral + IEEE802154 + 0x60047000 + + 0x0 + 0x17C + registers + + + + COMMAND + 0x0 + 0x20 + - SLAVE_ADDR_UNMATCH_INT_ENA - The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 - 1 + OPCODE + 0 + 8 read-write - INT_STATUS - Status of captured I2C communication events - 0x2C + CTRL_CFG + 0x4 0x20 - RXFIFO_WM_INT_ST - The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + HW_AUTO_ACK_TX_EN 0 1 - read-only + read-write - TXFIFO_WM_INT_ST - The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + HW_ENHANCE_ACK_TX_EN 1 1 - read-only - - - RXFIFO_OVF_INT_ST - The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only + read-write - END_DETECT_INT_ST - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + HW_AUTO_ACK_RX_EN 3 1 - read-only - - - BYTE_TRANS_DONE_INT_ST - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only + read-write - ARBITRATION_LOST_INT_ST - The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + DIS_IFS_CONTROL 5 1 - read-only + read-write - MST_TXFIFO_UDF_INT_ST - The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + PAN_COORDINATOR 6 1 - read-only + read-write - TRANS_COMPLETE_INT_ST - The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + PROMISCUOUS_MODE 7 1 - read-only + read-write - TIME_OUT_INT_ST - The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. - 8 + DIS_FRAME_VERSION_RSV_FILTER + 11 1 - read-only + read-write - TRANS_START_INT_ST - The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. - 9 + AUTOPEND_ENHANCE + 12 1 - read-only + read-write - NACK_INT_ST - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. - 10 + FILTER_ENHANCE + 14 1 - read-only + read-write - TXFIFO_OVF_INT_ST - The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. - 11 + COEX_ARB_DELAY + 16 + 5 + read-write + + + BIT_ORDER + 24 1 - read-only + read-write - RXFIFO_UDF_INT_ST - The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. - 12 + NO_RSS_TRK_ENB + 25 1 - read-only + read-write - SCL_ST_TO_INT_ST - The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. - 13 + FORCE_RX_ENB + 26 1 - read-only + read-write - SCL_MAIN_ST_TO_INT_ST - The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 + RX_DONE_TRIGGER_IDLE + 27 1 - read-only + read-write - DET_START_INT_ST - The masked interrupt status bit for I2C_DET_START_INT interrupt. - 15 + MAC_INF0_ENABLE + 28 1 - read-only + read-write - SLAVE_STRETCH_INT_ST - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. - 16 + MAC_INF1_ENABLE + 29 1 - read-only + read-write - GENERAL_CALL_INT_ST - The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. - 17 + MAC_INF2_ENABLE + 30 1 - read-only + read-write - SLAVE_ADDR_UNMATCH_INT_ST - The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 + MAC_INF3_ENABLE + 31 1 - read-only + read-write - SDA_HOLD - Configures the hold time after a negative SCL edge. - 0x30 + INF0_SHORT_ADDR + 0x8 0x20 - TIME - This register is used to configure the time to hold the data after the negative -edge of SCL, in I2C module clock cycles. + MAC_INF0_SHORT_ADDR 0 - 9 + 16 read-write - SDA_SAMPLE - Configures the sample time after a positive SCL edge. - 0x34 + INF0_PAN_ID + 0xC 0x20 - TIME - This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + MAC_INF0_PAN_ID 0 - 9 + 16 read-write - SCL_HIGH_PERIOD - Configures the high level width of SCL - 0x38 + INF0_EXTEND_ADDR0 + 0x10 0x20 - SCL_HIGH_PERIOD - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + MAC_INF0_EXTEND_ADDR0 0 - 9 - read-write - - - SCL_WAIT_HIGH_PERIOD - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. - 9 - 7 + 32 read-write - SCL_START_HOLD - Configures the delay between the SDA and SCL negative edge for a start condition - 0x40 + INF0_EXTEND_ADDR1 + 0x14 0x20 - 0x00000008 - TIME - This register is used to configure the time between the negative edge -of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + MAC_INF0_EXTEND_ADDR1 0 - 9 + 32 read-write - SCL_RSTART_SETUP - Configures the delay between the positive -edge of SCL and the negative edge of SDA - 0x44 + INF1_SHORT_ADDR + 0x18 0x20 - 0x00000008 - TIME - This register is used to configure the time between the positive -edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + MAC_INF1_SHORT_ADDR 0 - 9 + 16 read-write - SCL_STOP_HOLD - Configures the delay after the SCL clock -edge for a stop condition - 0x48 + INF1_PAN_ID + 0x1C 0x20 - 0x00000008 - TIME - This register is used to configure the delay after the STOP condition, -in I2C module clock cycles. + MAC_INF1_PAN_ID 0 - 9 + 16 read-write - SCL_STOP_SETUP - Configures the delay between the SDA and -SCL positive edge for a stop condition - 0x4C + INF1_EXTEND_ADDR0 + 0x20 0x20 - 0x00000008 - TIME - This register is used to configure the time between the positive edge -of SCL and the positive edge of SDA, in I2C module clock cycles. + MAC_INF1_EXTEND_ADDR0 0 - 9 + 32 read-write - FILTER_CFG - SCL and SDA filter configuration register - 0x50 + INF1_EXTEND_ADDR1 + 0x24 0x20 - 0x00000300 - SCL_FILTER_THRES - When a pulse on the SCL input has smaller width than this register value -in I2C module clock cycles, the I2C controller will ignore that pulse. + MAC_INF1_EXTEND_ADDR1 0 - 4 - read-write - - - SDA_FILTER_THRES - When a pulse on the SDA input has smaller width than this register value -in I2C module clock cycles, the I2C controller will ignore that pulse. - 4 - 4 - read-write - - - SCL_FILTER_EN - This is the filter enable bit for SCL. - 8 - 1 - read-write - - - SDA_FILTER_EN - This is the filter enable bit for SDA. - 9 - 1 + 32 read-write - CLK_CONF - I2C CLK configuration register - 0x54 + INF2_SHORT_ADDR + 0x28 0x20 - 0x00200000 - SCLK_DIV_NUM - the integral part of the fractional divisor for i2c module + MAC_INF2_SHORT_ADDR 0 - 8 - read-write - - - SCLK_DIV_A - the numerator of the fractional part of the fractional divisor for i2c module - 8 - 6 + 16 read-write + + + + INF2_PAN_ID + 0x2C + 0x20 + - SCLK_DIV_B - the denominator of the fractional part of the fractional divisor for i2c module - 14 - 6 + MAC_INF2_PAN_ID + 0 + 16 read-write + + + + INF2_EXTEND_ADDR0 + 0x30 + 0x20 + - SCLK_SEL - The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - 20 - 1 + MAC_INF2_EXTEND_ADDR0 + 0 + 32 read-write + + + + INF2_EXTEND_ADDR1 + 0x34 + 0x20 + - SCLK_ACTIVE - The clock switch for i2c module - 21 - 1 + MAC_INF2_EXTEND_ADDR1 + 0 + 32 read-write - 8 - 0x4 - 0-7 - COMD%s - I2C command register %s - 0x58 + INF3_SHORT_ADDR + 0x38 0x20 - COMMAND - This is the content of command 0. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. + MAC_INF3_SHORT_ADDR 0 - 14 + 16 read-write + + + + INF3_PAN_ID + 0x3C + 0x20 + - COMMAND_DONE - When command 0 is done in I2C Master mode, this bit changes to high -level. - 31 - 1 + MAC_INF3_PAN_ID + 0 + 16 read-write - SCL_ST_TIME_OUT - SCL status time out register - 0x78 + INF3_EXTEND_ADDR0 + 0x40 0x20 - 0x00000010 - SCL_ST_TO_I2C - The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + MAC_INF3_EXTEND_ADDR0 0 - 5 + 32 read-write - SCL_MAIN_ST_TIME_OUT - SCL main status time out register - 0x7C + INF3_EXTEND_ADDR1 + 0x44 0x20 - 0x00000010 - SCL_MAIN_ST_TO_I2C - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + MAC_INF3_EXTEND_ADDR1 0 - 5 + 32 read-write - SCL_SP_CONF - Power configuration register - 0x80 + CHANNEL + 0x48 0x20 - SCL_RST_SLV_EN - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + HOP 0 - 1 + 7 read-write + + + + TX_POWER + 0x4C + 0x20 + - SCL_RST_SLV_NUM - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. - 1 + TX_POWER + 0 5 read-write + + + + ED_SCAN_DURATION + 0x50 + 0x20 + - SCL_PD_EN - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. - 6 - 1 + ED_SCAN_DURATION + 0 + 24 read-write - SDA_PD_EN - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. - 7 - 1 + ED_SCAN_WAIT_DLY + 24 + 4 read-write - SCL_STRETCH_CONF - Set SCL stretch of I2C slave - 0x84 + ED_SCAN_CFG + 0x54 0x20 - STRETCH_PROTECT_NUM - Configure the period of I2C slave stretching SCL line. + CCA_ED_THRESHOLD 0 - 10 + 8 read-write - SLAVE_SCL_STRETCH_EN - The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. - 10 - 1 + ED_SAMPLE_MODE + 11 + 2 read-write - SLAVE_SCL_STRETCH_CLR - Set this bit to clear the I2C slave SCL stretch function. - 11 + DIS_ED_POWER_SEL + 13 1 - write-only + read-write - SLAVE_BYTE_ACK_CTL_EN - The enable bit for slave to control ACK level function. - 12 - 1 + CCA_MODE + 14 + 2 + read-write + + + ED_RSS + 16 + 8 read-write - SLAVE_BYTE_ACK_LVL - Set the ACK level when slave controlling ACK level function enables. - 13 + CCA_BUSY + 24 1 read-write - DATE - Version register - 0xF8 + IFS + 0x58 0x20 - 0x02201172 - DATE - This is the the version register. + SIFS 0 - 32 + 8 + read-write + + + LIFS + 16 + 10 read-write - TXFIFO_START_ADDR - I2C TXFIFO base address register - 0x100 + ACK_TIMEOUT + 0x5C 0x20 - TXFIFO_START_ADDR - This is the I2C txfifo first address. + ACK_TIMEOUT 0 - 32 - read-only + 16 + read-write - RXFIFO_START_ADDR - I2C RXFIFO base address register - 0x180 + EVENT_EN + 0x60 0x20 - RXFIFO_START_ADDR - This is the I2C rxfifo first address. + EVENT_EN 0 - 32 - read-only + 13 + read-write - - - - I2C1 - I2C (Inter-Integrated Circuit) Controller 1 - 0x60005000 - - I2C_EXT1 - 40 - - - - I2S0 - I2S (Inter-IC Sound) Controller 0 - I2S - 0x6000D000 - - 0x0 - 0x60 - registers - - - I2S1 - 31 - - - INT_RAW - I2S interrupt raw register, valid in level. - 0xC + EVENT_STATUS + 0x64 0x20 - RX_DONE_INT_RAW - The raw interrupt status bit for the i2s_rx_done_int interrupt + EVENT_STATUS 0 - 1 - read-only - - - TX_DONE_INT_RAW - The raw interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only - - - RX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-only - - - TX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only + 13 + read-write - INT_ST - I2S interrupt status register. - 0x10 + RX_ABORT_INTR_CTRL + 0x68 0x20 - RX_DONE_INT_ST - The masked interrupt status bit for the i2s_rx_done_int interrupt + RX_ABORT_INTR_CTRL 0 - 1 - read-only - - - TX_DONE_INT_ST - The masked interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only + 31 + read-write + + + + ACK_FRAME_PENDING_EN + 0x6C + 0x20 + - RX_HUNG_INT_ST - The masked interrupt status bit for the i2s_rx_hung_int interrupt - 2 + ACK_FRAME_PENDING_EN + 0 1 - read-only + read-write - TX_HUNG_INT_ST - The masked interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only + ACK_TX_ACK_TIMEOUT + 16 + 16 + read-write - INT_ENA - I2S interrupt enable register. - 0x14 + COEX_PTI + 0x70 0x20 - RX_DONE_INT_ENA - The interrupt enable bit for the i2s_rx_done_int interrupt + COEX_PTI 0 - 1 + 4 read-write - TX_DONE_INT_ENA - The interrupt enable bit for the i2s_tx_done_int interrupt - 1 - 1 + COEX_ACK_PTI + 4 + 4 read-write - RX_HUNG_INT_ENA - The interrupt enable bit for the i2s_rx_hung_int interrupt - 2 + CLOSE_RF_SEL + 8 1 read-write + + + + CORE_DUMMY_DATA + 0x74 + 0x20 + - TX_HUNG_INT_ENA - The interrupt enable bit for the i2s_tx_hung_int interrupt - 3 - 1 + CORE_DUMMY_DATA + 0 + 32 read-write - INT_CLR - I2S interrupt clear register. - 0x18 + TX_ABORT_INTERRUPT_CONTROL + 0x78 0x20 - RX_DONE_INT_CLR - Set this bit to clear the i2s_rx_done_int interrupt + TX_ABORT_INTERRUPT_CONTROL 0 - 1 - write-only - - - TX_DONE_INT_CLR - Set this bit to clear the i2s_tx_done_int interrupt - 1 - 1 - write-only - - - RX_HUNG_INT_CLR - Set this bit to clear the i2s_rx_hung_int interrupt - 2 - 1 - write-only - - - TX_HUNG_INT_CLR - Set this bit to clear the i2s_tx_hung_int interrupt - 3 - 1 - write-only + 31 + read-write - RX_CONF - I2S RX configure register - 0x20 + ENHANCE_ACK_CFG + 0x7C 0x20 - 0x00C0B600 - RX_RESET - Set this bit to reset receiver + TX_ENH_ACK_GENERATE_DONE_NOTIFY 0 - 1 - write-only - - - RX_FIFO_RESET - Set this bit to reset Rx AFIFO - 1 - 1 - write-only - - - RX_START - Set this bit to start receiving data - 2 - 1 + 32 read-write + + + + RX_STATUS + 0x80 + 0x20 + - RX_SLAVE_MOD - Set this bit to enable slave receiver mode - 3 - 1 + FILTER_FAIL_STATUS + 0 + 4 read-write - RX_STOP_MODE - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + RX_ABORT_STATUS 4 - 2 - read-write - - - RX_MONO - Set this bit to enable receiver in mono mode - 6 - 1 + 5 read-write - RX_BIG_ENDIAN - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 + RX_STATE + 16 + 3 read-write - RX_UPDATE - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. - 8 + PREAMBLE_MATCH + 20 1 read-write - RX_MONO_FST_VLD - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. - 9 + SFD_MATCH + 21 1 read-write + + + + TX_STATUS + 0x84 + 0x20 + - RX_PCM_CONF - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 + TX_STATE + 0 + 4 read-write - RX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for received data. - 12 - 1 + TX_ABORT_STATUS + 4 + 5 read-write - RX_MSB_SHIFT - Set this bit to enable receiver in Phillips standard mode - 13 - 1 + TX_SEC_ERROR_CODE + 16 + 4 read-write + + + + TXRX_STATUS + 0x88 + 0x20 + - RX_LEFT_ALIGN - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. - 15 - 1 + TXRX_STATE + 0 + 4 read-write - RX_24_FILL_EN - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. - 16 + TX_PROC + 8 1 read-write - RX_WS_IDLE_POL - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. - 17 + RX_PROC + 9 1 read-write - RX_BIT_ORDER - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. - 18 + ED_PROC + 10 1 read-write - RX_TDM_EN - 1: Enable I2S TDM Rx mode . 0: Disable. - 19 + ED_TRIGGER_TX_PROC + 11 1 read-write - RX_PDM_EN - 1: Enable I2S PDM Rx mode . 0: Disable. - 20 - 1 + RF_CTRL_STATE + 16 + 4 read-write + + + + TX_CCM_SCHEDULE_STATUS + 0x8C + 0x20 + - RX_BCK_DIV_NUM - Bit clock configuration bits in receiver mode. - 21 - 6 + TX_CCM_SCHEDULE_STATUS + 0 + 31 read-write - TX_CONF - I2S TX configure register - 0x24 + CORE_GCK_CFG + 0x90 0x20 - 0x00C0F210 - TX_RESET - Set this bit to reset transmitter + DIS_PKT_GCK 0 1 - write-only - - - TX_FIFO_RESET - Set this bit to reset Tx AFIFO - 1 - 1 - write-only - - - TX_START - Set this bit to start transmitting data - 2 - 1 read-write - TX_SLAVE_MOD - Set this bit to enable slave transmitter mode - 3 + DIS_CTRL_GCK + 1 1 read-write + + + + TEST_CONTROL + 0x94 + 0x20 + - TX_STOP_EN - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy - 4 + WRONG_CRC + 0 1 read-write + + + + DTM_CONFIG + 0x98 + 0x20 + - TX_CHAN_EQUAL - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - 5 - 1 + DTMCH_TX_LENGTH + 0 + 8 read-write - TX_MONO - Set this bit to enable transmitter in mono mode - 6 - 1 + DTM_TX_PLD_TYPE + 8 + 4 read-write - TX_BIG_ENDIAN - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 + DTM_HOP_FREQ + 16 + 6 read-write - TX_UPDATE - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. - 8 + DTM_CONTRX_EN + 24 1 read-write - TX_MONO_FST_VLD - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. - 9 + DTM_ON + 25 1 read-write + + + + DTM_TX_PKT_CONFIG + 0x9C + 0x20 + - TX_PCM_CONF - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - TX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for transmitted data. - 12 - 1 + DTM_TX_PKT_THRESHOLD + 0 + 16 read-write + + + + DTM_PKT_COUNTER + 0xA0 + 0x20 + - TX_MSB_SHIFT - Set this bit to enable transmitter in Phillips standard mode - 13 - 1 + DTM_TXRX_PKT_COUNT + 0 + 16 read-write - TX_BCK_NO_DLY - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. - 14 - 1 + DTM_CRC_ERR_PKT_COUNT + 16 + 16 read-write + + + + RX_LENGTH + 0xA4 + 0x20 + - TX_LEFT_ALIGN - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - 15 - 1 + RX_LENGTH + 0 + 7 read-write + + + + TIME0_THRESHOLD + 0xA8 + 0x20 + - TX_24_FILL_EN - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - 16 - 1 + TIMER0_THRESHOLD + 0 + 32 read-write + + + + TIME0_VALUE + 0xAC + 0x20 + - TX_WS_IDLE_POL - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. - 17 - 1 + TIMER0_VALUE + 0 + 32 read-write + + + + TIME1_THRESHOLD + 0xB0 + 0x20 + - TX_BIT_ORDER - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. - 18 - 1 + TIMER1_THRESHOLD + 0 + 32 read-write + + + + TIME1_VALUE + 0xB4 + 0x20 + - TX_TDM_EN - 1: Enable I2S TDM Tx mode . 0: Disable. - 19 - 1 + TIMER1_VALUE + 0 + 32 read-write + + + + CLK_COUNTER_MATCH_VAL + 0xB8 + 0x20 + - TX_PDM_EN - 1: Enable I2S PDM Tx mode . 0: Disable. - 20 - 1 + CLK_COUNT_MATCH_VAL + 0 + 16 read-write + + + + CLK_COUNTER + 0xBC + 0x20 + - TX_BCK_DIV_NUM - Bit clock configuration bits in transmitter mode. - 21 - 6 + CLK_625US_CNT + 0 + 16 read-write + + + + IFS_COUNTER + 0xC0 + 0x20 + - TX_CHAN_MOD - I2S transmitter channel mode configuration bits. - 27 - 3 + IFS_COUNTER + 0 + 10 read-write - SIG_LOOPBACK - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. - 30 + EN + 16 1 read-write - RX_CONF1 - I2S RX configure register 1 - 0x28 + SFD_WAIT_SYMBOL + 0xC4 0x20 - 0x787BC000 - RX_TDM_WS_WIDTH - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + NUM 0 - 9 + 4 read-write + + + + TXRX_PATH_DELAY + 0xC8 + 0x20 + - RX_BITS_MOD - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 + TX_PATH_DELAY + 0 + 6 read-write - RX_HALF_SAMPLE_BITS - I2S Rx half sample bits -1. - 19 - 8 + RX_PATH_DELAY + 16 + 6 read-write + + + + BB_CLK + 0xCC + 0x20 + - RX_TDM_CHAN_BITS - The Rx bit number for each channel minus 1in TDM mode. - 27 + FREQ_MINUS_1 + 0 5 read-write - TX_CONF1 - I2S TX configure register 1 - 0x2C + TXDMA_ADDR + 0xD0 0x20 - 0x787BC000 - TX_TDM_WS_WIDTH - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + TXDMA_ADDR 0 - 9 + 32 read-write + + + + TXDMA_CTRL_STATE + 0xD4 + 0x20 + - TX_BITS_MOD - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 + TXDMA_WATER_LEVEL + 0 + 3 read-write - TX_HALF_SAMPLE_BITS - I2S Tx half sample bits -1. - 19 - 8 + TXDMA_FILL_ENTRY + 4 + 3 read-write - TX_TDM_CHAN_BITS - The Tx bit number for each channel minus 1in TDM mode. - 27 + TXDMA_STATE + 16 5 read-write + + TXDMA_FETCH_BYTE_CNT + 24 + 7 + read-write + - RX_CLKM_CONF - I2S RX clock configure register - 0x30 + TXDMA_ERR + 0xD8 0x20 - 0x00000002 - RX_CLKM_DIV_NUM - Integral I2S clock divider value + TXDMA_ERR 0 - 8 - read-write - - - RX_CLK_ACTIVE - I2S Rx module clock enable signal. - 26 - 1 - read-write - - - RX_CLK_SEL - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. - 27 - 2 + 4 read-write + + + + RXDMA_ADDR + 0xE0 + 0x20 + - MCLK_SEL - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. - 29 - 1 + RXDMA_ADDR + 0 + 32 read-write - TX_CLKM_CONF - I2S TX clock configure register - 0x34 + RXDMA_CTRL_STATE + 0xE4 0x20 - 0x00000002 - TX_CLKM_DIV_NUM - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + RXDMA_WATER_LEVEL 0 - 8 + 3 read-write - TX_CLK_ACTIVE - I2S Tx module clock enable signal. - 26 - 1 + RXDMA_STATE + 16 + 5 read-write - TX_CLK_SEL - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. - 27 - 2 + RXDMA_APPEND_LQI_OFFSET + 24 + 1 read-write - CLK_EN - Set this bit to enable clk gate - 29 + RXDMA_APPEND_FREQ_OFFSET + 25 1 read-write - RX_CLKM_DIV_CONF - I2S RX module clock divider configure register - 0x38 + RXDMA_ERR + 0xE8 0x20 - 0x00000200 - RX_CLKM_DIV_Z - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + RXDMA_ERR 0 - 9 + 4 read-write + + + + DMA_GCK_CFG + 0xF0 + 0x20 + - RX_CLKM_DIV_Y - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). - 9 - 9 + DMA_GCK_CFG + 0 + 1 read-write + + + + DMA_DUMMY + 0xF4 + 0x20 + - RX_CLKM_DIV_X - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. - 18 - 9 + DATA + 0 + 32 read-write + + + + PAON_DELAY + 0x100 + 0x20 + - RX_CLKM_DIV_YN1 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. - 27 - 1 + PAON_DELAY + 0 + 10 read-write - TX_CLKM_DIV_CONF - I2S TX module clock divider configure register - 0x3C + TXON_DELAY + 0x104 0x20 - 0x00000200 - TX_CLKM_DIV_Z - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + TXON_DELAY 0 - 9 + 10 read-write + + + + TXEN_STOP_DELAY + 0x108 + 0x20 + - TX_CLKM_DIV_Y - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). - 9 - 9 + TXEN_STOP_DLY + 0 + 6 read-write + + + + TXOFF_DELAY + 0x10C + 0x20 + - TX_CLKM_DIV_X - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. - 18 - 9 + TXOFF_DELAY + 0 + 6 read-write + + + + RXON_DELAY + 0x110 + 0x20 + - TX_CLKM_DIV_YN1 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. - 27 - 1 + RXON_DELAY + 0 + 11 read-write - TX_PCM2PDM_CONF - I2S TX PCM2PDM configuration register - 0x40 + TXRX_SWITCH_DELAY + 0x114 0x20 - 0x004AA004 - TX_PDM_HP_BYPASS - I2S TX PDM bypass hp filter or not. The option has been removed. + TXRX_SWITCH_DELAY 0 - 1 + 10 + read-write + + + + + CONT_RX_DELAY + 0x118 + 0x20 + + + CONT_RX_DELAY + 0 + 6 read-write + + + + DCDC_CTRL + 0x11C + 0x20 + - TX_PDM_SINC_OSR2 - I2S TX PDM OSR2 value - 1 - 4 + DCDC_PRE_UP_DELAY + 0 + 8 read-write - TX_PDM_PRESCALE - I2S TX PDM prescale for sigmadelta - 5 + DCDC_DOWN_DELAY + 8 8 read-write - TX_PDM_HP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 13 - 2 + EN + 16 + 1 read-write - TX_PDM_LP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 15 - 2 + TX_DCDC_UP + 31 + 1 read-write + + + + DEBUG_CTRL + 0x120 + 0x20 + - TX_PDM_SINC_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 17 - 2 + DEBUG_SIGNAL_SEL + 0 + 3 read-write - TX_PDM_SIGMADELTA_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 19 - 2 + DEBUG_TRIGGER_STATE_SELECT + 8 + 4 read-write - TX_PDM_SIGMADELTA_DITHER2 - I2S TX PDM sigmadelta dither2 value - 21 - 1 + DEBUG_SER_DEBUG_SEL + 12 + 4 read-write - TX_PDM_SIGMADELTA_DITHER - I2S TX PDM sigmadelta dither value - 22 - 1 + DEBUG_TRIGGER_STATE_MATCH_VALUE + 16 + 5 read-write - TX_PDM_DAC_2OUT_EN - I2S TX PDM dac mode enable - 23 + DEBUG_TRIGGER_PULSE_SELECT + 24 + 3 + read-write + + + DEBUG_STATE_MATCH_DUMP_EN + 30 1 read-write - TX_PDM_DAC_MODE_EN - I2S TX PDM dac 2channel enable - 24 + DEBUG_TRIGGER_DUMP_EN + 31 1 read-write + + + + SEC_CTRL + 0x128 + 0x20 + - PCM2PDM_CONV_EN - I2S TX PDM Converter enable - 25 + SEC_EN + 0 1 read-write + + SEC_PAYLOAD_OFFSET + 8 + 7 + read-write + - TX_PCM2PDM_CONF1 - I2S TX PCM2PDM configuration register - 0x44 + SEC_EXTEND_ADDRESS0 + 0x12C 0x20 - 0x03F783C0 - TX_PDM_FP - I2S TX PDM Fp + SEC_EXTEND_ADDRESS0 0 - 10 + 32 read-write + + + + SEC_EXTEND_ADDRESS1 + 0x130 + 0x20 + - TX_PDM_FS - I2S TX PDM Fs - 10 - 10 + SEC_EXTEND_ADDRESS1 + 0 + 32 read-write + + + + SEC_KEY0 + 0x134 + 0x20 + - TX_IIR_HP_MULT12_5 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) - 20 - 3 + SEC_KEY0 + 0 + 32 read-write + + + + SEC_KEY1 + 0x138 + 0x20 + - TX_IIR_HP_MULT12_0 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) - 23 - 3 + SEC_KEY1 + 0 + 32 read-write - RX_TDM_CTRL - I2S TX TDM mode control register - 0x50 + SEC_KEY2 + 0x13C 0x20 - 0x0000FFFF - RX_TDM_PDM_CHAN0_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + SEC_KEY2 0 - 1 + 32 read-write + + + + SEC_KEY3 + 0x140 + 0x20 + - RX_TDM_PDM_CHAN1_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. - 1 - 1 + SEC_KEY3 + 0 + 32 read-write + + + + SFD_TIMEOUT_CNT + 0x144 + 0x20 + - RX_TDM_PDM_CHAN2_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. - 2 - 1 + SFD_TIMEOUT_CNT + 0 + 16 read-write + + + + CRC_ERROR_CNT + 0x148 + 0x20 + - RX_TDM_PDM_CHAN3_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. - 3 - 1 + CRC_ERROR_CNT + 0 + 16 read-write + + + + ED_ABORT_CNT + 0x14C + 0x20 + - RX_TDM_PDM_CHAN4_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. - 4 - 1 + ED_ABORT_CNT + 0 + 16 read-write + + + + CCA_FAIL_CNT + 0x150 + 0x20 + - RX_TDM_PDM_CHAN5_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. - 5 - 1 + CCA_FAIL_CNT + 0 + 16 read-write + + + + RX_FILTER_FAIL_CNT + 0x154 + 0x20 + - RX_TDM_PDM_CHAN6_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. - 6 - 1 + RX_FILTER_FAIL_CNT + 0 + 16 read-write + + + + NO_RSS_DETECT_CNT + 0x158 + 0x20 + - RX_TDM_PDM_CHAN7_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. - 7 - 1 + NO_RSS_DETECT_CNT + 0 + 16 read-write + + + + RX_ABORT_COEX_CNT + 0x15C + 0x20 + - RX_TDM_CHAN8_EN - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. - 8 - 1 + RX_ABORT_COEX_CNT + 0 + 16 read-write + + + + RX_RESTART_CNT + 0x160 + 0x20 + - RX_TDM_CHAN9_EN - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. - 9 - 1 + RX_RESTART_CNT + 0 + 16 read-write + + + + TX_ACK_ABORT_COEX_CNT + 0x164 + 0x20 + - RX_TDM_CHAN10_EN - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. - 10 - 1 + TX_ACK_ABORT_COEX_CNT + 0 + 16 read-write + + + + ED_SCAN_COEX_CNT + 0x168 + 0x20 + - RX_TDM_CHAN11_EN - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. - 11 - 1 + ED_SCAN_COEX_CNT + 0 + 16 read-write + + + + RX_ACK_ABORT_COEX_CNT + 0x16C + 0x20 + - RX_TDM_CHAN12_EN - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. - 12 - 1 + RX_ACK_ABORT_COEX_CNT + 0 + 16 read-write + + + + RX_ACK_TIMEOUT_CNT + 0x170 + 0x20 + - RX_TDM_CHAN13_EN - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. - 13 - 1 + RX_ACK_TIMEOUT_CNT + 0 + 16 read-write + + + + TX_BREAK_COEX_CNT + 0x174 + 0x20 + - RX_TDM_CHAN14_EN - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. - 14 - 1 + TX_BREAK_COEX_CNT + 0 + 16 read-write + + + + TX_SECURITY_ERROR_CNT + 0x178 + 0x20 + - RX_TDM_CHAN15_EN - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. - 15 - 1 + TX_SECURITY_ERROR_CNT + 0 + 16 read-write + + + + CCA_BUSY_CNT + 0x17C + 0x20 + - RX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 + CCA_BUSY_CNT + 0 + 16 read-write - TX_TDM_CTRL - I2S TX TDM mode control register - 0x54 + ERROR_CNT_CLEAR + 0x180 0x20 - 0x0000FFFF - TX_TDM_CHAN0_EN - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + CCA_BUSY_CNT_CLEAR 0 1 read-write - TX_TDM_CHAN1_EN - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + TX_SECURITY_ERROR_CNT_CLEAR 1 1 read-write - TX_TDM_CHAN2_EN - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + TX_BREAK_COEX_CNT_CLEAR 2 1 read-write - TX_TDM_CHAN3_EN - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + RX_ACK_TIMEOUT_CNT_CLEAR 3 1 read-write - TX_TDM_CHAN4_EN - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + RX_ACK_ABORT_COEX_CNT_CLEAR 4 1 read-write - TX_TDM_CHAN5_EN - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + ED_SCAN_COEX_CNT_CLEAR 5 1 read-write - TX_TDM_CHAN6_EN - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + TX_ACK_ABORT_COEX_CNT_CLEAR 6 1 read-write - TX_TDM_CHAN7_EN - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + RX_RESTART_CNT_CLEAR 7 1 read-write - TX_TDM_CHAN8_EN - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + RX_ABORT_COEX_CNT_CLEAR 8 1 read-write - TX_TDM_CHAN9_EN - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + NO_RSS_DETECT_CNT_CLEAR 9 1 read-write - TX_TDM_CHAN10_EN - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + RX_FILTER_FAIL_CNT_CLEAR 10 1 read-write - TX_TDM_CHAN11_EN - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + CCA_FAIL_CNT_CLEAR 11 1 read-write - TX_TDM_CHAN12_EN - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + ED_ABORT_CNT_CLEAR 12 1 read-write - TX_TDM_CHAN13_EN - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + CRC_ERROR_CNT_CLEAR 13 1 read-write - TX_TDM_CHAN14_EN - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + SFD_TIMEOUT_CNT_CLEAR 14 1 read-write - - TX_TDM_CHAN15_EN - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. - 15 - 1 - read-write - - - TX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - TX_TDM_SKIP_MSK_EN - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. - 20 - 1 - read-write - - - - - RX_TIMING - I2S RX timing control register - 0x58 - 0x20 - - - RX_SD_IN_DM - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - RX_WS_OUT_DM - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - RX_BCK_OUT_DM - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - RX_WS_IN_DM - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - RX_BCK_IN_DM - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - TX_TIMING - I2S TX timing control register - 0x5C + DEBUG_SEL_CFG0 + 0x184 0x20 - TX_SD_OUT_DM - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + DEBUG_FIELD0_SEL 0 - 2 + 5 read-write - TX_SD1_OUT_DM - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 4 - 2 + DEBUG_FIELD1_SEL + 8 + 5 read-write - TX_WS_OUT_DM - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + DEBUG_FIELD2_SEL 16 - 2 - read-write - - - TX_BCK_OUT_DM - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 + 5 read-write - TX_WS_IN_DM - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + DEBUG_FIELD3_SEL 24 - 2 - read-write - - - TX_BCK_IN_DM - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 + 5 read-write - LC_HUNG_CONF - I2S HUNG configure register. - 0x60 + DEBUG_SEL_CFG1 + 0x188 0x20 - 0x00000810 - LC_FIFO_TIMEOUT - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + DEBUG_FIELD4_SEL 0 - 8 + 5 read-write - LC_FIFO_TIMEOUT_SHIFT - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + DEBUG_FIELD5_SEL 8 - 3 + 5 read-write - LC_FIFO_TIMEOUT_ENA - The enable bit for FIFO timeout - 11 - 1 + DEBUG_FIELD6_SEL + 16 + 5 read-write - - - - RXEOF_NUM - I2S RX data number control register. - 0x64 - 0x20 - 0x00000040 - - RX_EOF_NUM - The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. - 0 - 12 + DEBUG_FIELD7_SEL + 24 + 5 read-write - CONF_SIGLE_DATA - I2S signal data register - 0x68 + MAC_DATE + 0x18C 0x20 - SINGLE_DATA - The configured constant channel data to be sent out. + MAC_DATE 0 32 read-write - - STATE - I2S TX status register - 0x6C - 0x20 - 0x00000001 - - - TX_IDLE - 1: i2s_tx is idle state. 0: i2s_tx is working. - 0 - 1 - read-only - - - - - ETM_CONF - I2S ETM configure register - 0x70 - 0x20 - 0x00010040 - - - ETM_TX_SEND_WORD_NUM - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. - 0 - 10 - read-write - - - ETM_RX_RECEIVE_WORD_NUM - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. - 10 - 10 - read-write - - - - - DATE - Version control register - 0x80 - 0x20 - 0x02208250 - - - DATE - I2S version control register - 0 - 28 - read-write - - - @@ -14745,7 +17306,7 @@ level. 0x20 - TIMER_SEL_CH + TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 @@ -14754,28 +17315,28 @@ level. read-write - SIG_OUT_EN_CH + SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write - IDLE_LV_CH + IDLE_LV This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write - PARA_UP_CH + PARA_UP This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only - OVF_NUM_CH + OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. @@ -14784,14 +17345,14 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows read-write - OVF_CNT_EN_CH + OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write - OVF_CNT_RESET_CH + OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 @@ -14808,7 +17369,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - HPOINT_CH + HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 20 @@ -14825,7 +17386,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - DUTY_CH + DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. @@ -14844,7 +17405,7 @@ The output value turns to low when the selected timers has reached the Lpoint.0x20 - DUTY_START_CH + DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 @@ -14879,14 +17440,14 @@ The output value turns to low when the selected timers has reached the Lpoint.0x01000000 - TIMER_DUTY_RES + DUTY_RES This register is used to control the range of the counter in timer %s. 0 5 read-write - CLK_DIV_TIMER + CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. @@ -14895,21 +17456,21 @@ The least significant eight bits represent the fractional part. read-write - TIMER_PAUSE + PAUSE This bit is used to suspend the counter in timer %s. 23 1 read-write - TIMER_RST + RST This bit is used to reset timer %s. The counter will show 0 after reset. 24 1 read-write - TICK_SEL_TIMER + TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK @@ -14918,7 +17479,7 @@ The least significant eight bits represent the fractional part. read-write - TIMER_PARA_UP + PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 26 1 @@ -17643,7 +20204,7 @@ The least significant eight bits represent the fractional part. LP_APM - LP_APM Peripheral + Low-power Access Permission Management Controller LP_APM 0x600B3800 @@ -18487,7 +21048,7 @@ The least significant eight bits represent the fractional part. LP_TIMER - LP_TIMER Peripheral + Low-power Timer LP_TIMER 0x600B0C00 @@ -18767,7 +21328,7 @@ The least significant eight bits represent the fractional part. LP_WDT - LP_WDT Peripheral + Low-power Watchdog Timer LP_WDT 0x600B1C00 @@ -18781,7 +21342,7 @@ The least significant eight bits represent the fractional part. - CONFIG0 + WDTCONFIG0 need_des 0x0 0x20 @@ -18961,7 +21522,7 @@ The least significant eight bits represent the fractional part. - FEED + WDTFEED need_des 0x18 0x20 @@ -18976,7 +21537,7 @@ The least significant eight bits represent the fractional part. - WPROTECT + WDTWPROTECT need_des 0x1C 0x20 @@ -18991,7 +21552,7 @@ The least significant eight bits represent the fractional part. - SWD_CONFIG + SWD_CONF need_des 0x20 0x20 @@ -19079,7 +21640,7 @@ The least significant eight bits represent the fractional part. - INT_ST + INT_ST_RTC need_des 0x2C 0x20 @@ -19092,7 +21653,7 @@ The least significant eight bits represent the fractional part. read-only - LP_WDT_INT_ST + WDT_INT_ST need_des 31 1 @@ -19101,7 +21662,7 @@ The least significant eight bits represent the fractional part. - INT_ENA + INT_ENA_RTC need_des 0x30 0x20 @@ -19114,7 +21675,7 @@ The least significant eight bits represent the fractional part. read-write - LP_WDT_INT_ENA + WDT_INT_ENA need_des 31 1 @@ -19123,7 +21684,7 @@ The least significant eight bits represent the fractional part. - INT_CLR + INT_CLR_RTC need_des 0x34 0x20 @@ -19136,7 +21697,7 @@ The least significant eight bits represent the fractional part. write-only - LP_WDT_INT_CLR + WDT_INT_CLR need_des 31 1 @@ -23842,7 +26403,6 @@ The least significant eight bits represent the fractional part. CLK_EN - . 0 1 read-write @@ -23856,77 +26416,66 @@ The least significant eight bits represent the fractional part. CLK_ETM_EN - . 21 1 read-write CLK_ZB_APB_EN - . 22 1 read-write CLK_ZB_MAC_EN - . 23 1 read-write CLK_MODEM_SEC_ECB_EN - . 24 1 read-write CLK_MODEM_SEC_CCM_EN - . 25 1 read-write CLK_MODEM_SEC_BAH_EN - . 26 1 read-write CLK_MODEM_SEC_APB_EN - . 27 1 read-write CLK_MODEM_SEC_EN - . 28 1 read-write CLK_BLE_TIMER_APB_EN - . 29 1 read-write CLK_BLE_TIMER_EN - . 30 1 read-write CLK_DATA_DUMP_EN - . 31 1 read-write @@ -23940,35 +26489,30 @@ The least significant eight bits represent the fractional part. CLK_ETM_FO - . 22 1 read-write CLK_ZB_FO - . 24 1 read-write CLK_MODEM_SEC_FO - . 29 1 read-write CLK_BLE_TIMER_FO - . 30 1 read-write CLK_DATA_DUMP_FO - . 31 1 read-write @@ -23982,91 +26526,78 @@ The least significant eight bits represent the fractional part. RST_FE - . 14 1 read-write RST_BTMAC_APB - . 15 1 read-write RST_BTMAC - . 16 1 read-write RST_BTBB_APB - . 17 1 read-write RST_BTBB - . 18 1 read-write RST_ETM - . 22 1 read-write RST_ZBMAC - . 24 1 read-write RST_MODEM_ECB - . 25 1 read-write RST_MODEM_CCM - . 26 1 read-write RST_MODEM_BAH - . 27 1 read-write RST_MODEM_SEC - . 29 1 read-write RST_BLE_TIMER - . 30 1 read-write RST_DATA_DUMP - . 31 1 read-write @@ -24080,49 +26611,42 @@ The least significant eight bits represent the fractional part. CLK_FE_16M_EN - . 12 1 read-write CLK_FE_32M_EN - . 13 1 read-write CLK_FE_SDM_EN - . 14 1 read-write CLK_FE_ADC_EN - . 15 1 read-write CLK_FE_APB_EN - . 16 1 read-write CLK_BT_APB_EN - . 17 1 read-write CLK_BT_EN - . 18 1 read-write @@ -24136,14 +26660,12 @@ The least significant eight bits represent the fractional part. CLK_FE_FO - . 16 1 read-write CLK_BT_FO - . 18 1 read-write @@ -24158,21 +26680,18 @@ The least significant eight bits represent the fractional part. MODEM_MEM_WP - . 0 3 read-write MODEM_MEM_WA - . 3 3 read-write MODEM_MEM_RA - . 6 2 read-write @@ -24187,7 +26706,6 @@ The least significant eight bits represent the fractional part. DATE - . 0 28 read-write @@ -26192,7 +28710,7 @@ The least significant eight bits represent the fractional part. PARL_IO - PARL_IO Peripheral + Parallel IO Controller PARL_IO 0x60015000 @@ -27172,7 +29690,7 @@ The least significant eight bits represent the fractional part. 0x00003C10 - FILTER_THRES_U + FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. @@ -27181,49 +29699,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - FILTER_EN_U + FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write - THR_ZERO_EN_U + THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write - THR_H_LIM_EN_U + THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. 12 1 read-write - THR_L_LIM_EN_U + THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. 13 1 read-write - THR_THRES0_EN_U + THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write - THR_THRES1_EN_U + THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write - CH0_NEG_MODE_U + CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter @@ -27232,7 +29750,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_POS_MODE_U + CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter @@ -27241,7 +29759,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_HCTRL_MODE_U + CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification @@ -27250,7 +29768,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_LCTRL_MODE_U + CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification @@ -27259,7 +29777,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_NEG_MODE_U + CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter @@ -27268,7 +29786,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_POS_MODE_U + CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter @@ -27277,7 +29795,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_HCTRL_MODE_U + CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification @@ -27286,7 +29804,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_LCTRL_MODE_U + CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification @@ -27305,14 +29823,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THRES0_U + CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write - CNT_THRES1_U + CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 @@ -27329,14 +29847,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_H_LIM_U + CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. 0 16 read-write - CNT_L_LIM_U + CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. 16 16 @@ -27353,7 +29871,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - PULSE_CNT_U + CNT This register stores the current pulse count value for unit %s. 0 16 @@ -27368,28 +29886,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -27404,28 +29922,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -27440,28 +29958,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -27476,28 +29994,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -27514,42 +30032,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_ZERO_MODE_U + ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only - CNT_THR_THRES1_LAT_U + THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others 2 1 read-only - CNT_THR_THRES0_LAT_U + THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others 3 1 read-only - CNT_THR_L_LIM_LAT_U + L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others 4 1 read-only - CNT_THR_H_LIM_LAT_U + H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others 5 1 read-only - CNT_THR_ZERO_LAT_U + ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others 6 1 @@ -27565,7 +30083,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000001 - PULSE_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 @@ -27579,7 +30097,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit 1's counter. 2 1 @@ -27593,7 +30111,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit 2's counter. 4 1 @@ -27607,7 +30125,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit 3's counter. 6 1 @@ -28127,35 +30645,35 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00301000 - RMT_SCLK_DIV_A + SCLK_DIV_A The denominator of the frequency divider factor of the rmt function clock. 0 6 read-write - RMT_SCLK_DIV_B + SCLK_DIV_B The numerator of the frequency divider factor of the rmt function clock. 6 6 read-write - RMT_SCLK_DIV_NUM + SCLK_DIV_NUM The integral part of the frequency divider factor of the rmt function clock. 12 8 read-write - RMT_SCLK_SEL + SCLK_SEL set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL. 20 1 read-write - RMT_SCLK_EN + SCLK_EN Set 1 to enable rmt function clock 21 1 @@ -34111,115 +36629,115 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x4 - TX_CH%sDATA + CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 - CHDATA + DATA Read and write data for channel %s via APB FIFO. 0 32 - read-only + read-write 2 0x4 - TX_CH%sCONF0 + CH%s_TX_CONF0 Channel %s configure register 0 0x10 0x20 0x00710200 - TX_START_CH0 + TX_START Set this bit to start sending data on CHANNEL%s. 0 1 write-only - MEM_RD_RST_CH0 + MEM_RD_RST Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. 1 1 write-only - APB_MEM_RST_CH0 + APB_MEM_RST Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 2 1 write-only - TX_CONTI_MODE_CH0 + TX_CONTI_MODE Set this bit to restart transmission from the first data to the last data in CHANNEL%s. 3 1 read-write - MEM_TX_WRAP_EN_CH0 + MEM_TX_WRAP_EN This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. 4 1 read-write - IDLE_OUT_LV_CH0 + IDLE_OUT_LV This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. 5 1 read-write - IDLE_OUT_EN_CH0 + IDLE_OUT_EN This is the output enable-control bit for CHANNEL%s in IDLE state. 6 1 read-write - TX_STOP_CH0 + TX_STOP Set this bit to stop the transmitter of CHANNEL%s sending data out. 7 1 read-write - DIV_CNT_CH0 + DIV_CNT This register is used to configure the divider for clock of CHANNEL%s. 8 8 read-write - MEM_SIZE_CH0 + MEM_SIZE This register is used to configure the maximum size of memory allocated to CHANNEL%s. 16 3 read-write - CARRIER_EFF_EN_CH0 + CARRIER_EFF_EN 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. 20 1 read-write - CARRIER_EN_CH0 + CARRIER_EN This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 21 1 read-write - CARRIER_OUT_LV_CH0 + CARRIER_OUT_LV This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. @@ -34230,14 +36748,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - AFIFO_RST_CH0 + AFIFO_RST Reserved 23 1 write-only - CONF_UPDATE_CH0 + CONF_UPDATE synchronization bit for CHANNEL%s 24 1 @@ -34248,42 +36766,43 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x8 - RX_CH%sCONF0 + 2-3 + CH%s_RX_CONF0 Channel %s configure register 0 0x18 0x20 0x30FFFF02 - DIV_CNT_CH2 + DIV_CNT This register is used to configure the divider for clock of CHANNEL%s. 0 8 read-write - IDLE_THRES_CH2 + IDLE_THRES When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. 8 15 read-write - MEM_SIZE_CH2 + MEM_SIZE This register is used to configure the maximum size of memory allocated to CHANNEL%s. 23 3 read-write - CARRIER_EN_CH2 + CARRIER_EN This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 28 1 read-write - CARRIER_OUT_LV_CH2 + CARRIER_OUT_LV This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. @@ -34298,35 +36817,36 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x8 - RX_CH%sCONF1 + 2-3 + CH%s_RX_CONF1 Channel %s configure register 1 0x1C 0x20 0x000001E8 - RX_EN_CH2 + RX_EN Set this bit to enable receiver to receive data on CHANNEL%s. 0 1 read-write - MEM_WR_RST_CH2 + MEM_WR_RST Set this bit to reset write ram address for CHANNEL%s by accessing receiver. 1 1 write-only - APB_MEM_RST_CH2 + APB_MEM_RST Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 2 1 write-only - MEM_OWNER_CH2 + MEM_OWNER This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. @@ -34337,35 +36857,35 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RX_FILTER_EN_CH2 + RX_FILTER_EN This is the receive filter's enable bit for CHANNEL%s. 4 1 read-write - RX_FILTER_THRES_CH2 + RX_FILTER_THRES Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). 5 8 read-write - MEM_RX_WRAP_EN_CH2 + MEM_RX_WRAP_EN This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. 13 1 read-write - AFIFO_RST_CH2 + AFIFO_RST Reserved 14 1 write-only - CONF_UPDATE_CH2 + CONF_UPDATE synchronization bit for CHANNEL%s 15 1 @@ -34376,55 +36896,55 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x4 - TX_CH%sSTATUS + CH%s_TX_STATUS Channel %s status register 0x28 0x20 - MEM_RADDR_EX_CH0 + MEM_RADDR_EX This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. 0 9 read-only - STATE_CH0 + STATE This register records the FSM status of CHANNEL%s. 9 3 read-only - APB_MEM_WADDR_CH0 + APB_MEM_WADDR This register records the memory address offset when writes RAM over APB bus. 12 9 read-only - APB_MEM_RD_ERR_CH0 + APB_MEM_RD_ERR This status bit will be set if the offset address out of memory size when reading via APB bus. 21 1 read-only - MEM_EMPTY_CH0 + MEM_EMPTY This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. 22 1 read-only - APB_MEM_WR_ERR_CH0 + APB_MEM_WR_ERR This status bit will be set if the offset address out of memory size when writes via APB bus. 23 1 read-only - APB_MEM_RADDR_CH0 + APB_MEM_RADDR This register records the memory address offset when reading RAM over APB bus. 24 8 @@ -34435,48 +36955,48 @@ Any pulses with width less than this will be ignored when the filter is enabled. 2 0x4 - RX_CH%sSTATUS + CH%s_RX_STATUS Channel %s status register 0x30 0x20 - MEM_WADDR_EX_CH2 + MEM_WADDR_EX This register records the memory address offset when receiver of CHANNEL%s is using the RAM. 0 9 read-only - APB_MEM_RADDR_CH2 + APB_MEM_RADDR This register records the memory address offset when reads RAM over APB bus. 12 9 read-only - STATE_CH2 + STATE This register records the FSM status of CHANNEL%s. 22 3 read-only - MEM_OWNER_ERR_CH2 + MEM_OWNER_ERR This status bit will be set when the ownership of memory block is wrong. 25 1 read-only - MEM_FULL_CH2 + MEM_FULL This status bit will be set if the receiver receives more data than the memory size. 26 1 read-only - APB_MEM_RD_ERR_CH2 + APB_MEM_RD_ERR This status bit will be set if the offset address out of memory size when reads via APB bus. 27 1 @@ -34491,103 +37011,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 2 + 0x1 + 0-1 + CH%s_TX_END + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 read-write - CH1_TX_END_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmission done. - 1 - 1 - read-write - - - CH2_RX_END_INT_RAW + 2 + 0x1 + 2-3 + CH%s_RX_END The interrupt raw bit for CHANNEL2. Triggered when reception done. 2 1 read-write - CH3_RX_END_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when reception done. - 3 - 1 - read-write - - - TX_CH0_ERR_INT_RAW + 2 + 0x1 + 0-1 + CH%s_TX_ERR The interrupt raw bit for CHANNEL4. Triggered when error occurs. 4 1 read-write - TX_CH1_ERR_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when error occurs. - 5 - 1 - read-write - - - TX_CH2_ERR_INT_RAW + 2 + 0x1 + 2-3 + CH%s_RX_ERR The interrupt raw bit for CHANNEL6. Triggered when error occurs. 6 1 read-write - TX_CH3_ERR_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when error occurs. - 7 - 1 - read-write - - - CH0_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 8 1 read-write - CH1_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. - 9 - 1 - read-write - - - CH2_RX_THR_EVENT_INT_RAW + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. 10 1 read-write - CH3_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. - 11 - 1 - read-write - - - CH0_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 2 + 0x1 + 0-1 + CH%s_TX_LOOP + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 12 1 read-write - - CH1_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. - 13 - 1 - read-write - @@ -34597,103 +37089,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_ST - The masked interrupt status bit for CH0_TX_END_INT. + 2 + 0x1 + 0-1 + CH%s_TX_END + The masked interrupt status bit for CH%s_TX_END_INT. 0 1 read-only - CH1_TX_END_INT_ST - The masked interrupt status bit for CH1_TX_END_INT. - 1 - 1 - read-only - - - CH2_RX_END_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_END The masked interrupt status bit for CH2_RX_END_INT. 2 1 read-only - CH3_RX_END_INT_ST - The masked interrupt status bit for CH3_RX_END_INT. - 3 - 1 - read-only - - - RX_CH0_ERR_INT_ST + 2 + 0x1 + 0-1 + CH%s_TX_ERR The masked interrupt status bit for CH4_ERR_INT. 4 1 read-only - RX_CH1_ERR_INT_ST - The masked interrupt status bit for CH5_ERR_INT. - 5 - 1 - read-only - - - RX_CH2_ERR_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_ERR The masked interrupt status bit for CH6_ERR_INT. 6 1 read-only - RX_CH3_ERR_INT_ST - The masked interrupt status bit for CH7_ERR_INT. - 7 - 1 - read-only - - - CH0_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 8 1 read-only - CH1_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-only - - - CH2_RX_THR_EVENT_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT The masked interrupt status bit for CH2_RX_THR_EVENT_INT. 10 1 read-only - CH3_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH3_RX_THR_EVENT_INT. - 11 - 1 - read-only - - - CH0_TX_LOOP_INT_ST - The masked interrupt status bit for CH0_TX_LOOP_INT. + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The masked interrupt status bit for CH%s_TX_LOOP_INT. 12 1 read-only - - CH1_TX_LOOP_INT_ST - The masked interrupt status bit for CH1_TX_LOOP_INT. - 13 - 1 - read-only - @@ -34703,103 +37167,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_ENA - The interrupt enable bit for CH0_TX_END_INT. + 2 + 0x1 + 0-1 + CH%s_TX_END + The interrupt enable bit for CH%s_TX_END_INT. 0 1 read-write - CH1_TX_END_INT_ENA - The interrupt enable bit for CH1_TX_END_INT. - 1 - 1 - read-write - - - CH2_RX_END_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_END The interrupt enable bit for CH2_RX_END_INT. 2 1 read-write - CH3_RX_END_INT_ENA - The interrupt enable bit for CH3_RX_END_INT. - 3 - 1 - read-write - - - CH0_ERR_INT_ENA + 2 + 0x1 + 0-1 + CH%s_TX_ERR The interrupt enable bit for CH4_ERR_INT. 4 1 read-write - CH1_ERR_INT_ENA - The interrupt enable bit for CH5_ERR_INT. - 5 - 1 - read-write - - - CH2_ERR_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_ERR The interrupt enable bit for CH6_ERR_INT. 6 1 read-write - CH3_ERR_INT_ENA - The interrupt enable bit for CH7_ERR_INT. - 7 - 1 - read-write - - - CH0_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. 8 1 read-write - CH1_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-write - - - CH2_RX_THR_EVENT_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT The interrupt enable bit for CH2_RX_THR_EVENT_INT. 10 1 read-write - CH3_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH3_RX_THR_EVENT_INT. - 11 - 1 - read-write - - - CH0_TX_LOOP_INT_ENA - The interrupt enable bit for CH0_TX_LOOP_INT. + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The interrupt enable bit for CH%s_TX_LOOP_INT. 12 1 read-write - - CH1_TX_LOOP_INT_ENA - The interrupt enable bit for CH1_TX_LOOP_INT. - 13 - 1 - read-write - @@ -34809,103 +37245,75 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH0_TX_END_INT_CLR - Set this bit to clear theCH0_TX_END_INT interrupt. + 2 + 0x1 + 0-1 + CH%s_TX_END + Set this bit to clear theCH%s_TX_END_INT interrupt. 0 1 write-only - CH1_TX_END_INT_CLR - Set this bit to clear theCH1_TX_END_INT interrupt. - 1 - 1 - write-only - - - CH2_RX_END_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_END Set this bit to clear theCH2_RX_END_INT interrupt. 2 1 write-only - CH3_RX_END_INT_CLR - Set this bit to clear theCH3_RX_END_INT interrupt. - 3 - 1 - write-only - - - RX_CH0_ERR_INT_CLR + 2 + 0x1 + 0-1 + CH%s_TX_ERR Set this bit to clear theCH4_ERR_INT interrupt. 4 1 write-only - RX_CH1_ERR_INT_CLR - Set this bit to clear theCH5_ERR_INT interrupt. - 5 - 1 - write-only - - - RX_CH2_ERR_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_ERR Set this bit to clear theCH6_ERR_INT interrupt. 6 1 write-only - RX_CH3_ERR_INT_CLR - Set this bit to clear theCH7_ERR_INT interrupt. - 7 - 1 - write-only - - - CH0_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. 8 1 write-only - CH1_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. - 9 - 1 - write-only - - - CH2_RX_THR_EVENT_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. 10 1 write-only - CH3_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. - 11 - 1 - write-only - - - CH0_TX_LOOP_INT_CLR - Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 2 + 0x1 + 0-1 + CH%s_TX_LOOP + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. 12 1 write-only - - CH1_TX_LOOP_INT_CLR - Set this bit to clear theCH1_TX_LOOP_INT interrupt. - 13 - 1 - write-only - @@ -34918,14 +37326,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00400040 - CARRIER_LOW_CH0 + CARRIER_LOW This register is used to configure carrier wave 's low level clock period for CHANNEL%s. 0 16 read-write - CARRIER_HIGH_CH0 + CARRIER_HIGH This register is used to configure carrier wave 's high level clock period for CHANNEL%s. 16 16 @@ -34942,14 +37350,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CARRIER_LOW_THRES_CH2 + CARRIER_LOW_THRES The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. 0 16 read-write - CARRIER_HIGH_THRES_CH2 + CARRIER_HIGH_THRES The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. 16 16 @@ -34967,35 +37375,35 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000080 - TX_LIM_CH0 + TX_LIM This register is used to configure the maximum entries that CHANNEL%s can send out. 0 9 read-write - TX_LOOP_NUM_CH0 + TX_LOOP_NUM This register is used to configure the maximum loop count when tx_conti_mode is valid. 9 10 read-write - TX_LOOP_CNT_EN_CH0 + TX_LOOP_CNT_EN This register is the enabled bit for loop count. 19 1 read-write - LOOP_COUNT_RESET_CH0 + LOOP_COUNT_RESET This register is used to reset the loop count when tx_conti_mode is valid. 20 1 write-only - LOOP_STOP_EN_CH0 + LOOP_STOP_EN This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. 21 1 @@ -35013,7 +37421,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000080 - RMT_RX_LIM_CH2 + RMT_RX_LIM This register is used to configure the maximum entries that CHANNEL%s can receive. 0 9 @@ -35043,49 +37451,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RMT_MEM_FORCE_PD + MEM_FORCE_PD Set this bit to power down RMT memory. 2 1 read-write - RMT_MEM_FORCE_PU + MEM_FORCE_PU 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. 3 1 read-write - RMT_SCLK_DIV_NUM + SCLK_DIV_NUM the integral part of the fractional divisor 4 8 read-write - RMT_SCLK_DIV_A + SCLK_DIV_A the numerator of the fractional part of the fractional divisor 12 6 read-write - RMT_SCLK_DIV_B + SCLK_DIV_B the denominator of the fractional part of the fractional divisor 18 6 read-write - RMT_SCLK_SEL + SCLK_SEL choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL 24 2 read-write - RMT_SCLK_ACTIVE + SCLK_ACTIVE rmt_sclk switch 26 1 @@ -35136,7 +37544,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - TX_REF_CNT_RST_CH0 + TX_REF_CNT_RST This register is used to reset the clock divider of CHANNEL0. 0 1 @@ -35187,7 +37595,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RNG Hardware Random Number Generator RNG - 0x600260B0 + 0x600B2800 0x0 0x4 @@ -35197,7 +37605,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. DATA Random number data - 0x0 + 0x8 0x20 read-only @@ -35219,39 +37627,39 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 384 - 0x1 + 96 + 0x4 M_MEM[%s] Represents M 0x0 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 Z_MEM[%s] Represents Z 0x200 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 Y_MEM[%s] Represents Y 0x400 - 0x8 + 0x20 read-write - 384 - 0x1 + 96 + 0x4 X_MEM[%s] Represents X 0x600 - 0x8 + 0x20 read-write @@ -35296,9 +37704,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: Not complete -1: Completed - - +1: Completed 0 1 read-only @@ -35317,9 +37723,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: No effect -1: Start - - +1: Start 0 1 write-only @@ -35338,9 +37742,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: No effect -1: Start - - +1: Start 0 1 write-only @@ -35359,9 +37761,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: No effect -1: Start - - +1: Start 0 1 write-only @@ -35380,9 +37780,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: Busy -1: Idle - - +1: Idle 0 1 read-only @@ -35417,9 +37815,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0: Acceleration -1: No acceleration (default) - - +1: No acceleration (default) 0 1 read-write @@ -35692,26 +38088,26 @@ This option should be used together with RSA_SEARCH_POS. - 64 - 0x1 + 8 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 SOC_ETM - SOC_ETM Peripheral + Event Task Matrix SOC_ETM 0x60013000 @@ -42555,27 +44951,27 @@ This option should be used together with RSA_SEARCH_POS. - SPI_CMD + CMD Command control register 0x0 0x20 - SPI_CONF_BITLEN + CONF_BITLEN Define the APB cycles of SPI_CONF state. Can be configured in CONF state. 0 18 read-write - SPI_UPDATE + UPDATE Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. 23 1 - write-only + read-write - SPI_USR + USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. 24 1 @@ -42584,13 +44980,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_ADDR + ADDR Address value register 0x4 0x20 - SPI_USR_ADDR_VALUE + USR_ADDR_VALUE Address to slave. Can be configured in CONF state. 0 32 @@ -42599,119 +44995,119 @@ This option should be used together with RSA_SEARCH_POS. - SPI_CTRL + CTRL SPI control register 0x8 0x20 0x003C0000 - SPI_DUMMY_OUT + DUMMY_OUT 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. 3 1 read-write - SPI_FADDR_DUAL + FADDR_DUAL Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 5 1 read-write - SPI_FADDR_QUAD + FADDR_QUAD Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 6 1 read-write - SPI_FADDR_OCT + FADDR_OCT Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 read-only - SPI_FCMD_DUAL + FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 8 1 read-write - SPI_FCMD_QUAD + FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 9 1 read-write - SPI_FCMD_OCT + FCMD_OCT Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 read-only - SPI_FREAD_DUAL + FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. 14 1 read-write - SPI_FREAD_QUAD + FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. 15 1 read-write - SPI_FREAD_OCT + FREAD_OCT In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. 16 1 read-only - SPI_Q_POL + Q_POL The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. 18 1 read-write - SPI_D_POL + D_POL The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. 19 1 read-write - SPI_HOLD_POL + HOLD_POL SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 20 1 read-write - SPI_WP_POL + WP_POL Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 21 1 read-write - SPI_RD_BIT_ORDER + RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. 23 2 read-write - SPI_WR_BIT_ORDER + WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. 25 2 @@ -42720,42 +45116,42 @@ This option should be used together with RSA_SEARCH_POS. - SPI_CLOCK + CLOCK SPI clock control register 0xC 0x20 0x80003043 - SPI_CLKCNT_L + CLKCNT_L In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. 0 6 read-write - SPI_CLKCNT_H + CLKCNT_H In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. 6 6 read-write - SPI_CLKCNT_N + CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. 12 6 read-write - SPI_CLKDIV_PRE + CLKDIV_PRE In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 18 4 read-write - SPI_CLK_EQU_SYSCLK + CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. 31 1 @@ -42764,154 +45160,154 @@ This option should be used together with RSA_SEARCH_POS. - SPI_USER + USER SPI USER control register 0x10 0x20 0x800000C0 - SPI_DOUTDIN + DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. 0 1 read-write - SPI_QPI_MODE + QPI_MODE Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. 3 1 read-write - SPI_OPI_MODE + OPI_MODE Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. 4 1 read-only - SPI_TSCK_I_EDGE + TSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. 5 1 read-write - SPI_CS_HOLD + CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write - SPI_CS_SETUP + CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write - SPI_RSCK_I_EDGE + RSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. 8 1 read-write - SPI_CK_OUT_EDGE + CK_OUT_EDGE the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. 9 1 read-write - SPI_FWRITE_DUAL + FWRITE_DUAL In the write operations read-data phase apply 2 signals. Can be configured in CONF state. 12 1 read-write - SPI_FWRITE_QUAD + FWRITE_QUAD In the write operations read-data phase apply 4 signals. Can be configured in CONF state. 13 1 read-write - SPI_FWRITE_OCT + FWRITE_OCT In the write operations read-data phase apply 8 signals. Can be configured in CONF state. 14 1 read-only - SPI_USR_CONF_NXT + USR_CONF_NXT 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. 15 1 read-write - SPI_SIO + SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. 17 1 read-write - SPI_USR_MISO_HIGHPART + USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 24 1 read-write - SPI_USR_MOSI_HIGHPART + USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 25 1 read-write - SPI_USR_DUMMY_IDLE + USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. 26 1 read-write - SPI_USR_MOSI + USR_MOSI This bit enable the write-data phase of an operation. Can be configured in CONF state. 27 1 read-write - SPI_USR_MISO + USR_MISO This bit enable the read-data phase of an operation. Can be configured in CONF state. 28 1 read-write - SPI_USR_DUMMY + USR_DUMMY This bit enable the dummy phase of an operation. Can be configured in CONF state. 29 1 read-write - SPI_USR_ADDR + USR_ADDR This bit enable the address phase of an operation. Can be configured in CONF state. 30 1 read-write - SPI_USR_COMMAND + USR_COMMAND This bit enable the command phase of an operation. Can be configured in CONF state. 31 1 @@ -42920,42 +45316,42 @@ This option should be used together with RSA_SEARCH_POS. - SPI_USER1 + USER1 SPI USER control register 1 0x14 0x20 0xB8410007 - SPI_USR_DUMMY_CYCLELEN + USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. 0 8 read-write - SPI_MST_WFULL_ERR_END_EN + MST_WFULL_ERR_END_EN 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 16 1 read-write - SPI_CS_SETUP_TIME + CS_SETUP_TIME (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. 17 5 read-write - SPI_CS_HOLD_TIME + CS_HOLD_TIME delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. 22 5 read-write - SPI_USR_ADDR_BITLEN + USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. 27 5 @@ -42964,28 +45360,28 @@ This option should be used together with RSA_SEARCH_POS. - SPI_USER2 + USER2 SPI USER control register 2 0x18 0x20 0x78000000 - SPI_USR_COMMAND_VALUE + USR_COMMAND_VALUE The value of command. Can be configured in CONF state. 0 16 read-write - SPI_MST_REMPTY_ERR_END_EN + MST_REMPTY_ERR_END_EN 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 27 1 read-write - SPI_USR_COMMAND_BITLEN + USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. 28 4 @@ -42994,13 +45390,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_MS_DLEN + MS_DLEN SPI data bit length control register 0x1C 0x20 - SPI_MS_DATA_BITLEN + MS_DATA_BITLEN The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. 0 18 @@ -43009,126 +45405,126 @@ This option should be used together with RSA_SEARCH_POS. - SPI_MISC + MISC SPI misc register 0x20 0x20 0x0000003E - SPI_CS0_DIS + CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. 0 1 read-write - SPI_CS1_DIS + CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. 1 1 read-write - SPI_CS2_DIS + CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. 2 1 read-write - SPI_CS3_DIS + CS3_DIS SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. 3 1 read-write - SPI_CS4_DIS + CS4_DIS SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. 4 1 read-write - SPI_CS5_DIS + CS5_DIS SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. 5 1 read-write - SPI_CK_DIS + CK_DIS 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 6 1 read-write - SPI_MASTER_CS_POL + MASTER_CS_POL In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. 7 6 read-write - SPI_CLK_DATA_DTR_EN + CLK_DATA_DTR_EN 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 read-only - SPI_DATA_DTR_EN + DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 read-only - SPI_ADDR_DTR_EN + ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 read-only - SPI_CMD_DTR_EN + CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 read-only - SPI_SLAVE_CS_POL + SLAVE_CS_POL spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. 23 1 read-write - SPI_DQS_IDLE_EDGE + DQS_IDLE_EDGE The default value of spi_dqs. Can be configured in CONF state. 24 1 read-only - SPI_CK_IDLE_EDGE + CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. 29 1 read-write - SPI_CS_KEEP_ACTIVE + CS_KEEP_ACTIVE spi cs line keep low when the bit is set. Can be configured in CONF state. 30 1 read-write - SPI_QUAD_DIN_PIN_SWAP + QUAD_DIN_PIN_SWAP 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. 31 1 @@ -43137,69 +45533,69 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DIN_MODE + DIN_MODE SPI input delay mode configuration 0x24 0x20 - SPI_DIN0_MODE + DIN0_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 read-write - SPI_DIN1_MODE + DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 read-write - SPI_DIN2_MODE + DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 read-write - SPI_DIN3_MODE + DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 read-write - SPI_DIN4_MODE + DIN4_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 8 2 read-only - SPI_DIN5_MODE + DIN5_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 10 2 read-only - SPI_DIN6_MODE + DIN6_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 12 2 read-only - SPI_DIN7_MODE + DIN7_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 14 2 read-only - SPI_TIMING_HCLK_ACTIVE + TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 @@ -43208,62 +45604,62 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DIN_NUM + DIN_NUM SPI input delay number configuration 0x28 0x20 - SPI_DIN0_NUM + DIN0_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write - SPI_DIN1_NUM + DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write - SPI_DIN2_NUM + DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write - SPI_DIN3_NUM + DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write - SPI_DIN4_NUM + DIN4_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-only - SPI_DIN5_NUM + DIN5_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 read-only - SPI_DIN6_NUM + DIN6_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 read-only - SPI_DIN7_NUM + DIN7_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 @@ -43272,69 +45668,69 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DOUT_MODE + DOUT_MODE SPI output delay mode configuration 0x2C 0x20 - SPI_DOUT0_MODE + DOUT0_MODE The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 read-write - SPI_DOUT1_MODE + DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 read-write - SPI_DOUT2_MODE + DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 read-write - SPI_DOUT3_MODE + DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 read-write - SPI_DOUT4_MODE + DOUT4_MODE The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 4 1 read-only - SPI_DOUT5_MODE + DOUT5_MODE The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 5 1 read-only - SPI_DOUT6_MODE + DOUT6_MODE The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 6 1 read-only - SPI_DOUT7_MODE + DOUT7_MODE The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 7 1 read-only - SPI_D_DQS_MODE + D_DQS_MODE The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 8 1 @@ -43343,84 +45739,84 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_CONF + DMA_CONF SPI DMA control register 0x30 0x20 0x00000003 - SPI_DMA_OUTFIFO_EMPTY + DMA_OUTFIFO_EMPTY Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. 0 1 read-only - SPI_DMA_INFIFO_FULL + DMA_INFIFO_FULL Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. 1 1 read-only - SPI_DMA_SLV_SEG_TRANS_EN + DMA_SLV_SEG_TRANS_EN Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 18 1 read-write - SPI_SLV_RX_SEG_TRANS_CLR_EN + SLV_RX_SEG_TRANS_CLR_EN 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. 19 1 read-write - SPI_SLV_TX_SEG_TRANS_CLR_EN + SLV_TX_SEG_TRANS_CLR_EN 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. 20 1 read-write - SPI_RX_EOF_EN + RX_EOF_EN 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. 21 1 read-write - SPI_DMA_RX_ENA + DMA_RX_ENA Set this bit to enable SPI DMA controlled receive data mode. 27 1 read-write - SPI_DMA_TX_ENA + DMA_TX_ENA Set this bit to enable SPI DMA controlled send data mode. 28 1 read-write - SPI_RX_AFIFO_RST + RX_AFIFO_RST Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. 29 1 write-only - SPI_BUF_AFIFO_RST + BUF_AFIFO_RST Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. 30 1 write-only - SPI_DMA_AFIFO_RST + DMA_AFIFO_RST Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. 31 1 @@ -43429,153 +45825,153 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_INT_ENA + DMA_INT_ENA SPI interrupt enable register 0x34 0x20 - SPI_DMA_INFIFO_FULL_ERR_INT_ENA + DMA_INFIFO_FULL_ERR_INT_ENA The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-write - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + DMA_OUTFIFO_EMPTY_ERR_INT_ENA The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-write - SPI_SLV_EX_QPI_INT_ENA + SLV_EX_QPI_INT_ENA The enable bit for SPI slave Ex_QPI interrupt. 2 1 read-write - SPI_SLV_EN_QPI_INT_ENA + SLV_EN_QPI_INT_ENA The enable bit for SPI slave En_QPI interrupt. 3 1 read-write - SPI_SLV_CMD7_INT_ENA + SLV_CMD7_INT_ENA The enable bit for SPI slave CMD7 interrupt. 4 1 read-write - SPI_SLV_CMD8_INT_ENA + SLV_CMD8_INT_ENA The enable bit for SPI slave CMD8 interrupt. 5 1 read-write - SPI_SLV_CMD9_INT_ENA + SLV_CMD9_INT_ENA The enable bit for SPI slave CMD9 interrupt. 6 1 read-write - SPI_SLV_CMDA_INT_ENA + SLV_CMDA_INT_ENA The enable bit for SPI slave CMDA interrupt. 7 1 read-write - SPI_SLV_RD_DMA_DONE_INT_ENA + SLV_RD_DMA_DONE_INT_ENA The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-write - SPI_SLV_WR_DMA_DONE_INT_ENA + SLV_WR_DMA_DONE_INT_ENA The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-write - SPI_SLV_RD_BUF_DONE_INT_ENA + SLV_RD_BUF_DONE_INT_ENA The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-write - SPI_SLV_WR_BUF_DONE_INT_ENA + SLV_WR_BUF_DONE_INT_ENA The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-write - SPI_TRANS_DONE_INT_ENA + TRANS_DONE_INT_ENA The enable bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-write - SPI_DMA_SEG_TRANS_DONE_INT_ENA + DMA_SEG_TRANS_DONE_INT_ENA The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-write - SPI_SEG_MAGIC_ERR_INT_ENA + SEG_MAGIC_ERR_INT_ENA The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-write - SPI_SLV_BUF_ADDR_ERR_INT_ENA + SLV_BUF_ADDR_ERR_INT_ENA The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-write - SPI_SLV_CMD_ERR_INT_ENA + SLV_CMD_ERR_INT_ENA The enable bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-write - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + MST_RX_AFIFO_WFULL_ERR_INT_ENA The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-write - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + MST_TX_AFIFO_REMPTY_ERR_INT_ENA The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-write - SPI_APP2_INT_ENA + APP2_INT_ENA The enable bit for SPI_APP2_INT interrupt. 19 1 read-write - SPI_APP1_INT_ENA + APP1_INT_ENA The enable bit for SPI_APP1_INT interrupt. 20 1 @@ -43584,153 +45980,153 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_INT_CLR + DMA_INT_CLR SPI interrupt clear register 0x38 0x20 - SPI_DMA_INFIFO_FULL_ERR_INT_CLR + DMA_INFIFO_FULL_ERR_INT_CLR The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + DMA_OUTFIFO_EMPTY_ERR_INT_CLR The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only - SPI_SLV_EX_QPI_INT_CLR + SLV_EX_QPI_INT_CLR The clear bit for SPI slave Ex_QPI interrupt. 2 1 write-only - SPI_SLV_EN_QPI_INT_CLR + SLV_EN_QPI_INT_CLR The clear bit for SPI slave En_QPI interrupt. 3 1 write-only - SPI_SLV_CMD7_INT_CLR + SLV_CMD7_INT_CLR The clear bit for SPI slave CMD7 interrupt. 4 1 write-only - SPI_SLV_CMD8_INT_CLR + SLV_CMD8_INT_CLR The clear bit for SPI slave CMD8 interrupt. 5 1 write-only - SPI_SLV_CMD9_INT_CLR + SLV_CMD9_INT_CLR The clear bit for SPI slave CMD9 interrupt. 6 1 write-only - SPI_SLV_CMDA_INT_CLR + SLV_CMDA_INT_CLR The clear bit for SPI slave CMDA interrupt. 7 1 write-only - SPI_SLV_RD_DMA_DONE_INT_CLR + SLV_RD_DMA_DONE_INT_CLR The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only - SPI_SLV_WR_DMA_DONE_INT_CLR + SLV_WR_DMA_DONE_INT_CLR The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only - SPI_SLV_RD_BUF_DONE_INT_CLR + SLV_RD_BUF_DONE_INT_CLR The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only - SPI_SLV_WR_BUF_DONE_INT_CLR + SLV_WR_BUF_DONE_INT_CLR The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only - SPI_TRANS_DONE_INT_CLR + TRANS_DONE_INT_CLR The clear bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only - SPI_DMA_SEG_TRANS_DONE_INT_CLR + DMA_SEG_TRANS_DONE_INT_CLR The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only - SPI_SEG_MAGIC_ERR_INT_CLR + SEG_MAGIC_ERR_INT_CLR The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only - SPI_SLV_BUF_ADDR_ERR_INT_CLR + SLV_BUF_ADDR_ERR_INT_CLR The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only - SPI_SLV_CMD_ERR_INT_CLR + SLV_CMD_ERR_INT_CLR The clear bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only - SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + MST_RX_AFIFO_WFULL_ERR_INT_CLR The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + MST_TX_AFIFO_REMPTY_ERR_INT_CLR The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only - SPI_APP2_INT_CLR + APP2_INT_CLR The clear bit for SPI_APP2_INT interrupt. 19 1 write-only - SPI_APP1_INT_CLR + APP1_INT_CLR The clear bit for SPI_APP1_INT interrupt. 20 1 @@ -43739,153 +46135,153 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_INT_RAW + DMA_INT_RAW SPI interrupt raw register 0x3C 0x20 - SPI_DMA_INFIFO_FULL_ERR_INT_RAW + DMA_INFIFO_FULL_ERR_INT_RAW 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. 0 1 read-write - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + DMA_OUTFIFO_EMPTY_ERR_INT_RAW 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. 1 1 read-write - SPI_SLV_EX_QPI_INT_RAW + SLV_EX_QPI_INT_RAW The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. 2 1 read-write - SPI_SLV_EN_QPI_INT_RAW + SLV_EN_QPI_INT_RAW The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. 3 1 read-write - SPI_SLV_CMD7_INT_RAW + SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. 4 1 read-write - SPI_SLV_CMD8_INT_RAW + SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. 5 1 read-write - SPI_SLV_CMD9_INT_RAW + SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. 6 1 read-write - SPI_SLV_CMDA_INT_RAW + SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. 7 1 read-write - SPI_SLV_RD_DMA_DONE_INT_RAW + SLV_RD_DMA_DONE_INT_RAW The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. 8 1 read-write - SPI_SLV_WR_DMA_DONE_INT_RAW + SLV_WR_DMA_DONE_INT_RAW The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. 9 1 read-write - SPI_SLV_RD_BUF_DONE_INT_RAW + SLV_RD_BUF_DONE_INT_RAW The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. 10 1 read-write - SPI_SLV_WR_BUF_DONE_INT_RAW + SLV_WR_BUF_DONE_INT_RAW The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. 11 1 read-write - SPI_TRANS_DONE_INT_RAW + TRANS_DONE_INT_RAW The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. 12 1 read-write - SPI_DMA_SEG_TRANS_DONE_INT_RAW + DMA_SEG_TRANS_DONE_INT_RAW The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. 13 1 read-write - SPI_SEG_MAGIC_ERR_INT_RAW + SEG_MAGIC_ERR_INT_RAW The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. 14 1 read-write - SPI_SLV_BUF_ADDR_ERR_INT_RAW + SLV_BUF_ADDR_ERR_INT_RAW The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. 15 1 read-write - SPI_SLV_CMD_ERR_INT_RAW + SLV_CMD_ERR_INT_RAW The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. 16 1 read-write - SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. 17 1 read-write - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 18 1 read-write - SPI_APP2_INT_RAW + APP2_INT_RAW The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. 19 1 read-write - SPI_APP1_INT_RAW + APP1_INT_RAW The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. 20 1 @@ -43894,153 +46290,153 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_INT_ST + DMA_INT_ST SPI interrupt status register 0x40 0x20 - SPI_DMA_INFIFO_FULL_ERR_INT_ST + DMA_INFIFO_FULL_ERR_INT_ST The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-only - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + DMA_OUTFIFO_EMPTY_ERR_INT_ST The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-only - SPI_SLV_EX_QPI_INT_ST + SLV_EX_QPI_INT_ST The status bit for SPI slave Ex_QPI interrupt. 2 1 read-only - SPI_SLV_EN_QPI_INT_ST + SLV_EN_QPI_INT_ST The status bit for SPI slave En_QPI interrupt. 3 1 read-only - SPI_SLV_CMD7_INT_ST + SLV_CMD7_INT_ST The status bit for SPI slave CMD7 interrupt. 4 1 read-only - SPI_SLV_CMD8_INT_ST + SLV_CMD8_INT_ST The status bit for SPI slave CMD8 interrupt. 5 1 read-only - SPI_SLV_CMD9_INT_ST + SLV_CMD9_INT_ST The status bit for SPI slave CMD9 interrupt. 6 1 read-only - SPI_SLV_CMDA_INT_ST + SLV_CMDA_INT_ST The status bit for SPI slave CMDA interrupt. 7 1 read-only - SPI_SLV_RD_DMA_DONE_INT_ST + SLV_RD_DMA_DONE_INT_ST The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-only - SPI_SLV_WR_DMA_DONE_INT_ST + SLV_WR_DMA_DONE_INT_ST The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-only - SPI_SLV_RD_BUF_DONE_INT_ST + SLV_RD_BUF_DONE_INT_ST The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-only - SPI_SLV_WR_BUF_DONE_INT_ST + SLV_WR_BUF_DONE_INT_ST The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-only - SPI_TRANS_DONE_INT_ST + TRANS_DONE_INT_ST The status bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-only - SPI_DMA_SEG_TRANS_DONE_INT_ST + DMA_SEG_TRANS_DONE_INT_ST The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-only - SPI_SEG_MAGIC_ERR_INT_ST + SEG_MAGIC_ERR_INT_ST The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-only - SPI_SLV_BUF_ADDR_ERR_INT_ST + SLV_BUF_ADDR_ERR_INT_ST The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-only - SPI_SLV_CMD_ERR_INT_ST + SLV_CMD_ERR_INT_ST The status bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-only - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + MST_RX_AFIFO_WFULL_ERR_INT_ST The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-only - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + MST_TX_AFIFO_REMPTY_ERR_INT_ST The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-only - SPI_APP2_INT_ST + APP2_INT_ST The status bit for SPI_APP2_INT interrupt. 19 1 read-only - SPI_APP1_INT_ST + APP1_INT_ST The status bit for SPI_APP1_INT interrupt. 20 1 @@ -44049,153 +46445,153 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DMA_INT_SET + DMA_INT_SET SPI interrupt software set register 0x44 0x20 - SPI_DMA_INFIFO_FULL_ERR_INT_SET + DMA_INFIFO_FULL_ERR_INT_SET The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + DMA_OUTFIFO_EMPTY_ERR_INT_SET The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only - SPI_SLV_EX_QPI_INT_SET + SLV_EX_QPI_INT_SET The software set bit for SPI slave Ex_QPI interrupt. 2 1 write-only - SPI_SLV_EN_QPI_INT_SET + SLV_EN_QPI_INT_SET The software set bit for SPI slave En_QPI interrupt. 3 1 write-only - SPI_SLV_CMD7_INT_SET + SLV_CMD7_INT_SET The software set bit for SPI slave CMD7 interrupt. 4 1 write-only - SPI_SLV_CMD8_INT_SET + SLV_CMD8_INT_SET The software set bit for SPI slave CMD8 interrupt. 5 1 write-only - SPI_SLV_CMD9_INT_SET + SLV_CMD9_INT_SET The software set bit for SPI slave CMD9 interrupt. 6 1 write-only - SPI_SLV_CMDA_INT_SET + SLV_CMDA_INT_SET The software set bit for SPI slave CMDA interrupt. 7 1 write-only - SPI_SLV_RD_DMA_DONE_INT_SET + SLV_RD_DMA_DONE_INT_SET The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only - SPI_SLV_WR_DMA_DONE_INT_SET + SLV_WR_DMA_DONE_INT_SET The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only - SPI_SLV_RD_BUF_DONE_INT_SET + SLV_RD_BUF_DONE_INT_SET The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only - SPI_SLV_WR_BUF_DONE_INT_SET + SLV_WR_BUF_DONE_INT_SET The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only - SPI_TRANS_DONE_INT_SET + TRANS_DONE_INT_SET The software set bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only - SPI_DMA_SEG_TRANS_DONE_INT_SET + DMA_SEG_TRANS_DONE_INT_SET The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only - SPI_SEG_MAGIC_ERR_INT_SET + SEG_MAGIC_ERR_INT_SET The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only - SPI_SLV_BUF_ADDR_ERR_INT_SET + SLV_BUF_ADDR_ERR_INT_SET The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only - SPI_SLV_CMD_ERR_INT_SET + SLV_CMD_ERR_INT_SET The software set bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only - SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + MST_RX_AFIFO_WFULL_ERR_INT_SET The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + MST_TX_AFIFO_REMPTY_ERR_INT_SET The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only - SPI_APP2_INT_SET + APP2_INT_SET The software set bit for SPI_APP2_INT interrupt. 19 1 write-only - SPI_APP1_INT_SET + APP1_INT_SET The software set bit for SPI_APP1_INT interrupt. 20 1 @@ -44204,13 +46600,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W0 + W0 SPI CPU-controlled buffer0 0x98 0x20 - SPI_BUF0 + BUF0 data buffer 0 32 @@ -44219,13 +46615,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W1 + W1 SPI CPU-controlled buffer1 0x9C 0x20 - SPI_BUF1 + BUF1 data buffer 0 32 @@ -44234,13 +46630,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W2 + W2 SPI CPU-controlled buffer2 0xA0 0x20 - SPI_BUF2 + BUF2 data buffer 0 32 @@ -44249,13 +46645,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W3 + W3 SPI CPU-controlled buffer3 0xA4 0x20 - SPI_BUF3 + BUF3 data buffer 0 32 @@ -44264,13 +46660,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W4 + W4 SPI CPU-controlled buffer4 0xA8 0x20 - SPI_BUF4 + BUF4 data buffer 0 32 @@ -44279,13 +46675,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W5 + W5 SPI CPU-controlled buffer5 0xAC 0x20 - SPI_BUF5 + BUF5 data buffer 0 32 @@ -44294,13 +46690,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W6 + W6 SPI CPU-controlled buffer6 0xB0 0x20 - SPI_BUF6 + BUF6 data buffer 0 32 @@ -44309,13 +46705,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W7 + W7 SPI CPU-controlled buffer7 0xB4 0x20 - SPI_BUF7 + BUF7 data buffer 0 32 @@ -44324,13 +46720,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W8 + W8 SPI CPU-controlled buffer8 0xB8 0x20 - SPI_BUF8 + BUF8 data buffer 0 32 @@ -44339,13 +46735,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W9 + W9 SPI CPU-controlled buffer9 0xBC 0x20 - SPI_BUF9 + BUF9 data buffer 0 32 @@ -44354,13 +46750,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W10 + W10 SPI CPU-controlled buffer10 0xC0 0x20 - SPI_BUF10 + BUF10 data buffer 0 32 @@ -44369,13 +46765,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W11 + W11 SPI CPU-controlled buffer11 0xC4 0x20 - SPI_BUF11 + BUF11 data buffer 0 32 @@ -44384,13 +46780,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W12 + W12 SPI CPU-controlled buffer12 0xC8 0x20 - SPI_BUF12 + BUF12 data buffer 0 32 @@ -44399,13 +46795,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W13 + W13 SPI CPU-controlled buffer13 0xCC 0x20 - SPI_BUF13 + BUF13 data buffer 0 32 @@ -44414,13 +46810,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W14 + W14 SPI CPU-controlled buffer14 0xD0 0x20 - SPI_BUF14 + BUF14 data buffer 0 32 @@ -44429,13 +46825,13 @@ This option should be used together with RSA_SEARCH_POS. - SPI_W15 + W15 SPI CPU-controlled buffer15 0xD4 0x20 - SPI_BUF15 + BUF15 data buffer 0 32 @@ -44444,63 +46840,63 @@ This option should be used together with RSA_SEARCH_POS. - SPI_SLAVE + SLAVE SPI slave control register 0xE0 0x20 0x02800000 - SPI_CLK_MODE + CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. 0 2 read-write - SPI_CLK_MODE_13 + CLK_MODE_13 {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 2 1 read-write - SPI_RSCK_DATA_OUT + RSCK_DATA_OUT It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge 3 1 read-write - SPI_SLV_RDDMA_BITLEN_EN + SLV_RDDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others 8 1 read-write - SPI_SLV_WRDMA_BITLEN_EN + SLV_WRDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others 9 1 read-write - SPI_SLV_RDBUF_BITLEN_EN + SLV_RDBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others 10 1 read-write - SPI_SLV_WRBUF_BITLEN_EN + SLV_WRBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others 11 1 read-write - SPI_DMA_SEG_MAGIC_VALUE + DMA_SEG_MAGIC_VALUE The magic value of BM table in master DMA seg-trans. 22 4 @@ -44514,21 +46910,21 @@ This option should be used together with RSA_SEARCH_POS. read-write - SPI_SOFT_RESET + SOFT_RESET Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. 27 1 write-only - SPI_USR_CONF + USR_CONF 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. 28 1 read-write - SPI_MST_FD_WAIT_DMA_TX_DATA + MST_FD_WAIT_DMA_TX_DATA In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. 29 1 @@ -44537,27 +46933,27 @@ This option should be used together with RSA_SEARCH_POS. - SPI_SLAVE1 + SLAVE1 SPI slave control register 1 0xE4 0x20 - SPI_SLV_DATA_BITLEN + SLV_DATA_BITLEN The transferred data bit length in SPI slave FD and HD mode. 0 18 read-write - SPI_SLV_LAST_COMMAND + SLV_LAST_COMMAND In the slave mode it is the value of command. 18 8 read-write - SPI_SLV_LAST_ADDR + SLV_LAST_ADDR In the slave mode it is the value of address. 26 6 @@ -44566,27 +46962,27 @@ This option should be used together with RSA_SEARCH_POS. - SPI_CLK_GATE + CLK_GATE SPI module clock and register clock control 0xE8 0x20 - SPI_CLK_EN + CLK_EN Set this bit to enable clk gate 0 1 read-write - SPI_MST_CLK_ACTIVE + MST_CLK_ACTIVE Set this bit to power on the SPI module clock. 1 1 read-write - SPI_MST_CLK_SEL + MST_CLK_SEL This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. 2 1 @@ -44595,14 +46991,14 @@ This option should be used together with RSA_SEARCH_POS. - SPI_DATE + DATE Version control 0xF0 0x20 0x02201300 - SPI_DATE + DATE SPI register version. 0 28 @@ -45934,11 +48330,11 @@ This option should be used together with RSA_SEARCH_POS. registers - TG0_T0 + TG0_T0_LEVEL 41 - TG0_WDT + TG0_WDT_LEVEL 42 @@ -46119,8 +48515,7 @@ counter. LOAD - -Write any value to trigger a timer %s time-base counter reload. + Write any value to trigger a timer %s time-base counter reload. 0 32 write-only @@ -46187,32 +48582,28 @@ Write any value to trigger a timer %s time-base counter reload. WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write @@ -46590,17 +48981,17 @@ protection is enabled. Timer Group 1 0x6000A000 - TG1_T0 + TG1_T0_LEVEL 43 - TG1_WDT + TG1_WDT_LEVEL 44 TRACE - TRACE Peripheral + RISC-V Trace Encoder TRACE 0x600C0000 @@ -46620,7 +49011,7 @@ protection is enabled. 0x20 - MEM_STAET_ADDR + MEM_START_ADDR The start address of trace memory 0 32 @@ -49173,7 +51564,7 @@ protection is enabled. read-write - RX_SCLK_EN + SCLK_EN Set this bit to enable UART Rx clock. 25 1 @@ -49187,7 +51578,7 @@ protection is enabled. read-write - RX_RST_CORE + RST_CORE Write 1 then write 0 to this bit to reset UART Rx. 27 1 @@ -50348,7 +52739,7 @@ protection is enabled. registers - USB + USB_DEVICE 37 diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32p4.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32p4.svd new file mode 100644 index 000000000..e805dcf66 --- /dev/null +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32p4.svd @@ -0,0 +1,133701 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-P4 + ESP32 P-Series + 2 + 32-bit RISC-V MCU + Copyright 2024 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + RV32IMAFC + r0p0 + little + false + true + 0 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC (Analog to Digital Converter) + ADC + 0x500DE000 + + 0x0 + 0x7C + registers + + + + CTRL + Register + 0x0 + 0x20 + 0x403FC120 + + + START_FORCE + need_des + 0 + 1 + read-write + + + START + need_des + 1 + 1 + read-write + + + WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 2 + 2 + read-write + + + SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 4 + 1 + read-write + + + SAR_CLK_GATED + need_des + 5 + 1 + read-write + + + SAR_CLK_DIV + SAR clock divider + 6 + 8 + read-write + + + SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 14 + 4 + read-write + + + SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 18 + 4 + read-write + + + SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 22 + 1 + read-write + + + SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 23 + 1 + read-write + + + DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 24 + 1 + read-write + + + DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 25 + 1 + read-write + + + XPD_SAR1_FORCE + force option to xpd sar1 blocks + 26 + 2 + read-write + + + XPD_SAR2_FORCE + force option to xpd sar2 blocks + 28 + 2 + read-write + + + WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + Register + 0x4 + 0x20 + 0x0000A1FE + + + MEAS_NUM_LIMIT + need_des + 0 + 1 + read-write + + + MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + Register + 0x8 + 0x20 + + + FILTER_FACTOR1 + need_des + 26 + 3 + read-write + + + FILTER_FACTOR0 + need_des + 29 + 3 + read-write + + + + + FSM_WAIT + Register + 0xC + 0x20 + 0x00FF0808 + + + XPD_WAIT + need_des + 0 + 8 + read-write + + + RSTB_WAIT + need_des + 8 + 8 + read-write + + + STANDBY_WAIT + need_des + 16 + 8 + read-write + + + + + SAR1_STATUS + Register + 0x10 + 0x20 + + + SAR1_STATUS + 0 + 32 + read-only + + + + + SAR2_STATUS + Register + 0x14 + 0x20 + + + SAR2_STATUS + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + Register + 0x18 + 0x20 + + + SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + Register + 0x1C + 0x20 + + + SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + Register + 0x20 + 0x20 + + + SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + Register + 0x24 + 0x20 + + + SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + Register + 0x28 + 0x20 + + + SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + Register + 0x2C + 0x20 + + + SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + Register + 0x30 + 0x20 + + + SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + Register + 0x34 + 0x20 + + + SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + ARB_CTRL + Register + 0x38 + 0x20 + 0x00000900 + + + ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + Register + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + need_des + 14 + 5 + read-write + + + FILTER_CHANNEL0 + apb_adc1_filter_factor + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1_DATA_STATUS + Register + 0x40 + 0x20 + + + APB_SARADC1_DATA + need_des + 0 + 17 + read-only + + + + + THRES0_CTRL + Register + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + need_des + 0 + 5 + read-write + + + THRES0_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES0_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + Register + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + need_des + 0 + 5 + read-write + + + THRES1_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES1_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + Register + 0x4C + 0x20 + + + THRES_ALL_EN + need_des + 27 + 1 + read-write + + + THRES3_EN + need_des + 28 + 1 + read-write + + + THRES2_EN + need_des + 29 + 1 + read-write + + + THRES1_EN + need_des + 30 + 1 + read-write + + + THRES0_EN + need_des + 31 + 1 + read-write + + + + + INT_ENA + Register + 0x50 + 0x20 + + + THRES1_LOW_INT_ENA + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_ENA + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_RAW + Register + 0x54 + 0x20 + + + THRES1_LOW_INT_RAW + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_RAW + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_RAW + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_RAW + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_RAW + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + Register + 0x58 + 0x20 + + + THRES1_LOW_INT_ST + need_des + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + need_des + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + need_des + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + need_des + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + need_des + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_CLR + Register + 0x5C + 0x20 + + + THRES1_LOW_INT_CLR + need_des + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + need_des + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + need_des + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + need_des + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + need_des + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + need_des + 31 + 1 + write-only + + + + + DMA_CONF + Register + 0x60 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + SAR2_DATA_STATUS + Register + 0x64 + 0x20 + + + APB_SARADC2_DATA + need_des + 0 + 17 + read-only + + + + + CALI + Register + 0x68 + 0x20 + 0x00008000 + + + CFG + need_des + 0 + 17 + read-write + + + + + RND_ECO_LOW + Register + 0x6C + 0x20 + + + RND_ECO_LOW + rnd eco low + 0 + 32 + read-write + + + + + RND_ECO_HIGH + Register + 0x70 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + rnd eco high + 0 + 32 + read-write + + + + + RND_ECO_CS + Register + 0x74 + 0x20 + + + RND_ECO_EN + need_des + 0 + 1 + read-write + + + RND_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + CTRL_DATE + Register + 0x3FC + 0x20 + 0x02212260 + + + CTRL_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x50090000 + + 0x0 + 0xBC + registers + + + AES + 69 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 4 + 0x4 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x20 + + + 4 + 0x4 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x20 + + + 4 + 0x4 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x20 + + + 4 + 0x4 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x20 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + AHB_DMA + AHB_DMA Peripheral + AHB_DMA + 0x50085000 + + 0x0 + 0x2C4 + registers + + + AHB_PDMA_IN_CH0 + 56 + + + AHB_PDMA_IN_CH1 + 57 + + + AHB_PDMA_IN_CH2 + 58 + + + AHB_PDMA_OUT_CH0 + 59 + + + AHB_PDMA_OUT_CH1 + 60 + + + AHB_PDMA_OUT_CH2 + 61 + + + AXI_PDMA_IN_CH0 + 62 + + + AXI_PDMA_IN_CH1 + 63 + + + AXI_PDMA_IN_CH2 + 64 + + + AXI_PDMA_OUT_CH0 + 65 + + + AXI_PDMA_OUT_CH1 + 66 + + + AXI_PDMA_OUT_CH2 + 67 + + + + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + + + AHB_TEST + reserved + 0x60 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + MISC register + 0x64 + 0x20 + + + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 + 1 + read-write + + + + + DATE + Version control register + 0x68 + 0x20 + 0x02303140 + + + DATE + register version. + 0 + 32 + read-write + + + + + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 + 0x20 + + + IN_RST_CH + This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA. + 4 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 5 + 1 + read-write + + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 27 + 1 + read-only + + + + + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from AHB_DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from AHB_DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 + 0x20 + 0x00000011 + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 0 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + + + + + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy + 0 + 6 + read-write + + + + + OUT_CONF0_CH0 + Configure 0 register of Tx channel 0 + 0xD0 + 0x20 + 0x00000008 + + + OUT_RST_CH0 + This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH0 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task. + 6 + 1 + read-write + + + + + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL_CH + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + + + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AHB_DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into AHB_DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 + 0x20 + 0x00000008 + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 0 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 1 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 + read-only + + + + + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC + 0x20 + + + TX_PRI_CH + The priority of Tx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy + 0 + 6 + read-write + + + + + 2 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 + 0x20 + 0x00000008 + + + OUT_RST_CH + This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. + 6 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x2BC + 0x20 + 0xFFFFFFFF + + + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x2C0 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x2C4 + 0x20 + + + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x2C8 + 0x20 + + + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x28 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x2CC + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x2D0 + 0x20 + + + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x2D4 + 0x20 + + + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 8 + read-write + + + + + 3 + 0x28 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x2D8 + 0x20 + + + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x2DC + 0x20 + + + TX_CH_ARB_WEIGH_CH + reserved + 0 + 4 + read-write + + + + + 3 + 0x28 + TX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x2E0 + 0x20 + + + TX_ARB_WEIGH_OPT_DIR_CH + reserved + 0 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x334 + 0x20 + 0xFFFFFFFF + + + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x338 + 0x20 + + + RX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x33C + 0x20 + + + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result + 0 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x340 + 0x20 + + + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx + 0 + 32 + read-only + + + + + 3 + 0x28 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x344 + 0x20 + + + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x348 + 0x20 + + + RX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x34C + 0x20 + + + RX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 8 + read-write + + + + + 3 + 0x28 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x350 + 0x20 + + + RX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x354 + 0x20 + + + RX_CH_ARB_WEIGH_CH + reserved + 0 + 4 + read-write + + + + + 3 + 0x28 + RX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x358 + 0x20 + + + RX_ARB_WEIGH_OPT_DIR_CH + reserved + 0 + 1 + read-write + + + + + 3 + 0x4 + IN_LINK_ADDR_CH%s + Link descriptor configure of Rx channel 0 + 0x3AC + 0x20 + + + INLINK_ADDR_CH + This register stores the 32 least significant bits of the first inlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x4 + OUT_LINK_ADDR_CH%s + Link descriptor configure of Tx channel 0 + 0x3B8 + 0x20 + + + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x3C4 + 0x20 + + + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x3C8 + 0x20 + 0xFFFFFFFF + + + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + ARB_TIMEOUT_TX + This retister is used to config arbiter time slice for tx dir + 0x3CC + 0x20 + + + ARB_TIMEOUT_TX + This register is used to config arbiter time out value + 0 + 16 + read-write + + + + + ARB_TIMEOUT_RX + This retister is used to config arbiter time slice for rx dir + 0x3D0 + 0x20 + + + ARB_TIMEOUT_RX + This register is used to config arbiter time out value + 0 + 16 + read-write + + + + + WEIGHT_EN_TX + This register is used to config arbiter weigh function to on or off for tx dir + 0x3D4 + 0x20 + + + WEIGHT_EN_TX + This register is used to config arbiter weight function off/on + 0 + 1 + read-write + + + + + WEIGHT_EN_RX + This register is used to config arbiter weigh function to on or off for rx dir + 0x3D8 + 0x20 + + + WEIGHT_EN_RX + This register is used to config arbiter weight function off/on + 0 + 1 + read-write + + + + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + ANA_I2C_MST + 0x50124000 + + 0x0 + 0x3C + registers + + + + I2C0_CTRL + need des + 0x0 + 0x20 + + + I2C0_CTRL + need des + 0 + 25 + read-write + + + I2C0_BUSY + need des + 25 + 1 + read-only + + + + + I2C1_CTRL + need des + 0x4 + 0x20 + + + I2C1_CTRL + need des + 0 + 25 + read-write + + + I2C1_BUSY + need des + 25 + 1 + read-only + + + + + I2C0_CONF + need des + 0x8 + 0x20 + + + I2C0_CONF + need des + 0 + 24 + read-write + + + I2C0_STATUS + need des + 24 + 8 + read-only + + + + + I2C1_CONF + need des + 0xC + 0x20 + + + I2C1_CONF + need des + 0 + 24 + read-write + + + I2C1_STATUS + need des + 24 + 8 + read-only + + + + + I2C_BURST_CONF + need des + 0x10 + 0x20 + + + I2C_MST_BURST_CTRL + need des + 0 + 32 + read-write + + + + + I2C_BURST_STATUS + need des + 0x14 + 0x20 + 0x40000000 + + + I2C_MST_BURST_DONE + need des + 0 + 1 + read-only + + + I2C_MST0_BURST_ERR_FLAG + need des + 1 + 1 + read-only + + + I2C_MST1_BURST_ERR_FLAG + need des + 2 + 1 + read-only + + + I2C_MST_BURST_TIMEOUT_CNT + need des + 20 + 12 + read-write + + + + + ANA_CONF0 + need des + 0x18 + 0x20 + + + ANA_CONF0 + need des + 0 + 24 + read-write + + + ANA_STATUS0 + need des + 24 + 8 + read-only + + + + + ANA_CONF1 + need des + 0x1C + 0x20 + + + ANA_CONF1 + need des + 0 + 24 + read-write + + + ANA_STATUS1 + need des + 24 + 8 + read-only + + + + + ANA_CONF2 + need des + 0x20 + 0x20 + + + ANA_CONF2 + need des + 0 + 24 + read-write + + + ANA_STATUS2 + need des + 24 + 8 + read-only + + + + + I2C0_CTRL1 + need des + 0x24 + 0x20 + 0x00000042 + + + I2C0_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C0_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + I2C1_CTRL1 + need des + 0x28 + 0x20 + 0x00000042 + + + I2C1_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C1_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + HW_I2C_CTRL + need des + 0x2C + 0x20 + 0x00000042 + + + HW_I2C_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + HW_I2C_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + ARBITER_DIS + need des + 11 + 1 + read-write + + + + + NOUSE + need des + 0x30 + 0x20 + + + I2C_MST_NOUSE + need des + 0 + 32 + read-write + + + + + CLK160M + need des + 0x34 + 0x20 + + + CLK_I2C_MST_SEL_160M + need des + 0 + 1 + read-write + + + + + DATE + need des + 0x38 + 0x20 + 0x02201300 + + + DATE + need des + 0 + 28 + read-write + + + I2C_MST_CLK_EN + need des + 28 + 1 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x3FF06000 + + 0x0 + 0x100 + registers + + + ASSIST_DEBUG + 127 + + + + CORE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_1_INTR_ENA + core1 monitor enable configuration register + 0x80 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_RAW + core1 monitor interrupt status register + 0x84 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTR_RLS + core1 monitor interrupt enable register + 0x88 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_CLR + core1 monitor interrupt clr register + 0x8C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_1_AREA_DRAM0_0_MIN + core1 dram0 region0 addr configuration register + 0x90 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + core1 dram0 region0 addr configuration register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + core1 dram0 region1 addr configuration register + 0x98 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + core1 dram0 region1 addr configuration register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + core1 PIF region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + core1 PIF region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + core1 PIF region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + core1 PIF region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + core1 area pc status register + 0xB0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + core1 area sp status register + 0xB4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_MIN + stack min value + 0xB8 + 0x20 + + + CORE_1_SP_MIN + core1 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + stack max value + 0xBC + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + core1 sp pc status register + 0 + 32 + read-write + + + + + CORE_1_SP_PC + stack monitor pc status register + 0xC0 + 0x20 + + + CORE_1_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_1_RCD_EN + record enable configuration register + 0xC4 + 0x20 + + + CORE_1_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_1_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGPC + record status regsiter + 0xC8 + 0x20 + + + CORE_1_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSP + record status regsiter + 0xCC + 0x20 + + + CORE_1_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0xD0 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + reg_core_1_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + reg_core_1_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + reg_core_1_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0xD4 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + reg_core_1_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + reg_core_1_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + reg_core_1_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0xD8 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_0 + reg_core_1_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + reg_core_1_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0xDC + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + reg_core_1_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0xE0 + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_0 + reg_core_1_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0xE4 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_1 + reg_core_1_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + reg_core_1_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0xE8 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + reg_core_1_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0xEC + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_1 + reg_core_1_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_1_LASTPC_BEFORE_EXCEPTION + cpu status register + 0xF0 + 0x20 + + + CORE_1_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_1_DEBUG_MODE + cpu status register + 0xF4 + 0x20 + + + CORE_1_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_1_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x100 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x104 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + CLOCK_GATE + clock register + 0x108 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + AXI_DMA + AXI_DMA Peripheral + AXI_DMA + 0x5008A000 + + 0x0 + 0x2D8 + registers + + + + 3 + 0x68 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-only + + + + + 3 + 0x68 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + write-only + + + + + 3 + 0x68 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x10 + 0x20 + + + IN_RST_CH + This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. + 2 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 3 + 1 + read-write + + + IN_BURST_SIZE_SEL_CH + 3'b000-3'b100:burst length 8byte~128byte + 4 + 3 + read-write + + + IN_CMD_DISABLE_CH + 1:mean disable cmd of this ch0 + 7 + 1 + read-write + + + IN_ECC_AEC_EN_CH + 1: mean access ecc or aes domain,0: mean not + 8 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 9 + 1 + read-write + + + + + 3 + 0x68 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x14 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x00008803 + + + INFIFO_L3_FULL_CH + L3 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_L3_EMPTY_CH + L3 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + INFIFO_L3_UDF_CH + L3 Rx FIFO under flow signal for Rx channel 0. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH + L3 Rx FIFO over flow signal for Rx channel 0. + 9 + 1 + read-only + + + INFIFO_L1_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 10 + 1 + read-only + + + INFIFO_L1_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 11 + 1 + read-only + + + INFIFO_L1_UDF_CH + L1 Rx FIFO under flow signal for Rx channel 0. + 12 + 1 + read-only + + + INFIFO_L1_OVF_CH + L1 Rx FIFO over flow signal for Rx channel 0. + 13 + 1 + read-only + + + INFIFO_L2_FULL_CH + L2 Rx RAM full signal for Rx channel 0. + 14 + 1 + read-only + + + INFIFO_L2_EMPTY_CH + L2 Rx RAM empty signal for Rx channel 0. + 15 + 1 + read-only + + + INFIFO_L2_UDF_CH + L2 Rx FIFO under flow signal for Rx channel 0. + 16 + 1 + read-only + + + INFIFO_L2_OVF_CH + L2 Rx FIFO over flow signal for Rx channel 0. + 17 + 1 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + IN_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + IN_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + IN_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 31 + 1 + read-only + + + + + 3 + 0x68 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from AXI_DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from AXI_DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0x68 + IN_LINK1_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x00000011 + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 0 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + + + + + 3 + 0x68 + IN_LINK2_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x24 + 0x20 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x28 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x2C + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x30 + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x3C + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x40 + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + RX_CH_ARB_WEIGH_CH + The weight of Rx channel 0 + 4 + 4 + read-write + + + RX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x44 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x48 + 0x20 + 0xFFFFFFFF + + + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x4C + 0x20 + + + RX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x50 + 0x20 + + + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x54 + 0x20 + + + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx + 0 + 32 + read-only + + + + + 3 + 0x68 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x58 + 0x20 + + + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x5C + 0x20 + + + RX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x60 + 0x20 + + + RX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x64 + 0x20 + + + RX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_INT_RAW_CH%s + Raw status interrupt of channel0 + 0x138 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_ST_CH%s + Masked interrupt of channel0 + 0x13C + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUTFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + OUTFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 3 + 0x68 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel0 + 0x140 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel0 + 0x144 + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUTFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + OUTFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + OUT_CONF0_CH0 + Configure 0 register of Tx channel0 + 0x148 + 0x20 + 0x00000008 + + + OUT_RST_CH0 + This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH0 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH0 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH0 + 1:mean disable cmd of this ch0 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH0 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + 3 + 0x68 + OUT_CONF1_CH%s + Configure 1 register of Tx channel0 + 0x14C + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel0 + 0x150 + 0x20 + 0x7F808802 + + + OUTFIFO_L3_FULL_CH + L3 Tx FIFO full signal for Tx channel0. + 0 + 1 + read-only + + + OUTFIFO_L3_EMPTY_CH + L3 Tx FIFO empty signal for Tx channel0. + 1 + 1 + read-only + + + OUTFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. + 2 + 6 + read-only + + + OUTFIFO_L3_UDF_CH + L3 Tx FIFO under flow signal for Tx channel0. + 8 + 1 + read-only + + + OUTFIFO_L3_OVF_CH + L3 Tx FIFO over flow signal for Tx channel0. + 9 + 1 + read-only + + + OUTFIFO_L1_FULL_CH + L1 Tx FIFO full signal for Tx channel0. + 10 + 1 + read-only + + + OUTFIFO_L1_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel0. + 11 + 1 + read-only + + + OUTFIFO_L1_UDF_CH + L1 Tx FIFO under flow signal for Tx channel0. + 12 + 1 + read-only + + + OUTFIFO_L1_OVF_CH + L1 Tx FIFO over flow signal for Tx channel0. + 13 + 1 + read-only + + + OUTFIFO_L2_FULL_CH + L2 Tx RAM full signal for Tx channel0. + 14 + 1 + read-only + + + OUTFIFO_L2_EMPTY_CH + L2 Tx RAM empty signal for Tx channel0. + 15 + 1 + read-only + + + OUTFIFO_L2_UDF_CH + L2 Tx FIFO under flow signal for Tx channel0. + 16 + 1 + read-only + + + OUTFIFO_L2_OVF_CH + L2 Tx FIFO over flow signal for Tx channel0. + 17 + 1 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + OUT_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + OUT_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + OUT_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + OUT_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + + + 3 + 0x68 + OUT_PUSH_CH%s + Push control register of Tx channel0 + 0x154 + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AXI_DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into AXI_DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0x68 + OUT_LINK1_CH%s + Link descriptor configure and control register of Tx channel0 + 0x158 + 0x20 + 0x00000008 + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 0 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 1 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 + read-only + + + + + 3 + 0x68 + OUT_LINK2_CH%s + Link descriptor configure and control register of Tx channel0 + 0x15C + 0x20 + + + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_STATE_CH%s + Transmit status of Tx channel0 + 0x160 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel0 + 0x164 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel0 + 0x168 + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_CH%s + Current outlink descriptor address of Tx channel0 + 0x16C + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF0_CH%s + The last outlink descriptor address of Tx channel0 + 0x170 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF1_CH%s + The second-to-last outlink descriptor address of Tx channel0 + 0x174 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last outlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_PRI_CH%s + Priority register of Tx channel0. + 0x178 + 0x20 + + + TX_PRI_CH + The priority of Tx channel0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + TX_CH_ARB_WEIGH_CH + The weight of Tx channel0 + 4 + 4 + read-write + + + TX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel0 + 0x17C + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x180 + 0x20 + 0xFFFFFFFF + + + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x184 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x188 + 0x20 + + + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x18C + 0x20 + + + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x68 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x190 + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x194 + 0x20 + + + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x198 + 0x20 + + + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x19C + 0x20 + + + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + OUT_CONF0_CH1 + Configure 0 register of Tx channel1 + 0x1B0 + 0x20 + 0x00000008 + + + OUT_RST_CH1 + This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH1 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH1 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH1 + 1:mean disable cmd of this ch1 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH1 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + OUT_CONF0_CH2 + Configure 0 register of Tx channel2 + 0x218 + 0x20 + 0x00000008 + + + OUT_RST_CH2 + This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH2 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH2 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH2 + 1:mean disable cmd of this ch2 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH2 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + ARB_TIMEOUT + This retister is used to config arbiter time slice + 0x270 + 0x20 + + + TX + This register is used to config tx arbiter time out value + 0 + 16 + read-write + + + RX + This register is used to config rx arbiter time out value + 16 + 16 + read-write + + + + + WEIGHT_EN + This register is used to config arbiter weight function to on or off + 0x274 + 0x20 + + + TX + This register is used to config tx arbiter weight function off/on + 0 + 1 + read-write + + + RX + This register is used to config rx arbiter weight function off/on + 1 + 1 + read-write + + + + + IN_MEM_CONF + Mem power configure register of Rx channel + 0x278 + 0x20 + + + IN_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 0 + 1 + read-write + + + IN_MEM_FORCE_PU + Force power up ram + 1 + 1 + read-write + + + IN_MEM_FORCE_PD + Force power down ram + 2 + 1 + read-write + + + OUT_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 3 + 1 + read-write + + + OUT_MEM_FORCE_PU + Force power up ram + 4 + 1 + read-write + + + OUT_MEM_FORCE_PD + Force power down ram + 5 + 1 + read-write + + + + + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x27C + 0x20 + 0x30100000 + + + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x280 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTR_MEM_START_ADDR + The start address of accessible address space. + 0x284 + 0x20 + 0x30100000 + + + ACCESS_EXTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x288 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + 3 + 0x4 + IN_RESET_AVAIL_CH%s + The rx channel 0 reset valid_flag register. + 0x28C + 0x20 + 0x00000001 + + + IN_RESET_AVAIL_CH + rx chan0 reset valid reg. + 0 + 1 + read-only + + + + + 3 + 0x4 + OUT_RESET_AVAIL_CH%s + The tx channel 0 reset valid_flag register. + 0x298 + 0x20 + 0x00000001 + + + OUT_RESET_AVAIL_CH + tx chan0 reset valid reg. + 0 + 1 + read-only + + + + + MISC_CONF + MISC register + 0x2A8 + 0x20 + + + AXIM_RST_WR_INTER + Set this bit then clear this bit to reset the internal axi_wr FSM. + 0 + 1 + read-write + + + AXIM_RST_RD_INTER + Set this bit then clear this bit to reset the internal axi_rd FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + RDN_RESULT + reserved + 0x2AC + 0x20 + + + RDN_ENA + reserved + 0 + 1 + read-write + + + RDN_RESULT + reserved + 1 + 1 + read-only + + + + + RDN_ECO_HIGH + reserved + 0x2B0 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + The start address of accessible address space. + 0 + 32 + read-write + + + + + RDN_ECO_LOW + reserved + 0x2B4 + 0x20 + + + RDN_ECO_LOW + The start address of accessible address space. + 0 + 32 + read-write + + + + + WRESP_CNT + AXI wr responce cnt register. + 0x2B8 + 0x20 + + + WRESP_CNT + axi wr responce cnt reg. + 0 + 4 + read-only + + + + + RRESP_CNT + AXI wr responce cnt register. + 0x2BC + 0x20 + + + RRESP_CNT + axi rd responce cnt reg. + 0 + 4 + read-only + + + + + 3 + 0x4 + INFIFO_STATUS1_CH%s + Receive FIFO status of Rx channel 0 + 0x2C0 + 0x20 + + + L1INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 0 + 6 + read-only + + + L2INFIFO_CNT_CH + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 6 + 4 + read-only + + + + + 3 + 0x4 + OUTFIFO_STATUS1_CH%s + Receive FIFO status of Tx channel 0 + 0x2CC + 0x20 + + + L1OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 0 + 6 + read-only + + + L2OUTFIFO_CNT_CH + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 6 + 4 + read-only + + + + + DATE + Version control register + 0x2D8 + 0x20 + 0x02303140 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + BITSCRAMBLER + BITSCRAMBLER Peripheral + BITSCRAMBLER + 0x500A3000 + + 0x0 + 0x40 + registers + + + + TX_INST_CFG0 + Control and configuration registers + 0x0 + 0x20 + + + TX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + TX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + TX_INST_CFG1 + Control and configuration registers + 0x4 + 0x20 + 0x00000004 + + + TX_INST + write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG + 0 + 32 + read-write + + + + + RX_INST_CFG0 + Control and configuration registers + 0x8 + 0x20 + + + RX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + RX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + RX_INST_CFG1 + Control and configuration registers + 0xC + 0x20 + 0x0000000C + + + RX_INST + write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG + 0 + 32 + read-write + + + + + TX_LUT_CFG0 + Control and configuration registers + 0x10 + 0x20 + + + TX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode + 0 + 11 + read-write + + + TX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + TX_LUT_CFG1 + Control and configuration registers + 0x14 + 0x20 + 0x00000014 + + + TX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + RX_LUT_CFG0 + Control and configuration registers + 0x18 + 0x20 + + + RX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode + 0 + 11 + read-write + + + RX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + RX_LUT_CFG1 + Control and configuration registers + 0x1C + 0x20 + 0x0000001C + + + RX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + TX_TAILING_BITS + Control and configuration registers + 0x20 + 0x20 + + + TX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + RX_TAILING_BITS + Control and configuration registers + 0x24 + 0x20 + + + RX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + TX_CTRL + Control and configuration registers + 0x28 + 0x20 + 0x00000004 + + + TX_ENA + write this bit to enable the bitscrambler tx + 0 + 1 + read-write + + + TX_PAUSE + write this bit to pause the bitscrambler tx core + 1 + 1 + read-write + + + TX_HALT + write this bit to halt the bitscrambler tx core + 2 + 1 + read-write + + + TX_EOF_MODE + write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer + 3 + 1 + read-write + + + TX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + TX_FETCH_MODE + write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + TX_HALT_MODE + write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + TX_RD_DUMMY + write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + TX_FIFO_RST + write this bit to reset the bitscrambler tx fifo + 8 + 1 + write-only + + + + + RX_CTRL + Control and configuration registers + 0x2C + 0x20 + 0x00000004 + + + RX_ENA + write this bit to enable the bitscrambler rx + 0 + 1 + read-write + + + RX_PAUSE + write this bit to pause the bitscrambler rx core + 1 + 1 + read-write + + + RX_HALT + write this bit to halt the bitscrambler rx core + 2 + 1 + read-write + + + RX_EOF_MODE + write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo + 3 + 1 + read-write + + + RX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + RX_FETCH_MODE + write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + RX_HALT_MODE + write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + RX_RD_DUMMY + write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + RX_FIFO_RST + write this bit to reset the bitscrambler rx fifo + 8 + 1 + write-only + + + + + TX_STATE + Status registers + 0x30 + 0x20 + 0x00000001 + + + TX_IN_IDLE + represents the bitscrambler tx core in halt mode + 0 + 1 + read-only + + + TX_IN_RUN + represents the bitscrambler tx core in run mode + 1 + 1 + read-only + + + TX_IN_WAIT + represents the bitscrambler tx core in wait mode to wait write back done + 2 + 1 + read-only + + + TX_IN_PAUSE + represents the bitscrambler tx core in pause mode + 3 + 1 + read-only + + + TX_FIFO_EMPTY + represents the bitscrambler tx fifo in empty state + 4 + 1 + read-only + + + TX_EOF_GET_CNT + represents the bytes numbers of bitscrambler tx core when get EOF + 16 + 14 + read-only + + + TX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler tx core + 30 + 1 + read-only + + + TX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers + 31 + 1 + write-only + + + + + RX_STATE + Status registers + 0x34 + 0x20 + 0x00000001 + + + RX_IN_IDLE + represents the bitscrambler rx core in halt mode + 0 + 1 + read-only + + + RX_IN_RUN + represents the bitscrambler rx core in run mode + 1 + 1 + read-only + + + RX_IN_WAIT + represents the bitscrambler rx core in wait mode to wait write back done + 2 + 1 + read-only + + + RX_IN_PAUSE + represents the bitscrambler rx core in pause mode + 3 + 1 + read-only + + + RX_FIFO_FULL + represents the bitscrambler rx fifo in full state + 4 + 1 + read-only + + + RX_EOF_GET_CNT + represents the bytes numbers of bitscrambler rx core when get EOF + 16 + 14 + read-only + + + RX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler rx core + 30 + 1 + read-only + + + RX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers + 31 + 1 + write-only + + + + + SYS + Control and configuration registers + 0xF8 + 0x20 + + + LOOP_MODE + write this bit to set the bitscrambler tx loop back to DMA rx + 0 + 1 + read-write + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Control and configuration registers + 0xFC + 0x20 + 0x02303240 + + + BITSCRAMBLER_VER + Reserved + 0 + 28 + read-write + + + + + + + CACHE + CACHE Peripheral + CACHE + 0x3FF10000 + + 0x0 + 0x3F0 + registers + + + CACHE + 83 + + + + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 + 0x20 + + + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS2 + Reserved + 2 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS3 + Reserved + 3 + 1 + read-only + + + L1_ICACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_DCACHE_CTRL + L1 data Cache(L1-DCache) control register + 0x4 + 0x20 + + + L1_DCACHE_SHUT_DBUS0 + The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS1 + The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_DCACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SHUT_DMA + The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable + 4 + 1 + read-write + + + L1_DCACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 + 0x20 + + + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + 0 + 1 + read-write + + + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + 1 + 1 + read-write + + + BYPASS_L1_ICACHE2_EN + Reserved + 2 + 1 + read-only + + + BYPASS_L1_ICACHE3_EN + Reserved + 3 + 1 + read-only + + + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 + 1 + read-write + + + + + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC + 0x20 + 0x00000001 + + + L1_DCACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. + 0 + 1 + read-write + + + + + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 + 0x20 + 0x00000040 + + + L1_ICACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 + 0x20 + 0x00000008 + + + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_DCACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 + 0x20 + 0x00000100 + + + L1_DCACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_DCACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_DCACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_DCACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_DCACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_DCACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_DCACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C + 0x20 + 0x00000008 + + + L1_DCACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 + 0x20 + + + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. + 0 + 1 + read-write + + + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 + read-write + + + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_DCACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 + 0x20 + 0x00055555 + + + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 + 0x20 + 0x00055555 + + + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C + 0x20 + + + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + 0 + 1 + read-write + + + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 1 + 1 + read-write + + + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + 4 + 1 + read-write + + + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 + 1 + read-write + + + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 + 1 + read-only + + + L1_ICACHE2_FREEZE_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_FREEZE_MODE + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_FREEZE_DONE + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_FREEZE_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_FREEZE_MODE + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_FREEZE_DONE + Reserved + 14 + 1 + read-only + + + L1_DCACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. + 16 + 1 + read-write + + + L1_DCACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 + 1 + read-write + + + L1_DCACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only + + + + + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 + 0x20 + 0x00033333 + + + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 + 0x20 + 0x00033333 + + + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 + 1 + read-write + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_DCACHE_PRELOCK_CONF + L1 data Cache prelock configure register + 0x78 + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-DCache. + 0 + 1 + read-write + + + L1_DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-DCache. + 1 + 1 + read-write + + + L1_DCACHE_PRELOCK_RGID + The bit is used to set the gid of l1 dcache prelock. + 2 + 4 + read-write + + + + + L1_DCACHE_PRELOCK_SCT0_ADDR + L1 data Cache prelock section0 address configure register + 0x7C + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 data Cache prelock section1 address configure register + 0x80 + 0x20 + + + L1_DCACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT_SIZE + L1 data Cache prelock section size configure register + 0x84 + 0x20 + 0x3FFF3FFF + + + L1_DCACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_DCACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 + 0x20 + 0x00000004 + + + LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. + 0 + 1 + read-write + + + UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. + 1 + 1 + read-write + + + LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-write + + + + + LOCK_MAP + Lock (manual lock) map configure register + 0x8C + 0x20 + + + LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + LOCK_ADDR + Lock (manual lock) address configure register + 0x90 + 0x20 + + + LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + 0 + 32 + read-write + + + + + LOCK_SIZE + Lock (manual lock) size configure register + 0x94 + 0x20 + + + LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + 0 + 16 + read-write + + + + + SYNC_CTRL + Sync-class operation control register + 0x98 + 0x20 + 0x00000001 + + + INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 0 + 1 + read-write + + + CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 + read-only + + + SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-write + + + + + SYNC_MAP + Sync map configure register + 0x9C + 0x20 + 0x0000001F + + + SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + SYNC_ADDR + Sync address configure register + 0xA0 + 0x20 + + + SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG + 0 + 32 + read-write + + + + + SYNC_SIZE + Sync size configure register + 0xA4 + 0x20 + + + SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG + 0 + 28 + read-write + + + + + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 + 0x20 + 0x00000002 + + + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-write + + + + + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC + 0x20 + + + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 + 0x20 + + + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 + 0x20 + 0x00000002 + + + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-write + + + + + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 + 0x20 + + + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC + 0x20 + + + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 + 0x20 + 0x00000002 + + + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 + read-only + + + + + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 + 0x20 + + + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 + 0x20 + + + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC + 0x20 + 0x00000002 + + + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 + read-only + + + + + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 + 0x20 + + + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 + 0x20 + + + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_DCACHE_PRELOAD_CTRL + L1 data Cache preload-operation control register + 0xD8 + 0x20 + 0x00000002 + + + L1_DCACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_DCACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_PRELOAD_RGID + The bit is used to set the gid of l1 dcache preload. + 3 + 4 + read-write + + + + + L1_DCACHE_PRELOAD_ADDR + L1 data Cache preload address configure register + 0xDC + 0x20 + + + L1_DCACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOAD_SIZE + L1 data Cache preload size configure register + 0xE0 + 0x20 + + + L1_DCACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 + 0x20 + 0x00000002 + + + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. + 8 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. + 9 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 + 0x20 + 0x00000002 + + + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C + 0x20 + 0x00000002 + + + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. + 8 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. + 9 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 + 0x20 + 0x00000002 + + + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + Reserved + 0 + 28 + read-only + + + + + L1_DCACHE_AUTOLOAD_CTRL + L1 data Cache autoload-operation control register + 0x134 + 0x20 + 0x00000002 + + + L1_DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_DCACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-DCache. + 8 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-DCache. + 9 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-DCache. + 10 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-DCache. + 11 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 dcache autoload. + 12 + 4 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + L1 data Cache autoload section 0 address configure register + 0x138 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + L1 data Cache autoload section 0 size configure register + 0x13C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + L1 data Cache autoload section 1 address configure register + 0x140 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + L1 data Cache autoload section 1 size configure register + 0x144 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + L1 data Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + L1 data Cache autoload section 2 size configure register + 0x14C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + L1 data Cache autoload section 1 address configure register + 0x150 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + L1 data Cache autoload section 1 size configure register + 0x154 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 + 0x20 + + + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ENA + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C + 0x20 + + + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + write-only + + + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + write-only + + + L1_IBUS2_OVF_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + write-only + + + L1_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 + 0x20 + + + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 + 1 + read-write + + + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 + 1 + read-write + + + L1_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-write + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 + 1 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 + 0x20 + + + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ST + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_ST + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x168 + 0x20 + + + L1_ICACHE0_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + L1_ICACHE1_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 1 + 1 + read-write + + + L1_ICACHE2_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 2 + 1 + read-write + + + L1_ICACHE3_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 3 + 1 + read-write + + + L1_DCACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x16C + 0x20 + + + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x170 + 0x20 + + + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + write-only + + + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + write-only + + + L1_ICACHE2_FAIL_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + write-only + + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x174 + 0x20 + + + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 + read-write + + + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 + read-write + + + L1_DCACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x178 + 0x20 + + + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x17C + 0x20 + + + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_CNT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_CNT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_CNT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_CNT_ENA + Reserved + 7 + 1 + read-only + + + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 + 1 + write-only + + + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 + 1 + write-only + + + L1_IBUS2_CNT_CLR + Reserved + 18 + 1 + read-only + + + L1_IBUS3_CNT_CLR + Reserved + 19 + 1 + read-only + + + L1_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 + 1 + write-only + + + L1_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 + 1 + write-only + + + L1_DBUS2_CNT_CLR + Reserved + 22 + 1 + read-only + + + L1_DBUS3_CNT_CLR + Reserved + 23 + 1 + read-only + + + + + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x180 + 0x20 + + + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x184 + 0x20 + + + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x188 + 0x20 + + + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_NXTLVL_RD_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x18C + 0x20 + + + L1_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x190 + 0x20 + + + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x194 + 0x20 + + + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x198 + 0x20 + + + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_NXTLVL_RD_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x19C + 0x20 + + + L1_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x1A0 + 0x20 + + + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A4 + 0x20 + + + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A8 + 0x20 + + + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_NXTLVL_RD_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1AC + 0x20 + + + L1_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1B0 + 0x20 + + + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B4 + 0x20 + + + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B8 + 0x20 + + + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_NXTLVL_RD_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1BC + 0x20 + + + L1_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_HIT_CNT + L1-DCache bus0 Hit-Access Counter register + 0x1C0 + 0x20 + + + L1_DBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_MISS_CNT + L1-DCache bus0 Miss-Access Counter register + 0x1C4 + 0x20 + + + L1_DBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_CONFLICT_CNT + L1-DCache bus0 Conflict-Access Counter register + 0x1C8 + 0x20 + + + L1_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_RD_CNT + L1-DCache bus0 Next-Level-Access Counter register + 0x1CC + 0x20 + + + L1_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_WR_CNT + L1-DCache bus0 WB-Access Counter register + 0x1D0 + 0x20 + + + L1_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_HIT_CNT + L1-DCache bus1 Hit-Access Counter register + 0x1D4 + 0x20 + + + L1_DBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_MISS_CNT + L1-DCache bus1 Miss-Access Counter register + 0x1D8 + 0x20 + + + L1_DBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_CONFLICT_CNT + L1-DCache bus1 Conflict-Access Counter register + 0x1DC + 0x20 + + + L1_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_RD_CNT + L1-DCache bus1 Next-Level-Access Counter register + 0x1E0 + 0x20 + + + L1_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_WR_CNT + L1-DCache bus1 WB-Access Counter register + 0x1E4 + 0x20 + + + L1_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1E8 + 0x20 + + + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1EC + 0x20 + + + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1F0 + 0x20 + + + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_RD_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1F4 + 0x20 + + + L1_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_WR_CNT + L1-DCache bus2 WB-Access Counter register + 0x1F8 + 0x20 + + + L1_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1FC + 0x20 + + + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x200 + 0x20 + + + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x204 + 0x20 + + + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_RD_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x208 + 0x20 + + + L1_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_WR_CNT + L1-DCache bus3 WB-Access Counter register + 0x20C + 0x20 + + + L1_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x210 + 0x20 + + + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x214 + 0x20 + + + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x218 + 0x20 + + + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x21C + 0x20 + + + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x220 + 0x20 + + + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x224 + 0x20 + + + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x228 + 0x20 + + + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x22C + 0x20 + + + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_DCACHE_ACS_FAIL_ID_ATTR + L1-DCache Access Fail ID/attribution information register + 0x230 + 0x20 + + + L1_DCACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-DCache. + 0 + 16 + read-only + + + L1_DCACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-DCache. + 16 + 16 + read-only + + + + + L1_DCACHE_ACS_FAIL_ADDR + L1-DCache Access Fail Address information register + 0x234 + 0x20 + + + L1_DCACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-DCache. + 0 + 32 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x238 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. + 4 + 1 + read-write + + + SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation error. + 11 + 1 + read-write + + + SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x23C + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + write-only + + + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + write-only + + + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + write-only + + + SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + write-only + + + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 + 1 + write-only + + + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + write-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-DCache preload-operation error. + 11 + 1 + write-only + + + SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x240 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_RAW + Reserved + 2 + 1 + read-write + + + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 + 1 + read-write + + + L1_DCACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-write + + + SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-write + + + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 + read-write + + + L1_DCACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. + 11 + 1 + read-write + + + SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x244 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-only + + + SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-DCache preload-operation error. + 11 + 1 + read-only + + + SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x248 + 0x20 + + + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. + 0 + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_DCACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-DCache. + 8 + 2 + read-only + + + SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only + + + + + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x24C + 0x20 + + + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SYNC_RST + set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x250 + 0x20 + + + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_RST + set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x254 + 0x20 + + + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. + 4 + 1 + read-write + + + + + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x258 + 0x20 + + + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + 0 + 1 + read-write + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-write + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. + 4 + 1 + read-write + + + + + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x25C + 0x20 + + + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_DCACHE_TAG_OBJECT + Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-write + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-write + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_DCACHE_MEM_OBJECT + Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 + read-write + + + + + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x260 + 0x20 + + + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L1_CACHE_VADDR + Cache Vaddr register + 0x264 + 0x20 + 0x40000000 + + + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x268 + 0x20 + 0x00000268 + + + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x26C + 0x20 + 0x0000026C + + + LEVEL_SPLIT0 + Reserved + 0 + 32 + read-only + + + + + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x270 + 0x20 + 0x00000010 + + + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-write + + + L2_CACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x274 + 0x20 + + + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 + read-write + + + + + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x278 + 0x20 + 0x00000400 + + + L2_CACHE_CACHESIZE_256 + The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_CACHESIZE_512 + The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-write + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-write + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-write + + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x27C + 0x20 + 0x00000008 + + + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x280 + 0x20 + + + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x284 + 0x20 + 0x00500000 + + + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x288 + 0x20 + 0x00500000 + + + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x28C + 0x20 + + + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 + read-write + + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-write + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x290 + 0x20 + 0x00300000 + + + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x294 + 0x20 + 0x00300000 + + + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x298 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. + 0 + 1 + read-write + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-write + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 + read-write + + + + + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x29C + 0x20 + + + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x2A0 + 0x20 + + + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x2A4 + 0x20 + 0xFFFFFFFF + + + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 16 + read-write + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 + read-write + + + + + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x2A8 + 0x20 + 0x00000002 + + + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 + read-write + + + + + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x2AC + 0x20 + + + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x2B0 + 0x20 + + + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + 0 + 16 + read-write + + + + + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2B4 + 0x20 + 0x00000002 + + + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-write + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2B8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2BC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2C0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2C4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2C8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2CC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2D0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2D4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2D8 + 0x20 + + + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2DC + 0x20 + + + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + write-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + write-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + write-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + write-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2E0 + 0x20 + + + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-write + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-write + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-write + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2E4 + 0x20 + + + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x2E8 + 0x20 + + + L2_CACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2EC + 0x20 + + + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2F0 + 0x20 + + + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + write-only + + + + + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2F4 + 0x20 + + + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2F8 + 0x20 + + + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2FC + 0x20 + + + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + write-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + write-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + write-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + write-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + + + + + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x300 + 0x20 + + + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x304 + 0x20 + + + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x308 + 0x20 + + + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x30C + 0x20 + + + L2_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x310 + 0x20 + + + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x314 + 0x20 + + + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x318 + 0x20 + + + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x31C + 0x20 + + + L2_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x320 + 0x20 + + + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x324 + 0x20 + + + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x328 + 0x20 + + + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x32C + 0x20 + + + L2_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x330 + 0x20 + + + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x334 + 0x20 + + + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x338 + 0x20 + + + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x33C + 0x20 + + + L2_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x340 + 0x20 + + + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x344 + 0x20 + + + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x348 + 0x20 + + + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x34C + 0x20 + + + L2_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_WR_CNT + L2-Cache bus0 WB-Access Counter register + 0x350 + 0x20 + + + L2_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x354 + 0x20 + + + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x358 + 0x20 + + + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x35C + 0x20 + + + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x360 + 0x20 + + + L2_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_WR_CNT + L2-Cache bus1 WB-Access Counter register + 0x364 + 0x20 + + + L2_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x368 + 0x20 + + + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x36C + 0x20 + + + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x370 + 0x20 + + + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x374 + 0x20 + + + L2_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_WR_CNT + L2-Cache bus2 WB-Access Counter register + 0x378 + 0x20 + + + L2_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x37C + 0x20 + + + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x380 + 0x20 + + + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x384 + 0x20 + + + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x388 + 0x20 + + + L2_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_WR_CNT + L2-Cache bus3 WB-Access Counter register + 0x38C + 0x20 + + + L2_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x390 + 0x20 + + + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. + 0 + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only + + + + + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x394 + 0x20 + + + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. + 0 + 32 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x398 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x39C + 0x20 + + + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + write-only + + + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + write-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x3A0 + 0x20 + + + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x3A4 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x3A8 + 0x20 + + + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only + + + + + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x3AC + 0x20 + + + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x3B0 + 0x20 + + + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x3B4 + 0x20 + + + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 + read-write + + + + + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x3B8 + 0x20 + + + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 + read-write + + + + + L2_CACHE_ACCESS_ATTR_CTRL + L2 cache access attribute control register + 0x3BC + 0x20 + 0x0000000F + + + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. + 0 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 + read-write + + + + + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x3C0 + 0x20 + + + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 + read-write + + + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 + read-write + + + + + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x3C4 + 0x20 + + + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L2_CACHE_VADDR + Cache Vaddr register + 0x3C8 + 0x20 + 0x40000000 + + + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3CC + 0x20 + 0x000003CC + + + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3D0 + 0x20 + 0x000003D0 + + + LEVEL_SPLIT1 + Reserved + 0 + 32 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x3D4 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3D8 + 0x20 + + + REDCY_SIG0 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3DC + 0x20 + + + REDCY_SIG1 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3E0 + 0x20 + + + REDCY_SIG2 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3E4 + 0x20 + + + REDCY_SIG3 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3E8 + 0x20 + + + REDCY_SIG4 + Those bits are prepared for ECO. + 0 + 4 + read-only + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02304130 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + CORE0 + 0x500D6000 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE0_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE0_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE0_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE0_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE0_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE0_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE0_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE0_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE0_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE0_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE0_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE0_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE0_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE0_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE0_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE0_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE0_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE0_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE0_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE0_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE0_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE0_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE0_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE0_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE0_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE0_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE0_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE0_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE0_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE0_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE0_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE0_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE0_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE0_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE0_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE0_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE0_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE0_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE0_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE0_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE0_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE0_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE0_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE0_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE0_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE0_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE0_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE0_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE0_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE0_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE0_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE0_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE0_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE0_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE0_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE0_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE0_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + CORE0_AHB_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + + + CORE0_AHB_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH0_INT_MAP + NA + 0xEC + 0x20 + + + CORE0_AHB_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + + + CORE0_AHB_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + + + CORE0_AHB_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + + + CORE0_AXI_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH1_INT_MAP + NA + 0xFC + 0x20 + + + CORE0_AXI_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + + + CORE0_AXI_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + + + CORE0_AXI_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE0_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE0_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE0_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE0_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE0_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE0_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE0_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE0_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE0_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE0_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE0_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE0_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE0_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE0_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE0_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE0_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + CORE0_CSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + + + CORE0_DSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + + + CORE0_CSI_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + + + CORE0_DSI_INT_MAP + NA + 0 + 6 + read-write + + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + + + CORE0_GMII_PHY_INT_MAP + NA + 0 + 6 + read-write + + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + + + CORE0_LPI_INT_MAP + NA + 0 + 6 + read-write + + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + + + CORE0_PMT_INT_MAP + NA + 0 + 6 + read-write + + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + + + CORE0_SBD_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + + + CORE0_USB_OTG_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + + + CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0 + 6 + read-write + + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + + + CORE0_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE0_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE0_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE0_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE0_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE0_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE0_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE0_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE0_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE0_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE0_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE0_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE0_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE0_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE0_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE0_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE0_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE0_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE0_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE0_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE0_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE0_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE0_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE0_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE0_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE0_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE0_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE0_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE0_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE0_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Controller (Core 1) + CORE1 + 0x500D6800 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE1_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE1_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE1_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE1_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE1_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE1_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE1_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE1_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE1_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE1_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE1_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE1_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE1_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE1_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE1_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE1_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE1_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE1_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE1_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE1_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE1_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE1_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE1_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE1_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE1_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE1_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE1_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE1_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE1_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE1_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE1_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE1_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE1_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE1_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE1_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE1_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE1_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE1_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE1_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE1_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE1_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE1_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE1_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE1_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE1_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE1_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE1_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE1_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE1_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE1_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE1_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE1_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE1_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE1_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE1_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE1_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE1_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + CORE1_AHB_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + + + CORE1_AHB_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH0_INT_MAP + NA + 0xEC + 0x20 + + + CORE1_AHB_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + + + CORE1_AXI_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH1_INT_MAP + NA + 0xFC + 0x20 + + + CORE1_AXI_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + + + CORE1_AXI_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE1_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE1_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE1_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE1_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE1_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE1_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE1_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE1_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE1_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE1_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE1_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE1_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE1_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE1_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE1_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + CORE1_CSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + + + CORE1_DSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + + + CORE1_CSI_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + + + CORE1_DSI_INT_MAP + NA + 0 + 6 + read-write + + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + + + CORE1_GMII_PHY_INT_MAP + NA + 0 + 6 + read-write + + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + + + CORE1_LPI_INT_MAP + NA + 0 + 6 + read-write + + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + + + CORE1_PMT_INT_MAP + NA + 0 + 6 + read-write + + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + + + CORE1_SBD_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + + + CORE1_USB_OTG_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + + + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0 + 6 + read-write + + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + + + CORE1_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE1_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE1_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE1_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE1_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE1_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE1_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE1_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE1_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE1_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE1_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE1_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE1_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE1_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE1_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE1_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE1_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE1_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE1_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE1_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE1_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE1_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE1_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE1_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE1_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE1_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE1_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE1_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE1_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE1_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + MIPI_CSI_BRIDGE + MIPI Camera Interface Bridge + CSI_BRIG + 0x5009F800 + + 0x0 + 0x48 + registers + + + CSI_BRIDGE + 85 + + + + CLK_EN + csi bridge register mapping unit clock gating. + 0x0 + 0x20 + + + CLK_EN + 0: enable clock gating. 1: disable clock gating, clock always on. + 0 + 1 + read-write + + + + + CSI_EN + csi bridge enable. + 0x4 + 0x20 + + + CSI_BRIG_EN + 0: disable csi bridge. 1: enable csi bridge. + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dma request configuration. + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + DMA burst length. + 0 + 12 + read-write + + + DMA_CFG_UPD_BY_BLK + 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. + 12 + 1 + read-write + + + DMA_FORCE_RD_STATUS + 1: mask dma request when reading frame info. 0: disable mask. + 16 + 1 + read-write + + + + + BUF_FLOW_CTL + csi bridge buffer control. + 0xC + 0x20 + 0x000007F8 + + + CSI_BUF_AFULL_THRD + buffer almost full threshold. + 0 + 14 + read-write + + + CSI_BUF_DEPTH + buffer data count. + 16 + 14 + read-only + + + + + DATA_TYPE_CFG + pixel data type configuration. + 0x10 + 0x20 + 0x00002F18 + + + DATA_TYPE_MIN + the min value of data type used for pixel filter. + 0 + 6 + read-write + + + DATA_TYPE_MAX + the max value of data type used for pixel filter. + 8 + 6 + read-write + + + + + FRAME_CFG + frame configuration. + 0x14 + 0x20 + 0x011E01E0 + + + VADR_NUM + vadr of frame data. + 0 + 12 + read-write + + + HADR_NUM + hadr of frame data. + 12 + 12 + read-write + + + HAS_HSYNC_E + 0: frame data doesn't contain hsync. 1: frame data contains hsync. + 24 + 1 + read-write + + + VADR_NUM_CHECK + 0: disable vadr check. 1: enable vadr check. + 25 + 1 + read-write + + + + + ENDIAN_MODE + data endianness order configuration. + 0x18 + 0x20 + + + BYTE_ENDIAN_ORDER + endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. + 0 + 1 + read-write + + + BIT_ENDIAN_ORDER + N/A + 1 + 1 + read-write + + + + + INT_RAW + csi bridge interrupt raw. + 0x1C + 0x20 + + + VADR_NUM_GT_INT_RAW + reg_vadr_num is greater than real interrupt raw. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_RAW + reg_vadr_num is less than real interrupt raw. + 1 + 1 + read-write + + + DISCARD_INT_RAW + an incomplete frame of data was sent interrupt raw. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_RAW + buffer overrun interrupt raw. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_RAW + buffer overflow interrupt raw. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_RAW + dma configuration update complete interrupt raw. + 5 + 1 + read-write + + + + + INT_CLR + csi bridge interrupt clr. + 0x20 + 0x20 + + + VADR_NUM_GT_REAL_INT_CLR + reg_vadr_num is greater than real interrupt clr. + 0 + 1 + write-only + + + VADR_NUM_LT_REAL_INT_CLR + reg_vadr_num is less than real interrupt clr. + 1 + 1 + write-only + + + DISCARD_INT_CLR + an incomplete frame of data was sent interrupt clr. + 2 + 1 + write-only + + + CSI_BUF_OVERRUN_INT_CLR + buffer overrun interrupt clr. + 3 + 1 + write-only + + + CSI_ASYNC_FIFO_OVF_INT_CLR + buffer overflow interrupt clr. + 4 + 1 + write-only + + + DMA_CFG_HAS_UPDATED_INT_CLR + dma configuration update complete interrupt clr. + 5 + 1 + write-only + + + + + INT_ST + csi bridge interrupt st. + 0x24 + 0x20 + + + VADR_NUM_GT_INT_ST + reg_vadr_num is greater than real interrupt st. + 0 + 1 + read-only + + + VADR_NUM_LT_INT_ST + reg_vadr_num is less than real interrupt st. + 1 + 1 + read-only + + + DISCARD_INT_ST + an incomplete frame of data was sent interrupt st. + 2 + 1 + read-only + + + CSI_BUF_OVERRUN_INT_ST + buffer overrun interrupt st. + 3 + 1 + read-only + + + CSI_ASYNC_FIFO_OVF_INT_ST + buffer overflow interrupt st. + 4 + 1 + read-only + + + DMA_CFG_HAS_UPDATED_INT_ST + dma configuration update complete interrupt st. + 5 + 1 + read-only + + + + + INT_ENA + csi bridge interrupt enable. + 0x28 + 0x20 + + + VADR_NUM_GT_INT_ENA + reg_vadr_num is greater than real interrupt enable. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_ENA + reg_vadr_num is less than real interrupt enable. + 1 + 1 + read-write + + + DISCARD_INT_ENA + an incomplete frame of data was sent interrupt enable. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_ENA + buffer overrun interrupt enable. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_ENA + buffer overflow interrupt enable. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_ENA + dma configuration update complete interrupt enable. + 5 + 1 + read-write + + + + + DMA_REQ_INTERVAL + DMA interval configuration. + 0x2C + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + 0 + 16 + read-write + + + + + DMABLK_SIZE + DMA block size configuration. + 0x30 + 0x20 + 0x00001FFF + + + DMABLK_SIZE + the number of reg_dma_burst_len in a block + 0 + 13 + read-write + + + + + RDN_ECO_CS + N/A + 0x34 + 0x20 + + + RDN_ECO_EN + N/A + 0 + 1 + read-write + + + RDN_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + RDN_ECO_LOW + N/A + 0x38 + 0x20 + + + RDN_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + N/A + 0x3C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + HOST_CTRL + csi host control by csi bridge. + 0x40 + 0x20 + 0x00000003 + + + CSI_ENABLECLK + enable clock lane module of csi phy. + 0 + 1 + read-write + + + CSI_CFG_CLK_EN + enable cfg_clk of csi host module. + 1 + 1 + read-write + + + LOOPBK_TEST_EN + for phy test by loopback dsi phy to csi phy. + 2 + 1 + read-write + + + + + MEM_CTRL + csi bridge buffer control. + 0x44 + 0x20 + 0x00002640 + + + CSI_BRIDGE_MEM_CLK_FORCE_ON + csi bridge memory clock gating force on. + 0 + 1 + read-write + + + CSI_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + + + + + MIPI_CSI_HOST + MIPI Camera Interface Host + CSI_HOST + 0x5009F000 + + 0x0 + 0xA8 + registers + + + CSI + 87 + + + + VERSION + NA + 0x0 + 0x20 + 0x3135302A + + + VERSION + NA + 0 + 32 + read-only + + + + + N_LANES + NA + 0x4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 3 + read-write + + + + + CSI2_RESETN + NA + 0x8 + 0x20 + + + CSI2_RESETN + NA + 0 + 1 + read-write + + + + + INT_ST_MAIN + NA + 0xC + 0x20 + + + ST_STATUS_INT_PHY_FATAL + NA + 0 + 1 + read-only + + + ST_STATUS_INT_PKT_FATAL + NA + 1 + 1 + read-only + + + ST_STATUS_INT_BNDRY_FRAME_FATAL + NA + 2 + 1 + read-only + + + ST_STATUS_INT_SEQ_FRAME_FATAL + NA + 3 + 1 + read-only + + + ST_STATUS_INT_CRC_FRAME_FATAL + NA + 4 + 1 + read-only + + + ST_STATUS_INT_PLD_CRC_FATAL + NA + 5 + 1 + read-only + + + ST_STATUS_INT_DATA_ID + NA + 6 + 1 + read-only + + + ST_STATUS_INT_ECC_CORRECTED + NA + 7 + 1 + read-only + + + ST_STATUS_INT_PHY + NA + 16 + 1 + read-only + + + + + PHY_SHUTDOWNZ + NA + 0x40 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + DPHY_RSTZ + NA + 0x44 + 0x20 + + + DPHY_RSTZ + NA + 0 + 1 + read-write + + + + + PHY_RX + NA + 0x48 + 0x20 + 0x00010000 + + + PHY_RXULPSESC_0 + NA + 0 + 1 + read-only + + + PHY_RXULPSESC_1 + NA + 1 + 1 + read-only + + + PHY_RXULPSCLKNOT + NA + 16 + 1 + read-only + + + PHY_RXCLKACTIVEHS + NA + 17 + 1 + read-only + + + + + PHY_STOPSTATE + NA + 0x4C + 0x20 + + + PHY_STOPSTATEDATA_0 + NA + 0 + 1 + read-only + + + PHY_STOPSTATEDATA_1 + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLK + NA + 16 + 1 + read-only + + + + + PHY_TEST_CTRL0 + NA + 0x50 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TEST_CTRL1 + NA + 0x54 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHY_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + VC_EXTENSION + NA + 0xC8 + 0x20 + + + VCX + NA + 0 + 1 + read-write + + + + + PHY_CAL + NA + 0xCC + 0x20 + + + RXSKEWCALHS + NA + 0 + 1 + read-only + + + + + INT_ST_PHY_FATAL + NA + 0xE0 + 0x20 + + + ST_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-only + + + ST_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-only + + + + + INT_MSK_PHY_FATAL + NA + 0xE4 + 0x20 + + + MASK_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-write + + + MASK_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-write + + + + + INT_FORCE_PHY_FATAL + NA + 0xE8 + 0x20 + + + FORCE_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-write + + + FORCE_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-write + + + + + INT_ST_PKT_FATAL + NA + 0xF0 + 0x20 + + + ST_ERR_ECC_DOUBLE + NA + 0 + 1 + read-only + + + ST_SHORTER_PAYLOAD + NA + 1 + 1 + read-only + + + + + INT_MSK_PKT_FATAL + NA + 0xF4 + 0x20 + + + MASK_ERR_ECC_DOUBLE + NA + 0 + 1 + read-write + + + MASK_SHORTER_PAYLOAD + NA + 1 + 1 + read-write + + + + + INT_FORCE_PKT_FATAL + NA + 0xF8 + 0x20 + + + FORCE_ERR_ECC_DOUBLE + NA + 0 + 1 + read-write + + + FORCE_SHORTER_PAYLOAD + NA + 1 + 1 + read-write + + + + + INT_ST_PHY + NA + 0x110 + 0x20 + + + ST_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-only + + + ST_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-only + + + ST_PHY_ERRESC_0 + NA + 16 + 1 + read-only + + + ST_PHY_ERRESC_1 + NA + 17 + 1 + read-only + + + + + INT_MSK_PHY + NA + 0x114 + 0x20 + + + MASK_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-write + + + MASK_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-write + + + MASK_PHY_ERRESC_0 + NA + 16 + 1 + read-write + + + MASK_PHY_ERRESC_1 + NA + 17 + 1 + read-write + + + + + INT_FORCE_PHY + NA + 0x118 + 0x20 + + + FORCE_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-write + + + FORCE_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-write + + + FORCE_PHY_ERRESC_0 + NA + 16 + 1 + read-write + + + FORCE_PHY_ERRESC_1 + NA + 17 + 1 + read-write + + + + + INT_ST_BNDRY_FRAME_FATAL + NA + 0x280 + 0x20 + + + ST_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_BNDRY_FRAME_FATAL + NA + 0x284 + 0x20 + + + MASK_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_BNDRY_FRAME_FATAL + NA + 0x288 + 0x20 + + + FORCE_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_SEQ_FRAME_FATAL + NA + 0x290 + 0x20 + + + ST_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_SEQ_FRAME_FATAL + NA + 0x294 + 0x20 + + + MASK_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_SEQ_FRAME_FATAL + NA + 0x298 + 0x20 + + + FORCE_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_CRC_FRAME_FATAL + NA + 0x2A0 + 0x20 + + + ST_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_CRC_FRAME_FATAL + NA + 0x2A4 + 0x20 + + + MASK_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_CRC_FRAME_FATAL + NA + 0x2A8 + 0x20 + + + FORCE_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_PLD_CRC_FATAL + NA + 0x2B0 + 0x20 + + + ST_ERR_CRC_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_CRC_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_CRC_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_CRC_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_CRC_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_CRC_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_CRC_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_CRC_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_CRC_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_CRC_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_CRC_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_CRC_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_CRC_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_CRC_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_CRC_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_CRC_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_PLD_CRC_FATAL + NA + 0x2B4 + 0x20 + + + MASK_ERR_CRC_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_CRC_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_CRC_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_CRC_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_CRC_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_CRC_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_CRC_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_CRC_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_CRC_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_CRC_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_CRC_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_CRC_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_CRC_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_CRC_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_CRC_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_CRC_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_PLD_CRC_FATAL + NA + 0x2B8 + 0x20 + + + FORCE_ERR_CRC_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_CRC_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_CRC_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_CRC_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_CRC_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_CRC_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_CRC_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_CRC_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_CRC_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_CRC_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_CRC_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_CRC_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_CRC_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_CRC_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_CRC_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_CRC_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_DATA_ID + NA + 0x2C0 + 0x20 + + + ST_ERR_ID_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_ID_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_ID_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_ID_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_ID_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_ID_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_ID_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_ID_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_ID_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_ID_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_ID_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_ID_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_ID_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_ID_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_ID_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_ID_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_DATA_ID + NA + 0x2C4 + 0x20 + + + MASK_ERR_ID_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_ID_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_ID_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_ID_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_ID_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_ID_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_ID_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_ID_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_ID_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_ID_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_ID_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_ID_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_ID_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_ID_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_ID_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_ID_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_DATA_ID + NA + 0x2C8 + 0x20 + + + FORCE_ERR_ID_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_ID_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_ID_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_ID_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_ID_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_ID_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_ID_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_ID_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_ID_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_ID_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_ID_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_ID_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_ID_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_ID_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_ID_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_ID_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_ECC_CORRECTED + NA + 0x2D0 + 0x20 + + + ST_ERR_ECC_CORRECTED_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_ECC_CORRECTED_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_ECC_CORRECTED + NA + 0x2D4 + 0x20 + + + MASK_ERR_ECC_CORRECTED_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_ECC_CORRECTED_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_ECC_CORRECTED + NA + 0x2D8 + 0x20 + + + FORCE_ERR_ECC_CORRECTED_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_ECC_CORRECTED_VC15 + NA + 15 + 1 + read-write + + + + + SCRAMBLING + NA + 0x300 + 0x20 + + + SCRAMBLE_ENABLE + NA + 0 + 1 + read-write + + + + + SCRAMBLING_SEED1 + NA + 0x304 + 0x20 + 0x00001008 + + + SCRAMBLE_SEED_LANE1 + NA + 0 + 16 + read-write + + + + + SCRAMBLING_SEED2 + NA + 0x308 + 0x20 + 0x00001188 + + + SCRAMBLE_SEED_LANE2 + NA + 0 + 16 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMAC + 0x50081000 + + 0x0 + 0x234 + registers + + + DMA + 24 + + + + ID0 + NA + 0x0 + 0x20 + + + DMAC_ID + NA + 0 + 32 + read-only + + + + + COMPVER0 + NA + 0x8 + 0x20 + 0x3230302A + + + DMAC_COMPVER + NA + 0 + 32 + read-only + + + + + CFG0 + NA + 0x10 + 0x20 + + + DMAC_EN + NA + 0 + 1 + read-write + + + INT_EN + NA + 1 + 1 + read-write + + + + + CHEN0 + NA + 0x18 + 0x20 + + + CH1_EN + NA + 0 + 1 + read-write + + + CH2_EN + NA + 1 + 1 + read-write + + + CH3_EN + NA + 2 + 1 + read-write + + + CH4_EN + NA + 3 + 1 + read-write + + + CH1_EN_WE + NA + 8 + 1 + write-only + + + CH2_EN_WE + NA + 9 + 1 + write-only + + + CH3_EN_WE + NA + 10 + 1 + write-only + + + CH4_EN_WE + NA + 11 + 1 + write-only + + + CH1_SUSP + NA + 16 + 1 + read-write + + + CH2_SUSP + NA + 17 + 1 + read-write + + + CH3_SUSP + NA + 18 + 1 + read-write + + + CH4_SUSP + NA + 19 + 1 + read-write + + + CH1_SUSP_WE + NA + 24 + 1 + write-only + + + CH2_SUSP_WE + NA + 25 + 1 + write-only + + + CH3_SUSP_WE + NA + 26 + 1 + write-only + + + CH4_SUSP_WE + NA + 27 + 1 + write-only + + + + + CHEN1 + NA + 0x1C + 0x20 + + + CH1_ABORT + NA + 0 + 1 + read-write + + + CH2_ABORT + NA + 1 + 1 + read-write + + + CH3_ABORT + NA + 2 + 1 + read-write + + + CH4_ABORT + NA + 3 + 1 + read-write + + + CH1_ABORT_WE + NA + 8 + 1 + write-only + + + CH2_ABORT_WE + NA + 9 + 1 + write-only + + + CH3_ABORT_WE + NA + 10 + 1 + write-only + + + CH4_ABORT_WE + NA + 11 + 1 + write-only + + + + + INTSTATUS0 + NA + 0x30 + 0x20 + + + CH1_INTSTAT + NA + 0 + 1 + read-only + + + CH2_INTSTAT + NA + 1 + 1 + read-only + + + CH3_INTSTAT + NA + 2 + 1 + read-only + + + CH4_INTSTAT + NA + 3 + 1 + read-only + + + COMMONREG_INTSTAT + NA + 16 + 1 + read-only + + + + + COMMONREG_INTCLEAR0 + NA + 0x38 + 0x20 + + + CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT + NA + 0 + 1 + write-only + + + CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + NA + 1 + 1 + write-only + + + CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + NA + 2 + 1 + write-only + + + CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + NA + 3 + 1 + write-only + + + CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 9 + 1 + write-only + + + CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 10 + 1 + write-only + + + CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 11 + 1 + write-only + + + CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 12 + 1 + write-only + + + CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + NA + 13 + 1 + write-only + + + CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 14 + 1 + write-only + + + CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 15 + 1 + write-only + + + CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 16 + 1 + write-only + + + CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 17 + 1 + write-only + + + CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 18 + 1 + write-only + + + CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + NA + 19 + 1 + write-only + + + CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 20 + 1 + write-only + + + + + COMMONREG_INTSTATUS_ENABLE0 + NA + 0x40 + 0x20 + 0x001FFF8F + + + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT + NA + 0 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + NA + 1 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + NA + 2 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + NA + 3 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT + NA + 7 + 1 + read-only + + + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT + NA + 8 + 1 + read-write + + + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 9 + 1 + read-only + + + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 10 + 1 + read-only + + + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 11 + 1 + read-only + + + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 12 + 1 + read-only + + + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + NA + 13 + 1 + read-only + + + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 14 + 1 + read-only + + + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 15 + 1 + read-only + + + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 16 + 1 + read-only + + + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 17 + 1 + read-only + + + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 18 + 1 + read-only + + + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + NA + 19 + 1 + read-only + + + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 20 + 1 + read-only + + + + + COMMONREG_INTSIGNAL_ENABLE0 + NA + 0x48 + 0x20 + 0x001FFF8F + + + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL + NA + 0 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL + NA + 1 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL + NA + 2 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL + NA + 3 + 1 + read-write + + + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL + NA + 7 + 1 + read-only + + + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL + NA + 9 + 1 + read-only + + + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL + NA + 10 + 1 + read-only + + + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL + NA + 11 + 1 + read-only + + + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL + NA + 12 + 1 + read-only + + + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL + NA + 13 + 1 + read-only + + + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL + NA + 14 + 1 + read-only + + + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL + NA + 15 + 1 + read-only + + + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL + NA + 16 + 1 + read-only + + + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL + NA + 17 + 1 + read-only + + + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL + NA + 18 + 1 + read-only + + + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL + NA + 19 + 1 + read-only + + + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL + NA + 20 + 1 + read-only + + + + + COMMONREG_INTSTATUS0 + NA + 0x50 + 0x20 + + + SLVIF_COMMONREG_DEC_ERR_INTSTAT + NA + 0 + 1 + read-only + + + SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + NA + 1 + 1 + read-only + + + SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + NA + 2 + 1 + read-only + + + SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + NA + 3 + 1 + read-only + + + SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT + NA + 7 + 1 + read-only + + + SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT + NA + 8 + 1 + read-only + + + MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 9 + 1 + read-only + + + MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 10 + 1 + read-only + + + MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 11 + 1 + read-only + + + MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 12 + 1 + read-only + + + MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + NA + 13 + 1 + read-only + + + MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 14 + 1 + read-only + + + MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 15 + 1 + read-only + + + MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + NA + 16 + 1 + read-only + + + MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + NA + 17 + 1 + read-only + + + MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + NA + 18 + 1 + read-only + + + MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + NA + 19 + 1 + read-only + + + MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 20 + 1 + read-only + + + + + RESET0 + NA + 0x58 + 0x20 + + + DMAC_RST + NA + 0 + 1 + read-write + + + + + LOWPOWER_CFG0 + NA + 0x60 + 0x20 + 0x0000000F + + + GBL_CSLP_EN + NA + 0 + 1 + read-write + + + CHNL_CSLP_EN + NA + 1 + 1 + read-write + + + SBIU_CSLP_EN + NA + 2 + 1 + read-write + + + MXIF_CSLP_EN + NA + 3 + 1 + read-write + + + + + LOWPOWER_CFG1 + NA + 0x64 + 0x20 + 0x00404040 + + + GLCH_LPDLY + NA + 0 + 8 + read-write + + + SBIU_LPDLY + NA + 8 + 8 + read-write + + + MXIF_LPDLY + NA + 16 + 8 + read-write + + + + + CH1_SAR0 + NA + 0x100 + 0x20 + + + CH1_SAR0 + NA + 0 + 32 + read-write + + + + + CH1_SAR1 + NA + 0x104 + 0x20 + + + CH1_SAR1 + NA + 0 + 32 + read-write + + + + + CH1_DAR0 + NA + 0x108 + 0x20 + + + CH1_DAR0 + NA + 0 + 32 + read-write + + + + + CH1_DAR1 + NA + 0x10C + 0x20 + + + CH1_DAR1 + NA + 0 + 32 + read-write + + + + + CH1_BLOCK_TS0 + NA + 0x110 + 0x20 + + + CH1_BLOCK_TS + NA + 0 + 22 + read-write + + + + + CH1_CTL0 + NA + 0x118 + 0x20 + 0x00001200 + + + CH1_SMS + NA + 0 + 1 + read-write + + + CH1_DMS + NA + 2 + 1 + read-write + + + CH1_SINC + NA + 4 + 1 + read-write + + + CH1_DINC + NA + 6 + 1 + read-write + + + CH1_SRC_TR_WIDTH + NA + 8 + 3 + read-write + + + CH1_DST_TR_WIDTH + NA + 11 + 3 + read-write + + + CH1_SRC_MSIZE + NA + 14 + 4 + read-write + + + CH1_DST_MSIZE + NA + 18 + 4 + read-write + + + CH1_AR_CACHE + NA + 22 + 4 + read-write + + + CH1_AW_CACHE + NA + 26 + 4 + read-write + + + CH1_NONPOSTED_LASTWRITE_EN + NA + 30 + 1 + read-write + + + + + CH1_CTL1 + NA + 0x11C + 0x20 + + + CH1_AR_PROT + NA + 0 + 3 + read-write + + + CH1_AW_PROT + NA + 3 + 3 + read-write + + + CH1_ARLEN_EN + NA + 6 + 1 + read-write + + + CH1_ARLEN + NA + 7 + 8 + read-write + + + CH1_AWLEN_EN + NA + 15 + 1 + read-write + + + CH1_AWLEN + NA + 16 + 8 + read-write + + + CH1_SRC_STAT_EN + NA + 24 + 1 + read-write + + + CH1_DST_STAT_EN + NA + 25 + 1 + read-write + + + CH1_IOC_BLKTFR + NA + 26 + 1 + read-write + + + CH1_SHADOWREG_OR_LLI_LAST + NA + 30 + 1 + read-write + + + CH1_SHADOWREG_OR_LLI_VALID + NA + 31 + 1 + read-write + + + + + CH1_CFG0 + NA + 0x120 + 0x20 + + + CH1_SRC_MULTBLK_TYPE + NA + 0 + 2 + read-write + + + CH1_DST_MULTBLK_TYPE + NA + 2 + 2 + read-write + + + CH1_RD_UID + NA + 18 + 4 + read-only + + + CH1_WR_UID + NA + 25 + 4 + read-only + + + + + CH1_CFG1 + NA + 0x124 + 0x20 + 0x0006001B + + + CH1_TT_FC + NA + 0 + 3 + read-write + + + CH1_HS_SEL_SRC + NA + 3 + 1 + read-write + + + CH1_HS_SEL_DST + NA + 4 + 1 + read-write + + + CH1_SRC_HWHS_POL + NA + 5 + 1 + read-only + + + CH1_DST_HWHS_POL + NA + 6 + 1 + read-only + + + CH1_SRC_PER + NA + 7 + 2 + read-write + + + CH1_DST_PER + NA + 12 + 2 + read-write + + + CH1_CH_PRIOR + NA + 17 + 3 + read-write + + + CH1_LOCK_CH + NA + 20 + 1 + read-only + + + CH1_LOCK_CH_L + NA + 21 + 2 + read-only + + + CH1_SRC_OSR_LMT + NA + 23 + 4 + read-write + + + CH1_DST_OSR_LMT + NA + 27 + 4 + read-write + + + + + CH1_LLP0 + NA + 0x128 + 0x20 + + + CH1_LMS + NA + 0 + 1 + read-write + + + CH1_LOC0 + NA + 6 + 26 + read-write + + + + + CH1_LLP1 + NA + 0x12C + 0x20 + + + CH1_LOC1 + NA + 0 + 32 + read-write + + + + + CH1_STATUS0 + NA + 0x130 + 0x20 + + + CH1_CMPLTD_BLK_TFR_SIZE + NA + 0 + 22 + read-only + + + + + CH1_STATUS1 + NA + 0x134 + 0x20 + + + CH1_DATA_LEFT_IN_FIFO + NA + 0 + 15 + read-only + + + + + CH1_SWHSSRC0 + NA + 0x138 + 0x20 + + + CH1_SWHS_REQ_SRC + NA + 0 + 1 + read-write + + + CH1_SWHS_REQ_SRC_WE + NA + 1 + 1 + write-only + + + CH1_SWHS_SGLREQ_SRC + NA + 2 + 1 + read-write + + + CH1_SWHS_SGLREQ_SRC_WE + NA + 3 + 1 + write-only + + + CH1_SWHS_LST_SRC + NA + 4 + 1 + read-write + + + CH1_SWHS_LST_SRC_WE + NA + 5 + 1 + write-only + + + + + CH1_SWHSDST0 + NA + 0x140 + 0x20 + + + CH1_SWHS_REQ_DST + NA + 0 + 1 + read-write + + + CH1_SWHS_REQ_DST_WE + NA + 1 + 1 + write-only + + + CH1_SWHS_SGLREQ_DST + NA + 2 + 1 + read-write + + + CH1_SWHS_SGLREQ_DST_WE + NA + 3 + 1 + write-only + + + CH1_SWHS_LST_DST + NA + 4 + 1 + read-write + + + CH1_SWHS_LST_DST_WE + NA + 5 + 1 + write-only + + + + + CH1_BLK_TFR_RESUMEREQ0 + NA + 0x148 + 0x20 + + + CH1_BLK_TFR_RESUMEREQ + NA + 0 + 1 + write-only + + + + + CH1_AXI_ID0 + NA + 0x150 + 0x20 + + + CH1_AXI_READ_ID_SUFFIX + NA + 0 + 1 + read-write + + + CH1_AXI_WRITE_ID_SUFFIX + NA + 16 + 1 + read-write + + + + + CH1_AXI_QOS0 + NA + 0x158 + 0x20 + + + CH1_AXI_AWQOS + NA + 0 + 4 + read-write + + + CH1_AXI_ARQOS + NA + 4 + 4 + read-write + + + + + CH1_SSTAT0 + NA + 0x160 + 0x20 + + + CH1_SSTAT + NA + 0 + 32 + read-only + + + + + CH1_DSTAT0 + NA + 0x168 + 0x20 + + + CH1_DSTAT + NA + 0 + 32 + read-only + + + + + CH1_SSTATAR0 + NA + 0x170 + 0x20 + + + CH1_SSTATAR0 + NA + 0 + 32 + read-write + + + + + CH1_SSTATAR1 + NA + 0x174 + 0x20 + + + CH1_SSTATAR1 + NA + 0 + 32 + read-write + + + + + CH1_DSTATAR0 + NA + 0x178 + 0x20 + + + CH1_DSTATAR0 + NA + 0 + 32 + read-write + + + + + CH1_DSTATAR1 + NA + 0x17C + 0x20 + + + CH1_DSTATAR1 + NA + 0 + 32 + read-write + + + + + CH1_INTSTATUS_ENABLE0 + NA + 0x180 + 0x20 + 0xFA3F7FFB + + + CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-write + + + CH1_ENABLE_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-write + + + CH1_ENABLE_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-write + + + CH1_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-write + + + CH1_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-write + + + CH1_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-write + + + CH1_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-write + + + CH1_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-write + + + CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-write + + + CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-write + + + CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-write + + + CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-write + + + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-write + + + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-write + + + CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-write + + + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-write + + + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-write + + + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-write + + + CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-write + + + CH1_ENABLE_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-write + + + CH1_ENABLE_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-write + + + CH1_ENABLE_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-write + + + + + CH1_INTSTATUS_ENABLE1 + NA + 0x184 + 0x20 + 0x0000000F + + + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH1_INTSTATUS0 + NA + 0x188 + 0x20 + + + CH1_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-only + + + CH1_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-only + + + CH1_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-only + + + CH1_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-only + + + CH1_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH1_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH1_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH1_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-only + + + CH1_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-only + + + CH1_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-only + + + CH1_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-only + + + CH1_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-only + + + CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-only + + + CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-only + + + CH1_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-only + + + CH1_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-only + + + CH1_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-only + + + CH1_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-only + + + CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-only + + + CH1_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-only + + + CH1_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH1_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-only + + + CH1_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH1_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH1_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH1_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only + + + + + CH1_INTSTATUS1 + NA + 0x18C + 0x20 + + + CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH1_INTSIGNAL_ENABLE0 + NA + 0x190 + 0x20 + 0xFA3F7FFB + + + CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + NA + 0 + 1 + read-write + + + CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL + NA + 1 + 1 + read-write + + + CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL + NA + 3 + 1 + read-write + + + CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL + NA + 4 + 1 + read-write + + + CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL + NA + 5 + 1 + read-write + + + CH1_ENABLE_DST_DEC_ERR_INTSIGNAL + NA + 6 + 1 + read-write + + + CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL + NA + 7 + 1 + read-write + + + CH1_ENABLE_DST_SLV_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + NA + 9 + 1 + read-write + + + CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + NA + 10 + 1 + read-write + + + CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + NA + 11 + 1 + read-write + + + CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + NA + 12 + 1 + read-write + + + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + NA + 13 + 1 + read-write + + + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + NA + 14 + 1 + read-write + + + CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + NA + 16 + 1 + read-write + + + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + NA + 17 + 1 + read-write + + + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + NA + 18 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + NA + 19 + 1 + read-write + + + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + NA + 20 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + NA + 21 + 1 + read-write + + + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + NA + 25 + 1 + read-only + + + CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + NA + 27 + 1 + read-write + + + CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + NA + 28 + 1 + read-write + + + CH1_ENABLE_CH_SUSPENDED_INTSIGNAL + NA + 29 + 1 + read-write + + + CH1_ENABLE_CH_DISABLED_INTSIGNAL + NA + 30 + 1 + read-write + + + CH1_ENABLE_CH_ABORTED_INTSIGNAL + NA + 31 + 1 + read-write + + + + + CH1_INTSIGNAL_ENABLE1 + NA + 0x194 + 0x20 + 0x0000000F + + + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + NA + 0 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + NA + 1 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH1_INTCLEAR0 + NA + 0x198 + 0x20 + + + CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH1_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH1_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH1_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH1_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH1_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH1_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH1_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH1_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH1_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH1_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH1_INTCLEAR1 + NA + 0x19C + 0x20 + + + CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + CH2_SAR0 + NA + 0x200 + 0x20 + + + CH2_SAR0 + NA + 0 + 32 + read-write + + + + + CH2_SAR1 + NA + 0x204 + 0x20 + + + CH2_SAR1 + NA + 0 + 32 + read-write + + + + + CH2_DAR0 + NA + 0x208 + 0x20 + + + CH2_DAR0 + NA + 0 + 32 + read-write + + + + + CH2_DAR1 + NA + 0x20C + 0x20 + + + CH2_DAR1 + NA + 0 + 32 + read-write + + + + + CH2_BLOCK_TS0 + NA + 0x210 + 0x20 + + + CH2_BLOCK_TS + NA + 0 + 22 + read-write + + + + + CH2_CTL0 + NA + 0x218 + 0x20 + 0x00001200 + + + CH2_SMS + NA + 0 + 1 + read-write + + + CH2_DMS + NA + 2 + 1 + read-write + + + CH2_SINC + NA + 4 + 1 + read-write + + + CH2_DINC + NA + 6 + 1 + read-write + + + CH2_SRC_TR_WIDTH + NA + 8 + 3 + read-write + + + CH2_DST_TR_WIDTH + NA + 11 + 3 + read-write + + + CH2_SRC_MSIZE + NA + 14 + 4 + read-write + + + CH2_DST_MSIZE + NA + 18 + 4 + read-write + + + CH2_AR_CACHE + NA + 22 + 4 + read-write + + + CH2_AW_CACHE + NA + 26 + 4 + read-write + + + CH2_NONPOSTED_LASTWRITE_EN + NA + 30 + 1 + read-write + + + + + CH2_CTL1 + NA + 0x21C + 0x20 + + + CH2_AR_PROT + NA + 0 + 3 + read-write + + + CH2_AW_PROT + NA + 3 + 3 + read-write + + + CH2_ARLEN_EN + NA + 6 + 1 + read-write + + + CH2_ARLEN + NA + 7 + 8 + read-write + + + CH2_AWLEN_EN + NA + 15 + 1 + read-write + + + CH2_AWLEN + NA + 16 + 8 + read-write + + + CH2_SRC_STAT_EN + NA + 24 + 1 + read-write + + + CH2_DST_STAT_EN + NA + 25 + 1 + read-write + + + CH2_IOC_BLKTFR + NA + 26 + 1 + read-write + + + CH2_SHADOWREG_OR_LLI_LAST + NA + 30 + 1 + read-write + + + CH2_SHADOWREG_OR_LLI_VALID + NA + 31 + 1 + read-write + + + + + CH2_CFG0 + NA + 0x220 + 0x20 + + + CH2_SRC_MULTBLK_TYPE + NA + 0 + 2 + read-write + + + CH2_DST_MULTBLK_TYPE + NA + 2 + 2 + read-write + + + CH2_RD_UID + NA + 18 + 4 + read-only + + + CH2_WR_UID + NA + 25 + 4 + read-only + + + + + CH2_CFG1 + NA + 0x224 + 0x20 + 0x0004001B + + + CH2_TT_FC + NA + 0 + 3 + read-write + + + CH2_HS_SEL_SRC + NA + 3 + 1 + read-write + + + CH2_HS_SEL_DST + NA + 4 + 1 + read-write + + + CH2_SRC_HWHS_POL + NA + 5 + 1 + read-only + + + CH2_DST_HWHS_POL + NA + 6 + 1 + read-only + + + CH2_SRC_PER + NA + 7 + 2 + read-write + + + CH2_DST_PER + NA + 12 + 2 + read-write + + + CH2_CH_PRIOR + NA + 17 + 3 + read-write + + + CH2_LOCK_CH + NA + 20 + 1 + read-only + + + CH2_LOCK_CH_L + NA + 21 + 2 + read-only + + + CH2_SRC_OSR_LMT + NA + 23 + 4 + read-write + + + CH2_DST_OSR_LMT + NA + 27 + 4 + read-write + + + + + CH2_LLP0 + NA + 0x228 + 0x20 + + + CH2_LMS + NA + 0 + 1 + read-write + + + CH2_LOC0 + NA + 6 + 26 + read-write + + + + + CH2_LLP1 + NA + 0x22C + 0x20 + + + CH2_LOC1 + NA + 0 + 32 + read-write + + + + + CH2_STATUS0 + NA + 0x230 + 0x20 + + + CH2_CMPLTD_BLK_TFR_SIZE + NA + 0 + 22 + read-only + + + + + CH2_STATUS1 + NA + 0x234 + 0x20 + + + CH2_DATA_LEFT_IN_FIFO + NA + 0 + 15 + read-only + + + + + CH2_SWHSSRC0 + NA + 0x238 + 0x20 + + + CH2_SWHS_REQ_SRC + NA + 0 + 1 + read-write + + + CH2_SWHS_REQ_SRC_WE + NA + 1 + 1 + write-only + + + CH2_SWHS_SGLREQ_SRC + NA + 2 + 1 + read-write + + + CH2_SWHS_SGLREQ_SRC_WE + NA + 3 + 1 + write-only + + + CH2_SWHS_LST_SRC + NA + 4 + 1 + read-write + + + CH2_SWHS_LST_SRC_WE + NA + 5 + 1 + write-only + + + + + CH2_SWHSDST0 + NA + 0x240 + 0x20 + + + CH2_SWHS_REQ_DST + NA + 0 + 1 + read-write + + + CH2_SWHS_REQ_DST_WE + NA + 1 + 1 + write-only + + + CH2_SWHS_SGLREQ_DST + NA + 2 + 1 + read-write + + + CH2_SWHS_SGLREQ_DST_WE + NA + 3 + 1 + write-only + + + CH2_SWHS_LST_DST + NA + 4 + 1 + read-write + + + CH2_SWHS_LST_DST_WE + NA + 5 + 1 + write-only + + + + + CH2_BLK_TFR_RESUMEREQ0 + NA + 0x248 + 0x20 + + + CH2_BLK_TFR_RESUMEREQ + NA + 0 + 1 + write-only + + + + + CH2_AXI_ID0 + NA + 0x250 + 0x20 + + + CH2_AXI_READ_ID_SUFFIX + NA + 0 + 1 + read-write + + + CH2_AXI_WRITE_ID_SUFFIX + NA + 16 + 1 + read-write + + + + + CH2_AXI_QOS0 + NA + 0x258 + 0x20 + + + CH2_AXI_AWQOS + NA + 0 + 4 + read-write + + + CH2_AXI_ARQOS + NA + 4 + 4 + read-write + + + + + CH2_SSTAT0 + NA + 0x260 + 0x20 + + + CH2_SSTAT + NA + 0 + 32 + read-only + + + + + CH2_DSTAT0 + NA + 0x268 + 0x20 + + + CH2_DSTAT + NA + 0 + 32 + read-only + + + + + CH2_SSTATAR0 + NA + 0x270 + 0x20 + + + CH2_SSTATAR0 + NA + 0 + 32 + read-write + + + + + CH2_SSTATAR1 + NA + 0x274 + 0x20 + + + CH2_SSTATAR1 + NA + 0 + 32 + read-write + + + + + CH2_DSTATAR0 + NA + 0x278 + 0x20 + + + CH2_DSTATAR0 + NA + 0 + 32 + read-write + + + + + CH2_DSTATAR1 + NA + 0x27C + 0x20 + + + CH2_DSTATAR1 + NA + 0 + 32 + read-write + + + + + CH2_INTSTATUS_ENABLE0 + NA + 0x280 + 0x20 + 0xFA3F7FFB + + + CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-write + + + CH2_ENABLE_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-write + + + CH2_ENABLE_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-write + + + CH2_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-write + + + CH2_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-write + + + CH2_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-write + + + CH2_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-write + + + CH2_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-write + + + CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-write + + + CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-write + + + CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-write + + + CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-write + + + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-write + + + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-write + + + CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-write + + + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-write + + + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-write + + + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-write + + + CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-write + + + CH2_ENABLE_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-write + + + CH2_ENABLE_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-write + + + CH2_ENABLE_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-write + + + + + CH2_INTSTATUS_ENABLE1 + NA + 0x284 + 0x20 + 0x0000000F + + + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH2_INTSTATUS0 + NA + 0x288 + 0x20 + + + CH2_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-only + + + CH2_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-only + + + CH2_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-only + + + CH2_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-only + + + CH2_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH2_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH2_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH2_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-only + + + CH2_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-only + + + CH2_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-only + + + CH2_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-only + + + CH2_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-only + + + CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-only + + + CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-only + + + CH2_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-only + + + CH2_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-only + + + CH2_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-only + + + CH2_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-only + + + CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-only + + + CH2_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-only + + + CH2_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH2_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-only + + + CH2_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH2_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH2_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH2_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only + + + + + CH2_INTSTATUS1 + NA + 0x28C + 0x20 + + + CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH2_INTSIGNAL_ENABLE0 + NA + 0x290 + 0x20 + 0xFA3F7FFB + + + CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + NA + 0 + 1 + read-write + + + CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL + NA + 1 + 1 + read-write + + + CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL + NA + 3 + 1 + read-write + + + CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL + NA + 4 + 1 + read-write + + + CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL + NA + 5 + 1 + read-write + + + CH2_ENABLE_DST_DEC_ERR_INTSIGNAL + NA + 6 + 1 + read-write + + + CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL + NA + 7 + 1 + read-write + + + CH2_ENABLE_DST_SLV_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + NA + 9 + 1 + read-write + + + CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + NA + 10 + 1 + read-write + + + CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + NA + 11 + 1 + read-write + + + CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + NA + 12 + 1 + read-write + + + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + NA + 13 + 1 + read-write + + + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + NA + 14 + 1 + read-write + + + CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + NA + 16 + 1 + read-write + + + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + NA + 17 + 1 + read-write + + + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + NA + 18 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + NA + 19 + 1 + read-write + + + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + NA + 20 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + NA + 21 + 1 + read-write + + + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + NA + 25 + 1 + read-only + + + CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + NA + 27 + 1 + read-write + + + CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + NA + 28 + 1 + read-write + + + CH2_ENABLE_CH_SUSPENDED_INTSIGNAL + NA + 29 + 1 + read-write + + + CH2_ENABLE_CH_DISABLED_INTSIGNAL + NA + 30 + 1 + read-write + + + CH2_ENABLE_CH_ABORTED_INTSIGNAL + NA + 31 + 1 + read-write + + + + + CH2_INTSIGNAL_ENABLE1 + NA + 0x294 + 0x20 + 0x0000000F + + + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + NA + 0 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + NA + 1 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH2_INTCLEAR0 + NA + 0x298 + 0x20 + + + CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH2_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH2_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH2_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH2_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH2_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH2_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH2_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH2_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH2_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH2_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH2_INTCLEAR1 + NA + 0x29C + 0x20 + + + CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + CH3_SAR0 + NA + 0x300 + 0x20 + + + CH3_SAR0 + NA + 0 + 32 + read-write + + + + + CH3_SAR1 + NA + 0x304 + 0x20 + + + CH3_SAR1 + NA + 0 + 32 + read-write + + + + + CH3_DAR0 + NA + 0x308 + 0x20 + + + CH3_DAR0 + NA + 0 + 32 + read-write + + + + + CH3_DAR1 + NA + 0x30C + 0x20 + + + CH3_DAR1 + NA + 0 + 32 + read-write + + + + + CH3_BLOCK_TS0 + NA + 0x310 + 0x20 + + + CH3_BLOCK_TS + NA + 0 + 22 + read-write + + + + + CH3_CTL0 + NA + 0x318 + 0x20 + 0x00001200 + + + CH3_SMS + NA + 0 + 1 + read-write + + + CH3_DMS + NA + 2 + 1 + read-write + + + CH3_SINC + NA + 4 + 1 + read-write + + + CH3_DINC + NA + 6 + 1 + read-write + + + CH3_SRC_TR_WIDTH + NA + 8 + 3 + read-write + + + CH3_DST_TR_WIDTH + NA + 11 + 3 + read-write + + + CH3_SRC_MSIZE + NA + 14 + 4 + read-write + + + CH3_DST_MSIZE + NA + 18 + 4 + read-write + + + CH3_AR_CACHE + NA + 22 + 4 + read-write + + + CH3_AW_CACHE + NA + 26 + 4 + read-write + + + CH3_NONPOSTED_LASTWRITE_EN + NA + 30 + 1 + read-write + + + + + CH3_CTL1 + NA + 0x31C + 0x20 + + + CH3_AR_PROT + NA + 0 + 3 + read-write + + + CH3_AW_PROT + NA + 3 + 3 + read-write + + + CH3_ARLEN_EN + NA + 6 + 1 + read-write + + + CH3_ARLEN + NA + 7 + 8 + read-write + + + CH3_AWLEN_EN + NA + 15 + 1 + read-write + + + CH3_AWLEN + NA + 16 + 8 + read-write + + + CH3_SRC_STAT_EN + NA + 24 + 1 + read-write + + + CH3_DST_STAT_EN + NA + 25 + 1 + read-write + + + CH3_IOC_BLKTFR + NA + 26 + 1 + read-write + + + CH3_SHADOWREG_OR_LLI_LAST + NA + 30 + 1 + read-write + + + CH3_SHADOWREG_OR_LLI_VALID + NA + 31 + 1 + read-write + + + + + CH3_CFG0 + NA + 0x320 + 0x20 + + + CH3_SRC_MULTBLK_TYPE + NA + 0 + 2 + read-write + + + CH3_DST_MULTBLK_TYPE + NA + 2 + 2 + read-write + + + CH3_RD_UID + NA + 18 + 4 + read-only + + + CH3_WR_UID + NA + 25 + 4 + read-only + + + + + CH3_CFG1 + NA + 0x324 + 0x20 + 0x0002001B + + + CH3_TT_FC + NA + 0 + 3 + read-write + + + CH3_HS_SEL_SRC + NA + 3 + 1 + read-write + + + CH3_HS_SEL_DST + NA + 4 + 1 + read-write + + + CH3_SRC_HWHS_POL + NA + 5 + 1 + read-only + + + CH3_DST_HWHS_POL + NA + 6 + 1 + read-only + + + CH3_SRC_PER + NA + 7 + 2 + read-write + + + CH3_DST_PER + NA + 12 + 2 + read-write + + + CH3_CH_PRIOR + NA + 17 + 3 + read-write + + + CH3_LOCK_CH + NA + 20 + 1 + read-only + + + CH3_LOCK_CH_L + NA + 21 + 2 + read-only + + + CH3_SRC_OSR_LMT + NA + 23 + 4 + read-write + + + CH3_DST_OSR_LMT + NA + 27 + 4 + read-write + + + + + CH3_LLP0 + NA + 0x328 + 0x20 + + + CH3_LMS + NA + 0 + 1 + read-write + + + CH3_LOC0 + NA + 6 + 26 + read-write + + + + + CH3_LLP1 + NA + 0x32C + 0x20 + + + CH3_LOC1 + NA + 0 + 32 + read-write + + + + + CH3_STATUS0 + NA + 0x330 + 0x20 + + + CH3_CMPLTD_BLK_TFR_SIZE + NA + 0 + 22 + read-only + + + + + CH3_STATUS1 + NA + 0x334 + 0x20 + + + CH3_DATA_LEFT_IN_FIFO + NA + 0 + 15 + read-only + + + + + CH3_SWHSSRC0 + NA + 0x338 + 0x20 + + + CH3_SWHS_REQ_SRC + NA + 0 + 1 + read-write + + + CH3_SWHS_REQ_SRC_WE + NA + 1 + 1 + write-only + + + CH3_SWHS_SGLREQ_SRC + NA + 2 + 1 + read-write + + + CH3_SWHS_SGLREQ_SRC_WE + NA + 3 + 1 + write-only + + + CH3_SWHS_LST_SRC + NA + 4 + 1 + read-write + + + CH3_SWHS_LST_SRC_WE + NA + 5 + 1 + write-only + + + + + CH3_SWHSDST0 + NA + 0x340 + 0x20 + + + CH3_SWHS_REQ_DST + NA + 0 + 1 + read-write + + + CH3_SWHS_REQ_DST_WE + NA + 1 + 1 + write-only + + + CH3_SWHS_SGLREQ_DST + NA + 2 + 1 + read-write + + + CH3_SWHS_SGLREQ_DST_WE + NA + 3 + 1 + write-only + + + CH3_SWHS_LST_DST + NA + 4 + 1 + read-write + + + CH3_SWHS_LST_DST_WE + NA + 5 + 1 + write-only + + + + + CH3_BLK_TFR_RESUMEREQ0 + NA + 0x348 + 0x20 + + + CH3_BLK_TFR_RESUMEREQ + NA + 0 + 1 + write-only + + + + + CH3_AXI_ID0 + NA + 0x350 + 0x20 + + + CH3_AXI_READ_ID_SUFFIX + NA + 0 + 1 + read-write + + + CH3_AXI_WRITE_ID_SUFFIX + NA + 16 + 1 + read-write + + + + + CH3_AXI_QOS0 + NA + 0x358 + 0x20 + + + CH3_AXI_AWQOS + NA + 0 + 4 + read-write + + + CH3_AXI_ARQOS + NA + 4 + 4 + read-write + + + + + CH3_SSTAT0 + NA + 0x360 + 0x20 + + + CH3_SSTAT + NA + 0 + 32 + read-only + + + + + CH3_DSTAT0 + NA + 0x368 + 0x20 + + + CH3_DSTAT + NA + 0 + 32 + read-only + + + + + CH3_SSTATAR0 + NA + 0x370 + 0x20 + + + CH3_SSTATAR0 + NA + 0 + 32 + read-write + + + + + CH3_SSTATAR1 + NA + 0x374 + 0x20 + + + CH3_SSTATAR1 + NA + 0 + 32 + read-write + + + + + CH3_DSTATAR0 + NA + 0x378 + 0x20 + + + CH3_DSTATAR0 + NA + 0 + 32 + read-write + + + + + CH3_DSTATAR1 + NA + 0x37C + 0x20 + + + CH3_DSTATAR1 + NA + 0 + 32 + read-write + + + + + CH3_INTSTATUS_ENABLE0 + NA + 0x380 + 0x20 + 0xFA3F7FFB + + + CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-write + + + CH3_ENABLE_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-write + + + CH3_ENABLE_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-write + + + CH3_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-write + + + CH3_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-write + + + CH3_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-write + + + CH3_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-write + + + CH3_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-write + + + CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-write + + + CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-write + + + CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-write + + + CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-write + + + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-write + + + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-write + + + CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-write + + + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-write + + + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-write + + + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-write + + + CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-write + + + CH3_ENABLE_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-write + + + CH3_ENABLE_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-write + + + CH3_ENABLE_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-write + + + + + CH3_INTSTATUS_ENABLE1 + NA + 0x384 + 0x20 + 0x0000000F + + + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH3_INTSTATUS0 + NA + 0x388 + 0x20 + + + CH3_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-only + + + CH3_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-only + + + CH3_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-only + + + CH3_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-only + + + CH3_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH3_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH3_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH3_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-only + + + CH3_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-only + + + CH3_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-only + + + CH3_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-only + + + CH3_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-only + + + CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-only + + + CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-only + + + CH3_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-only + + + CH3_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-only + + + CH3_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-only + + + CH3_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-only + + + CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-only + + + CH3_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-only + + + CH3_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH3_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-only + + + CH3_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH3_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH3_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH3_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only + + + + + CH3_INTSTATUS1 + NA + 0x38C + 0x20 + + + CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH3_INTSIGNAL_ENABLE0 + NA + 0x390 + 0x20 + 0xFA3F7FFB + + + CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + NA + 0 + 1 + read-write + + + CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL + NA + 1 + 1 + read-write + + + CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL + NA + 3 + 1 + read-write + + + CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL + NA + 4 + 1 + read-write + + + CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL + NA + 5 + 1 + read-write + + + CH3_ENABLE_DST_DEC_ERR_INTSIGNAL + NA + 6 + 1 + read-write + + + CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL + NA + 7 + 1 + read-write + + + CH3_ENABLE_DST_SLV_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + NA + 9 + 1 + read-write + + + CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + NA + 10 + 1 + read-write + + + CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + NA + 11 + 1 + read-write + + + CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + NA + 12 + 1 + read-write + + + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + NA + 13 + 1 + read-write + + + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + NA + 14 + 1 + read-write + + + CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + NA + 16 + 1 + read-write + + + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + NA + 17 + 1 + read-write + + + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + NA + 18 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + NA + 19 + 1 + read-write + + + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + NA + 20 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + NA + 21 + 1 + read-write + + + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + NA + 25 + 1 + read-only + + + CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + NA + 27 + 1 + read-write + + + CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + NA + 28 + 1 + read-write + + + CH3_ENABLE_CH_SUSPENDED_INTSIGNAL + NA + 29 + 1 + read-write + + + CH3_ENABLE_CH_DISABLED_INTSIGNAL + NA + 30 + 1 + read-write + + + CH3_ENABLE_CH_ABORTED_INTSIGNAL + NA + 31 + 1 + read-write + + + + + CH3_INTSIGNAL_ENABLE1 + NA + 0x394 + 0x20 + 0x0000000F + + + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + NA + 0 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + NA + 1 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH3_INTCLEAR0 + NA + 0x398 + 0x20 + + + CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH3_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH3_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH3_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH3_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH3_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH3_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH3_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH3_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH3_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH3_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH3_INTCLEAR1 + NA + 0x39C + 0x20 + + + CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + CH4_SAR0 + NA + 0x400 + 0x20 + + + CH4_SAR0 + NA + 0 + 32 + read-write + + + + + CH4_SAR1 + NA + 0x404 + 0x20 + + + CH4_SAR1 + NA + 0 + 32 + read-write + + + + + CH4_DAR0 + NA + 0x408 + 0x20 + + + CH4_DAR0 + NA + 0 + 32 + read-write + + + + + CH4_DAR1 + NA + 0x40C + 0x20 + + + CH4_DAR1 + NA + 0 + 32 + read-write + + + + + CH4_BLOCK_TS0 + NA + 0x410 + 0x20 + + + CH4_BLOCK_TS + NA + 0 + 22 + read-write + + + + + CH4_CTL0 + NA + 0x418 + 0x20 + 0x00001200 + + + CH4_SMS + NA + 0 + 1 + read-write + + + CH4_DMS + NA + 2 + 1 + read-write + + + CH4_SINC + NA + 4 + 1 + read-write + + + CH4_DINC + NA + 6 + 1 + read-write + + + CH4_SRC_TR_WIDTH + NA + 8 + 3 + read-write + + + CH4_DST_TR_WIDTH + NA + 11 + 3 + read-write + + + CH4_SRC_MSIZE + NA + 14 + 4 + read-write + + + CH4_DST_MSIZE + NA + 18 + 4 + read-write + + + CH4_AR_CACHE + NA + 22 + 4 + read-write + + + CH4_AW_CACHE + NA + 26 + 4 + read-write + + + CH4_NONPOSTED_LASTWRITE_EN + NA + 30 + 1 + read-write + + + + + CH4_CTL1 + NA + 0x41C + 0x20 + + + CH4_AR_PROT + NA + 0 + 3 + read-write + + + CH4_AW_PROT + NA + 3 + 3 + read-write + + + CH4_ARLEN_EN + NA + 6 + 1 + read-write + + + CH4_ARLEN + NA + 7 + 8 + read-write + + + CH4_AWLEN_EN + NA + 15 + 1 + read-write + + + CH4_AWLEN + NA + 16 + 8 + read-write + + + CH4_SRC_STAT_EN + NA + 24 + 1 + read-write + + + CH4_DST_STAT_EN + NA + 25 + 1 + read-write + + + CH4_IOC_BLKTFR + NA + 26 + 1 + read-write + + + CH4_SHADOWREG_OR_LLI_LAST + NA + 30 + 1 + read-write + + + CH4_SHADOWREG_OR_LLI_VALID + NA + 31 + 1 + read-write + + + + + CH4_CFG0 + NA + 0x420 + 0x20 + + + CH4_SRC_MULTBLK_TYPE + NA + 0 + 2 + read-write + + + CH4_DST_MULTBLK_TYPE + NA + 2 + 2 + read-write + + + CH4_RD_UID + NA + 18 + 4 + read-only + + + CH4_WR_UID + NA + 25 + 4 + read-only + + + + + CH4_CFG1 + NA + 0x424 + 0x20 + 0x0000001B + + + CH4_TT_FC + NA + 0 + 3 + read-write + + + CH4_HS_SEL_SRC + NA + 3 + 1 + read-write + + + CH4_HS_SEL_DST + NA + 4 + 1 + read-write + + + CH4_SRC_HWHS_POL + NA + 5 + 1 + read-only + + + CH4_DST_HWHS_POL + NA + 6 + 1 + read-only + + + CH4_SRC_PER + NA + 7 + 2 + read-write + + + CH4_DST_PER + NA + 12 + 2 + read-write + + + CH4_CH_PRIOR + NA + 17 + 3 + read-write + + + CH4_LOCK_CH + NA + 20 + 1 + read-only + + + CH4_LOCK_CH_L + NA + 21 + 2 + read-only + + + CH4_SRC_OSR_LMT + NA + 23 + 4 + read-write + + + CH4_DST_OSR_LMT + NA + 27 + 4 + read-write + + + + + CH4_LLP0 + NA + 0x428 + 0x20 + + + CH4_LMS + NA + 0 + 1 + read-write + + + CH4_LOC0 + NA + 6 + 26 + read-write + + + + + CH4_LLP1 + NA + 0x42C + 0x20 + + + CH4_LOC1 + NA + 0 + 32 + read-write + + + + + CH4_STATUS0 + NA + 0x430 + 0x20 + + + CH4_CMPLTD_BLK_TFR_SIZE + NA + 0 + 22 + read-only + + + + + CH4_STATUS1 + NA + 0x434 + 0x20 + + + CH4_DATA_LEFT_IN_FIFO + NA + 0 + 15 + read-only + + + + + CH4_SWHSSRC0 + NA + 0x438 + 0x20 + + + CH4_SWHS_REQ_SRC + NA + 0 + 1 + read-write + + + CH4_SWHS_REQ_SRC_WE + NA + 1 + 1 + write-only + + + CH4_SWHS_SGLREQ_SRC + NA + 2 + 1 + read-write + + + CH4_SWHS_SGLREQ_SRC_WE + NA + 3 + 1 + write-only + + + CH4_SWHS_LST_SRC + NA + 4 + 1 + read-write + + + CH4_SWHS_LST_SRC_WE + NA + 5 + 1 + write-only + + + + + CH4_SWHSDST0 + NA + 0x440 + 0x20 + + + CH4_SWHS_REQ_DST + NA + 0 + 1 + read-write + + + CH4_SWHS_REQ_DST_WE + NA + 1 + 1 + write-only + + + CH4_SWHS_SGLREQ_DST + NA + 2 + 1 + read-write + + + CH4_SWHS_SGLREQ_DST_WE + NA + 3 + 1 + write-only + + + CH4_SWHS_LST_DST + NA + 4 + 1 + read-write + + + CH4_SWHS_LST_DST_WE + NA + 5 + 1 + write-only + + + + + CH4_BLK_TFR_RESUMEREQ0 + NA + 0x448 + 0x20 + + + CH4_BLK_TFR_RESUMEREQ + NA + 0 + 1 + write-only + + + + + CH4_AXI_ID0 + NA + 0x450 + 0x20 + + + CH4_AXI_READ_ID_SUFFIX + NA + 0 + 1 + read-write + + + CH4_AXI_WRITE_ID_SUFFIX + NA + 16 + 1 + read-write + + + + + CH4_AXI_QOS0 + NA + 0x458 + 0x20 + + + CH4_AXI_AWQOS + NA + 0 + 4 + read-write + + + CH4_AXI_ARQOS + NA + 4 + 4 + read-write + + + + + CH4_SSTAT0 + NA + 0x460 + 0x20 + + + CH4_SSTAT + NA + 0 + 32 + read-only + + + + + CH4_DSTAT0 + NA + 0x468 + 0x20 + + + CH4_DSTAT + NA + 0 + 32 + read-only + + + + + CH4_SSTATAR0 + NA + 0x470 + 0x20 + + + CH4_SSTATAR0 + NA + 0 + 32 + read-write + + + + + CH4_SSTATAR1 + NA + 0x474 + 0x20 + + + CH4_SSTATAR1 + NA + 0 + 32 + read-write + + + + + CH4_DSTATAR0 + NA + 0x478 + 0x20 + + + CH4_DSTATAR0 + NA + 0 + 32 + read-write + + + + + CH4_DSTATAR1 + NA + 0x47C + 0x20 + + + CH4_DSTATAR1 + NA + 0 + 32 + read-write + + + + + CH4_INTSTATUS_ENABLE0 + NA + 0x480 + 0x20 + 0xFA3F7FFB + + + CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-write + + + CH4_ENABLE_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-write + + + CH4_ENABLE_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-write + + + CH4_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-write + + + CH4_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-write + + + CH4_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-write + + + CH4_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-write + + + CH4_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-write + + + CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-write + + + CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-write + + + CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-write + + + CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-write + + + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-write + + + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-write + + + CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-write + + + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-write + + + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-write + + + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-write + + + CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-write + + + CH4_ENABLE_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-write + + + CH4_ENABLE_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-write + + + CH4_ENABLE_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-write + + + + + CH4_INTSTATUS_ENABLE1 + NA + 0x484 + 0x20 + 0x0000000F + + + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH4_INTSTATUS0 + NA + 0x488 + 0x20 + + + CH4_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-only + + + CH4_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-only + + + CH4_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-only + + + CH4_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-only + + + CH4_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH4_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH4_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH4_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-only + + + CH4_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-only + + + CH4_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-only + + + CH4_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-only + + + CH4_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-only + + + CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-only + + + CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-only + + + CH4_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-only + + + CH4_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-only + + + CH4_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-only + + + CH4_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-only + + + CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-only + + + CH4_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-only + + + CH4_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH4_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-only + + + CH4_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH4_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH4_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH4_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only + + + + + CH4_INTSTATUS1 + NA + 0x48C + 0x20 + + + CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH4_INTSIGNAL_ENABLE0 + NA + 0x490 + 0x20 + 0xFA3F7FFB + + + CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + NA + 0 + 1 + read-write + + + CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL + NA + 1 + 1 + read-write + + + CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL + NA + 3 + 1 + read-write + + + CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL + NA + 4 + 1 + read-write + + + CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL + NA + 5 + 1 + read-write + + + CH4_ENABLE_DST_DEC_ERR_INTSIGNAL + NA + 6 + 1 + read-write + + + CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL + NA + 7 + 1 + read-write + + + CH4_ENABLE_DST_SLV_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + NA + 9 + 1 + read-write + + + CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + NA + 10 + 1 + read-write + + + CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + NA + 11 + 1 + read-write + + + CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + NA + 12 + 1 + read-write + + + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + NA + 13 + 1 + read-write + + + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + NA + 14 + 1 + read-write + + + CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + NA + 16 + 1 + read-write + + + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + NA + 17 + 1 + read-write + + + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + NA + 18 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + NA + 19 + 1 + read-write + + + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + NA + 20 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + NA + 21 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + NA + 25 + 1 + read-only + + + CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + NA + 27 + 1 + read-write + + + CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + NA + 28 + 1 + read-write + + + CH4_ENABLE_CH_SUSPENDED_INTSIGNAL + NA + 29 + 1 + read-write + + + CH4_ENABLE_CH_DISABLED_INTSIGNAL + NA + 30 + 1 + read-write + + + CH4_ENABLE_CH_ABORTED_INTSIGNAL + NA + 31 + 1 + read-write + + + + + CH4_INTSIGNAL_ENABLE1 + NA + 0x494 + 0x20 + 0x0000000F + + + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + NA + 0 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + NA + 1 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH4_INTCLEAR0 + NA + 0x498 + 0x20 + + + CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH4_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH4_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH4_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH4_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH4_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH4_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH4_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH4_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH4_INTCLEAR1 + NA + 0x49C + 0x20 + + + CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + + + DS + Digital Signature + DS + 0x50094000 + + 0x0 + 0xA5C + registers + + + + 128 + 0x4 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x20 + + + 128 + 0x4 + M_MEM[%s] + memory that stores M + 0x200 + 0x20 + + + 128 + 0x4 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x20 + + + 12 + 0x4 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x20 + + + 4 + 0x4 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x20 + + + 128 + 0x4 + X_MEM[%s] + memory that stores X + 0x800 + 0x20 + + + 128 + 0x4 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x20 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + MIPI_DSI_BRIDGE + MIPI Camera Interface Bridge + DSI_BRG + 0x500A0800 + + 0x0 + 0x94 + registers + + + DSI_BRIDGE + 86 + + + + CLK_EN + dsi bridge clk control register + 0x0 + 0x20 + + + CLK_EN + this bit configures force_on of dsi_bridge register clock gate + 0 + 1 + read-write + + + + + EN + dsi bridge en register + 0x4 + 0x20 + + + DSI_EN + this bit configures module enable of dsi_bridge. 0: disable, 1: enable + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dsi bridge dma burst len register + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller + 0 + 12 + read-write + + + + + RAW_NUM_CFG + dsi bridge raw number control register + 0xC + 0x20 + 0x00038400 + + + RAW_NUM_TOTAL + this field configures number of total pix bits/64 + 0 + 22 + read-write + + + UNALIGN_64BIT_EN + this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit + 22 + 1 + read-write + + + RAW_NUM_TOTAL_SET + this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller + 31 + 1 + write-only + + + + + RAW_BUF_CREDIT_CTL + dsi bridge credit register + 0x10 + 0x20 + 0x03200400 + + + CREDIT_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller + 0 + 15 + read-write + + + CREDIT_BURST_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller + 16 + 15 + read-write + + + CREDIT_RESET + this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller + 31 + 1 + read-write + + + + + FIFO_FLOW_STATUS + dsi bridge raw buffer depth register + 0x14 + 0x20 + + + RAW_BUF_DEPTH + this field configures the depth of dsi_bridge fifo depth + 0 + 14 + read-only + + + + + PIXEL_TYPE + dsi bridge dpi type control register + 0x18 + 0x20 + + + RAW_TYPE + this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + 0 + 4 + read-write + + + DPI_CONFIG + this field configures the pixel arrange type of dpi interface + 4 + 2 + read-write + + + DATA_IN_TYPE + input data type, 0: rgb, 1: yuv + 6 + 1 + read-write + + + + + DMA_BLOCK_INTERVAL + dsi bridge dma block interval control register + 0x1C + 0x20 + 0x30002409 + + + DMA_BLOCK_SLOT + this field configures the max block_slot_cnt + 0 + 10 + read-write + + + DMA_BLOCK_INTERVAL + this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full + 10 + 18 + read-write + + + RAW_NUM_TOTAL_AUTO_RELOAD + this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable of interval between dma block transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + DMA_REQ_INTERVAL + dsi bridge dma req interval control register + 0x20 + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + this field configures the interval between dma req events + 0 + 16 + read-write + + + + + DPI_LCD_CTL + dsi bridge dpi signal control register + 0x24 + 0x20 + + + DPISHUTDN + this bit configures dpishutdn signal in dpi interface + 0 + 1 + read-write + + + DPICOLORM + this bit configures dpicolorm signal in dpi interface + 1 + 1 + read-write + + + DPIUPDATECFG + this bit configures dpiupdatecfg signal in dpi interface + 2 + 1 + read-write + + + + + DPI_RSV_DPI_DATA + dsi bridge dpi reserved data register + 0x28 + 0x20 + 0x00003FFF + + + DPI_RSV_DATA + this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + 0 + 30 + read-write + + + + + DPI_V_CFG0 + dsi bridge dpi v config register 0 + 0x30 + 0x20 + 0x01E0020D + + + VTOTAL + this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + 0 + 12 + read-write + + + VDISP + this field configures the length of valid line (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_V_CFG1 + dsi bridge dpi v config register 1 + 0x34 + 0x20 + 0x00020021 + + + VBANK + this field configures the length between vsync and valid line (by line) for dpi output + 0 + 12 + read-write + + + VSYNC + this field configures the length of vsync (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG0 + dsi bridge dpi h config register 0 + 0x38 + 0x20 + 0x02800320 + + + HTOTAL + this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + 0 + 12 + read-write + + + HDISP + this field configures the length of valid pixel data (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG1 + dsi bridge dpi h config register 1 + 0x3C + 0x20 + 0x00600030 + + + HBANK + this field configures the length between hsync and pixel data valid (by pixel num) for dpi output + 0 + 12 + read-write + + + HSYNC + this field configures the length of hsync (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_MISC_CONFIG + dsi_bridge dpi misc config register + 0x40 + 0x20 + 0x000019D0 + + + DPI_EN + this bit configures enable of dpi output, 0: disable, 1: enable + 0 + 1 + read-write + + + FIFO_UNDERRUN_DISCARD_VCNT + this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field + 4 + 12 + read-write + + + + + DPI_CONFIG_UPDATE + dsi_bridge dpi config update register + 0x44 + 0x20 + + + DPI_CONFIG_UPDATE + write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + 0 + 1 + write-only + + + + + INT_ENA + dsi_bridge interrupt enable register + 0x50 + 0x20 + + + UNDERRUN_INT_ENA + write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal + 0 + 1 + read-write + + + + + INT_CLR + dsi_bridge interrupt clear register + 0x54 + 0x20 + + + UNDERRUN_INT_CLR + write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + 0 + 1 + write-only + + + + + INT_RAW + dsi_bridge raw interrupt register + 0x58 + 0x20 + + + UNDERRUN_INT_RAW + the raw interrupt status of dpi_underrun + 0 + 1 + read-write + + + + + INT_ST + dsi_bridge masked interrupt register + 0x5C + 0x20 + + + UNDERRUN_INT_ST + the masked interrupt status of dpi_underrun + 0 + 1 + read-only + + + + + HOST_BIST_CTL + dsi_bridge host bist control register + 0x60 + 0x20 + + + BISTOK + bistok + 0 + 1 + read-only + + + BISTON + biston + 1 + 1 + read-write + + + + + HOST_TRIGGER_REV + dsi_bridge host trigger reverse control register + 0x64 + 0x20 + + + TX_TRIGGER_REV_EN + tx_trigger reverse. 0: disable, 1: enable + 0 + 1 + read-write + + + RX_TRIGGER_REV_EN + rx_trigger reverse. 0: disable, 1: enable + 1 + 1 + read-write + + + + + BLK_RAW_NUM_CFG + dsi_bridge block raw number control register + 0x68 + 0x20 + 0x00038400 + + + BLK_RAW_NUM_TOTAL + this field configures number of total block pix bits/64 + 0 + 22 + read-write + + + BLK_RAW_NUM_TOTAL_SET + write 1 to reload reg_blk_raw_num_total to internal cnt + 31 + 1 + write-only + + + + + DMA_FRAME_INTERVAL + dsi_bridge dam frame interval control register + 0x6C + 0x20 + 0x20002409 + + + DMA_FRAME_SLOT + this field configures the max frame_slot_cnt + 0 + 10 + read-write + + + DMA_FRAME_INTERVAL + this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full + 10 + 18 + read-write + + + DMA_MULTIBLK_EN + this bit configures enable multi-blk transfer, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable interval between frame transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + MEM_AUX_CTRL + dsi_bridge mem aux control register + 0x70 + 0x20 + 0x00001320 + + + DSI_MEM_AUX_CTRL + this field configures dsi_bridge fifo memory aux ctrl + 0 + 14 + read-write + + + + + RDN_ECO_CS + dsi_bridge rdn eco cs register + 0x74 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + dsi_bridge rdn eco all low register + 0x78 + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + dsi_bridge rdn eco all high register + 0x7C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + HOST_CTRL + dsi_bridge host control register + 0x80 + 0x20 + 0x00000001 + + + DSI_CFG_REF_CLK_EN + this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable + 0 + 1 + read-write + + + + + MEM_CLK_CTRL + dsi_bridge mem force on control register + 0x84 + 0x20 + + + DSI_BRIDGE_MEM_CLK_FORCE_ON + this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on + 0 + 1 + read-write + + + DSI_MEM_CLK_FORCE_ON + this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + 1 + 1 + read-write + + + + + DMA_FLOW_CTRL + dsi_bridge dma flow controller register + 0x88 + 0x20 + 0x00000011 + + + DSI_DMA_FLOW_CONTROLLER + this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller + 0 + 1 + read-write + + + DMA_FLOW_MULTIBLK_NUM + this field configures the num of blocks when multi-blk is enable and dmac as flow controller + 4 + 4 + read-write + + + + + RAW_BUF_ALMOST_EMPTY_THRD + dsi_bridge buffer empty threshold register + 0x8C + 0x20 + 0x00000200 + + + DSI_RAW_BUF_ALMOST_EMPTY_THRD + this field configures the fifo almost empty threshold, is valid only when dmac as flow controller + 0 + 11 + read-write + + + + + YUV_CFG + dsi_bridge yuv format config register + 0x90 + 0x20 + + + PROTOCAL + this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + 0 + 1 + read-write + + + YUV_PIX_ENDIAN + this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + 1 + 1 + read-write + + + YUV422_FORMAT + this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + 2 + 2 + read-write + + + + + PHY_LP_LOOPBACK_CTRL + dsi phy lp_loopback test ctrl + 0x94 + 0x20 + + + PHY_LP_TXDATAESC_1 + txdataesc_1 ctrl when enable dsi phy lp_loopback_test + 0 + 8 + read-write + + + PHY_LP_TXREQUESTESC_1 + txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + 8 + 1 + read-write + + + PHY_LP_TXVALIDESC_1 + txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + 9 + 1 + read-write + + + PHY_LP_TXLPDTESC_1 + txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + 10 + 1 + read-write + + + PHY_LP_BASEDIR_1 + basedir_1 ctrl when enable dsi phy lp_loopback_test + 11 + 1 + read-write + + + PHY_LP_TXDATAESC_0 + txdataesc_0 ctrl when enable dsi phy lp_loopback_test + 16 + 8 + read-write + + + PHY_LP_TXREQUESTESC_0 + txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + 24 + 1 + read-write + + + PHY_LP_TXVALIDESC_0 + txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + 25 + 1 + read-write + + + PHY_LP_TXLPDTESC_0 + txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + 26 + 1 + read-write + + + PHY_LP_BASEDIR_0 + basedir_0 ctrl when enable dsi phy lp_loopback_test + 27 + 1 + read-write + + + PHY_LP_LOOPBACK_CHECK + dsi phy lp_loopback test start check + 28 + 1 + write-only + + + PHY_LP_LOOPBACK_CHECK_DONE + dsi phy lp_loopback test check done + 29 + 1 + read-only + + + PHY_LP_LOOPBACK_EN + dsi phy lp_loopback ctrl en + 30 + 1 + read-write + + + PHY_LP_LOOPBACK_OK + result of dsi phy lp_loopback test + 31 + 1 + read-only + + + + + PHY_HS_LOOPBACK_CTRL + dsi phy hp_loopback test ctrl + 0x98 + 0x20 + 0x00000200 + + + PHY_HS_TXDATAHS_1 + txdatahs_1 ctrl when enable dsi phy hs_loopback_test + 0 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_1 + txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + 8 + 1 + read-write + + + PHY_HS_BASEDIR_1 + basedir_1 ctrl when enable dsi phy hs_loopback_test + 9 + 1 + read-write + + + PHY_HS_TXDATAHS_0 + txdatahs_0 ctrl when enable dsi phy hs_loopback_test + 16 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_0 + txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + 24 + 1 + read-write + + + PHY_HS_BASEDIR_0 + basedir_0 ctrl when enable dsi phy hs_loopback_test + 25 + 1 + read-write + + + PHY_HS_TXREQUESTHSCLK + txrequesthsclk when enable dsi phy hs_loopback_test + 27 + 1 + read-write + + + PHY_HS_LOOPBACK_CHECK + dsi phy hs_loopback test start check + 28 + 1 + write-only + + + PHY_HS_LOOPBACK_CHECK_DONE + dsi phy hs_loopback test check done + 29 + 1 + read-only + + + PHY_HS_LOOPBACK_EN + dsi phy hs_loopback ctrl en + 30 + 1 + read-write + + + PHY_HS_LOOPBACK_OK + result of dsi phy hs_loopback test + 31 + 1 + read-only + + + + + PHY_LOOPBACK_CNT + loopback test cnt + 0x9C + 0x20 + 0x00400040 + + + PHY_HS_CHECK_CNT_TH + hs_loopback test check cnt + 0 + 8 + read-write + + + PHY_LP_CHECK_CNT_TH + lp_loopback test check cnt + 16 + 8 + read-write + + + + + + + MIPI_DSI_HOST + MIPI Display Interface Host + DSI_HOST + 0x500A0000 + + 0x0 + 0x128 + registers + + + DSI + 88 + + + + VERSION + NA + 0x0 + 0x20 + 0x3134312A + + + VERSION + NA + 0 + 32 + read-only + + + + + PWR_UP + NA + 0x4 + 0x20 + + + SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + CLKMGR_CFG + NA + 0x8 + 0x20 + + + TX_ESC_CLK_DIVISION + NA + 0 + 8 + read-write + + + TO_CLK_DIVISION + NA + 8 + 8 + read-write + + + + + DPI_VCID + NA + 0xC + 0x20 + + + DPI_VCID + NA + 0 + 2 + read-write + + + + + DPI_COLOR_CODING + NA + 0x10 + 0x20 + + + DPI_COLOR_CODING + NA + 0 + 4 + read-write + + + LOOSELY18_EN + NA + 8 + 1 + read-write + + + + + DPI_CFG_POL + NA + 0x14 + 0x20 + + + DATAEN_ACTIVE_LOW + NA + 0 + 1 + read-write + + + VSYNC_ACTIVE_LOW + NA + 1 + 1 + read-write + + + HSYNC_ACTIVE_LOW + NA + 2 + 1 + read-write + + + SHUTD_ACTIVE_LOW + NA + 3 + 1 + read-write + + + COLORM_ACTIVE_LOW + NA + 4 + 1 + read-write + + + + + DPI_LP_CMD_TIM + NA + 0x18 + 0x20 + + + INVACT_LPCMD_TIME + NA + 0 + 8 + read-write + + + OUTVACT_LPCMD_TIME + NA + 16 + 8 + read-write + + + + + DBI_VCID + NA + 0x1C + 0x20 + + + DBI_VCID + NA + 0 + 2 + read-write + + + + + DBI_CFG + NA + 0x20 + 0x20 + + + IN_DBI_CONF + NA + 0 + 4 + read-write + + + OUT_DBI_CONF + NA + 8 + 4 + read-write + + + LUT_SIZE_CONF + NA + 16 + 2 + read-write + + + + + DBI_PARTITIONING_EN + NA + 0x24 + 0x20 + + + PARTITIONING_EN + NA + 0 + 1 + read-write + + + + + DBI_CMDSIZE + NA + 0x28 + 0x20 + + + WR_CMD_SIZE + NA + 0 + 16 + read-write + + + ALLOWED_CMD_SIZE + NA + 16 + 16 + read-write + + + + + PCKHDL_CFG + NA + 0x2C + 0x20 + + + EOTP_TX_EN + NA + 0 + 1 + read-write + + + EOTP_RX_EN + NA + 1 + 1 + read-write + + + BTA_EN + NA + 2 + 1 + read-write + + + ECC_RX_EN + NA + 3 + 1 + read-write + + + CRC_RX_EN + NA + 4 + 1 + read-write + + + EOTP_TX_LP_EN + NA + 5 + 1 + read-write + + + + + GEN_VCID + NA + 0x30 + 0x20 + + + RX + NA + 0 + 2 + read-write + + + TEAR_AUTO + NA + 8 + 2 + read-write + + + TX_AUTO + NA + 16 + 2 + read-write + + + + + MODE_CFG + NA + 0x34 + 0x20 + 0x00000001 + + + CMD_VIDEO_MODE + NA + 0 + 1 + read-write + + + + + VID_MODE_CFG + NA + 0x38 + 0x20 + + + VID_MODE_TYPE + NA + 0 + 2 + read-write + + + LP_VSA_EN + NA + 8 + 1 + read-write + + + LP_VBP_EN + NA + 9 + 1 + read-write + + + LP_VFP_EN + NA + 10 + 1 + read-write + + + LP_VACT_EN + NA + 11 + 1 + read-write + + + LP_HBP_EN + NA + 12 + 1 + read-write + + + LP_HFP_EN + NA + 13 + 1 + read-write + + + FRAME_BTA_ACK_EN + NA + 14 + 1 + read-write + + + LP_CMD_EN + NA + 15 + 1 + read-write + + + VPG_EN + NA + 16 + 1 + read-write + + + VPG_MODE + NA + 20 + 1 + read-write + + + VPG_ORIENTATION + NA + 24 + 1 + read-write + + + + + VID_PKT_SIZE + NA + 0x3C + 0x20 + + + VID_PKT_SIZE + NA + 0 + 14 + read-write + + + + + VID_NUM_CHUNKS + NA + 0x40 + 0x20 + + + VID_NUM_CHUNKS + NA + 0 + 13 + read-write + + + + + VID_NULL_SIZE + NA + 0x44 + 0x20 + + + VID_NULL_SIZE + NA + 0 + 13 + read-write + + + + + VID_HSA_TIME + NA + 0x48 + 0x20 + + + VID_HSA_TIME + NA + 0 + 12 + read-write + + + + + VID_HBP_TIME + NA + 0x4C + 0x20 + + + VID_HBP_TIME + NA + 0 + 12 + read-write + + + + + VID_HLINE_TIME + NA + 0x50 + 0x20 + + + VID_HLINE_TIME + NA + 0 + 15 + read-write + + + + + VID_VSA_LINES + NA + 0x54 + 0x20 + + + VSA_LINES + NA + 0 + 10 + read-write + + + + + VID_VBP_LINES + NA + 0x58 + 0x20 + + + VBP_LINES + NA + 0 + 10 + read-write + + + + + VID_VFP_LINES + NA + 0x5C + 0x20 + + + VFP_LINES + NA + 0 + 10 + read-write + + + + + VID_VACTIVE_LINES + NA + 0x60 + 0x20 + + + V_ACTIVE_LINES + NA + 0 + 14 + read-write + + + + + EDPI_CMD_SIZE + NA + 0x64 + 0x20 + + + EDPI_ALLOWED_CMD_SIZE + NA + 0 + 16 + read-write + + + + + CMD_MODE_CFG + NA + 0x68 + 0x20 + + + TEAR_FX_EN + NA + 0 + 1 + read-write + + + ACK_RQST_EN + NA + 1 + 1 + read-write + + + GEN_SW_0P_TX + NA + 8 + 1 + read-write + + + GEN_SW_1P_TX + NA + 9 + 1 + read-write + + + GEN_SW_2P_TX + NA + 10 + 1 + read-write + + + GEN_SR_0P_TX + NA + 11 + 1 + read-write + + + GEN_SR_1P_TX + NA + 12 + 1 + read-write + + + GEN_SR_2P_TX + NA + 13 + 1 + read-write + + + GEN_LW_TX + NA + 14 + 1 + read-write + + + DCS_SW_0P_TX + NA + 16 + 1 + read-write + + + DCS_SW_1P_TX + NA + 17 + 1 + read-write + + + DCS_SR_0P_TX + NA + 18 + 1 + read-write + + + DCS_LW_TX + NA + 19 + 1 + read-write + + + MAX_RD_PKT_SIZE + NA + 24 + 1 + read-write + + + + + GEN_HDR + NA + 0x6C + 0x20 + + + GEN_DT + NA + 0 + 6 + read-write + + + GEN_VC + NA + 6 + 2 + read-write + + + GEN_WC_LSBYTE + NA + 8 + 8 + read-write + + + GEN_WC_MSBYTE + NA + 16 + 8 + read-write + + + + + GEN_PLD_DATA + NA + 0x70 + 0x20 + + + GEN_PLD_B1 + NA + 0 + 8 + read-write + + + GEN_PLD_B2 + NA + 8 + 8 + read-write + + + GEN_PLD_B3 + NA + 16 + 8 + read-write + + + GEN_PLD_B4 + NA + 24 + 8 + read-write + + + + + CMD_PKT_STATUS + NA + 0x74 + 0x20 + 0x00050015 + + + GEN_CMD_EMPTY + NA + 0 + 1 + read-only + + + GEN_CMD_FULL + NA + 1 + 1 + read-only + + + GEN_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + GEN_PLD_W_FULL + NA + 3 + 1 + read-only + + + GEN_PLD_R_EMPTY + NA + 4 + 1 + read-only + + + GEN_PLD_R_FULL + NA + 5 + 1 + read-only + + + GEN_RD_CMD_BUSY + NA + 6 + 1 + read-only + + + GEN_BUFF_CMD_EMPTY + NA + 16 + 1 + read-only + + + GEN_BUFF_CMD_FULL + NA + 17 + 1 + read-only + + + GEN_BUFF_PLD_EMPTY + NA + 18 + 1 + read-only + + + GEN_BUFF_PLD_FULL + NA + 19 + 1 + read-only + + + + + TO_CNT_CFG + NA + 0x78 + 0x20 + + + LPRX_TO_CNT + NA + 0 + 16 + read-write + + + HSTX_TO_CNT + NA + 16 + 16 + read-write + + + + + HS_RD_TO_CNT + NA + 0x7C + 0x20 + + + HS_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_RD_TO_CNT + NA + 0x80 + 0x20 + + + LP_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + HS_WR_TO_CNT + NA + 0x84 + 0x20 + + + HS_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_WR_TO_CNT + NA + 0x88 + 0x20 + + + LP_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + BTA_TO_CNT + NA + 0x8C + 0x20 + + + BTA_TO_CNT + NA + 0 + 16 + read-write + + + + + SDF_3D + NA + 0x90 + 0x20 + + + MODE_3D + NA + 0 + 2 + read-write + + + FORMAT_3D + NA + 2 + 2 + read-write + + + SECOND_VSYNC + NA + 4 + 1 + read-write + + + RIGHT_FIRST + NA + 5 + 1 + read-write + + + SEND_3D_CFG + NA + 16 + 1 + read-write + + + + + LPCLK_CTRL + NA + 0x94 + 0x20 + + + PHY_TXREQUESTCLKHS + NA + 0 + 1 + read-write + + + AUTO_CLKLANE_CTRL + NA + 1 + 1 + read-write + + + + + PHY_TMR_LPCLK_CFG + NA + 0x98 + 0x20 + + + PHY_CLKLP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_CLKHS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_TMR_CFG + NA + 0x9C + 0x20 + + + PHY_LP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_HS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_RSTZ + NA + 0xA0 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + PHY_RSTZ + NA + 1 + 1 + read-write + + + PHY_ENABLECLK + NA + 2 + 1 + read-write + + + PHY_FORCEPLL + NA + 3 + 1 + read-write + + + + + PHY_IF_CFG + NA + 0xA4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 2 + read-write + + + PHY_STOP_WAIT_TIME + NA + 8 + 8 + read-write + + + + + PHY_ULPS_CTRL + NA + 0xA8 + 0x20 + + + PHY_TXREQULPSCLK + NA + 0 + 1 + read-write + + + PHY_TXEXITULPSCLK + NA + 1 + 1 + read-write + + + PHY_TXREQULPSLAN + NA + 2 + 1 + read-write + + + PHY_TXEXITULPSLAN + NA + 3 + 1 + read-write + + + + + PHY_TX_TRIGGERS + NA + 0xAC + 0x20 + + + PHY_TX_TRIGGERS + NA + 0 + 4 + read-write + + + + + PHY_STATUS + NA + 0xB0 + 0x20 + 0x00000140 + + + PHY_LOCK + NA + 0 + 1 + read-only + + + PHY_DIRECTION + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLKLANE + NA + 2 + 1 + read-only + + + PHY_ULPSACTIVENOTCLK + NA + 3 + 1 + read-only + + + PHY_STOPSTATE0LANE + NA + 4 + 1 + read-only + + + PHY_ULPSACTIVENOT0LANE + NA + 5 + 1 + read-only + + + PHY_RXULPSESC0LANE + NA + 6 + 1 + read-only + + + PHY_STOPSTATE1LANE + NA + 7 + 1 + read-only + + + PHY_ULPSACTIVENOT1LANE + NA + 8 + 1 + read-only + + + + + PHY_TST_CTRL0 + NA + 0xB4 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TST_CTRL1 + NA + 0xB8 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHT_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + INT_ST0 + NA + 0xBC + 0x20 + + + ACK_WITH_ERR_0 + NA + 0 + 1 + read-only + + + ACK_WITH_ERR_1 + NA + 1 + 1 + read-only + + + ACK_WITH_ERR_2 + NA + 2 + 1 + read-only + + + ACK_WITH_ERR_3 + NA + 3 + 1 + read-only + + + ACK_WITH_ERR_4 + NA + 4 + 1 + read-only + + + ACK_WITH_ERR_5 + NA + 5 + 1 + read-only + + + ACK_WITH_ERR_6 + NA + 6 + 1 + read-only + + + ACK_WITH_ERR_7 + NA + 7 + 1 + read-only + + + ACK_WITH_ERR_8 + NA + 8 + 1 + read-only + + + ACK_WITH_ERR_9 + NA + 9 + 1 + read-only + + + ACK_WITH_ERR_10 + NA + 10 + 1 + read-only + + + ACK_WITH_ERR_11 + NA + 11 + 1 + read-only + + + ACK_WITH_ERR_12 + NA + 12 + 1 + read-only + + + ACK_WITH_ERR_13 + NA + 13 + 1 + read-only + + + ACK_WITH_ERR_14 + NA + 14 + 1 + read-only + + + ACK_WITH_ERR_15 + NA + 15 + 1 + read-only + + + DPHY_ERRORS_0 + NA + 16 + 1 + read-only + + + DPHY_ERRORS_1 + NA + 17 + 1 + read-only + + + DPHY_ERRORS_2 + NA + 18 + 1 + read-only + + + DPHY_ERRORS_3 + NA + 19 + 1 + read-only + + + DPHY_ERRORS_4 + NA + 20 + 1 + read-only + + + + + INT_ST1 + NA + 0xC0 + 0x20 + + + TO_HS_TX + NA + 0 + 1 + read-only + + + TO_LP_RX + NA + 1 + 1 + read-only + + + ECC_SINGLE_ERR + NA + 2 + 1 + read-only + + + ECC_MILTI_ERR + NA + 3 + 1 + read-only + + + CRC_ERR + NA + 4 + 1 + read-only + + + PKT_SIZE_ERR + NA + 5 + 1 + read-only + + + EOPT_ERR + NA + 6 + 1 + read-only + + + DPI_PLD_WR_ERR + NA + 7 + 1 + read-only + + + GEN_CMD_WR_ERR + NA + 8 + 1 + read-only + + + GEN_PLD_WR_ERR + NA + 9 + 1 + read-only + + + GEN_PLD_SEND_ERR + NA + 10 + 1 + read-only + + + GEN_PLD_RD_ERR + NA + 11 + 1 + read-only + + + GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-only + + + DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-only + + + + + INT_MSK0 + NA + 0xC4 + 0x20 + + + MASK_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + MASK_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + MASK_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + MASK_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + MASK_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + MASK_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + MASK_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + MASK_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + MASK_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + MASK_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + MASK_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + MASK_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + MASK_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + MASK_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + MASK_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + MASK_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + MASK_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + MASK_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + MASK_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + MASK_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + MASK_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_MSK1 + NA + 0xC8 + 0x20 + + + MASK_TO_HS_TX + NA + 0 + 1 + read-write + + + MASK_TO_LP_RX + NA + 1 + 1 + read-write + + + MASK_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + MASK_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + MASK_CRC_ERR + NA + 4 + 1 + read-write + + + MASK_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + MASK_EOPT_ERR + NA + 6 + 1 + read-write + + + MASK_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + MASK_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + MASK_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + MASK_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + MASK_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + MASK_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + MASK_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + PHY_CAL + NA + 0xCC + 0x20 + + + TXSKEWCALHS + NA + 0 + 1 + read-write + + + + + INT_FORCE0 + NA + 0xD8 + 0x20 + + + FORCE_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + FORCE_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + FORCE_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + FORCE_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + FORCE_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + FORCE_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + FORCE_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + FORCE_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + FORCE_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + FORCE_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + FORCE_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + FORCE_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + FORCE_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + FORCE_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + FORCE_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + FORCE_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + FORCE_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + FORCE_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + FORCE_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + FORCE_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + FORCE_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_FORCE1 + NA + 0xDC + 0x20 + + + FORCE_TO_HS_TX + NA + 0 + 1 + read-write + + + FORCE_TO_LP_RX + NA + 1 + 1 + read-write + + + FORCE_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + FORCE_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + FORCE_CRC_ERR + NA + 4 + 1 + read-write + + + FORCE_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + FORCE_EOPT_ERR + NA + 6 + 1 + read-write + + + FORCE_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + FORCE_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + FORCE_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + FORCE_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + FORCE_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + FORCE_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + FORCE_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + DSC_PARAMETER + NA + 0xF0 + 0x20 + + + COMPRESSION_MODE + NA + 0 + 1 + read-write + + + COMPRESS_ALGO + NA + 8 + 2 + read-write + + + PPS_SEL + NA + 16 + 2 + read-write + + + + + PHY_TMR_RD_CFG + NA + 0xF4 + 0x20 + + + MAX_RD_TIME + NA + 0 + 15 + read-write + + + + + VID_SHADOW_CTRL + NA + 0x100 + 0x20 + + + VID_SHADOW_EN + NA + 0 + 1 + read-write + + + VID_SHADOW_REQ + NA + 8 + 1 + read-write + + + VID_SHADOW_PIN_REQ + NA + 16 + 1 + read-write + + + + + DPI_VCID_ACT + NA + 0x10C + 0x20 + + + DPI_VCID_ACT + NA + 0 + 2 + read-only + + + + + DPI_COLOR_CODING_ACT + NA + 0x110 + 0x20 + + + DPI_COLOR_CODING_ACT + NA + 0 + 4 + read-only + + + LOOSELY18_EN_ACT + NA + 8 + 1 + read-only + + + + + DPI_LP_CMD_TIM_ACT + NA + 0x118 + 0x20 + + + INVACT_LPCMD_TIME_ACT + NA + 0 + 8 + read-only + + + OUTVACT_LPCMD_TIME_ACT + NA + 16 + 8 + read-only + + + + + EDPI_TE_HW_CFG + NA + 0x11C + 0x20 + + + HW_TEAR_EFFECT_ON + NA + 0 + 1 + read-write + + + HW_TEAR_EFFECT_GEN + NA + 1 + 1 + read-write + + + HW_SET_SCAN_LINE + NA + 4 + 1 + read-write + + + SCAN_LINE_PARAMETER + NA + 16 + 16 + read-write + + + + + VID_MODE_CFG_ACT + NA + 0x138 + 0x20 + + + VID_MODE_TYPE_ACT + NA + 0 + 2 + read-only + + + LP_VSA_EN_ACT + NA + 2 + 1 + read-only + + + LP_VBP_EN_ACT + NA + 3 + 1 + read-only + + + LP_VFP_EN_ACT + NA + 4 + 1 + read-only + + + LP_VACT_EN_ACT + NA + 5 + 1 + read-only + + + LP_HBP_EN_ACT + NA + 6 + 1 + read-only + + + LP_HFP_EN_ACT + NA + 7 + 1 + read-only + + + FRAME_BTA_ACK_EN_ACT + NA + 8 + 1 + read-only + + + LP_CMD_EN_ACT + NA + 9 + 1 + read-only + + + + + VID_PKT_SIZE_ACT + NA + 0x13C + 0x20 + + + VID_PKT_SIZE_ACT + NA + 0 + 14 + read-only + + + + + VID_NUM_CHUNKS_ACT + NA + 0x140 + 0x20 + + + VID_NUM_CHUNKS_ACT + NA + 0 + 13 + read-only + + + + + VID_NULL_SIZE_ACT + NA + 0x144 + 0x20 + + + VID_NULL_SIZE_ACT + NA + 0 + 13 + read-only + + + + + VID_HSA_TIME_ACT + NA + 0x148 + 0x20 + + + VID_HSA_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HBP_TIME_ACT + NA + 0x14C + 0x20 + + + VID_HBP_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HLINE_TIME_ACT + NA + 0x150 + 0x20 + + + VID_HLINE_TIME_ACT + NA + 0 + 15 + read-only + + + + + VID_VSA_LINES_ACT + NA + 0x154 + 0x20 + + + VSA_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VBP_LINES_ACT + NA + 0x158 + 0x20 + + + VBP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VFP_LINES_ACT + NA + 0x15C + 0x20 + + + VFP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VACTIVE_LINES_ACT + NA + 0x160 + 0x20 + + + V_ACTIVE_LINES_ACT + NA + 0 + 14 + read-only + + + + + VID_PKT_STATUS + NA + 0x168 + 0x20 + 0x00010005 + + + DPI_CMD_W_EMPTY + NA + 0 + 1 + read-only + + + DPI_CMD_W_FULL + NA + 1 + 1 + read-only + + + DPI_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + DPI_PLD_W_FULL + NA + 3 + 1 + read-only + + + DPI_BUFF_PLD_EMPTY + NA + 16 + 1 + read-only + + + DPI_BUFF_PLD_FULL + NA + 17 + 1 + read-only + + + + + SDF_3D_ACT + NA + 0x190 + 0x20 + + + MODE_3D_ACT + NA + 0 + 2 + read-only + + + FORMAT_3D_ACT + NA + 2 + 2 + read-only + + + SECOND_VSYNC_ACT + NA + 4 + 1 + read-only + + + RIGHT_FIRST_ACT + NA + 5 + 1 + read-only + + + SEND_3D_CFG_ACT + NA + 16 + 1 + read-only + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x50093000 + + 0x0 + 0x78 + registers + + + ECC + 71 + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + MOD_BASE + The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + 3 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + 4 + 4 + read-write + + + SECURITY_MODE + Reserved + 8 + 1 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 29 + 1 + read-only + + + CLK_EN + Write 1 to force on register clock gate. + 30 + 1 + read-write + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 8 + 0x4 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x20 + + + 8 + 0x4 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x20 + + + 8 + 0x4 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x20 + + + + + ECDSA + ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + ECDSA + 0x50096000 + + 0x0 + 0xF8 + registers + + + + CONF + ECDSA configure register + 0x4 + 0x20 + + + WORK_MODE + The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. + 0 + 2 + read-write + + + ECC_CURVE + The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SOFTWARE_SET_K + The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. + 3 + 1 + read-write + + + SOFTWARE_SET_Z + The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. + 4 + 1 + read-write + + + DETERMINISTIC_K + The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. + 5 + 1 + read-write + + + DETERMINISTIC_LOOP + The (loop number - 1) value in the deterministic derivation algorithm to derive k. + 6 + 16 + read-write + + + + + CLK + ECDSA clock gate register + 0x8 + 0x20 + + + GATE_FORCE_ON + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + + + INT_RAW + ECDSA interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_RAW + The raw interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ST + ECDSA interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_ST + The masked interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ENA + ECDSA interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-write + + + SHA_RELEASE_INT_ENA + The interrupt enable bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-write + + + + + INT_CLR + ECDSA interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecdsa_calc_done_int interrupt + 0 + 1 + write-only + + + SHA_RELEASE_INT_CLR + Set this bit to clear the ecdsa_sha_release_int interrupt + 1 + 1 + write-only + + + + + START + ECDSA start register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + LOAD_DONE + Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 1 + 1 + write-only + + + GET_DONE + Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 2 + 1 + write-only + + + + + STATE + ECDSA status register + 0x20 + 0x20 + + + BUSY + The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. + 0 + 2 + read-only + + + + + RESULT + ECDSA result register + 0x24 + 0x20 + + + OPERATION_RESULT + The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. + 0 + 1 + read-only + + + K_VALUE_WARNING + The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. + 1 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02304070 + + + DATE + ECDSA version control register + 0 + 28 + read-write + + + + + SHA_MODE + ECDSA control SHA register + 0x200 + 0x20 + + + SHA_MODE + The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. + 0 + 3 + read-write + + + + + SHA_START + ECDSA control SHA register + 0x210 + 0x20 + + + SHA_START + Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_CONTINUE + ECDSA control SHA register + 0x214 + 0x20 + + + SHA_CONTINUE + Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_BUSY + ECDSA status register + 0x218 + 0x20 + + + SHA_BUSY + The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. + 0 + 1 + read-only + + + + + 8 + 0x4 + MESSAGE_MEM[%s] + The memory that stores message. + 0x280 + 0x20 + + + 8 + 0x4 + R_MEM[%s] + The memory that stores r. + 0xA00 + 0x20 + + + 8 + 0x4 + S_MEM[%s] + The memory that stores s. + 0xA20 + 0x20 + + + 8 + 0x4 + Z_MEM[%s] + The memory that stores software written z. + 0xA40 + 0x20 + + + 8 + 0x4 + QAX_MEM[%s] + The memory that stores x coordinates of QA or software written k. + 0xA60 + 0x20 + + + 8 + 0x4 + QAY_MEM[%s] + The memory that stores y coordinates of QA. + 0xA80 + 0x20 + + + + + EFUSE + eFuse Controller + EFUSE + 0x5012D000 + + 0x0 + 0x3D8 + registers + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + USB_DEVICE_EXCHG_PINS + Enable usb device exchange pins of D+ and D-. + 7 + 1 + read-only + + + USB_OTG11_EXCHG_PINS + Enable usb otg11 exchange pins of D+ and D-. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + POWERGLITCH_EN + Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. + 13 + 1 + read-only + + + DIS_TWAI + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DEVICE_DREFH + USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV + 21 + 2 + read-only + + + USB_OTG11_DREFH + USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV + 23 + 2 + read-only + + + USB_PHY_SEL + TBD + 25 + 1 + read-only + + + KM_HUK_GEN_STATE_LOW + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 26 + 6 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + KM_HUK_GEN_STATE_HIGH + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE + Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE + Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY + Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY + Set this bit to disable software written init key, and force use efuse_init_key. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256 + Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + 14 + 1 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x00080000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K + Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + FLASH_TYPE + The type of interfaced flash. 0: four data lines, 1: eight data lines. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE + Set flash page size. + 24 + 2 + read-only + + + FLASH_ECC_EN + Set this bit to enable ecc for flash boot. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE + Set this bit to disable download via USB-OTG. + 27 + 1 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + LOCK_KM_KEY + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 8 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 25 + 1 + read-only + + + HYS_EN_PAD + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. + 26 + 1 + read-only + + + DCDC_VSET + Set the dcdc voltage default. + 27 + 5 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + _0PXA_TIEH_SEL_0 + TBD + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1 + TBD. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2 + TBD. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3 + TBD. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL + Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 12 + 2 + read-only + + + USB_OTG11_DREFL + Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL + HP system power source select. 0:LDO. 1: DCDC. + 18 + 1 + read-only + + + DCDC_VSET_EN + Select dcdc vset use efuse_dcdc_vset. + 19 + 1 + read-only + + + DIS_WDT + Set this bit to disable watch dog. + 20 + 1 + read-only + + + DIS_SWD + Set this bit to disable super-watchdog. + 21 + 1 + read-only + + + + + RD_MAC_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_RESERVED_1 + Reserved. + 0 + 14 + read-only + + + MAC_RESERVED_0 + Reserved. + 14 + 18 + read-only + + + + + RD_MAC_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + MAC_RESERVED_2 + Reserved. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + DIS_USB_DEVICE_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + 7 + 1 + read-only + + + DIS_USB_OTG11_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + POWERGLITCH_EN_ERR + Indicates a programming error of POWERGLITCH_EN. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_TWAI. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DEVICE_DREFH_ERR + Indicates a programming error of USB_DEVICE_DREFH. + 21 + 2 + read-only + + + USB_OTG11_DREFH_ERR + Indicates a programming error of USB_OTG11_DREFH. + 23 + 2 + read-only + + + USB_PHY_SEL_ERR + Indicates a programming error of USB_PHY_SEL. + 25 + 1 + read-only + + + HUK_GEN_STATE_LOW_ERR + Indicates a programming error of HUK_GEN_STATE_LOW. + 26 + 6 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + KM_HUK_GEN_STATE_HIGH_ERR + Indicates a programming error of HUK_GEN_STATE_HIGH. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE_ERR + Indicates a programming error of KM_RND_SWITCH_CYCLE. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE_ERR + Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY_ERR + Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY_ERR + Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256_ERR + Indicates a programming error of XTS_KEY_LENGTH_256. + 14 + 1 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K_ERR + Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + FLASH_TYPE_ERR + Indicates a programming error of FLASH_TYPE. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + Indicates a programming error of FLASH_PAGE_SIZE. + 24 + 2 + read-only + + + FLASH_ECC_EN_ERR + Indicates a programming error of FLASH_ECC_EN. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + 27 + 1 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + 2 + 1 + read-only + + + LOCK_KM_KEY_ERR + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 8 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE VERSION. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE_ERR + Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + 25 + 1 + read-only + + + HYS_EN_PAD_ERR + Indicates a programming error of HYS_EN_PAD. + 26 + 1 + read-only + + + DCDC_VSET_ERR + Indicates a programming error of DCDC_VSET. + 27 + 5 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x18C + 0x20 + + + _0PXA_TIEH_SEL_0_ERR + Indicates a programming error of 0PXA_TIEH_SEL_0. + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1_ERR + Indicates a programming error of 0PXA_TIEH_SEL_1. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2_ERR + Indicates a programming error of 0PXA_TIEH_SEL_2. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3_ERR + Indicates a programming error of 0PXA_TIEH_SEL_3. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE_ERR + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL_ERR + Indicates a programming error of USB_DEVICE_DREFL. + 12 + 2 + read-only + + + USB_OTG11_DREFL_ERR + Indicates a programming error of USB_OTG11_DREFL. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL_ERR + Indicates a programming error of HP_PWR_SRC_SEL. + 18 + 1 + read-only + + + DCDC_VSET_EN_ERR + Indicates a programming error of DCDC_VSET_EN. + 19 + 1 + read-only + + + DIS_WDT_ERR + Indicates a programming error of DIS_WDT. + 20 + 1 + read-only + + + DIS_SWD_ERR + Indicates a programming error of DIS_SWD. + 21 + 1 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SYS_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SYS_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + CFG_ECDSA_BLK + Configures which block to use for ECDSA key output. + 16 + 4 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + CUR_ECDSA_BLK + Indicates which block is used for ECDSA key output. + 20 + 4 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE17 + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x0F010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01266701 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00A00140 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02305050 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + APB2OTP_WR_DIS + eFuse apb2otp block0 data register1. + 0x800 + 0x20 + + + APB2OTP_BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W1 + eFuse apb2otp block0 data register2. + 0x804 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W2 + eFuse apb2otp block0 data register3. + 0x808 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W3 + eFuse apb2otp block0 data register4. + 0x80C + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W4 + eFuse apb2otp block0 data register5. + 0x810 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W5 + eFuse apb2otp block0 data register6. + 0x814 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W1 + eFuse apb2otp block0 data register7. + 0x818 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W2 + eFuse apb2otp block0 data register8. + 0x81C + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W3 + eFuse apb2otp block0 data register9. + 0x820 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W4 + eFuse apb2otp block0 data register10. + 0x824 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W5 + eFuse apb2otp block0 data register11. + 0x828 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W1 + eFuse apb2otp block0 data register12. + 0x82C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W2 + eFuse apb2otp block0 data register13. + 0x830 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W3 + eFuse apb2otp block0 data register14. + 0x834 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W4 + eFuse apb2otp block0 data register15. + 0x838 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W5 + eFuse apb2otp block0 data register16. + 0x83C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W1 + eFuse apb2otp block0 data register17. + 0x840 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W2 + eFuse apb2otp block0 data register18. + 0x844 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W3 + eFuse apb2otp block0 data register19. + 0x848 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W4 + eFuse apb2otp block0 data register20. + 0x84C + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W5 + eFuse apb2otp block0 data register21. + 0x850 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W1 + eFuse apb2otp block1 data register1. + 0x854 + 0x20 + + + APB2OTP_BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W2 + eFuse apb2otp block1 data register2. + 0x858 + 0x20 + + + APB2OTP_BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W3 + eFuse apb2otp block1 data register3. + 0x85C + 0x20 + + + APB2OTP_BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W4 + eFuse apb2otp block1 data register4. + 0x860 + 0x20 + + + APB2OTP_BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W5 + eFuse apb2otp block1 data register5. + 0x864 + 0x20 + + + APB2OTP_BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W6 + eFuse apb2otp block1 data register6. + 0x868 + 0x20 + + + APB2OTP_BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W7 + eFuse apb2otp block1 data register7. + 0x86C + 0x20 + + + APB2OTP_BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W8 + eFuse apb2otp block1 data register8. + 0x870 + 0x20 + + + APB2OTP_BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W9 + eFuse apb2otp block1 data register9. + 0x874 + 0x20 + + + APB2OTP_BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W1 + eFuse apb2otp block2 data register1. + 0x878 + 0x20 + + + APB2OTP_BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W2 + eFuse apb2otp block2 data register2. + 0x87C + 0x20 + + + APB2OTP_BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W3 + eFuse apb2otp block2 data register3. + 0x880 + 0x20 + + + APB2OTP_BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W4 + eFuse apb2otp block2 data register4. + 0x884 + 0x20 + + + APB2OTP_BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W5 + eFuse apb2otp block2 data register5. + 0x888 + 0x20 + + + APB2OTP_BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W6 + eFuse apb2otp block2 data register6. + 0x88C + 0x20 + + + APB2OTP_BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W7 + eFuse apb2otp block2 data register7. + 0x890 + 0x20 + + + APB2OTP_BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W8 + eFuse apb2otp block2 data register8. + 0x894 + 0x20 + + + APB2OTP_BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W9 + eFuse apb2otp block2 data register9. + 0x898 + 0x20 + + + APB2OTP_BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W10 + eFuse apb2otp block2 data register10. + 0x89C + 0x20 + + + APB2OTP_BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W11 + eFuse apb2otp block2 data register11. + 0x8A0 + 0x20 + + + APB2OTP_BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W1 + eFuse apb2otp block3 data register1. + 0x8A4 + 0x20 + + + APB2OTP_BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W2 + eFuse apb2otp block3 data register2. + 0x8A8 + 0x20 + + + APB2OTP_BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W3 + eFuse apb2otp block3 data register3. + 0x8AC + 0x20 + + + APB2OTP_BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W4 + eFuse apb2otp block3 data register4. + 0x8B0 + 0x20 + + + APB2OTP_BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W5 + eFuse apb2otp block3 data register5. + 0x8B4 + 0x20 + + + APB2OTP_BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W6 + eFuse apb2otp block3 data register6. + 0x8B8 + 0x20 + + + APB2OTP_BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W7 + eFuse apb2otp block3 data register7. + 0x8BC + 0x20 + + + APB2OTP_BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W8 + eFuse apb2otp block3 data register8. + 0x8C0 + 0x20 + + + APB2OTP_BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W9 + eFuse apb2otp block3 data register9. + 0x8C4 + 0x20 + + + APB2OTP_BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W10 + eFuse apb2otp block3 data register10. + 0x8C8 + 0x20 + + + APB2OTP_BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W11 + eFuse apb2otp block3 data register11. + 0x8CC + 0x20 + + + APB2OTP_BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W1 + eFuse apb2otp block4 data register1. + 0x8D0 + 0x20 + + + APB2OTP_BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W2 + eFuse apb2otp block4 data register2. + 0x8D4 + 0x20 + + + APB2OTP_BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W3 + eFuse apb2otp block4 data register3. + 0x8D8 + 0x20 + + + APB2OTP_BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W4 + eFuse apb2otp block4 data register4. + 0x8DC + 0x20 + + + APB2OTP_BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W5 + eFuse apb2otp block4 data register5. + 0x8E0 + 0x20 + + + APB2OTP_BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W6 + eFuse apb2otp block4 data register6. + 0x8E4 + 0x20 + + + APB2OTP_BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W7 + eFuse apb2otp block4 data register7. + 0x8E8 + 0x20 + + + APB2OTP_BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W8 + eFuse apb2otp block4 data register8. + 0x8EC + 0x20 + + + APB2OTP_BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W9 + eFuse apb2otp block4 data register9. + 0x8F0 + 0x20 + + + APB2OTP_BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W10 + eFuse apb2otp block4 data registe10. + 0x8F4 + 0x20 + + + APB2OTP_BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W11 + eFuse apb2otp block4 data register11. + 0x8F8 + 0x20 + + + APB2OTP_BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W1 + eFuse apb2otp block5 data register1. + 0x8FC + 0x20 + + + APB2OTP_BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W2 + eFuse apb2otp block5 data register2. + 0x900 + 0x20 + + + APB2OTP_BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W3 + eFuse apb2otp block5 data register3. + 0x904 + 0x20 + + + APB2OTP_BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W4 + eFuse apb2otp block5 data register4. + 0x908 + 0x20 + + + APB2OTP_BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W5 + eFuse apb2otp block5 data register5. + 0x90C + 0x20 + + + APB2OTP_BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W6 + eFuse apb2otp block5 data register6. + 0x910 + 0x20 + + + APB2OTP_BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W7 + eFuse apb2otp block5 data register7. + 0x914 + 0x20 + + + APB2OTP_BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W8 + eFuse apb2otp block5 data register8. + 0x918 + 0x20 + + + APB2OTP_BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W9 + eFuse apb2otp block5 data register9. + 0x91C + 0x20 + + + APB2OTP_BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W10 + eFuse apb2otp block5 data register10. + 0x920 + 0x20 + + + APB2OTP_BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W11 + eFuse apb2otp block5 data register11. + 0x924 + 0x20 + + + APB2OTP_BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W1 + eFuse apb2otp block6 data register1. + 0x928 + 0x20 + + + APB2OTP_BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W2 + eFuse apb2otp block6 data register2. + 0x92C + 0x20 + + + APB2OTP_BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W3 + eFuse apb2otp block6 data register3. + 0x930 + 0x20 + + + APB2OTP_BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W4 + eFuse apb2otp block6 data register4. + 0x934 + 0x20 + + + APB2OTP_BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W5 + eFuse apb2otp block6 data register5. + 0x938 + 0x20 + + + APB2OTP_BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W6 + eFuse apb2otp block6 data register6. + 0x93C + 0x20 + + + APB2OTP_BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W7 + eFuse apb2otp block6 data register7. + 0x940 + 0x20 + + + APB2OTP_BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W8 + eFuse apb2otp block6 data register8. + 0x944 + 0x20 + + + APB2OTP_BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W9 + eFuse apb2otp block6 data register9. + 0x948 + 0x20 + + + APB2OTP_BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W10 + eFuse apb2otp block6 data register10. + 0x94C + 0x20 + + + APB2OTP_BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W11 + eFuse apb2otp block6 data register11. + 0x950 + 0x20 + + + APB2OTP_BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W1 + eFuse apb2otp block7 data register1. + 0x954 + 0x20 + + + APB2OTP_BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W2 + eFuse apb2otp block7 data register2. + 0x958 + 0x20 + + + APB2OTP_BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W3 + eFuse apb2otp block7 data register3. + 0x95C + 0x20 + + + APB2OTP_BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W4 + eFuse apb2otp block7 data register4. + 0x960 + 0x20 + + + APB2OTP_BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W5 + eFuse apb2otp block7 data register5. + 0x964 + 0x20 + + + APB2OTP_BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W6 + eFuse apb2otp block7 data register6. + 0x968 + 0x20 + + + APB2OTP_BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W7 + eFuse apb2otp block7 data register7. + 0x96C + 0x20 + + + APB2OTP_BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W8 + eFuse apb2otp block7 data register8. + 0x970 + 0x20 + + + APB2OTP_BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W9 + eFuse apb2otp block7 data register9. + 0x974 + 0x20 + + + APB2OTP_BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W10 + eFuse apb2otp block7 data register10. + 0x978 + 0x20 + + + APB2OTP_BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W11 + eFuse apb2otp block7 data register11. + 0x97C + 0x20 + + + APB2OTP_BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W1 + eFuse apb2otp block8 data register1. + 0x980 + 0x20 + + + APB2OTP_BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W2 + eFuse apb2otp block8 data register2. + 0x984 + 0x20 + + + APB2OTP_BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W3 + eFuse apb2otp block8 data register3. + 0x988 + 0x20 + + + APB2OTP_BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W4 + eFuse apb2otp block8 data register4. + 0x98C + 0x20 + + + APB2OTP_BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W5 + eFuse apb2otp block8 data register5. + 0x990 + 0x20 + + + APB2OTP_BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W6 + eFuse apb2otp block8 data register6. + 0x994 + 0x20 + + + APB2OTP_BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W7 + eFuse apb2otp block8 data register7. + 0x998 + 0x20 + + + APB2OTP_BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W8 + eFuse apb2otp block8 data register8. + 0x99C + 0x20 + + + APB2OTP_BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W9 + eFuse apb2otp block8 data register9. + 0x9A0 + 0x20 + + + APB2OTP_BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W10 + eFuse apb2otp block8 data register10. + 0x9A4 + 0x20 + + + APB2OTP_BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W11 + eFuse apb2otp block8 data register11. + 0x9A8 + 0x20 + + + APB2OTP_BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W1 + eFuse apb2otp block9 data register1. + 0x9AC + 0x20 + + + APB2OTP_BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W2 + eFuse apb2otp block9 data register2. + 0x9B0 + 0x20 + + + APB2OTP_BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W3 + eFuse apb2otp block9 data register3. + 0x9B4 + 0x20 + + + APB2OTP_BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W4 + eFuse apb2otp block9 data register4. + 0x9B8 + 0x20 + + + APB2OTP_BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W5 + eFuse apb2otp block9 data register5. + 0x9BC + 0x20 + + + APB2OTP_BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W6 + eFuse apb2otp block9 data register6. + 0x9C0 + 0x20 + + + APB2OTP_BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W7 + eFuse apb2otp block9 data register7. + 0x9C4 + 0x20 + + + APB2OTP_BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W8 + eFuse apb2otp block9 data register8. + 0x9C8 + 0x20 + + + APB2OTP_BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W9 + eFuse apb2otp block9 data register9. + 0x9CC + 0x20 + + + APB2OTP_BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W10 + eFuse apb2otp block9 data register10. + 0x9D0 + 0x20 + + + APB2OTP_BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W11 + eFuse apb2otp block9 data register11. + 0x9D4 + 0x20 + + + APB2OTP_BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W1 + eFuse apb2otp block10 data register1. + 0x9D8 + 0x20 + + + APB2OTP_BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W2 + eFuse apb2otp block10 data register2. + 0x9DC + 0x20 + + + APB2OTP_BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W3 + eFuse apb2otp block10 data register3. + 0x9E0 + 0x20 + + + APB2OTP_BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W4 + eFuse apb2otp block10 data register4. + 0x9E4 + 0x20 + + + APB2OTP_BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W5 + eFuse apb2otp block10 data register5. + 0x9E8 + 0x20 + + + APB2OTP_BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W6 + eFuse apb2otp block10 data register6. + 0x9EC + 0x20 + + + APB2OTP_BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W7 + eFuse apb2otp block10 data register7. + 0x9F0 + 0x20 + + + APB2OTP_BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W8 + eFuse apb2otp block10 data register8. + 0x9F4 + 0x20 + + + APB2OTP_BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W9 + eFuse apb2otp block10 data register9. + 0x9F8 + 0x20 + + + APB2OTP_BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W10 + eFuse apb2otp block10 data register10. + 0x9FC + 0x20 + + + APB2OTP_BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W11 + eFuse apb2otp block10 data register11. + 0xA00 + 0x20 + + + APB2OTP_BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_EN + eFuse apb2otp enable configuration register. + 0xA08 + 0x20 + + + APB2OTP_APB2OTP_EN + Apb2otp mode enable signal. + 0 + 1 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x500E0000 + + 0x0 + 0x5F8 + registers + + + GPIO_INT0 + 74 + + + GPIO_INT1 + 75 + + + GPIO_INT2 + 76 + + + GPIO_INT3 + 77 + + + GPIO_PAD_COMP + 78 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-56 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-56 + 0 + 25 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0 + 25 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-56 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-56 + 0 + 25 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0 + 25 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + IN1 + GPIO input register for GPIO32-56 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-56 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-56 + 0 + 25 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0 + 25 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0 + 25 + write-only + + + + + INTR_0 + GPIO interrupt 0 status register for GPIO0-31 + 0x5C + 0x20 + + + INT_0 + GPIO interrupt 0 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0x60 + 0x20 + + + INT1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_1 + GPIO interrupt 1 status register for GPIO0-31 + 0x64 + 0x20 + + + INT_1 + GPIO interrupt 1 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0x68 + 0x20 + + + INT1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x6C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0x70 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0 + 25 + read-only + + + + + 57 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + 57 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x558 + 0x20 + 0x00000100 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + INTR_2 + GPIO interrupt 2 status register for GPIO0-31 + 0x63C + 0x20 + + + INT_2 + GPIO interrupt 2 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0x640 + 0x20 + + + INT1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_3 + GPIO interrupt 3 status register for GPIO0-31 + 0x644 + 0x20 + + + INT_3 + GPIO interrupt 3 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0x648 + 0x20 + + + INT1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0 + 25 + read-only + + + + + CLOCK_GATE + GPIO clock gate register + 0x64C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + INT_RAW + analog comparator interrupt raw + 0x700 + 0x20 + + + COMP0_NEG_INT_RAW + analog comparator pos edge interrupt raw + 0 + 1 + read-write + + + COMP0_POS_INT_RAW + analog comparator neg edge interrupt raw + 1 + 1 + read-write + + + COMP0_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 2 + 1 + read-write + + + COMP1_NEG_INT_RAW + analog comparator pos edge interrupt raw + 3 + 1 + read-write + + + COMP1_POS_INT_RAW + analog comparator neg edge interrupt raw + 4 + 1 + read-write + + + COMP1_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 5 + 1 + read-write + + + BISTOK_INT_RAW + pad bistok interrupt raw + 6 + 1 + read-write + + + BISTFAIL_INT_RAW + pad bistfail interrupt raw + 7 + 1 + read-write + + + + + INT_ST + analog comparator interrupt status + 0x704 + 0x20 + + + COMP0_NEG_INT_ST + analog comparator pos edge interrupt status + 0 + 1 + read-only + + + COMP0_POS_INT_ST + analog comparator neg edge interrupt status + 1 + 1 + read-only + + + COMP0_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 2 + 1 + read-only + + + COMP1_NEG_INT_ST + analog comparator pos edge interrupt status + 3 + 1 + read-only + + + COMP1_POS_INT_ST + analog comparator neg edge interrupt status + 4 + 1 + read-only + + + COMP1_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 5 + 1 + read-only + + + BISTOK_INT_ST + pad bistok interrupt status + 6 + 1 + read-only + + + BISTFAIL_INT_ST + pad bistfail interrupt status + 7 + 1 + read-only + + + + + INT_ENA + analog comparator interrupt enable + 0x708 + 0x20 + 0x000000FF + + + COMP0_NEG_INT_ENA + analog comparator pos edge interrupt enable + 0 + 1 + read-write + + + COMP0_POS_INT_ENA + analog comparator neg edge interrupt enable + 1 + 1 + read-write + + + COMP0_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 2 + 1 + read-write + + + COMP1_NEG_INT_ENA + analog comparator pos edge interrupt enable + 3 + 1 + read-write + + + COMP1_POS_INT_ENA + analog comparator neg edge interrupt enable + 4 + 1 + read-write + + + COMP1_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 5 + 1 + read-write + + + BISTOK_INT_ENA + pad bistok interrupt enable + 6 + 1 + read-write + + + BISTFAIL_INT_ENA + pad bistfail interrupt enable + 7 + 1 + read-write + + + + + INT_CLR + analog comparator interrupt clear + 0x70C + 0x20 + + + COMP0_NEG_INT_CLR + analog comparator pos edge interrupt clear + 0 + 1 + write-only + + + COMP0_POS_INT_CLR + analog comparator neg edge interrupt clear + 1 + 1 + write-only + + + COMP0_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 2 + 1 + write-only + + + COMP1_NEG_INT_CLR + analog comparator pos edge interrupt clear + 3 + 1 + write-only + + + COMP1_POS_INT_CLR + analog comparator neg edge interrupt clear + 4 + 1 + write-only + + + COMP1_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 5 + 1 + write-only + + + BISTOK_INT_CLR + pad bistok interrupt enable + 6 + 1 + write-only + + + BISTFAIL_INT_CLR + pad bistfail interrupt enable + 7 + 1 + write-only + + + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x710 + 0x20 + 0xFFFFFFFF + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x714 + 0x20 + 0xFFFFFFFF + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + SEND_SEQ + High speed sdio pad bist send sequence + 0x718 + 0x20 + 0x12345678 + + + SEND_SEQ + High speed sdio pad bist send sequence + 0 + 32 + read-write + + + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0x71C + 0x20 + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0 + 32 + read-only + + + + + BISTIN_SEL + High speed sdio pad bist in pad sel + 0x720 + 0x20 + 0x0000000F + + + BISTIN_SEL + High speed sdio pad bist in pad sel 0:pad39, 1: pad40... + 0 + 4 + read-write + + + + + BIST_CTRL + High speed sdio pad bist control + 0x724 + 0x20 + 0x00000001 + + + BIST_PAD_OE + High speed sdio pad bist out pad oe + 0 + 1 + read-write + + + BIST_START + High speed sdio pad bist start + 1 + 1 + write-only + + + + + DATE + GPIO version register + 0x7FC + 0x20 + 0x00230403 + + + DATE + version register + 0 + 28 + read-write + + + + + 254 + 0x4 + 1-254 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x15C + 0x20 + read-write + + + IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x500E0F00 + + 0x0 + 0xA4 + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 6 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC + 0x20 + + + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO31_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO31_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P8_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC0 + 0x20 + + + ETM_TASK_GPIO32_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO32_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO33_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO33_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO34_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO34_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO35_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO35_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P9_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC4 + 0x20 + + + ETM_TASK_GPIO36_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO36_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO37_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO37_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO38_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO38_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO39_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO39_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P10_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC8 + 0x20 + + + ETM_TASK_GPIO40_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO40_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO41_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO41_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO42_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO42_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO43_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO43_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P11_CFG + Etm Configure Register to decide which GPIO been chosen + 0xCC + 0x20 + + + ETM_TASK_GPIO44_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO44_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO45_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO45_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO46_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO46_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO47_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO47_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P12_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD0 + 0x20 + + + ETM_TASK_GPIO48_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO48_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO49_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO49_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO50_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO50_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO51_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO51_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P13_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD4 + 0x20 + + + ETM_TASK_GPIO52_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO52_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO53_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO53_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO54_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO54_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02203050 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + H264 + H264 Encoder (Core) + H264 + 0x50084000 + + 0x0 + 0xF4 + registers + + + H264_REG + 126 + + + + SYS_CTRL + H264 system level control register. + 0x0 + 0x20 + + + FRAME_START + Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame + 0 + 1 + write-only + + + DMA_MOVE_START + Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem + 1 + 1 + write-only + + + FRAME_MODE + Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA + 2 + 1 + read-write + + + SYS_RST_PULSE + Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip + 3 + 1 + write-only + + + + + GOP_CONF + GOP related configuration register. + 0x4 + 0x20 + + + DUAL_STREAM_MODE + Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode + 0 + 1 + read-write + + + GOP_NUM + Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP + 1 + 8 + read-write + + + + + A_SYS_MB_RES + Video A horizontal and vertical MB resolution register. + 0x8 + 0x20 + + + A_SYS_TOTAL_MB_Y + Configures video A vertical MB resolution. + 0 + 7 + read-write + + + A_SYS_TOTAL_MB_X + Configures video A horizontal MB resolution. + 7 + 7 + read-write + + + + + A_SYS_CONF + Video A system level configuration register. + 0xC + 0x20 + 0x00000203 + + + A_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + A_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + A_INTRA_COST_CMP_OFFSET + Configures video A intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + A_DECI_SCORE + Video A luma and chroma MB decimate score Register. + 0x10 + 0x20 + + + A_C_DECI_SCORE + Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + A_L_DECI_SCORE + Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + A_DECI_SCORE_OFFSET + Video A luma and chroma MB decimate score offset Register. + 0x14 + 0x20 + + + A_I16X16_DECI_SCORE_OFFSET + Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + A_I_CHROMA_DECI_SCORE_OFFSET + Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + A_P16X16_DECI_SCORE_OFFSET + Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + A_P_CHROMA_DECI_SCORE_OFFSET + Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + A_RC_CONF0 + Video A rate control configuration register0. + 0x18 + 0x20 + + + A_QP + Configures video A frame level initial luma QP value. + 0 + 6 + read-write + + + A_RATE_CTRL_U + Configures video A parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + A_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + A_RC_CONF1 + Video A rate control configuration register1. + 0x1C + 0x20 + + + A_CHROMA_DC_QP_DELTA + Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + A_CHROMA_QP_DELTA + Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + A_QP_MIN + Configures video A allowed luma QP min value. + 7 + 6 + read-write + + + A_QP_MAX + Configures video A allowed luma QP max value. + 13 + 6 + read-write + + + A_MAD_FRAME_PRED + Configures vdieo A frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + A_DB_BYPASS + Video A Deblocking bypass register + 0x20 + 0x20 + + + A_BYPASS_DB_FILTER + Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + A_ROI_REGION0 + Video A H264 ROI region0 range configure register. + 0x24 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION1 + Video A H264 ROI region1 range configure register. + 0x28 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION2 + Video A H264 ROI region2 range configure register. + 0x2C + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION3 + Video A H264 ROI region3 range configure register. + 0x30 + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION4 + Video A H264 ROI region4 range configure register. + 0x34 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION5 + Video A H264 ROI region5 range configure register. + 0x38 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION6 + Video A H264 ROI region6 range configure register. + 0x3C + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION7 + Video A H264 ROI region7 range configure register. + 0x40 + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION0_3_QP + Video A H264 ROI region0, region1,region2,region3 QP register. + 0x44 + 0x20 + + + A_ROI_REGION0_QP + Configure H264 ROI region0 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION1_QP + Configure H264 ROI region1 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION2_QP + Configure H264 ROI region2 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION3_QP + Configure H264 ROI region3 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_ROI_REGION4_7_QP + Video A H264 ROI region4, region5,region6,region7 QP register. + 0x48 + 0x20 + + + A_ROI_REGION4_QP + Configure H264 ROI region4 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION5_QP + Configure H264 ROI region5 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION6_QP + Configure H264 ROI region6 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION7_QP + Configure H264 ROI region7 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_NO_ROI_REGION_QP_OFFSET + Video A H264 no roi region QP register. + 0x4C + 0x20 + + + A_NO_ROI_REGION_QP + Configure H264 no region qp in video A, delta qp. + 0 + 7 + read-write + + + + + A_ROI_CONFIG + Video A H264 ROI configure register. + 0x50 + 0x20 + + + A_ROI_EN + Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + A_ROI_MODE + Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + B_SYS_MB_RES + Video B horizontal and vertical MB resolution register. + 0x54 + 0x20 + + + B_SYS_TOTAL_MB_Y + Configures video B vertical MB resolution. + 0 + 7 + read-write + + + B_SYS_TOTAL_MB_X + Configures video B horizontal MB resolution. + 7 + 7 + read-write + + + + + B_SYS_CONF + Video B system level configuration register. + 0x58 + 0x20 + 0x00000203 + + + B_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + B_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + B_INTRA_COST_CMP_OFFSET + Configures video B intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + B_DECI_SCORE + Video B luma and chroma MB decimate score Register. + 0x5C + 0x20 + + + B_C_DECI_SCORE + Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + B_L_DECI_SCORE + Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + B_DECI_SCORE_OFFSET + Video B luma and chroma MB decimate score offset Register. + 0x60 + 0x20 + + + B_I16X16_DECI_SCORE_OFFSET + Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + B_I_CHROMA_DECI_SCORE_OFFSET + Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + B_P16X16_DECI_SCORE_OFFSET + Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + B_P_CHROMA_DECI_SCORE_OFFSET + Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + B_RC_CONF0 + Video B rate control configuration register0. + 0x64 + 0x20 + + + B_QP + Configures video B frame level initial luma QP value. + 0 + 6 + read-write + + + B_RATE_CTRL_U + Configures video B parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + B_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + B_RC_CONF1 + Video B rate control configuration register1. + 0x68 + 0x20 + + + B_CHROMA_DC_QP_DELTA + Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + B_CHROMA_QP_DELTA + Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + B_QP_MIN + Configures video B allowed luma QP min value. + 7 + 6 + read-write + + + B_QP_MAX + Configures video B allowed luma QP max value. + 13 + 6 + read-write + + + B_MAD_FRAME_PRED + Configures vdieo B frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + B_DB_BYPASS + Video B Deblocking bypass register + 0x6C + 0x20 + + + B_BYPASS_DB_FILTER + Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + B_ROI_REGION0 + Video B H264 ROI region0 range configure register. + 0x70 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION1 + Video B H264 ROI region1 range configure register. + 0x74 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION2 + Video B H264 ROI region2 range configure register. + 0x78 + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION3 + Video B H264 ROI region3 range configure register. + 0x7C + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION4 + Video B H264 ROI region4 range configure register. + 0x80 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION5 + Video B H264 ROI region5 range configure register. + 0x84 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION6 + Video B H264 ROI region6 range configure register. + 0x88 + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION7 + Video B H264 ROI region7 range configure register. + 0x8C + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION0_3_QP + Video B H264 ROI region0, region1,region2,region3 QP register. + 0x90 + 0x20 + + + B_ROI_REGION0_QP + Configure H264 ROI region0 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION1_QP + Configure H264 ROI region1 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION2_QP + Configure H264 ROI region2 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION3_QP + Configure H264 ROI region3 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_ROI_REGION4_7_QP + Video B H264 ROI region4, region5,region6,region7 QP register. + 0x94 + 0x20 + + + B_ROI_REGION4_QP + Configure H264 ROI region4 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION5_QP + Configure H264 ROI region5 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION6_QP + Configure H264 ROI region6 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION7_QP + Configure H264 ROI region7 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_NO_ROI_REGION_QP_OFFSET + Video B H264 no roi region QP register. + 0x98 + 0x20 + + + B_NO_ROI_REGION_QP + Configure H264 no region qp in video B, delta qp. + 0 + 7 + read-write + + + + + B_ROI_CONFIG + Video B H264 ROI configure register. + 0x9C + 0x20 + + + B_ROI_EN + Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + B_ROI_MODE + Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + RC_STATUS0 + Rate control status register0. + 0xA0 + 0x20 + + + FRAME_MAD_SUM + Represents all MB actual MAD sum value of one frame. + 0 + 21 + read-only + + + + + RC_STATUS1 + Rate control status register1. + 0xA4 + 0x20 + + + FRAME_ENC_BITS + Represents all MB actual encoding bits sum value of one frame. + 0 + 27 + read-only + + + + + RC_STATUS2 + Rate control status register2. + 0xA8 + 0x20 + + + FRAME_QP_SUM + Represents all MB actual luma QP sum value of one frame. + 0 + 19 + read-only + + + + + SLICE_HEADER_REMAIN + Frame Slice Header remain bit register. + 0xAC + 0x20 + + + SLICE_REMAIN_BITLENGTH + Configures Slice Header remain bit number + 0 + 3 + read-write + + + SLICE_REMAIN_BIT + Configures Slice Header remain bit + 3 + 8 + read-write + + + + + SLICE_HEADER_BYTE_LENGTH + Frame Slice Header byte length register. + 0xB0 + 0x20 + + + SLICE_BYTE_LENGTH + Configures Slice Header byte number + 0 + 4 + read-write + + + + + BS_THRESHOLD + Bitstream buffer overflow threshold register + 0xB4 + 0x20 + 0x00000030 + + + BS_BUFFER_THRESHOLD + Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. + 0 + 7 + read-write + + + + + SLICE_HEADER_BYTE0 + Frame Slice Header byte low 32 bit register. + 0xB8 + 0x20 + + + SLICE_BYTE_LSB + Configures Slice Header low 32 bit + 0 + 32 + read-write + + + + + SLICE_HEADER_BYTE1 + Frame Slice Header byte high 32 bit register. + 0xBC + 0x20 + + + SLICE_BYTE_MSB + Configures Slice Header high 32 bit + 0 + 32 + read-write + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + DB_TMP_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. + 0 + 1 + read-write + + + REC_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. + 1 + 1 + read-write + + + FRAME_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. + 3 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + DB_TMP_READY_INT_ST + The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. + 0 + 1 + read-only + + + REC_READY_INT_ST + The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. + 1 + 1 + read-only + + + FRAME_DONE_INT_ST + The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. + 2 + 1 + read-only + + + DMA_MOVE_2MB_LINE_DONE_INT_ST + Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + DB_TMP_READY_INT_ENA + Write 1 to enable H264_DB_TMP_READY_INT. + 0 + 1 + read-write + + + REC_READY_INT_ENA + Write 1 to enable H264_REC_READY_INT. + 1 + 1 + read-write + + + FRAME_DONE_INT_ENA + Write 1 to enable H264_FRAME_DONE_INT. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_ENA + Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + DB_TMP_READY_INT_CLR + Write 1 to clear H264_DB_TMP_READY_INT. + 0 + 1 + write-only + + + REC_READY_INT_CLR + Write 1 to clear H264_REC_READY_INT. + 1 + 1 + write-only + + + FRAME_DONE_INT_CLR + Write 1 to clear H264_FRAME_DONE_INT. + 2 + 1 + write-only + + + DMA_MOVE_2MB_LINE_DONE_INT_CLR + Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + write-only + + + + + CONF + General configuration register. + 0xD0 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + REC_RAM_CLK_EN2 + Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 + 1 + 1 + read-write + + + REC_RAM_CLK_EN1 + Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 + 2 + 1 + read-write + + + QUANT_RAM_CLK_EN2 + Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 + 3 + 1 + read-write + + + QUANT_RAM_CLK_EN1 + Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 + 4 + 1 + read-write + + + PRE_RAM_CLK_EN + Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram + 5 + 1 + read-write + + + MVD_RAM_CLK_EN + Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram + 6 + 1 + read-write + + + MC_RAM_CLK_EN + Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram + 7 + 1 + read-write + + + REF_RAM_CLK_EN + Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram + 8 + 1 + read-write + + + I4X4_REF_RAM_CLK_EN + Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram + 9 + 1 + read-write + + + IME_RAM_CLK_EN + Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram + 10 + 1 + read-write + + + FME_RAM_CLK_EN + Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram + 11 + 1 + read-write + + + FETCH_RAM_CLK_EN + Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram + 12 + 1 + read-write + + + DB_RAM_CLK_EN + Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram + 13 + 1 + read-write + + + CUR_MB_RAM_CLK_EN + Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram + 14 + 1 + read-write + + + CAVLC_RAM_CLK_EN + Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram + 15 + 1 + read-write + + + IME_CLK_EN + Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime + 16 + 1 + read-write + + + FME_CLK_EN + Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme + 17 + 1 + read-write + + + MC_CLK_EN + Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc + 18 + 1 + read-write + + + INTERPOLATOR_CLK_EN + Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator + 19 + 1 + read-write + + + DB_CLK_EN + Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter + 20 + 1 + read-write + + + CLAVLC_CLK_EN + Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc + 21 + 1 + read-write + + + INTRA_CLK_EN + Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra + 22 + 1 + read-write + + + DECI_CLK_EN + Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate + 23 + 1 + read-write + + + BS_CLK_EN + Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer + 24 + 1 + read-write + + + MV_MERGE_CLK_EN + Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge + 25 + 1 + read-write + + + + + MV_MERGE_CONFIG + Mv merge configuration register. + 0xD4 + 0x20 + + + MV_MERGE_TYPE + Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. + 0 + 2 + read-write + + + INT_MV_OUT_EN + Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. + 2 + 1 + read-write + + + A_MV_MERGE_EN + Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. + 3 + 1 + read-write + + + B_MV_MERGE_EN + Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. + 4 + 1 + read-write + + + MB_VALID_NUM + Represents the valid mb number of mv merge output. + 5 + 13 + read-only + + + + + DEBUG_DMA_SEL + Debug H264 DMA select register + 0xD8 + 0x20 + + + DBG_DMA_SEL + Every bit represents a dma in h264 + 0 + 8 + read-write + + + + + SYS_STATUS + System status register. + 0xDC + 0x20 + + + FRAME_NUM + Represents current frame number. + 0 + 9 + read-only + + + DUAL_STREAM_SEL + Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. + 9 + 1 + read-only + + + INTRA_FLAG + Represents the type of current encoding frame.\\0: P frame\\1: I frame. + 10 + 1 + read-only + + + + + FRAME_CODE_LENGTH + Frame code byte length register. + 0xE0 + 0x20 + + + FRAME_CODE_LENGTH + Represents current frame code byte length. + 0 + 24 + read-only + + + + + DEBUG_INFO0 + Debug information register0. + 0xE4 + 0x20 + + + TOP_CTRL_INTER_DEBUG_STATE + Represents top_ctrl_inter module FSM info. + 0 + 4 + read-only + + + TOP_CTRL_INTRA_DEBUG_STATE + Represents top_ctrl_intra module FSM info. + 4 + 3 + read-only + + + P_I_CMP_DEBUG_STATE + Represents p_i_cmp module FSM info. + 7 + 3 + read-only + + + MVD_DEBUG_STATE + Represents mvd module FSM info. + 10 + 3 + read-only + + + MC_CHROMA_IP_DEBUG_STATE + Represents mc_chroma_ip module FSM info. + 13 + 1 + read-only + + + INTRA_16X16_CHROMA_CTRL_DEBUG_STATE + Represents intra_16x16_chroma_ctrl module FSM info. + 14 + 4 + read-only + + + INTRA_4X4_CTRL_DEBUG_STATE + Represents intra_4x4_ctrl module FSM info. + 18 + 4 + read-only + + + INTRA_TOP_CTRL_DEBUG_STATE + Represents intra_top_ctrl module FSM info. + 22 + 3 + read-only + + + IME_CTRL_DEBUG_STATE + Represents ime_ctrl module FSM info. + 25 + 3 + read-only + + + + + DEBUG_INFO1 + Debug information register1. + 0xE8 + 0x20 + + + FME_CTRL_DEBUG_STATE + Represents fme_ctrl module FSM info. + 0 + 3 + read-only + + + DECI_CALC_DEBUG_STATE + Represents deci_calc module's FSM info. DEV use only. + 3 + 2 + read-only + + + DB_DEBUG_STATE + Represents db module FSM info. + 5 + 3 + read-only + + + CAVLC_ENC_DEBUG_STATE + Represents cavlc module enc FSM info. + 8 + 4 + read-only + + + CAVLC_SCAN_DEBUG_STATE + Represents cavlc module scan FSM info. + 12 + 4 + read-only + + + CAVLC_CTRL_DEBUG_STATE + Represents cavlc module ctrl FSM info. + 16 + 2 + read-only + + + BS_BUFFER_DEBUG_STATE + Represents bs buffer overflow info. + 18 + 1 + read-only + + + + + DEBUG_INFO2 + Debug information register2. + 0xEC + 0x20 + + + P_RC_DONE_DEBUG_FLAG + Represents p rate ctrl done status.\\0: not done\\1: done. + 0 + 1 + read-only + + + P_P_I_CMP_DONE_DEBUG_FLAG + Represents p p_i_cmp done status.\\0: not done\\1: done. + 1 + 1 + read-only + + + P_MV_MERGE_DONE_DEBUG_FLAG + Represents p mv merge done status.\\0: not done\\1: done. + 2 + 1 + read-only + + + P_MOVE_ORI_DONE_DEBUG_FLAG + Represents p move origin done status.\\0: not done\\1: done. + 3 + 1 + read-only + + + P_MC_DONE_DEBUG_FLAG + Represents p mc done status.\\0: not done\\1: done. + 4 + 1 + read-only + + + P_IME_DONE_DEBUG_FLAG + Represents p ime done status.\\0: not done\\1: done. + 5 + 1 + read-only + + + P_GET_ORI_DONE_DEBUG_FLAG + Represents p get origin done status.\\0: not done\\1: done. + 6 + 1 + read-only + + + P_FME_DONE_DEBUG_FLAG + Represents p fme done status.\\0: not done\\1: done. + 7 + 1 + read-only + + + P_FETCH_DONE_DEBUG_FLAG + Represents p fetch done status.\\0: not done\\1: done. + 8 + 1 + read-only + + + P_DB_DONE_DEBUG_FLAG + Represents p deblocking done status.\\0: not done\\1: done. + 9 + 1 + read-only + + + P_BS_BUF_DONE_DEBUG_FLAG + Represents p bitstream buffer done status.\\0: not done\\1: done. + 10 + 1 + read-only + + + REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG + Represents dma move 2 ref mb line done status.\\0: not done\\1: done. + 11 + 1 + read-only + + + I_P_I_CMP_DONE_DEBUG_FLAG + Represents I p_i_cmp done status.\\0: not done\\1: done. + 12 + 1 + read-only + + + I_MOVE_ORI_DONE_DEBUG_FLAG + Represents I move origin done status.\\0: not done\\1: done. + 13 + 1 + read-only + + + I_GET_ORI_DONE_DEBUG_FLAG + Represents I get origin done status.\\0: not done\\1: done. + 14 + 1 + read-only + + + I_EC_DONE_DEBUG_FLAG + Represents I encoder done status.\\0: not done\\1: done. + 15 + 1 + read-only + + + I_DB_DONE_DEBUG_FLAG + Represents I deblocking done status.\\0: not done\\1: done. + 16 + 1 + read-only + + + I_BS_BUF_DONE_DEBUG_FLAG + Represents I bitstream buffer done status.\\0: not done\\1: done. + 17 + 1 + read-only + + + + + DATE + Version control register + 0xF0 + 0x20 + 0x02304240 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + H264_DMA + H264 Encoder (DMA) + H264_DMA + 0x500A7000 + + 0x0 + 0x3DC + registers + + + H264_DMA2D_OUT_CH0 + 115 + + + H264_DMA2D_OUT_CH1 + 116 + + + H264_DMA2D_OUT_CH2 + 117 + + + H264_DMA2D_OUT_CH3 + 118 + + + H264_DMA2D_OUT_CH4 + 119 + + + H264_DMA2D_IN_CH0 + 120 + + + H264_DMA2D_IN_CH1 + 121 + + + H264_DMA2D_IN_CH2 + 122 + + + H264_DMA2D_IN_CH3 + 123 + + + H264_DMA2D_IN_CH4 + 124 + + + H264_DMA2D_IN_CH5 + 125 + + + + OUT_CONF0_CH0 + TX CH0 config0 register + 0x0 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH0 + Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_REORDER_EN_CH0 + Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection + 16 + 1 + read-write + + + OUT_RST_CH0 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH0 + TX CH0 interrupt raw register + 0x4 + 0x20 + + + OUT_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH0 + TX CH0 interrupt ena register + 0x8 + 0x20 + + + OUT_DONE_CH0_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH0 + TX CH0 interrupt st register + 0xC + 0x20 + + + OUT_DONE_CH0_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH0 + TX CH0 interrupt clr register + 0x10 + 0x20 + + + OUT_DONE_CH0_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH0_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH0_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH0 + TX CH0 outfifo status register + 0x14 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH0 + Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH0 + Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + OUT_PUSH_CH0 + TX CH0 outfifo push register + 0x18 + 0x20 + + + OUTFIFO_WDATA_CH0 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH0 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH0 + TX CH0 out_link dscr ctrl register + 0x1C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH0 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH0 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH0 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH0 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH0 + TX CH0 out_link dscr addr register + 0x20 + 0x20 + + + OUTLINK_ADDR_CH0 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH0 + TX CH0 state register + 0x24 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH0 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH0 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH0 + TX CH0 eof des addr register + 0x28 + 0x20 + + + OUT_EOF_DES_ADDR_CH0 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH0 + TX CH0 next dscr addr register + 0x2C + 0x20 + + + OUTLINK_DSCR_CH0 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH0 + TX CH0 last dscr addr register + 0x30 + 0x20 + + + OUTLINK_DSCR_BF0_CH0 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH0 + TX CH0 second-to-last dscr addr register + 0x34 + 0x20 + + + OUTLINK_DSCR_BF1_CH0 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH0 + TX CH0 arb register + 0x3C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_RO_STATUS_CH0 + TX CH0 reorder status register + 0x40 + 0x20 + 0x00000800 + + + OUTFIFO_RO_CNT_CH0 + The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. + 0 + 2 + read-only + + + OUT_RO_WR_STATE_CH0 + The register stores the state of read ram of reorder + 6 + 2 + read-only + + + OUT_RO_RD_STATE_CH0 + The register stores the state of write ram of reorder + 8 + 2 + read-only + + + OUT_PIXEL_BYTE_CH0 + the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + 10 + 4 + read-only + + + OUT_BURST_BLOCK_NUM_CH0 + the number of macro blocks contained in a burst of data at TX channel + 14 + 4 + read-only + + + + + OUT_RO_PD_CONF_CH0 + TX CH0 reorder power config register + 0x44 + 0x20 + 0x00000020 + + + OUT_RO_RAM_FORCE_PD_CH0 + dma reorder ram power down + 4 + 1 + read-write + + + OUT_RO_RAM_FORCE_PU_CH0 + dma reorder ram power up + 5 + 1 + read-write + + + OUT_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + OUT_MODE_ENABLE_CH0 + tx CH0 mode enable register + 0x50 + 0x20 + + + OUT_TEST_MODE_ENABLE_CH0 + tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode + 0 + 1 + read-write + + + + + OUT_MODE_YUV_CH0 + tx CH0 test mode yuv value register + 0x54 + 0x20 + + + OUT_TEST_Y_VALUE_CH0 + tx CH0 test mode y value + 0 + 8 + read-write + + + OUT_TEST_U_VALUE_CH0 + tx CH0 test mode u value + 8 + 8 + read-write + + + OUT_TEST_V_VALUE_CH0 + tx CH0 test mode v value + 16 + 8 + read-write + + + + + OUT_ETM_CONF_CH0 + TX CH0 ETM config register + 0x68 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH0 + tx CH0 buf len register + 0x70 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH0 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH0 + tx CH0 fifo byte cnt register + 0x74 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH0 + tx CH0 push byte cnt register + 0x78 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH0 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH0 + tx CH0 xaddr register + 0x7C + 0x20 + + + OUT_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH1 + TX CH1 config0 register + 0x100 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH1 + Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH1 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH1 + TX CH1 interrupt raw register + 0x104 + 0x20 + + + OUT_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH1 + TX CH1 interrupt ena register + 0x108 + 0x20 + + + OUT_DONE_CH1_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH1 + TX CH1 interrupt st register + 0x10C + 0x20 + + + OUT_DONE_CH1_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH1 + TX CH1 interrupt clr register + 0x110 + 0x20 + + + OUT_DONE_CH1_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH1_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH1_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH1 + TX CH1 outfifo status register + 0x114 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH1 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH1 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + OUT_PUSH_CH1 + TX CH1 outfifo push register + 0x118 + 0x20 + + + OUTFIFO_WDATA_CH1 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH1 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH1 + TX CH1 out_link dscr ctrl register + 0x11C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH1 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH1 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH1 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH1 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH1 + TX CH1 out_link dscr addr register + 0x120 + 0x20 + + + OUTLINK_ADDR_CH1 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH1 + TX CH1 state register + 0x124 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH1 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH1 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH1 + TX CH1 eof des addr register + 0x128 + 0x20 + + + OUT_EOF_DES_ADDR_CH1 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH1 + TX CH1 next dscr addr register + 0x12C + 0x20 + + + OUTLINK_DSCR_CH1 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH1 + TX CH1 last dscr addr register + 0x130 + 0x20 + + + OUTLINK_DSCR_BF0_CH1 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH1 + TX CH1 second-to-last dscr addr register + 0x134 + 0x20 + + + OUTLINK_DSCR_BF1_CH1 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH1 + TX CH1 arb register + 0x13C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH1 + TX CH1 ETM config register + 0x168 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH1 + tx CH1 buf len register + 0x170 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH1 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH1 + tx CH1 fifo byte cnt register + 0x174 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH1 + tx CH1 push byte cnt register + 0x178 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH1 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH1 + tx CH1 xaddr register + 0x17C + 0x20 + + + OUT_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH2 + TX CH2 config0 register + 0x200 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH2 + Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH2 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH2 + TX CH2 interrupt raw register + 0x204 + 0x20 + + + OUT_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH2 + TX CH2 interrupt ena register + 0x208 + 0x20 + + + OUT_DONE_CH2_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH2 + TX CH2 interrupt st register + 0x20C + 0x20 + + + OUT_DONE_CH2_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH2 + TX CH2 interrupt clr register + 0x210 + 0x20 + + + OUT_DONE_CH2_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH2_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH2_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH2 + TX CH2 outfifo status register + 0x214 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH2 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH2 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH2 + TX CH2 outfifo push register + 0x218 + 0x20 + + + OUTFIFO_WDATA_CH2 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH2 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH2 + TX CH2 out_link dscr ctrl register + 0x21C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH2 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH2 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH2 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH2 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH2 + TX CH2 out_link dscr addr register + 0x220 + 0x20 + + + OUTLINK_ADDR_CH2 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH2 + TX CH2 state register + 0x224 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH2 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH2 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH2 + TX CH2 eof des addr register + 0x228 + 0x20 + + + OUT_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH2 + TX CH2 next dscr addr register + 0x22C + 0x20 + + + OUTLINK_DSCR_CH2 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH2 + TX CH2 last dscr addr register + 0x230 + 0x20 + + + OUTLINK_DSCR_BF0_CH2 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH2 + TX CH2 second-to-last dscr addr register + 0x234 + 0x20 + + + OUTLINK_DSCR_BF1_CH2 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH2 + TX CH2 arb register + 0x23C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH2 + TX CH2 ETM config register + 0x268 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH2 + tx CH2 buf len register + 0x270 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH2 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH2 + tx CH2 fifo byte cnt register + 0x274 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH2 + tx CH2 push byte cnt register + 0x278 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH2 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH2 + tx CH2 xaddr register + 0x27C + 0x20 + + + OUT_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH3 + TX CH3 config0 register + 0x300 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH3 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH3 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH3 + Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH3 + TX CH3 interrupt raw register + 0x304 + 0x20 + + + OUT_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH3 + TX CH3 interrupt ena register + 0x308 + 0x20 + + + OUT_DONE_CH3_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH3 + TX CH3 interrupt st register + 0x30C + 0x20 + + + OUT_DONE_CH3_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH3 + TX CH3 interrupt clr register + 0x310 + 0x20 + + + OUT_DONE_CH3_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH3_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH3_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH3 + TX CH3 outfifo status register + 0x314 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH3 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH3 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH3 + TX CH3 outfifo push register + 0x318 + 0x20 + + + OUTFIFO_WDATA_CH3 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH3 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH3 + TX CH3 out_link dscr ctrl register + 0x31C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH3 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH3 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH3 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH3 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH3 + TX CH3 out_link dscr addr register + 0x320 + 0x20 + + + OUTLINK_ADDR_CH3 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH3 + TX CH3 state register + 0x324 + 0x20 + + + OUTLINK_DSCR_ADDR_CH3 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH3 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH3 + TX CH3 eof des addr register + 0x328 + 0x20 + + + OUT_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH3 + TX CH3 next dscr addr register + 0x32C + 0x20 + + + OUTLINK_DSCR_CH3 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH3 + TX CH3 last dscr addr register + 0x330 + 0x20 + + + OUTLINK_DSCR_BF0_CH3 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH3 + TX CH3 second-to-last dscr addr register + 0x334 + 0x20 + + + OUTLINK_DSCR_BF1_CH3 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH3 + TX CH3 arb register + 0x33C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH3 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH3 + TX CH3 ETM config register + 0x368 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH3 + tx CH3 buf len register + 0x370 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH3 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH3 + tx CH3 fifo byte cnt register + 0x374 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH3 + tx CH3 push byte cnt register + 0x378 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH3 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH3 + tx CH3 xaddr register + 0x37C + 0x20 + + + OUT_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH3 + tx CH3 block buf len register + 0x380 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH3 + only for debug + 0 + 28 + read-only + + + + + OUT_CONF0_CH4 + TX CH4 config0 register + 0x400 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH4 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH4 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH4 + Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH4 + TX CH4 interrupt raw register + 0x404 + 0x20 + + + OUT_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH4 + TX CH4 interrupt ena register + 0x408 + 0x20 + + + OUT_DONE_CH4_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH4 + TX CH4 interrupt st register + 0x40C + 0x20 + + + OUT_DONE_CH4_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH4 + TX CH4 interrupt clr register + 0x410 + 0x20 + + + OUT_DONE_CH4_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH4_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH4_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH4 + TX CH4 outfifo status register + 0x414 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH4 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH4 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH4 + TX CH4 outfifo push register + 0x418 + 0x20 + + + OUTFIFO_WDATA_CH4 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH4 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH4 + TX CH4 out_link dscr ctrl register + 0x41C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH4 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH4 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH4 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH4 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH4 + TX CH4 out_link dscr addr register + 0x420 + 0x20 + + + OUTLINK_ADDR_CH4 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH4 + TX CH4 state register + 0x424 + 0x20 + + + OUTLINK_DSCR_ADDR_CH4 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH4 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH4 + TX CH4 eof des addr register + 0x428 + 0x20 + + + OUT_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH4 + TX CH4 next dscr addr register + 0x42C + 0x20 + + + OUTLINK_DSCR_CH4 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH4 + TX CH4 last dscr addr register + 0x430 + 0x20 + + + OUTLINK_DSCR_BF0_CH4 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH4 + TX CH4 second-to-last dscr addr register + 0x434 + 0x20 + + + OUTLINK_DSCR_BF1_CH4 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH4 + TX CH4 arb register + 0x43C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH4 + TX CH4 ETM config register + 0x468 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH4 + tx CH4 buf len register + 0x470 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH4 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH4 + tx CH4 fifo byte cnt register + 0x474 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH4 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH4 + tx CH4 push byte cnt register + 0x478 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH4 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH4 + tx CH4 xaddr register + 0x47C + 0x20 + + + OUT_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH4 + tx CH4 block buf len register + 0x480 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH4 + only for debug + 0 + 28 + read-only + + + + + IN_CONF0_CH0 + RX CH0 config0 register + 0x500 + 0x20 + + + INDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH0 + Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH0 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH0 + RX CH0 interrupt raw register + 0x504 + 0x20 + + + IN_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH0 + RX CH0 interrupt ena register + 0x508 + 0x20 + + + IN_DONE_CH0_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH0 + RX CH0 interrupt st register + 0x50C + 0x20 + + + IN_DONE_CH0_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH0 + RX CH0 interrupt clr register + 0x510 + 0x20 + + + IN_DONE_CH0_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH0_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH0_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH0_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH0 + RX CH0 INFIFO status register + 0x514 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH0 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH0 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + IN_POP_CH0 + RX CH0 INFIFO pop register + 0x518 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH0 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH0 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH0 + RX CH0 in_link dscr ctrl register + 0x51C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH0 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH0 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH0 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH0 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH0 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH0 + RX CH0 in_link dscr addr register + 0x520 + 0x20 + + + INLINK_ADDR_CH0 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH0 + RX CH0 state register + 0x524 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH0 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH0 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH0 + RX CH0 eof des addr register + 0x528 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH0 + RX CH0 err eof des addr register + 0x52C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH0 + RX CH0 next dscr addr register + 0x530 + 0x20 + + + INLINK_DSCR_CH0 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH0 + RX CH0 last dscr addr register + 0x534 + 0x20 + + + INLINK_DSCR_BF0_CH0 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH0 + RX CH0 second-to-last dscr addr register + 0x538 + 0x20 + + + INLINK_DSCR_BF1_CH0 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH0 + RX CH0 arb register + 0x540 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_RO_PD_CONF_CH0 + RX CH0 reorder power config register + 0x548 + 0x20 + + + IN_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + IN_ETM_CONF_CH0 + RX CH0 ETM config register + 0x56C + 0x20 + 0x00000004 + + + IN_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH0 + rx CH0 fifo cnt register + 0x580 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH0 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH0 + rx CH0 pop data cnt register + 0x584 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH0 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH0 + rx CH0 xaddr register + 0x588 + 0x20 + + + IN_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH0 + rx CH0 buf len hb rcv register + 0x58C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH0 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH1 + RX CH1 config0 register + 0x600 + 0x20 + + + INDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH1 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH1 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH1 + RX CH1 interrupt raw register + 0x604 + 0x20 + + + IN_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH1 + RX CH1 interrupt ena register + 0x608 + 0x20 + + + IN_DONE_CH1_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH1 + RX CH1 interrupt st register + 0x60C + 0x20 + + + IN_DONE_CH1_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH1 + RX CH1 interrupt clr register + 0x610 + 0x20 + + + IN_DONE_CH1_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH1_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH1_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH1_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH1 + RX CH1 INFIFO status register + 0x614 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH1 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH1 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH1 + RX CH1 INFIFO pop register + 0x618 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH1 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH1 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH1 + RX CH1 in_link dscr ctrl register + 0x61C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH1 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH1 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH1 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH1 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH1 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH1 + RX CH1 in_link dscr addr register + 0x620 + 0x20 + + + INLINK_ADDR_CH1 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH1 + RX CH1 state register + 0x624 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH1 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH1 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH1 + RX CH1 eof des addr register + 0x628 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH1 + RX CH1 err eof des addr register + 0x62C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH1 + RX CH1 next dscr addr register + 0x630 + 0x20 + + + INLINK_DSCR_CH1 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH1 + RX CH1 last dscr addr register + 0x634 + 0x20 + + + INLINK_DSCR_BF0_CH1 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH1 + RX CH1 second-to-last dscr addr register + 0x638 + 0x20 + + + INLINK_DSCR_BF1_CH1 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH1 + RX CH1 arb register + 0x640 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH1 + RX CH1 ETM config register + 0x648 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH1 + rx CH1 fifo cnt register + 0x680 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH1 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH1 + rx CH1 pop data cnt register + 0x684 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH1 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH1 + rx CH1 xaddr register + 0x688 + 0x20 + + + IN_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH1 + rx CH1 buf len hb rcv register + 0x68C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH1 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH2 + RX CH2 config0 register + 0x700 + 0x20 + + + INDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH2 + Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH2 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH2 + RX CH2 interrupt raw register + 0x704 + 0x20 + + + IN_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH2 + RX CH2 interrupt ena register + 0x708 + 0x20 + + + IN_DONE_CH2_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH2 + RX CH2 interrupt st register + 0x70C + 0x20 + + + IN_DONE_CH2_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH2 + RX CH2 interrupt clr register + 0x710 + 0x20 + + + IN_DONE_CH2_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH2_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH2_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH2_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH2 + RX CH2 INFIFO status register + 0x714 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH2 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH2 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH2 + RX CH2 INFIFO pop register + 0x718 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH2 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH2 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH2 + RX CH2 in_link dscr ctrl register + 0x71C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH2 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH2 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH2 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH2 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH2 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH2 + RX CH2 in_link dscr addr register + 0x720 + 0x20 + + + INLINK_ADDR_CH2 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH2 + RX CH2 state register + 0x724 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH2 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH2 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH2 + RX CH2 eof des addr register + 0x728 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH2 + RX CH2 err eof des addr register + 0x72C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH2 + RX CH2 next dscr addr register + 0x730 + 0x20 + + + INLINK_DSCR_CH2 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH2 + RX CH2 last dscr addr register + 0x734 + 0x20 + + + INLINK_DSCR_BF0_CH2 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH2 + RX CH2 second-to-last dscr addr register + 0x738 + 0x20 + + + INLINK_DSCR_BF1_CH2 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH2 + RX CH2 arb register + 0x740 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH2 + RX CH2 ETM config register + 0x748 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH2 + rx CH2 fifo cnt register + 0x780 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH2 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH2 + rx CH2 pop data cnt register + 0x784 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH2 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH2 + rx CH2 xaddr register + 0x788 + 0x20 + + + IN_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH2 + rx CH2 buf len hb rcv register + 0x78C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH2 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH3 + RX CH3 config0 register + 0x800 + 0x20 + + + INDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH3 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH3 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH3 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH3 + RX CH3 interrupt raw register + 0x804 + 0x20 + + + IN_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH3 + RX CH3 interrupt ena register + 0x808 + 0x20 + + + IN_DONE_CH3_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH3 + RX CH3 interrupt st register + 0x80C + 0x20 + + + IN_DONE_CH3_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH3 + RX CH3 interrupt clr register + 0x810 + 0x20 + + + IN_DONE_CH3_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH3_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH3_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH3_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH3 + RX CH3 INFIFO status register + 0x814 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH3 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH3 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH3 + RX CH3 INFIFO pop register + 0x818 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH3 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH3 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH3 + RX CH3 in_link dscr ctrl register + 0x81C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH3 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH3 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH3 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH3 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH3 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH3 + RX CH3 in_link dscr addr register + 0x820 + 0x20 + + + INLINK_ADDR_CH3 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH3 + RX CH3 state register + 0x824 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH3 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH3 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH3 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH3 + RX CH3 eof des addr register + 0x828 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH3 + RX CH3 err eof des addr register + 0x82C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH3 + RX CH3 next dscr addr register + 0x830 + 0x20 + + + INLINK_DSCR_CH3 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH3 + RX CH3 last dscr addr register + 0x834 + 0x20 + + + INLINK_DSCR_BF0_CH3 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH3 + RX CH3 second-to-last dscr addr register + 0x838 + 0x20 + + + INLINK_DSCR_BF1_CH3 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH3 + RX CH3 arb register + 0x840 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH3 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH3 + RX CH3 ETM config register + 0x848 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH3 + rx CH3 fifo cnt register + 0x880 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH3 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH3 + rx CH3 pop data cnt register + 0x884 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH3 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH3 + rx CH3 xaddr register + 0x888 + 0x20 + + + IN_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH3 + rx CH3 buf len hb rcv register + 0x88C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH3 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH4 + RX CH4 config0 register + 0x900 + 0x20 + + + INDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH4 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH4 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH4 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH4 + RX CH4 interrupt raw register + 0x904 + 0x20 + + + IN_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH4 + RX CH4 interrupt ena register + 0x908 + 0x20 + + + IN_DONE_CH4_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH4 + RX CH4 interrupt st register + 0x90C + 0x20 + + + IN_DONE_CH4_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH4 + RX CH4 interrupt clr register + 0x910 + 0x20 + + + IN_DONE_CH4_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH4_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH4_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH4_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH4 + RX CH4 INFIFO status register + 0x914 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH4 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH4 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH4 + RX CH4 INFIFO pop register + 0x918 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH4 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH4 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH4 + RX CH4 in_link dscr ctrl register + 0x91C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH4 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH4 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH4 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH4 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH4 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH4 + RX CH4 in_link dscr addr register + 0x920 + 0x20 + + + INLINK_ADDR_CH4 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH4 + RX CH4 state register + 0x924 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH4 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH4 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH4 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH4 + RX CH4 eof des addr register + 0x928 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH4 + RX CH4 err eof des addr register + 0x92C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH4 + RX CH4 next dscr addr register + 0x930 + 0x20 + + + INLINK_DSCR_CH4 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH4 + RX CH4 last dscr addr register + 0x934 + 0x20 + + + INLINK_DSCR_BF0_CH4 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH4 + RX CH4 second-to-last dscr addr register + 0x938 + 0x20 + + + INLINK_DSCR_BF1_CH4 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH4 + RX CH4 arb register + 0x940 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH4 + RX CH4 ETM config register + 0x948 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH4 + rx CH4 fifo cnt register + 0x980 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH4 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH4 + rx CH4 pop data cnt register + 0x984 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH4 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH4 + rx CH4 xaddr register + 0x988 + 0x20 + + + IN_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH4 + rx CH4 buf len hb rcv register + 0x98C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH4 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH5 + RX CH5 config0 register + 0xA00 + 0x20 + + + IN_ECC_AES_EN_CH5 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH5 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH5 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH5 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH5 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + + + IN_CONF1_CH5 + RX CH5 config1 register + 0xA04 + 0x20 + + + BLOCK_START_ADDR_CH5 + RX Channel 5 destination start address + 0 + 32 + read-write + + + + + IN_CONF2_CH5 + RX CH5 config2 register + 0xA08 + 0x20 + 0x3C007800 + + + BLOCK_ROW_LENGTH_12LINE_CH5 + The number of bytes contained in a row block 12line in RX channel 5 + 0 + 16 + read-write + + + BLOCK_ROW_LENGTH_4LINE_CH5 + The number of bytes contained in a row block 4line in RX channel 5 + 16 + 16 + read-write + + + + + IN_CONF3_CH5 + RX CH5 config3 register + 0xA0C + 0x20 + 0x00200100 + + + BLOCK_LENGTH_12LINE_CH5 + The number of bytes contained in a block 12line + 0 + 14 + read-write + + + BLOCK_LENGTH_4LINE_CH5 + The number of bytes contained in a block 4line + 14 + 14 + read-write + + + + + IN_INT_RAW_CH5 + RX CH5 interrupt raw register + 0xA10 + 0x20 + + + IN_DONE_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 4 + 1 + read-write + + + + + IN_INT_ENA_CH5 + RX CH5 interrupt ena register + 0xA14 + 0x20 + + + IN_DONE_CH5_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + + + IN_INT_ST_CH5 + RX CH5 interrupt st register + 0xA18 + 0x20 + + + IN_DONE_CH5_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH5_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + INFIFO_OVF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-only + + + INFIFO_UDF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + + + IN_INT_CLR_CH5 + RX CH5 interrupt clr register + 0xA1C + 0x20 + + + IN_DONE_CH5_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH5_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + INFIFO_OVF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + write-only + + + INFIFO_UDF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + write-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + + + INFIFO_STATUS_CH5 + RX CH5 INFIFO status register + 0xA20 + 0x20 + 0x00000002 + + + INFIFO_FULL_L1_CH5 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1_CH5 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + INFIFO_CNT_L1_CH5 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 5 + read-only + + + + + IN_POP_CH5 + RX CH5 INFIFO pop register + 0xA24 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH5 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH5 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_STATE_CH5 + RX CH5 state register + 0xA28 + 0x20 + 0x00000008 + + + IN_STATE_CH5 + This register stores the current control module state machine state. + 0 + 3 + read-only + + + IN_RESET_AVAIL_CH5 + This register indicate that if the channel reset is safety. + 3 + 1 + read-only + + + + + IN_ARB_CH5 + RX CH5 arb register + 0xA40 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH5 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH5 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_FIFO_CNT_CH5 + rx CH5 fifo cnt register + 0xA80 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH5 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH5 + rx CH5 pop data cnt register + 0xA84 + 0x20 + 0x000000FF + + + IN_CMDFIFO_POP_DATA_CNT_CH5 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH5 + rx CH5 xaddr register + 0xA88 + 0x20 + + + IN_CMDFIFO_XADDR_CH5 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH5 + rx CH5 buf len hb rcv register + 0xA8C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH5 + only for debug + 0 + 29 + read-only + + + + + INTER_AXI_ERR + inter memory axi err register + 0xB00 + 0x20 + + + INTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + INTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + INTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + INTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + INTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + INTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + INTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + EXTER_AXI_ERR + exter memory axi err register + 0xB04 + 0x20 + + + EXTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + EXTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + EXTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + EXTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + EXTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + EXTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + EXTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + RST_CONF + axi reset config register + 0xB08 + 0x20 + + + INTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 0 + 1 + read-write + + + INTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 1 + 1 + read-write + + + EXTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 2 + 1 + read-write + + + EXTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + INTER_MEM_START_ADDR0 + Start address of inter memory range0 register + 0xB0C + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR0 + end address of inter memory range0 register + 0xB10 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + INTER_MEM_START_ADDR1 + Start address of inter memory range1 register + 0xB14 + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR1 + end address of inter memory range1 register + 0xB18 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR0 + Start address of exter memory range0 register + 0xB20 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR0 + end address of exter memory range0 register + 0xB24 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR1 + Start address of exter memory range1 register + 0xB28 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR1 + end address of exter memory range1 register + 0xB2C + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + OUT_ARB_CONFIG + reserved + 0xB30 + 0x20 + + + OUT_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + OUT_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + IN_ARB_CONFIG + reserved + 0xB34 + 0x20 + + + IN_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + IN_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + DATE + reserved + 0xB3C + 0x20 + 0x20230403 + + + DATE + register version. + 0 + 32 + read-write + + + + + COUNTER_RST + counter reset register + 0xB50 + 0x20 + + + RX_CH0_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch0 counter. + 0 + 1 + read-write + + + RX_CH1_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch1 counter. + 1 + 1 + read-write + + + RX_CH2_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch2 counter. + 2 + 1 + read-write + + + RX_CH5_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch5 counter. + 3 + 1 + read-write + + + + + RX_CH0_COUNTER + rx ch0 counter register + 0xB54 + 0x20 + + + RX_CH0_CNT + rx ch0 counter register + 0 + 23 + read-only + + + + + RX_CH1_COUNTER + rx ch1 counter register + 0xB58 + 0x20 + + + RX_CH1_CNT + rx ch1 counter register + 0 + 21 + read-only + + + + + RX_CH2_COUNTER + rx ch2 counter register + 0xB5C + 0x20 + + + RX_CH2_CNT + rx ch2 counter register + 0 + 11 + read-only + + + + + RX_CH5_COUNTER + rx ch5 counter register + 0xB60 + 0x20 + + + RX_CH5_CNT + rx ch5 counter register + 0 + 17 + read-only + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x50095000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 16 + 0x4 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x20 + + + 8 + 0x4 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x20 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + HP_SYS + High-Power System + HP_SYS + 0x500E5000 + + 0x0 + 0x16C + registers + + + HP_SYS + 110 + + + + VER_DATE + NA + 0x0 + 0x20 + 0x20230519 + + + REG_VER_DATE + NA + 0 + 32 + read-write + + + + + CLK_EN + NA + 0x4 + 0x20 + + + REG_CLK_EN + NA + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + NA + 0x10 + 0x20 + + + CPU_INTR_FROM_CPU_0 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + NA + 0x14 + 0x20 + + + CPU_INTR_FROM_CPU_1 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + NA + 0x18 + 0x20 + + + CPU_INTR_FROM_CPU_2 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + NA + 0x1C + 0x20 + + + CPU_INTR_FROM_CPU_3 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CACHE_CLK_CONFIG + NA + 0x20 + 0x20 + 0x00000033 + + + REG_L2_CACHE_CLK_ON + l2 cahce clk enable + 0 + 1 + read-write + + + REG_L1_D_CACHE_CLK_ON + l1 dcahce clk enable + 1 + 1 + read-write + + + REG_L1_I1_CACHE_CLK_ON + l1 icahce1 clk enable + 4 + 1 + read-write + + + REG_L1_I0_CACHE_CLK_ON + l1 icahce0 clk enable + 5 + 1 + read-write + + + + + CACHE_RESET_CONFIG + NA + 0x24 + 0x20 + + + REG_L1_D_CACHE_RESET + set 1 to reset l1 dcahce + 1 + 1 + read-write + + + REG_L1_I1_CACHE_RESET + set 1 to reset l1 icahce1 + 4 + 1 + read-write + + + REG_L1_I0_CACHE_RESET + set 1 to reset l1 icahce0 + 5 + 1 + read-write + + + + + DMA_ADDR_CTRL + NA + 0x2C + 0x20 + + + REG_SYS_DMA_ADDR_SEL + 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx + 0 + 1 + read-write + + + + + TCM_RAM_WRR_CONFIG + NA + 0x34 + 0x20 + 0x826ED93F + + + REG_TCM_RAM_IBUS0_WT + weight value of ibus0 + 0 + 3 + read-write + + + REG_TCM_RAM_IBUS1_WT + weight value of ibus1 + 3 + 3 + read-write + + + REG_TCM_RAM_IBUS2_WT + weight value of ibus2 + 6 + 3 + read-write + + + REG_TCM_RAM_IBUS3_WT + weight value of ibus3 + 9 + 3 + read-write + + + REG_TCM_RAM_DBUS0_WT + weight value of dbus0 + 12 + 3 + read-write + + + REG_TCM_RAM_DBUS1_WT + weight value of dbus1 + 15 + 3 + read-write + + + REG_TCM_RAM_DBUS2_WT + weight value of dbus2 + 18 + 3 + read-write + + + REG_TCM_RAM_DBUS3_WT + weight value of dbus3 + 21 + 3 + read-write + + + REG_TCM_RAM_DMA_WT + weight value of dma + 24 + 3 + read-write + + + REG_TCM_RAM_WRR_HIGH + enable weighted round robin arbitration + 31 + 1 + read-write + + + + + TCM_SW_PARITY_BWE_MASK + NA + 0x38 + 0x20 + + + REG_TCM_SW_PARITY_BWE_MASK_CTRL + Set 1 to mask tcm bwe parity code bit + 0 + 1 + read-write + + + + + TCM_RAM_PWR_CTRL0 + NA + 0x3C + 0x20 + + + REG_HP_TCM_CLK_FORCE_ON + hp_tcm clk gatig force on + 0 + 1 + read-write + + + + + L2_ROM_PWR_CTRL0 + NA + 0x40 + 0x20 + + + REG_L2_ROM_CLK_FORCE_ON + l2_rom clk gating force on + 0 + 1 + read-write + + + + + PROBEA_CTRL + NA + 0x50 + 0x20 + + + REG_PROBE_A_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode + 0 + 16 + read-write + + + REG_PROBE_A_TOP_SEL + Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + 16 + 8 + read-write + + + REG_PROBE_L_SEL + Tihs field is used to selec probe_out[31:16] + 24 + 2 + read-write + + + REG_PROBE_H_SEL + Tihs field is used to selec probe_out[31:16] + 26 + 2 + read-write + + + REG_PROBE_GLOBAL_EN + Set this bit to enable global debug probe in hp system. + 28 + 1 + read-write + + + + + PROBEB_CTRL + NA + 0x54 + 0x20 + + + REG_PROBE_B_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. + 0 + 16 + read-write + + + REG_PROBE_B_TOP_SEL + Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + 16 + 8 + read-write + + + REG_PROBE_B_EN + Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. + 24 + 1 + read-write + + + + + PROBE_OUT + NA + 0x5C + 0x20 + + + REG_PROBE_TOP_OUT + NA + 0 + 32 + read-only + + + + + L2_MEM_RAM_PWR_CTRL0 + NA + 0x60 + 0x20 + + + REG_L2_MEM_CLK_FORCE_ON + l2ram clk_gating force on + 0 + 1 + read-write + + + + + CPU_CORESTALLED_ST + NA + 0x64 + 0x20 + + + REG_CORE0_CORESTALLED_ST + hp core0 corestalled status + 0 + 1 + read-only + + + REG_CORE1_CORESTALLED_ST + hp core1 corestalled status + 1 + 1 + read-only + + + + + CRYPTO_CTRL + NA + 0x70 + 0x20 + + + REG_ENABLE_SPI_MANUAL_ENCRYPT + NA + 0 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_DB_ENCRYPT + NA + 1 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_G0CB_DECRYPT + NA + 2 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT + NA + 3 + 1 + read-write + + + + + GPIO_O_HOLD_CTRL0 + NA + 0x74 + 0x20 + + + REG_GPIO_0_HOLD_LOW + hold control for gpio47~16 + 0 + 32 + read-write + + + + + GPIO_O_HOLD_CTRL1 + NA + 0x78 + 0x20 + + + REG_GPIO_0_HOLD_HIGH + hold control for gpio56~48 + 0 + 9 + read-write + + + + + RDN_ECO_CS + NA + 0x7C + 0x20 + + + REG_HP_SYS_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_HP_SYS_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + CACHE_APB_POSTW_EN + NA + 0x80 + 0x20 + + + REG_CACHE_APB_POSTW_EN + cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + L2_MEM_SUBSIZE + NA + 0x84 + 0x20 + + + REG_L2_MEM_SUB_BLKSIZE + l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + 0 + 2 + read-write + + + + + L2_MEM_INT_RAW + NA + 0x9C + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_RAW + intr triggered when two bit error detected and corrected from ecc + 0 + 1 + read-write + + + REG_L2_MEM_EXCEED_ADDR_INT_RAW + intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode + 1 + 1 + read-write + + + REG_L2_MEM_ERR_RESP_INT_RAW + intr triggered when err response occurs + 2 + 1 + read-write + + + + + L2_MEM_INT_ST + NA + 0xA0 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ST + NA + 0 + 1 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_ST + NA + 1 + 1 + read-only + + + REG_L2_MEM_ERR_RESP_INT_ST + NA + 2 + 1 + read-only + + + + + L2_MEM_INT_ENA + NA + 0xA4 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ENA + NA + 0 + 1 + read-write + + + REG_L2_MEM_EXCEED_ADDR_INT_ENA + NA + 1 + 1 + read-write + + + REG_L2_MEM_ERR_RESP_INT_ENA + NA + 2 + 1 + read-write + + + + + L2_MEM_INT_CLR + NA + 0xA8 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_CLR + NA + 0 + 1 + write-only + + + REG_L2_MEM_EXCEED_ADDR_INT_CLR + NA + 1 + 1 + write-only + + + REG_L2_MEM_ERR_RESP_INT_CLR + NA + 2 + 1 + write-only + + + + + L2_MEM_L2_RAM_ECC + NA + 0xAC + 0x20 + + + REG_L2_RAM_UNIT0_ECC_EN + NA + 0 + 1 + read-write + + + REG_L2_RAM_UNIT1_ECC_EN + NA + 1 + 1 + read-write + + + REG_L2_RAM_UNIT2_ECC_EN + NA + 2 + 1 + read-write + + + REG_L2_RAM_UNIT3_ECC_EN + NA + 3 + 1 + read-write + + + REG_L2_RAM_UNIT4_ECC_EN + NA + 4 + 1 + read-write + + + REG_L2_RAM_UNIT5_ECC_EN + NA + 5 + 1 + read-write + + + + + L2_MEM_INT_RECORD0 + NA + 0xB0 + 0x20 + + + REG_L2_MEM_EXCEED_ADDR_INT_ADDR + NA + 0 + 21 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_WE + NA + 21 + 1 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_MASTER + NA + 22 + 3 + read-only + + + + + L2_MEM_INT_RECORD1 + NA + 0xB4 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ADDR + NA + 0 + 15 + read-only + + + REG_L2_MEM_ECC_ONE_BIT_ERR + NA + 15 + 1 + read-only + + + REG_L2_MEM_ECC_TWO_BIT_ERR + NA + 16 + 1 + read-only + + + REG_L2_MEM_ECC_ERR_BIT + NA + 17 + 9 + read-only + + + REG_L2_CACHE_ERR_BANK + NA + 26 + 1 + read-only + + + + + L2_MEM_L2_CACHE_ECC + NA + 0xC4 + 0x20 + + + REG_L2_CACHE_ECC_EN + NA + 0 + 1 + read-write + + + + + L1CACHE_BUS0_ID + NA + 0xC8 + 0x20 + + + REG_L1_CACHE_BUS0_ID + NA + 0 + 4 + read-write + + + + + L1CACHE_BUS1_ID + NA + 0xCC + 0x20 + + + REG_L1_CACHE_BUS1_ID + NA + 0 + 4 + read-write + + + + + L2_MEM_RDN_ECO_CS + NA + 0xD8 + 0x20 + + + REG_L2_MEM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_L2_MEM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + L2_MEM_RDN_ECO_LOW + NA + 0xDC + 0x20 + + + REG_L2_MEM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + L2_MEM_RDN_ECO_HIGH + NA + 0xE0 + 0x20 + 0xFFFFFFFF + + + REG_L2_MEM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + TCM_RDN_ECO_CS + NA + 0xE4 + 0x20 + + + REG_HP_TCM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_HP_TCM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + TCM_RDN_ECO_LOW + NA + 0xE8 + 0x20 + + + REG_HP_TCM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + TCM_RDN_ECO_HIGH + NA + 0xEC + 0x20 + 0xFFFFFFFF + + + REG_HP_TCM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + GPIO_DED_HOLD_CTRL + NA + 0xF0 + 0x20 + + + REG_GPIO_DED_HOLD + hold control for gpio63~56 + 0 + 26 + read-write + + + + + L2_MEM_SW_ECC_BWE_MASK + NA + 0xF4 + 0x20 + + + REG_L2_MEM_SW_ECC_BWE_MASK_CTRL + Set 1 to mask bwe hamming code bit + 0 + 1 + read-write + + + + + USB20OTG_MEM_CTRL + NA + 0xF8 + 0x20 + + + REG_USB20_MEM_CLK_FORCE_ON + NA + 0 + 1 + read-write + + + + + TCM_INT_RAW + need_des + 0xFC + 0x20 + + + TCM_PARITY_ERR_INT_RAW + need_des + 31 + 1 + read-write + + + + + TCM_INT_ST + need_des + 0x100 + 0x20 + + + TCM_PARITY_ERR_INT_ST + need_des + 31 + 1 + read-only + + + + + TCM_INT_ENA + need_des + 0x104 + 0x20 + + + TCM_PARITY_ERR_INT_ENA + need_des + 31 + 1 + read-write + + + + + TCM_INT_CLR + need_des + 0x108 + 0x20 + + + TCM_PARITY_ERR_INT_CLR + need_des + 31 + 1 + write-only + + + + + TCM_PARITY_INT_RECORD + need_des + 0x10C + 0x20 + + + TCM_PARITY_ERR_INT_ADDR + hp tcm_parity_err_addr + 0 + 13 + read-only + + + + + L1_CACHE_PWR_CTRL + NA + 0x110 + 0x20 + + + REG_L1_CACHE_MEM_FO + need_des + 0 + 6 + read-write + + + + + L2_CACHE_PWR_CTRL + NA + 0x114 + 0x20 + + + REG_L2_CACHE_MEM_FO + need_des + 0 + 2 + read-write + + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x118 + 0x20 + 0x00000001 + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 0 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 1 + 4 + read-write + + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x11C + 0x20 + + + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 + 1 + read-write + + + + + CORE_AHB_TIMEOUT + need_des + 0x120 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ahb bus timeout threshold + 1 + 16 + read-write + + + + + CORE_IBUS_TIMEOUT + need_des + 0x124 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ibus timeout threshold + 1 + 16 + read-write + + + + + CORE_DBUS_TIMEOUT + need_des + 0x128 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 dbus timeout threshold + 1 + 16 + read-write + + + + + ICM_CPU_H2X_CFG + need_des + 0x138 + 0x20 + 0x00000003 + + + CPU_ICM_H2X_POST_WR_EN + need_des + 0 + 1 + read-write + + + CPU_ICM_H2X_CUT_THROUGH_EN + need_des + 1 + 1 + read-write + + + CPU_ICM_H2X_BRIDGE_BUSY + need_des + 2 + 1 + read-only + + + + + PERI1_APB_POSTW_EN + NA + 0x13C + 0x20 + + + PERI1_APB_POSTW_EN + hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + BITSCRAMBLER_PERI_SEL + Bitscrambler Peri Sel + 0x140 + 0x20 + 0x000000FF + + + BITSCRAMBLER_PERI_RX_SEL + Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 0 + 4 + read-write + + + BITSCRAMBLER_PERI_TX_SEL + Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 4 + 4 + read-write + + + + + APB_SYNC_POSTW_EN + N/A + 0x144 + 0x20 + + + GMAC_APB_POSTW_EN + N/A + 0 + 1 + read-write + + + DSI_HOST_APB_POSTW_EN + N/A + 1 + 1 + read-write + + + CSI_HOST_APB_SYNC_POSTW_EN + N/A + 2 + 1 + read-write + + + CSI_HOST_APB_ASYNC_POSTW_EN + N/A + 3 + 1 + read-write + + + + + GDMA_CTRL + N/A + 0x148 + 0x20 + + + DEBUG_CH_NUM + N/A + 0 + 2 + read-write + + + + + GMAC_CTRL0 + N/A + 0x14C + 0x20 + + + PTP_PPS + N/A + 0 + 1 + read-only + + + SBD_FLOWCTRL + N/A + 1 + 1 + read-write + + + PHY_INTF_SEL + N/A + 2 + 3 + read-write + + + GMAC_MEM_CLK_FORCE_ON + N/A + 5 + 1 + read-write + + + GMAC_RST_CLK_TX_N + N/A + 6 + 1 + read-only + + + GMAC_RST_CLK_RX_N + N/A + 7 + 1 + read-only + + + + + GMAC_CTRL1 + N/A + 0x150 + 0x20 + + + PTP_TIMESTAMP_L + N/A + 0 + 32 + read-only + + + + + GMAC_CTRL2 + N/A + 0x154 + 0x20 + + + PTP_TIMESTAMP_H + N/A + 0 + 32 + read-only + + + + + VPU_CTRL + N/A + 0x158 + 0x20 + + + PPA_LSLP_MEM_PD + N/A + 0 + 1 + read-write + + + JPEG_SDSLP_MEM_PD + N/A + 1 + 1 + read-write + + + JPEG_LSLP_MEM_PD + N/A + 2 + 1 + read-write + + + JPEG_DSLP_MEM_PD + N/A + 3 + 1 + read-write + + + DMA2D_LSLP_MEM_PD + N/A + 4 + 1 + read-write + + + + + USBOTG20_CTRL + N/A + 0x15C + 0x20 + 0x00822640 + + + OTG_PHY_TEST_DONE + N/A + 0 + 1 + read-only + + + USB_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + PHY_SUSPENDM + N/A + 15 + 1 + read-write + + + PHY_SUSPEND_FORCE_EN + N/A + 16 + 1 + read-write + + + PHY_RSTN + N/A + 17 + 1 + read-write + + + PHY_RESET_FORCE_EN + N/A + 18 + 1 + read-write + + + PHY_PLL_FORCE_EN + N/A + 19 + 1 + read-write + + + PHY_PLL_EN + N/A + 20 + 1 + read-write + + + OTG_SUSPENDM + N/A + 21 + 1 + read-write + + + OTG_PHY_TXBITSTUFF_EN + N/A + 22 + 1 + read-write + + + OTG_PHY_REFCLK_MODE + N/A + 23 + 1 + read-write + + + OTG_PHY_BISTEN + N/A + 24 + 1 + read-write + + + + + TCM_ERR_RESP_CTRL + need_des + 0x160 + 0x20 + + + TCM_ERR_RESP_EN + Set 1 to turn on tcm error response + 0 + 1 + read-write + + + + + L2_MEM_REFRESH + NA + 0x164 + 0x20 + 0x00000040 + + + REG_L2_MEM_UNIT0_REFERSH_EN + NA + 0 + 1 + read-write + + + REG_L2_MEM_UNIT1_REFERSH_EN + NA + 1 + 1 + read-write + + + REG_L2_MEM_UNIT2_REFERSH_EN + NA + 2 + 1 + read-write + + + REG_L2_MEM_UNIT3_REFERSH_EN + NA + 3 + 1 + read-write + + + REG_L2_MEM_UNIT4_REFERSH_EN + NA + 4 + 1 + read-write + + + REG_L2_MEM_UNIT5_REFERSH_EN + NA + 5 + 1 + read-write + + + REG_L2_MEM_REFERSH_CNT_RESET + Set 1 to reset l2mem_refresh_cnt + 6 + 1 + read-write + + + REG_L2_MEM_UNIT0_REFRESH_DONE + NA + 7 + 1 + read-only + + + REG_L2_MEM_UNIT1_REFRESH_DONE + NA + 8 + 1 + read-only + + + REG_L2_MEM_UNIT2_REFRESH_DONE + NA + 9 + 1 + read-only + + + REG_L2_MEM_UNIT3_REFRESH_DONE + NA + 10 + 1 + read-only + + + REG_L2_MEM_UNIT4_REFRESH_DONE + NA + 11 + 1 + read-only + + + REG_L2_MEM_UNIT5_REFRESH_DONE + NA + 12 + 1 + read-only + + + + + TCM_INIT + NA + 0x168 + 0x20 + 0x00000002 + + + REG_TCM_INIT_EN + NA + 0 + 1 + read-write + + + REG_TCM_INIT_CNT_RESET + Set 1 to reset tcm init cnt + 1 + 1 + read-write + + + REG_TCM_INIT_DONE + NA + 2 + 1 + read-only + + + + + TCM_PARITY_CHECK_CTRL + need_des + 0x16C + 0x20 + + + TCM_PARITY_CHECK_EN + Set 1 to turn on tcm parity check + 0 + 1 + read-write + + + + + DESIGN_FOR_VERIFICATION0 + need_des + 0x170 + 0x20 + + + DFV0 + register for DV + 0 + 32 + read-write + + + + + DESIGN_FOR_VERIFICATION1 + need_des + 0x174 + 0x20 + + + DFV1 + register for DV + 0 + 32 + read-write + + + + + PSRAM_FLASH_ADDR_INTERCHANGE + need_des + 0x180 + 0x20 + + + CPU + Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache + 0 + 1 + read-write + + + DMA + Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb + 1 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_RAW + NA + 0x188 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_RAW + the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. + 0 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_ST + need_des + 0x18C + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_ST + the masked interrupt status of cpu_icm_h2x_bresp_err + 31 + 1 + read-only + + + + + AHB2AXI_BRESP_ERR_INT_ENA + need_des + 0x190 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_ENA + Write 1 to enable cpu_icm_h2x_bresp_err int + 31 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_CLR + need_des + 0x194 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_CLR + Write 1 to clear cpu_icm_h2x_bresp_err int + 31 + 1 + write-only + + + + + L2_MEM_ERR_RESP_CTRL + need_des + 0x198 + 0x20 + + + L2_MEM_ERR_RESP_EN + Set 1 to turn on l2mem error response + 0 + 1 + read-write + + + + + L2_MEM_AHB_BUFFER_CTRL + need_des + 0x19C + 0x20 + + + L2_MEM_AHB_WRBUFFER_EN + Set 1 to turn on l2mem ahb wr buffer + 0 + 1 + read-write + + + L2_MEM_AHB_RDBUFFER_EN + Set 1 to turn on l2mem ahb rd buffer + 1 + 1 + read-write + + + + + CORE_DMACTIVE_LPCORE + need_des + 0x1A0 + 0x20 + + + CORE_DMACTIVE_LPCORE + hp core dmactive_lpcore value + 0 + 1 + read-only + + + + + CORE_ERR_RESP_DIS + need_des + 0x1A4 + 0x20 + + + CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + CORE_TIMEOUT_INT_RAW + Hp core bus timeout interrupt raw register + 0x1A8 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ahb timeout + 0 + 1 + read-write + + + CORE1_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ahb timeout + 1 + 1 + read-write + + + CORE0_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ibus timeout + 2 + 1 + read-write + + + CORE1_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ibus timeout + 3 + 1 + read-write + + + CORE0_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 dbus timeout + 4 + 1 + read-write + + + CORE1_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 dbus timeout + 5 + 1 + read-write + + + + + CORE_TIMEOUT_INT_ST + masked interrupt register + 0x1AC + 0x20 + + + CORE0_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ahb timeout + 0 + 1 + read-only + + + CORE1_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ahb timeout + 1 + 1 + read-only + + + CORE0_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ibus timeout + 2 + 1 + read-only + + + CORE1_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ibus timeout + 3 + 1 + read-only + + + CORE0_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 dbus timeout + 4 + 1 + read-only + + + CORE1_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 dbus timeout + 5 + 1 + read-only + + + + + CORE_TIMEOUT_INT_ENA + masked interrupt register + 0x1B0 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ahb_timeout int + 0 + 1 + read-write + + + CORE1_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ahb_timeout int + 1 + 1 + read-write + + + CORE0_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ibus_timeout int + 2 + 1 + read-write + + + CORE1_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ibus_timeout int + 3 + 1 + read-write + + + CORE0_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_dbus_timeout int + 4 + 1 + read-write + + + CORE1_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_dbus_timeout int + 5 + 1 + read-write + + + + + CORE_TIMEOUT_INT_CLR + interrupt clear register + 0x1B4 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ahb_timeout int + 0 + 1 + write-only + + + CORE1_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ahb_timeout int + 1 + 1 + write-only + + + CORE0_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ibus_timeout int + 2 + 1 + write-only + + + CORE1_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ibus_timeout int + 3 + 1 + write-only + + + CORE0_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_dbus_timeout int + 4 + 1 + write-only + + + CORE1_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_dbus_timeout int + 5 + 1 + write-only + + + + + GPIO_O_HYS_CTRL0 + NA + 0x1C0 + 0x20 + + + REG_GPIO_0_HYS_LOW + hys control for gpio47~16 + 0 + 32 + read-write + + + + + GPIO_O_HYS_CTRL1 + NA + 0x1C4 + 0x20 + + + REG_GPIO_0_HYS_HIGH + hys control for gpio56~48 + 0 + 9 + read-write + + + + + RSA_PD_CTRL + rsa pd ctrl register + 0x1D0 + 0x20 + 0x00000002 + + + RSA_MEM_FORCE_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + RSA_MEM_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + ECC_PD_CTRL + ecc pd ctrl register + 0x1D4 + 0x20 + 0x00000002 + + + ECC_MEM_FORCE_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + ECC_MEM_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + RNG_CFG + rng cfg register + 0x1D8 + 0x20 + + + RNG_SAMPLE_ENABLE + enable rng sample chain + 0 + 1 + read-write + + + RNG_CHAIN_CLK_DIV_NUM + chain clk div num to pad for debug + 16 + 8 + read-write + + + RNG_SAMPLE_CNT + debug rng sample cnt + 24 + 8 + read-only + + + + + UART_PD_CTRL + ecc pd ctrl register + 0x1DC + 0x20 + 0x00000002 + + + UART_MEM_FORCE_PD + Set this bit to power down hp uart internal memory. + 0 + 1 + read-write + + + UART_MEM_FORCE_PU + Set this bit to force power up hp uart internal memory + 1 + 1 + read-write + + + + + PERI_MEM_CLK_FORCE_ON + hp peri mem clk force on regpster + 0x1E0 + 0x20 + + + RMT_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in rmt + 0 + 1 + read-write + + + BITSCRAMBLER_TX_MEM_CLK_FORCE_ON + Set this bit to force on tx mem clk in bitscrambler + 1 + 1 + read-write + + + BITSCRAMBLER_RX_MEM_CLK_FORCE_ON + Set this bit to force on rx mem clk in bitscrambler + 2 + 1 + read-write + + + GDMA_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in gdma + 3 + 1 + read-write + + + + + + + HP_SYS_CLKRST + HP_SYS_CLKRST Peripheral + HP_SYS_CLKRST + 0x500E6000 + + 0x0 + 0xF0 + registers + + + + CLK_EN0 + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + ROOT_CLK_CTRL0 + Reserved + 0x4 + 0x20 + + + REG_CPUICM_DELAY_NUM + Reserved + 0 + 4 + read-write + + + REG_SOC_CLK_DIV_UPDATE + Reserved + 4 + 1 + write-only + + + REG_CPU_CLK_DIV_NUM + Reserved + 5 + 8 + read-write + + + REG_CPU_CLK_DIV_NUMERATOR + Reserved + 13 + 8 + read-write + + + REG_CPU_CLK_DIV_DENOMINATOR + Reserved + 21 + 8 + read-write + + + + + ROOT_CLK_CTRL1 + Reserved + 0x8 + 0x20 + 0x00000001 + + + REG_MEM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_MEM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_MEM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_SYS_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL2 + Reserved + 0xC + 0x20 + 0x00010000 + + + REG_SYS_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_SYS_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_APB_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_APB_CLK_DIV_NUMERATOR + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL3 + Reserved + 0x10 + 0x20 + + + REG_APB_CLK_DIV_DENOMINATOR + Reserved + 0 + 8 + read-write + + + + + SOC_CLK_CTRL0 + Reserved + 0x14 + 0x20 + 0xE6DF97AF + + + REG_CORE0_CLIC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_CORE1_CLIC_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_MISC_CPU_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_CORE0_CPU_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_CORE1_CPU_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TCM_CPU_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_BUSMON_CPU_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_TRACE_CPU_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_ICM_CPU_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_GDMA_CPU_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_VPU_CPU_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_L2MEM_MEM_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_L2MEMMON_MEM_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_ICM_MEM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_MISC_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TRACE_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_L2CACHE_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_L2MEM_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_L2MEMMON_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TCMMON_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_ICM_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_FLASH_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PSRAM_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL1 + Reserved + 0x18 + 0x20 + 0x7C7F801F + + + REG_GPSPI2_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_GPSPI3_SYS_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REGDMA_SYS_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_AHB_PDMA_SYS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_AXI_PDMA_SYS_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_GDMA_SYS_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_DMA2D_SYS_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_VPU_SYS_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_JPEG_SYS_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PPA_SYS_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_CSI_BRG_SYS_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_CSI_HOST_SYS_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_DSI_SYS_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_EMAC_SYS_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_SDMMC_SYS_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_USB_OTG11_SYS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_USB_OTG20_SYS_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_UHCI_SYS_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_UART0_SYS_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_UART1_SYS_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_UART2_SYS_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_UART3_SYS_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_UART4_SYS_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_PARLIO_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_ETM_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_PVT_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_CRYPTO_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_KEY_MANAGER_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_BITSRAMBLER_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_BITSRAMBLER_RX_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_BITSRAMBLER_TX_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_H264_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL2 + Reserved + 0x1C + 0x20 + 0x20F80FDE + + + REG_RMT_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_HP_CLKRST_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_SYSREG_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_ICM_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_INTRMTX_APB_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_ADC_APB_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_UHCI_APB_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_UART0_APB_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_UART1_APB_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_UART2_APB_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_UART3_APB_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_UART4_APB_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2C0_APB_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_I2C1_APB_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_I2S0_APB_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_I2S1_APB_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_I2S2_APB_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_I3C_MST_APB_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_I3C_SLV_APB_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_GPSPI2_APB_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_GPSPI3_APB_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_TIMERGRP0_APB_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_TIMERGRP1_APB_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_SYSTIMER_APB_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TWAI0_APB_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TWAI1_APB_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI2_APB_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_MCPWM0_APB_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_MCPWM1_APB_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_USB_DEVICE_APB_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_PCNT_APB_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PARLIO_APB_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL3 + Reserved + 0x20 + 0x20 + 0x00000008 + + + REG_LEDC_APB_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_LCDCAM_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_ETM_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_IOMUX_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + + + REF_CLK_CTRL0 + Reserved + 0x24 + 0x20 + 0x02011309 + + + REG_REF_50M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_25M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_240M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_REF_160M_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + REF_CLK_CTRL1 + Reserved + 0x28 + 0x20 + 0x58170503 + + + REG_REF_120M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_80M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_20M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_TM_400M_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TM_200M_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TM_100M_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_REF_50M_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_REF_25M_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_TM_480M_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_REF_240M_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TM_240M_CLK_EN + Reserved + 31 + 1 + read-write + + + + + REF_CLK_CTRL2 + Reserved + 0x2C + 0x20 + 0x00000115 + + + REG_REF_160M_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_TM_160M_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REF_120M_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_TM_120M_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_REF_80M_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TM_80M_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_TM_60M_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_TM_48M_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_REF_20M_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_TM_20M_CLK_EN + Reserved + 9 + 1 + read-write + + + + + PERI_CLK_CTRL00 + Reserved + 0x30 + 0x20 + 0x0000C03C + + + REG_FLASH_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_FLASH_PLL_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_FLASH_CORE_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_FLASH_CORE_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_PSRAM_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_PSRAM_PLL_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_PSRAM_CORE_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_PSRAM_CORE_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PAD_EMAC_REF_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_EMAC_RMII_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_EMAC_RMII_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_EMAC_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_EMAC_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL01 + Reserved + 0x34 + 0x20 + 0x00000401 + + + REG_EMAC_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_EMAC_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_EMAC_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_EMAC_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_EMAC_PTP_REF_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_EMAC_PTP_REF_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_EMAC_UNUSED0_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_EMAC_UNUSED1_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_SDIO_HS_MODE + Reserved + 22 + 1 + read-write + + + REG_SDIO_LS_CLK_SRC_SEL + Reserved + 23 + 1 + read-write + + + REG_SDIO_LS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL02 + Reserved + 0x38 + 0x20 + + + REG_SDIO_LS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_SDIO_LS_CLK_EDGE_CFG_UPDATE + Reserved + 8 + 1 + write-only + + + REG_SDIO_LS_CLK_EDGE_L + Reserved + 9 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_H + Reserved + 13 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_N + Reserved + 17 + 4 + read-write + + + REG_SDIO_LS_SLF_CLK_EDGE_SEL + Reserved + 21 + 2 + read-write + + + REG_SDIO_LS_DRV_CLK_EDGE_SEL + Reserved + 23 + 2 + read-write + + + REG_SDIO_LS_SAM_CLK_EDGE_SEL + Reserved + 25 + 2 + read-write + + + REG_SDIO_LS_SLF_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_SDIO_LS_DRV_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SDIO_LS_SAM_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_MIPI_DSI_DPHY_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL03 + Reserved + 0x3C + 0x20 + + + REG_MIPI_DSI_DPHY_CFG_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN + Reserved + 1 + 1 + read-write + + + REG_MIPI_CSI_DPHY_CLK_SRC_SEL + Reserved + 2 + 2 + read-write + + + REG_MIPI_CSI_DPHY_CFG_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_SRC_SEL + Reserved + 5 + 2 + read-write + + + REG_MIPI_DSI_DPICLK_EN + Reserved + 7 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + + + PERI_CLK_CTRL10 + Reserved + 0x40 + 0x20 + + + REG_I2C0_CLK_SRC_SEL + Reserved + 0 + 1 + read-write + + + REG_I2C0_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_I2C0_CLK_DIV_NUM + Reserved + 2 + 8 + read-write + + + REG_I2C0_CLK_DIV_NUMERATOR + Reserved + 10 + 8 + read-write + + + REG_I2C0_CLK_DIV_DENOMINATOR + Reserved + 18 + 8 + read-write + + + REG_I2C1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_I2C1_CLK_EN + Reserved + 27 + 1 + read-write + + + + + PERI_CLK_CTRL11 + Reserved + 0x44 + 0x20 + + + REG_I2C1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_I2C1_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_I2C1_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_I2S0_RX_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_I2S0_RX_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + + + PERI_CLK_CTRL12 + Reserved + 0x48 + 0x20 + + + REG_I2S0_RX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S0_RX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S0_RX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL13 + Reserved + 0x4C + 0x20 + + + REG_I2S0_RX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S0_RX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S0_TX_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_I2S0_TX_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_I2S0_TX_DIV_N + Reserved + 13 + 8 + read-write + + + REG_I2S0_TX_DIV_X + Reserved + 21 + 9 + read-write + + + + + PERI_CLK_CTRL14 + Reserved + 0x50 + 0x20 + + + REG_I2S0_TX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S0_TX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S0_TX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S0_MST_CLK_SEL + Reserved + 19 + 1 + read-write + + + REG_I2S1_RX_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_I2S1_RX_CLK_SRC_SEL + Reserved + 21 + 2 + read-write + + + REG_I2S1_RX_DIV_N + Reserved + 23 + 8 + read-write + + + + + PERI_CLK_CTRL15 + Reserved + 0x54 + 0x20 + + + REG_I2S1_RX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S1_RX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S1_RX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S1_RX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S1_TX_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_I2S1_TX_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + + + PERI_CLK_CTRL16 + Reserved + 0x58 + 0x20 + + + REG_I2S1_TX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S1_TX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S1_TX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL17 + Reserved + 0x5C + 0x20 + + + REG_I2S1_TX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S1_TX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S1_MST_CLK_SEL + Reserved + 10 + 1 + read-write + + + REG_I2S2_RX_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2S2_RX_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_I2S2_RX_DIV_N + Reserved + 14 + 8 + read-write + + + REG_I2S2_RX_DIV_X + Reserved + 22 + 9 + read-write + + + + + PERI_CLK_CTRL18 + Reserved + 0x60 + 0x20 + + + REG_I2S2_RX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S2_RX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S2_RX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S2_TX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_I2S2_TX_CLK_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_I2S2_TX_DIV_N + Reserved + 22 + 8 + read-write + + + + + PERI_CLK_CTRL19 + Reserved + 0x64 + 0x20 + + + REG_I2S2_TX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S2_TX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S2_TX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S2_TX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S2_MST_CLK_SEL + Reserved + 28 + 1 + read-write + + + REG_LCD_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + REG_LCD_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL110 + Reserved + 0x68 + 0x20 + 0x04000000 + + + REG_LCD_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_LCD_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_LCD_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART0_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART0_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL111 + Reserved + 0x6C + 0x20 + 0x04000000 + + + REG_UART0_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART0_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART0_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART1_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART1_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL112 + Reserved + 0x70 + 0x20 + 0x04000000 + + + REG_UART1_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART1_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART1_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART2_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART2_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL113 + Reserved + 0x74 + 0x20 + 0x04000000 + + + REG_UART2_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART2_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART2_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART3_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART3_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL114 + Reserved + 0x78 + 0x20 + 0x04000000 + + + REG_UART3_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART3_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART3_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART4_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART4_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL115 + Reserved + 0x7C + 0x20 + + + REG_UART4_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART4_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART4_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_TWAI0_CLK_SRC_SEL + Reserved + 24 + 1 + read-write + + + REG_TWAI0_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_TWAI1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TWAI2_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_TWAI2_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL116 + Reserved + 0x80 + 0x20 + 0x01100008 + + + REG_GPSPI2_CLK_SRC_SEL + Reserved + 0 + 3 + read-write + + + REG_GPSPI2_HS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_GPSPI2_HS_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_GPSPI2_MST_CLK_DIV_NUM + Reserved + 12 + 8 + read-write + + + REG_GPSPI2_MST_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_GPSPI3_CLK_SRC_SEL + Reserved + 21 + 3 + read-write + + + REG_GPSPI3_HS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL117 + Reserved + 0x84 + 0x20 + 0x00010000 + + + REG_GPSPI3_HS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_GPSPI3_MST_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_GPSPI3_MST_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_PARLIO_RX_CLK_SRC_SEL + Reserved + 17 + 2 + read-write + + + REG_PARLIO_RX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_PARLIO_RX_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + + + PERI_CLK_CTRL118 + Reserved + 0x88 + 0x20 + + + REG_PARLIO_RX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_RX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_PARLIO_TX_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_PARLIO_TX_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_PARLIO_TX_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + + + PERI_CLK_CTRL119 + Reserved + 0x8C + 0x20 + + + REG_PARLIO_TX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_TX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_I3C_MST_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_I3C_MST_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_I3C_MST_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + REG_CAM_CLK_SRC_SEL + Reserved + 27 + 2 + read-write + + + REG_CAM_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL120 + Reserved + 0x90 + 0x20 + + + REG_CAM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_CAM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_CAM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + + + PERI_CLK_CTRL20 + Reserved + 0x94 + 0x20 + 0xC9000000 + + + REG_MCPWM0_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_MCPWM0_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_MCPWM0_CLK_DIV_NUM + Reserved + 3 + 8 + read-write + + + REG_MCPWM1_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_MCPWM1_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_MCPWM1_CLK_DIV_NUM + Reserved + 14 + 8 + read-write + + + REG_TIMERGRP0_T0_SRC_SEL + Reserved + 22 + 2 + read-write + + + REG_TIMERGRP0_T0_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TIMERGRP0_T1_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_TIMERGRP0_T1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TIMERGRP0_WDT_SRC_SEL + Reserved + 28 + 2 + read-write + + + REG_TIMERGRP0_WDT_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TIMERGRP0_TGRT_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL21 + Reserved + 0x98 + 0x20 + 0x52400000 + + + REG_TIMERGRP0_TGRT_CLK_SRC_SEL + Reserved + 0 + 4 + read-write + + + REG_TIMERGRP0_TGRT_CLK_DIV_NUM + Reserved + 4 + 16 + read-write + + + REG_TIMERGRP1_T0_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_TIMERGRP1_T0_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_TIMERGRP1_T1_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_TIMERGRP1_T1_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TIMERGRP1_WDT_SRC_SEL + Reserved + 26 + 2 + read-write + + + REG_TIMERGRP1_WDT_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SYSTIMER_CLK_SRC_SEL + Reserved + 29 + 1 + read-write + + + REG_SYSTIMER_CLK_EN + Reserved + 30 + 1 + read-write + + + + + PERI_CLK_CTRL22 + Reserved + 0x9C + 0x20 + + + REG_LEDC_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_LEDC_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_RMT_CLK_SRC_SEL + Reserved + 3 + 2 + read-write + + + REG_RMT_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_RMT_CLK_DIV_NUM + Reserved + 6 + 8 + read-write + + + REG_RMT_CLK_DIV_NUMERATOR + Reserved + 14 + 8 + read-write + + + REG_RMT_CLK_DIV_DENOMINATOR + Reserved + 22 + 8 + read-write + + + REG_ADC_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL23 + Reserved + 0xA0 + 0x20 + 0x00000008 + + + REG_ADC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_ADC_CLK_DIV_NUM + Reserved + 1 + 8 + read-write + + + REG_ADC_CLK_DIV_NUMERATOR + Reserved + 9 + 8 + read-write + + + REG_ADC_CLK_DIV_DENOMINATOR + Reserved + 17 + 8 + read-write + + + + + PERI_CLK_CTRL24 + Reserved + 0xA4 + 0x20 + 0x00000404 + + + REG_ADC_SAR1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_ADC_SAR2_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_PVT_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PVT_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL25 + Reserved + 0xA8 + 0x20 + 0x007FC000 + + + REG_PVT_PERI_GROUP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PVT_PERI_GROUP1_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PVT_PERI_GROUP2_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PVT_PERI_GROUP3_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_PVT_PERI_GROUP4_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_CRYPTO_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_CRYPTO_AES_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_CRYPTO_DS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_CRYPTO_ECC_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_CRYPTO_HMAC_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_CRYPTO_RSA_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_CRYPTO_SEC_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_CRYPTO_SHA_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_CRYPTO_ECDSA_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_CRYPTO_KM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_ISP_CLK_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_ISP_CLK_EN + Reserved + 25 + 1 + read-write + + + + + PERI_CLK_CTRL26 + Reserved + 0xAC + 0x20 + 0x00000200 + + + REG_ISP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_IOMUX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_IOMUX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_IOMUX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_H264_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_H264_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_H264_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + REG_PADBIST_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_PADBIST_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL27 + Reserved + 0xB0 + 0x20 + + + REG_PADBIST_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PADBIST_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_PADBIST_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PADBIST_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + + + CLK_FORCE_ON_CTRL0 + Reserved + 0xB4 + 0x20 + 0x0003FFFF + + + REG_CPUICM_GATED_CLK_FORCE_ON + Reserved + 0 + 1 + read-write + + + REG_TCM_CPU_CLK_FORCE_ON + Reserved + 1 + 1 + read-write + + + REG_BUSMON_CPU_CLK_FORCE_ON + Reserved + 2 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_FORCE_ON + Reserved + 3 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_FORCE_ON + Reserved + 4 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_FORCE_ON + Reserved + 5 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_FORCE_ON + Reserved + 6 + 1 + read-write + + + REG_TRACE_CPU_CLK_FORCE_ON + Reserved + 7 + 1 + read-write + + + REG_TRACE_SYS_CLK_FORCE_ON + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_FORCE_ON + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_FORCE_ON + Reserved + 10 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_FORCE_ON + Reserved + 11 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_FORCE_ON + Reserved + 12 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_FORCE_ON + Reserved + 13 + 1 + read-write + + + REG_L2MEM_MEM_CLK_FORCE_ON + Reserved + 14 + 1 + read-write + + + REG_SAR1_CLK_FORCE_ON + Reserved + 15 + 1 + read-write + + + REG_SAR2_CLK_FORCE_ON + Reserved + 16 + 1 + read-write + + + REG_GMAC_TX_CLK_FORCE_ON + Reserved + 17 + 1 + read-write + + + + + DPA_CTRL0 + Reserved + 0xB8 + 0x20 + + + REG_SEC_DPA_LEVEL + Reserved + 0 + 2 + read-write + + + REG_SEC_DPA_CFG_SEL + Reserved + 2 + 1 + read-write + + + + + ANA_PLL_CTRL0 + Reserved + 0xBC + 0x20 + + + REG_PLLA_CAL_END + Reserved + 0 + 1 + read-only + + + REG_PLLA_CAL_STOP + Reserved + 1 + 1 + read-write + + + REG_CPU_PLL_CAL_END + Reserved + 2 + 1 + read-only + + + REG_CPU_PLL_CAL_STOP + Reserved + 3 + 1 + read-write + + + REG_SDIO_PLL_CAL_END + Reserved + 4 + 1 + read-only + + + REG_SDIO_PLL_CAL_STOP + Reserved + 5 + 1 + read-write + + + REG_SYS_PLL_CAL_END + Reserved + 6 + 1 + read-only + + + REG_SYS_PLL_CAL_STOP + Reserved + 7 + 1 + read-write + + + REG_MSPI_CAL_END + Reserved + 8 + 1 + read-only + + + REG_MSPI_CAL_STOP + Reserved + 9 + 1 + read-write + + + + + HP_RST_EN0 + Reserved + 0xC0 + 0x20 + 0x00000100 + + + REG_RST_EN_CORECTRL + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PVT_TOP + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP1 + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP2 + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP3 + Reserved + 4 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP4 + Reserved + 5 + 1 + read-write + + + REG_RST_EN_REGDMA + Reserved + 6 + 1 + read-write + + + REG_RST_EN_CORE0_GLOBAL + Reserved + 7 + 1 + read-write + + + REG_RST_EN_CORE1_GLOBAL + Reserved + 8 + 1 + read-write + + + REG_RST_EN_CORETRACE0 + Reserved + 9 + 1 + read-write + + + REG_RST_EN_CORETRACE1 + Reserved + 10 + 1 + read-write + + + REG_RST_EN_HP_TCM + Reserved + 11 + 1 + read-write + + + REG_RST_EN_HP_CACHE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_L1_I0_CACHE + Reserved + 13 + 1 + read-write + + + REG_RST_EN_L1_I1_CACHE + Reserved + 14 + 1 + read-write + + + REG_RST_EN_L1_D_CACHE + Reserved + 15 + 1 + read-write + + + REG_RST_EN_L2_CACHE + Reserved + 16 + 1 + read-write + + + REG_RST_EN_L2_MEM + Reserved + 17 + 1 + read-write + + + REG_RST_EN_L2MEMMON + Reserved + 18 + 1 + read-write + + + REG_RST_EN_TCMMON + Reserved + 19 + 1 + read-write + + + REG_RST_EN_PVT_APB + Reserved + 20 + 1 + read-write + + + REG_RST_EN_GDMA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_MSPI_AXI + Reserved + 22 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_AXI + Reserved + 23 + 1 + read-write + + + REG_RST_EN_MSPI_APB + Reserved + 24 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_APB + Reserved + 25 + 1 + read-write + + + REG_RST_EN_DSI_BRG + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CSI_HOST + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CSI_BRG + Reserved + 28 + 1 + read-write + + + REG_RST_EN_ISP + Reserved + 29 + 1 + read-write + + + REG_RST_EN_JPEG + Reserved + 30 + 1 + read-write + + + REG_RST_EN_DMA2D + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN1 + Reserved + 0xC4 + 0x20 + + + REG_RST_EN_PPA + Reserved + 0 + 1 + read-write + + + REG_RST_EN_AHB_PDMA + Reserved + 1 + 1 + read-write + + + REG_RST_EN_AXI_PDMA + Reserved + 2 + 1 + read-write + + + REG_RST_EN_IOMUX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PADBIST + Reserved + 4 + 1 + read-write + + + REG_RST_EN_STIMER + Reserved + 5 + 1 + read-write + + + REG_RST_EN_TIMERGRP0 + Reserved + 6 + 1 + read-write + + + REG_RST_EN_TIMERGRP1 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_UART0_CORE + Reserved + 8 + 1 + read-write + + + REG_RST_EN_UART1_CORE + Reserved + 9 + 1 + read-write + + + REG_RST_EN_UART2_CORE + Reserved + 10 + 1 + read-write + + + REG_RST_EN_UART3_CORE + Reserved + 11 + 1 + read-write + + + REG_RST_EN_UART4_CORE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_UART0_APB + Reserved + 13 + 1 + read-write + + + REG_RST_EN_UART1_APB + Reserved + 14 + 1 + read-write + + + REG_RST_EN_UART2_APB + Reserved + 15 + 1 + read-write + + + REG_RST_EN_UART3_APB + Reserved + 16 + 1 + read-write + + + REG_RST_EN_UART4_APB + Reserved + 17 + 1 + read-write + + + REG_RST_EN_UHCI + Reserved + 18 + 1 + read-write + + + REG_RST_EN_I3CMST + Reserved + 19 + 1 + read-write + + + REG_RST_EN_I3CSLV + Reserved + 20 + 1 + read-write + + + REG_RST_EN_I2C1 + Reserved + 21 + 1 + read-write + + + REG_RST_EN_I2C0 + Reserved + 22 + 1 + read-write + + + REG_RST_EN_RMT + Reserved + 23 + 1 + read-write + + + REG_RST_EN_PWM0 + Reserved + 24 + 1 + read-write + + + REG_RST_EN_PWM1 + Reserved + 25 + 1 + read-write + + + REG_RST_EN_CAN0 + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CAN1 + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CAN2 + Reserved + 28 + 1 + read-write + + + REG_RST_EN_LEDC + Reserved + 29 + 1 + read-write + + + REG_RST_EN_PCNT + Reserved + 30 + 1 + read-write + + + REG_RST_EN_ETM + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN2 + Reserved + 0xC8 + 0x20 + + + REG_RST_EN_INTRMTX + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PARLIO + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PARLIO_RX + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PARLIO_TX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_I2S0_APB + Reserved + 4 + 1 + read-write + + + REG_RST_EN_I2S1_APB + Reserved + 5 + 1 + read-write + + + REG_RST_EN_I2S2_APB + Reserved + 6 + 1 + read-write + + + REG_RST_EN_SPI2 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_SPI3 + Reserved + 8 + 1 + read-write + + + REG_RST_EN_LCDCAM + Reserved + 9 + 1 + read-write + + + REG_RST_EN_ADC + Reserved + 10 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER + Reserved + 11 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_RX + Reserved + 12 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_TX + Reserved + 13 + 1 + read-write + + + REG_RST_EN_CRYPTO + Reserved + 14 + 1 + read-write + + + REG_RST_EN_SEC + Reserved + 15 + 1 + read-write + + + REG_RST_EN_AES + Reserved + 16 + 1 + read-write + + + REG_RST_EN_DS + Reserved + 17 + 1 + read-write + + + REG_RST_EN_SHA + Reserved + 18 + 1 + read-write + + + REG_RST_EN_HMAC + Reserved + 19 + 1 + read-write + + + REG_RST_EN_ECDSA + Reserved + 20 + 1 + read-write + + + REG_RST_EN_RSA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_ECC + Reserved + 22 + 1 + read-write + + + REG_RST_EN_KM + Reserved + 23 + 1 + read-write + + + REG_RST_EN_H264 + Reserved + 24 + 1 + read-write + + + + + HP_FORCE_NORST0 + Reserved + 0xCC + 0x20 + + + REG_FORCE_NORST_CORE0 + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_CORE1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE1 + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_L2MEMMON + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_TCMMON + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_GDMA + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_MSPI_AXI + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_AXI + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_MSPI_APB + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_APB + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_DSI_BRG + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_CSI_HOST + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_CSI_BRG + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_ISP + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_JPEG + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_DMA2D + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_PPA + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_AHB_PDMA + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_AXI_PDMA + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_IOMUX + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_PADBIST + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_STIMER + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP0 + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP1 + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_UART0 + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_UART1 + Reserved + 26 + 1 + read-write + + + REG_FORCE_NORST_UART2 + Reserved + 27 + 1 + read-write + + + REG_FORCE_NORST_UART3 + Reserved + 28 + 1 + read-write + + + REG_FORCE_NORST_UART4 + Reserved + 29 + 1 + read-write + + + REG_FORCE_NORST_UHCI + Reserved + 30 + 1 + read-write + + + REG_FORCE_NORST_I3CMST + Reserved + 31 + 1 + read-write + + + + + HP_FORCE_NORST1 + Reserved + 0xD0 + 0x20 + + + REG_FORCE_NORST_I3CSLV + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_I2C1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_I2C0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_RMT + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_PWM0 + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_PWM1 + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_CAN0 + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_CAN1 + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_CAN2 + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_LEDC + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_PCNT + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_ETM + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_INTRMTX + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_PARLIO + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_RX + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_TX + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_I2S0 + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_I2S1 + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_I2S2 + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_SPI2 + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_SPI3 + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_LCDCAM + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_ADC + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_RX + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_TX + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_H264 + Reserved + 26 + 1 + read-write + + + + + HPWDT_CORE0_RST_CTRL0 + Reserved + 0xD4 + 0x20 + 0x00001011 + + + REG_HPCORE0_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE0_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE0_RST_LEN + Reserved + 9 + 8 + read-write + + + + + HPWDT_CORE1_RST_CTRL0 + Reserved + 0xD8 + 0x20 + 0x00001011 + + + REG_HPCORE1_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE1_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE1_RST_LEN + Reserved + 9 + 8 + read-write + + + + + CPU_SRC_FREQ0 + CPU Source Frequency + 0xDC + 0x20 + + + REG_CPU_SRC_FREQ + cpu source clock frequency, step by 0.25MHz + 0 + 32 + read-only + + + + + CPU_CLK_STATUS0 + CPU Clock Status + 0xE0 + 0x20 + + + REG_ASIC_OR_FPGA + 0: ASIC mode, 1: FPGA mode + 0 + 1 + read-only + + + REG_CPU_DIV_EFFECT + 0: Divider bypass, 1: Divider takes effect + 1 + 1 + read-only + + + REG_CPU_SRC_IS_CPLL + 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m + 2 + 1 + read-only + + + REG_CPU_DIV_NUM_CUR + cpu current div number + 3 + 8 + read-only + + + REG_CPU_DIV_NUMERATOR_CUR + cpu current div numerator + 11 + 8 + read-only + + + REG_CPU_DIV_DENOMINATOR_CUR + cpu current div denominator + 19 + 8 + read-only + + + + + DBG_CLK_CTRL0 + Reserved + 0xE4 + 0x20 + 0x03FFFFFF + + + REG_DBG_CH0_SEL + Reserved + 0 + 8 + read-write + + + REG_DBG_CH1_SEL + Reserved + 8 + 8 + read-write + + + REG_DBG_CH2_SEL + Reserved + 16 + 8 + read-write + + + REG_DBG_CH0_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + DBG_CLK_CTRL1 + Reserved + 0xE8 + 0x20 + 0x00000303 + + + REG_DBG_CH1_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_DBG_CH2_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_DBG_CH0_EN + Reserved + 16 + 1 + read-write + + + REG_DBG_CH1_EN + Reserved + 17 + 1 + read-write + + + REG_DBG_CH2_EN + Reserved + 18 + 1 + read-write + + + + + HPCORE_WDT_RESET_SOURCE0 + Reserved + 0xEC + 0x20 + 0x00000002 + + + REG_HPCORE0_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 + 0 + 1 + read-write + + + REG_HPCORE1_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 + 1 + 1 + read-write + + + + + + + LP_HUK + LP_HUK Peripheral + HUK + 0x50114000 + + 0x0 + 0x1A8 + registers + + + LP_HUK + 20 + + + + CLK + HUK Generator clock gate control register + 0x4 + 0x20 + 0x00000001 + + + EN + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + MEM_CG_FORCE_ON + Write 1 to force on memory clock gate. + 1 + 1 + read-write + + + + + INT_RAW + HUK Generator interrupt raw register, valid in level. + 0x8 + 0x20 + + + PREP_DONE_INT_RAW + The raw interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_RAW + The raw interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_RAW + The raw interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ST + HUK Generator interrupt status register. + 0xC + 0x20 + + + PREP_DONE_INT_ST + The masked interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_ST + The masked interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_ST + The masked interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ENA + HUK Generator interrupt enable register. + 0x10 + 0x20 + + + PREP_DONE_INT_ENA + The interrupt enable bit for the huk_prep_done_int interrupt + 0 + 1 + read-write + + + PROC_DONE_INT_ENA + The interrupt enable bit for the huk_proc_done_int interrupt + 1 + 1 + read-write + + + POST_DONE_INT_ENA + The interrupt enable bit for the huk_post_done_int interrupt + 2 + 1 + read-write + + + + + INT_CLR + HUK Generator interrupt clear register. + 0x14 + 0x20 + + + PREP_DONE_INT_CLR + Set this bit to clear the huk_prep_done_int interrupt + 0 + 1 + write-only + + + PROC_DONE_INT_CLR + Set this bit to clear the huk_proc_done_int interrupt + 1 + 1 + write-only + + + POST_DONE_INT_CLR + Set this bit to clear the huk_post_done_int interrupt + 2 + 1 + write-only + + + + + CONF + HUK Generator configuration register + 0x20 + 0x20 + + + MODE + Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. + 0 + 1 + read-write + + + + + START + HUK Generator control register + 0x24 + 0x20 + + + START + Write 1 to continue HUK Generator operation at LOAD/GAIN state. + 0 + 1 + write-only + + + CONTINUE + Write 1 to start HUK Generator at IDLE state. + 1 + 1 + write-only + + + + + STATE + HUK Generator state register + 0x28 + 0x20 + + + STATE + The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + 0 + 2 + read-only + + + + + STATUS + HUK Generator HUK status register + 0x34 + 0x20 + + + STATUS + The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. + 0 + 2 + read-only + + + RISK_LEVEL + The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. + 2 + 3 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + HUK Generator version control register. + 0 + 28 + read-write + + + + + 96 + 0x4 + INFO_MEM[%s] + The memory that stores HUK info. + 0x100 + 0x20 + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x500C4000 + + 0x0 + 0x90 + registers + + + I2C0 + 44 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Configures the module as an I2C Master or Slave. +0: Slave + +1: Master + 4 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + Configures to enable slave to send data automatically +0: Disable + +1: Enable + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. +0: Not check + +1: Check + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + Configures to support the 7bit general call function. +0: Not support + +1: Support + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + Represents the transfer direction in slave mode,. +1: Master reads from slave, + +0: Master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + Represents whether the address sent by the master is equal to the address of the slave. +Valid only when the module is configured as an I2C Slave. +0: Not equal + +1: Equal + 5 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + Represents the cause of SCL clocking stretching in slave mode. +0: Stretching SCL low when the master starts to read data. + +1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + +2: Stretching SCL low when I2C RX FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + Configure the slave address of I2C Slave. + 0 + 15 + read-write + + + ADDR_10BIT_EN + Configures to enable the slave 10-bit addressing mode in master mode. +0: No effect + +1: Enable + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 5 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 5 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 5 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 5 + read-only + + + SLAVE_RW_POINT + Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. +0: Disable + +1: Enable + 11 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to enable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to enable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to enable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and SCL rising edge for a stop condition. +Measurement unit: i2c_sclk + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 1 + 5 + read-write + + + SCL_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SDA line. +0: Not power down. + +1: Power down. +Valid only when reg_sda_force_out is 1. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. +Measurement unit: i2c_sclk + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + Configures to enable slave SCL stretch function. +0: Disable + +1: Enable +The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Configures to clear the I2C slave SCL stretch function. +0: No effect + +1: Clear + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + Configures to enable the function for slave to control ACK level. +0: Disable + +1: Enable + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. +0: Low level + +1: High level + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x500C5000 + + I2C1 + 45 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x500C6000 + + 0x0 + 0x60 + registers + + + I2S0 + 27 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00C0B600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 4 + 2 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 6 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 + 1 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x00C0F210 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 4 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 5 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 + 6 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x787BC000 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_PDM2PCM_CONF + I2S RX configure register + 0x48 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + FIFO_CNT + I2S sync counter register + 0x74 + 0x20 + + + TX_FIFO_CNT + tx fifo counter value. + 0 + 31 + read-only + + + TX_FIFO_CNT_RST + Set this bit to reset tx fifo counter. + 31 + 1 + write-only + + + + + BCK_CNT + I2S sync counter register + 0x78 + 0x20 + + + TX_BCK_CNT + tx bck counter value. + 0 + 31 + read-only + + + TX_BCK_CNT_RST + Set this bit to reset tx bck counter. + 31 + 1 + write-only + + + + + CLK_GATE + Clock gate register + 0x7C + 0x20 + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02303240 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + 0x500C7000 + + I2S1 + 28 + + + + I2S2 + I2S (Inter-IC Sound) Controller 2 + 0x500C8000 + + I2S2 + 29 + + + + I3C_MST + I3C Controller (Master) + I3C_MST + 0x500DA000 + + 0x0 + 0x90 + registers + + + I3C + 101 + + + + DEVICE_CTRL + DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. + 0x0 + 0x20 + 0x00001020 + + + REG_BA_INCLUDE + This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) + 1 + 1 + read-write + + + REG_TRANS_START + Transfer Start + 2 + 1 + read-write + + + REG_CLK_EN + NA + 3 + 1 + read-write + + + REG_IBI_RSTART_TRANS_EN + NA + 4 + 1 + read-write + + + REG_AUTO_DIS_IBI_EN + NA + 5 + 1 + read-write + + + REG_DMA_RX_EN + NA + 6 + 1 + read-write + + + REG_DMA_TX_EN + NA + 7 + 1 + read-write + + + REG_MULTI_SLV_SINGLE_CCC_EN + 0: rx high bit first, 1: rx low bit first + 8 + 1 + read-write + + + REG_RX_BIT_ORDER + 0: rx low byte fist, 1: rx high byte first + 9 + 1 + read-write + + + REG_RX_BYTE_ORDER + NA + 10 + 1 + read-write + + + REG_SCL_PULLUP_FORCE_EN + This bit is used to force scl_pullup_en + 11 + 1 + read-write + + + REG_SCL_OE_FORCE_EN + This bit is used to force scl_oe + 12 + 1 + read-write + + + REG_SDA_PP_RD_PULLUP_EN + NA + 13 + 1 + read-write + + + REG_SDA_RD_TBIT_HLVL_PULLUP_EN + NA + 14 + 1 + read-write + + + REG_SDA_PP_WR_PULLUP_EN + NA + 15 + 1 + read-write + + + REG_DATA_BYTE_CNT_UNLATCH + 1: read current real-time updated value 0: read latch data byte cnt value + 16 + 1 + read-write + + + REG_MEM_CLK_FORCE_ON + 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. + 17 + 1 + read-write + + + + + BUFFER_THLD_CTRL + In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. + 0x1C + 0x20 + 0x00041041 + + + REG_CMD_BUF_EMPTY_THLD + Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. + 0 + 4 + read-write + + + REG_RESP_BUF_THLD + Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. + 6 + 3 + read-write + + + REG_IBI_DATA_BUF_THLD + In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. + 12 + 3 + read-write + + + REG_IBI_STATUS_BUF_THLD + NA + 18 + 3 + read-write + + + + + DATA_BUFFER_THLD_CTRL + NA + 0x20 + 0x20 + 0x00000009 + + + REG_TX_DATA_BUF_THLD + Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 + 0 + 3 + read-write + + + REG_RX_DATA_BUF_THLD + Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 + 3 + 3 + read-write + + + + + IBI_NOTIFY_CTRL + NA + 0x24 + 0x20 + + + REG_NOTIFY_SIR_REJECTED + Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. + 2 + 1 + read-write + + + + + IBI_SIR_REQ_PAYLOAD + NA + 0x28 + 0x20 + + + REG_SIR_REQ_PAYLOAD + NA + 0 + 32 + read-write + + + + + IBI_SIR_REQ_REJECT + NA + 0x2C + 0x20 + + + REG_SIR_REQ_REJECT + The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC + 0 + 32 + read-write + + + + + INT_CLR + NA + 0x30 + 0x20 + + + TX_DATA_BUF_THLD_INT_CLR + NA + 0 + 1 + write-only + + + RX_DATA_BUF_THLD_INT_CLR + NA + 1 + 1 + write-only + + + IBI_STATUS_THLD_INT_CLR + NA + 2 + 1 + write-only + + + CMD_BUF_EMPTY_THLD_INT_CLR + NA + 3 + 1 + write-only + + + RESP_READY_INT_CLR + NA + 4 + 1 + write-only + + + NXT_CMD_REQ_ERR_INT_CLR + NA + 5 + 1 + write-only + + + TRANSFER_ERR_INT_CLR + NA + 6 + 1 + write-only + + + TRANSFER_COMPLETE_INT_CLR + NA + 7 + 1 + write-only + + + COMMAND_DONE_INT_CLR + NA + 8 + 1 + write-only + + + DETECT_START_INT_CLR + NA + 9 + 1 + write-only + + + RESP_BUF_OVF_INT_CLR + NA + 10 + 1 + write-only + + + IBI_DATA_BUF_OVF_INT_CLR + NA + 11 + 1 + write-only + + + IBI_STATUS_BUF_OVF_INT_CLR + NA + 12 + 1 + write-only + + + IBI_HANDLE_DONE_INT_CLR + NA + 13 + 1 + write-only + + + IBI_DETECT_INT_CLR + NA + 14 + 1 + write-only + + + CMD_CCC_MISMATCH_INT_CLR + NA + 15 + 1 + write-only + + + + + INT_RAW + NA + 0x34 + 0x20 + 0x00000008 + + + TX_DATA_BUF_THLD_INT_RAW + NA + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_RAW + NA + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_RAW + NA + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_RAW + NA + 3 + 1 + read-write + + + RESP_READY_INT_RAW + NA + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_RAW + NA + 5 + 1 + read-write + + + TRANSFER_ERR_INT_RAW + NA + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_RAW + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_RAW + NA + 8 + 1 + read-write + + + DETECT_START_INT_RAW + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_RAW + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_RAW + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_RAW + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_RAW + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_RAW + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_RAW + NA + 15 + 1 + read-write + + + + + INT_ST + NA + 0x38 + 0x20 + + + TX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. + 0 + 1 + read-only + + + RX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. + 1 + 1 + read-only + + + IBI_STATUS_THLD_INT_ST + Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. + 2 + 1 + read-only + + + CMD_BUF_EMPTY_THLD_INT_ST + This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. + 3 + 1 + read-only + + + RESP_READY_INT_ST + This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. + 4 + 1 + read-only + + + NXT_CMD_REQ_ERR_INT_ST + This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. + 5 + 1 + read-only + + + TRANSFER_ERR_INT_ST + This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. + 6 + 1 + read-only + + + TRANSFER_COMPLETE_INT_ST + NA + 7 + 1 + read-only + + + COMMAND_DONE_INT_ST + NA + 8 + 1 + read-only + + + DETECT_START_INT_ST + NA + 9 + 1 + read-only + + + RESP_BUF_OVF_INT_ST + NA + 10 + 1 + read-only + + + IBI_DATA_BUF_OVF_INT_ST + NA + 11 + 1 + read-only + + + IBI_STATUS_BUF_OVF_INT_ST + NA + 12 + 1 + read-only + + + IBI_HANDLE_DONE_INT_ST + NA + 13 + 1 + read-only + + + IBI_DETECT_INT_ST + NA + 14 + 1 + read-only + + + CMD_CCC_MISMATCH_INT_ST + NA + 15 + 1 + read-only + + + + + INT_ST_ENA + The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. + 0x3C + 0x20 + + + TX_DATA_BUF_THLD_INT_ENA + Transmit Buffer threshold status enable. + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_ENA + Receive Buffer threshold status enable. + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_ENA + Only used in master mode. IBI Buffer threshold status enable. + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_ENA + Command buffer ready status enable. + 3 + 1 + read-write + + + RESP_READY_INT_ENA + Response buffer ready status enable. + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_ENA + next command request error status enable + 5 + 1 + read-write + + + TRANSFER_ERR_INT_ENA + Transfer error status enable + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_ENA + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_ENA + NA + 8 + 1 + read-write + + + DETECT_START_INT_ENA + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_ENA + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_ENA + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_ENA + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_ENA + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_ENA + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_ENA + NA + 15 + 1 + read-write + + + + + RESET_CTRL + NA + 0x44 + 0x20 + + + REG_CORE_SOFT_RST + NA + 0 + 1 + write-only + + + REG_CMD_BUF_RST + NA + 1 + 1 + read-write + + + REG_RESP_BUF_RST + NA + 2 + 1 + read-write + + + REG_TX_DATA_BUF_BUF_RST + NA + 3 + 1 + read-write + + + REG_RX_DATA_BUF_RST + NA + 4 + 1 + read-write + + + REG_IBI_DATA_BUF_RST + NA + 5 + 1 + read-write + + + REG_IBI_STATUS_BUF_RST + NA + 6 + 1 + read-write + + + + + BUFFER_STATUS_LEVEL + BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. + 0x48 + 0x20 + 0x00000010 + + + CMD_BUF_EMPTY_CNT + Command Buffer Empty Locations contains the number of empty locations in the command buffer. + 0 + 5 + read-only + + + RESP_BUF_CNT + Response Buffer Level Value contains the number of valid data entries in the response buffer. + 8 + 4 + read-only + + + IBI_DATA_BUF_CNT + IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. + 16 + 4 + read-only + + + IBI_STATUS_BUF_CNT + IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. + 24 + 4 + read-only + + + + + DATA_BUFFER_STATUS_LEVEL + DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. + 0x4C + 0x20 + 0x00000020 + + + TX_DATA_BUF_EMPTY_CNT + Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. + 0 + 6 + read-only + + + RX_DATA_BUF_CNT + Receive Buffer Level value contains the number of valid data entries in the receive buffer. + 16 + 6 + read-only + + + + + PRESENT_STATE0 + NA + 0x50 + 0x20 + 0x00000003 + + + SDA_LVL + This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. + 0 + 1 + read-only + + + SCL_LVL + This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. + 1 + 1 + read-only + + + BUS_BUSY + NA + 2 + 1 + read-only + + + BUS_FREE + NA + 3 + 1 + read-only + + + CMD_TID + NA + 9 + 4 + read-only + + + SCL_GEN_FSM_STATE + NA + 13 + 3 + read-only + + + IBI_EV_HANDLE_FSM_STATE + NA + 16 + 3 + read-only + + + I2C_MODE_FSM_STATE + NA + 19 + 3 + read-only + + + SDR_MODE_FSM_STATE + NA + 22 + 4 + read-only + + + DAA_MODE_FSM_STATE + Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle + 26 + 3 + read-only + + + MAIN_FSM_STATE + NA + 29 + 3 + read-only + + + + + PRESENT_STATE1 + NA + 0x54 + 0x20 + + + DATA_BYTE_CNT + Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. + 0 + 16 + read-only + + + + + DEVICE_TABLE + Pointer for Device Address Table + 0x58 + 0x20 + + + REG_DCT_DAA_INIT_INDEX + Reserved + 0 + 4 + read-write + + + REG_DAT_DAA_INIT_INDEX + NA + 4 + 4 + read-write + + + PRESENT_DCT_INDEX + NA + 8 + 4 + read-only + + + PRESENT_DAT_INDEX + NA + 12 + 4 + read-only + + + + + TIME_OUT_VALUE + NA + 0x5C + 0x20 + 0x00410410 + + + REG_RESP_BUF_TO_VALUE + NA + 0 + 5 + read-write + + + REG_RESP_BUF_TO_EN + NA + 5 + 1 + read-write + + + REG_IBI_DATA_BUF_TO_VALUE + NA + 6 + 5 + read-write + + + REG_IBI_DATA_BUF_TO_EN + NA + 11 + 1 + read-write + + + REG_IBI_STATUS_BUF_TO_VALUE + NA + 12 + 5 + read-write + + + REG_IBI_STATUS_BUF_TO_EN + NA + 17 + 1 + read-write + + + REG_RX_DATA_BUF_TO_VALUE + NA + 18 + 5 + read-write + + + REG_RX_DATA_BUF_TO_EN + NA + 23 + 1 + read-write + + + + + SCL_I3C_MST_OD_TIME + NA + 0x60 + 0x20 + 0x00050019 + + + REG_I3C_MST_OD_LOW_PERIOD + SCL Open-Drain low count for I3C transfers targeted to I3C devices. + 0 + 16 + read-write + + + REG_I3C_MST_OD_HIGH_PERIOD + SCL Open-Drain High count for I3C transfers targeted to I3C devices. + 16 + 16 + read-write + + + + + SCL_I3C_MST_PP_TIME + NA + 0x64 + 0x20 + 0x00050005 + + + REG_I3C_MST_PP_LOW_PERIOD + NA + 0 + 8 + read-write + + + REG_I3C_MST_PP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_I2C_FM_TIME + NA + 0x68 + 0x20 + 0x004B00A3 + + + REG_I2C_FM_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FM_HIGH_PERIOD + The SCL open-drain low count timing for I2C Fast Mode transfers. + 16 + 16 + read-write + + + + + SCL_I2C_FMP_TIME + NA + 0x6C + 0x20 + 0x0021003F + + + REG_I2C_FMP_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FMP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_EXT_LOW_TIME + NA + 0x70 + 0x20 + + + REG_I3C_MST_EXT_LOW_PERIOD1 + NA + 0 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD2 + NA + 8 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD3 + NA + 16 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD4 + NA + 24 + 8 + read-write + + + + + SDA_SAMPLE_TIME + NA + 0x74 + 0x20 + + + REG_SDA_OD_SAMPLE_TIME + It is used to adjust sda sample point when scl high under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_SAMPLE_TIME + It is used to adjust sda sample point when scl high under push pull speed + 9 + 5 + read-write + + + + + SDA_HOLD_TIME + NA + 0x78 + 0x20 + 0x00000001 + + + REG_SDA_OD_TX_HOLD_TIME + It is used to adjust sda drive point after scl neg under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_TX_HOLD_TIME + It is used to adjust sda dirve point after scl neg under push pull speed + 9 + 5 + read-write + + + + + SCL_START_HOLD + NA + 0x7C + 0x20 + 0x00000008 + + + REG_SCL_START_HOLD_TIME + I2C_SCL_START_HOLD_TIME + 0 + 9 + read-write + + + REG_START_DET_HOLD_TIME + NA + 9 + 2 + read-write + + + + + SCL_RSTART_SETUP + NA + 0x80 + 0x20 + 0x00000008 + + + REG_SCL_RSTART_SETUP_TIME + I2C_SCL_RSTART_SETUP_TIME + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + NA + 0x84 + 0x20 + 0x00000008 + + + REG_SCL_STOP_HOLD_TIME + I2C_SCL_STOP_HOLD_TIME + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + NA + 0x88 + 0x20 + 0x00000008 + + + REG_SCL_STOP_SETUP_TIME + I2C_SCL_STOP_SETUP_TIME + 0 + 9 + read-write + + + + + BUS_FREE_TIME + NA + 0x90 + 0x20 + 0x00000005 + + + REG_BUS_FREE_TIME + I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. + 0 + 16 + read-write + + + + + SCL_TERMN_T_EXT_LOW_TIME + NA + 0x94 + 0x20 + 0x00000002 + + + REG_I3C_MST_TERMN_T_EXT_LOW_TIME + NA + 0 + 8 + read-write + + + + + VER_ID + NA + 0xA0 + 0x20 + 0x20230504 + + + REG_I3C_MST_VER_ID + This field indicates the controller current release number that is read by an application. + 0 + 32 + read-write + + + + + VER_TYPE + NA + 0xA4 + 0x20 + + + REG_I3C_MST_VER_TYPE + This field indicates the controller current release type that is read by an application. + 0 + 32 + read-write + + + + + FPGA_DEBUG_PROBE + NA + 0xAC + 0x20 + 0x00000001 + + + REG_I3C_MST_FPGA_DEBUG_PROBE + For Debug Probe Test on FPGA + 0 + 32 + read-write + + + + + RND_ECO_CS + NA + 0xB0 + 0x20 + + + REG_RND_ECO_EN + NA + 0 + 1 + read-write + + + RND_ECO_RESULT + NA + 1 + 1 + read-only + + + + + RND_ECO_LOW + NA + 0xB4 + 0x20 + + + REG_RND_ECO_LOW + NA + 0 + 32 + read-write + + + + + RND_ECO_HIGH + NA + 0xB8 + 0x20 + 0x0000FFFF + + + REG_RND_ECO_HIGH + NA + 0 + 32 + read-write + + + + + + + I3C_MST_MEM + I3C_MST_MEM Peripheral + I3C_MST_MEM + 0x500DA000 + + 0x0 + 0x108 + registers + + + + COMMAND_BUF_PORT + NA + 0x8 + 0x20 + + + REG_COMMAND + Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. + 0 + 32 + read-write + + + + + RESPONSE_BUF_PORT + NA + 0xC + 0x20 + + + RESPONSE + The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. + 0 + 32 + read-only + + + + + RX_DATA_PORT + NA + 0x10 + 0x20 + + + RX_DATA_PORT + Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-only + + + + + TX_DATA_PORT + NA + 0x14 + 0x20 + + + REG_TX_DATA_PORT + Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-write + + + + + IBI_STATUS_BUF + In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) + 0x18 + 0x20 + + + DATA_LENGTH + This field represents the length of data received along with IBI, in bytes. + 0 + 8 + read-only + + + IBI_ID + IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. + 8 + 8 + read-only + + + IBI_STS + IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). + 28 + 1 + read-only + + + + + IBI_DATA_BUF + NA + 0x40 + 0x20 + + + IBI_DATA + NA + 0 + 32 + read-only + + + + + DEV_ADDR_TABLE1_LOC + NA + 0xC0 + 0x20 + + + REG_DAT_DEV1_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV1_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV1_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV1_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE2_LOC + NA + 0xC4 + 0x20 + + + REG_DAT_DEV2_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV2_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV2_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV2_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE3_LOC + NA + 0xC8 + 0x20 + + + REG_DAT_DEV3_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV3_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV3_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV3_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE4_LOC + NA + 0xCC + 0x20 + + + REG_DAT_DEV4_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV4_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV4_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV4_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE5_LOC + NA + 0xD0 + 0x20 + + + REG_DAT_DEV5_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV5_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV5_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV5_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE6_LOC + NA + 0xD4 + 0x20 + + + REG_DAT_DEV6_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV6_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV6_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV6_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE7_LOC + NA + 0xD8 + 0x20 + + + REG_DAT_DEV7_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV7_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV7_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV7_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE8_LOC + NA + 0xDC + 0x20 + + + REG_DAT_DEV8_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV8_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV8_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV8_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE9_LOC + NA + 0xE0 + 0x20 + + + REG_DAT_DEV9_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV9_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV9_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV9_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE10_LOC + NA + 0xE4 + 0x20 + + + REG_DAT_DEV10_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV10_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV10_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV10_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE11_LOC + NA + 0xE8 + 0x20 + + + REG_DAT_DEV11_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV11_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV11_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV11_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE12_LOC + NA + 0xEC + 0x20 + + + REG_DAT_DEV12_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV12_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV12_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV12_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_CHAR_TABLE1_LOC1 + NA + 0x100 + 0x20 + + + DCT_DEV1_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC2 + NA + 0x104 + 0x20 + + + DCT_DEV1_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC3 + NA + 0x108 + 0x20 + + + DCT_DEV1_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC4 + NA + 0x10C + 0x20 + + + DCT_DEV1_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC1 + NA + 0x110 + 0x20 + + + DCT_DEV2_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC2 + NA + 0x114 + 0x20 + + + DCT_DEV2_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC3 + NA + 0x118 + 0x20 + + + DCT_DEV2_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC4 + NA + 0x11C + 0x20 + + + DCT_DEV2_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC1 + NA + 0x120 + 0x20 + + + DCT_DEV3_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC2 + NA + 0x124 + 0x20 + + + DCT_DEV3_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC3 + NA + 0x128 + 0x20 + + + DCT_DEV3_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC4 + NA + 0x12C + 0x20 + + + DCT_DEV3_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC1 + NA + 0x130 + 0x20 + + + DCT_DEV4_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC2 + NA + 0x134 + 0x20 + + + DCT_DEV4_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC3 + NA + 0x138 + 0x20 + + + DCT_DEV4_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC4 + NA + 0x13C + 0x20 + + + DCT_DEV4_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC1 + NA + 0x140 + 0x20 + + + DCT_DEV5_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC2 + NA + 0x144 + 0x20 + + + DCT_DEV5_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC3 + NA + 0x148 + 0x20 + + + DCT_DEV5_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC4 + NA + 0x14C + 0x20 + + + DCT_DEV5_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC1 + NA + 0x150 + 0x20 + + + DCT_DEV6_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC2 + NA + 0x154 + 0x20 + + + DCT_DEV6_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC3 + NA + 0x158 + 0x20 + + + DCT_DEV6_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC4 + NA + 0x15C + 0x20 + + + DCT_DEV6_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC1 + NA + 0x160 + 0x20 + + + DCT_DEV7_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC2 + NA + 0x164 + 0x20 + + + DCT_DEV7_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC3 + NA + 0x168 + 0x20 + + + DCT_DEV7_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC4 + NA + 0x16C + 0x20 + + + DCT_DEV7_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC1 + NA + 0x170 + 0x20 + + + DCT_DEV8_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC2 + NA + 0x174 + 0x20 + + + DCT_DEV8_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC3 + NA + 0x178 + 0x20 + + + DCT_DEV8_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC4 + NA + 0x17C + 0x20 + + + DCT_DEV8_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC1 + NA + 0x180 + 0x20 + + + DCT_DEV9_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC2 + NA + 0x184 + 0x20 + + + DCT_DEV9_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC3 + NA + 0x188 + 0x20 + + + DCT_DEV9_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC4 + NA + 0x18C + 0x20 + + + DCT_DEV9_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC1 + NA + 0x190 + 0x20 + + + DCT_DEV10_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC2 + NA + 0x194 + 0x20 + + + DCT_DEV10_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC3 + NA + 0x198 + 0x20 + + + DCT_DEV10_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC4 + NA + 0x19C + 0x20 + + + DCT_DEV10_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC1 + NA + 0x1A0 + 0x20 + + + DCT_DEV11_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC2 + NA + 0x1A4 + 0x20 + + + DCT_DEV11_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC3 + NA + 0x1A8 + 0x20 + + + DCT_DEV11_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC4 + NA + 0x1AC + 0x20 + + + DCT_DEV11_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC1 + NA + 0x1B0 + 0x20 + + + DCT_DEV12_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC2 + NA + 0x1B4 + 0x20 + + + DCT_DEV12_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC3 + NA + 0x1B8 + 0x20 + + + DCT_DEV12_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC4 + NA + 0x1BC + 0x20 + + + DCT_DEV12_LOC4 + NA + 0 + 32 + read-only + + + + + + + I3C_SLV + I3C Controller (Slave) + I3C_SLV + 0x500DB000 + + 0x0 + 0x40 + registers + + + I3C_SLV + 102 + + + + CONFIG + NA + 0x4 + 0x20 + 0x002F0001 + + + SLVENA + 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master + 0 + 1 + read-write + + + NACK + 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. + 1 + 1 + read-write + + + MATCHSS + 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. + 2 + 1 + read-write + + + S0IGNORE + If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. + 3 + 1 + read-write + + + DDROK + NA + 4 + 1 + read-write + + + IDRAND + NA + 8 + 1 + read-write + + + OFFLINE + NA + 9 + 1 + read-write + + + BAMATCH + Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS + 16 + 8 + read-write + + + SADDR + If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. + 25 + 7 + read-write + + + + + STATUS + NA + 0x8 + 0x20 + + + STNOTSTOP + Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. + 0 + 1 + read-only + + + STMSG + Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. + 1 + 1 + read-only + + + STCCCH + Is 1 if a CCC message is being handled automatically. + 2 + 1 + read-only + + + STREQRD + 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, + 3 + 1 + read-only + + + STREQWR + NA + 4 + 1 + read-only + + + STDAA + NA + 5 + 1 + read-only + + + STHDR + NA + 6 + 1 + read-only + + + START + NA + 8 + 1 + read-write + + + MATCHED + NA + 9 + 1 + read-write + + + STOP + NA + 10 + 1 + read-write + + + RXPEND + Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) + 11 + 1 + read-only + + + TXNOTFULL + Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. + 12 + 1 + read-only + + + DACHG + The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. + 13 + 1 + read-write + + + CCC + A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. + 14 + 1 + read-write + + + ERRWARN + NA + 15 + 1 + read-only + + + HDRMATCH + NA + 16 + 1 + read-write + + + + + CTRL + NA + 0xC + 0x20 + + + SLV_EVENT + If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. + 0 + 2 + read-write + + + EXTDATA + reserved + 3 + 1 + read-write + + + MAPIDX + Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. + 4 + 4 + read-write + + + IBIDATA + Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. + 8 + 8 + read-write + + + PENDINT + Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. + 16 + 4 + read-write + + + ACTSTATE + NA + 20 + 2 + read-write + + + VENDINFO + NA + 24 + 8 + read-write + + + + + INTSET + INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) + 0x10 + 0x20 + + + STOP_ENA + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-write + + + RXPEND_ENA + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-write + + + TXSEND_ENA + NA + 12 + 1 + read-write + + + + + INTCLR + NA + 0x14 + 0x20 + + + STOP_CLR + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + write-only + + + RXPEND_CLR + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + write-only + + + TXSEND_CLR + NA + 12 + 1 + write-only + + + + + INTMASKED + NA + 0x18 + 0x20 + + + STOP_MASK + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-only + + + RXPEND_MASK + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-only + + + TXSEND_MASK + NA + 12 + 1 + read-only + + + + + DATACTRL + NA + 0x2C + 0x20 + 0x000000B0 + + + FLUSHTB + Flushes the from-bus buffer/FIFO. Not normally used + 0 + 1 + write-only + + + FLUSHFB + Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely + 1 + 1 + write-only + + + UNLOCK + If this bit is not written 1, the register bits from 7 to 4 are not changed on write. + 3 + 1 + write-only + + + TXTRIG + Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 4 + 2 + read-write + + + RXTRIG + Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 6 + 2 + read-write + + + TXCOUNT + NA + 16 + 5 + read-only + + + RXCOUNT + NA + 24 + 5 + read-only + + + TXFULL + NA + 30 + 1 + read-only + + + RXEMPTY + NA + 31 + 1 + read-only + + + + + WDATAB + NA + 0x30 + 0x20 + + + WDATAB + NA + 0 + 8 + write-only + + + WDATA_END + NA + 8 + 1 + write-only + + + + + WDATABE + NA + 0x34 + 0x20 + + + WDATABE + NA + 0 + 8 + write-only + + + + + RDARAB + Read Byte Data (from-bus) register + 0x40 + 0x20 + + + DATA0 + This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register + 0 + 8 + read-only + + + + + RDATAH + Read Half-word Data (from-bus) register + 0x48 + 0x20 + + + DATA_LSB + NA + 0 + 8 + read-only + + + DATA_MSB + This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register + 8 + 8 + read-only + + + + + CAPABILITIES2 + NA + 0x5C + 0x20 + 0x00000100 + + + CAPABLITIES2 + NA + 0 + 32 + read-only + + + + + CAPABILITIES + NA + 0x60 + 0x20 + 0x7C13FC1C + + + CAPABLITIES + NA + 0 + 32 + read-only + + + + + IDPARTNO + NA + 0x6C + 0x20 + + + PARTNO + NA + 0 + 32 + read-write + + + + + IDEXT + NA + 0x70 + 0x20 + + + IDEXT + NA + 0 + 32 + read-write + + + + + VENDORID + NA + 0x74 + 0x20 + 0x00005550 + + + VID + NA + 0 + 15 + read-write + + + + + + + AXI_ICM + AXI_ICM Peripheral + ICM_AXI + 0x500A4000 + + 0x0 + 0x10 + registers + + + + VERID_FILEDS + NA + 0x0 + 0x20 + 0x3430342A + + + ICM_REG_VERID + NA + 0 + 32 + read-only + + + + + HW_CFG + NA + 0x4 + 0x20 + 0x0070D151 + + + ICM_REG_AXI_HWCFG_QOS_SUPPORT + NA + 0 + 1 + read-only + + + ICM_REG_AXI_HWCFG_APB3_SUPPORT + NA + 1 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI4_SUPPORT + NA + 2 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOCK_EN + NA + 3 + 1 + read-only + + + ICM_REG_AXI_HWCFG_TRUST_ZONE_EN + NA + 4 + 1 + read-only + + + ICM_REG_AXI_HWCFG_DECODER_TYPE + NA + 5 + 1 + read-only + + + ICM_REG_AXI_HWCFG_REMAP_EN + NA + 6 + 1 + read-only + + + ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN + NA + 7 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN + NA + 8 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS + NA + 12 + 5 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES + NA + 20 + 5 + read-only + + + + + CMD + NA + 0x8 + 0x20 + + + ICM_REG_AXI_CMD + NA + 0 + 3 + read-write + + + ICM_REG_RD_WR_CHAN + NA + 7 + 1 + read-write + + + ICM_REG_AXI_MASTER_PORT + NA + 8 + 4 + read-write + + + ICM_REG_AXI_ERR_BIT + NA + 28 + 1 + read-only + + + ICM_REG_AXI_SOFT_RESET_BIT + NA + 29 + 1 + read-write + + + ICM_REG_AXI_RD_WR_CMD + NA + 30 + 1 + read-write + + + ICM_REG_AXI_CMD_EN + NA + 31 + 1 + read-write + + + + + DATA + NA + 0xC + 0x20 + + + ICM_REG_DATA + NA + 0 + 32 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x500E1000 + + 0x0 + 0xE8 + registers + + + + DATE + iomux version + 0x104 + 0x20 + 0x00201222 + + + DATE + csv date + 0 + 28 + read-write + + + + + 54 + 0x4 + 0-53 + GPIO%s + IO_MUX Control Register + 0x4 + 0x20 + read-write + + + MCU_OE + Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable + 0 + 1 + + + SLP_SEL + Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter + 1 + 1 + + + MCU_WPD + Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable + 2 + 1 + + + MCU_WPU + Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable + 3 + 1 + + + MCU_IE + Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable + 4 + 1 + + + MCU_DRV + Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA + 5 + 2 + + + FUN_WPD + Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable + 7 + 1 + + + FUN_WPU + Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable + 8 + 1 + + + FUN_IE + Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable + 9 + 1 + + + FUN_DRV + Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA + 10 + 2 + + + MCU_SEL + Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ...... + 12 + 3 + + + FILTER_EN + Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable + 15 + 1 + + + + + + + ISP + ISP Peripheral + ISP + 0x500A1000 + + 0x0 + 0x244 + registers + + + ISP + 100 + + + + VER_DATE + version control register + 0x0 + 0x20 + 0x20210608 + + + VER_DATA + csv version + 0 + 32 + read-write + + + + + CLK_EN + isp clk control register + 0x4 + 0x20 + + + CLK_EN + this bit configures the clk force on of isp reg. 0: disable, 1: enable + 0 + 1 + read-write + + + CLK_BLC_FORCE_ON + this bit configures the clk force on of blc. 0: disable, 1: enable + 1 + 1 + read-write + + + CLK_DPC_FORCE_ON + this bit configures the clk force on of dpc. 0: disable, 1: enable + 2 + 1 + read-write + + + CLK_BF_FORCE_ON + this bit configures the clk force on of bf. 0: disable, 1: enable + 3 + 1 + read-write + + + CLK_LSC_FORCE_ON + this bit configures the clk force on of lsc. 0: disable, 1: enable + 4 + 1 + read-write + + + CLK_DEMOSAIC_FORCE_ON + this bit configures the clk force on of demosaic. 0: disable, 1: enable + 5 + 1 + read-write + + + CLK_MEDIAN_FORCE_ON + this bit configures the clk force on of median. 0: disable, 1: enable + 6 + 1 + read-write + + + CLK_CCM_FORCE_ON + this bit configures the clk force on of ccm. 0: disable, 1: enable + 7 + 1 + read-write + + + CLK_GAMMA_FORCE_ON + this bit configures the clk force on of gamma. 0: disable, 1: enable + 8 + 1 + read-write + + + CLK_RGB2YUV_FORCE_ON + this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + 9 + 1 + read-write + + + CLK_SHARP_FORCE_ON + this bit configures the clk force on of sharp. 0: disable, 1: enable + 10 + 1 + read-write + + + CLK_COLOR_FORCE_ON + this bit configures the clk force on of color. 0: disable, 1: enable + 11 + 1 + read-write + + + CLK_YUV2RGB_FORCE_ON + this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + 12 + 1 + read-write + + + CLK_AE_FORCE_ON + this bit configures the clk force on of ae. 0: disable, 1: enable + 13 + 1 + read-write + + + CLK_AF_FORCE_ON + this bit configures the clk force on of af. 0: disable, 1: enable + 14 + 1 + read-write + + + CLK_AWB_FORCE_ON + this bit configures the clk force on of awb. 0: disable, 1: enable + 15 + 1 + read-write + + + CLK_HIST_FORCE_ON + this bit configures the clk force on of hist. 0: disable, 1: enable + 16 + 1 + read-write + + + CLK_MIPI_IDI_FORCE_ON + this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + 17 + 1 + read-write + + + ISP_MEM_CLK_FORCE_ON + this bit configures the clk force on of all isp memory. 0: disable, 1: enable + 18 + 1 + read-write + + + + + CNTL + isp module enable control register + 0x8 + 0x20 + 0x40002442 + + + MIPI_DATA_EN + this bit configures mipi input data enable. 0: disable, 1: enable + 0 + 1 + read-write + + + ISP_EN + this bit configures isp global enable. 0: disable, 1: enable + 1 + 1 + read-write + + + BLC_EN + this bit configures blc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_EN + this bit configures dpc enable. 0: disable, 1: enable + 3 + 1 + read-write + + + BF_EN + this bit configures bf enable. 0: disable, 1: enable + 4 + 1 + read-write + + + LSC_EN + this bit configures lsc enable. 0: disable, 1: enable + 5 + 1 + read-write + + + DEMOSAIC_EN + this bit configures demosaic enable. 0: disable, 1: enable + 6 + 1 + read-write + + + MEDIAN_EN + this bit configures median enable. 0: disable, 1: enable + 7 + 1 + read-write + + + CCM_EN + this bit configures ccm enable. 0: disable, 1: enable + 8 + 1 + read-write + + + GAMMA_EN + this bit configures gamma enable. 0: disable, 1: enable + 9 + 1 + read-write + + + RGB2YUV_EN + this bit configures rgb2yuv enable. 0: disable, 1: enable + 10 + 1 + read-write + + + SHARP_EN + this bit configures sharp enable. 0: disable, 1: enable + 11 + 1 + read-write + + + COLOR_EN + this bit configures color enable. 0: disable, 1: enable + 12 + 1 + read-write + + + YUV2RGB_EN + this bit configures yuv2rgb enable. 0: disable, 1: enable + 13 + 1 + read-write + + + AE_EN + this bit configures ae enable. 0: disable, 1: enable + 14 + 1 + read-write + + + AF_EN + this bit configures af enable. 0: disable, 1: enable + 15 + 1 + read-write + + + AWB_EN + this bit configures awb enable. 0: disable, 1: enable + 16 + 1 + read-write + + + HIST_EN + this bit configures hist enable. 0: disable, 1: enable + 17 + 1 + read-write + + + BYTE_ENDIAN_ORDER + select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} + 24 + 1 + read-write + + + ISP_DATA_TYPE + this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + 25 + 2 + read-write + + + ISP_IN_SRC + this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + 27 + 2 + read-write + + + ISP_OUT_TYPE + this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565 + 29 + 3 + read-write + + + + + HSYNC_CNT + header hsync interval control register + 0xC + 0x20 + 0x00000007 + + + HSYNC_CNT + this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp + 0 + 8 + read-write + + + + + FRAME_CFG + frame control parameter register + 0x10 + 0x20 + 0x601E01E0 + + + VADR_NUM + this field configures input image size in y-direction, image row number - 1 + 0 + 12 + read-write + + + HADR_NUM + this field configures input image size in x-direction, image line number - 1 + 12 + 12 + read-write + + + BAYER_MODE + this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB + 27 + 2 + read-write + + + HSYNC_START_EXIST + this bit configures the line end packet exist or not. 0: not exist, 1: exist + 29 + 1 + read-write + + + HSYNC_END_EXIST + this bit configures the line start packet exist or not. 0: not exist, 1: exist + 30 + 1 + read-write + + + + + CCM_COEF0 + ccm coef register 0 + 0x14 + 0x20 + 0x02500740 + + + CCM_RR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_RG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF1 + ccm coef register 1 + 0x18 + 0x20 + 0x022810C0 + + + CCM_RB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GR + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF3 + ccm coef register 3 + 0x1C + 0x20 + 0x02200680 + + + CCM_GG + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GB + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF4 + ccm coef register 4 + 0x20 + 0x20 + 0x02581040 + + + CCM_BR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_BG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF5 + ccm coef register 5 + 0x24 + 0x20 + 0x00000740 + + + CCM_BB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + + + BF_MATRIX_CTRL + bf pix2matrix ctrl + 0x28 + 0x20 + + + BF_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + BF_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + BF_PADDING_DATA + this field configures bf matrix padding data + 16 + 8 + read-write + + + BF_PADDING_MODE + this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + BF_SIGMA + bf denoising level control register + 0x2C + 0x20 + 0x00000002 + + + SIGMA + this field configures the bayer denoising level, valid data from 2 to 20 + 0 + 6 + read-write + + + + + BF_GAU0 + bf gau template register 0 + 0x30 + 0x20 + 0xFFFFFFFF + + + GAU_TEMPLATE21 + this field configures index 21 of gausian template + 0 + 4 + read-write + + + GAU_TEMPLATE20 + this field configures index 20 of gausian template + 4 + 4 + read-write + + + GAU_TEMPLATE12 + this field configures index 12 of gausian template + 8 + 4 + read-write + + + GAU_TEMPLATE11 + this field configures index 11 of gausian template + 12 + 4 + read-write + + + GAU_TEMPLATE10 + this field configures index 10 of gausian template + 16 + 4 + read-write + + + GAU_TEMPLATE02 + this field configures index 02 of gausian template + 20 + 4 + read-write + + + GAU_TEMPLATE01 + this field configures index 01 of gausian template + 24 + 4 + read-write + + + GAU_TEMPLATE00 + this field configures index 00 of gausian template + 28 + 4 + read-write + + + + + BF_GAU1 + bf gau template register 1 + 0x34 + 0x20 + 0x0000000F + + + GAU_TEMPLATE22 + this field configures index 22 of gausian template + 0 + 4 + read-write + + + + + DPC_CTRL + DPC mode control register + 0x38 + 0x20 + 0x00000004 + + + DPC_CHECK_EN + this bit configures the check mode enable. 0: disable, 1: enable + 0 + 1 + read-write + + + STA_EN + this bit configures the sta dpc enable. 0: disable, 1: enable + 1 + 1 + read-write + + + DYN_EN + this bit configures the dyn dpc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_BLACK_EN + this bit configures input image type select when in check mode, 0: white img, 1: black img + 3 + 1 + read-write + + + DPC_METHOD_SEL + this bit configures dyn dpc method select. 0: simple method, 1: hard method + 4 + 1 + read-write + + + DPC_CHECK_OD_EN + this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output + 5 + 1 + read-write + + + + + DPC_CONF + DPC parameter config register + 0x3C + 0x20 + 0x04103030 + + + DPC_THRESHOLD_L + this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 0 + 8 + read-write + + + DPC_THRESHOLD_H + this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 8 + 8 + read-write + + + DPC_FACTOR_DARK + this field configures the dynamic correction method 1 dark factor + 16 + 6 + read-write + + + DPC_FACTOR_BRIG + this field configures the dynamic correction method 1 bright factor + 22 + 6 + read-write + + + + + DPC_MATRIX_CTRL + dpc pix2matrix ctrl + 0x40 + 0x20 + + + DPC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DPC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DPC_PADDING_DATA + this field configures dpc matrix padding data + 16 + 8 + read-write + + + DPC_PADDING_MODE + this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DPC_DEADPIX_CNT + DPC dead-pix number register + 0x44 + 0x20 + + + DPC_DEADPIX_CNT + this field represents the dead pixel count + 0 + 10 + read-only + + + + + LUT_CMD + LUT command register + 0x48 + 0x20 + + + LUT_ADDR + this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b lut, 01 sel r_gr lut + 0 + 12 + write-only + + + LUT_NUM + this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT + 12 + 4 + write-only + + + LUT_CMD + this bit configures the access event of lut. 0:rd 1: wr + 16 + 1 + write-only + + + + + LUT_WDATA + LUT write data register + 0x4C + 0x20 + + + LUT_WDATA + this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register + 0 + 32 + read-write + + + + + LUT_RDATA + LUT read data register + 0x50 + 0x20 + + + LUT_RDATA + this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register + 0 + 32 + read-only + + + + + LSC_TABLESIZE + LSC point in x-direction + 0x54 + 0x20 + 0x0000001F + + + LSC_XTABLESIZE + this field configures lsc table size in x-direction + 0 + 5 + read-write + + + + + DEMOSAIC_MATRIX_CTRL + demosaic pix2matrix ctrl + 0x58 + 0x20 + + + DEMOSAIC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DEMOSAIC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DEMOSAIC_PADDING_DATA + this field configures demosaic matrix padding data + 16 + 8 + read-write + + + DEMOSAIC_PADDING_MODE + this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DEMOSAIC_GRAD_RATIO + demosaic gradient select ratio + 0x5C + 0x20 + 0x00000010 + + + DEMOSAIC_GRAD_RATIO + this field configures demosaic gradient select ratio + 0 + 6 + read-write + + + + + MEDIAN_MATRIX_CTRL + median pix2matrix ctrl + 0x60 + 0x20 + + + MEDIAN_PADDING_DATA + this field configures median matrix padding data + 0 + 8 + read-write + + + MEDIAN_PADDING_MODE + this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 8 + 1 + read-write + + + + + INT_RAW + raw interrupt register + 0x64 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_RAW + the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_RAW + the raw interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_RAW + the raw interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_RAW + the raw interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_RAW + the raw interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_RAW + the raw interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_RAW + the raw interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_RAW + the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256 + 7 + 1 + read-only + + + AE_MONITOR_INT_RAW + the raw interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_RAW + the raw interrupt status of ae. + 9 + 1 + read-only + + + AF_FDONE_INT_RAW + the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done + 10 + 1 + read-only + + + AF_ENV_INT_RAW + the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected + 11 + 1 + read-only + + + AWB_FDONE_INT_RAW + the raw interrupt status of awb. send a int pulse when statistic of one awb frame done + 12 + 1 + read-only + + + HIST_FDONE_INT_RAW + the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done + 13 + 1 + read-only + + + FRAME_INT_RAW + the raw interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_RAW + the raw interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_RAW + the raw interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_RAW + the raw interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_RAW + the raw interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_RAW + the raw interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_RAW + the raw interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_RAW + the raw interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_RAW + the raw interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_RAW + the raw interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_RAW + the raw interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_RAW + the raw interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_RAW + the raw interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_RAW + the raw interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_RAW + the raw interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x68 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_ST + the masked interrupt status of input data type error + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_ST + the masked interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_ST + the masked interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_ST + the masked interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_ST + the masked interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_ST + the masked interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_ST + the masked interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_ST + the masked interrupt status of gamma setting error + 7 + 1 + read-only + + + AE_MONITOR_INT_ST + the masked interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_ST + the masked interrupt status of ae + 9 + 1 + read-only + + + AF_FDONE_INT_ST + the masked interrupt status of af statistic + 10 + 1 + read-only + + + AF_ENV_INT_ST + the masked interrupt status of af monitor + 11 + 1 + read-only + + + AWB_FDONE_INT_ST + the masked interrupt status of awb + 12 + 1 + read-only + + + HIST_FDONE_INT_ST + the masked interrupt status of histogram + 13 + 1 + read-only + + + FRAME_INT_ST + the masked interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_ST + the masked interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_ST + the masked interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_ST + the masked interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_ST + the masked interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_ST + the masked interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_ST + the masked interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_ST + the masked interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_ST + the masked interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_ST + the masked interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_ST + the masked interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_ST + the masked interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_ST + the masked interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_ST + the masked interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_ST + the masked interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x6C + 0x20 + 0x000000C3 + + + ISP_DATA_TYPE_ERR_INT_ENA + write 1 to enable input data type error + 0 + 1 + read-write + + + ISP_ASYNC_FIFO_OVF_INT_ENA + write 1 to enable isp input fifo overflow + 1 + 1 + read-write + + + ISP_BUF_FULL_INT_ENA + write 1 to enable isp input buffer full + 2 + 1 + read-write + + + ISP_HVNUM_SETTING_ERR_INT_ENA + write 1 to enable hnum and vnum setting format error + 3 + 1 + read-write + + + ISP_DATA_TYPE_SETTING_ERR_INT_ENA + write 1 to enable setting invalid reg_data_type + 4 + 1 + read-write + + + ISP_MIPI_HNUM_UNMATCH_INT_ENA + write 1 to enable hnum setting unmatch with mipi input + 5 + 1 + read-write + + + DPC_CHECK_DONE_INT_ENA + write 1 to enable dpc check done + 6 + 1 + read-write + + + GAMMA_XCOORD_ERR_INT_ENA + write 1 to enable gamma setting error + 7 + 1 + read-write + + + AE_MONITOR_INT_ENA + write 1 to enable ae monitor + 8 + 1 + read-write + + + AE_FRAME_DONE_INT_ENA + write 1 to enable ae + 9 + 1 + read-write + + + AF_FDONE_INT_ENA + write 1 to enable af statistic + 10 + 1 + read-write + + + AF_ENV_INT_ENA + write 1 to enable af monitor + 11 + 1 + read-write + + + AWB_FDONE_INT_ENA + write 1 to enable awb + 12 + 1 + read-write + + + HIST_FDONE_INT_ENA + write 1 to enable histogram + 13 + 1 + read-write + + + FRAME_INT_ENA + write 1 to enable isp frame end + 14 + 1 + read-write + + + BLC_FRAME_INT_ENA + write 1 to enable blc frame done + 15 + 1 + read-write + + + LSC_FRAME_INT_ENA + write 1 to enable lsc frame done + 16 + 1 + read-write + + + DPC_FRAME_INT_ENA + write 1 to enable dpc frame done + 17 + 1 + read-write + + + BF_FRAME_INT_ENA + write 1 to enable bf frame done + 18 + 1 + read-write + + + DEMOSAIC_FRAME_INT_ENA + write 1 to enable demosaic frame done + 19 + 1 + read-write + + + MEDIAN_FRAME_INT_ENA + write 1 to enable median frame done + 20 + 1 + read-write + + + CCM_FRAME_INT_ENA + write 1 to enable ccm frame done + 21 + 1 + read-write + + + GAMMA_FRAME_INT_ENA + write 1 to enable gamma frame done + 22 + 1 + read-write + + + RGB2YUV_FRAME_INT_ENA + write 1 to enable rgb2yuv frame done + 23 + 1 + read-write + + + SHARP_FRAME_INT_ENA + write 1 to enable sharp frame done + 24 + 1 + read-write + + + COLOR_FRAME_INT_ENA + write 1 to enable color frame done + 25 + 1 + read-write + + + YUV2RGB_FRAME_INT_ENA + write 1 to enable yuv2rgb frame done + 26 + 1 + read-write + + + TAIL_IDI_FRAME_INT_ENA + write 1 to enable isp_tail idi frame_end + 27 + 1 + read-write + + + HEADER_IDI_FRAME_INT_ENA + write 1 to enable real input frame end of isp_input + 28 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x70 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_CLR + write 1 to clear input data type error + 0 + 1 + write-only + + + ISP_ASYNC_FIFO_OVF_INT_CLR + write 1 to clear isp input fifo overflow + 1 + 1 + write-only + + + ISP_BUF_FULL_INT_CLR + write 1 to clear isp input buffer full + 2 + 1 + write-only + + + ISP_HVNUM_SETTING_ERR_INT_CLR + write 1 to clear hnum and vnum setting format error + 3 + 1 + write-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_CLR + write 1 to clear setting invalid reg_data_type + 4 + 1 + write-only + + + ISP_MIPI_HNUM_UNMATCH_INT_CLR + write 1 to clear hnum setting unmatch with mipi input + 5 + 1 + write-only + + + DPC_CHECK_DONE_INT_CLR + write 1 to clear dpc check done + 6 + 1 + write-only + + + GAMMA_XCOORD_ERR_INT_CLR + write 1 to clear gamma setting error + 7 + 1 + write-only + + + AE_MONITOR_INT_CLR + write 1 to clear ae monitor + 8 + 1 + write-only + + + AE_FRAME_DONE_INT_CLR + write 1 to clear ae + 9 + 1 + write-only + + + AF_FDONE_INT_CLR + write 1 to clear af statistic + 10 + 1 + write-only + + + AF_ENV_INT_CLR + write 1 to clear af monitor + 11 + 1 + write-only + + + AWB_FDONE_INT_CLR + write 1 to clear awb + 12 + 1 + write-only + + + HIST_FDONE_INT_CLR + write 1 to clear histogram + 13 + 1 + write-only + + + FRAME_INT_CLR + write 1 to clear isp frame end + 14 + 1 + write-only + + + BLC_FRAME_INT_CLR + write 1 to clear blc frame done + 15 + 1 + write-only + + + LSC_FRAME_INT_CLR + write 1 to clear lsc frame done + 16 + 1 + write-only + + + DPC_FRAME_INT_CLR + write 1 to clear dpc frame done + 17 + 1 + write-only + + + BF_FRAME_INT_CLR + write 1 to clear bf frame done + 18 + 1 + write-only + + + DEMOSAIC_FRAME_INT_CLR + write 1 to clear demosaic frame done + 19 + 1 + write-only + + + MEDIAN_FRAME_INT_CLR + write 1 to clear median frame done + 20 + 1 + write-only + + + CCM_FRAME_INT_CLR + write 1 to clear ccm frame done + 21 + 1 + write-only + + + GAMMA_FRAME_INT_CLR + write 1 to clear gamma frame done + 22 + 1 + write-only + + + RGB2YUV_FRAME_INT_CLR + write 1 to clear rgb2yuv frame done + 23 + 1 + write-only + + + SHARP_FRAME_INT_CLR + write 1 to clear sharp frame done + 24 + 1 + write-only + + + COLOR_FRAME_INT_CLR + write 1 to clear color frame done + 25 + 1 + write-only + + + YUV2RGB_FRAME_INT_CLR + write 1 to clear yuv2rgb frame done + 26 + 1 + write-only + + + TAIL_IDI_FRAME_INT_CLR + write 1 to clear isp_tail idi frame_end + 27 + 1 + write-only + + + HEADER_IDI_FRAME_INT_CLR + write 1 to clear real input frame end of isp_input + 28 + 1 + write-only + + + + + GAMMA_CTRL + gamma control register + 0x74 + 0x20 + 0x0000000E + + + GAMMA_UPDATE + Indicates that gamma register configuration is complete + 0 + 1 + read-write + + + GAMMA_B_LAST_CORRECT + this bit configures enable of last b segment correcction. 0: disable, 1: enable + 1 + 1 + read-write + + + GAMMA_G_LAST_CORRECT + this bit configures enable of last g segment correcction. 0: disable, 1: enable + 2 + 1 + read-write + + + GAMMA_R_LAST_CORRECT + this bit configures enable of last r segment correcction. 0: disable, 1: enable + 3 + 1 + read-write + + + + + GAMMA_RY1 + point of Y-axis of r channel gamma curve register 1 + 0x78 + 0x20 + 0x10203040 + + + GAMMA_R_Y03 + this field configures the point 3 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y02 + this field configures the point 2 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y01 + this field configures the point 1 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y00 + this field configures the point 0 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY2 + point of Y-axis of r channel gamma curve register 2 + 0x7C + 0x20 + 0x50607080 + + + GAMMA_R_Y07 + this field configures the point 7 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y06 + this field configures the point 6 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y05 + this field configures the point 5 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y04 + this field configures the point 4 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY3 + point of Y-axis of r channel gamma curve register 3 + 0x80 + 0x20 + 0x90A0B0C0 + + + GAMMA_R_Y0B + this field configures the point 11 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0A + this field configures the point 10 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y09 + this field configures the point 9 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y08 + this field configures the point 8 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY4 + point of Y-axis of r channel gamma curve register 4 + 0x84 + 0x20 + 0xD0E0F0FF + + + GAMMA_R_Y0F + this field configures the point 15 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0E + this field configures the point 14 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y0D + this field configures the point 13 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y0C + this field configures the point 12 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY1 + point of Y-axis of g channel gamma curve register 1 + 0x88 + 0x20 + 0x10203040 + + + GAMMA_G_Y03 + this field configures the point 3 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y02 + this field configures the point 2 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y01 + this field configures the point 1 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y00 + this field configures the point 0 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY2 + point of Y-axis of g channel gamma curve register 2 + 0x8C + 0x20 + 0x50607080 + + + GAMMA_G_Y07 + this field configures the point 7 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y06 + this field configures the point 6 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y05 + this field configures the point 5 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y04 + this field configures the point 4 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY3 + point of Y-axis of g channel gamma curve register 3 + 0x90 + 0x20 + 0x90A0B0C0 + + + GAMMA_G_Y0B + this field configures the point 11 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0A + this field configures the point 10 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y09 + this field configures the point 9 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y08 + this field configures the point 8 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY4 + point of Y-axis of g channel gamma curve register 4 + 0x94 + 0x20 + 0xD0E0F0FF + + + GAMMA_G_Y0F + this field configures the point 15 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0E + this field configures the point 14 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y0D + this field configures the point 13 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y0C + this field configures the point 12 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY1 + point of Y-axis of b channel gamma curve register 1 + 0x98 + 0x20 + 0x10203040 + + + GAMMA_B_Y03 + this field configures the point 3 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y02 + this field configures the point 2 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y01 + this field configures the point 1 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y00 + this field configures the point 0 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY2 + point of Y-axis of b channel gamma curve register 2 + 0x9C + 0x20 + 0x50607080 + + + GAMMA_B_Y07 + this field configures the point 7 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y06 + this field configures the point 6 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y05 + this field configures the point 5 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y04 + this field configures the point 4 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY3 + point of Y-axis of b channel gamma curve register 3 + 0xA0 + 0x20 + 0x90A0B0C0 + + + GAMMA_B_Y0B + this field configures the point 11 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0A + this field configures the point 10 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y09 + this field configures the point 9 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y08 + this field configures the point 8 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY4 + point of Y-axis of b channel gamma curve register 4 + 0xA4 + 0x20 + 0xD0E0F0FF + + + GAMMA_B_Y0F + this field configures the point 15 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0E + this field configures the point 14 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y0D + this field configures the point 13 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y0C + this field configures the point 12 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RX1 + point of X-axis of r channel gamma curve register 1 + 0xA8 + 0x20 + 0x00924924 + + + GAMMA_R_X07 + this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X06 + this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X05 + this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X04 + this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X03 + this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X02 + this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X01 + this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X00 + this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_RX2 + point of X-axis of r channel gamma curve register 2 + 0xAC + 0x20 + 0x00924924 + + + GAMMA_R_X0F + this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X0E + this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X0D + this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X0C + this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X0B + this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X0A + this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X09 + this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X08 + this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX1 + point of X-axis of g channel gamma curve register 1 + 0xB0 + 0x20 + 0x00924924 + + + GAMMA_G_X07 + this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X06 + this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X05 + this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X04 + this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X03 + this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X02 + this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X01 + this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X00 + this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX2 + point of X-axis of g channel gamma curve register 2 + 0xB4 + 0x20 + 0x00924924 + + + GAMMA_G_X0F + this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X0E + this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X0D + this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X0C + this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X0B + this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X0A + this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X09 + this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X08 + this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX1 + point of X-axis of b channel gamma curve register 1 + 0xB8 + 0x20 + 0x00924924 + + + GAMMA_B_X07 + this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X06 + this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X05 + this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X04 + this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X03 + this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X02 + this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X01 + this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X00 + this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX2 + point of X-axis of b channel gamma curve register 2 + 0xBC + 0x20 + 0x00924924 + + + GAMMA_B_X0F + this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X0E + this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X0D + this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X0C + this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X0B + this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X0A + this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X09 + this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X08 + this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + AE_CTRL + ae control register + 0xC0 + 0x20 + + + AE_UPDATE + write 1 to this bit triggers one statistic event + 0 + 1 + write-only + + + AE_SELECT + this field configures ae input data source, 0: data from median, 1: data from gama + 1 + 1 + read-write + + + + + AE_MONITOR + ae monitor control register + 0xC4 + 0x20 + + + TL + this field configures the lower lum threshold of ae monitor + 0 + 8 + read-write + + + TH + this field configures the higher lum threshold of ae monitor + 8 + 8 + read-write + + + PERIOD + this field cnfigures ae monitor frame period + 16 + 6 + read-write + + + + + AE_BX + ae window register in x-direction + 0xC8 + 0x20 + 0x00000180 + + + AE_X_BSIZE + this field configures every block x size + 0 + 11 + read-write + + + AE_X_START + this field configures first block start x address + 11 + 11 + read-write + + + + + AE_BY + ae window register in y-direction + 0xCC + 0x20 + 0x000000D8 + + + AE_Y_BSIZE + this field configures every block y size + 0 + 11 + read-write + + + AE_Y_START + this field configures first block start y address + 11 + 11 + read-write + + + + + AE_WINPIXNUM + ae sub-window pix num register + 0xD0 + 0x20 + 0x00014400 + + + AE_SUBWIN_PIXNUM + this field configures the pixel number of each sub win + 0 + 17 + read-write + + + + + AE_WIN_RECIPROCAL + reciprocal of ae sub-window pixel number + 0xD4 + 0x20 + + + AE_SUBWIN_RECIP + this field configures the reciprocal of each subwin_pixnum, 20bit fraction + 0 + 20 + read-write + + + + + AE_BLOCK_MEAN_0 + ae statistic result register 0 + 0xD8 + 0x20 + + + AE_B03_MEAN + this field configures block03 Y mean data + 0 + 8 + read-only + + + AE_B02_MEAN + this field configures block02 Y mean data + 8 + 8 + read-only + + + AE_B01_MEAN + this field configures block01 Y mean data + 16 + 8 + read-only + + + AE_B00_MEAN + this field configures block00 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_1 + ae statistic result register 1 + 0xDC + 0x20 + + + AE_B12_MEAN + this field configures block12 Y mean data + 0 + 8 + read-only + + + AE_B11_MEAN + this field configures block11 Y mean data + 8 + 8 + read-only + + + AE_B10_MEAN + this field configures block10 Y mean data + 16 + 8 + read-only + + + AE_B04_MEAN + this field configures block04 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_2 + ae statistic result register 2 + 0xE0 + 0x20 + + + AE_B21_MEAN + this field configures block21 Y mean data + 0 + 8 + read-only + + + AE_B20_MEAN + this field configures block20 Y mean data + 8 + 8 + read-only + + + AE_B14_MEAN + this field configures block14 Y mean data + 16 + 8 + read-only + + + AE_B13_MEAN + this field configures block13 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_3 + ae statistic result register 3 + 0xE4 + 0x20 + + + AE_B30_MEAN + this field configures block30 Y mean data + 0 + 8 + read-only + + + AE_B24_MEAN + this field configures block24 Y mean data + 8 + 8 + read-only + + + AE_B23_MEAN + this field configures block23 Y mean data + 16 + 8 + read-only + + + AE_B22_MEAN + this field configures block22 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_4 + ae statistic result register 4 + 0xE8 + 0x20 + + + AE_B34_MEAN + this field configures block34 Y mean data + 0 + 8 + read-only + + + AE_B33_MEAN + this field configures block33 Y mean data + 8 + 8 + read-only + + + AE_B32_MEAN + this field configures block32 Y mean data + 16 + 8 + read-only + + + AE_B31_MEAN + this field configures block31 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_5 + ae statistic result register 5 + 0xEC + 0x20 + + + AE_B43_MEAN + this field configures block43 Y mean data + 0 + 8 + read-only + + + AE_B42_MEAN + this field configures block42 Y mean data + 8 + 8 + read-only + + + AE_B41_MEAN + this field configures block41 Y mean data + 16 + 8 + read-only + + + AE_B40_MEAN + this field configures block40 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_6 + ae statistic result register 6 + 0xF0 + 0x20 + + + AE_B44_MEAN + this field configures block44 Y mean data + 24 + 8 + read-only + + + + + SHARP_CTRL0 + sharp control register 0 + 0xF4 + 0x20 + + + SHARP_THRESHOLD_LOW + this field configures sharpen threshold for detail + 0 + 8 + read-write + + + SHARP_THRESHOLD_HIGH + this field configures sharpen threshold for edge + 8 + 8 + read-write + + + SHARP_AMOUNT_LOW + this field configures sharpen amount for detail + 16 + 8 + read-write + + + SHARP_AMOUNT_HIGH + this field configures sharpen amount for edge + 24 + 8 + read-write + + + + + SHARP_FILTER0 + sharp usm config register 0 + 0xF8 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE00 + this field configures unsharp masking(usm) filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE01 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE02 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER1 + sharp usm config register 1 + 0xFC + 0x20 + 0x00000882 + + + SHARP_FILTER_COE10 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE11 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE12 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER2 + sharp usm config register 2 + 0x100 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE20 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE21 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE22 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_MATRIX_CTRL + sharp pix2matrix ctrl + 0x104 + 0x20 + + + SHARP_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + SHARP_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + SHARP_PADDING_DATA + this field configures sharp padding data + 16 + 8 + read-write + + + SHARP_PADDING_MODE + this field configures sharp padding mode + 24 + 1 + read-write + + + + + SHARP_CTRL1 + sharp control register 1 + 0x108 + 0x20 + + + SHARP_GRADIENT_MAX + this field configures sharp max gradient, refresh at the end of each frame end + 0 + 8 + read-only + + + + + DMA_CNTL + isp dma source trans control register + 0x10C + 0x20 + 0x001080A8 + + + DMA_EN + write 1 to triger dma to get 1 frame + 0 + 1 + write-only + + + DMA_UPDATE + write 1 to update reg_dma_burst_len & reg_dma_data_type + 1 + 1 + read-write + + + DMA_DATA_TYPE + this field configures the idi data type for image data + 2 + 6 + read-write + + + DMA_BURST_LEN + this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer + 8 + 12 + read-write + + + DMA_INTERVAL + this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + 20 + 12 + read-write + + + + + DMA_RAW_DATA + isp dma source total raw number set register + 0x110 + 0x20 + + + DMA_RAW_NUM_TOTAL + this field configures the the number of 64bits in a frame + 0 + 22 + read-write + + + DMA_RAW_NUM_TOTAL_SET + write 1 to update reg_dma_raw_num_total + 31 + 1 + write-only + + + + + CAM_CNTL + isp cam source control register + 0x114 + 0x20 + 0x00000004 + + + CAM_EN + write 1 to start recive camera data, write 0 to disable + 0 + 1 + read-write + + + CAM_UPDATE + write 1 to update ISP_CAM_CONF + 1 + 1 + read-write + + + CAM_RESET + this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + 2 + 1 + read-write + + + CAM_CLK_INV + this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk + 3 + 1 + read-write + + + + + CAM_CONF + isp cam source config register + 0x118 + 0x20 + 0x000000A8 + + + CAM_DATA_ORDER + this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], cam_data_in[15:8]} + 0 + 1 + read-write + + + CAM_2BYTE_MODE + this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable + 1 + 1 + read-write + + + CAM_DATA_TYPE + this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12 + 2 + 6 + read-write + + + CAM_DE_INV + this bit configures cam data enable invert. 0: not invert, 1: invert + 8 + 1 + read-write + + + CAM_HSYNC_INV + this bit configures cam hsync invert. 0: not invert, 1: invert + 9 + 1 + read-write + + + CAM_VSYNC_INV + this bit configures cam vsync invert. 0: not invert, 1: invert + 10 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + this bit configures the number of clock of vsync filter length + 11 + 3 + read-write + + + CAM_VSYNC_FILTER_EN + this bit configures vsync filter en + 14 + 1 + read-write + + + + + AF_CTRL0 + af control register 0 + 0x11C + 0x20 + + + AF_AUTO_UPDATE + this bit configures auto_update enable. when set to 1, will update sum and lum each frame + 0 + 1 + read-write + + + AF_MANUAL_UPDATE + write 1 to this bit will update the sum and lum once + 4 + 1 + write-only + + + AF_ENV_THRESHOLD + this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional + 8 + 4 + read-write + + + AF_ENV_PERIOD + this field configures environment changes detection period (frame). When set to 0, disable this function + 16 + 8 + read-write + + + + + AF_CTRL1 + af control register 1 + 0x120 + 0x20 + + + AF_THPIXNUM + this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation + 0 + 22 + read-write + + + + + AF_GEN_TH_CTRL + af gen threshold control register + 0x124 + 0x20 + 0x04400080 + + + AF_GEN_THRESHOLD_MIN + this field configures min threshold when use auto_threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD_MAX + this field configures max threshold when use auto_threshold + 16 + 16 + read-write + + + + + AF_ENV_USER_TH_SUM + af monitor user sum threshold register + 0x128 + 0x20 + + + AF_ENV_USER_THRESHOLD_SUM + this field configures user setup env detect sum threshold + 0 + 32 + read-write + + + + + AF_ENV_USER_TH_LUM + af monitor user lum threshold register + 0x12C + 0x20 + + + AF_ENV_USER_THRESHOLD_LUM + this field configures user setup env detect lum threshold + 0 + 30 + read-write + + + + + AF_THRESHOLD + af threshold register + 0x130 + 0x20 + 0x00000100 + + + AF_THRESHOLD + this field configures user threshold. When set to non-zero, autofocus will use this threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD + this field represents the last calculated threshold + 16 + 16 + read-only + + + + + AF_HSCALE_A + h-scale of af window a register + 0x134 + 0x20 + 0x00010080 + + + AF_RPOINT_A + this field configures left coordinate of focus window a, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_A + this field configures top coordinate of focus window a, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_A + v-scale of af window a register + 0x138 + 0x20 + 0x00010080 + + + AF_BPOINT_A + this field configures right coordinate of focus window a, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_A + this field configures bottom coordinate of focus window a, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_B + h-scale of af window b register + 0x13C + 0x20 + 0x00010080 + + + AF_RPOINT_B + this field configures left coordinate of focus window b, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_B + this field configures top coordinate of focus window b, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_B + v-scale of af window b register + 0x140 + 0x20 + 0x00010080 + + + AF_BPOINT_B + this field configures right coordinate of focus window b, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_B + this field configures bottom coordinate of focus window b, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_C + v-scale of af window c register + 0x144 + 0x20 + 0x00010080 + + + AF_RPOINT_C + this field configures left coordinate of focus window c, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_C + this field configures top coordinate of focus window c, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_C + v-scale of af window c register + 0x148 + 0x20 + 0x00010080 + + + AF_BPOINT_C + this field configures right coordinate of focus window c, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_C + this field configures bottom coordinate of focus window c, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_SUM_A + result of sum of af window a + 0x14C + 0x20 + + + AF_SUMA + this field represents the result of accumulation of pix grad of focus window a + 0 + 30 + read-only + + + + + AF_SUM_B + result of sum of af window b + 0x150 + 0x20 + + + AF_SUMB + this field represents the result of accumulation of pix grad of focus window b + 0 + 30 + read-only + + + + + AF_SUM_C + result of sum of af window c + 0x154 + 0x20 + + + AF_SUMC + this field represents the result of accumulation of pix grad of focus window c + 0 + 30 + read-only + + + + + AF_LUM_A + result of lum of af window a + 0x158 + 0x20 + + + AF_LUMA + this field represents the result of accumulation of pix light of focus window a + 0 + 28 + read-only + + + + + AF_LUM_B + result of lum of af window b + 0x15C + 0x20 + + + AF_LUMB + this field represents the result of accumulation of pix light of focus window b + 0 + 28 + read-only + + + + + AF_LUM_C + result of lum of af window c + 0x160 + 0x20 + + + AF_LUMC + this field represents the result of accumulation of pix light of focus window c + 0 + 28 + read-only + + + + + AWB_MODE + awb mode control register + 0x164 + 0x20 + 0x00000003 + + + AWB_MODE + this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 + 0 + 2 + read-write + + + AWB_SAMPLE + this bit configures awb sample location, 0:before ccm, 1:after ccm + 4 + 1 + read-write + + + + + AWB_HSCALE + h-scale of awb window + 0x168 + 0x20 + 0x0000077F + + + AWB_RPOINT + this field configures awb window right coordinate + 0 + 12 + read-write + + + AWB_LPOINT + this field configures awb window left coordinate + 16 + 12 + read-write + + + + + AWB_VSCALE + v-scale of awb window + 0x16C + 0x20 + 0x00000437 + + + AWB_BPOINT + this field configures awb window bottom coordinate + 0 + 12 + read-write + + + AWB_TPOINT + this field configures awb window top coordinate + 16 + 12 + read-write + + + + + AWB_TH_LUM + awb lum threshold register + 0x170 + 0x20 + 0x02FD0000 + + + AWB_MIN_LUM + this field configures lower threshold of r+g+b + 0 + 10 + read-write + + + AWB_MAX_LUM + this field configures upper threshold of r+g+b + 16 + 10 + read-write + + + + + AWB_TH_RG + awb r/g threshold register + 0x174 + 0x20 + 0x03FF0000 + + + AWB_MIN_RG + this field configures lower threshold of r/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_RG + this field configures upper threshold of r/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB_TH_BG + awb b/g threshold register + 0x178 + 0x20 + 0x03FF0000 + + + AWB_MIN_BG + this field configures lower threshold of b/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_BG + this field configures upper threshold of b/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB0_WHITE_CNT + result of awb white point number + 0x17C + 0x20 + + + AWB0_WHITE_CNT + this field configures number of white point detected of algo0 + 0 + 24 + read-only + + + + + AWB0_ACC_R + result of accumulate of r channel of all white points + 0x180 + 0x20 + + + AWB0_ACC_R + this field represents accumulate of channel r of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_G + result of accumulate of g channel of all white points + 0x184 + 0x20 + + + AWB0_ACC_G + this field represents accumulate of channel g of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_B + result of accumulate of b channel of all white points + 0x188 + 0x20 + + + AWB0_ACC_B + this field represents accumulate of channel b of all white point of algo0 + 0 + 32 + read-only + + + + + COLOR_CTRL + color control register + 0x18C + 0x20 + 0x00800080 + + + COLOR_SATURATION + this field configures the color saturation value + 0 + 8 + read-write + + + COLOR_HUE + this field configures the color hue angle + 8 + 8 + read-write + + + COLOR_CONTRAST + this field configures the color contrast value + 16 + 8 + read-write + + + COLOR_BRIGHTNESS + this field configures the color brightness value, signed 2's complement + 24 + 8 + read-write + + + + + BLC_VALUE + blc black level register + 0x190 + 0x20 + + + BLC_R3_VALUE + this field configures the black level of bottom right channel of bayer img + 0 + 8 + read-write + + + BLC_R2_VALUE + this field configures the black level of bottom left channel of bayer img + 8 + 8 + read-write + + + BLC_R1_VALUE + this field configures the black level of top right channel of bayer img + 16 + 8 + read-write + + + BLC_R0_VALUE + this field configures the black level of top left channel of bayer img + 24 + 8 + read-write + + + + + BLC_CTRL0 + blc stretch control register + 0x194 + 0x20 + + + BLC_R3_STRETCH + this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable + 0 + 1 + read-write + + + BLC_R2_STRETCH + this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable + 1 + 1 + read-write + + + BLC_R1_STRETCH + this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable + 2 + 1 + read-write + + + BLC_R0_STRETCH + this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable + 3 + 1 + read-write + + + + + BLC_CTRL1 + blc window control register + 0x198 + 0x20 + + + BLC_WINDOW_TOP + this field configures blc average calculation window top + 0 + 11 + read-write + + + BLC_WINDOW_LEFT + this field configures blc average calculation window left + 11 + 11 + read-write + + + BLC_WINDOW_VNUM + this field configures blc average calculation window vnum + 22 + 4 + read-write + + + BLC_WINDOW_HNUM + this field configures blc average calculation window hnum + 26 + 4 + read-write + + + BLC_FILTER_EN + this bit configures enable blc average input filter. 0: disable, 1: enable + 30 + 1 + read-write + + + + + BLC_CTRL2 + blc black threshold control register + 0x19C + 0x20 + + + BLC_R3_TH + this field configures black threshold when get blc average of bottom right channel + 0 + 8 + read-write + + + BLC_R2_TH + this field configures black threshold when get blc average of bottom left channel + 8 + 8 + read-write + + + BLC_R1_TH + this field configures black threshold when get blc average of top right channel + 16 + 8 + read-write + + + BLC_R0_TH + this field configures black threshold when get blc average of top left channel + 24 + 8 + read-write + + + + + BLC_MEAN + results of the average of black window + 0x1A0 + 0x20 + + + BLC_R3_MEAN + this field represents the average black value of bottom right channel + 0 + 8 + read-only + + + BLC_R2_MEAN + this field represents the average black value of bottom left channel + 8 + 8 + read-only + + + BLC_R1_MEAN + this field represents the average black value of top right channel + 16 + 8 + read-only + + + BLC_R0_MEAN + this field represents the average black value of top left channel + 24 + 8 + read-only + + + + + HIST_MODE + histogram mode control register + 0x1A4 + 0x20 + 0x00000004 + + + HIST_MODE + this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + 0 + 3 + read-write + + + + + HIST_COEFF + histogram rgb to gray coefficients register + 0x1A8 + 0x20 + 0x00555555 + + + B + this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 0 + 8 + read-write + + + G + this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 8 + 8 + read-write + + + R + this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 16 + 8 + read-write + + + + + HIST_OFFS + histogram window offsets register + 0x1AC + 0x20 + + + HIST_Y_OFFS + this field configures y coordinate of first window + 0 + 12 + read-write + + + HIST_X_OFFS + this field configures x coordinate of first window + 16 + 12 + read-write + + + + + HIST_SIZE + histogram sub-window size register + 0x1B0 + 0x20 + 0x00120020 + + + HIST_Y_SIZE + this field configures y direction size of subwindow + 0 + 9 + read-write + + + HIST_X_SIZE + this field configures x direction size of subwindow + 16 + 9 + read-write + + + + + HIST_SEG0 + histogram bin control register 0 + 0x1B4 + 0x20 + 0x10203040 + + + HIST_SEG_3_4 + this field configures threshold of histogram bin 3 and bin 4 + 0 + 8 + read-write + + + HIST_SEG_2_3 + this field configures threshold of histogram bin 2 and bin 3 + 8 + 8 + read-write + + + HIST_SEG_1_2 + this field configures threshold of histogram bin 1 and bin 2 + 16 + 8 + read-write + + + HIST_SEG_0_1 + this field configures threshold of histogram bin 0 and bin 1 + 24 + 8 + read-write + + + + + HIST_SEG1 + histogram bin control register 1 + 0x1B8 + 0x20 + 0x50607080 + + + HIST_SEG_7_8 + this field configures threshold of histogram bin 7 and bin 8 + 0 + 8 + read-write + + + HIST_SEG_6_7 + this field configures threshold of histogram bin 6 and bin 7 + 8 + 8 + read-write + + + HIST_SEG_5_6 + this field configures threshold of histogram bin 5 and bin 6 + 16 + 8 + read-write + + + HIST_SEG_4_5 + this field configures threshold of histogram bin 4 and bin 5 + 24 + 8 + read-write + + + + + HIST_SEG2 + histogram bin control register 2 + 0x1BC + 0x20 + 0x90A0B0C0 + + + HIST_SEG_11_12 + this field configures threshold of histogram bin 11 and bin 12 + 0 + 8 + read-write + + + HIST_SEG_10_11 + this field configures threshold of histogram bin 10 and bin 11 + 8 + 8 + read-write + + + HIST_SEG_9_10 + this field configures threshold of histogram bin 9 and bin 10 + 16 + 8 + read-write + + + HIST_SEG_8_9 + this field configures threshold of histogram bin 8 and bin 9 + 24 + 8 + read-write + + + + + HIST_SEG3 + histogram bin control register 3 + 0x1C0 + 0x20 + 0x00D0E0F0 + + + HIST_SEG_14_15 + this field configures threshold of histogram bin 14 and bin 15 + 0 + 8 + read-write + + + HIST_SEG_13_14 + this field configures threshold of histogram bin 13 and bin 14 + 8 + 8 + read-write + + + HIST_SEG_12_13 + this field configures threshold of histogram bin 12 and bin 13 + 16 + 8 + read-write + + + + + HIST_WEIGHT0 + histogram sub-window weight register 0 + 0x1C4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_03 + this field configures weight of subwindow 03 + 0 + 8 + read-write + + + HIST_WEIGHT_02 + this field configures weight of subwindow 02 + 8 + 8 + read-write + + + HIST_WEIGHT_01 + this field configures weight of subwindow 01 + 16 + 8 + read-write + + + HIST_WEIGHT_00 + this field configures weight of subwindow 00 and sum of all weight should be 256 + 24 + 8 + read-write + + + + + HIST_WEIGHT1 + histogram sub-window weight register 1 + 0x1C8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_12 + this field configures weight of subwindow 12 + 0 + 8 + read-write + + + HIST_WEIGHT_11 + this field configures weight of subwindow 11 + 8 + 8 + read-write + + + HIST_WEIGHT_10 + this field configures weight of subwindow 10 + 16 + 8 + read-write + + + HIST_WEIGHT_04 + this field configures weight of subwindow 04 + 24 + 8 + read-write + + + + + HIST_WEIGHT2 + histogram sub-window weight register 2 + 0x1CC + 0x20 + 0x01010101 + + + HIST_WEIGHT_21 + this field configures weight of subwindow 21 + 0 + 8 + read-write + + + HIST_WEIGHT_20 + this field configures weight of subwindow 20 + 8 + 8 + read-write + + + HIST_WEIGHT_14 + this field configures weight of subwindow 04 + 16 + 8 + read-write + + + HIST_WEIGHT_13 + this field configures weight of subwindow 13 + 24 + 8 + read-write + + + + + HIST_WEIGHT3 + histogram sub-window weight register 3 + 0x1D0 + 0x20 + 0xE8010101 + + + HIST_WEIGHT_30 + this field configures weight of subwindow 30 + 0 + 8 + read-write + + + HIST_WEIGHT_24 + this field configures weight of subwindow 24 + 8 + 8 + read-write + + + HIST_WEIGHT_23 + this field configures weight of subwindow 23 + 16 + 8 + read-write + + + HIST_WEIGHT_22 + this field configures weight of subwindow 22 + 24 + 8 + read-write + + + + + HIST_WEIGHT4 + histogram sub-window weight register 4 + 0x1D4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_34 + this field configures weight of subwindow 34 + 0 + 8 + read-write + + + HIST_WEIGHT_33 + this field configures weight of subwindow 33 + 8 + 8 + read-write + + + HIST_WEIGHT_32 + this field configures weight of subwindow 32 + 16 + 8 + read-write + + + HIST_WEIGHT_31 + this field configures weight of subwindow 31 + 24 + 8 + read-write + + + + + HIST_WEIGHT5 + histogram sub-window weight register 5 + 0x1D8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_43 + this field configures weight of subwindow 43 + 0 + 8 + read-write + + + HIST_WEIGHT_42 + this field configures weight of subwindow 42 + 8 + 8 + read-write + + + HIST_WEIGHT_41 + this field configures weight of subwindow 41 + 16 + 8 + read-write + + + HIST_WEIGHT_40 + this field configures weight of subwindow 40 + 24 + 8 + read-write + + + + + HIST_WEIGHT6 + histogram sub-window weight register 6 + 0x1DC + 0x20 + 0x00000001 + + + HIST_WEIGHT_44 + this field configures weight of subwindow 44 + 0 + 8 + read-write + + + + + HIST_BIN0 + result of histogram bin 0 + 0x1E0 + 0x20 + + + HIST_BIN_0 + this field represents result of histogram bin 0 + 0 + 17 + read-only + + + + + HIST_BIN1 + result of histogram bin 1 + 0x1E4 + 0x20 + + + HIST_BIN_1 + this field represents result of histogram bin 1 + 0 + 17 + read-only + + + + + HIST_BIN2 + result of histogram bin 2 + 0x1E8 + 0x20 + + + HIST_BIN_2 + this field represents result of histogram bin 2 + 0 + 17 + read-only + + + + + HIST_BIN3 + result of histogram bin 3 + 0x1EC + 0x20 + + + HIST_BIN_3 + this field represents result of histogram bin 3 + 0 + 17 + read-only + + + + + HIST_BIN4 + result of histogram bin 4 + 0x1F0 + 0x20 + + + HIST_BIN_4 + this field represents result of histogram bin 4 + 0 + 17 + read-only + + + + + HIST_BIN5 + result of histogram bin 5 + 0x1F4 + 0x20 + + + HIST_BIN_5 + this field represents result of histogram bin 5 + 0 + 17 + read-only + + + + + HIST_BIN6 + result of histogram bin 6 + 0x1F8 + 0x20 + + + HIST_BIN_6 + this field represents result of histogram bin 6 + 0 + 17 + read-only + + + + + HIST_BIN7 + result of histogram bin 7 + 0x1FC + 0x20 + + + HIST_BIN_7 + this field represents result of histogram bin 7 + 0 + 17 + read-only + + + + + HIST_BIN8 + result of histogram bin 8 + 0x200 + 0x20 + + + HIST_BIN_8 + this field represents result of histogram bin 8 + 0 + 17 + read-only + + + + + HIST_BIN9 + result of histogram bin 9 + 0x204 + 0x20 + + + HIST_BIN_9 + this field represents result of histogram bin 9 + 0 + 17 + read-only + + + + + HIST_BIN10 + result of histogram bin 10 + 0x208 + 0x20 + + + HIST_BIN_10 + this field represents result of histogram bin 10 + 0 + 17 + read-only + + + + + HIST_BIN11 + result of histogram bin 11 + 0x20C + 0x20 + + + HIST_BIN_11 + this field represents result of histogram bin 11 + 0 + 17 + read-only + + + + + HIST_BIN12 + result of histogram bin 12 + 0x210 + 0x20 + + + HIST_BIN_12 + this field represents result of histogram bin 12 + 0 + 17 + read-only + + + + + HIST_BIN13 + result of histogram bin 13 + 0x214 + 0x20 + + + HIST_BIN_13 + this field represents result of histogram bin 13 + 0 + 17 + read-only + + + + + HIST_BIN14 + result of histogram bin 14 + 0x218 + 0x20 + + + HIST_BIN_14 + this field represents result of histogram bin 14 + 0 + 17 + read-only + + + + + HIST_BIN15 + result of histogram bin 15 + 0x21C + 0x20 + + + HIST_BIN_15 + this field represents result of histogram bin 15 + 0 + 17 + read-only + + + + + MEM_AUX_CTRL_0 + mem aux control register 0 + 0x220 + 0x20 + 0x13201320 + + + HEADER_MEM_AUX_CTRL + this field configures the mem_aux of isp input buffer memory + 0 + 14 + read-write + + + DPC_LUT_MEM_AUX_CTRL + this field represents this field configures the mem_aux of dpc lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_1 + mem aux control register 1 + 0x224 + 0x20 + 0x13201320 + + + LSC_LUT_R_GR_MEM_AUX_CTRL + this field configures the mem_aux of lsc r gr lut memory + 0 + 14 + read-write + + + LSC_LUT_GB_B_MEM_AUX_CTRL + this field configures the mem_aux of lsc gb b lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_2 + mem aux control register 2 + 0x228 + 0x20 + 0x13201320 + + + BF_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of bf line buffer memory + 0 + 14 + read-write + + + DPC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of dpc line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_3 + mem aux control register 3 + 0x22C + 0x20 + 0x13201320 + + + SHARP_MATRIX_Y_MEM_AUX_CTRL + this field configures the mem_aux of sharp y line buffer memory + 0 + 14 + read-write + + + DEMOSAIC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of demosaic line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_4 + mem aux control register 4 + 0x230 + 0x20 + 0x00001320 + + + SHARP_MATRIX_UV_MEM_AUX_CTRL + this field configures the mem_aux of sharp uv line buffer memory + 0 + 14 + read-write + + + + + YUV_FORMAT + yuv format control register + 0x234 + 0x20 + + + YUV_MODE + this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + 0 + 1 + read-write + + + YUV_RANGE + this bit configures the yuv range. 0: full range, 1: limit range + 1 + 1 + read-write + + + + + RDN_ECO_CS + rdn eco cs register + 0x238 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + rdn eco all low register + 0x23C + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + rdn eco all high register + 0x240 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + + + JPEG + JPEG Codec + JPEG + 0x50086000 + + 0x0 + 0xB0 + registers + + + JPEG + 95 + + + + CONFIG + Control and configuration registers + 0x0 + 0x20 + 0x00408958 + + + FSM_RST + fsm reset + 0 + 1 + write-only + + + JPEG_START + start to compress a new pic(in dma reg mode) + 1 + 1 + write-only + + + QNR_PRESITION + 0:8bit qnr,1:12bit qnr(TBD) + 2 + 1 + read-write + + + FF_CHECK_EN + enable whether to add "00" after "ff" + 3 + 1 + read-write + + + SAMPLE_SEL + 0:yuv444,1:yuv422, 2:yuv420 + 4 + 2 + read-write + + + DMA_LINKLIST_MODE + 1:use linklist to configure dma + 6 + 1 + read-only + + + DEBUG_DIRECT_OUT_EN + 0:normal mode,1:debug mode for direct output from input + 7 + 1 + read-write + + + GRAY_SEL + 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + 8 + 1 + read-write + + + LQNR_TBL_SEL + choose luminance quntization table id(TBD) + 9 + 2 + read-write + + + CQNR_TBL_SEL + choose chrominance quntization table id (TBD) + 11 + 2 + read-write + + + COLOR_SPACE + configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + 13 + 2 + read-write + + + DHT_FIFO_EN + 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way + 15 + 1 + read-write + + + MEM_CLK_FORCE_ON + force memory's clock enabled + 16 + 1 + read-write + + + JFIF_VER + decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1 + 17 + 6 + read-write + + + DECODE_TIMEOUT_TASK_SEL + 0: software use reset to abort decode process ,1: decoder abort decode process by itself + 23 + 1 + read-write + + + SOFT_RST + when set to 1, soft reset JPEG module except jpeg_reg module + 24 + 1 + read-write + + + FIFO_RST + fifo reset + 25 + 1 + read-write + + + PIXEL_REV + reverse the source color pixel + 26 + 1 + read-write + + + TAILER_EN + set this bit to add EOI of "0xffd9" at the end of bitstream + 27 + 1 + read-write + + + PAUSE_EN + set this bit to pause jpeg encoding + 28 + 1 + read-write + + + MEM_FORCE_PD + 0: no operation,1:force jpeg memory to power down + 29 + 1 + read-write + + + MEM_FORCE_PU + 0: no operation,1:force jpeg memory to power up + 30 + 1 + read-write + + + MODE + 0:encoder mode, 1: decoder mode + 31 + 1 + read-write + + + + + DQT_INFO + Control and configuration registers + 0x4 + 0x20 + 0x03020100 + + + T0_DQT_INFO + Configure dqt table0's quantization coefficient precision in bit[7:4], configure dqt table0's table id in bit[3:0] + 0 + 8 + read-write + + + T1_DQT_INFO + Configure dqt table1's quantization coefficient precision in bit[7:4], configure dqt table1's table id in bit[3:0] + 8 + 8 + read-write + + + T2_DQT_INFO + Configure dqt table2's quantization coefficient precision in bit[7:4], configure dqt table2's table id in bit[3:0] + 16 + 8 + read-write + + + T3_DQT_INFO + Configure dqt table3's quantization coefficient precision in bit[7:4], configure dqt table3's table id in bit[3:0] + 24 + 8 + read-write + + + + + PIC_SIZE + Control and configuration registers + 0x8 + 0x20 + 0x028001E0 + + + VA + configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 0 + 16 + read-write + + + HA + configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 16 + 16 + read-write + + + + + T0QNR + Control and configuration registers + 0x10 + 0x20 + + + T0_QNR_VAL + write this reg to configure 64 quantization coefficient in t0 table + 0 + 32 + read-only + + + + + T1QNR + Control and configuration registers + 0x14 + 0x20 + + + CHROMINANCE_QNR_VAL + write this reg to configure 64 quantization coefficient in t1 table + 0 + 32 + read-only + + + + + T2QNR + Control and configuration registers + 0x18 + 0x20 + + + T2_QNR_VAL + write this reg to configure 64 quantization coefficient in t2 table + 0 + 32 + read-only + + + + + T3QNR + Control and configuration registers + 0x1C + 0x20 + + + T3_QNR_VAL + write this reg to configure 64 quantization coefficient in t3 table + 0 + 32 + read-only + + + + + DECODE_CONF + Control and configuration registers + 0x20 + 0x20 + 0x5F030000 + + + RESTART_INTERVAL + configure restart interval in DRI marker when decode + 0 + 16 + read-write + + + COMPONENT_NUM + configure number of components in frame when decode + 16 + 8 + read-write + + + SW_DHT_EN + software decode dht table enable + 24 + 1 + read-only + + + SOS_CHECK_BYTE_NUM + Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + 25 + 2 + read-write + + + RST_CHECK_BYTE_NUM + Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1 + 27 + 2 + read-write + + + MULTI_SCAN_ERR_CHECK + reserved for decoder + 29 + 1 + read-write + + + DEZIGZAG_READY_CTL + reserved for decoder + 30 + 1 + read-write + + + + + C0 + Control and configuration registers + 0x24 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c0 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c0 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c0 + 12 + 4 + read-write + + + ID + the identifier of c0 + 16 + 8 + read-write + + + + + C1 + Control and configuration registers + 0x28 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c1 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c1 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c1 + 12 + 4 + read-write + + + ID + the identifier of c1 + 16 + 8 + read-write + + + + + C2 + Control and configuration registers + 0x2C + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c2 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c2 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c2 + 12 + 4 + read-write + + + ID + the identifier of c2 + 16 + 8 + read-write + + + + + C3 + Control and configuration registers + 0x30 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c3 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c3 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c3 + 12 + 4 + read-write + + + ID + the identifier of c3 + 16 + 8 + read-write + + + + + DHT_INFO + Control and configuration registers + 0x34 + 0x20 + 0x00001010 + + + DC0_DHT_ID + configure dht dc table 0 id + 0 + 4 + read-write + + + DC1_DHT_ID + configure dht dc table 1 id + 4 + 4 + read-write + + + AC0_DHT_ID + configure dht ac table 0 id + 8 + 4 + read-write + + + AC1_DHT_ID + configure dht ac table 1 id + 12 + 4 + read-write + + + + + INT_RAW + Interrupt raw registers + 0x38 + 0x20 + + + DONE_INT_RAW + This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_RAW + The raw interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_RAW + The raw interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_RAW + The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_RAW + The raw interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_RAW + The raw interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_RAW + The raw interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_RAW + The raw interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_RAW + The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_RAW + The raw interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_RAW + The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_RAW + The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_RAW + The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers + 0x3C + 0x20 + + + DONE_INT_ENA + This enable interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_ENA + The enable interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_ENA + The enable interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_ENA + The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_ENA + The enable interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_ENA + The enable interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_ENA + The enable interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_ENA + The enable interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_ENA + The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_ENA + The enable interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_ENA + The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_ENA + The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_ENA + The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ST + Interrupt status registers + 0x40 + 0x20 + + + DONE_INT_ST + This status interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-only + + + RLE_PARALLEL_ERR_INT_ST + The status interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-only + + + CID_ERR_INT_ST + The status interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-only + + + C_DHT_DC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-only + + + C_DHT_AC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-only + + + C_DQT_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-only + + + RST_UXP_ERR_INT_ST + The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-only + + + RST_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-only + + + RST_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-only + + + OUT_EOF_INT_ST + The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-only + + + SR_COLOR_MODE_ERR_INT_ST + The status interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-only + + + DCT_DONE_INT_ST + The status interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-only + + + BS_LAST_BLOCK_EOF_INT_ST + The status interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-only + + + SCAN_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-only + + + SCAN_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-only + + + UXP_DET_INT_ST + The status interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-only + + + EN_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-only + + + EN_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-only + + + DE_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-only + + + DE_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-only + + + SOS_UNMATCH_ERR_INT_ST + The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-only + + + MARKER_ERR_FST_SCAN_INT_ST + The status interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-only + + + MARKER_ERR_OTHER_SCAN_INT_ST + The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-only + + + UNDET_INT_ST + The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-only + + + DECODE_TIMEOUT_INT_ST + The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers + 0x44 + 0x20 + + + DONE_INT_CLR + This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + write-only + + + RLE_PARALLEL_ERR_INT_CLR + The clear interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + write-only + + + CID_ERR_INT_CLR + The clear interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + write-only + + + C_DHT_DC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + write-only + + + C_DHT_AC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + write-only + + + C_DQT_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + write-only + + + RST_UXP_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + write-only + + + RST_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + write-only + + + RST_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + write-only + + + OUT_EOF_INT_CLR + The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + write-only + + + SR_COLOR_MODE_ERR_INT_CLR + The clear interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + write-only + + + DCT_DONE_INT_CLR + The clear interrupt bit to sign that one dct calculation is finished. + 11 + 1 + write-only + + + BS_LAST_BLOCK_EOF_INT_CLR + The clear interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + write-only + + + SCAN_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + write-only + + + SCAN_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + write-only + + + UXP_DET_INT_CLR + The clear interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + write-only + + + EN_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + write-only + + + EN_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + write-only + + + DE_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + write-only + + + DE_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + write-only + + + SOS_UNMATCH_ERR_INT_CLR + The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + write-only + + + MARKER_ERR_FST_SCAN_INT_CLR + The clear interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + write-only + + + MARKER_ERR_OTHER_SCAN_INT_CLR + The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + write-only + + + UNDET_INT_CLR + The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + write-only + + + DECODE_TIMEOUT_INT_CLR + The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + write-only + + + + + STATUS0 + Trace and Debug registers + 0x48 + 0x20 + + + BITSTREAM_EOF_VLD_CNT + the valid bit count for last bitstream + 11 + 6 + read-only + + + DCTOUT_ZZSCAN_ADDR + the zig-zag read addr from dctout_ram + 17 + 6 + read-only + + + QNRVAL_ZZSCAN_ADDR + the zig-zag read addr from qnrval_ram + 23 + 6 + read-only + + + REG_STATE_YUV + the state of jpeg fsm + 29 + 3 + read-only + + + + + STATUS2 + Trace and Debug registers + 0x4C + 0x20 + 0x08000000 + + + SOURCE_PIXEL + source pixels fetched from dma + 0 + 24 + read-only + + + LAST_BLOCK + indicate the encoding process for the last mcu of the picture + 24 + 1 + read-only + + + LAST_MCU + indicate the encoding process for the last block of the picture + 25 + 1 + read-only + + + LAST_DC + indicate the encoding process is at the header of the last block of the picture + 26 + 1 + read-only + + + PACKFIFO_READY + the jpeg pack_fifo ready signal, high active + 27 + 1 + read-only + + + + + STATUS3 + Trace and Debug registers + 0x50 + 0x20 + + + YO + component y transferred from rgb input + 0 + 9 + read-only + + + Y_READY + component y valid signal, high active + 9 + 1 + read-only + + + CBO + component cb transferred from rgb input + 10 + 9 + read-only + + + CB_READY + component cb valid signal, high active + 19 + 1 + read-only + + + CRO + component cr transferred from rgb input + 20 + 9 + read-only + + + CR_READY + component cr valid signal, high active + 29 + 1 + read-only + + + + + STATUS4 + Trace and Debug registers + 0x54 + 0x20 + + + HFM_BITSTREAM + the hufman bitstream during encoding process + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC0 + Trace and Debug registers + 0x58 + 0x20 + + + DHT_TOTLEN_DC0 + write the numbers of 1~n codeword length sum from 1~16 of dc0 table + 0 + 32 + read-only + + + + + DHT_VAl_DC0 + Trace and Debug registers + 0x5C + 0x20 + + + DHT_VAL_DC0 + write codeword corresponding huffman values of dc0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC0 + Trace and Debug registers + 0x60 + 0x20 + + + DHT_TOTLEN_AC0 + write the numbers of 1~n codeword length sum from 1~16 of ac0 table + 0 + 32 + read-only + + + + + DHT_VAl_AC0 + Trace and Debug registers + 0x64 + 0x20 + + + DHT_VAL_AC0 + write codeword corresponding huffman values of ac0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC1 + Trace and Debug registers + 0x68 + 0x20 + + + DHT_TOTLEN_DC1 + write the numbers of 1~n codeword length sum from 1~16 of dc1 table + 0 + 32 + read-only + + + + + DHT_VAl_DC1 + Trace and Debug registers + 0x6C + 0x20 + + + DHT_VAL_DC1 + write codeword corresponding huffman values of dc1 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC1 + Trace and Debug registers + 0x70 + 0x20 + + + DHT_TOTLEN_AC1 + write the numbers of 1~n codeword length sum from 1~16 of ac1 table + 0 + 32 + read-only + + + + + DHT_VAl_AC1 + Trace and Debug registers + 0x74 + 0x20 + + + DHT_VAL_AC1 + write codeword corresponding huffman values of ac1 table + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC0 + Trace and Debug registers + 0x78 + 0x20 + + + DHT_CODEMIN_DC0 + write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC0 + Trace and Debug registers + 0x7C + 0x20 + + + DHT_CODEMIN_AC0 + write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC1 + Trace and Debug registers + 0x80 + 0x20 + + + DHT_CODEMIN_DC1 + write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC1 + Trace and Debug registers + 0x84 + 0x20 + + + DHT_CODEMIN_AC1 + write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DECODER_STATUS0 + Trace and Debug registers + 0x88 + 0x20 + + + DECODE_BYTE_CNT + Reserved + 0 + 26 + read-only + + + HEADER_DEC_ST + Reserved + 26 + 4 + read-only + + + DECODE_SAMPLE_SEL + Reserved + 30 + 2 + read-only + + + + + DECODER_STATUS1 + Trace and Debug registers + 0x8C + 0x20 + + + ENCODE_DATA + Reserved + 0 + 16 + read-only + + + COUNT_Q + Reserved + 16 + 7 + read-only + + + MCU_FSM_READY + Reserved + 23 + 1 + read-only + + + DECODE_DATA + Reserved + 24 + 8 + read-only + + + + + DECODER_STATUS2 + Trace and Debug registers + 0x90 + 0x20 + + + COMP_BLOCK_NUM + Reserved + 0 + 26 + read-only + + + SCAN_NUM + Reserved + 26 + 3 + read-only + + + RST_CHECK_WAIT + Reserved + 29 + 1 + read-only + + + SCAN_CHECK_WAIT + Reserved + 30 + 1 + read-only + + + MCU_IN_PROC + Reserved + 31 + 1 + read-only + + + + + DECODER_STATUS3 + Trace and Debug registers + 0x94 + 0x20 + + + LOOKUP_DATA + Reserved + 0 + 32 + read-only + + + + + DECODER_STATUS4 + Trace and Debug registers + 0x98 + 0x20 + + + BLOCK_EOF_CNT + Reserved + 0 + 26 + read-only + + + DEZIGZAG_READY + Reserved + 26 + 1 + read-only + + + DE_FRAME_EOF_CHECK + Reserved + 27 + 1 + read-only + + + DE_DMA2D_IN_PUSH + Reserved + 28 + 1 + read-only + + + + + DECODER_STATUS5 + Trace and Debug registers + 0x9C + 0x20 + + + IDCT_HFM_DATA + Reserved + 0 + 16 + read-only + + + NS0 + Reserved + 16 + 3 + read-only + + + NS1 + Reserved + 19 + 3 + read-only + + + NS2 + Reserved + 22 + 3 + read-only + + + NS3 + Reserved + 25 + 3 + read-only + + + DATA_LAST_O + Reserved + 28 + 1 + read-only + + + RDN_RESULT + redundant registers for jpeg + 29 + 1 + read-only + + + RDN_ENA + redundant control registers for jpeg + 30 + 1 + read-write + + + + + STATUS5 + Trace and Debug registers + 0xA0 + 0x20 + + + PIC_BLOCK_NUM + Reserved + 0 + 24 + read-only + + + + + ECO_LOW + Trace and Debug registers + 0xA4 + 0x20 + + + RDN_ECO_LOW + redundant registers for jpeg + 0 + 32 + read-write + + + + + ECO_HIGH + Trace and Debug registers + 0xA8 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + redundant registers for jpeg + 0 + 32 + read-write + + + + + SYS + Trace and Debug registers + 0xF8 + 0x20 + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Trace and Debug registers + 0xFC + 0x20 + 0x02111190 + + + JPEG_VER + Reserved + 0 + 28 + read-write + + + + + + + LCD_CAM + Camera/LCD Controller + LCDCAM + 0x500DC000 + + 0x0 + 0x4C + registers + + + + LCD_CLOCK + LCD clock config register. + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + CAM config register. + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + CAM config register. + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + CAM YUV/RGB converter configuration register. + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD YUV/RGB converter configuration register. + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD config register. + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_MODE + 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + 14 + 3 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_ENABLE + 1: enable byte swizzle 0: disable + 17 + 1 + read-write + + + LCD_DOUT_BIT_ORDER + 1: change bit order in every byte. 0: Not change. + 18 + 1 + read-write + + + LCD_BYTE_MODE + 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + 19 + 2 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 21 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD config register. + 0x18 + 0x20 + 0x000000C0 + + + LCD_WIRE_MODE + The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + 4 + 2 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD config register. + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD config register. + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD config register. + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_FIRST_CMD_VAL + LCD config register. + 0x28 + 0x20 + + + LCD_FIRST_CMD_VALUE + The LCD write command value of first cmd cycle. + 0 + 32 + read-write + + + + + LCD_LATTER_CMD_VAL + LCD config register. + 0x2C + 0x20 + + + LCD_LATTER_CMD_VALUE + The LCD write command value of latter cmd cycle. + 0 + 32 + read-write + + + + + LCD_DLY_MODE_CFG1 + LCD config register. + 0x30 + 0x20 + + + DOUT16_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT17_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT18_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT19_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT20_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT21_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT22_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT23_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + + + LCD_DLY_MODE_CFG2 + LCD config register. + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCDCAM interrupt enable register. + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCDCAM interrupt raw register, valid in level. + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCDCAM interrupt status register. + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCDCAM interrupt clear register. + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02303090 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x500D3000 + + 0x0 + 0x124 + registers + + + LEDC + 52 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + Configures which timer is channel %s selected.\\0: Select timer0\\1: Select timer1\\2: Select timer2\\3: Select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN_CH + Configures whether or not to enable signal output on channel %s.\\0: Signal output disable\\1: Signal output enable + 2 + 1 + read-write + + + IDLE_LV_CH + Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\0: Output level is low\\1: Output level is high + 3 + 1 + read-write + + + PARA_UP_CH + Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + 4 + 1 + write-only + + + OVF_NUM_CH + Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN_CH + Configures whether or not to enable the ovf_cnt of channel %s.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + OVF_CNT_RESET_CH + Configures whether or not to reset the ovf_cnt of channel %s.\\0: Invalid. No effect\\1: Reset the ovf_cnt + 16 + 1 + write-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT_CH + Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle register for channel %s + 0x8 + 0x20 + + + DUTY_CH + Configures the duty of signal output on channel %s. + 0 + 25 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START_CH + Configures whether the duty cycle fading configurations take effect.\\0: Not take effect\\1: Take effect + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle register for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + Represents the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration register + 0xA0 + 0x20 + 0x01000000 + + + TIMER_DUTY_RES + Configures the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV_TIMER + Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + TIMER_PAUSE + Configures whether or not to pause the counter in timer %s.\\0: Normal\\1: Pause + 23 + 1 + read-write + + + TIMER_RST + Configures whether or not to reset timer %s. The counter will show 0 after reset.\\0: Not reset\\1: Reset + 24 + 1 + read-write + + + TICK_SEL_TIMER + Configures which clock is timer %s selected. Unused. + 25 + 1 + read-write + + + TIMER_PARA_UP + Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\0: Invalid. No effect\\1: Update + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value register + 0xA4 + 0x20 + + + TIMER_CNT + Represents the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-write + + + TIMER1_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-write + + + TIMER2_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-write + + + TIMER3_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + 19 + 1 + write-only + + + + + 8 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x100 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Configures the number of duty cycle fading rages for LEDC ch%s. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Configures whether or not to pause duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Pause + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Resume + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x120 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH6_EN + Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH7_EN + Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x124 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH6_EN + Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH7_EN + Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_OVF_CNT_RST_CH6_EN + Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_OVF_CNT_RST_CH7_EN + Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_TIMER0_RST_EN + Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x128 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GAMMA_RESTART_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_GAMMA_RESTART_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_GAMMA_RESUME_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_GAMMA_RESUME_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x140 + 0x20 + + + TIMER_CMP + Configures the comparison value for LEDC timer%s. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s captured count value register. + 0x150 + 0x20 + + + TIMER_CNT_CAP + Represents the captured LEDC timer%s count value. + 0 + 20 + read-only + + + + + CONF + LEDC global configuration register + 0x170 + 0x20 + + + APB_CLK_SEL + Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC ch0 gamma ram + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC ch1 gamma ram + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC ch2 gamma ram + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC ch3 gamma ram + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC ch4 gamma ram + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC ch5 gamma ram + 7 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH6 + Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC ch6 gamma ram + 8 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH7 + Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC ch7 gamma ram + 9 + 1 + read-write + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 31 + 1 + read-write + + + + + DATE + Version control register + 0x174 + 0x20 + 0x02303070 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + LP_INTR + Low-power Interrupt Controller + LPINTR + 0x5012C000 + + 0x0 + 0x18 + registers + + + + SW_INT_RAW + need_des + 0x0 + 0x20 + + + LP_SW_INT_RAW + need_des + 31 + 1 + read-write + + + + + SW_INT_ST + need_des + 0x4 + 0x20 + + + LP_SW_INT_ST + need_des + 31 + 1 + read-only + + + + + SW_INT_ENA + need_des + 0x8 + 0x20 + + + LP_SW_INT_ENA + need_des + 31 + 1 + read-write + + + + + SW_INT_CLR + need_des + 0xC + 0x20 + + + LP_SW_INT_CLR + need_des + 31 + 1 + write-only + + + + + STATUS + need_des + 0x10 + 0x20 + + + LP_HUK_INTR_ST + need_des + 10 + 1 + read-only + + + SYSREG_INTR_ST + need_des + 11 + 1 + read-only + + + LP_SW_INTR_ST + need_des + 12 + 1 + read-only + + + LP_EFUSE_INTR_ST + need_des + 13 + 1 + read-only + + + LP_UART_INTR_ST + need_des + 14 + 1 + read-only + + + LP_TSENS_INTR_ST + need_des + 15 + 1 + read-only + + + LP_TOUCH_INTR_ST + need_des + 16 + 1 + read-only + + + LP_SPI_INTR_ST + need_des + 17 + 1 + read-only + + + LP_I2S_INTR_ST + need_des + 18 + 1 + read-only + + + LP_I2C_INTR_ST + need_des + 19 + 1 + read-only + + + LP_GPIO_INTR_ST + need_des + 20 + 1 + read-only + + + LP_ADC_INTR_ST + need_des + 21 + 1 + read-only + + + ANAPERI_INTR_ST + need_des + 22 + 1 + read-only + + + PMU_REG_1_INTR_ST + need_des + 23 + 1 + read-only + + + PMU_REG_0_INTR_ST + need_des + 24 + 1 + read-only + + + MB_LP_INTR_ST + need_des + 25 + 1 + read-only + + + MB_HP_INTR_ST + need_des + 26 + 1 + read-only + + + LP_TIMER_REG_1_INTR_ST + need_des + 27 + 1 + read-only + + + LP_TIMER_REG_0_INTR_ST + need_des + 28 + 1 + read-only + + + LP_WDT_INTR_ST + need_des + 29 + 1 + read-only + + + LP_RTC_INTR_ST + need_des + 30 + 1 + read-only + + + HP_INTR_ST + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_PERI + LP_PERI Peripheral + LPPERI + 0x50120000 + + 0x0 + 0x2C + registers + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7FFF0000 + + + CK_EN_RNG + need_des + 16 + 1 + read-write + + + CK_EN_LP_TSENS + need_des + 17 + 1 + read-write + + + CK_EN_LP_PMS + need_des + 18 + 1 + read-write + + + CK_EN_LP_EFUSE + need_des + 19 + 1 + read-write + + + CK_EN_LP_IOMUX + need_des + 20 + 1 + read-write + + + CK_EN_LP_TOUCH + need_des + 21 + 1 + read-write + + + CK_EN_LP_SPI + need_des + 22 + 1 + read-write + + + CK_EN_LP_ADC + need_des + 23 + 1 + read-write + + + CK_EN_LP_I2S_TX + need_des + 24 + 1 + read-write + + + CK_EN_LP_I2S_RX + need_des + 25 + 1 + read-write + + + CK_EN_LP_I2S + need_des + 26 + 1 + read-write + + + CK_EN_LP_I2CMST + need_des + 27 + 1 + read-write + + + CK_EN_LP_I2C + need_des + 28 + 1 + read-write + + + CK_EN_LP_UART + need_des + 29 + 1 + read-write + + + CK_EN_LP_INTR + need_des + 30 + 1 + read-write + + + CK_EN_LP_CORE + write 1 to force on lp_core clk + 31 + 1 + read-write + + + + + CORE_CLK_SEL + need_des + 0x4 + 0x20 + + + LP_I2S_TX_CLK_SEL + need_des + 24 + 2 + read-write + + + LP_I2S_RX_CLK_SEL + need_des + 26 + 2 + read-write + + + LP_I2C_CLK_SEL + need_des + 28 + 2 + read-write + + + LP_UART_CLK_SEL + need_des + 30 + 2 + read-write + + + + + RESET_EN + need_des + 0x8 + 0x20 + + + RST_EN_LP_TSENS + need_des + 18 + 1 + read-write + + + RST_EN_LP_PMS + need_des + 19 + 1 + read-write + + + RST_EN_LP_EFUSE + need_des + 20 + 1 + read-write + + + RST_EN_LP_IOMUX + need_des + 21 + 1 + read-write + + + RST_EN_LP_TOUCH + need_des + 22 + 1 + read-write + + + RST_EN_LP_SPI + need_des + 23 + 1 + read-write + + + RST_EN_LP_ADC + need_des + 24 + 1 + read-write + + + RST_EN_LP_I2S + need_des + 25 + 1 + read-write + + + RST_EN_LP_I2CMST + need_des + 26 + 1 + read-write + + + RST_EN_LP_I2C + need_des + 27 + 1 + read-write + + + RST_EN_LP_UART + need_des + 28 + 1 + read-write + + + RST_EN_LP_INTR + need_des + 29 + 1 + read-write + + + RST_EN_LP_ROM + need_des + 30 + 1 + read-write + + + RST_EN_LP_CORE + need_des + 31 + 1 + write-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVAILABLE + need_des + 31 + 1 + read-write + + + + + MEM_CTRL + need_des + 0x28 + 0x20 + 0x80000000 + + + LP_UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + LP_UART_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + LP_UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + LP_UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + LP_UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + ADC_CTRL + need_des + 0x2C + 0x20 + 0x04040400 + + + SAR2_CLK_FORCE_ON + need_des + 6 + 1 + read-write + + + SAR1_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + LPADC_FUNC_DIV_NUM + need_des + 8 + 8 + read-write + + + LPADC_SAR2_DIV_NUM + need_des + 16 + 8 + read-write + + + LPADC_SAR1_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_NUM + need_des + 0x30 + 0x20 + 0x02000000 + + + LP_I2S_RX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_XYZ + need_des + 0x34 + 0x20 + 0x00004000 + + + LP_I2S_RX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_RX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + LP_I2S_TXCLK_DIV_NUM + need_des + 0x38 + 0x20 + 0x02000000 + + + LP_I2S_TX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_TXCLK_DIV_XYZ + need_des + 0x3C + 0x20 + 0x00004000 + + + LP_I2S_TX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_TX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_SYS + LP_SYS Peripheral + LPSYSREG + 0x50110000 + + 0x0 + 0x110 + registers + + + LP_SYS + 19 + + + + LP_SYS_VER_DATE + need_des + 0x0 + 0x20 + 0x20230509 + + + VER_DATE + need_des + 0 + 32 + read-write + + + + + CLK_SEL_CTRL + need_des + 0x4 + 0x20 + + + ENA_SW_SEL_SYS_CLK + reserved + 16 + 1 + read-write + + + SW_SYS_CLK_SRC_SEL + reserved + 17 + 1 + read-write + + + + + SYS_CTRL + need_des + 0x8 + 0x20 + 0x1FFFC7F8 + + + LP_CORE_DISABLE + lp cpu disable + 0 + 1 + read-write + + + SYS_SW_RST + digital system software reset bit + 1 + 1 + write-only + + + FORCE_DOWNLOAD_BOOT + need_des + 2 + 1 + read-write + + + DIG_FIB + need_des + 3 + 8 + read-write + + + IO_MUX_RESET_DISABLE + reset disable bit for LP IOMUX + 11 + 1 + read-write + + + ANA_FIB + need_des + 14 + 7 + read-only + + + LP_FIB_SEL + need_des + 21 + 8 + read-write + + + LP_CORE_ETM_WAKEUP_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_CORE_ETM_WAKEUP_FLAG + need_des + 30 + 1 + read-write + + + SYSTIMER_STALL_SEL + 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1 + 31 + 1 + read-write + + + + + LP_CLK_CTRL + need_des + 0xC + 0x20 + 0x00004001 + + + CLK_EN + need_des + 0 + 1 + read-write + + + LP_FOSC_HP_CKEN + reserved + 14 + 1 + read-write + + + + + LP_RST_CTRL + need_des + 0x10 + 0x20 + 0x00000003 + + + ANA_RST_BYPASS + analog source reset bypass : wdt,brown out,super wdt,glitch + 0 + 1 + read-write + + + SYS_RST_BYPASS + system source reset bypass : software reset,hp wdt,lp wdt,efuse + 1 + 1 + read-write + + + EFUSE_FORCE_NORST + efuse force no reset control + 2 + 1 + read-write + + + + + LP_CORE_BOOT_ADDR + need_des + 0x18 + 0x20 + 0x50100000 + + + LP_CPU_BOOT_ADDR + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + need_des + 0x1C + 0x20 + + + SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 16 + read-write + + + STATUS_CLR + clear ext wakeup1 status + 16 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + need_des + 0x20 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 16 + read-only + + + + + LP_TCM_PWR_CTRL + need_des + 0x24 + 0x20 + + + LP_TCM_ROM_CLK_FORCE_ON + need_des + 5 + 1 + read-write + + + LP_TCM_RAM_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + + + BOOT_ADDR_HP_LP + need_des + 0x28 + 0x20 + + + BOOT_ADDR_HP_LP + need_des + 0 + 32 + read-write + + + + + LP_STORE0 + need_des + 0x2C + 0x20 + + + LP_SCRATCH0 + need_des + 0 + 32 + read-write + + + + + LP_STORE1 + need_des + 0x30 + 0x20 + + + LP_SCRATCH1 + need_des + 0 + 32 + read-write + + + + + LP_STORE2 + need_des + 0x34 + 0x20 + + + LP_SCRATCH2 + need_des + 0 + 32 + read-write + + + + + LP_STORE3 + need_des + 0x38 + 0x20 + + + LP_SCRATCH3 + need_des + 0 + 32 + read-write + + + + + LP_STORE4 + need_des + 0x3C + 0x20 + + + LP_SCRATCH4 + need_des + 0 + 32 + read-write + + + + + LP_STORE5 + need_des + 0x40 + 0x20 + + + LP_SCRATCH5 + need_des + 0 + 32 + read-write + + + + + LP_STORE6 + need_des + 0x44 + 0x20 + + + LP_SCRATCH6 + need_des + 0 + 32 + read-write + + + + + LP_STORE7 + need_des + 0x48 + 0x20 + + + LP_SCRATCH7 + need_des + 0 + 32 + read-write + + + + + LP_STORE8 + need_des + 0x4C + 0x20 + + + LP_SCRATCH8 + need_des + 0 + 32 + read-write + + + + + LP_STORE9 + need_des + 0x50 + 0x20 + + + LP_SCRATCH9 + need_des + 0 + 32 + read-write + + + + + LP_STORE10 + need_des + 0x54 + 0x20 + + + LP_SCRATCH10 + need_des + 0 + 32 + read-write + + + + + LP_STORE11 + need_des + 0x58 + 0x20 + + + LP_SCRATCH11 + need_des + 0 + 32 + read-write + + + + + LP_STORE12 + need_des + 0x5C + 0x20 + + + LP_SCRATCH12 + need_des + 0 + 32 + read-write + + + + + LP_STORE13 + need_des + 0x60 + 0x20 + + + LP_SCRATCH13 + need_des + 0 + 32 + read-write + + + + + LP_STORE14 + need_des + 0x64 + 0x20 + + + LP_SCRATCH14 + need_des + 0 + 32 + read-write + + + + + LP_STORE15 + need_des + 0x68 + 0x20 + + + LP_SCRATCH15 + need_des + 0 + 32 + read-write + + + + + LP_PROBEA_CTRL + need_des + 0x6C + 0x20 + + + PROBE_A_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_A_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_L_SEL + need_des + 24 + 2 + read-write + + + PROBE_H_SEL + need_des + 26 + 2 + read-write + + + PROBE_GLOBAL_EN + need_des + 28 + 1 + read-write + + + + + LP_PROBEB_CTRL + need_des + 0x70 + 0x20 + + + PROBE_B_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_B_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_B_EN + need_des + 24 + 1 + read-write + + + + + LP_PROBE_OUT + need_des + 0x74 + 0x20 + + + PROBE_TOP_OUT + need_des + 0 + 32 + read-only + + + + + F2S_APB_BRG_CNTL + need_des + 0x9C + 0x20 + + + F2S_APB_POSTW_EN + reserved + 0 + 1 + read-write + + + + + USB_CTRL + need_des + 0x100 + 0x20 + + + SW_HW_USB_PHY_SEL + need_des + 0 + 1 + read-write + + + SW_USB_PHY_SEL + need_des + 1 + 1 + read-write + + + USBOTG20_WAKEUP_CLR + clear usb wakeup to PMU. + 2 + 1 + write-only + + + USBOTG20_IN_SUSPEND + indicate usb otg2.0 is in suspend state. + 3 + 1 + read-write + + + + + ANA_XPD_PAD_GROUP + need_des + 0x10C + 0x20 + 0x000000FF + + + ANA_REG_XPD_PAD_GROUP + Set 1 to power up pad group + 0 + 8 + read-write + + + + + LP_TCM_RAM_RDN_ECO_CS + need_des + 0x110 + 0x20 + + + LP_TCM_RAM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_RAM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0x114 + 0x20 + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0x118 + 0x20 + 0xFFFFFFFF + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_CS + need_des + 0x11C + 0x20 + + + LP_TCM_ROM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_ROM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0x120 + 0x20 + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0x124 + 0x20 + 0xFFFFFFFF + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + HP_ROOT_CLK_CTRL + need_des + 0x130 + 0x20 + 0x00000003 + + + CPU_CLK_EN + clock gate enable for hp cpu root 400M clk + 0 + 1 + read-write + + + SYS_CLK_EN + clock gate enable for hp sys root 480M clk + 1 + 1 + read-write + + + + + LP_PMU_RDN_ECO_LOW + need_des + 0x138 + 0x20 + + + PMU_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_PMU_RDN_ECO_HIGH + need_des + 0x13C + 0x20 + 0xFFFFFFFF + + + PMU_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + PAD_COMP0 + need_des + 0x148 + 0x20 + + + DREF_COMP0 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP0 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP0 + pad comp xpd + 4 + 1 + read-write + + + + + PAD_COMP1 + need_des + 0x14C + 0x20 + + + DREF_COMP1 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP1 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP1 + pad comp xpd + 4 + 1 + read-write + + + + + BACKUP_DMA_CFG0 + need_des + 0x154 + 0x20 + 0x1906414A + + + BURST_LIMIT_AON + need_des + 0 + 5 + read-write + + + READ_INTERVAL_AON + need_des + 5 + 7 + read-write + + + LINK_BACKUP_TOUT_THRES_AON + need_des + 12 + 10 + read-write + + + LINK_TOUT_THRES_AON + need_des + 22 + 10 + read-write + + + + + BACKUP_DMA_CFG1 + need_des + 0x158 + 0x20 + + + AON_BYPASS + need_des + 31 + 1 + read-write + + + + + BACKUP_DMA_CFG2 + need_des + 0x15C + 0x20 + + + LINK_ADDR_AON + need_des + 0 + 32 + read-write + + + + + BOOT_ADDR_HP_CORE1 + need_des + 0x164 + 0x20 + + + BOOT_ADDR_HP_CORE1 + need_des + 0 + 32 + read-write + + + + + LP_ADDRHOLE_ADDR + need_des + 0x168 + 0x20 + + + LP_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + LP_ADDRHOLE_INFO + need_des + 0x16C + 0x20 + + + LP_ADDRHOLE_ID + master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. + 0 + 5 + read-only + + + LP_ADDRHOLE_WR + 1:write trans, 0: read trans. + 5 + 1 + read-only + + + LP_ADDRHOLE_SECURE + 1: illegal address access, 0: access without permission + 6 + 1 + read-only + + + + + INT_RAW + raw interrupt register + 0x170 + 0x20 + + + LP_ADDRHOLE_INT_RAW + the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_RAW + the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_RAW + the raw interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_RAW + the raw interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_RAW + the raw interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x174 + 0x20 + + + LP_ADDRHOLE_INT_ST + the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_ST + the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_ST + the masked interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_ST + the masked interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_ST + the masked interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ENA + masked interrupt register + 0x178 + 0x20 + + + LP_ADDRHOLE_INT_ENA + Write 1 to enable lp addrhole int + 0 + 1 + read-write + + + IDBUS_ADDRHOLE_INT_ENA + Write 1 to enable idbus addrhole int + 1 + 1 + read-write + + + LP_CORE_AHB_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ahb_timeout int + 2 + 1 + read-write + + + LP_CORE_IBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ibus_timeout int + 3 + 1 + read-write + + + LP_CORE_DBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_dbus_timeout int + 4 + 1 + read-write + + + ETM_TASK_ULP_INT_ENA + Write 1 to enable etm task ulp int + 5 + 1 + read-write + + + SLOW_CLK_TICK_INT_ENA + Write 1 to enable slow_clk_tick int + 6 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x17C + 0x20 + + + LP_ADDRHOLE_INT_CLR + write 1 to clear lp addrhole int + 0 + 1 + write-only + + + IDBUS_ADDRHOLE_INT_CLR + write 1 to clear idbus addrhole int + 1 + 1 + write-only + + + LP_CORE_AHB_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ahb_timeout int + 2 + 1 + write-only + + + LP_CORE_IBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ibus_timeout int + 3 + 1 + write-only + + + LP_CORE_DBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_dbus_timeout int + 4 + 1 + write-only + + + ETM_TASK_ULP_INT_CLR + Write 1 to clear etm tasl ulp int + 5 + 1 + write-only + + + SLOW_CLK_TICK_INT_CLR + Write 1 to clear slow_clk_tick int + 6 + 1 + write-only + + + + + HP_MEM_AUX_CTRL + need_des + 0x180 + 0x20 + 0x00002070 + + + HP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_MEM_AUX_CTRL + need_des + 0x184 + 0x20 + 0x00002070 + + + LP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + HP_ROM_AUX_CTRL + need_des + 0x188 + 0x20 + 0x00000070 + + + HP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_ROM_AUX_CTRL + need_des + 0x18C + 0x20 + 0x00000070 + + + LP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_CPU_DBG_PC + need_des + 0x190 + 0x20 + + + LP_CPU_DBG_PC + need_des + 0 + 32 + read-only + + + + + LP_CPU_EXC_PC + need_des + 0x194 + 0x20 + + + LP_CPU_EXC_PC + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_ADDR + need_des + 0x198 + 0x20 + + + IDBUS_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_INFO + need_des + 0x19C + 0x20 + + + IDBUS_ADDRHOLE_ID + need_des + 0 + 5 + read-only + + + IDBUS_ADDRHOLE_WR + need_des + 5 + 1 + read-only + + + IDBUS_ADDRHOLE_SECURE + need_des + 6 + 1 + read-only + + + + + HP_POR_RST_BYPASS_CTRL + need_des + 0x1A0 + 0x20 + 0xFF00FF00 + + + HP_PO_CNNT_RSTN_BYPASS_CTRL + [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn +[14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn +[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn +[12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn +[11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst +[10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst +[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn +[8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn + 8 + 8 + read-write + + + HP_PO_RSTN_BYPASS_CTRL + [31] 1'b1: po_rstn bypass sys_sw_rstn +[30] 1'b1: po_rstn bypass hp_wdt_sys_rstn +[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn +[28] 1'b1: po_rstn bypass hp_sdio_sys_rstn +[27] 1'b1: po_rstn bypass usb_jtag_chip_rst +[26] 1'b1: po_rstn bypass usb_uart_chip_rst +[25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn +[24] 1'b1: po_rstn bypass efuse_err_rstn + 24 + 8 + read-write + + + + + RNG_DATA + rng data register + 0x1A4 + 0x20 + + + RND_DATA + result of rng output + 0 + 32 + read-only + + + + + LP_CORE_AHB_TIMEOUT + need_des + 0x1B0 + 0x20 + 0x007FFFFF + + + EN + set this field to 1 to enable lp core ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ahb bus timeout threshold + 1 + 16 + read-write + + + LP2HP_AHB_TIMEOUT_EN + set this field to 1 to enable lp2hp ahb timeout handle + 17 + 1 + read-write + + + LP2HP_AHB_TIMEOUT_THRES + This field used to set lp2hp ahb bus timeout threshold + 18 + 5 + read-write + + + + + LP_CORE_IBUS_TIMEOUT + need_des + 0x1B4 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ibus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_DBUS_TIMEOUT + need_des + 0x1B8 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core dbus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_ERR_RESP_DIS + need_des + 0x1BC + 0x20 + + + LP_CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + RNG_CFG + rng cfg register + 0x1C0 + 0x20 + 0x00000003 + + + RNG_TIMER_EN + enable rng timer + 0 + 1 + read-write + + + RNG_TIMER_PSCALE + configure ng timer pscale + 1 + 8 + read-write + + + RNG_SAR_ENABLE + enable rng_saradc + 9 + 1 + read-write + + + RNG_SAR_DATA + debug rng sar sample cnt + 16 + 13 + read-only + + + + + + + LP_ANA_PERI + LP_ANA_PERI Peripheral + LP_ANA_PERI + 0x50113000 + + 0x0 + 0x140 + registers + + + LP_ANA + 8 + + + + LP_ANA_BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + LP_ANA_BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + LP_ANA_BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + LP_ANA_BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + LP_ANA_BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_VDD_SOURCE_CNTL + need_des + 0x8 + 0x20 + 0x040000FF + + + LP_ANA_DETMODE_SEL + need_des + 0 + 8 + read-write + + + LP_ANA_VGOOD_EVENT_RECORD + need_des + 8 + 8 + read-only + + + LP_ANA_VBAT_EVENT_RECORD_CLR + need_des + 16 + 8 + write-only + + + LP_ANA_BOD_SOURCE_ENA + need_des + 24 + 8 + read-write + + + + + LP_ANA_VDDBAT_BOD_CNTL + need_des + 0xC + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_VDDBAT_CHARGE_CNTL + need_des + 0x10 + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_CK_GLITCH_CNTL + need_des + 0x14 + 0x20 + + + LP_ANA_CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_PG_GLITCH_CNTL + need_des + 0x18 + 0x20 + + + LP_ANA_POWER_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_FIB_ENABLE + need_des + 0x1C + 0x20 + 0xFFFFFFFF + + + LP_ANA_ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + LP_ANA_INT_RAW + need_des + 0x20 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_ST + need_des + 0x24 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST + need_des + 27 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + need_des + 28 + 1 + read-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ST + need_des + 29 + 1 + read-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST + need_des + 30 + 1 + read-only + + + LP_ANA_BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_INT_ENA + need_des + 0x28 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_CLR + need_des + 0x2C + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + need_des + 27 + 1 + write-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + need_des + 28 + 1 + write-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR + need_des + 29 + 1 + write-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR + need_des + 30 + 1 + write-only + + + LP_ANA_BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_LP_INT_RAW + need_des + 0x30 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_ST + need_des + 0x34 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_LP_INT_ENA + need_des + 0x38 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_CLR + need_des + 0x3C + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM + need_des + 0xFC + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL1 + need_des + 0x100 + 0x20 + 0x00080000 + + + LP_ANA_TOUCH_SHIELD_PAD_EN + need_des + 0 + 1 + read-write + + + LP_ANA_TOUCH_INACTIVE_CONNECTION + need_des + 1 + 1 + read-write + + + LP_ANA_TOUCH_SCAN_PAD_MAP + need_des + 2 + 15 + read-write + + + LP_ANA_TOUCH_XPD_WAIT + need_des + 17 + 15 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL2 + need_des + 0x104 + 0x20 + 0x37BFFFC0 + + + LP_ANA_TOUCH_TIMEOUT_NUM + need_des + 6 + 16 + read-write + + + LP_ANA_TOUCH_TIMEOUT_EN + need_des + 22 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RING + need_des + 23 + 4 + read-write + + + LP_ANA_FREQ_SCAN_EN + need_des + 27 + 1 + read-write + + + LP_ANA_FREQ_SCAN_CNT_LIMIT + need_des + 28 + 2 + read-write + + + + + LP_ANA_TOUCH_WORK + need_des + 0x108 + 0x20 + + + LP_ANA_DIV_NUM2 + need_des + 16 + 3 + read-write + + + LP_ANA_DIV_NUM1 + need_des + 19 + 3 + read-write + + + LP_ANA_DIV_NUM0 + need_des + 22 + 3 + read-write + + + LP_ANA_TOUCH_OUT_SEL + need_des + 25 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RESET + need_des + 26 + 1 + write-only + + + LP_ANA_TOUCH_OUT_GATE + need_des + 27 + 1 + read-write + + + + + LP_ANA_TOUCH_WORK_MEAS_NUM + need_des + 0x10C + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_FILTER1 + need_des + 0x110 + 0x20 + 0x6A0A0200 + + + LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN + Reserved + 0 + 1 + read-write + + + LP_ANA_TOUCH_HYSTERESIS + need_des + 1 + 2 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_THRES + need_des + 3 + 2 + read-write + + + LP_ANA_TOUCH_NOISE_THRES + need_des + 5 + 2 + read-write + + + LP_ANA_TOUCH_SMOOTH_LVL + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_JITTER_STEP + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FILTER_MODE + need_des + 13 + 3 + read-write + + + LP_ANA_TOUCH_FILTER_EN + need_des + 16 + 1 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_LIMIT + need_des + 17 + 4 + read-write + + + LP_ANA_TOUCH_APPROACH_LIMIT + need_des + 21 + 8 + read-write + + + LP_ANA_TOUCH_DEBOUNCE_LIMIT + need_des + 29 + 3 + read-write + + + + + LP_ANA_TOUCH_FILTER2 + need_des + 0x114 + 0x20 + 0x1FFF8000 + + + LP_ANA_TOUCH_OUTEN + need_des + 15 + 15 + read-write + + + LP_ANA_TOUCH_BYPASS_NOISE_THRES + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_FILTER3 + need_des + 0x118 + 0x20 + + + LP_ANA_TOUCH_BASELINE_SW + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_UPDATE_BASELINE_SW + need_des + 16 + 1 + write-only + + + + + LP_ANA_TOUCH_SLP0 + need_des + 0x11C + 0x20 + 0x001E0000 + + + LP_ANA_TOUCH_SLP_TH0 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_CHANNEL_CLR + need_des + 16 + 1 + write-only + + + LP_ANA_TOUCH_SLP_PAD + need_des + 17 + 4 + read-write + + + + + LP_ANA_TOUCH_SLP1 + need_des + 0x120 + 0x20 + + + LP_ANA_TOUCH_SLP_TH2 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_TH1 + need_des + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_CLR + need_des + 0x124 + 0x20 + + + LP_ANA_TOUCH_CHANNEL_CLR + need_des + 0 + 15 + write-only + + + LP_ANA_TOUCH_STATUS_CLR + need_des + 15 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH + need_des + 0x128 + 0x20 + 0x00000FFF + + + PAD0 + need_des + 0 + 4 + read-write + + + PAD1 + need_des + 4 + 4 + read-write + + + PAD2 + need_des + 8 + 4 + read-write + + + LP_ANA_TOUCH_SLP_APPROACH_EN + need_des + 12 + 1 + read-write + + + + + LP_ANA_TOUCH_FREQ0_SCAN_PARA + need_des + 0x12C + 0x20 + + + LP_ANA_TOUCH_FREQ0_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ0_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ0_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ1_SCAN_PARA + need_des + 0x130 + 0x20 + + + LP_ANA_TOUCH_FREQ1_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ1_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ1_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ2_SCAN_PARA + need_des + 0x134 + 0x20 + + + LP_ANA_TOUCH_FREQ2_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ2_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ2_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_ANA_PARA + need_des + 0x138 + 0x20 + + + LP_ANA_TOUCH_TOUCH_BUF_DRV + need_des + 0 + 3 + read-write + + + LP_ANA_TOUCH_TOUCH_EN_CAL + need_des + 3 + 1 + read-write + + + LP_ANA_TOUCH_TOUCH_DCAP_CAL + need_des + 4 + 7 + read-write + + + + + LP_ANA_TOUCH_MUX0 + need_des + 0x13C + 0x20 + 0x20000000 + + + LP_ANA_TOUCH_DATA_SEL + need_des + 8 + 2 + read-write + + + LP_ANA_TOUCH_FREQ_SEL + need_des + 10 + 2 + read-write + + + LP_ANA_TOUCH_BUFSEL + need_des + 12 + 15 + read-write + + + LP_ANA_TOUCH_DONE_EN + need_des + 27 + 1 + read-write + + + LP_ANA_TOUCH_DONE_FORCE + need_des + 28 + 1 + read-write + + + LP_ANA_TOUCH_FSM_EN + need_des + 29 + 1 + read-write + + + LP_ANA_TOUCH_START_EN + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_START_FORCE + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_MUX1 + need_des + 0x140 + 0x20 + + + LP_ANA_TOUCH_START + need_des + 0 + 15 + read-write + + + LP_ANA_TOUCH_XPD + need_des + 15 + 15 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH0 + need_des + 0x144 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH1 + need_des + 0x148 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH2 + need_des + 0x14C + 0x20 + + + LP_ANA_TOUCH_PAD0_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH0 + need_des + 0x150 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH1 + need_des + 0x154 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH2 + need_des + 0x158 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH0 + need_des + 0x15C + 0x20 + + + LP_ANA_TOUCH_PAD2_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH1 + need_des + 0x160 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH2 + need_des + 0x164 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH0 + need_des + 0x168 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH1 + need_des + 0x16C + 0x20 + + + LP_ANA_TOUCH_PAD3_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH2 + need_des + 0x170 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH0 + need_des + 0x174 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH1 + need_des + 0x178 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH2 + need_des + 0x17C + 0x20 + + + LP_ANA_TOUCH_PAD4_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH0 + need_des + 0x180 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH1 + need_des + 0x184 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH2 + need_des + 0x188 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH0 + need_des + 0x18C + 0x20 + + + LP_ANA_TOUCH_PAD6_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH1 + need_des + 0x190 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH2 + need_des + 0x194 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH0 + need_des + 0x198 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH1 + need_des + 0x19C + 0x20 + + + LP_ANA_TOUCH_PAD7_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH2 + need_des + 0x1A0 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH0 + need_des + 0x1A4 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH1 + need_des + 0x1A8 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH2 + need_des + 0x1AC + 0x20 + + + LP_ANA_TOUCH_PAD8_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH0 + need_des + 0x1B0 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH1 + need_des + 0x1B4 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH2 + need_des + 0x1B8 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH0 + need_des + 0x1BC + 0x20 + + + LP_ANA_TOUCH_PAD10_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH1 + need_des + 0x1C0 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH2 + need_des + 0x1C4 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH0 + need_des + 0x1C8 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH1 + need_des + 0x1CC + 0x20 + + + LP_ANA_TOUCH_PAD11_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH2 + need_des + 0x1D0 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH0 + need_des + 0x1D4 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH1 + need_des + 0x1D8 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH2 + need_des + 0x1DC + 0x20 + + + LP_ANA_TOUCH_PAD12_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH0 + need_des + 0x1E0 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH1 + need_des + 0x1E4 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH2 + need_des + 0x1E8 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH0 + need_des + 0x1EC + 0x20 + + + LP_ANA_TOUCH_PAD14_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH1 + need_des + 0x1F0 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH2 + need_des + 0x1F4 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_DATE + need_des + 0x3FC + 0x20 + 0x00230420 + + + LP_ANA_LP_ANA_DATE + need_des + 0 + 31 + read-write + + + LP_ANA_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON_CLKRST + LP_AON_CLKRST Peripheral + LP_AON_CLKRST + 0x50111000 + + 0x0 + 0x54 + registers + + + + LP_AONCLKRST_LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + LP_AONCLKRST_SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + LP_AONCLKRST_FAST_CLK_SEL + need_des + 2 + 2 + read-write + + + LP_AONCLKRST_LP_PERI_DIV_NUM + need_des + 4 + 6 + read-write + + + LP_AONCLKRST_ANA_SEL_REF_PLL8M + need_des + 10 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_PO_EN + need_des + 0x4 + 0x20 + + + LP_AONCLKRST_CLK_CORE_EFUSE_OEN + need_des + 0 + 1 + read-write + + + LP_AONCLKRST_CLK_LP_BUS_OEN + need_des + 1 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_SLOW_OEN + need_des + 2 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_FAST_OEN + need_des + 3 + 1 + read-write + + + LP_AONCLKRST_CLK_SLOW_OEN + need_des + 4 + 1 + read-write + + + LP_AONCLKRST_CLK_FAST_OEN + need_des + 5 + 1 + read-write + + + LP_AONCLKRST_CLK_FOSC_OEN + need_des + 6 + 1 + read-write + + + LP_AONCLKRST_CLK_RC32K_OEN + need_des + 7 + 1 + read-write + + + LP_AONCLKRST_CLK_SXTAL_OEN + need_des + 8 + 1 + read-write + + + LP_AONCLKRST_CLK_SOSC_OEN + 1'b1: probe sosc clk on +1'b0: probe sosc clk off + 9 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_EN + need_des + 0x8 + 0x20 + 0x08000000 + + + LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_CK_EN_LP_RAM + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_ETM_EVENT_TICK_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_PLL8M_CLK_FORCE_ON + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_XTAL_CLK_FORCE_ON + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_FOSC_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_LP_RST_EN + need_des + 0xC + 0x20 + + + LP_AONCLKRST_RST_EN_LP_HUK + need_des + 24 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_ANAPERI + need_des + 25 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_WDT + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_TIMER + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RTC + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_MAILBOX + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_AONEFUSEREG + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RAM + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_RESET_CAUSE + need_des + 0x10 + 0x20 + 0x02000000 + + + LP_AONCLKRST_LPCORE_RESET_CAUSE + 6'h1: POR reset +6'h9: PMU LP PERI power down reset +6'ha: PMU LP CPU reset +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: software reset + 0 + 6 + read-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG + need_des + 6 + 1 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 7 + 6 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG + need_des + 13 + 1 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 14 + 6 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG + need_des + 20 + 1 + read-only + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK + 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause + 25 + 1 + read-write + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR + need_des + 26 + 1 + write-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG_CLR + need_des + 27 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR + need_des + 28 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR + need_des + 30 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL0 + need_des + 0x14 + 0x20 + 0x80028002 + + + LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN + write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature + 0 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH + need_des + 1 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN + write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature + 4 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_WAIT + need_des + 5 + 7 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_EN + need_des + 12 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_SW_RESET + need_des + 13 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET + need_des + 14 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 15 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN + write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature + 16 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH + need_des + 17 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN + write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature + 20 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_WAIT + need_des + 21 + 7 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_SW_RESET + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 31 + 1 + read-write + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL1 + need_des + 0x18 + 0x20 + + + LP_AONCLKRST_HPCORE0_SW_STALL_CODE + HP core0 software stall when set to 8'h86 + 16 + 8 + read-write + + + LP_AONCLKRST_HPCORE1_SW_STALL_CODE + HP core1 software stall when set to 8'h86 + 24 + 8 + read-write + + + + + LP_AONCLKRST_FOSC_CNTL + need_des + 0x1C + 0x20 + 0x64000000 + + + LP_AONCLKRST_FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_RC32K_CNTL + need_des + 0x20 + 0x20 + 0x0000028A + + + LP_AONCLKRST_RC32K_DFREQ + need_des + 0 + 32 + read-write + + + + + LP_AONCLKRST_SOSC_CNTL + need_des + 0x24 + 0x20 + 0x2B000000 + + + LP_AONCLKRST_SOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_CLK_TO_HP + need_des + 0x28 + 0x20 + 0xF0000000 + + + LP_AONCLKRST_ICG_HP_XTAL32K + reserved + 28 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_SOSC + reserved + 29 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_OSC32K + reserved + 30 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_FOSC + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_LPMEM_FORCE + need_des + 0x2C + 0x20 + + + LP_AONCLKRST_LPMEM_CLK_FORCE_ON + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_XTAL32K + need_des + 0x30 + 0x20 + 0x66C00000 + + + LP_AONCLKRST_DRES_XTAL32K + need_des + 22 + 3 + read-write + + + LP_AONCLKRST_DGM_XTAL32K + need_des + 25 + 3 + read-write + + + LP_AONCLKRST_DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + need_des + 0x34 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HP_CLK_CTRL + HP Clock Control Register. + 0x40 + 0x20 + 0x1FFFFFFC + + + LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL + HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + 0 + 2 + read-write + + + LP_AONCLKRST_HP_ROOT_CLK_EN + HP SoC Root Clock Enable. + 2 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN + PARLIO TX Clock From Pad Enable. + 3 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN + PARLIO RX Clock From Pad Enable. + 4 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN + UART4 SLP Clock From Pad Enable. + 5 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN + UART3 SLP Clock From Pad Enable. + 6 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN + UART2 SLP Clock From Pad Enable. + 7 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN + UART1 SLP Clock From Pad Enable. + 8 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN + UART0 SLP Clock From Pad Enable. + 9 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN + I2S2 MCLK Clock From Pad Enable. + 10 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN + I2S1 MCLK Clock From Pad Enable. + 11 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN + I2S0 MCLK Clock From Pad Enable. + 12 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN + EMAC RX Clock From Pad Enable. + 13 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN + EMAC TX Clock From Pad Enable. + 14 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN + EMAC TXRX Clock From Pad Enable. + 15 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_32K_CLK_EN + XTAL 32K Clock Enable. + 16 + 1 + read-write + + + LP_AONCLKRST_HP_RC_32K_CLK_EN + RC 32K Clock Enable. + 17 + 1 + read-write + + + LP_AONCLKRST_HP_SOSC_150K_CLK_EN + SOSC 150K Clock Enable. + 18 + 1 + read-write + + + LP_AONCLKRST_HP_PLL_8M_CLK_EN + PLL 8M Clock Enable. + 19 + 1 + read-write + + + LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN + AUDIO PLL Clock Enable. + 20 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN + SDIO PLL2 Clock Enable. + 21 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN + SDIO PLL1 Clock Enable. + 22 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN + SDIO PLL0 Clock Enable. + 23 + 1 + read-write + + + LP_AONCLKRST_HP_FOSC_20M_CLK_EN + FOSC 20M Clock Enable. + 24 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_40M_CLK_EN + XTAL 40M Clock Enalbe. + 25 + 1 + read-write + + + LP_AONCLKRST_HP_CPLL_400M_CLK_EN + CPLL 400M Clock Enable. + 26 + 1 + read-write + + + LP_AONCLKRST_HP_SPLL_480M_CLK_EN + SPLL 480M Clock Enable. + 27 + 1 + read-write + + + LP_AONCLKRST_HP_MPLL_500M_CLK_EN + MPLL 500M Clock Enable. + 28 + 1 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL0 + HP USB Clock Reset Control Register. + 0x44 + 0x20 + 0x09C4C27A + + + LP_AONCLKRST_USB_OTG20_SLEEP_MODE + unused. + 0 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN + unused. + 1 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_SLEEP_MODE + unused. + 2 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN + unused. + 3 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_48M_CLK_EN + usb otg11 fs phy clock enable. + 4 + 1 + read-write + + + LP_AONCLKRST_USB_DEVICE_48M_CLK_EN + usb device fs phy clock enable. + 5 + 1 + read-write + + + LP_AONCLKRST_USB_48M_DIV_NUM + usb 480m to 25m divide number. + 6 + 8 + read-write + + + LP_AONCLKRST_USB_25M_DIV_NUM + usb 500m to 25m divide number. + 14 + 8 + read-write + + + LP_AONCLKRST_USB_12M_DIV_NUM + usb 480m to 12m divide number. + 22 + 8 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL1 + HP USB Clock Reset Control Register. + 0x48 + 0x20 + 0xC0000000 + + + LP_AONCLKRST_RST_EN_USB_OTG20_ADP + usb otg20 adp reset en + 0 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20_PHY + usb otg20 phy reset en + 1 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20 + usb otg20 reset en + 2 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG11 + usb org11 reset en + 3 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_DEVICE + usb device reset en + 4 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL + usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + 28 + 2 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN + usb otg20 hs phy refclk enable. + 30 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN + usb otg20 ulpi clock enable. + 31 + 1 + read-write + + + + + LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL + need_des + 0x4C + 0x20 + + + LP_AONCLKRST_RST_EN_SDMMC + hp sdmmc reset en + 28 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_SDMMC + hp sdmmc force norst + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_EMAC + hp emac reset en + 30 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_EMAC + hp emac force norst + 31 + 1 + read-write + + + + + LP_AONCLKRST_DATE + need_des + 0x3FC + 0x20 + + + LP_AONCLKRST_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_GPIO + Low-power General Purpose Input/Output + LP_GPIO + 0x5012A000 + + 0x0 + 0xEC + registers + + + LP_GPIO + 10 + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230323 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + OUT + Reserved + 0x8 + 0x20 + + + REG_GPIO_OUT_DATA + Reserved + 0 + 16 + read-write + + + + + OUT_W1TS + Reserved + 0xC + 0x20 + + + REG_GPIO_OUT_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + OUT_W1TC + Reserved + 0x10 + 0x20 + + + REG_GPIO_OUT_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + ENABLE + Reserved + 0x14 + 0x20 + + + REG_GPIO_ENABLE_DATA + Reserved + 0 + 16 + read-write + + + + + ENABLE_W1TS + Reserved + 0x18 + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + ENABLE_W1TC + Reserved + 0x1C + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS + Reserved + 0x20 + 0x20 + + + REG_GPIO_STATUS_DATA + Reserved + 0 + 16 + read-write + + + + + STATUS_W1TS + Reserved + 0x24 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + STATUS_W1TC + Reserved + 0x28 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS_NEXT + Reserved + 0x2C + 0x20 + + + REG_GPIO_STATUS_INTERRUPT_NEXT + Reserved + 0 + 16 + read-only + + + + + IN + Reserved + 0x30 + 0x20 + + + REG_GPIO_IN_DATA_NEXT + Reserved + 0 + 16 + read-only + + + + + PIN0 + Reserved + 0x34 + 0x20 + + + REG_GPIO_PIN0_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN0_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN0_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPIO_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN1 + Reserved + 0x38 + 0x20 + + + REG_GPIO_PIN1_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN1_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN1_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI1_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN2 + Reserved + 0x3C + 0x20 + + + REG_GPIO_PIN2_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN2_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN2_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI2_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN3 + Reserved + 0x40 + 0x20 + + + REG_GPIO_PIN3_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN3_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN3_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI3_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN4 + Reserved + 0x44 + 0x20 + + + REG_GPIO_PIN4_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN4_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN4_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI4_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN5 + Reserved + 0x48 + 0x20 + + + REG_GPIO_PIN5_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN5_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN5_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI5_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN6 + Reserved + 0x4C + 0x20 + + + REG_GPIO_PIN6_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN6_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN6_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI6_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN7 + Reserved + 0x50 + 0x20 + + + REG_GPIO_PIN7_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN7_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN7_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI7_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN8 + Reserved + 0x54 + 0x20 + + + REG_GPIO_PIN8_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN8_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN8_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI8_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN9 + Reserved + 0x58 + 0x20 + + + REG_GPIO_PIN9_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN9_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN9_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI9_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN10 + Reserved + 0x5C + 0x20 + + + REG_GPIO_PIN10_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN10_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN10_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI10_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN11 + Reserved + 0x60 + 0x20 + + + REG_GPIO_PIN11_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN11_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN11_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI11_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN12 + Reserved + 0x64 + 0x20 + + + REG_GPIO_PIN12_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN12_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN12_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI12_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN13 + Reserved + 0x68 + 0x20 + + + REG_GPIO_PIN13_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN13_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN13_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI13_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN14 + Reserved + 0x6C + 0x20 + + + REG_GPIO_PIN14_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN14_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN14_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI14_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN15 + Reserved + 0x70 + 0x20 + + + REG_GPIO_PIN15_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN15_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN15_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI15_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + FUNC0_IN_SEL_CFG + Reserved + 0x74 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC0_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG0_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_IN_SEL + reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0 + 2 + 6 + read-write + + + + + FUNC1_IN_SEL_CFG + Reserved + 0x78 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC1_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG1_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC2_IN_SEL_CFG + Reserved + 0x7C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC2_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG2_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC3_IN_SEL_CFG + Reserved + 0x80 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC3_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG3_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC4_IN_SEL_CFG + Reserved + 0x84 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC4_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG4_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC5_IN_SEL_CFG + Reserved + 0x88 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC5_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG5_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC6_IN_SEL_CFG + Reserved + 0x8C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC6_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG6_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC7_IN_SEL_CFG + Reserved + 0x90 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC7_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG7_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC8_IN_SEL_CFG + Reserved + 0x94 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC8_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG8_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC9_IN_SEL_CFG + Reserved + 0x98 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC9_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG9_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC10_IN_SEL_CFG + Reserved + 0x9C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC10_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG10_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC11_IN_SEL_CFG + Reserved + 0xA0 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC11_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG11_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC12_IN_SEL_CFG + Reserved + 0xA4 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC12_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG12_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC13_IN_SEL_CFG + Reserved + 0xA8 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC13_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG13_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC0_OUT_SEL_CFG + Reserved + 0xF4 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC0_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC0_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_SEL + reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad + 3 + 6 + read-write + + + + + FUNC1_OUT_SEL_CFG + Reserved + 0xF8 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC1_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC1_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC2_OUT_SEL_CFG + Reserved + 0xFC + 0x20 + 0x00000100 + + + REG_GPIO_FUNC2_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC2_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC3_OUT_SEL_CFG + Reserved + 0x100 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC3_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC3_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC4_OUT_SEL_CFG + Reserved + 0x104 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC4_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC4_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC5_OUT_SEL_CFG + Reserved + 0x108 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC5_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC5_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC6_OUT_SEL_CFG + Reserved + 0x10C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC6_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC6_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC7_OUT_SEL_CFG + Reserved + 0x110 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC7_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC7_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC8_OUT_SEL_CFG + Reserved + 0x114 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC8_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC8_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC9_OUT_SEL_CFG + Reserved + 0x118 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC9_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC9_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC10_OUT_SEL_CFG + Reserved + 0x11C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC10_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC10_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC11_OUT_SEL_CFG + Reserved + 0x120 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC11_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC11_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC12_OUT_SEL_CFG + Reserved + 0x124 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC12_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC12_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC13_OUT_SEL_CFG + Reserved + 0x128 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC13_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC13_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC14_OUT_SEL_CFG + Reserved + 0x12C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC14_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC14_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC15_OUT_SEL_CFG + Reserved + 0x130 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC15_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC15_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + + + LP_I2C0 + Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C + 0x50122000 + + 0x0 + 0x88 + registers + + + LP_I2C0 + 11 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 5 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 5 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 4 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 4 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 4 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to anable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to anable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to anable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 1 + 5 + read-write + + + SCL_PD_EN + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 7 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_I2S0 + Low-power I2S (Inter-IC Sound) Controller 0 + LP_I2S + 0x50125000 + + 0x0 + 0x98 + registers + + + LP_I2S0 + 12 + + + + VAD_CONF + I2S VAD Configure register + 0x0 + 0x20 + + + VAD_EN + VAD enable register + 0 + 1 + read-write + + + VAD_RESET + VAD reset register + 1 + 1 + write-only + + + VAD_FORCE_START + VAD force start register. + 2 + 1 + write-only + + + + + VAD_RESULT + I2S VAD Result register + 0x4 + 0x20 + + + VAD_FLAG + Reg vad flag observe signal + 0 + 1 + read-only + + + ENERGY_ENOUGH + Reg energy enough observe signal + 1 + 1 + read-only + + + + + RX_MEM_CONF + I2S VAD Observe register + 0x8 + 0x20 + 0x00007E00 + + + RX_MEM_FIFO_CNT + The number of data in the rx mem + 0 + 9 + read-only + + + RX_MEM_THRESHOLD + I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold + 9 + 8 + read-write + + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_RAW + The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + VAD_DONE_INT_RAW + The raw interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + VAD_RESET_DONE_INT_RAW + The raw interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_RAW + The raw interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_ST + The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + LP_VAD_DONE_INT_ST + The masked interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + LP_VAD_RESET_DONE_INT_ST + The masked interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_ST + The masked interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-write + + + RX_FIFOMEM_UDF_INT_ENA + The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-write + + + LP_VAD_DONE_INT_ENA + The interrupt enable bit for the vad_done_int interrupt + 3 + 1 + read-write + + + LP_VAD_RESET_DONE_INT_ENA + The interrupt enable bit for the vad_reset_done_int interrupt + 4 + 1 + read-write + + + RX_MEM_THRESHOLD_INT_ENA + The interrupt enable bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 1 + 1 + write-only + + + RX_FIFOMEM_UDF_INT_CLR + Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + write-only + + + LP_VAD_DONE_INT_CLR + Set this bit to clear the vad_done_int interrupt + 3 + 1 + write-only + + + LP_VAD_RESET_DONE_INT_CLR + Set this bit to clear the vad_reset_done_int interrupt + 4 + 1 + write-only + + + RX_MEM_THRESHOLD_INT_CLR + Set this bit to clear the rx_mem_threshold_int interrupt + 5 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_FIFOMEM_RESET + Set this bit to reset Rx Syncfifomem + 4 + 1 + write-only + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x00000003 + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + RX_PDM_CONF + I2S RX configure register + 0x70 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + ECO_LOW + I2S ECO register + 0x74 + 0x20 + + + RDN_ECO_LOW + logic low eco registers + 0 + 32 + read-write + + + + + ECO_HIGH + I2S ECO register + 0x78 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + logic high eco registers + 0 + 32 + read-write + + + + + ECO_CONF + I2S ECO register + 0x7C + 0x20 + + + RDN_ENA + enable rdn counter bit + 0 + 1 + read-write + + + RDN_RESULT + rdn result + 1 + 1 + read-only + + + + + VAD_PARAM0 + I2S VAD Parameter register + 0x80 + 0x20 + 0x00C81388 + + + PARAM_MIN_ENERGY + VAD parameter + 0 + 16 + read-write + + + PARAM_INIT_FRAME_NUM + VAD parameter + 16 + 9 + read-write + + + + + VAD_PARAM1 + I2S VAD Parameter register + 0x84 + 0x20 + 0x281E1E43 + + + PARAM_MIN_SPEECH_COUNT + VAD parameter + 0 + 4 + read-write + + + PARAM_MAX_SPEECH_COUNT + VAD parameter + 4 + 7 + read-write + + + PARAM_HANGOVER_SPEECH + VAD parameter + 11 + 5 + read-write + + + PARAM_HANGOVER_SILENT + VAD parameter + 16 + 8 + read-write + + + PARAM_MAX_OFFSET + VAD parameter + 24 + 7 + read-write + + + PARAM_SKIP_BAND_ENERGY + Set 1 to skip band energy check. + 31 + 1 + read-write + + + + + VAD_PARAM2 + I2S VAD Parameter register + 0x88 + 0x20 + 0x7EB86666 + + + PARAM_NOISE_AMP_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_AMP_UP + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM3 + I2S VAD Parameter register + 0x8C + 0x20 + 0x7D717FDF + + + PARAM_NOISE_SPE_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_SPE_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM4 + I2S VAD Parameter register + 0x90 + 0x20 + 0x799A6666 + + + PARAM_NOISE_SPE_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_DOWN + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM5 + I2S VAD Parameter register + 0x94 + 0x20 + 0x7C287D71 + + + PARAM_NOISE_MEAN_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM6 + I2S VAD Parameter register + 0x98 + 0x20 + 0xB4007D00 + + + PARAM_NOISE_STD_FS_THSL + Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5 + 0 + 16 + read-write + + + PARAM_NOISE_STD_FS_THSH + Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5 + 16 + 16 + read-write + + + + + VAD_PARAM7 + I2S VAD Parameter register + 0x9C + 0x20 + 0x01487EB8 + + + PARAM_THRES_UPD_BASE + VAD parameter + 0 + 16 + read-write + + + PARAM_THRES_UPD_VARY + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM8 + I2S VAD Parameter register + 0xA0 + 0x20 + 0x20005040 + + + PARAM_THRES_UPD_BDL + Noise_std boundary low when updating threshold. + 0 + 8 + read-write + + + PARAM_THRES_UPD_BDH + Noise_std boundary high when updating threshold. + 8 + 8 + read-write + + + PARAM_FEATURE_BURST + VAD parameter + 16 + 16 + read-write + + + + + VAD_OB0 + I2S VAD Observe register + 0xB0 + 0x20 + + + SPEECH_COUNT_OB + Reg silent count observe + 0 + 8 + read-only + + + SILENT_COUNT_OB + Reg speech count observe + 8 + 8 + read-only + + + MAX_SIGNAL0_OB + Reg max signal0 observe + 16 + 16 + read-only + + + + + VAD_OB1 + I2S VAD Observe register + 0xB4 + 0x20 + + + MAX_SIGNAL1_OB + Reg max signal1 observe + 0 + 16 + read-only + + + MAX_SIGNAL2_OB + Reg max signal2 observe + 16 + 16 + read-only + + + + + VAD_OB2 + I2S VAD Observe register + 0xB8 + 0x20 + + + NOISE_AMP_OB + Reg noise_amp observe signal + 0 + 32 + read-only + + + + + VAD_OB3 + I2S VAD Observe register + 0xBC + 0x20 + + + NOISE_MEAN_OB + Reg noise_mean observe signal + 0 + 32 + read-only + + + + + VAD_OB4 + I2S VAD Observe register + 0xC0 + 0x20 + + + NOISE_STD_OB + Reg noise_std observe signal + 0 + 32 + read-only + + + + + VAD_OB5 + I2S VAD Observe register + 0xC4 + 0x20 + + + OFFSET_OB + Reg offset observe signal + 0 + 32 + read-only + + + + + VAD_OB6 + I2S VAD Observe register + 0xC8 + 0x20 + + + THRESHOLD_OB + Reg threshold observe signal + 0 + 32 + read-only + + + + + VAD_OB7 + I2S VAD Observe register + 0xCC + 0x20 + + + ENERGY_LOW_OB + Reg energy bit 31~0 observe signal + 0 + 32 + read-only + + + + + VAD_OB8 + I2S VAD Observe register + 0xD0 + 0x20 + + + ENERGY_HIGH_OB + Reg energy bit 63~32 observe signal + 0 + 32 + read-only + + + + + CLK_GATE + Clock gate register + 0xF8 + 0x20 + 0x0000000A + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + VAD_CG_FORCE_ON + VAD clock gate force on register + 1 + 1 + read-write + + + RX_MEM_CG_FORCE_ON + I2S rx mem clock gate force on register + 2 + 1 + read-write + + + RX_REG_CG_FORCE_ON + I2S rx reg clock gate force on register + 3 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + LP_IO_MUX + Low-power Input/Output Multiplexer + LP_IOMUX + 0x5012B000 + + 0x0 + 0x54 + registers + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230313 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + PAD0 + Reserved + 0x8 + 0x20 + 0x00000002 + + + REG_PAD0_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD0_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD0_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD0_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD0_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD0_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD0_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD0_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD0_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD0_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD1 + Reserved + 0xC + 0x20 + 0x00000002 + + + REG_PAD1_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD1_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD1_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD1_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD1_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD1_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD1_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD1_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD1_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD2 + Reserved + 0x10 + 0x20 + 0x00000002 + + + REG_PAD2_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD2_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD2_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD2_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD2_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD2_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD2_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD2_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD2_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD3 + Reserved + 0x14 + 0x20 + 0x00000002 + + + REG_PAD3_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD3_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD3_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD3_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD3_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD3_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD3_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD3_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD3_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD3_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD4 + Reserved + 0x18 + 0x20 + 0x00000002 + + + REG_PAD4_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD4_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD4_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD4_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD4_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD4_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD4_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD4_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD4_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD4_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD5 + Reserved + 0x1C + 0x20 + 0x00000002 + + + REG_PAD5_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD5_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD5_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD5_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD5_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD5_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD5_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD5_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD5_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD5_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD6 + Reserved + 0x20 + 0x20 + 0x00000002 + + + REG_PAD6_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD6_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD6_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD6_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD6_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD6_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD6_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD6_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD6_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD6_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD7 + Reserved + 0x24 + 0x20 + 0x00000002 + + + REG_PAD7_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD7_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD7_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD7_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD7_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD7_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD7_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD7_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD7_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD7_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD8 + Reserved + 0x28 + 0x20 + 0x00000002 + + + REG_PAD8_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD8_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD8_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD8_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD8_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD8_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD8_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD8_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD8_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD8_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD9 + Reserved + 0x2C + 0x20 + 0x00000002 + + + REG_PAD9_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD9_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD9_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD9_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD9_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD9_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD9_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD9_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD9_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD9_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD10 + Reserved + 0x30 + 0x20 + 0x00000002 + + + REG_PAD10_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD10_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD10_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD10_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD10_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD10_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD10_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD10_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD10_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD10_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD11 + Reserved + 0x34 + 0x20 + 0x00000002 + + + REG_PAD11_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD11_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD11_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD11_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD11_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD11_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD11_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD11_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD11_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD11_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD120 + Reserved + 0x38 + 0x20 + 0x00000002 + + + REG_PAD12_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD12_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD12_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD12_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD12_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD12_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD12_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD12_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD12_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD12_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD13 + Reserved + 0x3C + 0x20 + 0x00000002 + + + REG_PAD13_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD13_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD13_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD13_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD13_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD13_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD13_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD13_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD13_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD13_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD14 + Reserved + 0x40 + 0x20 + 0x00000002 + + + REG_PAD14_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD14_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD14_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD14_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD14_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD14_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD14_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD14_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD14_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD14_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD15 + Reserved + 0x44 + 0x20 + 0x00000002 + + + REG_PAD15_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD15_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD15_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD15_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD15_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD15_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD15_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD15_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD15_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD15_FILTER_EN + need des + 11 + 1 + read-write + + + + + EXT_WAKEUP0_SEL + Reserved + 0x48 + 0x20 + + + REG_XTL_EXT_CTR_SEL + select LP GPIO 0 ~ 15 to control XTAL + 0 + 5 + read-write + + + REG_EXT_WAKEUP0_SEL + Reserved + 5 + 5 + read-write + + + + + LP_PAD_HOLD + Reserved + 0x4C + 0x20 + + + REG_LP_GPIO_HOLD + Reserved + 0 + 16 + read-write + + + + + LP_PAD_HYS + Reserved + 0x50 + 0x20 + + + REG_LP_GPIO_HYS + Reserved + 0 + 16 + read-write + + + + + + + LP_UART + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART + 0x50121000 + + 0x0 + 0x84 + registers + + + LP_UART + 16 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + Configuration register 0 + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + MCPWM + 0x500C0000 + + 0x0 + 0x14C + registers + + + PWM0 + 38 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). + 0 + 8 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG0 + PWM timer%s period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER_PRESCALE + Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER_PERIOD + Configures the period shadow of PWM timer%s + 8 + 16 + read-write + + + TIMER_PERIOD_UPMETHOD + Configures the update method for active register of PWM timer%s period.\\0: Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG1 + PWM timer%s working mode and start/stop control register. + 0x8 + 0x20 + + + TIMER_START + Configures whether or not to start/stop PWM timer%s.\\0: If PWM timer%s starts, then stops at TEZ\\1: If timer%s starts, then stops at TEP\\2: PWM timer%s starts and runs on\\3: Timer%s starts and stops at the next TEZ\\4: Timer0 starts and stops at the next TEP.\\TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER_MOD + Configures the working mode of PWM timer%s.\\0: Freeze\\1: Increase mode\\2: Decrease mode\\3: Up-down mode + 3 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_SYNC + PWM timer%s sync function configuration register. + 0xC + 0x20 + + + TIMER_SYNCI_EN + Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + SW + Configures the generation of software sync. Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER_SYNCO_SEL + Configures the selection of PWM timer%s sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: Invalid, sync_out selects noting + 2 + 2 + read-write + + + TIMER_PHASE + Configures the phase for timer%s reload on sync event. + 4 + 16 + read-write + + + TIMER_PHASE_DIRECTION + Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\0: Increase\\1: Decrease + 20 + 1 + read-write + + + + + 3 + 0x10 + TIMER%s_STATUS + PWM timer%s status register. + 0x10 + 0x20 + + + TIMER_VALUE + Represents current PWM timer%s counter value. + 0 + 16 + read-only + + + TIMER_DIRECTION + Represents current PWM timer%s counter direction.\\0: Increment\\1: Decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection register for PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: Invert + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: Invert + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: Invert + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + PWM operator's timer select register + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 4 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_STMP_CFG + Generator%s time stamp registers A and B transfer status and update method register + 0x3C + 0x20 + + + CMPR_A_UPMETHOD + Configures the update method for PWM generator %s time stamp A's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + CMPR_B_UPMETHOD + Configures the update method for PWM generator %s time stamp B's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + CMPR_A_SHDW_FULL + Represents whether or not generator%s time stamp A's shadow reg is transferred.\\0: A's active reg has been updated with shadow register latest value.\\1: A's shadow reg is filled and waiting to be transferred to A's active reg + 8 + 1 + read-write + + + CMPR_B_SHDW_FULL + Represents whether or not generator%s time stamp B's shadow reg is transferred.\\0: B's active reg has been updated with shadow register latest value.\\1: B's shadow reg is filled and waiting to be transferred to B's active reg + 9 + 1 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_A + Generator%s time stamp A's shadow register + 0x40 + 0x20 + + + CMPR_A + Configures the value of PWM generator %s time stamp A's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_B + Generator%s time stamp B's shadow register + 0x44 + 0x20 + + + CMPR_B + Configures the value of PWM generator %s time stamp B's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_CFG0 + Generator%s fault event T0 and T1 configuration register + 0x48 + 0x20 + + + GEN_CFG_UPMETHOD + Configures update method for PWM generator %s's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + GEN_T0_SEL + Configures source selection for PWM generator %s event_t0, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 4 + 3 + read-write + + + GEN_T1_SEL + Configures source selection for PWM generator %s event_t1, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 7 + 3 + read-write + + + + + 3 + 0x38 + GEN%s_FORCE + Generator%s output signal force mode register. + 0x4C + 0x20 + 0x00000020 + + + GEN_CNTUFORCE_UPMETHOD + Configures update method for continuous software force of PWM generator%s.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B. + 0 + 6 + read-write + + + GEN_A_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 6 + 2 + read-write + + + GEN_B_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 8 + 2 + read-write + + + GEN_A_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN_A_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 11 + 2 + read-write + + + GEN_B_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN_B_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 14 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_A + PWM%s output signal A actions configuration register + 0x50 + 0x20 + + + UTEZ + Configures action on PWM%s A triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s A triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s A triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s A triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s A triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s A triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s A triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s A triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s A triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_B + PWM%s output signal B actions configuration register + 0x54 + 0x20 + + + UTEZ + Configures action on PWM%s B triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s B triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s B triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s B triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s B triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s B triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s B triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s B triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s B triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + DT%s_CFG + Dead time configuration register + 0x58 + 0x20 + 0x00018000 + + + DB_FED_UPMETHOD + Configures update method for FED (Falling edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + DB_RED_UPMETHOD + Configures update method for RED (rising edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + DB_DEB_MODE + Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB_A_OUTSWAP + Configures S6 in table. + 9 + 1 + read-write + + + DB_B_OUTSWAP + Configures S7 in table. + 10 + 1 + read-write + + + DB_RED_INSEL + Configures S4 in table. + 11 + 1 + read-write + + + DB_FED_INSEL + Configures S5 in table. + 12 + 1 + read-write + + + DB_RED_OUTINVERT + Configures S2 in table. + 13 + 1 + read-write + + + DB_FED_OUTINVERT + Configures S3 in table. + 14 + 1 + read-write + + + DB_A_OUTBYPASS + Configures S1 in table. + 15 + 1 + read-write + + + DB_B_OUTBYPASS + Configures S0 in table. + 16 + 1 + read-write + + + DB_CLK_SEL + Configures dead time generator %s clock selection.\\0: PWM_clk\\1: PT_clk + 17 + 1 + read-write + + + + + 3 + 0x38 + DT%s_FED_CFG + Falling edge delay (FED) shadow register + 0x5C + 0x20 + + + DB_FED + Configures shadow register for FED. + 0 + 16 + read-write + + + + + 3 + 0x38 + DT%s_RED_CFG + Rising edge delay (RED) shadow register + 0x60 + 0x20 + + + DB_RED + Configures shadow register for RED. + 0 + 16 + read-write + + + + + 3 + 0x38 + CARRIER%s_CFG + Carrier%s configuration register + 0x64 + 0x20 + + + CHOPPER_EN + Configures whether or not to enable carrier%s.\\0: Bypassed\\1: Enabled + 0 + 1 + read-write + + + CHOPPER_PRESCALE + Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER_DUTY + Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER_OSHTWTH + Configures width of the first pulse. Measurement unit: Periods of the carrier. + 8 + 4 + read-write + + + CHOPPER_OUT_INVERT + Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 12 + 1 + read-write + + + CHOPPER_IN_INVERT + Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 13 + 1 + read-write + + + + + 3 + 0x38 + FH%s_CFG0 + PWM%s A and PWM%s B trip events actions configuration register + 0x68 + 0x20 + + + TZ_SW_CBC + Configures whether or not to enable software force cycle-by-cycle mode action.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TZ_F2_CBC + Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TZ_F1_CBC + Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TZ_F0_CBC + Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TZ_SW_OST + Configures whether or not to enable software force one-shot mode action.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TZ_F2_OST + Configures whether or not event_f2 will trigger one-shot mode action.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TZ_F1_OST + Configures whether or not event_f1 will trigger one-shot mode action.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TZ_F0_OST + Configures whether or not event_f0 will trigger one-shot mode action.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TZ_A_CBC_D + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 8 + 2 + read-write + + + TZ_A_CBC_U + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 10 + 2 + read-write + + + TZ_A_OST_D + Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 12 + 2 + read-write + + + TZ_A_OST_U + Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 14 + 2 + read-write + + + TZ_B_CBC_D + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 16 + 2 + read-write + + + TZ_B_CBC_U + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 18 + 2 + read-write + + + TZ_B_OST_D + Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 20 + 2 + read-write + + + TZ_B_OST_U + Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + FH%s_CFG1 + Software triggers for fault handler actions configuration register + 0x6C + 0x20 + + + TZ_CLR_OST + Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action. + 0 + 1 + read-write + + + TZ_CBCPULSE + Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + 1 + 2 + read-write + + + TZ_FORCE_CBC + Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action. + 3 + 1 + read-write + + + TZ_FORCE_OST + Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action. + 4 + 1 + read-write + + + + + 3 + 0x38 + FH%s_STATUS + Fault events status register + 0x70 + 0x20 + + + TZ_CBC_ON + Represents whether or not an cycle-by-cycle mode action is on going.\\0:No action\\1: On going + 0 + 1 + read-only + + + TZ_OST_ON + Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status register + 0xE4 + 0x20 + + + F0_EN + Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + F1_EN + Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + F2_EN + Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + F0_POLE + Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level low\\1: Level high + 3 + 1 + read-write + + + F1_POLE + Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level low\\1: Level high + 4 + 1 + read-write + + + F2_POLE + Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level low\\1: Level high + 5 + 1 + read-write + + + EVENT_F0 + Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + 6 + 1 + read-only + + + EVENT_F1 + Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + 7 + 1 + read-only + + + EVENT_F2 + Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Capture timer configuration register + 0xE8 + 0x20 + + + CAP_TIMER_EN + Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_SYNCI_EN + Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CAP_SYNCI_SEL + Configures the selection of capture module sync input.\\0: None\\1: Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + 2 + 3 + read-write + + + CAP_SYNC_SW + Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Capture timer sync phase register + 0xEC + 0x20 + + + CAP_PHASE + Configures phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + 3 + 0x4 + CAP_CH%s_CFG + Capture channel %s configuration register + 0xF0 + 0x20 + + + CAP_EN + Configures whether or not to enable capture on channel %s.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_MODE + Configures which edge of capture on channel %s after prescaling is used.\\0: None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: Enable capture on the positive edge + 1 + 2 + read-write + + + CAP_PRESCALE + Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1 + 3 + 8 + read-write + + + CAP_IN_INVERT + Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\0: Normal\\1: Invert + 11 + 1 + read-write + + + CAP_SW + Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a software forced capture on channel %s + 12 + 1 + write-only + + + + + 3 + 0x4 + CAP_CH%s + CAP%s capture value register + 0xFC + 0x20 + + + CAP_VALUE + Represents value of last capture on CAP%s + 0 + 32 + read-only + + + + + CAP_STATUS + Last capture trigger edge information register + 0x108 + 0x20 + + + CAP0_EDGE + Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + 0 + 1 + read-only + + + CAP1_EDGE + Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + 1 + 1 + read-only + + + CAP2_EDGE + Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Generator Update configuration register + 0x10C + 0x20 + 0x00000005 + + + GLOBAL_UP_EN + Configures whether or not to enable global update for all active registers in MCPWM module.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + 1 + 1 + read-write + + + OP0_UP_EN + Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + OP0_FORCE_UP + Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + 3 + 1 + read-write + + + OP1_UP_EN + Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + OP1_FORCE_UP + Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + 5 + 1 + read-write + + + OP2_UP_EN + Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + OP2_FORCE_UP + Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable register + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_RAW + Interrupt raw status register + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-only + + + CAP1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-only + + + CAP2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear register + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + 29 + 1 + write-only + + + + + EVT_EN + Event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + Configures whether or not to enable timer0 equal zero event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + Configures whether or not to enable timer1 equal zero event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + Configures whether or not to enable timer2 equal zero event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + Configures whether or not to enable timer0 equal period event generate.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + Configures whether or not to enable timer1 equal period event generate.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + Configures whether or not to enable timer2 equal period event generate.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + Configures whether or not to enable PWM generator0 timer equal a event generate.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + Configures whether or not to enable PWM generator1 timer equal a event generate.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + Configures whether or not to enable PWM generator2 timer equal a event generate.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + Configures whether or not to enable PWM generator0 timer equal b event generate.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + Configures whether or not to enable PWM generator1 timer equal b event generate.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + Configures whether or not to enable PWM generator2 timer equal b event generate.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_F0_EN + Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_F1_EN + Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_F2_EN + Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_F0_CLR_EN + Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_F1_CLR_EN + Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_F2_CLR_EN + Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + EVT_CAP0_EN + Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + EVT_CAP1_EN + Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + EVT_CAP2_EN + Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + + + TASK_EN + Task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + Configures whether or not to enable all PWM generate stop task receive.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + Configures whether or not to enable timer0 period update task receive.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + Configures whether or not to enable timer1 period update task receive.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + Configures whether or not to enable timer2 period update task receive.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + Configures whether or not to enable one shot trip0 clear task receive.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + Configures whether or not to enable one shot trip1 clear task receive.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + Configures whether or not to enable one shot trip2 clear task receive.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_CAP0_EN + Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_CAP1_EN + Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_CAP2_EN + Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + + + EVT_EN2 + Event enable register2 + 0x128 + 0x20 + + + EVT_OP0_TEE1_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_OP1_TEE1_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_OP2_TEE1_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_OP0_TEE2_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_OP1_TEE2_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_OP2_TEE2_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E1 + Generator%s timer stamp E1 value register + 0x12C + 0x20 + + + OP_TSTMP_E1 + Configures generator%s timer stamp E1 value register + 0 + 16 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E2 + Generator%s timer stamp E2 value register + 0x130 + 0x20 + + + OP_TSTMP_E2 + Configures generator%s timer stamp E2 value register + 0 + 16 + read-write + + + + + CLK + Global configuration register + 0x144 + 0x20 + + + EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x148 + 0x20 + 0x02212290 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + MCPWM1 + Motor Control Pulse-Width Modulation 1 + 0x500C1000 + + PWM1 + 39 + + + + PARL_IO + Parallel IO Controller + PARL_IO + 0x500CF000 + + 0x0 + 0x54 + registers + + + PARLIO_RX + 113 + + + PARLIO_TX + 114 + + + + RX_MODE_CFG + Parallel RX Sampling mode configuration register. + 0x0 + 0x20 + 0x00E00000 + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from IO PAD. + 21 + 4 + read-write + + + RX_SW_EN + Set this bit to enable data sampling by software. + 25 + 1 + read-write + + + RX_EXT_EN_INV + Set this bit to invert the external enable signal. + 26 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Configures the rxd pulse sampling submode. +4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) +4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) +4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) +4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +4'd4: positive pulse start(data bit included) && length end +4'd5: positive pulse start(data bit excluded) && length end + 27 + 3 + read-write + + + RX_SMP_MODE_SEL + Configures the rxd sampling mode. +2'b00: external level enable mode +2'b01: external pulse enable mode +2'b10: internal software enable mode + 30 + 2 + read-write + + + + + RX_DATA_CFG + Parallel RX data configuration register. + 0x4 + 0x20 + 0x60000000 + + + RX_BITLEN + Configures expected byte number of received data. + 9 + 19 + read-write + + + RX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + 28 + 1 + read-write + + + RX_BUS_WID_SEL + Configures the rxd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + RX_GENRL_CFG + Parallel RX general configuration register. + 0x8 + 0x20 + 0x21FFE000 + + + RX_GATING_EN + Set this bit to enable the clock gating of output rx clock. + 12 + 1 + read-write + + + RX_TIMEOUT_THRES + Configures threshold of timeout counter. + 13 + 16 + read-write + + + RX_TIMEOUT_EN + Set this bit to enable timeout function to generate error eof. + 29 + 1 + read-write + + + RX_EOF_GEN_SEL + Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal. + 30 + 1 + read-write + + + + + RX_START_CFG + Parallel RX Start configuration register. + 0xC + 0x20 + + + RX_START + Set this bit to start rx data sampling. + 31 + 1 + read-write + + + + + TX_DATA_CFG + Parallel TX data configuration register. + 0x10 + 0x20 + 0x60000000 + + + TX_BITLEN + Configures expected byte number of sent data. + 9 + 19 + read-write + + + TX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + 28 + 1 + read-write + + + TX_BUS_WID_SEL + Configures the txd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + TX_START_CFG + Parallel TX Start configuration register. + 0x14 + 0x20 + + + TX_START + Set this bit to start tx data transmit. + 31 + 1 + read-write + + + + + TX_GENRL_CFG + Parallel TX general configuration register. + 0x18 + 0x20 + + + TX_EOF_GEN_SEL + Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof. + 13 + 1 + read-write + + + TX_IDLE_VALUE + Configures bus value of transmitter in IDLE state. + 14 + 16 + read-write + + + TX_GATING_EN + Set this bit to enable the clock gating of output tx clock. + 30 + 1 + read-write + + + TX_VALID_OUTPUT_EN + Set this bit to enable the output of tx data valid signal. + 31 + 1 + read-write + + + + + FIFO_CFG + Parallel IO FIFO configuration register. + 0x1C + 0x20 + + + TX_FIFO_SRST + Set this bit to reset async fifo in tx module. + 30 + 1 + read-write + + + RX_FIFO_SRST + Set this bit to reset async fifo in rx module. + 31 + 1 + read-write + + + + + REG_UPDATE + Parallel IO FIFO configuration register. + 0x20 + 0x20 + + + RX_REG_UPDATE + Set this bit to update rx register configuration. + 31 + 1 + write-only + + + + + ST + Parallel IO module status register0. + 0x24 + 0x20 + + + TX_READY + Represents the status that tx is ready to transmit. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x28 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Set this bit to enable TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_ENA + Set this bit to enable RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Set this bit to enable TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x2C + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_RAW + The raw interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x30 + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-only + + + RX_FIFO_WOVF_INT_ST + The masked interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INT. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x34 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Set this bit to clear TX_FIFO_REMPTY_INT. + 0 + 1 + write-only + + + RX_FIFO_WOVF_INT_CLR + Set this bit to clear RX_FIFO_WOVF_INT. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Set this bit to clear TX_EOF_INT. + 2 + 1 + write-only + + + + + RX_ST0 + Parallel IO RX status register0 + 0x38 + 0x20 + + + RX_CNT + Indicates the cycle number of reading Rx FIFO. + 8 + 5 + read-only + + + RX_FIFO_WR_BIT_CNT + Indicates the current written bit number into Rx FIFO. + 13 + 19 + read-only + + + + + RX_ST1 + Parallel IO RX status register1 + 0x3C + 0x20 + + + RX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Rx FIFO. + 13 + 19 + read-only + + + + + TX_ST0 + Parallel IO TX status register0 + 0x40 + 0x20 + + + TX_CNT + Indicates the cycle number of reading Tx FIFO. + 6 + 7 + read-only + + + TX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Tx FIFO. + 13 + 19 + read-only + + + + + RX_CLK_CFG + Parallel IO RX clk configuration register + 0x44 + 0x20 + + + RX_CLK_I_INV + Set this bit to invert the input Rx core clock. + 30 + 1 + read-write + + + RX_CLK_O_INV + Set this bit to invert the output Rx core clock. + 31 + 1 + read-write + + + + + TX_CLK_CFG + Parallel IO TX clk configuration register + 0x48 + 0x20 + + + TX_CLK_I_INV + Set this bit to invert the input Tx core clock. + 30 + 1 + read-write + + + TX_CLK_O_INV + Set this bit to invert the output Tx core clock. + 31 + 1 + read-write + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 31 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02212260 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + PAU Peripheral + PAU + 0x60093000 + + 0x0 + 0x44 + registers + + + PAU + 112 + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + INT_ENA + Read only register for error and done + 0x30 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x34 + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-write + + + ERROR_INT_RAW + error flag + 1 + 1 + read-write + + + + + INT_CLR + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x500C9000 + + 0x0 + 0x78 + registers + + + PCNT + 111 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + DALTA_CHANGE_EN_U0 + Configures this bit to enable unit 0's step comparator. + 8 + 1 + read-write + + + DALTA_CHANGE_EN_U1 + Configures this bit to enable unit 1's step comparator. + 9 + 1 + read-write + + + DALTA_CHANGE_EN_U2 + Configures this bit to enable unit 2's step comparator. + 10 + 1 + read-write + + + DALTA_CHANGE_EN_U3 + Configures this bit to enable unit 3's step comparator. + 11 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + U3_CHANGE_CONF + Configuration register for unit $n's step value. + 0x64 + 0x20 + + + CNT_STEP_U3 + Configures the step value for unit 3. + 0 + 16 + read-write + + + CNT_STEP_LIM_U3 + Configures the step limit value for unit 3. + 16 + 16 + read-write + + + + + U2_CHANGE_CONF + Configuration register for unit $n's step value. + 0x68 + 0x20 + + + CNT_STEP_U2 + Configures the step value for unit 2. + 0 + 16 + read-write + + + CNT_STEP_LIM_U2 + Configures the step limit value for unit 2. + 16 + 16 + read-write + + + + + U1_CHANGE_CONF + Configuration register for unit $n's step value. + 0x6C + 0x20 + + + CNT_STEP_U1 + Configures the step value for unit 1. + 0 + 16 + read-write + + + CNT_STEP_LIM_U1 + Configures the step limit value for unit 1. + 16 + 16 + read-write + + + + + U0_CHANGE_CONF + Configuration register for unit $n's step value. + 0x70 + 0x20 + + + CNT_STEP_U0 + Configures the step value for unit 0. + 0 + 16 + read-write + + + CNT_STEP_LIM_U0 + Configures the step limit value for unit 0. + 16 + 16 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x22091900 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PMU + PMU Peripheral + PMU + 0x50115000 + + 0x0 + 0x21C + registers + + + PMU0 + 6 + + + PMU1 + 7 + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_ACTIVE_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_ACTIVE_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_ACTIVE_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + 0x00500000 + + + HP_ACTIVE_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_ACTIVE_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_EN + need_des + 29 + 1 + read-write + + + HP_MODEM2ACTIVE_BACKUP_EN + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BACKUP_CLK + need_des + 0x20 + 0x20 + + + HP_ACTIVE_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_SYSCLK + need_des + 0x24 + 0x20 + + + HP_ACTIVE_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_ACTIVE_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_ACTIVE_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_ACTIVE_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_REGULATOR0 + need_des + 0x28 + 0x20 + 0xC6677180 + + + LP_DBIAS_VOL + need_des + 4 + 5 + read-only + + + HP_DBIAS_VOL + need_des + 9 + 5 + read-only + + + DIG_REGULATOR0_DBIAS_SEL + need_des + 14 + 1 + read-write + + + DIG_DBIAS_INIT + need_des + 15 + 1 + write-only + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_ACTIVE_HP_REGULATOR1 + need_des + 0x2C + 0x20 + + + HP_ACTIVE_HP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_ACTIVE_XTAL + need_des + 0x30 + 0x20 + 0x80000000 + + + HP_ACTIVE_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_MODEM_DIG_POWER + need_des + 0x34 + 0x20 + + + HP_MODEM_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_MODEM_HP_MEM_DSLP + need_des + 22 + 1 + write-only + + + HP_MODEM_PD_HP_MEM_PD_EN + need_des + 23 + 4 + write-only + + + HP_MODEM_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_PD_HP_CPU_PD_EN + need_des + 29 + 1 + write-only + + + HP_MODEM_PD_CNNT_PD_EN + need_des + 30 + 1 + write-only + + + HP_MODEM_PD_TOP_PD_EN + need_des + 31 + 1 + write-only + + + + + HP_MODEM_ICG_HP_FUNC + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_HP_APB + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_APB_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_MODEM + need_des + 0x40 + 0x20 + + + HP_MODEM_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_SYS_CNTL + need_des + 0x44 + 0x20 + + + HP_MODEM_HP_POWER_DET_BYPASS + need_des + 23 + 1 + write-only + + + HP_MODEM_UART_WAKEUP_EN + need_des + 24 + 1 + write-only + + + HP_MODEM_LP_PAD_HOLD_ALL + need_des + 25 + 1 + write-only + + + HP_MODEM_HP_PAD_HOLD_ALL + need_des + 26 + 1 + write-only + + + HP_MODEM_DIG_PAD_SLP_SEL + need_des + 27 + 1 + write-only + + + HP_MODEM_DIG_PAUSE_WDT + need_des + 28 + 1 + write-only + + + HP_MODEM_DIG_CPU_STALL + need_des + 29 + 1 + write-only + + + + + HP_MODEM_HP_CK_POWER + need_des + 0x48 + 0x20 + + + HP_MODEM_I2C_ISO_EN + need_des + 21 + 1 + write-only + + + HP_MODEM_I2C_RETENTION + need_des + 22 + 1 + write-only + + + HP_MODEM_XPD_PLL_I2C + need_des + 23 + 4 + write-only + + + HP_MODEM_XPD_PLL + need_des + 27 + 4 + write-only + + + + + HP_MODEM_BIAS + need_des + 0x4C + 0x20 + 0x00500000 + + + HP_MODEM_DCM_VSET + need_des + 18 + 5 + write-only + + + HP_MODEM_DCM_MODE + need_des + 23 + 2 + write-only + + + HP_MODEM_XPD_BIAS + need_des + 25 + 1 + write-only + + + HP_MODEM_DBG_ATTEN + need_des + 26 + 4 + write-only + + + HP_MODEM_PD_CUR + need_des + 30 + 1 + write-only + + + SLEEP + need_des + 31 + 1 + write-only + + + + + HP_MODEM_BACKUP + need_des + 0x50 + 0x20 + + + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + write-only + + + HP_MODEM_RETENTION_MODE + need_des + 10 + 1 + write-only + + + HP_SLEEP2MODEM_RETENTION_EN + need_des + 11 + 1 + write-only + + + HP_SLEEP2MODEM_BACKUP_CLK_SEL + need_des + 14 + 2 + write-only + + + HP_SLEEP2MODEM_BACKUP_MODE + need_des + 20 + 3 + write-only + + + HP_SLEEP2MODEM_BACKUP_EN + need_des + 29 + 1 + write-only + + + + + HP_MODEM_BACKUP_CLK + need_des + 0x54 + 0x20 + + + HP_MODEM_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_SYSCLK + need_des + 0x58 + 0x20 + + + HP_MODEM_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + write-only + + + HP_MODEM_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_SYS_CLK_SLP_SEL + need_des + 28 + 1 + write-only + + + HP_MODEM_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + HP_MODEM_DIG_SYS_CLK_SEL + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_REGULATOR0 + need_des + 0x5C + 0x20 + 0xC6670000 + + + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_XPD + need_des + 18 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_DBIAS + need_des + 27 + 5 + write-only + + + + + HP_MODEM_HP_REGULATOR1 + need_des + 0x60 + 0x20 + + + HP_MODEM_HP_REGULATOR_DRV_B + need_des + 8 + 24 + write-only + + + + + HP_MODEM_XTAL + need_des + 0x64 + 0x20 + 0x80000000 + + + HP_MODEM_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + HP_SLEEP_DIG_POWER + need_des + 0x68 + 0x20 + + + HP_SLEEP_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_SLEEP_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_SLEEP_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_ICG_HP_FUNC + need_des + 0x6C + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_HP_APB + need_des + 0x70 + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_MODEM + need_des + 0x74 + 0x20 + + + HP_SLEEP_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_SYS_CNTL + need_des + 0x78 + 0x20 + + + HP_SLEEP_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_SLEEP_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_SLEEP_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_SLEEP_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_SLEEP_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_SLEEP_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_SLEEP_HP_CK_POWER + need_des + 0x7C + 0x20 + + + HP_SLEEP_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_SLEEP_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_SLEEP_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_SLEEP_BIAS + need_des + 0x80 + 0x20 + 0x00500000 + + + HP_SLEEP_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_SLEEP_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP + need_des + 0x84 + 0x20 + + + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 8 + 2 + read-write + + + HP_SLEEP_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_MODEM2SLEEP_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_ACTIVE2SLEEP_RETENTION_EN + need_des + 13 + 1 + read-write + + + HP_MODEM2SLEEP_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + need_des + 18 + 2 + read-write + + + HP_MODEM2SLEEP_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODE + need_des + 26 + 3 + read-write + + + HP_MODEM2SLEEP_BACKUP_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP_CLK + need_des + 0x88 + 0x20 + + + HP_SLEEP_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_SYSCLK + need_des + 0x8C + 0x20 + + + HP_SLEEP_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_SLEEP_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_SLEEP_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_SLEEP_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_REGULATOR0 + need_des + 0x90 + 0x20 + 0xC6670000 + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_HP_REGULATOR1 + need_des + 0x94 + 0x20 + + + HP_SLEEP_HP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_SLEEP_XTAL + need_des + 0x98 + 0x20 + 0x80000000 + + + HP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_REGULATOR0 + need_des + 0x9C + 0x20 + 0xC6600000 + + + HP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_LP_REGULATOR1 + need_des + 0xA0 + 0x20 + + + HP_SLEEP_LP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0xA4 + 0x20 + + + PMU_HP_SLEEP_LP_DCDC_RESERVE + need_des + 0 + 32 + write-only + + + + + HP_SLEEP_LP_DIG_POWER + need_des + 0xA8 + 0x20 + + + HP_SLEEP_LP_PAD_SLP_SEL + need_des + 26 + 1 + read-write + + + HP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + HP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_CK_POWER + need_des + 0xAC + 0x20 + 0x40000000 + + + HP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + HP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0xB0 + 0x20 + + + PMU_LP_SLEEP_LP_BIAS_RESERVE + need_des + 0 + 32 + write-only + + + + + LP_SLEEP_LP_REGULATOR0 + need_des + 0xB4 + 0x20 + 0xC6600000 + + + LP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + LP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + LP_SLEEP_LP_REGULATOR1 + need_des + 0xB8 + 0x20 + + + LP_SLEEP_LP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + LP_SLEEP_XTAL + need_des + 0xBC + 0x20 + 0x80000000 + + + LP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_DIG_POWER + need_des + 0xC0 + 0x20 + + + LP_SLEEP_LP_PAD_SLP_SEL + need_des + 26 + 1 + read-write + + + LP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + LP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + LP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_CK_POWER + need_des + 0xC4 + 0x20 + 0x40000000 + + + LP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + LP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + LP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + LP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_BIAS + need_des + 0xC8 + 0x20 + + + LP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + LP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + LP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + IMM_HP_CK_POWER + need_des + 0xCC + 0x20 + + + TIE_LOW_CALI_XTAL_ICG + need_des + 0 + 1 + read-write + + + TIE_LOW_GLOBAL_PLL_ICG + need_des + 1 + 4 + write-only + + + TIE_LOW_GLOBAL_XTAL_ICG + need_des + 5 + 1 + write-only + + + TIE_LOW_I2C_RETENTION + need_des + 6 + 1 + write-only + + + TIE_LOW_XPD_PLL_I2C + need_des + 7 + 4 + write-only + + + TIE_LOW_XPD_PLL + need_des + 11 + 4 + write-only + + + TIE_LOW_XPD_XTAL + need_des + 15 + 1 + write-only + + + TIE_HIGH_CALI_XTAL_ICG + need_des + 16 + 1 + read-write + + + TIE_HIGH_GLOBAL_PLL_ICG + need_des + 17 + 4 + write-only + + + TIE_HIGH_GLOBAL_XTAL_ICG + need_des + 21 + 1 + write-only + + + TIE_HIGH_I2C_RETENTION + need_des + 22 + 1 + write-only + + + TIE_HIGH_XPD_PLL_I2C + need_des + 23 + 4 + write-only + + + TIE_HIGH_XPD_PLL + need_des + 27 + 4 + write-only + + + TIE_HIGH_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + IMM_SLEEP_SYSCLK + need_des + 0xD0 + 0x20 + + + UPDATE_DIG_ICG_SWITCH + need_des + 28 + 1 + write-only + + + TIE_LOW_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + TIE_HIGH_ICG_SLP_SEL + need_des + 30 + 1 + write-only + + + UPDATE_DIG_SYS_CLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_HP_FUNC_ICG + need_des + 0xD4 + 0x20 + + + UPDATE_DIG_ICG_FUNC_EN + need_des + 31 + 1 + write-only + + + + + IMM_HP_APB_ICG + need_des + 0xD8 + 0x20 + + + UPDATE_DIG_ICG_APB_EN + need_des + 31 + 1 + write-only + + + + + IMM_MODEM_ICG + need_des + 0xDC + 0x20 + + + UPDATE_DIG_ICG_MODEM_EN + need_des + 31 + 1 + write-only + + + + + IMM_LP_ICG + need_des + 0xE0 + 0x20 + + + TIE_LOW_LP_ROOTCLK_SEL + need_des + 30 + 1 + write-only + + + TIE_HIGH_LP_ROOTCLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_PAD_HOLD_ALL + need_des + 0xE4 + 0x20 + + + PAD_SLP_SEL + need_des + 0 + 1 + read-only + + + LP_PAD_HOLD_ALL + need_des + 1 + 1 + read-only + + + HP_PAD_HOLD_ALL + need_des + 2 + 1 + read-only + + + TIE_HIGH_PAD_SLP_SEL + need_des + 26 + 1 + write-only + + + TIE_LOW_PAD_SLP_SEL + need_des + 27 + 1 + write-only + + + TIE_HIGH_LP_PAD_HOLD_ALL + need_des + 28 + 1 + write-only + + + TIE_LOW_LP_PAD_HOLD_ALL + need_des + 29 + 1 + write-only + + + TIE_HIGH_HP_PAD_HOLD_ALL + need_des + 30 + 1 + write-only + + + TIE_LOW_HP_PAD_HOLD_ALL + need_des + 31 + 1 + write-only + + + + + IMM_I2C_ISO + need_des + 0xE8 + 0x20 + + + TIE_HIGH_I2C_ISO_EN + need_des + 30 + 1 + write-only + + + TIE_LOW_I2C_ISO_EN + need_des + 31 + 1 + write-only + + + + + POWER_WAIT_TIMER0 + need_des + 0xEC + 0x20 + 0x7FBFDFE0 + + + DG_HP_POWERDOWN_TIMER + need_des + 5 + 9 + read-write + + + DG_HP_POWERUP_TIMER + need_des + 14 + 9 + read-write + + + DG_HP_WAIT_TIMER + need_des + 23 + 9 + read-write + + + + + POWER_WAIT_TIMER1 + need_des + 0xF0 + 0x20 + 0x7FBFDFE0 + + + DG_LP_POWERDOWN_TIMER + need_des + 5 + 9 + read-write + + + DG_LP_POWERUP_TIMER + need_des + 14 + 9 + read-write + + + DG_LP_WAIT_TIMER + need_des + 23 + 9 + read-write + + + + + POWER_PD_TOP_CNTL + need_des + 0xF4 + 0x20 + 0x0000001C + + + FORCE_TOP_RESET + need_des + 0 + 1 + read-write + + + FORCE_TOP_ISO + need_des + 1 + 1 + read-write + + + FORCE_TOP_PU + need_des + 2 + 1 + read-write + + + FORCE_TOP_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_TOP_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_TOP_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_CNNT_CNTL + need_des + 0xF8 + 0x20 + 0x0000001C + + + FORCE_CNNT_RESET + need_des + 0 + 1 + read-write + + + FORCE_CNNT_ISO + need_des + 1 + 1 + read-write + + + FORCE_CNNT_PU + need_des + 2 + 1 + read-write + + + FORCE_CNNT_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_CNNT_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_CNNT_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_HPMEM_CNTL + need_des + 0xFC + 0x20 + 0x0000001C + + + FORCE_HP_MEM_RESET + need_des + 0 + 1 + read-write + + + FORCE_HP_MEM_ISO + need_des + 1 + 1 + read-write + + + FORCE_HP_MEM_PU + need_des + 2 + 1 + read-write + + + FORCE_HP_MEM_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_HP_MEM_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_HP_MEM_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_TOP_MASK + need_des + 0x100 + 0x20 + + + XPD_TOP_MASK + need_des + 0 + 5 + read-write + + + PD_TOP_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_CNNT_MASK + need_des + 0x104 + 0x20 + + + XPD_CNNT_MASK + need_des + 0 + 5 + read-write + + + PD_CNNT_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_HPMEM_MASK + need_des + 0x108 + 0x20 + + + XPD_HP_MEM_MASK + need_des + 0 + 6 + read-write + + + PD_HP_MEM_MASK + need_des + 26 + 6 + read-write + + + + + POWER_DCDC_SWITCH + need_des + 0x10C + 0x20 + 0x00000001 + + + FORCE_DCDC_SWITCH_PU + need_des + 0 + 1 + read-write + + + FORCE_DCDC_SWITCH_PD + need_des + 1 + 1 + read-write + + + + + POWER_PD_LPPERI_CNTL + need_des + 0x110 + 0x20 + 0x0000001C + + + FORCE_LP_PERI_RESET + need_des + 0 + 1 + read-write + + + FORCE_LP_PERI_ISO + need_des + 1 + 1 + read-write + + + FORCE_LP_PERI_PU + need_des + 2 + 1 + read-write + + + FORCE_LP_PERI_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_LP_PERI_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_LP_PERI_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_LPPERI_MASK + need_des + 0x114 + 0x20 + + + XPD_LP_PERI_MASK + need_des + 0 + 5 + read-write + + + PD_LP_PERI_MASK + need_des + 27 + 5 + read-write + + + + + POWER_HP_PAD + need_des + 0x118 + 0x20 + + + FORCE_HP_PAD_NO_ISO_ALL + need_des + 0 + 1 + read-write + + + FORCE_HP_PAD_ISO_ALL + need_des + 1 + 1 + read-write + + + + + POWER_CK_WAIT_CNTL + need_des + 0x11C + 0x20 + 0x01000100 + + + PMU_WAIT_XTL_STABLE + need_des + 0 + 16 + read-write + + + PMU_WAIT_PLL_STABLE + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_CNTL0 + need_des + 0x120 + 0x20 + + + SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL1 + need_des + 0x124 + 0x20 + + + SLEEP_REJECT_ENA + need_des + 0 + 31 + read-write + + + SLP_REJECT_EN + need_des + 31 + 1 + read-write + + + + + SLP_WAKEUP_CNTL2 + need_des + 0x128 + 0x20 + + + WAKEUP_ENA + need_des + 0 + 31 + read-write + + + + + SLP_WAKEUP_CNTL3 + need_des + 0x12C + 0x20 + + + LP_MIN_SLP_VAL + need_des + 0 + 8 + read-write + + + HP_MIN_SLP_VAL + need_des + 8 + 8 + read-write + + + SLEEP_PRT_SEL + need_des + 16 + 2 + read-write + + + + + SLP_WAKEUP_CNTL4 + need_des + 0x130 + 0x20 + + + SLP_REJECT_CAUSE_CLR + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL5 + need_des + 0x134 + 0x20 + 0x01000080 + + + MODEM_WAIT_TARGET + need_des + 0 + 20 + read-write + + + LP_ANA_WAIT_TARGET + need_des + 24 + 8 + read-write + + + + + SLP_WAKEUP_CNTL6 + need_des + 0x138 + 0x20 + 0x00000080 + + + SOC_WAKEUP_WAIT + need_des + 0 + 20 + read-write + + + SOC_WAKEUP_WAIT_CFG + need_des + 30 + 2 + read-write + + + + + SLP_WAKEUP_CNTL7 + need_des + 0x13C + 0x20 + 0x00010000 + + + ANA_WAIT_TARGET + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_CNTL8 + need_des + 0x140 + 0x20 + + + LP_LITE_WAKEUP_ENA + need_des + 31 + 1 + read-write + + + + + SLP_WAKEUP_STATUS0 + need_des + 0x144 + 0x20 + + + WAKEUP_CAUSE + need_des + 0 + 31 + read-only + + + + + SLP_WAKEUP_STATUS1 + need_des + 0x148 + 0x20 + + + REJECT_CAUSE + need_des + 0 + 31 + read-only + + + + + SLP_WAKEUP_STATUS2 + need_des + 0x14C + 0x20 + + + LP_LITE_WAKEUP_CAUSE + need_des + 31 + 1 + read-only + + + + + HP_CK_POWERON + need_des + 0x150 + 0x20 + 0x00000032 + + + I2C_POR_WAIT_TARGET + need_des + 0 + 8 + read-write + + + + + HP_CK_CNTL + need_des + 0x154 + 0x20 + 0x00000A0A + + + MODIFY_ICG_CNTL_WAIT + need_des + 0 + 8 + read-write + + + SWITCH_ICG_CNTL_WAIT + need_des + 8 + 8 + read-write + + + + + POR_STATUS + need_des + 0x158 + 0x20 + 0x80000000 + + + POR_DONE + need_des + 31 + 1 + read-only + + + + + RF_PWC + need_des + 0x15C + 0x20 + 0x08000000 + + + MSPI_PHY_XPD + need_des + 24 + 1 + read-write + + + SDIO_PLL_XPD + need_des + 25 + 1 + read-write + + + PERIF_I2C_RSTB + need_des + 26 + 1 + read-write + + + XPD_PERIF_I2C + need_des + 27 + 1 + read-write + + + XPD_TXRF_I2C + need_des + 28 + 1 + read-write + + + XPD_RFRX_PBUS + need_des + 29 + 1 + read-write + + + XPD_CKGEN_I2C + need_des + 30 + 1 + read-write + + + + + BACKUP_CFG + need_des + 0x160 + 0x20 + 0x80000000 + + + BACKUP_SYS_CLK_NO_DIV + need_des + 31 + 1 + read-write + + + + + INT_RAW + need_des + 0x164 + 0x20 + + + _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-write + + + LP_CPU_EXC_INT_RAW + need_des + 27 + 1 + read-write + + + SDIO_IDLE_INT_RAW + need_des + 28 + 1 + read-write + + + SW_INT_RAW + need_des + 29 + 1 + read-write + + + SOC_SLEEP_REJECT_INT_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + HP_INT_ST + need_des + 0x168 + 0x20 + + + _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-only + + + _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-only + + + _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-only + + + _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-only + + + _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-only + + + _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-only + + + _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-only + + + _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-only + + + _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-only + + + _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-only + + + _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-only + + + _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-only + + + LP_CPU_EXC_INT_ST + need_des + 27 + 1 + read-only + + + SDIO_IDLE_INT_ST + need_des + 28 + 1 + read-only + + + SW_INT_ST + need_des + 29 + 1 + read-only + + + SOC_SLEEP_REJECT_INT_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + HP_INT_ENA + need_des + 0x16C + 0x20 + + + _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-write + + + LP_CPU_EXC_INT_ENA + need_des + 27 + 1 + read-write + + + SDIO_IDLE_INT_ENA + need_des + 28 + 1 + read-write + + + SW_INT_ENA + need_des + 29 + 1 + read-write + + + SOC_SLEEP_REJECT_INT_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + HP_INT_CLR + need_des + 0x170 + 0x20 + + + _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + write-only + + + _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + write-only + + + _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + write-only + + + _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + write-only + + + _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + write-only + + + _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + write-only + + + _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + write-only + + + _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + write-only + + + _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + write-only + + + _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + write-only + + + _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + write-only + + + _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + write-only + + + LP_CPU_EXC_INT_CLR + need_des + 27 + 1 + write-only + + + SDIO_IDLE_INT_CLR + need_des + 28 + 1 + write-only + + + SW_INT_CLR + need_des + 29 + 1 + write-only + + + SOC_SLEEP_REJECT_INT_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x174 + 0x20 + + + LP_CPU_SLEEP_REJECT_INT_RAW + need_des + 13 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-write + + + LP_CPU_WAKEUP_INT_RAW + need_des + 26 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_END_INT_RAW + need_des + 27 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_END_INT_RAW + need_des + 28 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_START_INT_RAW + need_des + 29 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_START_INT_RAW + need_des + 30 + 1 + read-write + + + HP_SW_TRIGGER_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x178 + 0x20 + + + LP_CPU_SLEEP_REJECT_INT_ST + need_des + 13 + 1 + read-only + + + _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-only + + + _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-only + + + _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-only + + + _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-only + + + _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-only + + + _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-only + + + _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-only + + + _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-only + + + _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-only + + + _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-only + + + _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-only + + + _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-only + + + LP_CPU_WAKEUP_INT_ST + need_des + 26 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_END_INT_ST + need_des + 27 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_END_INT_ST + need_des + 28 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_START_INT_ST + need_des + 29 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_START_INT_ST + need_des + 30 + 1 + read-only + + + HP_SW_TRIGGER_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x17C + 0x20 + + + LP_CPU_SLEEP_REJECT_INT_ENA + need_des + 13 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + read-write + + + _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + read-write + + + _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + read-write + + + _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + read-write + + + _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + read-write + + + _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + read-write + + + _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + read-write + + + LP_CPU_WAKEUP_INT_ENA + need_des + 26 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_END_INT_ENA + need_des + 27 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_END_INT_ENA + need_des + 28 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_START_INT_ENA + need_des + 29 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_START_INT_ENA + need_des + 30 + 1 + read-write + + + HP_SW_TRIGGER_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x180 + 0x20 + + + LP_CPU_SLEEP_REJECT_LP_INT_CLR + need_des + 13 + 1 + write-only + + + _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR + reg_0p1a_0_counter after xpd reach target0 + 14 + 1 + write-only + + + _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR + reg_0p1a_1_counter after xpd reach target1 + 15 + 1 + write-only + + + _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR + reg_0p1a_0 counter after xpd reach target0 + 16 + 1 + write-only + + + _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR + reg_0p1a_1_counter after xpd reach target1 + 17 + 1 + write-only + + + _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR + reg_0p2a_0 counter after xpd reach target0 + 18 + 1 + write-only + + + _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR + reg_0p2a_1_counter after xpd reach target1 + 19 + 1 + write-only + + + _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR + reg_0p2a_0 counter after xpd reach target0 + 20 + 1 + write-only + + + _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR + reg_0p2a_1_counter after xpd reach target1 + 21 + 1 + write-only + + + _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR + reg_0p3a_0 counter after xpd reach target0 + 22 + 1 + write-only + + + _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR + reg_0p3a_1_counter after xpd reach target1 + 23 + 1 + write-only + + + _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR + reg_0p3a_0_counter after xpd reach target0 + 24 + 1 + write-only + + + _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR + reg_0p3a_1_counter after xpd reach target1 + 25 + 1 + write-only + + + LP_CPU_WAKEUP_INT_CLR + need_des + 26 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_END_INT_CLR + need_des + 27 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_END_INT_CLR + need_des + 28 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_START_INT_CLR + need_des + 29 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_START_INT_CLR + need_des + 30 + 1 + write-only + + + HP_SW_TRIGGER_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_CPU_PWR0 + need_des + 0x184 + 0x20 + 0x1FF00000 + + + LP_CPU_WAITI_RDY + need_des + 0 + 1 + read-only + + + LP_CPU_STALL_RDY + need_des + 1 + 1 + read-only + + + LP_CPU_FORCE_STALL + need_des + 18 + 1 + read-write + + + LP_CPU_SLP_WAITI_FLAG_EN + need_des + 19 + 1 + read-write + + + LP_CPU_SLP_STALL_FLAG_EN + need_des + 20 + 1 + read-write + + + LP_CPU_SLP_STALL_WAIT + need_des + 21 + 8 + read-write + + + LP_CPU_SLP_STALL_EN + need_des + 29 + 1 + read-write + + + LP_CPU_SLP_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_SLP_BYPASS_INTR_EN + need_des + 31 + 1 + read-write + + + + + LP_CPU_PWR1 + need_des + 0x188 + 0x20 + + + LP_CPU_SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + LP_CPU_PWR2 + need_des + 0x18C + 0x20 + + + LP_CPU_WAKEUP_EN + need_des + 0 + 31 + read-write + + + + + LP_CPU_PWR3 + need_des + 0x190 + 0x20 + + + LP_CPU_WAKEUP_CAUSE + need_des + 0 + 31 + read-only + + + + + LP_CPU_PWR4 + need_des + 0x194 + 0x20 + + + LP_CPU_REJECT_EN + need_des + 0 + 31 + read-write + + + + + LP_CPU_PWR5 + need_des + 0x198 + 0x20 + + + LP_CPU_REJECT_CAUSE + need_des + 0 + 31 + read-only + + + + + HP_LP_CPU_COMM + need_des + 0x19C + 0x20 + + + LP_TRIGGER_HP + need_des + 30 + 1 + write-only + + + HP_TRIGGER_LP + need_des + 31 + 1 + write-only + + + + + HP_REGULATOR_CFG + need_des + 0x1A0 + 0x20 + + + DIG_REGULATOR_EN_CAL + need_des + 31 + 1 + read-write + + + + + MAIN_STATE + need_des + 0x1A4 + 0x20 + 0x08100801 + + + ENABLE_CALI_PMU_CNTL + need_des + 0 + 1 + read-write + + + PMU_MAIN_LAST_ST_STATE + need_des + 11 + 7 + read-only + + + PMU_MAIN_TAR_ST_STATE + need_des + 18 + 7 + read-only + + + PMU_MAIN_CUR_ST_STATE + need_des + 25 + 7 + read-only + + + + + PWR_STATE + need_des + 0x1A8 + 0x20 + 0x00802000 + + + PMU_BACKUP_ST_STATE + need_des + 13 + 5 + read-only + + + PMU_LP_PWR_ST_STATE + need_des + 18 + 5 + read-only + + + PMU_HP_PWR_ST_STATE + need_des + 23 + 9 + read-only + + + + + CLK_STATE0 + need_des + 0x1AC + 0x20 + 0x0000000F + + + STABLE_XPD_PLL_STATE + need_des + 0 + 3 + read-only + + + STABLE_XPD_XTAL_STATE + need_des + 3 + 1 + read-only + + + PMU_ANA_XPD_PLL_I2C_STATE + need_des + 4 + 3 + read-only + + + PMU_SYS_CLK_SLP_SEL_STATE + need_des + 10 + 1 + read-only + + + PMU_SYS_CLK_SEL_STATE + need_des + 11 + 2 + read-only + + + PMU_SYS_CLK_NO_DIV_STATE + need_des + 13 + 1 + read-only + + + PMU_ICG_SYS_CLK_EN_STATE + need_des + 14 + 1 + read-only + + + PMU_ICG_MODEM_SWITCH_STATE + need_des + 15 + 1 + read-only + + + PMU_ICG_MODEM_CODE_STATE + need_des + 16 + 2 + read-only + + + PMU_ICG_SLP_SEL_STATE + need_des + 18 + 1 + read-only + + + PMU_ICG_GLOBAL_XTAL_STATE + need_des + 19 + 1 + read-only + + + PMU_ICG_GLOBAL_PLL_STATE + need_des + 20 + 4 + read-only + + + PMU_ANA_I2C_ISO_EN_STATE + need_des + 24 + 1 + read-only + + + PMU_ANA_I2C_RETENTION_STATE + need_des + 25 + 1 + read-only + + + PMU_ANA_XPD_PLL_STATE + need_des + 27 + 4 + read-only + + + PMU_ANA_XPD_XTAL_STATE + need_des + 31 + 1 + read-only + + + + + CLK_STATE1 + need_des + 0x1B0 + 0x20 + 0xFFFFFFFF + + + PMU_ICG_FUNC_EN_STATE + need_des + 0 + 32 + read-only + + + + + CLK_STATE2 + need_des + 0x1B4 + 0x20 + 0xFFFFFFFF + + + PMU_ICG_APB_EN_STATE + need_des + 0 + 32 + read-only + + + + + EXT_LDO_P0_0P1A + need_des + 0x1B8 + 0x20 + 0x40200100 + + + _0P1A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P1A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P1A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P1A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P1A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P1A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P1A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P1A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P1A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P1A_ANA + need_des + 0x1BC + 0x20 + 0xB1000000 + + + ANA_0P1A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P1A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P1A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P1A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P0_0P2A + need_des + 0x1C0 + 0x20 + 0x40200000 + + + _0P2A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P2A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P2A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P2A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P2A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P2A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P2A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P2A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P2A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P2A_ANA + need_des + 0x1C4 + 0x20 + 0xA0000000 + + + ANA_0P2A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P2A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P2A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P2A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P0_0P3A + need_des + 0x1C8 + 0x20 + 0x40200000 + + + _0P3A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P3A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P3A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P3A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P3A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P3A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P3A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P3A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P3A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P3A_ANA + need_des + 0x1CC + 0x20 + 0xA0000000 + + + ANA_0P3A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P3A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P3A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P3A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P1A + need_des + 0x1D0 + 0x20 + 0x40200000 + + + _0P1A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P1A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P1A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P1A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P1A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P1A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P1A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P1A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P1A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P1A_ANA + need_des + 0x1D4 + 0x20 + 0xA0000000 + + + ANA_0P1A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P1A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P1A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P1A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P2A + need_des + 0x1D8 + 0x20 + 0x40200000 + + + _0P2A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P2A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P2A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P2A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P2A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P2A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P2A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P2A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P2A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P2A_ANA + need_des + 0x1DC + 0x20 + 0xA0000000 + + + ANA_0P2A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P2A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P2A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P2A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P3A + need_des + 0x1E0 + 0x20 + 0x40200000 + + + _0P3A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P3A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P3A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P3A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P3A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P3A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P3A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P3A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P3A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P3A_ANA + need_des + 0x1E4 + 0x20 + 0xA0000000 + + + ANA_0P3A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P3A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P3A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P3A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_WAKEUP_LV + need_des + 0x1E8 + 0x20 + + + EXT_WAKEUP_LV + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP_SEL + need_des + 0x1EC + 0x20 + + + EXT_WAKEUP_SEL + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP_ST + need_des + 0x1F0 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 32 + read-only + + + + + EXT_WAKEUP_CNTL + need_des + 0x1F4 + 0x20 + + + EXT_WAKEUP_STATUS_CLR + need_des + 30 + 1 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + SDIO_WAKEUP_CNTL + need_des + 0x1F8 + 0x20 + 0x000003FF + + + SDIO_ACT_DNUM + need_des + 0 + 10 + read-write + + + + + XTAL_SLP + need_des + 0x1FC + 0x20 + 0x000F0000 + + + CNT_TARGET + need_des + 16 + 16 + read-write + + + + + CPU_SW_STALL + need_des + 0x200 + 0x20 + + + HPCORE1_SW_STALL_CODE + need_des + 16 + 8 + read-write + + + HPCORE0_SW_STALL_CODE + need_des + 24 + 8 + read-write + + + + + DCM_CTRL + need_des + 0x204 + 0x20 + 0x00010000 + + + DCDC_ON_REQ + SW trigger dcdc on + 0 + 1 + write-only + + + DCDC_OFF_REQ + SW trigger dcdc off + 1 + 1 + write-only + + + DCDC_LIGHTSLP_REQ + SW trigger dcdc enter lightsleep + 2 + 1 + write-only + + + DCDC_DEEPSLP_REQ + SW trigger dcdc enter deepsleep + 3 + 1 + write-only + + + DCDC_DONE_FORCE + need_des + 7 + 1 + read-write + + + DCDC_ON_FORCE_PU + need_des + 8 + 1 + read-write + + + DCDC_ON_FORCE_PD + need_des + 9 + 1 + read-write + + + DCDC_FB_RES_FORCE_PU + need_des + 10 + 1 + read-write + + + DCDC_FB_RES_FORCE_PD + need_des + 11 + 1 + read-write + + + DCDC_LS_FORCE_PU + need_des + 12 + 1 + read-write + + + DCDC_LS_FORCE_PD + need_des + 13 + 1 + read-write + + + DCDC_DS_FORCE_PU + need_des + 14 + 1 + read-write + + + DCDC_DS_FORCE_PD + need_des + 15 + 1 + read-write + + + DCM_CUR_ST + need_des + 16 + 8 + read-only + + + DCDC_EN_AMUX_TEST + Enable analog mux to pull PAD TEST_DCDC voltage signal + 29 + 1 + read-write + + + + + DCM_WAIT_DELAY + need_des + 0x208 + 0x20 + 0x004B0205 + + + DCDC_PRE_DELAY + DCDC pre-on/post off delay + 0 + 8 + read-write + + + DCDC_RES_OFF_DELAY + DCDC fb res off delay + 8 + 8 + read-write + + + DCDC_STABLE_DELAY + DCDC stable delay + 16 + 10 + read-write + + + + + VDDBAT_CFG + need_des + 0x20C + 0x20 + + + ANA_VDDBAT_MODE + need_des + 0 + 2 + read-only + + + VDDBAT_SW_UPDATE + need_des + 31 + 1 + write-only + + + + + TOUCH_PWR_CNTL + need_des + 0x210 + 0x20 + 0x00190140 + + + TOUCH_WAIT_CYCLES + need_des + 5 + 9 + read-write + + + TOUCH_SLEEP_CYCLES + need_des + 14 + 16 + read-write + + + TOUCH_FORCE_DONE + need_des + 30 + 1 + read-write + + + TOUCH_SLEEP_TIMER_EN + need_des + 31 + 1 + read-write + + + + + RDN_ECO + need_des + 0x214 + 0x20 + + + PMU_RDN_ECO_RESULT + need_des + 0 + 1 + read-only + + + PMU_RDN_ECO_EN + need_des + 31 + 1 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02303140 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + PPA + PPA Peripheral + PPA + 0x50087000 + + 0x0 + 0x88 + registers + + + PPA + 96 + + + + BLEND0_CLUT_DATA + CLUT sram data read/write register in background plane of blender + 0x0 + 0x20 + + + RDWR_WORD_BLEND0_CLUT + Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + BLEND1_CLUT_DATA + CLUT sram data read/write register in foreground plane of blender + 0x4 + 0x20 + + + RDWR_WORD_BLEND1_CLUT + Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + CLUT_CONF + CLUT configure register + 0xC + 0x20 + + + APB_FIFO_MASK + 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode. + 0 + 1 + read-write + + + BLEND0_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND0 CLUT. + 1 + 1 + read-write + + + BLEND1_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND1 CLUT. + 2 + 1 + read-write + + + BLEND0_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + 3 + 1 + read-write + + + BLEND1_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + 4 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PD + 1: force power down BLEND CLUT memory. + 5 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PU + 1: force power up BLEND CLUT memory. + 6 + 1 + read-write + + + BLEND0_CLUT_MEM_CLK_ENA + 1: Force clock on for BLEND CLUT memory. + 7 + 1 + read-write + + + + + INT_RAW + Raw status interrupt + 0x10 + 0x20 + + + SR_EOF_INT_RAW + The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image. + 0 + 1 + read-write + + + BLEND_EOF_INT_RAW + The raw interrupt bit turns to high level when blending engine calculate one frame image. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_RAW + The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG. + 2 + 1 + read-write + + + + + INT_ST + Masked interrupt + 0x14 + 0x20 + + + SR_EOF_INT_ST + The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-only + + + BLEND_EOF_INT_ST + The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-only + + + SR_PARAM_CFG_ERR_INT_ST + The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x18 + 0x20 + + + SR_EOF_INT_ENA + The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-write + + + BLEND_EOF_INT_ENA + The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_ENA + The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x1C + 0x20 + + + SR_EOF_INT_CLR + Set this bit to clear the PPA_SR_EOF_INT interrupt. + 0 + 1 + write-only + + + BLEND_EOF_INT_CLR + Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + write-only + + + SR_PARAM_CFG_ERR_INT_CLR + Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + write-only + + + + + SR_COLOR_MODE + Scaling and rotating engine color mode register + 0x20 + 0x20 + + + SR_RX_CM + The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 0 + 4 + read-write + + + SR_TX_CM + The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 4 + 4 + read-write + + + YUV_RX_RANGE + YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + 8 + 1 + read-write + + + YUV_TX_RANGE + YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + 9 + 1 + read-write + + + YUV2RGB_PROTOCAL + YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + 10 + 1 + read-write + + + RGB2YUV_PROTOCAL + RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + 11 + 1 + read-write + + + + + BLEND_COLOR_MODE + blending engine color mode register + 0x24 + 0x20 + + + BLEND0_RX_CM + The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. + 0 + 4 + read-write + + + BLEND1_RX_CM + The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + 4 + 4 + read-write + + + BLEND_TX_CM + The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.. + 8 + 4 + read-write + + + + + SR_BYTE_ORDER + Scaling and rotating engine byte order register + 0x28 + 0x20 + + + SR_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + SR_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 1 + 1 + read-write + + + SR_MACRO_BK_RO_BYPASS + Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory. + 2 + 1 + read-write + + + + + BLEND_BYTE_ORDER + Blending engine byte order register + 0x2C + 0x20 + + + BLEND0_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + BLEND1_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 1 + 1 + read-write + + + BLEND0_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 2 + 1 + read-write + + + BLEND1_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 3 + 1 + read-write + + + + + BLEND_TRANS_MODE + Blending engine mode configure register + 0x34 + 0x20 + + + BLEND_EN + Set this bit to enable alpha blending. + 0 + 1 + read-write + + + BLEND_BYPASS + Set this bit to bypass blender. Then background date would be output. + 1 + 1 + read-write + + + BLEND_FIX_PIXEL_FILL_EN + This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + 2 + 1 + read-write + + + UPDATE + Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid. + 3 + 1 + write-only + + + BLEND_RST + write 1 then write 0 to reset blending engine. + 4 + 1 + read-write + + + + + SR_FIX_ALPHA + Scaling and rotating engine alpha override register + 0x38 + 0x20 + 0x00000080 + + + SR_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + SR_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 8 + 2 + read-write + + + SR_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 10 + 1 + read-write + + + + + BLEND_TX_SIZE + Fix pixel filling mode image size register + 0x3C + 0x20 + + + BLEND_HB + The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel + 0 + 14 + read-write + + + BLEND_VB + The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel + 14 + 14 + read-write + + + + + BLEND_FIX_ALPHA + Blending engine alpha override register + 0x40 + 0x20 + 0x00008080 + + + BLEND0_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + BLEND1_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + 8 + 8 + read-write + + + BLEND0_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 16 + 2 + read-write + + + BLEND1_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 18 + 2 + read-write + + + BLEND0_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 20 + 1 + read-write + + + BLEND1_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 21 + 1 + read-write + + + + + BLEND_RGB + RGB color register + 0x48 + 0x20 + 0x00808080 + + + BLEND1_RX_B + blue color for A4/A8 mode. + 0 + 8 + read-write + + + BLEND1_RX_G + green color for A4/A8 mode. + 8 + 8 + read-write + + + BLEND1_RX_R + red color for A4/A8 mode. + 16 + 8 + read-write + + + + + BLEND_FIX_PIXEL + Blending engine fix pixel register + 0x4C + 0x20 + + + BLEND_TX_FIX_PIXEL + The configure fix pixel in fix pixel filling mode for blender engine. + 0 + 32 + read-write + + + + + CK_FG_LOW + foreground color key lower threshold + 0x50 + 0x20 + 0x00FFFFFF + + + COLORKEY_FG_B_LOW + color key lower threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_LOW + color key lower threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_LOW + color key lower threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_FG_HIGH + foreground color key higher threshold + 0x54 + 0x20 + + + COLORKEY_FG_B_HIGH + color key higher threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_HIGH + color key higher threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_HIGH + color key higher threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_BG_LOW + background color key lower threshold + 0x58 + 0x20 + 0x00FFFFFF + + + COLORKEY_BG_B_LOW + color key lower threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_LOW + color key lower threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_LOW + color key lower threshold of background r channel + 16 + 8 + read-write + + + + + CK_BG_HIGH + background color key higher threshold + 0x5C + 0x20 + + + COLORKEY_BG_B_HIGH + color key higher threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_HIGH + color key higher threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_HIGH + color key higher threshold of background r channel + 16 + 8 + read-write + + + + + CK_DEFAULT + default value when foreground and background both in color key range + 0x60 + 0x20 + + + COLORKEY_DEFAULT_B + default B channle value of color key + 0 + 8 + read-write + + + COLORKEY_DEFAULT_G + default G channle value of color key + 8 + 8 + read-write + + + COLORKEY_DEFAULT_R + default R channle value of color key + 16 + 8 + read-write + + + COLORKEY_FG_BG_REVERSE + when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg + 24 + 1 + read-write + + + + + SR_SCAL_ROTATE + Scaling and rotating coefficient register + 0x64 + 0x20 + 0x00001001 + + + SR_SCAL_X_INT + The integrated part of scaling coefficient in X direction. + 0 + 8 + read-write + + + SR_SCAL_X_FRAG + The fragment part of scaling coefficient in X direction. + 8 + 4 + read-write + + + SR_SCAL_Y_INT + The integrated part of scaling coefficient in Y direction. + 12 + 8 + read-write + + + SR_SCAL_Y_FRAG + The fragment part of scaling coefficient in Y direction. + 20 + 4 + read-write + + + SR_ROTATE_ANGLE + The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + 24 + 2 + read-write + + + SCAL_ROTATE_RST + Write 1 then write 0 to this bit to reset scaling and rotating engine. + 26 + 1 + read-write + + + SCAL_ROTATE_START + Write 1 to enable scaling and rotating engine after parameter is configured. + 27 + 1 + write-only + + + SR_MIRROR_X + Image mirror in X direction. 0: disable, 1: enable + 28 + 1 + read-write + + + SR_MIRROR_Y + Image mirror in Y direction. 0: disable, 1: enable + 29 + 1 + read-write + + + + + SR_MEM_PD + SR memory power done register + 0x68 + 0x20 + + + SR_MEM_CLK_ENA + Set this bit to force clock enable of scaling and rotating engine's data memory. + 0 + 1 + read-write + + + SR_MEM_FORCE_PD + Set this bit to force power down scaling and rotating engine's data memory. + 1 + 1 + read-write + + + SR_MEM_FORCE_PU + Set this bit to force power up scaling and rotating engine's data memory. + 2 + 1 + read-write + + + + + REG_CONF + Register clock enable register + 0x6C + 0x20 + + + CLK_EN + PPA register clock gate enable signal. + 0 + 1 + read-write + + + + + CLUT_CNT + BLEND CLUT write counter register + 0x70 + 0x20 + + + BLEND0_CLUT_CNT + The write data counter of BLEND0 CLUT in fifo mode. + 0 + 9 + read-only + + + BLEND1_CLUT_CNT + The write data counter of BLEND1 CLUT in fifo mode. + 9 + 9 + read-only + + + + + BLEND_ST + Blending engine status register + 0x74 + 0x20 + + + BLEND_SIZE_DIFF_ST + 1: indicate the size of two image is different. + 0 + 1 + read-only + + + + + SR_PARAM_ERR_ST + Scaling and rotating coefficient error register + 0x78 + 0x20 + + + TX_DSCR_VB_ERR_ST + The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor. + 0 + 1 + read-only + + + TX_DSCR_HB_ERR_ST + The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor. + 1 + 1 + read-only + + + Y_RX_SCAL_EQUAL_0_ERR_ST + The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + 2 + 1 + read-only + + + RX_DSCR_VB_ERR_ST + The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + 3 + 1 + read-only + + + YDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored. + 4 + 1 + read-only + + + YDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled width is larger than (2^13 - 1). + 5 + 1 + read-only + + + X_RX_SCAL_EQUAL_0_ERR_ST + The error is that the scaled image height is 0. + 6 + 1 + read-only + + + RX_DSCR_HB_ERR_ST + The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor. + 7 + 1 + read-only + + + XDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored. + 8 + 1 + read-only + + + XDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled image height is larger than (2^13 - 1). + 9 + 1 + read-only + + + X_YUV420_RX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx + 10 + 1 + read-only + + + Y_YUV420_RX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx + 11 + 1 + read-only + + + X_YUV420_TX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx + 12 + 1 + read-only + + + Y_YUV420_TX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx + 13 + 1 + read-only + + + + + SR_STATUS + SR FSM register + 0x7C + 0x20 + + + SR_RX_DSCR_SAMPLE_STATE + Reserved. + 0 + 2 + read-only + + + SR_RX_SCAN_STATE + Reserved. + 2 + 2 + read-only + + + SR_TX_DSCR_SAMPLE_STATE + Reserved. + 4 + 2 + read-only + + + SR_TX_SCAN_STATE + Reserved. + 6 + 3 + read-only + + + + + ECO_LOW + Reserved. + 0x80 + 0x20 + + + RND_ECO_LOW + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH + Reserved. + 0x84 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL + Reserved. + 0x88 + 0x20 + + + RDN_RESULT + Reserved. + 0 + 1 + read-only + + + RDN_ENA + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x8C + 0x20 + 0x00001320 + + + MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + PPA Version register + 0x100 + 0x20 + 0x02304041 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + PVT + PVT Peripheral + PVT + 0x5009E000 + + 0x0 + 0x1F0 + registers + + + + PMUP_BITMAP_HIGH0 + select valid pvt channel + 0x0 + 0x20 + + + PUMP_BITMAP_HIGH0 + select valid high channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH1 + select valid pvt channel + 0x4 + 0x20 + + + PUMP_BITMAP_HIGH1 + select valid high channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH2 + select valid pvt channel + 0x8 + 0x20 + + + PUMP_BITMAP_HIGH2 + select valid high channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH3 + select valid pvt channel + 0xC + 0x20 + + + PUMP_BITMAP_HIGH3 + select valid high channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH4 + select valid pvt channel + 0x10 + 0x20 + + + PUMP_BITMAP_HIGH4 + select valid high channel4 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW0 + select valid pvt channel + 0x14 + 0x20 + + + PUMP_BITMAP_LOW0 + select valid low channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW1 + select valid pvt channel + 0x18 + 0x20 + + + PUMP_BITMAP_LOW1 + select valid low channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW2 + select valid pvt channel + 0x1C + 0x20 + + + PUMP_BITMAP_LOW2 + select valid low channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW3 + select valid pvt channel + 0x20 + 0x20 + + + PUMP_BITMAP_LOW3 + select valid low channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW4 + select valid pvt channel + 0x24 + 0x20 + + + PUMP_BITMAP_LOW4 + select valid low channel4 + 0 + 32 + read-write + + + + + PMUP_DRV_CFG + configure pump drv + 0x28 + 0x20 + + + PUMP_EN + configure pvt charge xpd + 9 + 1 + read-write + + + CLK_EN + force register clken + 10 + 1 + read-write + + + PUMP_DRV4 + configure cmd4 drv + 11 + 4 + read-write + + + PUMP_DRV3 + configure cmd3 drv + 15 + 4 + read-write + + + PUMP_DRV2 + configure cmd2 drv + 19 + 4 + read-write + + + PUMP_DRV1 + configure cmd1 drv + 23 + 4 + read-write + + + PUMP_DRV0 + configure cmd0 drv + 27 + 4 + read-write + + + + + PMUP_CHANNEL_CFG + configure the code of valid pump channel code + 0x2C + 0x20 + + + PUMP_CHANNEL_CODE4 + configure cmd4 code + 7 + 5 + read-write + + + PUMP_CHANNEL_CODE3 + configure cmd3 code + 12 + 5 + read-write + + + PUMP_CHANNEL_CODE2 + configure cmd2 code + 17 + 5 + read-write + + + PUMP_CHANNEL_CODE1 + configure cmd1 code + 22 + 5 + read-write + + + PUMP_CHANNEL_CODE0 + configure cmd0 code + 27 + 5 + read-write + + + + + CLK_CFG + configure pvt clk + 0x30 + 0x20 + + + PUMP_CLK_DIV_NUM + needs field desc + 0 + 8 + read-write + + + MONITOR_CLK_PVT_EN + needs field desc + 8 + 1 + read-write + + + CLK_SEL + select pvt clk + 31 + 1 + read-write + + + + + DBIAS_CHANNEL_SEL0 + needs desc + 0x34 + 0x20 + 0x81020400 + + + DBIAS_CHANNEL3_SEL + needs field desc + 4 + 7 + read-write + + + DBIAS_CHANNEL2_SEL + needs field desc + 11 + 7 + read-write + + + DBIAS_CHANNEL1_SEL + needs field desc + 18 + 7 + read-write + + + DBIAS_CHANNEL0_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL_SEL1 + needs desc + 0x38 + 0x20 + 0x80000000 + + + DBIAS_CHANNEL4_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL0_SEL + needs desc + 0x3C + 0x20 + + + DBIAS_CHANNEL0_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL1_SEL + needs desc + 0x40 + 0x20 + + + DBIAS_CHANNEL1_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL2_SEL + needs desc + 0x44 + 0x20 + + + DBIAS_CHANNEL2_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL3_SEL + needs desc + 0x48 + 0x20 + + + DBIAS_CHANNEL3_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL4_SEL + needs desc + 0x4C + 0x20 + + + DBIAS_CHANNEL4_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD0 + needs desc + 0x50 + 0x20 + + + DBIAS_CMD0 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD1 + needs desc + 0x54 + 0x20 + + + DBIAS_CMD1 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD2 + needs desc + 0x58 + 0x20 + + + DBIAS_CMD2 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD3 + needs desc + 0x5C + 0x20 + + + DBIAS_CMD3 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD4 + needs desc + 0x60 + 0x20 + + + DBIAS_CMD4 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_TIMER + needs desc + 0x64 + 0x20 + 0x7FFF8000 + + + TIMER_TARGET + needs field desc + 15 + 16 + read-write + + + TIMER_EN + needs field desc + 31 + 1 + read-write + + + + + COMB_PD_SITE0_UNIT0_VT0_CONF1 + needs desc + 0x68 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT0_CONF1 + needs desc + 0x6C + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT0_CONF1 + needs desc + 0x70 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT0_CONF1 + needs desc + 0x74 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT1_CONF1 + needs desc + 0x78 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT1_CONF1 + needs desc + 0x7C + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT1_CONF1 + needs desc + 0x80 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT1_CONF1 + needs desc + 0x84 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT2_CONF1 + needs desc + 0x88 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT2_CONF1 + needs desc + 0x8C + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT2_CONF1 + needs desc + 0x90 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT2_CONF1 + needs desc + 0x94 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT0_CONF1 + needs desc + 0x98 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT0_CONF1 + needs desc + 0x9C + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT0_CONF1 + needs desc + 0xA0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT0_CONF1 + needs desc + 0xA4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT1_CONF1 + needs desc + 0xA8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE1_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE1_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE1_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE1_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT1_CONF1 + needs desc + 0xAC + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE1_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE1_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE1_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE1_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT1_CONF1 + needs desc + 0xB0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE1_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE1_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE1_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE1_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT1_CONF1 + needs desc + 0xB4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE1_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE1_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE1_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE1_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT2_CONF1 + needs desc + 0xB8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE1_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE1_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE1_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE1_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT2_CONF1 + needs desc + 0xBC + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE1_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE1_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE1_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE1_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT2_CONF1 + needs desc + 0xC0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE1_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE1_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE1_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE1_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT2_CONF1 + needs desc + 0xC4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE1_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE1_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE1_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE1_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT0_CONF1 + needs desc + 0xC8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE2_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE2_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE2_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE2_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT0_CONF1 + needs desc + 0xCC + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE2_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE2_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE2_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE2_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT0_CONF1 + needs desc + 0xD0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE2_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE2_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE2_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE2_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT0_CONF1 + needs desc + 0xD4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE2_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE2_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE2_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE2_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT1_CONF1 + needs desc + 0xD8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE2_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE2_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE2_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE2_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT1_CONF1 + needs desc + 0xDC + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE2_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE2_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE2_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE2_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT1_CONF1 + needs desc + 0xE0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE2_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE2_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE2_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE2_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT1_CONF1 + needs desc + 0xE4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE2_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE2_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE2_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE2_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT2_CONF1 + needs desc + 0xE8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE2_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE2_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE2_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE2_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT2_CONF1 + needs desc + 0xEC + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE2_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE2_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE2_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE2_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT2_CONF1 + needs desc + 0xF0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE2_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE2_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE2_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE2_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT2_CONF1 + needs desc + 0xF4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE2_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE2_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE2_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE2_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT0_CONF1 + needs desc + 0xF8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE3_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE3_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE3_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE3_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT0_CONF1 + needs desc + 0xFC + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE3_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE3_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE3_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE3_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT0_CONF1 + needs desc + 0x100 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE3_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE3_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE3_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE3_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT0_CONF1 + needs desc + 0x104 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE3_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE3_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE3_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE3_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT1_CONF1 + needs desc + 0x108 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE3_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE3_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE3_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE3_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT1_CONF1 + needs desc + 0x10C + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE3_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE3_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE3_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE3_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT1_CONF1 + needs desc + 0x110 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE3_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE3_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE3_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE3_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT1_CONF1 + needs desc + 0x114 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE3_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE3_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE3_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE3_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT2_CONF1 + needs desc + 0x118 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE3_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE3_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE3_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE3_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT2_CONF1 + needs desc + 0x11C + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE3_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE3_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE3_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE3_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT2_CONF1 + needs desc + 0x120 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE3_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE3_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE3_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE3_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT2_CONF1 + needs desc + 0x124 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE3_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE3_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE3_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE3_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT0_CONF2 + needs desc + 0x128 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE0_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT0_CONF2 + needs desc + 0x12C + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE0_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT0_CONF2 + needs desc + 0x130 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE0_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT0_CONF2 + needs desc + 0x134 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE0_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT1_CONF2 + needs desc + 0x138 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE0_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT1_CONF2 + needs desc + 0x13C + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE0_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT1_CONF2 + needs desc + 0x140 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE0_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT1_CONF2 + needs desc + 0x144 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE0_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT2_CONF2 + needs desc + 0x148 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE0_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT2_CONF2 + needs desc + 0x14C + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE0_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT2_CONF2 + needs desc + 0x150 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE0_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT2_CONF2 + needs desc + 0x154 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE0_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT0_CONF2 + needs desc + 0x158 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE1_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT0_CONF2 + needs desc + 0x15C + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE1_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT0_CONF2 + needs desc + 0x160 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE1_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT0_CONF2 + needs desc + 0x164 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE1_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT1_CONF2 + needs desc + 0x168 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE1_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT1_CONF2 + needs desc + 0x16C + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE1_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT1_CONF2 + needs desc + 0x170 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE1_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT1_CONF2 + needs desc + 0x174 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE1_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT2_CONF2 + needs desc + 0x178 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE1_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT2_CONF2 + needs desc + 0x17C + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE1_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT2_CONF2 + needs desc + 0x180 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE1_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT2_CONF2 + needs desc + 0x184 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE1_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT0_CONF2 + needs desc + 0x188 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE2_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT0_CONF2 + needs desc + 0x18C + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE2_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT0_CONF2 + needs desc + 0x190 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE2_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT0_CONF2 + needs desc + 0x194 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE2_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT1_CONF2 + needs desc + 0x198 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT1_CONF2 + needs desc + 0x19C + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT1_CONF2 + needs desc + 0x1A0 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT1_CONF2 + needs desc + 0x1A4 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT2_CONF2 + needs desc + 0x1A8 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT2_CONF2 + needs desc + 0x1AC + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT2_CONF2 + needs desc + 0x1B0 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT2_CONF2 + needs desc + 0x1B4 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT0_CONF2 + needs desc + 0x1B8 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT0_CONF2 + needs desc + 0x1BC + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT0_CONF2 + needs desc + 0x1C0 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT0_CONF2 + needs desc + 0x1C4 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT1_CONF2 + needs desc + 0x1C8 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT1_CONF2 + needs desc + 0x1CC + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT1_CONF2 + needs desc + 0x1D0 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT1_CONF2 + needs desc + 0x1D4 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT2_CONF2 + needs desc + 0x1D8 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT2_CONF2 + needs desc + 0x1DC + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT2_CONF2 + needs desc + 0x1E0 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT2_CONF2 + needs desc + 0x1E4 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + VALUE_UPDATE + needs field desc + 0x1E8 + 0x20 + + + VALUE_UPDATE + needs field desc + 0 + 1 + write-only + + + BYPASS + needs field desc + 1 + 1 + read-write + + + + + DATE + version register + 0xFFC + 0x20 + 0x02112130 + + + DATE + version register + 0 + 32 + read-write + + + + + + + RMT + Remote Control + RMT + 0x500D4000 + + 0x0 + 0xD0 + registers + + + RMT + 43 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT_CH4 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH4 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH4 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN_CH4 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH4 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN_CH4 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH4 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH4 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH4 + This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH4 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH4 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH4 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH4 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH4 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX_CH4 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR_CH4 + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH4 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH4 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH4 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH4 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-write + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-write + + + CH2_TX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmission done. + 2 + 1 + read-write + + + CH3_TX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmission done. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when error occurs. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when error occurs. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when error occurs. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when error occurs. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value. + 15 + 1 + read-write + + + CH4_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-write + + + CH5_RX_END_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when reception done. + 17 + 1 + read-write + + + CH6_RX_END_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when reception done. + 18 + 1 + read-write + + + CH7_RX_END_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when reception done. + 19 + 1 + read-write + + + RX_CH4_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-write + + + RX_CH5_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 21 + 1 + read-write + + + RX_CH6_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 22 + 1 + read-write + + + RX_CH7_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_TX_END_INT_ST + The masked interrupt status bit for CH2_TX_END_INT. + 2 + 1 + read-only + + + CH3_TX_END_INT_ST + The masked interrupt status bit for CH3_TX_END_INT. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_ST + The masked interrupt status bit for CH0_ERR_INT. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_ST + The masked interrupt status bit for CH1_ERR_INT. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_ST + The masked interrupt status bit for CH2_ERR_INT. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_ST + The masked interrupt status bit for CH3_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + CH2_TX_LOOP_INT_ST + The masked interrupt status bit for CH2_TX_LOOP_INT. + 14 + 1 + read-only + + + CH3_TX_LOOP_INT_ST + The masked interrupt status bit for CH3_TX_LOOP_INT. + 15 + 1 + read-only + + + CH4_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + CH5_RX_END_INT_ST + The masked interrupt status bit for CH5_RX_END_INT. + 17 + 1 + read-only + + + CH6_RX_END_INT_ST + The masked interrupt status bit for CH6_RX_END_INT. + 18 + 1 + read-only + + + CH7_RX_END_INT_ST + The masked interrupt status bit for CH7_RX_END_INT. + 19 + 1 + read-only + + + RX_CH4_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + RX_CH5_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 21 + 1 + read-only + + + RX_CH6_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 22 + 1 + read-only + + + RX_CH7_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 23 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_TX_END_INT_ENA + The interrupt enable bit for CH2_TX_END_INT. + 2 + 1 + read-write + + + CH3_TX_END_INT_ENA + The interrupt enable bit for CH3_TX_END_INT. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_ENA + The interrupt enable bit for CH0_ERR_INT. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_ENA + The interrupt enable bit for CH1_ERR_INT. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_ENA + The interrupt enable bit for CH2_ERR_INT. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_ENA + The interrupt enable bit for CH3_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_ENA + The interrupt enable bit for CH2_TX_LOOP_INT. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_ENA + The interrupt enable bit for CH3_TX_LOOP_INT. + 15 + 1 + read-write + + + CH4_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + CH5_RX_END_INT_ENA + The interrupt enable bit for CH5_RX_END_INT. + 17 + 1 + read-write + + + CH6_RX_END_INT_ENA + The interrupt enable bit for CH6_RX_END_INT. + 18 + 1 + read-write + + + CH7_RX_END_INT_ENA + The interrupt enable bit for CH7_RX_END_INT. + 19 + 1 + read-write + + + CH4_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH5_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 21 + 1 + read-write + + + CH6_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 22 + 1 + read-write + + + CH7_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_TX_END_INT_CLR + Set this bit to clear theCH2_TX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_TX_END_INT_CLR + Set this bit to clear theCH3_TX_END_INT interrupt. + 3 + 1 + write-only + + + TX_CH0_ERR_INT_CLR + Set this bit to clear theCH0_ERR_INT interrupt. + 4 + 1 + write-only + + + TX_CH1_ERR_INT_CLR + Set this bit to clear theCH1_ERR_INT interrupt. + 5 + 1 + write-only + + + TX_CH2_ERR_INT_CLR + Set this bit to clear theCH2_ERR_INT interrupt. + 6 + 1 + write-only + + + TX_CH3_ERR_INT_CLR + Set this bit to clear theCH3_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + CH2_TX_LOOP_INT_CLR + Set this bit to clear theCH2_TX_LOOP_INT interrupt. + 14 + 1 + write-only + + + CH3_TX_LOOP_INT_CLR + Set this bit to clear theCH3_TX_LOOP_INT interrupt. + 15 + 1 + write-only + + + CH4_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + CH5_RX_END_INT_CLR + Set this bit to clear theCH5_RX_END_INT interrupt. + 17 + 1 + write-only + + + CH6_RX_END_INT_CLR + Set this bit to clear theCH6_RX_END_INT interrupt. + 18 + 1 + write-only + + + CH7_RX_END_INT_CLR + Set this bit to clear theCH7_RX_END_INT interrupt. + 19 + 1 + write-only + + + RX_CH4_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + RX_CH5_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 21 + 1 + write-only + + + RX_CH6_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 22 + 1 + write-only + + + RX_CH7_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 23 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES_CH + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM_CH + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM_CH4 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + TX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + TX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + RX_REF_CNT_RST_CH4 + This register is used to reset the clock divider of CHANNEL4. + 4 + 1 + write-only + + + RX_REF_CNT_RST_CH5 + This register is used to reset the clock divider of CHANNEL5. + 5 + 1 + write-only + + + RX_REF_CNT_RST_CH6 + This register is used to reset the clock divider of CHANNEL6. + 6 + 1 + write-only + + + RX_REF_CNT_RST_CH7 + This register is used to reset the clock divider of CHANNEL7. + 7 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02201111 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x50092000 + + 0x0 + 0x74 + registers + + + RSA + 68 + + + + 4 + 0x4 + M_MEM[%s] + Represents M + 0x0 + 0x20 + + + 4 + 0x4 + Z_MEM[%s] + Represents Z + 0x200 + 0x20 + + + 4 + 0x4 + Y_MEM[%s] + Represents Y + 0x400 + 0x20 + + + 4 + 0x4 + X_MEM[%s] + Represents X + 0x600 + 0x20 + + + M_PRIME + Represents M’ + 0x800 + 0x20 + + + M_PRIME + Represents M’ + 0 + 32 + read-write + + + + + MODE + Configures RSA length + 0x804 + 0x20 + + + MODE + Configures the RSA length. + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA clean register + 0x808 + 0x20 + + + QUERY_CLEAN + Represents whether or not the RSA memory completes initialization. + +0: Not complete + +1: Completed + 0 + 1 + read-only + + + + + SET_START_MODEXP + Starts modular exponentiation + 0x80C + 0x20 + + + SET_START_MODEXP + Configure whether or not to start the modular exponentiation. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MODMULT + Starts modular multiplication + 0x810 + 0x20 + + + SET_START_MODMULT + Configure whether or not to start the modular multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MULT + Starts multiplication + 0x814 + 0x20 + + + SET_START_MULT + Configure whether or not to start the multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + QUERY_IDLE + Represents the RSA status + 0x818 + 0x20 + + + QUERY_IDLE + Represents the RSA status. + +0: Busy + +1: Idle + 0 + 1 + read-only + + + + + INT_CLR + Clears RSA interrupt + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Write 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + Configures the constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configures the constant_time option. + +0: Acceleration + +1: No acceleration (default) + 0 + 1 + read-write + + + + + SEARCH_ENABLE + Configures the search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure the search option. + +0: No acceleration (default) + +1: Acceleration + +This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + Configures the search position + 0x828 + 0x20 + + + SEARCH_POS + Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + Enables the RSA interrupt + 0x82C + 0x20 + + + INT_ENA + Write 1 to enable the RSA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + LP_ADC + Low-power Analog to Digital Converter + RTCADC + 0x50127000 + + 0x0 + 0x80 + registers + + + LP_ADC + 9 + + + + READER1_CTRL + Control the read operation of ADC1. + 0x0 + 0x20 + 0x20040002 + + + SAR1_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR1_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR1_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR1_DATA_INV + Invert SAR ADC1 data. + 28 + 1 + read-write + + + SAR1_INT_EN + Enable saradc1 to send out interrupt. + 29 + 1 + read-write + + + SAR1_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 30 + 2 + read-write + + + + + READER1_STATUS + N/A + 0x4 + 0x20 + 0x20000000 + + + SAR1_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS1_CTRL1 + N/A + 0x8 + 0x20 + + + FORCE_XPD_AMP + N/A + 24 + 2 + read-write + + + AMP_RST_FB_FORCE + N/A + 26 + 2 + read-write + + + AMP_SHORT_REF_FORCE + N/A + 28 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + N/A + 30 + 2 + read-write + + + + + MEAS1_CTRL2 + ADC1 configuration registers. + 0xC + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data. + 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication. + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap. + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS1_MUX + SAR ADC1 MUX register. + 0x10 + 0x20 + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL. + 31 + 1 + read-write + + + + + ATTEN1 + ADC1 attenuation registers. + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + AMP_CTRL1 + N/A + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + N/A + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL2 + N/A + 0x1C + 0x20 + 0x000A0000 + + + SAR1_DAC_XPD_FSM_IDLE + N/A + 0 + 1 + read-write + + + XPD_SAR_AMP_FSM_IDLE + N/A + 1 + 1 + read-write + + + AMP_RST_FB_FSM_IDLE + N/A + 2 + 1 + read-write + + + AMP_SHORT_REF_FSM_IDLE + N/A + 3 + 1 + read-write + + + AMP_SHORT_REF_GND_FSM_IDLE + N/A + 4 + 1 + read-write + + + XPD_SAR_FSM_IDLE + N/A + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + N/A + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL3 + N/A + 0x20 + 0x20 + 0x007338F3 + + + SAR1_DAC_XPD_FSM + N/A + 0 + 4 + read-write + + + XPD_SAR_AMP_FSM + N/A + 4 + 4 + read-write + + + AMP_RST_FB_FSM + N/A + 8 + 4 + read-write + + + AMP_SHORT_REF_FSM + N/A + 12 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + N/A + 16 + 4 + read-write + + + XPD_SAR_FSM + N/A + 20 + 4 + read-write + + + SAR_RSTB_FSM + N/A + 24 + 4 + read-write + + + + + READER2_CTRL + Control the read operation of ADC2. + 0x24 + 0x20 + 0x40050002 + + + SAR2_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR2_WAIT_ARB_CYCLE + Wait arbit stable after sar_done. + 16 + 2 + read-write + + + SAR2_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR2_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR2_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 27 + 2 + read-write + + + SAR2_DATA_INV + Invert SAR ADC2 data. + 29 + 1 + read-write + + + SAR2_INT_EN + Enable saradc2 to send out interrupt. + 30 + 1 + read-write + + + + + READER2_STATUS + N/A + 0x28 + 0x20 + + + SAR2_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS2_CTRL1 + ADC2 configuration registers. + 0x2C + 0x20 + 0x07020200 + + + SAR2_CNTL_STATE + saradc2_cntl_fsm. + 0 + 3 + read-only + + + SAR2_PWDET_CAL_EN + RTC control pwdet enable. + 3 + 1 + read-write + + + SAR2_PKDET_CAL_EN + RTC control pkdet enable. + 4 + 1 + read-write + + + SAR2_EN_TEST + SAR2_EN_TEST. + 5 + 1 + read-write + + + SAR2_RSTB_FORCE + N/A + 6 + 2 + read-write + + + SAR2_STANDBY_WAIT + N/A + 8 + 8 + read-write + + + SAR2_RSTB_WAIT + N/A + 16 + 8 + read-write + + + SAR2_XPD_WAIT + N/A + 24 + 8 + read-write + + + + + MEAS2_CTRL2 + ADC2 configuration registers. + 0x30 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data. + 0 + 16 + read-only + + + MEAS2_DONE_SAR + SAR ADC2 conversion done indication. + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap. + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS2_MUX + SAR ADC2 MUX register. + 0x34 + 0x20 + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT. + 28 + 3 + read-write + + + SAR2_RTC_FORCE + In sleep, force to use rtc to control ADC. + 31 + 1 + read-write + + + + + ATTEN2 + ADC1 attenuation registers. + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + FORCE_WPD_SAR + In sleep, force to use rtc to control ADC + 0x3C + 0x20 + + + FORCE_XPD_SAR1 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 0 + 2 + read-write + + + FORCE_XPD_SAR2 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 2 + 2 + read-write + + + + + MEAS_STATUS + N/A + 0x40 + 0x20 + + + SARADC_MEAS_STATUS + N/A + 0 + 8 + read-only + + + + + REG_CLKEN + N/A + 0x44 + 0x20 + + + CLK_EN + N/A + 0 + 1 + read-write + + + + + COCPU_INT_RAW + Interrupt raw registers. + 0x48 + 0x20 + + + COCPU_SARADC1_INT_RAW + ADC1 Conversion is done, int raw. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_RAW + ADC2 Conversion is done, int raw. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_RAW + An errro occurs from ADC1, int raw. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_RAW + An errro occurs from ADC2, int raw. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_RAW + A wakeup event is triggered from ADC1, int raw. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_RAW + A wakeup event is triggered from ADC2, int raw. + 5 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers. + 0x4C + 0x20 + + + COCPU_SARADC1_INT_ENA + ADC1 Conversion is done, int enable. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_ENA + ADC2 Conversion is done, int enable. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_ENA + An errro occurs from ADC1, int enable. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_ENA + An errro occurs from ADC2, int enable. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_ENA + A wakeup event is triggered from ADC1, int enable. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_ENA + A wakeup event is triggered from ADC2, int enable. + 5 + 1 + read-write + + + + + INT_ST + Interrupt status registers. + 0x50 + 0x20 + + + COCPU_SARADC1_INT_ST + ADC1 Conversion is done, int status. + 0 + 1 + read-only + + + COCPU_SARADC2_INT_ST + ADC2 Conversion is done, int status. + 1 + 1 + read-only + + + COCPU_SARADC1_ERROR_INT_ST + An errro occurs from ADC1, int status. + 2 + 1 + read-only + + + COCPU_SARADC2_ERROR_INT_ST + An errro occurs from ADC2, int status. + 3 + 1 + read-only + + + COCPU_SARADC1_WAKE_INT_ST + A wakeup event is triggered from ADC1, int status. + 4 + 1 + read-only + + + COCPU_SARADC2_WAKE_INT_ST + A wakeup event is triggered from ADC2, int status. + 5 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers. + 0x54 + 0x20 + + + COCPU_SARADC1_INT_CLR + ADC1 Conversion is done, int clear. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_CLR + ADC2 Conversion is done, int clear. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_CLR + An errro occurs from ADC1, int clear. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_CLR + An errro occurs from ADC2, int clear. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_CLR + A wakeup event is triggered from ADC1, int clear. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_CLR + A wakeup event is triggered from ADC2, int clear. + 5 + 1 + write-only + + + + + INT_ENA_W1TS + Interrupt enable assert registers. + 0x58 + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TS + ADC1 Conversion is done, write 1 to assert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TS + ADC2 Conversion is done, write 1 to assert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TS + An errro occurs from ADC1, write 1 to assert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TS + An errro occurs from ADC2, write 1 to assert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC1, write 1 to assert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC2, write 1 to assert int enable. + 5 + 1 + write-only + + + + + INT_ENA_W1TC + Interrupt enable deassert registers. + 0x5C + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TC + ADC1 Conversion is done, write 1 to deassert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TC + ADC2 Conversion is done, write 1 to deassert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TC + An errro occurs from ADC1, write 1 to deassert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TC + An errro occurs from ADC2, write 1 to deassert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC1, write 1 to deassert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC2, write 1 to deassert int enable. + 5 + 1 + write-only + + + + + WAKEUP1 + ADC1 wakeup configuration registers. + 0x60 + 0x20 + 0x03FFC000 + + + SAR1_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR1_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR1_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR1_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR1_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP2 + ADC2 wakeup configuration registers. + 0x64 + 0x20 + 0x03FFC000 + + + SAR2_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR2_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR2_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR2_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR2_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP_SEL + Wakeup source select register. + 0x68 + 0x20 + + + SAR_WAKEUP_SEL + 0: ADC1. 1: ADC2. + 0 + 1 + read-write + + + + + SAR1_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x6C + 0x20 + 0x000000C8 + + + ADC1_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC1_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + SAR2_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x70 + 0x20 + 0x000000C8 + + + ADC2_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC2_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x74 + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x78 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x7C + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + LP_TIMER + Low-power Timer + RTC_TIMER + 0x50112000 + + 0x0 + 0x4C + registers + + + LP_TIMER0 + 2 + + + LP_TIMER1 + 3 + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_TOUCH + LP_TOUCH Peripheral + RTC_TOUCH + 0x50128000 + + 0x0 + 0x64 + registers + + + LP_TOUCH + 14 + + + + INT_RAW + need_des + 0x0 + 0x20 + + + SCAN_DONE_INT_RAW + need_des + 0 + 1 + read-write + + + DONE_INT_RAW + need_des + 1 + 1 + read-write + + + ACTIVE_INT_RAW + need_des + 2 + 1 + read-write + + + INACTIVE_INT_RAW + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_RAW + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_RAW + need_des + 5 + 1 + read-write + + + + + INT_ST + need_des + 0x4 + 0x20 + + + SCAN_DONE_INT_ST + need_des + 0 + 1 + read-only + + + DONE_INT_ST + need_des + 1 + 1 + read-only + + + ACTIVE_INT_ST + need_des + 2 + 1 + read-only + + + INACTIVE_INT_ST + need_des + 3 + 1 + read-only + + + TIMEOUT_INT_ST + need_des + 4 + 1 + read-only + + + APPROACH_LOOP_DONE_INT_ST + need_des + 5 + 1 + read-only + + + + + INT_ENA + need_des + 0x8 + 0x20 + + + SCAN_DONE_INT_ENA + need_des + 0 + 1 + read-write + + + DONE_INT_ENA + need_des + 1 + 1 + read-write + + + ACTIVE_INT_ENA + need_des + 2 + 1 + read-write + + + INACTIVE_INT_ENA + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_ENA + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_ENA + need_des + 5 + 1 + read-write + + + + + INT_CLR + need_des + 0xC + 0x20 + + + SCAN_DONE_INT_CLR + need_des + 0 + 1 + write-only + + + DONE_INT_CLR + need_des + 1 + 1 + write-only + + + ACTIVE_INT_CLR + need_des + 2 + 1 + write-only + + + INACTIVE_INT_CLR + need_des + 3 + 1 + write-only + + + TIMEOUT_INT_CLR + need_des + 4 + 1 + write-only + + + APPROACH_LOOP_DONE_INT_CLR + need_des + 5 + 1 + write-only + + + + + CHN_STATUS + need_des + 0x10 + 0x20 + + + PAD_ACTIVE + need_des + 0 + 15 + read-only + + + MEAS_DONE + need_des + 15 + 1 + read-only + + + SCAN_CURR + need_des + 16 + 4 + read-only + + + + + STATUS_0 + need_des + 0x14 + 0x20 + + + PAD0_DATA + need_des + 0 + 16 + read-only + + + PAD0_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD0_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_1 + need_des + 0x18 + 0x20 + + + PAD1_DATA + need_des + 0 + 16 + read-only + + + PAD1_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD1_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_2 + need_des + 0x1C + 0x20 + + + PAD2_DATA + need_des + 0 + 16 + read-only + + + PAD2_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD2_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_3 + need_des + 0x20 + 0x20 + + + PAD3_DATA + need_des + 0 + 16 + read-only + + + PAD3_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD3_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_4 + need_des + 0x24 + 0x20 + + + PAD4_DATA + need_des + 0 + 16 + read-only + + + PAD4_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD4_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_5 + need_des + 0x28 + 0x20 + + + PAD5_DATA + need_des + 0 + 16 + read-only + + + PAD5_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD5_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_6 + need_des + 0x2C + 0x20 + + + PAD6_DATA + need_des + 0 + 16 + read-only + + + PAD6_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD6_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_7 + need_des + 0x30 + 0x20 + + + PAD7_DATA + need_des + 0 + 16 + read-only + + + PAD7_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD7_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_8 + need_des + 0x34 + 0x20 + + + PAD8_DATA + need_des + 0 + 16 + read-only + + + PAD8_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD8_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_9 + need_des + 0x38 + 0x20 + + + PAD9_DATA + need_des + 0 + 16 + read-only + + + PAD9_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD9_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_10 + need_des + 0x3C + 0x20 + + + PAD10_DATA + need_des + 0 + 16 + read-only + + + PAD10_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD10_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_11 + need_des + 0x40 + 0x20 + + + PAD11_DATA + need_des + 0 + 16 + read-only + + + PAD11_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD11_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_12 + need_des + 0x44 + 0x20 + + + PAD12_DATA + need_des + 0 + 16 + read-only + + + PAD12_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD12_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_13 + need_des + 0x48 + 0x20 + + + PAD13_DATA + need_des + 0 + 16 + read-only + + + PAD13_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD13_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_14 + need_des + 0x4C + 0x20 + + + PAD14_DATA + need_des + 0 + 16 + read-only + + + PAD14_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD14_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_15 + need_des + 0x50 + 0x20 + + + SLP_DATA + need_des + 0 + 16 + read-only + + + SLP_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + SLP_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_16 + need_des + 0x54 + 0x20 + + + APPROACH_PAD2_CNT + need_des + 0 + 8 + read-only + + + APPROACH_PAD1_CNT + need_des + 8 + 8 + read-only + + + APPROACH_PAD0_CNT + need_des + 16 + 8 + read-only + + + SLP_APPROACH_CNT + need_des + 24 + 8 + read-only + + + + + STATUS_17 + need_des + 0x58 + 0x20 + + + DCAP_LPF + Reserved + 0 + 7 + read-only + + + DRES_LPF + need_des + 7 + 2 + read-only + + + DRV_LS + need_des + 9 + 4 + read-only + + + DRV_HS + need_des + 13 + 5 + read-only + + + DBIAS + need_des + 18 + 5 + read-only + + + RTC_FREQ_SCAN_CNT + need_des + 23 + 2 + read-only + + + + + CHN_TMP_STATUS + need_des + 0x5C + 0x20 + + + PAD_INACTIVE_STATUS + need_des + 0 + 15 + read-only + + + PAD_ACTIVE_STATUS + need_des + 15 + 15 + read-only + + + + + DATE + need_des + 0x100 + 0x20 + 0x00230314 + + + RTC_DATE + need_des + 0 + 28 + read-write + + + RTC_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_WDT + Low-power Watchdog Timer + RTC_WDT + 0x50116000 + + 0x0 + 0x38 + registers + + + LP_WDT + 1 + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + FEED + need_des + 0x14 + 0x20 + + + FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-write + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + SDHOST + SD/MMC Host Controller + SDHOST + 0x50083000 + + 0x0 + 0xB0 + registers + + + + CTRL + Control register + 0x0 + 0x20 + + + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 + 1 + read-write + + + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 + 1 + read-write + + + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 + read-write + + + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 + 1 + read-write + + + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 + 1 + read-write + + + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 + 1 + read-write + + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + + + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 + read-write + + + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 + read-write + + + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 + read-write + + + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 + read-write + + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + + + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 + read-write + + + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 + 2 + read-write + + + + + TMOUT + Data and response timeout configuration register + 0x14 + 0x20 + 0xFFFFFF40 + + + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 + read-write + + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + + + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 + read-write + + + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. + 16 + 2 + read-write + + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + + + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 + read-write + + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + + + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 + 2 + read-write + + + + + CMDARG + Command argument data register + 0x28 + 0x20 + + + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 + read-write + + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + + + INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 + 1 + read-write + + + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 + read-write + + + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 + 1 + read-write + + + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 + 1 + read-write + + + TRANSFER_MODE + 0: Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 + 1 + read-write + + + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. + 13 + 1 + read-write + + + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. + 14 + 1 + read-write + + + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. + 15 + 1 + read-write + + + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. + 16 + 5 + read-write + + + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 + 1 + read-write + + + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 + 1 + read-write + + + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 + 1 + read-write + + + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 + read-write + + + + + RESP0 + Response data register + 0x30 + 0x20 + + + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only + + + + + RESP1 + Long response data register + 0x34 + 0x20 + + + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only + + + + + RESP2 + Long response data register + 0x38 + 0x20 + + + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + + RESP3 + Long response data register + 0x3C + 0x20 + + + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 + 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 + 2 + read-write + + + + + STATUS + SD/MMC status register + 0x48 + 0x20 + 0x00000716 + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. + 0 + 1 + read-only + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. + 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 + 1 + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only + + + + + FIFOTH + FIFO configuration register + 0x4C + 0x20 + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 + read-write + + + + + CDETECT + Card detect register + 0x50 + 0x20 + + + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + WRTPRT + Card write protection (WP) status register + 0x54 + 0x20 + + + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + TCBCNT + Transferred byte count register + 0x5C + 0x20 + + + TCBCNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-only + + + + + TBBCNT + Transferred byte count register + 0x60 + 0x20 + + + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-only + + + + + DEBNCE + Debounce filter time configuration register + 0x64 + 0x20 + + + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. + 0 + 24 + read-write + + + + + USRID + User ID (scratchpad) register + 0x68 + 0x20 + + + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. + 0 + 32 + read-write + + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + + + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only + + + + + HCON + Hardware feature register + 0x70 + 0x20 + 0x03444CC3 + + + CARD_TYPE + Hardware support SDIO and MMC. + 0 + 1 + read-only + + + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. + 7 + 3 + read-only + + + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 + 2 + read-only + + + + + UHS + UHS-1 register + 0x74 + 0x20 + + + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. + 16 + 2 + read-write + + + + + RST_N + Card reset register + 0x78 + 0x20 + 0x00000001 + + + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + 0 + 2 + read-write + + + + + BMOD + Burst mode transfer configuration register + 0x80 + 0x20 + + + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. + 0 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 + read-write + + + + + PLDMND + Poll demand configuration register + 0x84 + 0x20 + + + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . + 0 + 32 + write-only + + + + + DBADDR + Descriptor base address register + 0x88 + 0x20 + + + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. + 0 + 32 + read-write + + + + + IDSTS + IDMAC status register + 0x8C + 0x20 + + + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + 0 + 1 + read-write + + + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 + 1 + read-write + + + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 + 1 + read-write + + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + + + + + IDINTEN + IDMAC interrupt enable register + 0x90 + 0x20 + + + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 + read-write + + + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. + 8 + 1 + read-write + + + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 + read-write + + + + + DSCADDR + Host descriptor address pointer + 0x94 + 0x20 + + + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. + 0 + 32 + read-only + + + + + BUFADDR + Host buffer address pointer register + 0x98 + 0x20 + + + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. + 0 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 + read-write + + + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. + 2 + 1 + read-write + + + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 + read-write + + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + + + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 + 2 + read-write + + + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 + read-write + + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + + + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 + read-write + + + + + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 + 0x20 + + + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + 0 + 32 + read-write + + + + + CLK_EDGE_SEL + SDIO control register. + 0x800 + 0x20 + 0x00820200 + + + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. + 0 + 3 + read-write + + + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 + read-write + + + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 + read-write + + + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 + read-write + + + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 + read-write + + + CCLLKIN_EDGE_N + The clock division of cclk_in. + 17 + 4 + read-write + + + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable. + 23 + 1 + read-write + + + ULTRA_HIGH_SPEED_MODE + Enable ultra high speed mode, use dll to generate clk. + 24 + 1 + read-write + + + + + RAW_INTS + SDIO raw ints register. + 0x804 + 0x20 + + + RAW_INTS + It indicates raw ints. + 0 + 32 + read-only + + + + + DLL_CLK_CONF + SDIO DLL clock control register. + 0x808 + 0x20 + + + DLL_CCLK_IN_SLF_EN + Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 0 + 1 + read-write + + + DLL_CCLK_IN_DRV_EN + Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 1 + 1 + read-write + + + DLL_CCLK_IN_SAM_EN + Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 2 + 1 + read-write + + + DLL_CCLK_IN_SLF_PHASE + It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 3 + 6 + read-write + + + DLL_CCLK_IN_DRV_PHASE + It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 9 + 6 + read-write + + + DLL_CCLK_IN_SAM_PHASE + It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 15 + 6 + read-write + + + + + DLL_CONF + SDIO DLL configuration register. + 0x80C + 0x20 + + + DLL_CAL_STOP + Set 1 to stop calibration. + 0 + 1 + read-write + + + DLL_CAL_END + 1 means calibration finished. + 1 + 1 + read-only + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x50091000 + + 0x0 + 0xB0 + registers + + + SHA + 70 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 16 + 0x4 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x20 + + + 16 + 0x4 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x20 + + + + + SOC_ETM + Event Task Matrix + SOC_ETM + 0x500D5000 + + 0x0 + 0x228 + registers + + + + CH_ENA_AD0 + Channel enable status register + 0x0 + 0x20 + + + CH_ENA0 + Represents ch0 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA1 + Represents ch1 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA2 + Represents ch2 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA3 + Represents ch3 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA4 + Represents ch4 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA5 + Represents ch5 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA6 + Represents ch6 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA7 + Represents ch7 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA8 + Represents ch8 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA9 + Represents ch9 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA10 + Represents ch10 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA11 + Represents ch11 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA12 + Represents ch12 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA13 + Represents ch13 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA14 + Represents ch14 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA15 + Represents ch15 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA16 + Represents ch16 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA17 + Represents ch17 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + CH_ENA18 + Represents ch18 enable status.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + CH_ENA19 + Represents ch19 enable status.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + CH_ENA20 + Represents ch20 enable status.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + CH_ENA21 + Represents ch21 enable status.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + CH_ENA22 + Represents ch22 enable status.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + CH_ENA23 + Represents ch23 enable status.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + CH_ENA24 + Represents ch24 enable status.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + CH_ENA25 + Represents ch25 enable status.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + CH_ENA26 + Represents ch26 enable status.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + CH_ENA27 + Represents ch27 enable status.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + CH_ENA28 + Represents ch28 enable status.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + CH_ENA29 + Represents ch29 enable status.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + CH_ENA30 + Represents ch30 enable status.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + CH_ENA31 + Represents ch31 enable status.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + CH_ENA_AD0_SET + Channel enable set register + 0x4 + 0x20 + + + CH_SET0 + Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET1 + Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET2 + Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET3 + Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET4 + Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET5 + Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET6 + Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET7 + Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET8 + Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET9 + Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET10 + Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET11 + Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET12 + Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET13 + Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET14 + Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET15 + Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET16 + Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET17 + Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + CH_SET18 + Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + 18 + 1 + write-only + + + CH_SET19 + Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + 19 + 1 + write-only + + + CH_SET20 + Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + 20 + 1 + write-only + + + CH_SET21 + Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + 21 + 1 + write-only + + + CH_SET22 + Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + 22 + 1 + write-only + + + CH_SET23 + Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + 23 + 1 + write-only + + + CH_SET24 + Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + 24 + 1 + write-only + + + CH_SET25 + Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + 25 + 1 + write-only + + + CH_SET26 + Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + 26 + 1 + write-only + + + CH_SET27 + Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + 27 + 1 + write-only + + + CH_SET28 + Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + 28 + 1 + write-only + + + CH_SET29 + Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + 29 + 1 + write-only + + + CH_SET30 + Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + 30 + 1 + write-only + + + CH_SET31 + Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + 31 + 1 + write-only + + + + + CH_ENA_AD0_CLR + Channel enable clear register + 0x8 + 0x20 + + + CH_CLR0 + Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR1 + Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR2 + Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR3 + Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR4 + Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR5 + Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR6 + Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR7 + Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR8 + Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR9 + Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR10 + Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR11 + Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR12 + Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR13 + Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR14 + Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR15 + Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR16 + Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR17 + Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + CH_CLR18 + Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + CH_CLR19 + Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + CH_CLR20 + Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + CH_CLR21 + Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + CH_CLR22 + Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + CH_CLR23 + Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + CH_CLR24 + Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + CH_CLR25 + Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + CH_CLR26 + Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + CH_CLR27 + Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + CH_CLR28 + Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + CH_CLR29 + Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + CH_CLR30 + Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + CH_CLR31 + Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + CH_ENA_AD1 + Channel enable status register + 0xC + 0x20 + + + CH_ENA32 + Represents ch32 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA33 + Represents ch33 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA34 + Represents ch34 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA35 + Represents ch35 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA36 + Represents ch36 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA37 + Represents ch37 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA38 + Represents ch38 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA39 + Represents ch39 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA40 + Represents ch40 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA41 + Represents ch41 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA42 + Represents ch42 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA43 + Represents ch43 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA44 + Represents ch44 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA45 + Represents ch45 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA46 + Represents ch46 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA47 + Represents ch47 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA48 + Represents ch48 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA49 + Represents ch49 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + + + CH_ENA_AD1_SET + Channel enable set register + 0x10 + 0x20 + + + CH_SET32 + Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET33 + Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET34 + Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET35 + Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET36 + Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET37 + Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET38 + Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET39 + Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET40 + Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET41 + Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET42 + Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET43 + Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET44 + Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET45 + Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET46 + Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET47 + Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET48 + Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET49 + Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + + + CH_ENA_AD1_CLR + Channel enable clear register + 0x14 + 0x20 + + + CH_CLR32 + Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR33 + Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR34 + Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR35 + Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR36 + Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR37 + Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR38 + Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR39 + Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR40 + Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR41 + Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR42 + Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR43 + Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR44 + Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR45 + Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR46 + Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR47 + Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR48 + Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR49 + Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + + + CH0_EVT_ID + Channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + Configures ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + Channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + Configures ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + Channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + Configures ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + Channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + Configures ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + Channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + Configures ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + Channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + Configures ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + Channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + Configures ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + Channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + Configures ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + Channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + Configures ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + Channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + Configures ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + Channel5 event id register + 0x40 + 0x20 + + + CH5_EVT_ID + Configures ch5_evt_id + 0 + 8 + read-write + + + + + CH5_TASK_ID + Channel5 task id register + 0x44 + 0x20 + + + CH5_TASK_ID + Configures ch5_task_id + 0 + 8 + read-write + + + + + CH6_EVT_ID + Channel6 event id register + 0x48 + 0x20 + + + CH6_EVT_ID + Configures ch6_evt_id + 0 + 8 + read-write + + + + + CH6_TASK_ID + Channel6 task id register + 0x4C + 0x20 + + + CH6_TASK_ID + Configures ch6_task_id + 0 + 8 + read-write + + + + + CH7_EVT_ID + Channel7 event id register + 0x50 + 0x20 + + + CH7_EVT_ID + Configures ch7_evt_id + 0 + 8 + read-write + + + + + CH7_TASK_ID + Channel7 task id register + 0x54 + 0x20 + + + CH7_TASK_ID + Configures ch7_task_id + 0 + 8 + read-write + + + + + CH8_EVT_ID + Channel8 event id register + 0x58 + 0x20 + + + CH8_EVT_ID + Configures ch8_evt_id + 0 + 8 + read-write + + + + + CH8_TASK_ID + Channel8 task id register + 0x5C + 0x20 + + + CH8_TASK_ID + Configures ch8_task_id + 0 + 8 + read-write + + + + + CH9_EVT_ID + Channel9 event id register + 0x60 + 0x20 + + + CH9_EVT_ID + Configures ch9_evt_id + 0 + 8 + read-write + + + + + CH9_TASK_ID + Channel9 task id register + 0x64 + 0x20 + + + CH9_TASK_ID + Configures ch9_task_id + 0 + 8 + read-write + + + + + CH10_EVT_ID + Channel10 event id register + 0x68 + 0x20 + + + CH10_EVT_ID + Configures ch10_evt_id + 0 + 8 + read-write + + + + + CH10_TASK_ID + Channel10 task id register + 0x6C + 0x20 + + + CH10_TASK_ID + Configures ch10_task_id + 0 + 8 + read-write + + + + + CH11_EVT_ID + Channel11 event id register + 0x70 + 0x20 + + + CH11_EVT_ID + Configures ch11_evt_id + 0 + 8 + read-write + + + + + CH11_TASK_ID + Channel11 task id register + 0x74 + 0x20 + + + CH11_TASK_ID + Configures ch11_task_id + 0 + 8 + read-write + + + + + CH12_EVT_ID + Channel12 event id register + 0x78 + 0x20 + + + CH12_EVT_ID + Configures ch12_evt_id + 0 + 8 + read-write + + + + + CH12_TASK_ID + Channel12 task id register + 0x7C + 0x20 + + + CH12_TASK_ID + Configures ch12_task_id + 0 + 8 + read-write + + + + + CH13_EVT_ID + Channel13 event id register + 0x80 + 0x20 + + + CH13_EVT_ID + Configures ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + Channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + Configures ch13_task_id + 0 + 8 + read-write + + + + + CH14_EVT_ID + Channel14 event id register + 0x88 + 0x20 + + + CH14_EVT_ID + Configures ch14_evt_id + 0 + 8 + read-write + + + + + CH14_TASK_ID + Channel14 task id register + 0x8C + 0x20 + + + CH14_TASK_ID + Configures ch14_task_id + 0 + 8 + read-write + + + + + CH15_EVT_ID + Channel15 event id register + 0x90 + 0x20 + + + CH15_EVT_ID + Configures ch15_evt_id + 0 + 8 + read-write + + + + + CH15_TASK_ID + Channel15 task id register + 0x94 + 0x20 + + + CH15_TASK_ID + Configures ch15_task_id + 0 + 8 + read-write + + + + + CH16_EVT_ID + Channel16 event id register + 0x98 + 0x20 + + + CH16_EVT_ID + Configures ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + Channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + Configures ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + Channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + Configures ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + Channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + Configures ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + Channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + Configures ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + Channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + Configures ch18_task_id + 0 + 8 + read-write + + + + + CH19_EVT_ID + Channel19 event id register + 0xB0 + 0x20 + + + CH19_EVT_ID + Configures ch19_evt_id + 0 + 8 + read-write + + + + + CH19_TASK_ID + Channel19 task id register + 0xB4 + 0x20 + + + CH19_TASK_ID + Configures ch19_task_id + 0 + 8 + read-write + + + + + CH20_EVT_ID + Channel20 event id register + 0xB8 + 0x20 + + + CH20_EVT_ID + Configures ch20_evt_id + 0 + 8 + read-write + + + + + CH20_TASK_ID + Channel20 task id register + 0xBC + 0x20 + + + CH20_TASK_ID + Configures ch20_task_id + 0 + 8 + read-write + + + + + CH21_EVT_ID + Channel21 event id register + 0xC0 + 0x20 + + + CH21_EVT_ID + Configures ch21_evt_id + 0 + 8 + read-write + + + + + CH21_TASK_ID + Channel21 task id register + 0xC4 + 0x20 + + + CH21_TASK_ID + Configures ch21_task_id + 0 + 8 + read-write + + + + + CH22_EVT_ID + Channel22 event id register + 0xC8 + 0x20 + + + CH22_EVT_ID + Configures ch22_evt_id + 0 + 8 + read-write + + + + + CH22_TASK_ID + Channel22 task id register + 0xCC + 0x20 + + + CH22_TASK_ID + Configures ch22_task_id + 0 + 8 + read-write + + + + + CH23_EVT_ID + Channel23 event id register + 0xD0 + 0x20 + + + CH23_EVT_ID + Configures ch23_evt_id + 0 + 8 + read-write + + + + + CH23_TASK_ID + Channel23 task id register + 0xD4 + 0x20 + + + CH23_TASK_ID + Configures ch23_task_id + 0 + 8 + read-write + + + + + CH24_EVT_ID + Channel24 event id register + 0xD8 + 0x20 + + + CH24_EVT_ID + Configures ch24_evt_id + 0 + 8 + read-write + + + + + CH24_TASK_ID + Channel24 task id register + 0xDC + 0x20 + + + CH24_TASK_ID + Configures ch24_task_id + 0 + 8 + read-write + + + + + CH25_EVT_ID + Channel25 event id register + 0xE0 + 0x20 + + + CH25_EVT_ID + Configures ch25_evt_id + 0 + 8 + read-write + + + + + CH25_TASK_ID + Channel25 task id register + 0xE4 + 0x20 + + + CH25_TASK_ID + Configures ch25_task_id + 0 + 8 + read-write + + + + + CH26_EVT_ID + Channel26 event id register + 0xE8 + 0x20 + + + CH26_EVT_ID + Configures ch26_evt_id + 0 + 8 + read-write + + + + + CH26_TASK_ID + Channel26 task id register + 0xEC + 0x20 + + + CH26_TASK_ID + Configures ch26_task_id + 0 + 8 + read-write + + + + + CH27_EVT_ID + Channel27 event id register + 0xF0 + 0x20 + + + CH27_EVT_ID + Configures ch27_evt_id + 0 + 8 + read-write + + + + + CH27_TASK_ID + Channel27 task id register + 0xF4 + 0x20 + + + CH27_TASK_ID + Configures ch27_task_id + 0 + 8 + read-write + + + + + CH28_EVT_ID + Channel28 event id register + 0xF8 + 0x20 + + + CH28_EVT_ID + Configures ch28_evt_id + 0 + 8 + read-write + + + + + CH28_TASK_ID + Channel28 task id register + 0xFC + 0x20 + + + CH28_TASK_ID + Configures ch28_task_id + 0 + 8 + read-write + + + + + CH29_EVT_ID + Channel29 event id register + 0x100 + 0x20 + + + CH29_EVT_ID + Configures ch29_evt_id + 0 + 8 + read-write + + + + + CH29_TASK_ID + Channel29 task id register + 0x104 + 0x20 + + + CH29_TASK_ID + Configures ch29_task_id + 0 + 8 + read-write + + + + + CH30_EVT_ID + Channel30 event id register + 0x108 + 0x20 + + + CH30_EVT_ID + Configures ch30_evt_id + 0 + 8 + read-write + + + + + CH30_TASK_ID + Channel30 task id register + 0x10C + 0x20 + + + CH30_TASK_ID + Configures ch30_task_id + 0 + 8 + read-write + + + + + CH31_EVT_ID + Channel31 event id register + 0x110 + 0x20 + + + CH31_EVT_ID + Configures ch31_evt_id + 0 + 8 + read-write + + + + + CH31_TASK_ID + Channel31 task id register + 0x114 + 0x20 + + + CH31_TASK_ID + Configures ch31_task_id + 0 + 8 + read-write + + + + + CH32_EVT_ID + Channel32 event id register + 0x118 + 0x20 + + + CH32_EVT_ID + Configures ch32_evt_id + 0 + 8 + read-write + + + + + CH32_TASK_ID + Channel32 task id register + 0x11C + 0x20 + + + CH32_TASK_ID + Configures ch32_task_id + 0 + 8 + read-write + + + + + CH33_EVT_ID + Channel33 event id register + 0x120 + 0x20 + + + CH33_EVT_ID + Configures ch33_evt_id + 0 + 8 + read-write + + + + + CH33_TASK_ID + Channel33 task id register + 0x124 + 0x20 + + + CH33_TASK_ID + Configures ch33_task_id + 0 + 8 + read-write + + + + + CH34_EVT_ID + Channel34 event id register + 0x128 + 0x20 + + + CH34_EVT_ID + Configures ch34_evt_id + 0 + 8 + read-write + + + + + CH34_TASK_ID + Channel34 task id register + 0x12C + 0x20 + + + CH34_TASK_ID + Configures ch34_task_id + 0 + 8 + read-write + + + + + CH35_EVT_ID + Channel35 event id register + 0x130 + 0x20 + + + CH35_EVT_ID + Configures ch35_evt_id + 0 + 8 + read-write + + + + + CH35_TASK_ID + Channel35 task id register + 0x134 + 0x20 + + + CH35_TASK_ID + Configures ch35_task_id + 0 + 8 + read-write + + + + + CH36_EVT_ID + Channel36 event id register + 0x138 + 0x20 + + + CH36_EVT_ID + Configures ch36_evt_id + 0 + 8 + read-write + + + + + CH36_TASK_ID + Channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + Configures ch36_task_id + 0 + 8 + read-write + + + + + CH37_EVT_ID + Channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + Configures ch37_evt_id + 0 + 8 + read-write + + + + + CH37_TASK_ID + Channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + Configures ch37_task_id + 0 + 8 + read-write + + + + + CH38_EVT_ID + Channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + Configures ch38_evt_id + 0 + 8 + read-write + + + + + CH38_TASK_ID + Channel38 task id register + 0x14C + 0x20 + + + CH38_TASK_ID + Configures ch38_task_id + 0 + 8 + read-write + + + + + CH39_EVT_ID + Channel39 event id register + 0x150 + 0x20 + + + CH39_EVT_ID + Configures ch39_evt_id + 0 + 8 + read-write + + + + + CH39_TASK_ID + Channel39 task id register + 0x154 + 0x20 + + + CH39_TASK_ID + Configures ch39_task_id + 0 + 8 + read-write + + + + + CH40_EVT_ID + Channel40 event id register + 0x158 + 0x20 + + + CH40_EVT_ID + Configures ch40_evt_id + 0 + 8 + read-write + + + + + CH40_TASK_ID + Channel40 task id register + 0x15C + 0x20 + + + CH40_TASK_ID + Configures ch40_task_id + 0 + 8 + read-write + + + + + CH41_EVT_ID + Channel41 event id register + 0x160 + 0x20 + + + CH41_EVT_ID + Configures ch41_evt_id + 0 + 8 + read-write + + + + + CH41_TASK_ID + Channel41 task id register + 0x164 + 0x20 + + + CH41_TASK_ID + Configures ch41_task_id + 0 + 8 + read-write + + + + + CH42_EVT_ID + Channel42 event id register + 0x168 + 0x20 + + + CH42_EVT_ID + Configures ch42_evt_id + 0 + 8 + read-write + + + + + CH42_TASK_ID + Channel42 task id register + 0x16C + 0x20 + + + CH42_TASK_ID + Configures ch42_task_id + 0 + 8 + read-write + + + + + CH43_EVT_ID + Channel43 event id register + 0x170 + 0x20 + + + CH43_EVT_ID + Configures ch43_evt_id + 0 + 8 + read-write + + + + + CH43_TASK_ID + Channel43 task id register + 0x174 + 0x20 + + + CH43_TASK_ID + Configures ch43_task_id + 0 + 8 + read-write + + + + + CH44_EVT_ID + Channel44 event id register + 0x178 + 0x20 + + + CH44_EVT_ID + Configures ch44_evt_id + 0 + 8 + read-write + + + + + CH44_TASK_ID + Channel44 task id register + 0x17C + 0x20 + + + CH44_TASK_ID + Configures ch44_task_id + 0 + 8 + read-write + + + + + CH45_EVT_ID + Channel45 event id register + 0x180 + 0x20 + + + CH45_EVT_ID + Configures ch45_evt_id + 0 + 8 + read-write + + + + + CH45_TASK_ID + Channel45 task id register + 0x184 + 0x20 + + + CH45_TASK_ID + Configures ch45_task_id + 0 + 8 + read-write + + + + + CH46_EVT_ID + Channel46 event id register + 0x188 + 0x20 + + + CH46_EVT_ID + Configures ch46_evt_id + 0 + 8 + read-write + + + + + CH46_TASK_ID + Channel46 task id register + 0x18C + 0x20 + + + CH46_TASK_ID + Configures ch46_task_id + 0 + 8 + read-write + + + + + CH47_EVT_ID + Channel47 event id register + 0x190 + 0x20 + + + CH47_EVT_ID + Configures ch47_evt_id + 0 + 8 + read-write + + + + + CH47_TASK_ID + Channel47 task id register + 0x194 + 0x20 + + + CH47_TASK_ID + Configures ch47_task_id + 0 + 8 + read-write + + + + + CH48_EVT_ID + Channel48 event id register + 0x198 + 0x20 + + + CH48_EVT_ID + Configures ch48_evt_id + 0 + 8 + read-write + + + + + CH48_TASK_ID + Channel48 task id register + 0x19C + 0x20 + + + CH48_TASK_ID + Configures ch48_task_id + 0 + 8 + read-write + + + + + CH49_EVT_ID + Channel49 event id register + 0x1A0 + 0x20 + + + CH49_EVT_ID + Configures ch49_evt_id + 0 + 8 + read-write + + + + + CH49_TASK_ID + Channel49 task id register + 0x1A4 + 0x20 + + + CH49_TASK_ID + Configures ch49_task_id + 0 + 8 + read-write + + + + + EVT_ST0 + Events trigger status register + 0x1A8 + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST + Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_EVT_CH1_RISE_EDGE_ST + Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_EVT_CH2_RISE_EDGE_ST + Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_EVT_CH3_RISE_EDGE_ST + Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_EVT_CH4_RISE_EDGE_ST + Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_EVT_CH5_RISE_EDGE_ST + Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_EVT_CH6_RISE_EDGE_ST + Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_EVT_CH7_RISE_EDGE_ST + Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_EVT_CH0_FALL_EDGE_ST + Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_EVT_CH1_FALL_EDGE_ST + Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_EVT_CH2_FALL_EDGE_ST + Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_EVT_CH3_FALL_EDGE_ST + Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_EVT_CH4_FALL_EDGE_ST + Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_EVT_CH5_FALL_EDGE_ST + Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_EVT_CH6_FALL_EDGE_ST + Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_EVT_CH7_FALL_EDGE_ST + Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_EVT_CH0_ANY_EDGE_ST + Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_EVT_CH1_ANY_EDGE_ST + Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_EVT_CH2_ANY_EDGE_ST + Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_EVT_CH3_ANY_EDGE_ST + Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_EVT_CH4_ANY_EDGE_ST + Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_EVT_CH5_ANY_EDGE_ST + Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_EVT_CH6_ANY_EDGE_ST + Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_EVT_CH7_ANY_EDGE_ST + Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS0_ST + Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG0_ST + Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS1_ST + Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG1_ST + Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST + Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST + Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST + Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST + Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST0_CLR + Events trigger status clear register + 0x1AC + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_EVT_CH1_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_EVT_CH2_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_EVT_CH3_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_EVT_CH4_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_EVT_CH5_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_EVT_CH6_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_EVT_CH7_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_EVT_CH0_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_EVT_CH1_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_EVT_CH2_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_EVT_CH3_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_EVT_CH4_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_EVT_CH5_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_EVT_CH6_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_EVT_CH7_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_EVT_CH0_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_EVT_CH1_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_EVT_CH2_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_EVT_CH3_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_EVT_CH4_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_EVT_CH5_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_EVT_CH6_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_EVT_CH7_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST1 + Events trigger status register + 0x1B0 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST + Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST + Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST + Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST + Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST + Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST + Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST + Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST + Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST + Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST + Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST + Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST + Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER0_ST + Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER1_ST + Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER2_ST + Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER3_ST + Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_EVT_TIMER0_CMP_ST + Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_EVT_TIMER1_CMP_ST + Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_EVT_TIMER2_CMP_ST + Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_EVT_TIMER3_CMP_ST + Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER0_ST + Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER1_ST + Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER0_ST + Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER1_ST + Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP0_ST + Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP1_ST + Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP2_ST + Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_TIMER0_STOP_ST + Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_TIMER1_STOP_ST + Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_TIMER2_STOP_ST + Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEZ_ST + Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEZ_ST + Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST1_CLR + Events trigger status clear register + 0x1B4 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER0_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER1_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER2_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER3_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_EVT_TIMER0_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_EVT_TIMER1_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_EVT_TIMER2_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_EVT_TIMER3_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP0_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP1_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP2_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST2 + Events trigger status register + 0x1B8 + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST + Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEP_ST + Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEP_ST + Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_EVT_TIMER2_TEP_ST + Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_EVT_OP0_TEA_ST + Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_EVT_OP1_TEA_ST + Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM0_EVT_OP2_TEA_ST + Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM0_EVT_OP0_TEB_ST + Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM0_EVT_OP1_TEB_ST + Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM0_EVT_OP2_TEB_ST + Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM0_EVT_F0_ST + Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM0_EVT_F1_ST + Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM0_EVT_F2_ST + Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM0_EVT_F0_CLR_ST + Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM0_EVT_F1_CLR_ST + Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM0_EVT_F2_CLR_ST + Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_EVT_TZ0_CBC_ST + Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_EVT_TZ1_CBC_ST + Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_EVT_TZ2_CBC_ST + Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_EVT_TZ0_OST_ST + Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_EVT_TZ1_OST_ST + Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_EVT_TZ2_OST_ST + Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_EVT_CAP0_ST + Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_EVT_CAP1_ST + Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_EVT_CAP2_ST + Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE1_ST + Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE1_ST + Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE1_ST + Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE2_ST + Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE2_ST + Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE2_ST + Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_TIMER0_STOP_ST + Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST2_CLR + Events trigger status clear register + 0x1BC + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM0_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM0_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM0_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM0_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM0_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM0_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM0_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM0_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM0_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM0_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST3 + Events trigger status register + 0x1C0 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST + Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_TIMER2_STOP_ST + Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEZ_ST + Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEZ_ST + Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEZ_ST + Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEP_ST + Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEP_ST + Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEP_ST + Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_EVT_OP0_TEA_ST + Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_EVT_OP1_TEA_ST + Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_EVT_OP2_TEA_ST + Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_EVT_OP0_TEB_ST + Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_EVT_OP1_TEB_ST + Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_EVT_OP2_TEB_ST + Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_EVT_F0_ST + Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_EVT_F1_ST + Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_EVT_F2_ST + Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_EVT_F0_CLR_ST + Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_EVT_F1_CLR_ST + Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_EVT_F2_CLR_ST + Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_EVT_TZ0_CBC_ST + Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_EVT_TZ1_CBC_ST + Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_EVT_TZ2_CBC_ST + Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_EVT_TZ0_OST_ST + Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_EVT_TZ1_OST_ST + Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_EVT_TZ2_OST_ST + Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_EVT_CAP0_ST + Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_EVT_CAP1_ST + Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM1_EVT_CAP2_ST + Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM1_EVT_OP0_TEE1_ST + Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE1_ST + Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE1_ST + Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST3_CLR + Events trigger status clear register + 0x1C4 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM1_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM1_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST4 + Events trigger status register + 0x1C8 + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST + Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE2_ST + Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE2_ST + Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + ADC_EVT_CONV_CMPLT0_ST + Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH0_ST + Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH1_ST + Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH0_ST + Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH1_ST + Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + ADC_EVT_RESULT_DONE0_ST + Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + ADC_EVT_STOPPED0_ST + Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + ADC_EVT_STARTED0_ST + Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + REGDMA_EVT_DONE0_ST + Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + REGDMA_EVT_DONE1_ST + Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + REGDMA_EVT_DONE2_ST + Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + REGDMA_EVT_DONE3_ST + Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + REGDMA_EVT_ERR0_ST + Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + REGDMA_EVT_ERR1_ST + Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + REGDMA_EVT_ERR2_ST + Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + REGDMA_EVT_ERR3_ST + Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + TMPSNSR_EVT_OVER_LIMIT_ST + Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + I2S0_EVT_RX_DONE_ST + Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + I2S0_EVT_TX_DONE_ST + Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + I2S0_EVT_X_WORDS_RECEIVED_ST + Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + I2S0_EVT_X_WORDS_SENT_ST + Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + I2S1_EVT_RX_DONE_ST + Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + I2S1_EVT_TX_DONE_ST + Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + I2S1_EVT_X_WORDS_RECEIVED_ST + Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + I2S1_EVT_X_WORDS_SENT_ST + Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + I2S2_EVT_RX_DONE_ST + Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + I2S2_EVT_TX_DONE_ST + Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + I2S2_EVT_X_WORDS_RECEIVED_ST + Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + I2S2_EVT_X_WORDS_SENT_ST + Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST4_CLR + Events trigger status clear register + 0x1CC + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + ADC_EVT_CONV_CMPLT0_ST_CLR + Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + ADC_EVT_RESULT_DONE0_ST_CLR + Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + ADC_EVT_STOPPED0_ST_CLR + Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + ADC_EVT_STARTED0_ST_CLR + Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + REGDMA_EVT_DONE0_ST_CLR + Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + REGDMA_EVT_DONE1_ST_CLR + Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + REGDMA_EVT_DONE2_ST_CLR + Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + REGDMA_EVT_DONE3_ST_CLR + Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + REGDMA_EVT_ERR0_ST_CLR + Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + REGDMA_EVT_ERR1_ST_CLR + Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + REGDMA_EVT_ERR2_ST_CLR + Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + REGDMA_EVT_ERR3_ST_CLR + Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + TMPSNSR_EVT_OVER_LIMIT_ST_CLR + Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + I2S0_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + I2S0_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + I2S0_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + I2S0_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + I2S1_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + I2S1_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + I2S1_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + I2S1_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + I2S2_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + I2S2_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + I2S2_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + I2S2_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST5 + Events trigger status register + 0x1D0 + 0x20 + + + ULP_EVT_ERR_INTR_ST + Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + ULP_EVT_HALT_ST + Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + ULP_EVT_START_INTR_ST + Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + RTC_EVT_TICK_ST + Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + RTC_EVT_OVF_ST + Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + RTC_EVT_CMP_ST + Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH0_ST + Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH1_ST + Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH2_ST + Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST + Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST + Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST + Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST + Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST + Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST + Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST5_CLR + Events trigger status clear register + 0x1D4 + 0x20 + + + ULP_EVT_ERR_INTR_ST_CLR + Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + ULP_EVT_HALT_ST_CLR + Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + ULP_EVT_START_INTR_ST_CLR + Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + RTC_EVT_TICK_ST_CLR + Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + RTC_EVT_OVF_ST_CLR + Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + RTC_EVT_CMP_ST_CLR + Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST6 + Events trigger status register + 0x1D8 + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH0_ST + Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH1_ST + Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH2_ST + Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST + Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST + Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST + Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST + Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST + Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST + Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PMU_EVT_SLEEP_WEEKUP_ST + Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH0_ST + Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH1_ST + Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST + Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST6_CLR + Events trigger status clear register + 0x1DC + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PMU_EVT_SLEEP_WEEKUP_ST_CLR + Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST7 + Events trigger status register + 0x1E0 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST + Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH0_ST + Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH1_ST + Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH2_ST + Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH0_ST + Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH1_ST + Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH2_ST + Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST + Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST + Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST + Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + + + EVT_ST7_CLR + Events trigger status clear register + 0x1E4 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + + + TASK_ST0 + Tasks trigger status register + 0x1E8 + 0x20 + + + GPIO_TASK_CH0_SET_ST + Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_TASK_CH1_SET_ST + Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_TASK_CH2_SET_ST + Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_TASK_CH3_SET_ST + Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_TASK_CH4_SET_ST + Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_TASK_CH5_SET_ST + Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_TASK_CH6_SET_ST + Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_TASK_CH7_SET_ST + Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_TASK_CH0_CLEAR_ST + Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_TASK_CH1_CLEAR_ST + Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_TASK_CH2_CLEAR_ST + Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_TASK_CH3_CLEAR_ST + Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_TASK_CH4_CLEAR_ST + Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_TASK_CH5_CLEAR_ST + Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_TASK_CH6_CLEAR_ST + Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_TASK_CH7_CLEAR_ST + Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_TASK_CH0_TOGGLE_ST + Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_TASK_CH1_TOGGLE_ST + Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_TASK_CH2_TOGGLE_ST + Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_TASK_CH3_TOGGLE_ST + Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_TASK_CH4_TOGGLE_ST + Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_TASK_CH5_TOGGLE_ST + Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_TASK_CH6_TOGGLE_ST + Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_TASK_CH7_TOGGLE_ST + Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RES_UPDATE_ST + Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RES_UPDATE_ST + Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RES_UPDATE_ST + Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RES_UPDATE_ST + Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST + Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST + Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST + Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST + Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST0_CLR + Tasks trigger status clear register + 0x1EC + 0x20 + + + GPIO_TASK_CH0_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_TASK_CH1_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_TASK_CH2_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_TASK_CH3_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_TASK_CH4_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_TASK_CH5_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_TASK_CH6_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_TASK_CH7_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_TASK_CH0_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_TASK_CH1_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_TASK_CH2_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_TASK_CH3_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_TASK_CH4_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_TASK_CH5_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_TASK_CH6_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_TASK_CH7_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_TASK_CH0_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_TASK_CH1_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_TASK_CH2_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_TASK_CH3_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_TASK_CH4_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_TASK_CH5_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_TASK_CH6_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_TASK_CH7_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST1 + Tasks trigger status register + 0x1F0 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST + Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST + Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST + Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST + Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_TIMER0_CAP_ST + Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_TIMER1_CAP_ST + Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_TIMER2_CAP_ST + Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_TIMER3_CAP_ST + Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST + Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST + Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST + Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST + Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST + Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST + Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST + Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST + Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH0_ST + Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH1_ST + Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH2_ST + Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH3_ST + Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH4_ST + Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH5_ST + Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH6_ST + Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH7_ST + Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RST_ST + Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RST_ST + Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RST_ST + Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RST_ST + Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_TIMER0_RESUME_ST + Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_TIMER1_RESUME_ST + Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_TIMER2_RESUME_ST + Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_TIMER3_RESUME_ST + Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST1_CLR + Tasks trigger status clear register + 0x1F4 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_TIMER0_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_TIMER1_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_TIMER2_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_TIMER3_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_TIMER0_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_TIMER1_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_TIMER2_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_TIMER3_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST2 + Tasks trigger status register + 0x1F8 + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST + Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_TIMER1_PAUSE_ST + Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_TIMER2_PAUSE_ST + Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_TIMER3_PAUSE_ST + Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH0_ST + Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH1_ST + Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH2_ST + Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH3_ST + Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH4_ST + Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH5_ST + Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH6_ST + Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH7_ST + Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST + Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST + Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST + Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST + Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST + Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST + Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST + Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST + Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH0_ST + Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH1_ST + Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH2_ST + Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH3_ST + Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH4_ST + Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH5_ST + Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH6_ST + Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH7_ST + Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER0_ST + Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER0_ST + Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER0_ST + Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER0_ST + Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST2_CLR + Tasks trigger status clear register + 0x1FC + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_TIMER1_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_TIMER2_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_TIMER3_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST3 + Tasks trigger status register + 0x200 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST + Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER1_ST + Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER1_ST + Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER1_ST + Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER1_ST + Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TG0_TASK_CNT_CAP_TIMER1_ST + Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER0_ST + Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER0_ST + Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER0_ST + Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER0_ST + Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER0_ST + Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER1_ST + Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER1_ST + Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER1_ST + Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER1_ST + Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER1_ST + Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_TASK_CMPR0_A_UP_ST + Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_TASK_CMPR1_A_UP_ST + Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_TASK_CMPR2_A_UP_ST + Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_TASK_CMPR0_B_UP_ST + Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_TASK_CMPR1_B_UP_ST + Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_TASK_CMPR2_B_UP_ST + Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_TASK_GEN_STOP_ST + Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_TASK_TIMER0_SYN_ST + Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_TASK_TIMER1_SYN_ST + Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_TASK_TIMER2_SYN_ST + Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_TASK_TZ0_OST_ST + Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_TASK_TZ1_OST_ST + Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_TASK_TZ2_OST_ST + Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST3_CLR + Tasks trigger status clear register + 0x204 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TG0_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST4 + Tasks trigger status register + 0x208 + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST + Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_TASK_CLR1_OST_ST + Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_TASK_CLR2_OST_ST + Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_TASK_CAP0_ST + Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_TASK_CAP1_ST + Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_TASK_CAP2_ST + Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_TASK_CMPR0_A_UP_ST + Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_TASK_CMPR1_A_UP_ST + Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_TASK_CMPR2_A_UP_ST + Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_TASK_CMPR0_B_UP_ST + Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_TASK_CMPR1_B_UP_ST + Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_TASK_CMPR2_B_UP_ST + Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_TASK_GEN_STOP_ST + Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_TASK_TIMER0_SYN_ST + Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_TASK_TIMER1_SYN_ST + Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_TASK_TIMER2_SYN_ST + Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_TASK_TZ0_OST_ST + Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_TASK_TZ1_OST_ST + Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_TASK_TZ2_OST_ST + Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_TASK_CLR0_OST_ST + Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_TASK_CLR1_OST_ST + Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_TASK_CLR2_OST_ST + Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_TASK_CAP0_ST + Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_TASK_CAP1_ST + Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_TASK_CAP2_ST + Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + ADC_TASK_SAMPLE0_ST + Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + ADC_TASK_SAMPLE1_ST + Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + ADC_TASK_START0_ST + Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + ADC_TASK_STOP0_ST + Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST4_CLR + Tasks trigger status clear register + 0x20C + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + ADC_TASK_SAMPLE0_ST_CLR + Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + ADC_TASK_SAMPLE1_ST_CLR + Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + ADC_TASK_START0_ST_CLR + Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + ADC_TASK_STOP0_ST_CLR + Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST5 + Tasks trigger status register + 0x210 + 0x20 + + + REGDMA_TASK_START0_ST + Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + REGDMA_TASK_START1_ST + Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + REGDMA_TASK_START2_ST + Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + REGDMA_TASK_START3_ST + Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TMPSNSR_TASK_START_SAMPLE_ST + Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TMPSNSR_TASK_STOP_SAMPLE_ST + Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + I2S0_TASK_START_RX_ST + Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + I2S0_TASK_START_TX_ST + Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + I2S0_TASK_STOP_RX_ST + Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + I2S0_TASK_STOP_TX_ST + Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + I2S1_TASK_START_RX_ST + Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + I2S1_TASK_START_TX_ST + Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + I2S1_TASK_STOP_RX_ST + Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + I2S1_TASK_STOP_TX_ST + Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + I2S2_TASK_START_RX_ST + Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + I2S2_TASK_START_TX_ST + Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + I2S2_TASK_STOP_RX_ST + Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + I2S2_TASK_STOP_TX_ST + Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + ULP_TASK_WAKEUP_CPU_ST + Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + ULP_TASK_INT_CPU_ST + Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + RTC_TASK_START_ST + Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + RTC_TASK_STOP_ST + Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + RTC_TASK_CLR_ST + Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + RTC_TASK_TRIGGERFLW_ST + Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH0_ST + Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH1_ST + Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH2_ST + Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH0_ST + Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH1_ST + Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH2_ST + Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH0_ST + Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH1_ST + Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST5_CLR + Tasks trigger status clear register + 0x214 + 0x20 + + + REGDMA_TASK_START0_ST_CLR + Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + REGDMA_TASK_START1_ST_CLR + Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + REGDMA_TASK_START2_ST_CLR + Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + REGDMA_TASK_START3_ST_CLR + Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TMPSNSR_TASK_START_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TMPSNSR_TASK_STOP_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + I2S0_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + I2S0_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + I2S0_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + I2S0_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + I2S1_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + I2S1_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + I2S1_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + I2S1_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + I2S2_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + I2S2_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + I2S2_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + I2S2_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + ULP_TASK_WAKEUP_CPU_ST_CLR + Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + ULP_TASK_INT_CPU_ST_CLR + Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + RTC_TASK_START_ST_CLR + Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + RTC_TASK_STOP_ST_CLR + Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + RTC_TASK_CLR_ST_CLR + Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + RTC_TASK_TRIGGERFLW_ST_CLR + Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST6 + Tasks trigger status register + 0x218 + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST + Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH0_ST + Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH1_ST + Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH2_ST + Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PMU_TASK_SLEEP_REQ_ST + Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_TASK_IN_START_CH0_ST + Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_TASK_IN_START_CH1_ST + Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST + Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST + Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH0_ST + Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH1_ST + Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH2_ST + Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST + Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST + Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST + Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + + + TASK_ST6_CLR + Tasks trigger status clear register + 0x21C + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PMU_TASK_SLEEP_REQ_ST_CLR + Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + + + CLK_EN + ETM clock enable register + 0x220 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + DATE + ETM date register + 0x224 + 0x20 + 0x02303031 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x5008C000 + + 0x0 + 0x14C + registers + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-write + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-write + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-write + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-write + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x01002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-write + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-write + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-write + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-write + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-write + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-write + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-write + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-write + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-write + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-write + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-write + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0x80C00000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-write + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-write + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-write + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-write + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-write + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-write + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-write + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-write + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-write + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-write + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-write + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-write + + + SPI_MEM_SDIN_HEX + For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_SDOUT_HEX + For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + 27 + 1 + read-write + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-write + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + write-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + write-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + write-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + write-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + write-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + write-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow. + 31 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash PMS section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash PMS section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash PMS section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash PMS section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM PMS section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM PMS section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 27 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 27 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 5 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-write + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-write + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-write + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-write + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + + + SPI_SMEM_AXI_ADDR_CTRL + SPI0 AXI address control register + 0x178 + 0x20 + 0xFC000000 + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_MEM_AXI_ERR_RESP_EN + SPI0 AXI error response enable register + 0x17C + 0x20 + + + SPI_MEM_AW_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi write trans. + 0 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi write trans. + 1 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi write trans. + 2 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_FLASH + Set this bit to enable AXI response function for axi flash err in axi write trans. + 3 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi write trans. + 4 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sens in err axi write trans. + 5 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_WSTRB + Set this bit to enable AXI response function for axi wstrb err in axi write trans. + 6 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi read trans. + 7 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi read trans. + 8 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi read trans. + 9 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sensitive err in axi read trans. + 10 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi read trans. + 11 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-write + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-write + + + + + SPI_SMEM_DIN_HEX_MODE + MSPI 16x external RAM input timing delay mode control register + 0x1A4 + 0x20 + + + SPI_SMEM_DIN08_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN09_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN10_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN11_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN12_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN13_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN14_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN15_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_HEX_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_HEX_NUM + MSPI 16x external RAM input timing delay number control register + 0x1A8 + 0x20 + + + SPI_SMEM_DIN08_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN09_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN10_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN11_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN12_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN13_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN14_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN15_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_HEX_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_HEX_MODE + MSPI 16x external RAM output timing adjustment control register + 0x1AC + 0x20 + + + SPI_SMEM_DOUT08_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT09_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT10_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT11_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT12_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT13_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT14_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT15_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_HEX_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-write + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-write + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-write + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02303100 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x5008D000 + + 0x0 + 0xAC + registers + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02111240 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x500D0000 + + 0x0 + 0x98 + registers + + + SPI2 + 25 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SPI_CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + SPI_DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + SPI_DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller 3 + SPI3 + 0x500D1000 + + 0x0 + 0x98 + registers + + + SPI3 + 26 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x00000006 + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 3 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x500E2000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 53 + + + SYSTIMER_TARGET1 + 54 + + + SYSTIMER_TARGET2 + 55 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x500C2000 + + 0x0 + 0x68 + registers + + + TG0_T0 + 46 + + + TG0_T1 + 47 + + + TG0_WDT + 48 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02209142 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group 1 + 0x500C3000 + + TG1_T0 + 49 + + + TG1_T1 + 50 + + + TG1_WDT + 51 + + + + TRACE0 + TRACE0 Peripheral + TRACE + 0x3FF04000 + + 0x0 + 0x4C + registers + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_START_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + Represent whether the fifo is empty. \\1: empty \\0: not empty + 0 + 1 + read-only + + + WORK_STATUS + Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due to hart halted or havereset \\3: lost state + 1 + 2 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clear fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clear mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + Configure whether or not start trace.\\1: start trace \\0: invalid\\ + 0 + 1 + write-only + + + OFF + Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + 1 + 1 + write-only + + + MEM_LOOP + Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + 2 + 1 + read-write + + + RESTART_ENA + Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + 3 + 1 + read-write + + + + + CONFIG + trace configuration register + 0x24 + 0x20 + + + DM_TRIGGER_ENA + Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + 0 + 1 + read-write + + + RESET_ENA + Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ + 1 + 1 + read-write + + + HALT_ENA + Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + 2 + 1 + read-write + + + STALL_ENA + Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\1: enabled.\\0: disabled\\ + 3 + 1 + read-write + + + FULL_ADDRESS + Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta address mode\\ + 4 + 1 + read-write + + + IMPLICIT_EXCEPT + Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\1: enabled\\0: disabled\\ + 5 + 1 + read-write + + + + + FILTER_CONTROL + filter control register + 0x28 + 0x20 + + + FILTER_EN + Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + 0 + 1 + read-write + + + MATCH_COMP + when set, the comparator must be high in order for the filter to match + 1 + 1 + read-write + + + MATCH_PRIVILEGE + when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + 2 + 1 + read-write + + + MATCH_ECAUSE + when set, start matching from exception cause codes specified by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception. + 3 + 1 + read-write + + + MATCH_INTERRUPT + when set, start matching from a trap with the interrupt level codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap. + 4 + 1 + read-write + + + + + FILTER_MATCH_CONTROL + filter match control register + 0x2C + 0x20 + + + MATCH_CHOICE_PRIVILEGE + Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: user mode + 0 + 1 + read-write + + + MATCH_VALUE_INTERRUPT + Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: match itype or 1. + 1 + 1 + read-write + + + MATCH_CHOICE_ECAUSE + specified which ecause matched. + 2 + 6 + read-write + + + + + FILTER_COMPARATOR_CONTROL + filter comparator match control register + 0x30 + 0x20 + + + P_INPUT + Determines which input to compare against the primary comparator, \\0: iaddr, \\1: tval. + 0 + 1 + read-write + + + P_FUNCTION + Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 2 + 3 + read-write + + + P_NOTIFY + Generate a trace packet explicitly reporting the address that cause the primary match + 5 + 1 + read-write + + + S_INPUT + Determines which input to compare against the secondary comparator, \\0: iaddr, \\1: tval. + 8 + 1 + read-write + + + S_FUNCTION + Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 10 + 3 + read-write + + + S_NOTIFY + Generate a trace packet explicitly reporting the address that cause the secondary match + 13 + 1 + read-write + + + MATCH_MODE + 0: only primary matches, \\1: primary and secondary comparator both matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: set when primary matches and continue to match until after secondary comparator matches + 16 + 2 + read-write + + + + + FILTER_P_COMPARATOR_MATCH + primary comparator match value + 0x34 + 0x20 + + + P_MATCH + primary comparator match value + 0 + 32 + read-write + + + + + FILTER_S_COMPARATOR_MATCH + secondary comparator match value + 0x38 + 0x20 + + + S_MATCH + secondary comparator match value + 0 + 32 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x3C + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + 24 + 2 + read-write + + + + + AHB_CONFIG + AHB config register + 0x40 + 0x20 + + + HBURST + set hburst + 0 + 3 + read-write + + + MAX_INCR + set max continuous access for incr mode + 3 + 3 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x44 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02211300 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + TRACE1 + TRACE1 Peripheral + 0x3FF05000 + + + LP_TSENS + Low-power Temperature Sensor + TSENS + 0x5012F000 + + 0x0 + 0x38 + registers + + + LP_TSENS + 15 + + + + CTRL + Tsens configuration. + 0x0 + 0x20 + 0x00019400 + + + OUT + Temperature sensor data out. + 0 + 8 + read-only + + + READY + Indicate temperature sensor out ready. + 8 + 1 + read-only + + + SAMPLE_EN + Enable sample signal for wakeup module. + 9 + 1 + read-write + + + WAKEUP_MASK + Wake up signal mask. + 10 + 1 + read-write + + + INT_EN + Enable temperature sensor to send out interrupt. + 12 + 1 + read-write + + + IN_INV + Invert temperature sensor data. + 13 + 1 + read-write + + + CLK_DIV + Temperature sensor clock divider. + 14 + 8 + read-write + + + POWER_UP + Temperature sensor power up. + 22 + 1 + read-write + + + POWER_UP_FORCE + 1: dump out & power up controlled by SW, 0: by FSM. + 23 + 1 + read-write + + + + + CTRL2 + Tsens configuration. + 0x4 + 0x20 + 0x00004002 + + + XPD_WAIT + N/A + 0 + 12 + read-write + + + XPD_FORCE + N/A + 12 + 2 + read-write + + + CLK_INV + N/A + 14 + 1 + read-write + + + + + INT_RAW + Tsens interrupt raw registers. + 0x8 + 0x20 + + + COCPU_TSENS_WAKE_INT_RAW + Tsens wakeup interrupt raw. + 0 + 1 + read-write + + + + + INT_ST + Tsens interrupt status registers. + 0xC + 0x20 + + + COCPU_TSENS_WAKE_INT_ST + Tsens wakeup interrupt status. + 0 + 1 + read-only + + + + + INT_ENA + Tsens interrupt enable registers. + 0x10 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA + Tsens wakeup interrupt enable. + 0 + 1 + read-write + + + + + INT_CLR + Tsens interrupt clear registers. + 0x14 + 0x20 + + + COCPU_TSENS_WAKE_INT_CLR + Tsens wakeup interrupt clear. + 0 + 1 + write-only + + + + + CLK_CONF + Tsens regbank configuration registers. + 0x18 + 0x20 + + + CLK_EN + Tsens regbank clock gating enable. + 0 + 1 + read-write + + + + + INT_ENA_W1TS + Tsens wakeup interrupt enable assert. + 0x1C + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TS + Write 1 to this field to assert interrupt enable. + 0 + 1 + write-only + + + + + INT_ENA_W1TC + Tsens wakeup interrupt enable deassert. + 0x20 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TC + Write 1 to this field to deassert interrupt enable. + 0 + 1 + write-only + + + + + WAKEUP_CTRL + Tsens wakeup control registers. + 0x24 + 0x20 + 0x003FC000 + + + WAKEUP_TH_LOW + Lower threshold. + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + Upper threshold. + 14 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + WAKEUP_EN + Tsens wakeup enable. + 30 + 1 + read-write + + + WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + SAMPLE_RATE + Hardware automatic sampling control registers. + 0x28 + 0x20 + 0x00000014 + + + SAMPLE_RATE + Hardware automatic sampling rate. + 0 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x2C + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x30 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x34 + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x500D7000 + + 0x0 + 0x8C + registers + + + TWAI0 + 40 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + ACCEPTANCE_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQUEST + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUFFER + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RECEIVE_BUFFER + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TRANSMIT_BUFFER + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + NODE_BUS_OFF + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + TS_COUNTER_OVFL_INT_ST + 1: this bit is set then the timestamp counter reaches the maximum value and overflow. + 4 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + TS_COUNTER_OVFL_INT_ENA + enable the timestamp counter overflow interrupt request. + 4 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEGMENT1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEGMENT2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMPLING + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + DATA_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + DATA_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + DATA_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + DATA_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + DATA_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + DATA_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + DATA_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + DATA_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + DATA_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + DATA_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + DATA_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + DATA_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_COUNTER + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + TIMESTAMP_DATA + Timestamp data register + 0x94 + 0x20 + + + TIMESTAMP_DATA + Data of timestamp of a CAN frame. + 0 + 32 + read-only + + + + + TIMESTAMP_PRESCALER + Timestamp configuration register + 0x98 + 0x20 + 0x0000001F + + + TS_DIV_NUM + Configures the clock division number of timestamp counter. + 0 + 16 + read-write + + + + + TIMESTAMP_CFG + Timestamp configuration register + 0x9C + 0x20 + + + TS_ENABLE + enable the timestamp collection function. + 0 + 1 + read-write + + + + + + + TWAI1 + Two-Wire Automotive Interface + 0x500D8000 + + TWAI1 + 41 + + + + TWAI2 + Two-Wire Automotive Interface + 0x500D9000 + + TWAI2 + 42 + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x500CA000 + + 0x0 + 0x98 + registers + + + UART0 + 31 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-write + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + a + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x500CB000 + + UART1 + 32 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + 0x500CC000 + + UART2 + 33 + + + + UART3 + UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + 0x500CD000 + + UART3 + 34 + + + + UART4 + UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + 0x500CE000 + + UART4 + 35 + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x500DF000 + + 0x0 + 0x84 + registers + + + UHCI0 + 30 + + + + CONF0 + UHCI Configuration Register0 + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART_SEL + Select which uart to connect with GDMA. + 2 + 3 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + UHCI Interrupt Raw Register + 0x4 + 0x20 + + + RX_START_INT_RAW + Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + 0 + 1 + read-write + + + TX_START_INT_RAW + Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + 1 + 1 + read-write + + + RX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + 5 + 1 + read-write + + + OUT_EOF_INT_RAW + Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + 6 + 1 + read-write + + + APP_CTRL0_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + 8 + 1 + read-write + + + + + INT_ST + UHCI Interrupt Status Register + 0x8 + 0x20 + + + RX_START_INT_ST + Indicates the interrupt status of UHCI_RX_START_INT. + 0 + 1 + read-only + + + TX_START_INT_ST + Indicates the interrupt status of UHCI_TX_START_INT. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + Indicates the interrupt status of UHCI_RX_HUNG_INT. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + Indicates the interrupt status of UHCI_TX_HUNG_INT. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + Indicates the interrupt status of UHCI_OUT_EOF_INT. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL0_INT. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL1_INT. + 8 + 1 + read-only + + + + + INT_ENA + UHCI Interrupt Enable Register + 0xC + 0x20 + + + RX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_START_INT. + 0 + 1 + read-write + + + TX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_START_INT. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + read-write + + + + + INT_CLR + UHCI Interrupt Clear Register + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + write-only + + + + + CONF1 + UHCI Configuration Register1 + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable head checksum check when receiving. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable sequence number check when receiving. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation, and data integrity check bit should 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save data packet head when UHCI receive data. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode data packet with checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode data packet with ACK when reliable data packet is ready. + 5 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + 7 + 1 + read-write + + + SW_START + Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + 8 + 1 + write-only + + + + + STATE0 + UHCI Receive Status Register + 0x18 + 0x20 + + + RX_ERR_CAUSE + Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + Indicates UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI Transmit Status Register + 0x1C + 0x20 + + + ENCODE_STATE + Indicates UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + UHCI Escapes Configuration Register0 + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable resolve char 0xC0 when DMA receiving data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable resolve char 0xDB when DMA receiving data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xDB with special char when DMA receiving data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing 0x11 with special char when DMA receiving data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing 0x13 with special char when DMA receiving data. + 7 + 1 + read-write + + + + + HUNG_CONF + UHCI Hung Configuration Register0 + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when receiving. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when DMA sending data. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI Ack Value Configuration Register0 + 0x28 + 0x20 + + + ACK_NUM + Indicates the ACK number during software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to load the ACK value of UHCI_ACK_NUM. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI Head Register + 0x2C + 0x20 + + + RX_HEAD + Stores the head of received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UCHI Quick send Register + 0x30 + 0x20 + + + SINGLE_SEND_NUM + Configures single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable sending short packet with single_send mode. + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + Configures always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable sending short packet with always_send mode. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + UHCI Q0_WORD0 Quick Send Register + 0x34 + 0x20 + + + SEND_Q0_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + UHCI Q0_WORD1 Quick Send Register + 0x38 + 0x20 + + + SEND_Q0_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + UHCI Q1_WORD0 Quick Send Register + 0x3C + 0x20 + + + SEND_Q1_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + UHCI Q1_WORD1 Quick Send Register + 0x40 + 0x20 + + + SEND_Q1_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + UHCI Q2_WORD0 Quick Send Register + 0x44 + 0x20 + + + SEND_Q2_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + UHCI Q2_WORD1 Quick Send Register + 0x48 + 0x20 + + + SEND_Q2_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + UHCI Q3_WORD0 Quick Send Register + 0x4C + 0x20 + + + SEND_Q3_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + UHCI Q3_WORD1 Quick Send Register + 0x50 + 0x20 + + + SEND_Q3_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + UHCI Q4_WORD0 Quick Send Register + 0x54 + 0x20 + + + SEND_Q4_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + UHCI Q4_WORD1 Quick Send Register + 0x58 + 0x20 + + + SEND_Q4_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + UHCI Q5_WORD0 Quick Send Register + 0x5C + 0x20 + + + SEND_Q5_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + UHCI Q5_WORD1 Quick Send Register + 0x60 + 0x20 + + + SEND_Q5_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + UHCI Q6_WORD0 Quick Send Register + 0x64 + 0x20 + + + SEND_Q6_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + UHCI Q6_WORD1 Quick Send Register + 0x68 + 0x20 + + + SEND_Q6_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + UHCI Escapes Sequence Configuration Register0 + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + Configures the delimiter for encoding, default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + UHCI Escapes Sequence Configuration Register1 + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + Configures the char needing encoding, which is 0xDB as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + UHCI Escapes Sequence Configuration Register2 + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + Configures the char needing encoding, which is 0x11 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + UHCI Escapes Sequence Configuration Register3 + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + Configures the char needing encoding, which is 0x13 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + UCHI Packet Length Configuration Register + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI Version Register + 0x80 + 0x20 + 0x02201100 + + + DATE + Configures version. + 0 + 32 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x500D2000 + + 0x0 + 0x8C + registers + + + USB_DEVICE + 22 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + USB_SERIAL_JTAG_RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-only + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-write + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + USB_SERIAL_JTAG_PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + USB_SERIAL_JTAG_PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + USB_SERIAL_JTAG_VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + USB_SERIAL_JTAG_VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + USB_SERIAL_JTAG_VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + USB_SERIAL_JTAG_TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + USB_SERIAL_JTAG_IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + USB_SERIAL_JTAG_SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + USB_SERIAL_JTAG_OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + USB_SERIAL_JTAG_CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + USB_SERIAL_JTAG_RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + USB_SERIAL_JTAG_DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + USB_SERIAL_JTAG_BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + USB_SERIAL_JTAG_BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + USB_SERIAL_JTAG_BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + USB_SERIAL_JTAG_GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + USB_SERIAL_JTAG_GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + USB_SERIAL_JTAG_CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + ECO_LOW_48 + Reserved. + 0x6C + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_48 + Reserved. + 0x70 + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_48 + Reserved. + 0x74 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_48 + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_48 + Reserved. + 1 + 1 + read-write + + + + + ECO_LOW_APB + Reserved. + 0x78 + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_APB + Reserved. + 0x7C + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_APB + Reserved. + 0x80 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_APB + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_APB + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x84 + 0x20 + 0x00001320 + + + USB_SERIAL_JTAG_MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + Date register + 0x88 + 0x20 + 0x02112010 + + + USB_SERIAL_JTAG_DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + USB_WRAP Peripheral + USB_WRAP + 0x50080000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB wrapper configuration registers. + 0x0 + 0x20 + 0x00100000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV. + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV. + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold. + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown. + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup. + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown. + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup. + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown. + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on. + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on. + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers. + 31 + 1 + read-write + + + + + TEST_CONF + USB wrapper test configuration registers. + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad. + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test. + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test. + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test. + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test. + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test. + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test. + 6 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x23030504 + + + USB_WRAP_DATE + Date register. + 0 + 32 + read-only + + + + + + + \ No newline at end of file diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2-ulp.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2-ulp.svd new file mode 100644 index 000000000..d026169c5 --- /dev/null +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2-ulp.svd @@ -0,0 +1,2681 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S2-ULP + RISC-V ULP + 1 + 32-bit RISC-V MCU + + Copyright 2023 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + RTC_IO + Low-power Input/Output + RTCIO + 0x0000A400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO output register + 0x0 + 0x20 + + + GPIO_OUT_DATA + GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + RTC GPIO output bit set register + 0x4 + 0x20 + + + GPIO_OUT_DATA_W1TS + GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + RTC GPIO output bit clear register + 0x8 + 0x20 + + + GPIO_OUT_DATA_W1TC + GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + RTC GPIO output enable register + 0xC + 0x20 + + + REG_RTCIO_REG_GPIO_ENABLE + GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO output enable bit set register + 0x10 + 0x20 + + + REG_RTCIO_REG_GPIO_ENABLE_W1TS + GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE_W1TC + RTC GPIO output enable bit clear register + 0x14 + 0x20 + + + REG_RTCIO_REG_GPIO_ENABLE_W1TC + GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO interrupt status register + 0x18 + 0x20 + + + GPIO_STATUS_INT + GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt. + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + RTC GPIO interrupt status bit set register + 0x1C + 0x20 + + + GPIO_STATUS_INT_W1TS + GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + RTC GPIO interrupt status bit clear register + 0x20 + 0x20 + + + GPIO_STATUS_INT_W1TC + GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input register + 0x24 + 0x20 + + + GPIO_IN_NEXT + GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. + 10 + 22 + read-only + + + + + 22 + 0x4 + RTC_GPIO_PIN%s + RTC configuration for pin %s + 0x28 + 0x20 + + + GPIO_PIN_PAD_DRIVER + Pad driver selection. 0: normal output. 1: open drain. + 2 + 1 + read-write + + + GPIO_PIN_INT_TYPE + GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. + 7 + 3 + read-write + + + GPIO_PIN_WAKEUP_ENABLE + GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + RTC debug select register + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + 25 + 1 + read-write + + + + + 15 + 0x4 + TOUCH_PAD%s + Touch pad %s configuration register + 0x84 + 0x20 + 0x52000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 0: no sleep mode. 1: enable sleep mode. + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + Connect the RTC pad input to digital pad input. 0 is available. + 19 + 1 + read-write + + + XPD + Touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + The tie option of touch sensor. 0: tie low. 1: tie high. + 21 + 1 + read-write + + + START + Start touch sensor. + 22 + 1 + read-write + + + DAC + Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + 23 + 3 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + XTAL_32P_PAD + 32KHz crystal P-pad configuration register + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode. + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode. + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + X32P_FUN_SEL + Function selection. + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + X32P_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + X32P_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + X32P_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + XTAL_32N_PAD + 32KHz crystal N-pad configuration register + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + X32N_SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + X32N_SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + X32N_FUN_SEL + Function selection. + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + X32N_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + X32N_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + X32N_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + PAD_DAC1 + DAC1 configuration register + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + 3 + 8 + read-write + + + PDAC1_XPD_DAC + When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output. + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output. + 12 + 1 + read-write + + + PDAC1_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + PDAC1_SLP_OE + Output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + Input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode. 0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + DAC_1 function selection. + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + PDAC1_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + PDAC1_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + PAD_DAC2 + DAC2 configuration register + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + 3 + 8 + read-write + + + PDAC2_XPD_DAC + When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output. + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output. + 12 + 1 + read-write + + + PDAC2_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + PDAC2_SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + PDAC2_SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + PDAC2_FUN_SEL + DAC_2 function selection. + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + PDAC2_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + PDAC2_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + PDAC2_DRV + Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD19 + Touch pad 19 configuration register + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD20 + Touch pad 20 configuration register + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD21 + Touch pad 21 configuration register + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + External wake up configuration register + 0xDC + 0x20 + + + SEL + GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. +0: select GPIO0; 1: select GPIO2, etc + 27 + 5 + read-write + + + + + XTL_EXT_CTR + Crystal power down enable GPIO source + 0xE0 + 0x20 + + + SEL + Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. + 27 + 5 + read-write + + + + + SAR_I2C_IO + RTC I2C pad selection + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2. + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3. + 30 + 2 + read-write + + + + + RTC_IO_TOUCH_CTRL + Touch control register + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + 4 + 1 + read-write + + + + + RTC_IO_DATE + Version control register + 0x1FC + 0x20 + 0x01903170 + + + IO_DATE + Version control register + 0 + 28 + read-write + + + + + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x00008000 + + 0x0 + 0x138 + registers + + + RISCV_START_INT + 6 + + + SW_INT + 7 + + + SWD_INT + 8 + + + + ULP_CP_TIMER + Configure coprocessor timer + 0xF8 + 0x20 + + + ULP_CP_PC_INIT + ULP coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + Enable the option of ULP coprocessor woken up by +RTC GPIO + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + Disable the option of ULP coprocessor woken up by +RTC GPIO + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP coprocessor timer enable bit. 0: Disable hardware +Timer. 1: Enable hardware timer + 31 + 1 + read-write + + + + + ULP_CP_CTRL + ULP-FSM configuration register + 0xFC + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + 11 + 11 + read-write + + + ULP_CP_MEM_OFFSET_CLR + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ULP-FSM clock force on + 28 + 1 + read-write + + + ULP_CP_RESET + ULP-FSM clock software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + Write 1 to start ULP-FSM by software + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-FSM + 31 + 1 + read-write + + + + + COCPU_CTRL + ULP-RISCV configuration register + 0x100 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + ULP-RISCV clock force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + Time from ULP-RISCV startup to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + Time from ULP-RISCV startup to send out +RISCV_START_INT interrupt + 7 + 6 + read-write + + + COCPU_SHUT + Shut down ULP-RISCV + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + Time from shut down ULP-RISCV to disable clock + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + This bit is used to reset ULP-RISCV + 22 + 1 + read-write + + + COCPU_SEL + 0: select ULP-RISCV. 1: select ULP-FSM + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE +signal + 24 + 1 + read-write + + + COCPU_DONE + DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the +timer starts counting + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + Trigger ULP-RISCV register interrupt + 26 + 1 + write-only + + + + + ULP_CP_TIMER_1 + Configure sleep cycle of the timer + 0x130 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + Set sleep cycles for ULP coprocessor timer + 8 + 24 + read-write + + + + + + + RTC_I2C + Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C + 0x0000EC00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + Configure the low level width of SCL + 0x0 + 0x20 + 0x00000100 + + + PERIOD + This register is used to configure how many clock cycles SCL +remains low. + 0 + 20 + read-write + + + + + CTRL + Transmission setting + 0x4 + 0x20 + + + SDA_FORCE_OUT + SDA output mode. 0: open drain. 1: push pull. + 0 + 1 + read-write + + + SCL_FORCE_OUT + SCL output mode. 0: open drain. 1: push pull. + 1 + 1 + read-write + + + MS_MODE + Set this bit to configure RTC I²C as a master. + 2 + 1 + read-write + + + TRANS_START + Set this bit to 1, RTC I2C starts sending data. + 3 + 1 + read-write + + + TX_LSB_FIRST + This bit is used to control the sending mode. 0: send data from the most +significant bit. 1: send data from the least significant bit. + 4 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. 0: receive +data from the most significant bit. 1: receive data from the least significant bit. + 5 + 1 + read-write + + + CLK_GATE_EN + RTC I²C controller clock gate. + 29 + 1 + read-write + + + RESET + RTC I²C software reset. + 30 + 1 + read-write + + + CLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + RTC I2C status + 0x8 + 0x20 + + + ACK_REC + The received ACK value. 0: ACK. 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + 0: master writes to slave. 1: master reads from slave. + 1 + 1 + read-only + + + ARB_LOST + When the RTC I2C loses control of SCL line, the register changes to 1. + 2 + 1 + read-only + + + BUS_BUSY + 0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data. + 3 + 1 + read-only + + + SLAVE_ADDRESSED + When the address sent by the master matches the address of the +slave, then this bit will be set. + 4 + 1 + read-only + + + BYTE_TRANS + This field changes to 1 when one byte is transferred. + 5 + 1 + read-only + + + OP_CNT + Indicate which operation is working. + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + Configure RTC I2C timeout + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + Timeout threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + Configure slave address + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode. + 31 + 1 + read-write + + + + + SCL_HIGH + Configure the high level width of SCL + 0x14 + 0x20 + 0x00000100 + + + PERIOD + This register is used to configure how many cycles SCL remains high. + 0 + 20 + read-write + + + + + SDA_DUTY + Configure the SDA hold time after a negative +SCL edge + 0x18 + 0x20 + 0x00000010 + + + NUM + The number of clock cycles between the SDA switch and the falling +edge of SCL. + 0 + 20 + read-write + + + + + SCL_START_PERIOD + Configure the delay between the SDA and SCL +negative edge for a start condition + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + Number of clock cycles to wait after generating a start condition. + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + Configure the delay between SDA and SCL positive edge for a stop condition + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + Number of clock cycles to wait before generating a stop condition. + 0 + 20 + read-write + + + + + INT_CLR + Clear RTC I2C interrupt + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + RTC_I2C_MASTER_TRAN_COMP_INT interrupt +clear bit + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + RTC_I2C_TIME_OUT_INT interrupt clear bit + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + RTC_I2C_ACK_ERR_INT interrupt clear bit + 5 + 1 + write-only + + + RX_DATA_INT_CLR + RTC_I2C_RX_DATA_INT interrupt clear bit + 6 + 1 + write-only + + + TX_DATA_INT_CLR + RTC_I2C_TX_DATA_INT interrupt clear bit + 7 + 1 + write-only + + + DETECT_START_INT_CLR + RTC_I2C_DETECT_START_INT interrupt clear bit + 8 + 1 + write-only + + + + + INT_RAW + RTC I2C raw interrupt + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + RTC_I2C_TIME_OUT_INT interrupt raw bit + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + RTC_I2C_ACK_ERR_INT interrupt raw bit + 5 + 1 + read-only + + + RX_DATA_INT_RAW + RTC_I2C_RX_DATA_INT interrupt raw bit + 6 + 1 + read-only + + + TX_DATA_INT_RAW + RTC_I2C_TX_DATA_INT interrupt raw bit + 7 + 1 + read-only + + + DETECT_START_INT_RAW + RTC_I2C_DETECT_START_INT interrupt raw bit + 8 + 1 + read-only + + + + + INT_ST + RTC I2C interrupt status + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + RTC_I2C_ARBITRATION_LOST_INT interrupt status bit + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + RTC_I2C_TRANS_COMPLETE_INT interrupt status bit + 3 + 1 + read-only + + + TIME_OUT_INT_ST + RTC_I2C_TIME_OUT_INT interrupt status bit + 4 + 1 + read-only + + + ACK_ERR_INT_ST + RTC_I2C_ACK_ERR_INT interrupt status bit + 5 + 1 + read-only + + + RX_DATA_INT_ST + RTC_I2C_RX_DATA_INT interrupt status bit + 6 + 1 + read-only + + + TX_DATA_INT_ST + RTC_I2C_TX_DATA_INT interrupt status bit + 7 + 1 + read-only + + + DETECT_START_INT_ST + RTC_I2C_DETECT_START_INT interrupt status bit + 8 + 1 + read-only + + + + + INT_ENA + Enable RTC I2C interrupt + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + RTC_I2C_TIME_OUT_INT interrupt enable bit + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + RTC_I2C_ACK_ERR_INT interrupt enable bit + 5 + 1 + read-write + + + RX_DATA_INT_ENA + RTC_I2C_RX_DATA_INT interrupt enable bit + 6 + 1 + read-write + + + TX_DATA_INT_ENA + RTC_I2C_TX_DATA_INT interrupt enable bit + 7 + 1 + read-write + + + DETECT_START_INT_ENA + RTC_I2C_DETECT_START_INT interrupt enable bit + 8 + 1 + read-write + + + + + DATA + RTC I2C read data + 0x34 + 0x20 + + + RDATA + Data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + The data sent by slave + 8 + 8 + read-write + + + DONE + RTC I2C transmission is done. + 31 + 1 + read-only + + + + + CMD0 + RTC I2C Command 0 + 0x38 + 0x20 + 0x00000903 + + + COMMAND0 + Content of command 0. For more information, please refer to the register +I2C_COMD0_REG in Chapter I²C Controller + 0 + 14 + read-write + + + COMMAND0_DONE + When command 0 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD1 + RTC I2C Command 1 + 0x3C + 0x20 + 0x00001901 + + + COMMAND1 + Content of command 1. For more information, please refer to the register +I2C_COMD1_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND1_DONE + When command 1 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD2 + RTC I2C Command 2 + 0x40 + 0x20 + 0x00000902 + + + COMMAND2 + Content of command 2. For more information, please refer to the register +I2C_COMD2_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND2_DONE + When command 2 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD3 + RTC I2C Command 3 + 0x44 + 0x20 + 0x00000101 + + + COMMAND3 + Content of command 3. For more information, please refer to the register +I2C_COMD3_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND3_DONE + When command 3 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD4 + RTC I2C Command 4 + 0x48 + 0x20 + 0x00000901 + + + COMMAND4 + Content of command 4. For more information, please refer to the register +I2C_COMD4_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND4_DONE + When command 4 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD5 + RTC I2C Command 5 + 0x4C + 0x20 + 0x00001701 + + + COMMAND5 + Content of command 5. For more information, please refer to the register +I2C_COMD5_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND5_DONE + When command 5 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD6 + RTC I2C Command 6 + 0x50 + 0x20 + 0x00001901 + + + COMMAND6 + Content of command 6. For more information, please refer to the register +I2C_COMD6_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND6_DONE + When command 6 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD7 + RTC I2C Command 7 + 0x54 + 0x20 + 0x00000904 + + + COMMAND7 + Content of command 7. For more information, please refer to the register +I2C_COMD7_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND7_DONE + When command 7 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD8 + RTC I2C Command 8 + 0x58 + 0x20 + 0x00001901 + + + COMMAND8 + Content of command 8. For more information, please refer to the register +I2C_COMD8_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND8_DONE + When command 8 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD9 + RTC I2C Command 9 + 0x5C + 0x20 + 0x00000903 + + + COMMAND9 + Content of command 9. For more information, please refer to the register +I2C_COMD9_REG in Chapter I²C Controller + 0 + 14 + read-write + + + COMMAND9_DONE + When command 9 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD10 + RTC I2C Command 10 + 0x60 + 0x20 + 0x00000101 + + + COMMAND10 + Content of command 10. For more information, please refer to the register +I2C_COMD10_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND10_DONE + When command 10 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD11 + RTC I2C Command 11 + 0x64 + 0x20 + 0x00000901 + + + COMMAND11 + Content of command 11. For more information, please refer to the register +I2C_COMD11_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND11_DONE + When command 11 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD12 + RTC I2C Command 12 + 0x68 + 0x20 + 0x00001701 + + + COMMAND12 + Content of command 12. For more information, please refer to the register +I2C_COMD12_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND12_DONE + When command 12 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD13 + RTC I2C Command 13 + 0x6C + 0x20 + 0x00001901 + + + COMMAND13 + Content of command 13. For more information, please refer to the register +I2C_COMD13_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND13_DONE + When command 13 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD14 + RTC I2C Command 14 + 0x70 + 0x20 + + + COMMAND14 + Content of command 14. For more information, please refer to the register +I2C_COMD14_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND14_DONE + When command 14 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + CMD15 + RTC I2C Command 15 + 0x74 + 0x20 + + + COMMAND15 + Content of command 15. For more information, please refer to the register +I2C_COMD15_REG in Chapter I²C Controller. + 0 + 14 + read-write + + + COMMAND15_DONE + When command 15 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x01905310 + + + DATE + Version control register + 0 + 28 + read-write + + + + + + + SENS + SENS Peripheral + SENS + 0x0000C800 + + 0x0 + 0x110 + registers + + + TOUCH_DONE_INT + 0 + + + TOUCH_INACTIVE_INT + 1 + + + TOUCH_ACTIVE_INT + 2 + + + SARADC1_DONE_INT + 3 + + + SARADC2_DONE_INT + 4 + + + TSENS_DONE_INT + 5 + + + + SAR_SLAVE_ADDR1 + Configure slave addresses 0-1 of RTC I2C + 0x40 + 0x20 + + + I2C_SLAVE_ADDR1 + RTC I2C slave address 1 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR0 + RTC I2C slave address 0 + 11 + 11 + read-write + + + MEAS_STATUS + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + Configure slave addresses 2-3 of RTC I2C + 0x44 + 0x20 + + + I2C_SLAVE_ADDR3 + RTC I2C slave address 3 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR2 + RTC I2C slave address 2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + Configure slave addresses 4-5 of RTC I2C + 0x48 + 0x20 + + + I2C_SLAVE_ADDR5 + RTC I2C slave address 5 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR4 + RTC I2C slave address 4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + Configure slave addresses 6-7 of RTC I2C + 0x4C + 0x20 + + + I2C_SLAVE_ADDR7 + RTC I2C slave address 7 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR6 + RTC I2C slave address 6 + 11 + 11 + read-write + + + + + SAR_I2C_CTRL + Configure RTC I2C transmission + 0x58 + 0x20 + + + SAR_I2C_CTRL + RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = +1. + 0 + 28 + read-write + + + SAR_I2C_START + Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 0: RTC I2C started by FSM. 1: RTC I2C started by software. + 29 + 1 + read-write + + + + + SAR_COCPU_INT_RAW + Interrupt raw bit of ULP-RISCV + 0x128 + 0x20 + + + COCPU_TOUCH_DONE_INT_RAW + TOUCH_DONE_INT interrupt raw bit + 0 + 1 + read-only + + + COCPU_TOUCH_INACTIVE_INT_RAW + TOUCH_INACTIVE_INT interrupt raw bit + 1 + 1 + read-only + + + COCPU_TOUCH_ACTIVE_INT_RAW + TOUCH_ACTIVE_INT interrupt raw bit + 2 + 1 + read-only + + + COCPU_SARADC1_INT_RAW + SARADC1_DONE_INT interrupt raw bit + 3 + 1 + read-only + + + COCPU_SARADC2_INT_RAW + SARADC2_DONE_INT interrupt raw bit + 4 + 1 + read-only + + + COCPU_TSENS_INT_RAW + TSENS_DONE_INT interrupt raw bit + 5 + 1 + read-only + + + COCPU_START_INT_RAW + RISCV_START_INT interrupt raw bit + 6 + 1 + read-only + + + COCPU_SW_INT_RAW + SW_INT interrupt raw bit + 7 + 1 + read-only + + + COCPU_SWD_INT_RAW + SWD_INT interrupt raw bit + 8 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + Interrupt enable bit of ULP-RISCV + 0x12C + 0x20 + + + COCPU_TOUCH_DONE_INT_ENA + TOUCH_DONE_INT interrupt enable bit + 0 + 1 + read-write + + + COCPU_TOUCH_INACTIVE_INT_ENA + TOUCH_INACTIVE_INT interrupt enable bit + 1 + 1 + read-write + + + COCPU_TOUCH_ACTIVE_INT_ENA + TOUCH_ACTIVE_INT interrupt enable bit + 2 + 1 + read-write + + + COCPU_SARADC1_INT_ENA + SARADC1_DONE_INT interrupt enable bit + 3 + 1 + read-write + + + COCPU_SARADC2_INT_ENA + SARADC2_DONE_INT interrupt enable bit + 4 + 1 + read-write + + + COCPU_TSENS_INT_ENA + TSENS_DONE_INT interrupt enable bit + 5 + 1 + read-write + + + COCPU_START_INT_ENA + RISCV_START_INT interrupt enable bit + 6 + 1 + read-write + + + COCPU_SW_INT_ENA + SW_INT interrupt enable bit + 7 + 1 + read-write + + + COCPU_SWD_INT_ENA + SWD_INT interrupt enable bit + 8 + 1 + read-write + + + + + SAR_COCPU_INT_ST + Interrupt status bit of ULP-RISCV + 0x130 + 0x20 + + + COCPU_TOUCH_DONE_INT_ST + TOUCH_DONE_INT interrupt status bit + 0 + 1 + read-only + + + COCPU_TOUCH_INACTIVE_INT_ST + TOUCH_INACTIVE_INT interrupt status bit + 1 + 1 + read-only + + + COCPU_TOUCH_ACTIVE_INT_ST + TOUCH_ACTIVE_INT interrupt status bit + 2 + 1 + read-only + + + COCPU_SARADC1_INT_ST + SARADC1_DONE_INT interrupt status bit + 3 + 1 + read-only + + + COCPU_SARADC2_INT_ST + SARADC2_DONE_INT interrupt status bit + 4 + 1 + read-only + + + COCPU_TSENS_INT_ST + TSENS_DONE_INT interrupt status bit + 5 + 1 + read-only + + + COCPU_START_INT_ST + RISCV_START_INT interrupt status bit + 6 + 1 + read-only + + + COCPU_SW_INT_ST + SW_INT interrupt status bit + 7 + 1 + read-only + + + COCPU_SWD_INT_ST + SWD_INT interrupt status bit + 8 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + Interrupt clear bit of ULP-RISCV + 0x134 + 0x20 + + + COCPU_TOUCH_DONE_INT_CLR + TOUCH_DONE_INT interrupt clear bit + 0 + 1 + write-only + + + COCPU_TOUCH_INACTIVE_INT_CLR + TOUCH_INACTIVE_INT interrupt clear bit + 1 + 1 + write-only + + + COCPU_TOUCH_ACTIVE_INT_CLR + TOUCH_ACTIVE_INT interrupt clear bit + 2 + 1 + write-only + + + COCPU_SARADC1_INT_CLR + SARADC1_DONE_INT interrupt clear bit + 3 + 1 + write-only + + + COCPU_SARADC2_INT_CLR + SARADC2_DONE_INT interrupt clear bit + 4 + 1 + write-only + + + COCPU_TSENS_INT_CLR + TSENS_DONE_INT interrupt clear bit + 5 + 1 + write-only + + + COCPU_START_INT_CLR + RISCV_START_INT interrupt clear bit + 6 + 1 + write-only + + + COCPU_SW_INT_CLR + SW_INT interrupt clear bit + 7 + 1 + write-only + + + COCPU_SWD_INT_CLR + SWD_INT interrupt clear bit + 8 + 1 + write-only + + + + + + + \ No newline at end of file diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2.svd index 42d21bd8e..8342081b5 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s2.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S2 - ESP32-S2 - 8 + ESP32 S-Series + 19 32-bit MCU & 2.4 GHz Wi-Fi - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. Xtensa LX7 r0p0 little false false - 3 + 0 false 32 @@ -53,13 +51,13 @@ 8 0x4 - KEY_%s + KEY[%s] AES key register %s 0x0 0x20 - KEY_0 + KEY Stores AES keys. 0 32 @@ -70,13 +68,13 @@ 4 0x4 - TEXT_IN_%s + TEXT_IN[%s] Source data register %s 0x20 0x20 - TEXT_IN_0 + TEXT_IN Stores the source data when the AES Accelerator operates in the Typical AES working mode. 0 32 @@ -87,13 +85,13 @@ 4 0x4 - TEXT_OUT_%s + TEXT_OUT[%s] Result data register %s 0x30 0x20 - TEXT_OUT_0 + TEXT_OUT Stores the result data when the AES Accelerator operates in the Typical AES working mode. 0 32 @@ -185,7 +183,7 @@ For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. 0x20 - IV_0 + IV This register stores the %sth 32-bit piece of 128-bit initialization vector 0 32 @@ -202,7 +200,7 @@ For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. 0x20 - H_0 + H GCM hash subkey 0 32 @@ -219,7 +217,7 @@ For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. 0x20 - J0_0 + J0 This register stores the %sth 32-bit piece of 128-bit J0 0 32 @@ -236,7 +234,7 @@ For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. 0x20 - T0_0 + T0 This register stores the %sth 32-bit piece of 128-bit T0 0 32 @@ -425,7 +423,7 @@ For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. APB_SARADC - Successive Approximation Register Analog to Digital Converter + SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x3F440000 @@ -1290,9 +1288,54 @@ alternate-channel scan mode. + + BB + BB Peripheral + BB + 0x3F41D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + DEDICATED_GPIO - Dedicated GPIO + DEDICATED_GPIO Peripheral DEDIC_GPIO 0x3F4CF000 @@ -1946,12 +1989,12 @@ alternate-channel scan mode. - 1584 - 0x1 + 396 + 0x4 C_MEM[%s] memory C 0x0 - 0x8 + 0x20 4 @@ -1962,7 +2005,7 @@ alternate-channel scan mode. 0x20 - IV_0 + IV IV block data. 0 32 @@ -1971,20 +2014,20 @@ alternate-channel scan mode. - 512 - 0x1 + 128 + 0x4 X_MEM[%s] memory X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] memory Z 0xA00 - 0x8 + 0x20 SET_START @@ -2095,6 +2138,7 @@ alternate-channel scan mode. Version control register. 0 30 + read-write @@ -2124,7 +2168,7 @@ alternate-channel scan mode. 0x20 - PGM_DATA_0 + PGM_DATA The content of the %sth 32-bit data to be programmed. 0 32 @@ -2141,7 +2185,7 @@ alternate-channel scan mode. 0x20 - PGM_RS_DATA_0 + PGM_RS_DATA The content of the %sth 32-bit RS code to be programmed. 0 32 @@ -2744,7 +2788,7 @@ alternate-channel scan mode. 0x20 - SYS_DATA_PART1_0 + SYS_DATA_PART1 Stores the %sth 32 bits of the first part of system data. 0 32 @@ -2761,7 +2805,7 @@ alternate-channel scan mode. 0x20 - USR_DATA0 + USR_DATA Stores the %sth 32 bits of BLOCK3 (user). 0 32 @@ -2778,7 +2822,7 @@ alternate-channel scan mode. 0x20 - KEY0_DATA0 + KEY0_DATA Stores the %sth 32 bits of KEY0. 0 32 @@ -2795,7 +2839,7 @@ alternate-channel scan mode. 0x20 - KEY1_DATA0 + KEY1_DATA Stores the %sth 32 bits of KEY1. 0 32 @@ -2812,7 +2856,7 @@ alternate-channel scan mode. 0x20 - KEY2_DATA0 + KEY2_DATA Stores the %sth 32 bits of KEY2. 0 32 @@ -2829,7 +2873,7 @@ alternate-channel scan mode. 0x20 - KEY3_DATA0 + KEY3_DATA Stores the %sth 32 bits of KEY3. 0 32 @@ -2846,7 +2890,7 @@ alternate-channel scan mode. 0x20 - KEY4_DATA0 + KEY4_DATA Stores the %sth 32 bits of KEY4. 0 32 @@ -2863,7 +2907,7 @@ alternate-channel scan mode. 0x20 - KEY5_DATA0 + KEY5_DATA Stores the %sth 32 bits of KEY5. 0 32 @@ -2880,7 +2924,7 @@ alternate-channel scan mode. 0x20 - SYS_DATA_PART2_0 + SYS_DATA_PART2 Stores the %sth 32 bits of the 2nd part of system data. 0 32 @@ -6211,6 +6255,14 @@ alternate-channel scan mode. GPIO_NMI 24 + + GPIO_INTR_2 + 25 + + + GPIO_NMI_2 + 26 + BT_SELECT @@ -6459,11 +6511,11 @@ alternate-channel scan mode. 0x20 - DATA_NEXT + IN_DATA1_NEXT GPIO32 ~ 53 input value. Each bit represents a pad input value. 0 22 - read-write + read-only @@ -6656,49 +6708,49 @@ alternate-channel scan mode. 0x20 - PIN_SYNC2_BYPASS + SYNC2_BYPASS For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. 0 2 read-write - PIN_PAD_DRIVER + PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain output.. 2 1 read-write - PIN_SYNC1_BYPASS + SYNC1_BYPASS For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. 3 2 read-write - PIN_INT_TYPE + INT_TYPE Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W) 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. 10 1 read-write - PIN_CONFIG + CONFIG Reserved 11 2 read-write - PIN_INT_ENA + INT_ENA Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled. 13 5 @@ -6861,14 +6913,14 @@ alternate-channel scan mode. 0x0000FF00 - SD0_IN + SD_IN This field is used to configure the duty cycle of sigma delta modulation output. 0 8 read-write - SD0_PRESCALE + SD_PRESCALE This field is used to set a divider value to divide APB clock. 8 8 @@ -7099,14 +7151,12 @@ alternate-channel scan mode. 0x20 - QUREY_CHECK + QUERY_CHECK Hmac error status. 0: hmac key and purpose match. -1: error. - - +1: error. 0 1 read-only @@ -7125,9 +7175,7 @@ alternate-channel scan mode. 1'b0: idle. -1'b1: busy. - - +1'b1: busy. 0 1 read-only @@ -7218,7 +7266,7 @@ alternate-channel scan mode. I2C0 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 0 I2C 0x3F413000 @@ -8306,8 +8354,9 @@ The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interru - 8 + 16 0x4 + 0-15 COMD%s I2C command register %s 0x58 @@ -8315,119 +8364,7 @@ The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interru COMMAND - This is the content of command . It consists of three parts: - -op_code is the command, : RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND_DONE - When command is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD8 - I2C command register 8 - 0x78 - 0x20 - - - COMMAND8 - This is the content of command 8. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND8_DONE - When command 8 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD9 - I2C command register 9 - 0x7C - 0x20 - - - COMMAND9 - This is the content of command 9. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND9_DONE - When command 9 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD10 - I2C command register 10 - 0x80 - 0x20 - - - COMMAND10 - This is the content of command 10. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND10_DONE - When command 10 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD11 - I2C command register 11 - 0x84 - 0x20 - - - COMMAND11 - This is the content of command 11. It consists of three parts: + This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. @@ -8439,120 +8376,8 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc read-write - COMMAND11_DONE - When command 11 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD12 - I2C command register 12 - 0x88 - 0x20 - - - COMMAND12 - This is the content of command 12. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND12_DONE - When command 12 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD13 - I2C command register 13 - 0x8C - 0x20 - - - COMMAND13 - This is the content of command 13. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND13_DONE - When command 13 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD14 - I2C command register 14 - 0x90 - 0x20 - - - COMMAND14 - This is the content of command 14. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND14_DONE - When command 14 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD15 - I2C command register 15 - 0x94 - 0x20 - - - COMMAND15 - This is the content of command 15. It consists of three parts: - -op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. - -byte_num represents the number of bytes that need to be sent or received. - -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND15_DONE - When command 15 is done in I2C Master mode, this bit changes to high level. + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 read-write @@ -8676,7 +8501,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc I2C1 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 1 0x3F427000 I2C_EXT1 @@ -8684,8 +8509,8 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - I2S - I2S (Inter-IC Sound) Controller + I2S0 + I2S (Inter-IC Sound) Controller 0 I2S 0x3F40F000 @@ -8693,6 +8518,14 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x88 registers + + I2S0 + 35 + + + I2S1 + 36 + CONF @@ -10511,15 +10344,119 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - INTERRUPT - Interrupt - INTERRUPT + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + INTERRUPT_CORE0 0x3F4C2000 0x0 0x190 registers + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SLC0 + 11 + + + SLC1 + 12 + + + FROM_CPU_INTR0 + 28 + + + FROM_CPU_INTR1 + 29 + + + FROM_CPU_INTR2 + 30 + + + FROM_CPU_INTR3 + 31 + + + SDIO_HOST + 40 + + + WDT + 59 + + + CACHE_IA + 70 + + + ICACHE_PRELOAD + 87 + + + DCACHE_PRELOAD + 88 + + + CPU_PERI_ERR + 91 + + + APB_PERI_ERR + 92 + + + DCACHE_SYNC + 93 + + + ICACHE_SYNC + 94 + PRO_MAC_INTR_MAP @@ -13473,9 +13410,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO15 - Configuration register for pad GPIO15 - 0x40 + GPIO19 + Configuration register for pin GPIO19 + 0x50 0x20 0x00000B00 @@ -13559,9 +13496,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO16 - Configuration register for pad GPIO16 - 0x44 + GPIO20 + Configuration register for pin GPIO20 + 0x54 0x20 0x00000B00 @@ -13645,9 +13582,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO17 - Configuration register for pad GPIO17 - 0x48 + GPIO21 + Configuration register for pin GPIO21 + 0x58 0x20 0x00000B00 @@ -13731,9 +13668,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO18 - Configuration register for pad GPIO18 - 0x4C + GPIO33 + Configuration register for pin GPIO33 + 0x88 0x20 0x00000B00 @@ -13817,9 +13754,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO19 - Configuration register for pin GPIO19 - 0x50 + GPIO34 + Configuration register for pin GPIO34 + 0x8C 0x20 0x00000B00 @@ -13903,9 +13840,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO20 - Configuration register for pin GPIO20 - 0x54 + GPIO35 + Configuration register for pin GPIO35 + 0x90 0x20 0x00000B00 @@ -13989,9 +13926,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO21 - Configuration register for pin GPIO21 - 0x58 + GPIO36 + Configuration register for pin GPIO36 + 0x94 0x20 0x00000B00 @@ -14075,9 +14012,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO26 - Configuration register for pad GPIO26 - 0x6C + GPIO37 + Configuration register for pin GPIO37 + 0x98 0x20 0x00000B00 @@ -14161,9 +14098,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO27 - Configuration register for pad GPIO27 - 0x70 + GPIO38 + Configuration register for pin GPIO38 + 0x9C 0x20 0x00000B00 @@ -14247,9 +14184,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO28 - Configuration register for pad GPIO28 - 0x74 + GPIO45 + Configuration register for pin GPIO45 + 0xB8 0x20 0x00000B00 @@ -14333,9 +14270,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO29 - Configuration register for pad GPIO29 - 0x78 + GPIO46 + Configuration register for pin GPIO46 + 0xBC 0x20 0x00000B00 @@ -14419,9 +14356,25 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO30 - Configuration register for pad GPIO30 - 0x7C + DATE + Version control register + 0xFC + 0x20 + 0x01907160 + + + VERSION + Version control register + 0 + 28 + read-write + + + + + GPIO15 + Configuration register for pin GPIO15 + 0x40 0x20 0x00000B00 @@ -14505,9 +14458,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO31 - Configuration register for pad GPIO31 - 0x80 + GPIO16 + Configuration register for pin GPIO16 + 0x44 0x20 0x00000B00 @@ -14591,9 +14544,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO32 - Configuration register for pad GPIO32 - 0x84 + GPIO17 + Configuration register for pin GPIO17 + 0x48 0x20 0x00000B00 @@ -14677,9 +14630,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO33 - Configuration register for pin GPIO33 - 0x88 + GPIO18 + Configuration register for pin GPIO18 + 0x4C 0x20 0x00000B00 @@ -14763,9 +14716,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO34 - Configuration register for pin GPIO34 - 0x8C + GPIO26 + Configuration register for pin GPIO26 + 0x6C 0x20 0x00000B00 @@ -14849,9 +14802,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO35 - Configuration register for pin GPIO35 - 0x90 + GPIO27 + Configuration register for pin GPIO27 + 0x70 0x20 0x00000B00 @@ -14935,9 +14888,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO36 - Configuration register for pin GPIO36 - 0x94 + GPIO28 + Configuration register for pin GPIO28 + 0x74 0x20 0x00000B00 @@ -15021,9 +14974,9 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO37 - Configuration register for pin GPIO37 - 0x98 + GPIO29 + Configuration register for pin GPIO29 + 0x78 0x20 0x00000B00 @@ -15107,9 +15060,181 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - GPIO38 - Configuration register for pin GPIO38 - 0x9C + GPIO30 + Configuration register for pin GPIO30 + 0x7C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO31 + Configuration register for pin GPIO31 + 0x80 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO32 + Configuration register for pin GPIO32 + 0x84 0x20 0x00000B00 @@ -15194,7 +15319,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO39 - Configuration register for pad GPIO39 + Configuration register for pin GPIO39 0xA0 0x20 0x00000B00 @@ -15280,7 +15405,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO40 - Configuration register for pad GPIO40 + Configuration register for pin GPIO40 0xA4 0x20 0x00000B00 @@ -15366,7 +15491,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO41 - Configuration register for pad GPIO41 + Configuration register for pin GPIO41 0xA8 0x20 0x00000B00 @@ -15452,7 +15577,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO42 - Configuration register for pad GPIO42 + Configuration register for pin GPIO42 0xAC 0x20 0x00000B00 @@ -15538,7 +15663,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO43 - Configuration register for pad GPIO43 + Configuration register for pin GPIO43 0xB0 0x20 0x00000B00 @@ -15624,7 +15749,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc GPIO44 - Configuration register for pad GPIO44 + Configuration register for pin GPIO44 0xB4 0x20 0x00000B00 @@ -15708,199 +15833,11 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc - - GPIO45 - Configuration register for pin GPIO45 - 0xB8 - 0x20 - 0x00000B00 - - - MCU_OE - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. - 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. - 1 - 1 - read-write - - - MCU_WPD - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. - 2 - 1 - read-write - - - MCU_WPU - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. - 3 - 1 - read-write - - - MCU_IE - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. - 4 - 1 - read-write - - - FUN_WPD - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. - 7 - 1 - read-write - - - FUN_WPU - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. - 8 - 1 - read-write - - - FUN_IE - Input enable of the pin. 1: Input enabled. 0: Input disabled. - 9 - 1 - read-write - - - FUN_DRV - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. - 10 - 2 - read-write - - - MCU_SEL - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. - 12 - 3 - read-write - - - FILTER_EN - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. - 15 - 1 - read-write - - - - - GPIO46 - Configuration register for pin GPIO46 - 0xBC - 0x20 - 0x00000B00 - - - MCU_OE - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. - 0 - 1 - read-write - - - SLP_SEL - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. - 1 - 1 - read-write - - - MCU_WPD - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. - 2 - 1 - read-write - - - MCU_WPU - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. - 3 - 1 - read-write - - - MCU_IE - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. - 4 - 1 - read-write - - - FUN_WPD - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. - 7 - 1 - read-write - - - FUN_WPU - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. - 8 - 1 - read-write - - - FUN_IE - Input enable of the pin. 1: Input enabled. 0: Input disabled. - 9 - 1 - read-write - - - FUN_DRV - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. - 10 - 2 - read-write - - - MCU_SEL - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. - 12 - 3 - read-write - - - FILTER_EN - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. - 15 - 1 - read-write - - - - - DATE - Version control register - 0xFC - 0x20 - 0x01907160 - - - VERSION - Version control register - 0 - 28 - read-write - - - LEDC - LED PWM (Pulse Width Modulation) Controller + LED Control PWM (Pulse Width Modulation) LEDC 0x3F419000 @@ -15930,7 +15867,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x20 - TIMER_SEL_CH0 + TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer 0. @@ -15945,49 +15882,49 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc read-write - SIG_OUT_EN_CH0 + SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write - IDLE_LV_CH0 + IDLE_LV This bit is used to control the output value when channel %s is inactive. 3 1 read-write - PARA_UP_CH0 + PARA_UP This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s. 4 1 write-only - OVF_NUM_CH0 + OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. 5 10 read-write - OVF_CNT_EN_CH0 + OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write - OVF_CNT_RESET_CH0 + OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only - OVF_CNT_RESET_ST_CH0 + OVF_CNT_RESET_ST This is the status bit of LEDC_OVF_CNT_RESET_CH%s. 17 1 @@ -16004,7 +15941,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x20 - HPOINT_CH0 + HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 @@ -16021,7 +15958,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x20 - DUTY_CH0 + DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. 0 19 @@ -16039,35 +15976,35 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x40000000 - DUTY_SCALE_CH0 + DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write - DUTY_CYCLE_CH0 + DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write - DUTY_NUM_CH0 + DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write - DUTY_INC_CH0 + DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease. 30 1 read-write - DUTY_START_CH0 + DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 @@ -16084,7 +16021,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x20 - DUTY_R_CH0 + DUTY_R This register stores the current duty of output signal on channel %s. 0 19 @@ -16102,42 +16039,42 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x00800000 - TIMER0_DUTY_RES + DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write - CLK_DIV_TIMER0 + CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. 4 18 read-write - TIMER0_PAUSE + PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write - TIMER0_RST + RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write - TICK_SEL_TIMER0 + TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK. 24 1 read-write - TIMER0_PARA_UP + PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 @@ -16154,7 +16091,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x20 - TIMER0_CNT + CNT This register stores the current counter value of timer %s. 0 14 @@ -16819,7 +16756,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x00003C10 - FILTER_THRES_U0 + FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. 0 @@ -16827,49 +16764,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - FILTER_EN_U0 + FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write - THR_ZERO_EN_U0 + THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write - THR_H_LIM_EN_U0 + THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. 12 1 read-write - THR_L_LIM_EN_U0 + THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. 13 1 read-write - THR_THRES0_EN_U0 + THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write - THR_THRES1_EN_U0 + THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write - CH0_NEG_MODE_U0 + CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 16 @@ -16877,7 +16814,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_POS_MODE_U0 + CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 18 @@ -16885,7 +16822,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_HCTRL_MODE_U0 + CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 20 @@ -16893,7 +16830,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_LCTRL_MODE_U0 + CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 22 @@ -16901,7 +16838,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_NEG_MODE_U0 + CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 24 @@ -16909,7 +16846,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_POS_MODE_U0 + CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 26 @@ -16917,7 +16854,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_HCTRL_MODE_U0 + CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 28 @@ -16925,7 +16862,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_LCTRL_MODE_U0 + CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 30 @@ -16943,14 +16880,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THRES0_U0 + CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write - CNT_THRES1_U0 + CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 @@ -16967,14 +16904,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_H_LIM_U0 + CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. 0 16 read-write - CNT_L_LIM_U0 + CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. 16 16 @@ -16991,7 +16928,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - PULSE_CNT_U0 + CNT This register stores the current pulse count value for unit %s. 0 16 @@ -17006,28 +16943,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -17042,28 +16979,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -17078,28 +17015,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -17114,28 +17051,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -17152,42 +17089,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_ZERO_MODE_U0 + ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only - CNT_THR_THRES1_LAT_U0 + THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others. 2 1 read-only - CNT_THR_THRES0_LAT_U0 + THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others. 3 1 read-only - CNT_THR_L_LIM_LAT_U0 + L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others. 4 1 read-only - CNT_THR_H_LIM_LAT_U0 + H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others. 5 1 read-only - CNT_THR_ZERO_LAT_U0 + ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others. 6 1 @@ -17203,7 +17140,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000055 - PULSE_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 @@ -17217,7 +17154,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit 2's counter. 2 1 @@ -17231,7 +17168,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit 4's counter. 4 1 @@ -17245,7 +17182,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit 6's counter. 6 1 @@ -17295,6 +17232,38 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x10C registers + + PMS_PRO_IRAM0_ILG + 75 + + + PMS_PRO_DRAM0_ILG + 76 + + + PMS_PRO_DPORT_ILG + 77 + + + PMS_PRO_AHB_ILG + 78 + + + PMS_PRO_CACHE_ILG + 79 + + + PMS_DMA_APB_I_ILG + 80 + + + PMS_DMA_RX_I_ILG + 81 + + + PMS_DMA_TX_I_ILG + 82 + SDIO_0 @@ -19140,7 +19109,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CLOCK_GATE_REG + CLOCK_GATE Clock gate register of permission control. 0x104 0x20 @@ -19175,7 +19144,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RMT - Remote Control Peripheral + Remote Control RMT 0x3F416000 @@ -19197,7 +19166,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CH_DATA + DATA The read and write data register for CHANNEL%s by apb fifo access. 0 32 @@ -19477,7 +19446,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_TX_END_INT_RAW + CH%s_TX_END The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 @@ -19487,7 +19456,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_RX_END_INT_RAW + CH%s_RX_END The interrupt raw bit for CHANNEL%s. Triggered when reception done. 1 1 @@ -19497,7 +19466,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_ERR_INT_RAW + CH%s_ERR The interrupt raw bit for CHANNEL%s. Triggered when error occurs. 2 1 @@ -19507,7 +19476,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 12 1 @@ -19517,7 +19486,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 16 1 @@ -19535,7 +19504,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_TX_END_INT_ST + CH%s_TX_END The masked interrupt status bit for CH%s_TX_END_INT. 0 1 @@ -19545,7 +19514,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_RX_END_INT_ST + CH%s_RX_END The masked interrupt status bit for CH%s_RX_END_INT. 1 1 @@ -19555,7 +19524,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_ERR_INT_ST + CH%s_ERR The masked interrupt status bit for CH%s_ERR_INT. 2 1 @@ -19565,7 +19534,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 12 1 @@ -19575,7 +19544,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ST + CH%s_TX_LOOP The masked interrupt status bit for CH%s_TX_LOOP_INT. 16 1 @@ -19593,7 +19562,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_TX_END_INT_ENA + CH%s_TX_END The interrupt enabled bit for CH%s_TX_END_INT. 0 1 @@ -19603,7 +19572,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_RX_END_INT_ENA + CH%s_RX_END The interrupt enabled bit for CH%s_RX_END_INT. 1 1 @@ -19613,7 +19582,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_ERR_INT_ENA + CH%s_ERR The interrupt enabled bit for CH%s_ERR_INT. 2 1 @@ -19623,7 +19592,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT The interrupt enabled bit for CH%s_TX_THR_EVENT_INT. 12 1 @@ -19633,7 +19602,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ENA + CH%s_TX_LOOP The interrupt enabled bit for CH%s_TX_LOOP_INT. 16 1 @@ -19651,7 +19620,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_TX_END_INT_CLR + CH%s_TX_END Set this bit to clear the CH%s_TX_END_INT interrupt. 0 1 @@ -19661,7 +19630,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_RX_END_INT_CLR + CH%s_RX_END Set this bit to clear the CH%s_RX_END_INT interrupt. 1 1 @@ -19671,7 +19640,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x3 0-3 - CH%s_ERR_INT_CLR + CH%s_ERR Set this bit to clear the CH%s_ERR_INT interrupt. 2 1 @@ -19681,7 +19650,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt. 12 1 @@ -19691,7 +19660,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_CLR + CH%s_TX_LOOP Set this bit to clear the CH%s_TX_LOOP_INT interrupt. 16 1 @@ -19937,7 +19906,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RNG - Hardware random number generator + Hardware Random Number Generator RNG 0x60035000 @@ -19951,6 +19920,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. Random number data 0x110 0x20 + read-only @@ -20167,11 +20137,47 @@ Any pulses with width less than this will be ignored when the filter is enabled. + + 128 + 0x4 + M_MEM[%s] + Represents M + 0x0 + 0x20 + write-only + + + 128 + 0x4 + Z_MEM[%s] + Represents Z + 0x200 + 0x20 + read-write + + + 128 + 0x4 + Y_MEM[%s] + Represents Y + 0x400 + 0x20 + write-only + + + 128 + 0x4 + X_MEM[%s] + Represents X + 0x600 + 0x20 + write-only + - RTCIO - Peripheral RTCIO + RTC_IO + Low-power Input/Output RTCIO 0x3F408400 @@ -20256,13 +20262,13 @@ Any pulses with width less than this will be ignored when the filter is enabled. - RTC_GPIO_ENABLE_W1TC + ENABLE_W1TC RTC GPIO output enable bit clear register 0x14 0x20 - REG_RTCIO_REG_GPIO_ENABLE_W1TC + ENABLE_W1TC GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. 10 22 @@ -20333,27 +20339,27 @@ Any pulses with width less than this will be ignored when the filter is enabled. 22 0x4 - RTC_GPIO_PIN%s + PIN%s RTC configuration for pin %s 0x28 0x20 - GPIO_PIN0_PAD_DRIVER + PAD_DRIVER Pad driver selection. 0: normal output. 1: open drain. 2 1 read-write - GPIO_PIN0_INT_TYPE + GPIO_PIN_INT_TYPE GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. 7 3 read-write - GPIO_PIN0_WAKEUP_ENABLE + GPIO_PIN_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. 10 1 @@ -20415,91 +20421,91 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x52000000 - TOUCH_PAD0_FUN_IE + FUN_IE Input enable in normal execution. 13 1 read-write - TOUCH_PAD0_SLP_OE + SLP_OE Output enable in sleep mode. 14 1 read-write - TOUCH_PAD0_SLP_IE + SLP_IE Input enable in sleep mode. 15 1 read-write - TOUCH_PAD0_SLP_SEL + SLP_SEL 0: no sleep mode. 1: enable sleep mode. 16 1 read-write - TOUCH_PAD0_FUN_SEL + FUN_SEL Function selection. 17 2 read-write - TOUCH_PAD0_MUX_SEL + MUX_SEL Connect the RTC pad input to digital pad input. 0 is available. 19 1 read-write - TOUCH_PAD0_XPD + XPD Touch sensor power on. 20 1 read-write - TOUCH_PAD0_TIE_OPT + TIE_OPT The tie option of touch sensor. 0: tie low. 1: tie high. 21 1 read-write - TOUCH_PAD0_START + START Start touch sensor. 22 1 read-write - TOUCH_PAD0_DAC + DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. 23 3 read-write - TOUCH_PAD0_RUE + RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write - TOUCH_PAD0_RDE + RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write - TOUCH_PAD0_DRV + DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 @@ -21152,7 +21158,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_CNTL - Real Time Controller + Real-Time Clock Control RTC_CNTL 0x3F408000 @@ -25364,7 +25370,7 @@ proximity mode. Range: 0 – 255. RTC_I2C - Peripheral RTC_I2C + Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x3F408C00 @@ -25962,14 +25968,17 @@ clear bit - CMD0 - RTC I2C Command 0 + 16 + 0x4 + 0-15 + CMD%s + RTC I2C Command %s 0x38 0x20 0x00000903 - COMMAND0 + COMMAND Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller 0 @@ -25977,7 +25986,7 @@ I2C_COMD0_REG in Chapter I²C Controller read-write - COMMAND0_DONE + COMMAND_DONE When command 0 is done, this bit changes to 1. 31 1 @@ -25985,364 +25994,6 @@ I2C_COMD0_REG in Chapter I²C Controller - - CMD1 - RTC I2C Command 1 - 0x3C - 0x20 - 0x00001901 - - - COMMAND1 - Content of command 1. For more information, please refer to the register -I2C_COMD1_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND1_DONE - When command 1 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD2 - RTC I2C Command 2 - 0x40 - 0x20 - 0x00000902 - - - COMMAND2 - Content of command 2. For more information, please refer to the register -I2C_COMD2_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND2_DONE - When command 2 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD3 - RTC I2C Command 3 - 0x44 - 0x20 - 0x00000101 - - - COMMAND3 - Content of command 3. For more information, please refer to the register -I2C_COMD3_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND3_DONE - When command 3 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD4 - RTC I2C Command 4 - 0x48 - 0x20 - 0x00000901 - - - COMMAND4 - Content of command 4. For more information, please refer to the register -I2C_COMD4_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND4_DONE - When command 4 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD5 - RTC I2C Command 5 - 0x4C - 0x20 - 0x00001701 - - - COMMAND5 - Content of command 5. For more information, please refer to the register -I2C_COMD5_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND5_DONE - When command 5 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD6 - RTC I2C Command 6 - 0x50 - 0x20 - 0x00001901 - - - COMMAND6 - Content of command 6. For more information, please refer to the register -I2C_COMD6_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND6_DONE - When command 6 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD7 - RTC I2C Command 7 - 0x54 - 0x20 - 0x00000904 - - - COMMAND7 - Content of command 7. For more information, please refer to the register -I2C_COMD7_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND7_DONE - When command 7 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD8 - RTC I2C Command 8 - 0x58 - 0x20 - 0x00001901 - - - COMMAND8 - Content of command 8. For more information, please refer to the register -I2C_COMD8_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND8_DONE - When command 8 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD9 - RTC I2C Command 9 - 0x5C - 0x20 - 0x00000903 - - - COMMAND9 - Content of command 9. For more information, please refer to the register -I2C_COMD9_REG in Chapter I²C Controller - 0 - 14 - read-write - - - COMMAND9_DONE - When command 9 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD10 - RTC I2C Command 10 - 0x60 - 0x20 - 0x00000101 - - - COMMAND10 - Content of command 10. For more information, please refer to the register -I2C_COMD10_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND10_DONE - When command 10 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD11 - RTC I2C Command 11 - 0x64 - 0x20 - 0x00000901 - - - COMMAND11 - Content of command 11. For more information, please refer to the register -I2C_COMD11_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND11_DONE - When command 11 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD12 - RTC I2C Command 12 - 0x68 - 0x20 - 0x00001701 - - - COMMAND12 - Content of command 12. For more information, please refer to the register -I2C_COMD12_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND12_DONE - When command 12 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD13 - RTC I2C Command 13 - 0x6C - 0x20 - 0x00001901 - - - COMMAND13 - Content of command 13. For more information, please refer to the register -I2C_COMD13_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND13_DONE - When command 13 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD14 - RTC I2C Command 14 - 0x70 - 0x20 - - - COMMAND14 - Content of command 14. For more information, please refer to the register -I2C_COMD14_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND14_DONE - When command 14 is done, this bit changes to 1. - 31 - 1 - read-only - - - - - CMD15 - RTC I2C Command 15 - 0x74 - 0x20 - - - COMMAND15 - Content of command 15. For more information, please refer to the register -I2C_COMD15_REG in Chapter I²C Controller. - 0 - 14 - read-write - - - COMMAND15_DONE - When command 15 is done, this bit changes to 1. - 31 - 1 - read-only - - - DATE Version control register @@ -26363,7 +26014,7 @@ I2C_COMD15_REG in Chapter I²C Controller. SENS - Peripheral SENS + SENS Peripheral SENS 0x3F408800 @@ -28534,7 +28185,7 @@ I2C_COMD15_REG in Chapter I²C Controller. - CONTINUE_OP + CONTINUE Continues SHA operation (only effective in Typical SHA mode) 0x14 0x20 @@ -28644,13 +28295,13 @@ I2C_COMD15_REG in Chapter I²C Controller. 16 0x4 - H_%s + H_MEM%s Hash value 0x40 0x20 - H_0 + H Stores the %sth 32-bit piece of the Hash value. 0 32 @@ -28661,13 +28312,13 @@ I2C_COMD15_REG in Chapter I²C Controller. 32 0x4 - M_%s + M_MEM%s Message 0x80 0x20 - M_0 + M Stores the %sth 32-bit piece of the message. 0 32 @@ -28679,7 +28330,7 @@ I2C_COMD15_REG in Chapter I²C Controller. SPI0 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 0 SPI 0x3F403000 @@ -28687,6 +28338,10 @@ I2C_COMD15_REG in Chapter I²C Controller. 0x108 registers + + SPI0_REJECT_CACHE + 83 + CMD @@ -31532,7 +31187,7 @@ I2C_COMD15_REG in Chapter I²C Controller. SPI1 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 1 0x3F402000 SPI1 @@ -31541,7 +31196,7 @@ I2C_COMD15_REG in Chapter I²C Controller. SPI2 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 2 0x3F424000 SPI2 @@ -31554,7 +31209,7 @@ I2C_COMD15_REG in Chapter I²C Controller. SPI3 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 3 0x3F425000 SPI3 @@ -31567,803 +31222,1228 @@ I2C_COMD15_REG in Chapter I²C Controller. SPI4 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 4 0x3F437000 + + SPI4_DMA + 85 + + + SPI4 + 86 + - SYSTEM - System - SYSTEM - 0x3F4C0000 + SYSCON + SYSCON Peripheral + SYSCON + 0x3F426000 0x0 - 0x94 + 0xA0 registers - ROM_CTRL_0 - System ROM configuration register 0 + SYSCLK_CONF 0x0 0x20 - 0x00000003 - ROM_FO - This field is used to force on clock gate of internal ROM. - 0 - 2 + CLK_320M_EN + 10 + 1 + read-write + + + CLK_EN + 11 + 1 + read-write + + + RST_TICK_CNT + 12 + 1 read-write - ROM_CTRL_1 - System ROM configuration register 1 + TICK_CONF 0x4 0x20 - 0x0000000C + 0x00010727 - ROM_FORCE_PD - This field is used to power down internal ROM. + XTAL_TICK_NUM 0 - 2 + 8 read-write - ROM_FORCE_PU - This field is used to power up internal ROM. - 2 - 2 + CK8M_TICK_NUM + 8 + 8 + read-write + + + TICK_ENABLE + 16 + 1 read-write - SRAM_CTRL_0 - System SRAM configuration register 0 + CLK_OUT_EN 0x8 0x20 - 0x003FFFFF + 0x000007FF - SRAM_FO - This field is used to force on clock gate of internal SRAM. + CLK20_OEN 0 - 22 + 1 + read-write + + + CLK22_OEN + 1 + 1 + read-write + + + CLK44_OEN + 2 + 1 + read-write + + + CLK_BB_OEN + 3 + 1 + read-write + + + CLK80_OEN + 4 + 1 + read-write + + + CLK160_OEN + 5 + 1 + read-write + + + CLK_320M_OEN + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + 8 + 1 + read-write + + + CLK40X_BB_OEN + 9 + 1 + read-write + + + CLK_XTAL_OEN + 10 + 1 read-write - SRAM_CTRL_1 - System SRAM configuration register 1 + HOST_INF_SEL 0xC 0x20 - SRAM_FORCE_PD - This field is used to power down internal SRAM. + PERI_IO_SWAP 0 - 22 + 8 read-write - CPU_PERI_CLK_EN - CPU peripheral clock enable register + EXT_MEM_PMS_LOCK 0x10 0x20 - CLK_EN_DEDICATED_GPIO - Set this bit to enable clock of DEDICATED GPIO module. - 7 + EXT_MEM_PMS_LOCK + 0 1 read-write - CPU_PERI_RST_EN - CPU peripheral reset register + FLASH_ACE0_ATTR 0x14 0x20 - 0x00000080 + 0x00000007 - RST_EN_DEDICATED_GPIO - Set this bit to reset DEDICATED GPIO module. - 7 - 1 + FLASH_ACE0_ATTR + 0 + 3 read-write - CPU_PER_CONF - CPU peripheral clock configuration register + FLASH_ACE1_ATTR 0x18 0x20 - 0x0000000C + 0x00000007 - CPUPERIOD_SEL - This field is used to select the clock frequency of CPU or CPU period. + FLASH_ACE1_ATTR 0 - 2 - read-write - - - PLL_FREQ_SEL - This field is used to select the PLL clock frequency based on CPU period. - 2 - 1 - read-write - - - CPU_WAIT_MODE_FORCE_ON - Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction. - 3 - 1 - read-write - - - CPU_WAITI_DELAY_NUM - Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction. - 4 - 4 + 3 read-write - JTAG_CTRL_0 - JTAG configuration register 0 + FLASH_ACE2_ATTR 0x1C 0x20 + 0x00000007 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 - Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + FLASH_ACE2_ATTR 0 - 32 - write-only + 3 + read-write - JTAG_CTRL_1 - JTAG configuration register 1 + FLASH_ACE3_ATTR 0x20 0x20 + 0x00000007 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 - Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + FLASH_ACE3_ATTR 0 - 32 - write-only + 3 + read-write - JTAG_CTRL_2 - JTAG configuration register 2 + FLASH_ACE0_ADDR 0x24 0x20 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 - Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + S 0 32 - write-only + read-write - JTAG_CTRL_3 - JTAG configuration register 3 + FLASH_ACE1_ADDR 0x28 0x20 + 0x10000000 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 - Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + S 0 32 - write-only + read-write - JTAG_CTRL_4 - JTAG configuration register 4 + FLASH_ACE2_ADDR 0x2C 0x20 + 0x20000000 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 - Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + S 0 32 - write-only + read-write - JTAG_CTRL_5 - JTAG configuration register 5 + FLASH_ACE3_ADDR 0x30 0x20 + 0x30000000 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 - Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + S 0 32 - write-only + read-write - JTAG_CTRL_6 - JTAG configuration register 6 + FLASH_ACE0_SIZE 0x34 0x20 + 0x00001000 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 - Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + FLASH_ACE0_SIZE 0 - 32 - write-only + 16 + read-write - JTAG_CTRL_7 - JTAG configuration register 7 + FLASH_ACE1_SIZE 0x38 0x20 + 0x00001000 - CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 - Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG. + FLASH_ACE1_SIZE 0 - 32 - write-only + 16 + read-write - MEM_PD_MASK - Memory power-related controlling register (under low-sleep) + FLASH_ACE2_SIZE 0x3C 0x20 - 0x00000001 + 0x00001000 - LSLP_MEM_PD_MASK - Set this bit to allow the memory to work as usual when the chip enters the light-sleep state. + FLASH_ACE2_SIZE 0 - 1 + 16 read-write - PERIP_CLK_EN0 - System peripheral clock (for hardware accelerators) enable register + FLASH_ACE3_SIZE 0x40 0x20 - 0xF9C1E06F + 0x00001000 - TIMERS_CLK_EN - Set this bit to enable clock of timers. + FLASH_ACE3_SIZE 0 - 1 + 16 read-write + + + + SRAM_ACE0_ATTR + 0x44 + 0x20 + 0x00000007 + - SPI01_CLK_EN - Set this bit to enable clock of SPI0 and SPI1. - 1 - 1 + SRAM_ACE0_ATTR + 0 + 3 read-write + + + + SRAM_ACE1_ATTR + 0x48 + 0x20 + 0x00000007 + - UART_CLK_EN - Set this bit to enable clock of UART0. - 2 - 1 + SRAM_ACE1_ATTR + 0 + 3 read-write + + + + SRAM_ACE2_ATTR + 0x4C + 0x20 + 0x00000007 + - WDG_CLK_EN - Set this bit to enable clock of WDG. - 3 - 1 + SRAM_ACE2_ATTR + 0 + 3 read-write + + + + SRAM_ACE3_ATTR + 0x50 + 0x20 + 0x00000007 + - I2S0_CLK_EN - Set this bit to enable clock of I2S0. - 4 - 1 + SRAM_ACE3_ATTR + 0 + 3 read-write + + + + SRAM_ACE0_ADDR + 0x54 + 0x20 + - UART1_CLK_EN - Set this bit to enable clock of UART1. - 5 - 1 + S + 0 + 32 read-write + + + + SRAM_ACE1_ADDR + 0x58 + 0x20 + 0x10000000 + - SPI2_CLK_EN - Set this bit to enable clock of SPI2. - 6 - 1 + S + 0 + 32 read-write + + + + SRAM_ACE2_ADDR + 0x5C + 0x20 + 0x20000000 + - I2C_EXT0_CLK_EN - Set this bit to enable clock of I2C EXT0. - 7 - 1 + S + 0 + 32 read-write + + + + SRAM_ACE3_ADDR + 0x60 + 0x20 + 0x30000000 + - UHCI0_CLK_EN - Set this bit to enable clock of UHCI0. - 8 - 1 + S + 0 + 32 read-write + + + + SRAM_ACE0_SIZE + 0x64 + 0x20 + 0x00001000 + - RMT_CLK_EN - Set this bit to enable clock of remote controller. - 9 - 1 + SRAM_ACE0_SIZE + 0 + 16 read-write + + + + SRAM_ACE1_SIZE + 0x68 + 0x20 + 0x00001000 + - PCNT_CLK_EN - Set this bit to enable clock of pulse count. - 10 - 1 + SRAM_ACE1_SIZE + 0 + 16 read-write + + + + SRAM_ACE2_SIZE + 0x6C + 0x20 + 0x00001000 + - LEDC_CLK_EN - Set this bit to enable clock of LED PWM. - 11 - 1 + SRAM_ACE2_SIZE + 0 + 16 read-write + + + + SRAM_ACE3_SIZE + 0x70 + 0x20 + 0x00001000 + - UHCI1_CLK_EN - Set this bit to enable clock of UHCI1. - 12 - 1 + SRAM_ACE3_SIZE + 0 + 16 read-write + + + + SPI_MEM_PMS_CTRL + 0x74 + 0x20 + - TIMERGROUP_CLK_EN - Set this bit to enable clock of timer group0. - 13 + SPI_MEM_REJECT_INT + 0 1 - read-write + read-only - EFUSE_CLK_EN - Set this bit to enable clock of eFuse. - 14 + SPI_MEM_REJECT_CLR + 1 1 - read-write + write-only - TIMERGROUP1_CLK_EN - Set this bit to enable clock of timer group1. - 15 - 1 - read-write + SPI_MEM_REJECT_CDE + 2 + 5 + read-only + + + + SPI_MEM_REJECT_ADDR + 0x78 + 0x20 + - SPI3_CLK_EN - Set this bit to enable clock of SPI3. - 16 - 1 - read-write + SPI_MEM_REJECT_ADDR + 0 + 32 + read-only + + + + SDIO_CTRL + 0x7C + 0x20 + - PWM0_CLK_EN - Set this bit to enable clock of PWM0. - 17 + SDIO_WIN_ACCESS_EN + 0 1 read-write + + + + REDCY_SIG0 + 0x80 + 0x20 + - I2C_EXT1_CLK_EN - Set this bit to enable clock of I2C EXT1. - 18 - 1 + REDCY_SIG0 + 0 + 31 read-write - CAN_CLK_EN - Set this bit to enable clock of CAN. - 19 + REDCY_ANDOR + 31 1 - read-write + read-only + + + + REDCY_SIG1 + 0x84 + 0x20 + - PWM1_CLK_EN - Set this bit to enable clock of PWM1. - 20 - 1 + REDCY_SIG1 + 0 + 31 read-write - I2S1_CLK_EN - Set this bit to enable clock of I2S1. - 21 + REDCY_NANDOR + 31 1 - read-write + read-only + + + + WIFI_BB_CFG + 0x88 + 0x20 + - SPI2_DMA_CLK_EN - Set this bit to enable clock of SPI2 DMA. - 22 - 1 + WIFI_BB_CFG + 0 + 32 read-write + + + + WIFI_BB_CFG_2 + 0x8C + 0x20 + - USB_CLK_EN - Set this bit to enable clock of USB. - 23 - 1 + WIFI_BB_CFG_2 + 0 + 32 read-write + + + + WIFI_CLK_EN + 0x90 + 0x20 + 0xFFFCE030 + - UART_MEM_CLK_EN - Set this bit to enable clock of UART memory. - 24 - 1 + WIFI_CLK_EN + 0 + 32 read-write - - PWM2_CLK_EN - Set this bit to enable clock of PWM2. - 25 - 1 + + + + WIFI_RST_EN + 0x94 + 0x20 + 0xFFFCE030 + + + WIFI_RST + 0 + 32 read-write + + + + FRONT_END_MEM_PD + 0x98 + 0x20 + 0x00000015 + - PWM3_CLK_EN - Set this bit to enable clock of PWM3. - 26 + AGC_MEM_FORCE_PU + 0 1 read-write - SPI3_DMA_CLK_EN - Set this bit to enable clock of SPI3 DMA. - 27 + AGC_MEM_FORCE_PD + 1 1 read-write - APB_SARADC_CLK_EN - Set this bit to enable clock of SAR ADC. - 28 + PBUS_MEM_FORCE_PU + 2 1 read-write - SYSTIMER_CLK_EN - Set this bit to enable clock of system timer. - 29 + PBUS_MEM_FORCE_PD + 3 1 read-write - ADC2_ARB_CLK_EN - Set this bit to enable clock of aribiter of ADC2. - 30 + DC_MEM_FORCE_PU + 4 1 read-write - SPI4_CLK_EN - Set this bit to enable clock of SPI4. - 31 + DC_MEM_FORCE_PD + 5 1 read-write - PERIP_CLK_EN1 - System peripheral clock (for hardware accelerators) enable register 1 - 0x44 + DATE + 0x3FC 0x20 + 0x01907010 - CRYPTO_AES_CLK_EN - Set this bit to enable clock of cryptography AES. - 1 - 1 + DATE + 0 + 32 + read-write + + + + + + + SYSTEM + System Configuration Registers + SYSTEM + 0x3F4C0000 + + 0x0 + 0x94 + registers + + + + ROM_CTRL_0 + System ROM configuration register 0 + 0x0 + 0x20 + 0x00000003 + + + ROM_FO + This field is used to force on clock gate of internal ROM. + 0 + 2 read-write + + + + ROM_CTRL_1 + System ROM configuration register 1 + 0x4 + 0x20 + 0x0000000C + - CRYPTO_SHA_CLK_EN - Set this bit to enable clock of cryptography SHA. + ROM_FORCE_PD + This field is used to power down internal ROM. + 0 + 2 + read-write + + + ROM_FORCE_PU + This field is used to power up internal ROM. 2 + 2 + read-write + + + + + SRAM_CTRL_0 + System SRAM configuration register 0 + 0x8 + 0x20 + 0x003FFFFF + + + SRAM_FO + This field is used to force on clock gate of internal SRAM. + 0 + 22 + read-write + + + + + SRAM_CTRL_1 + System SRAM configuration register 1 + 0xC + 0x20 + + + SRAM_FORCE_PD + This field is used to power down internal SRAM. + 0 + 22 + read-write + + + + + CPU_PERI_CLK_EN + CPU peripheral clock enable register + 0x10 + 0x20 + + + CLK_EN_DEDICATED_GPIO + Set this bit to enable clock of DEDICATED GPIO module. + 7 1 read-write + + + + CPU_PERI_RST_EN + CPU peripheral reset register + 0x14 + 0x20 + 0x00000080 + - CRYPTO_RSA_CLK_EN - Set this bit to enable clock of cryptography RSA. - 3 + RST_EN_DEDICATED_GPIO + Set this bit to reset DEDICATED GPIO module. + 7 1 read-write + + + + CPU_PER_CONF + CPU peripheral clock configuration register + 0x18 + 0x20 + 0x0000000C + - CRYPTO_DS_CLK_EN - Set this bit to enable clock of cryptography Digital Signature. - 4 + CPUPERIOD_SEL + This field is used to select the clock frequency of CPU or CPU period. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field is used to select the PLL clock frequency based on CPU period. + 2 1 read-write - CRYPTO_HMAC_CLK_EN - Set this bit to enable clock of cryptography HMAC. - 5 + CPU_WAIT_MODE_FORCE_ON + Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction. + 3 1 read-write - CRYPTO_DMA_CLK_EN - Set this bit to enable clock of cryptography DMA. - 6 + CPU_WAITI_DELAY_NUM + Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction. + 4 + 4 + read-write + + + + + JTAG_CTRL_0 + JTAG configuration register 0 + 0x1C + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 + Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_1 + JTAG configuration register 1 + 0x20 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 + Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_2 + JTAG configuration register 2 + 0x24 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 + Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_3 + JTAG configuration register 3 + 0x28 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 + Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_4 + JTAG configuration register 4 + 0x2C + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 + Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_5 + JTAG configuration register 5 + 0x30 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 + Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_6 + JTAG configuration register 6 + 0x34 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 + Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_7 + JTAG configuration register 7 + 0x38 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 + Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + MEM_PD_MASK + Memory power-related controlling register (under low-sleep) + 0x3C + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set this bit to allow the memory to work as usual when the chip enters the light-sleep state. + 0 1 read-write - PERIP_RST_EN0 - System peripheral (hardware accelerators) reset register 0 - 0x48 + PERIP_CLK_EN0 + System peripheral clock (for hardware accelerators) enable register + 0x40 0x20 + 0xF9C1E06F - TIMERS_RST - Set this bit to reset timers. + TIMERS_CLK_EN + Set this bit to enable clock of timers. 0 1 read-write - SPI01_RST - Set this bit to reset SPI0 and SPI1. + SPI01_CLK_EN + Set this bit to enable clock of SPI0 and SPI1. 1 1 read-write - UART_RST - Set this bit to reset UART0. + UART_CLK_EN + Set this bit to enable clock of UART0. 2 1 read-write - WDG_RST - Set this bit to reset WDG. + WDG_CLK_EN + Set this bit to enable clock of WDG. 3 1 read-write - I2S0_RST - Set this bit to reset I2S0. + I2S0_CLK_EN + Set this bit to enable clock of I2S0. 4 1 read-write - UART1_RST - Set this bit to reset UART1. + UART1_CLK_EN + Set this bit to enable clock of UART1. 5 1 read-write - SPI2_RST - Set this bit to reset SPI2. + SPI2_CLK_EN + Set this bit to enable clock of SPI2. 6 1 read-write - I2C_EXT0_RST - Set this bit to reset I2C EXT0. + I2C_EXT0_CLK_EN + Set this bit to enable clock of I2C EXT0. 7 1 read-write - UHCI0_RST - Set this bit to reset UHCI0. + UHCI0_CLK_EN + Set this bit to enable clock of UHCI0. 8 1 read-write - RMT_RST - Set this bit to reset remote controller. + RMT_CLK_EN + Set this bit to enable clock of remote controller. 9 1 read-write - PCNT_RST - Set this bit to reset pulse count. + PCNT_CLK_EN + Set this bit to enable clock of pulse count. 10 1 read-write - LEDC_RST - Set this bit to reset LED PWM. + LEDC_CLK_EN + Set this bit to enable clock of LED PWM. 11 1 read-write - UHCI1_RST - Set this bit to reset UHCI1. + UHCI1_CLK_EN + Set this bit to enable clock of UHCI1. 12 1 read-write - TIMERGROUP_RST - Set this bit to reset timer group0. + TIMERGROUP_CLK_EN + Set this bit to enable clock of timer group0. 13 1 read-write - EFUSE_RST - Set this bit to reset eFuse. + EFUSE_CLK_EN + Set this bit to enable clock of eFuse. 14 1 read-write - TIMERGROUP1_RST - Set this bit to reset timer group1. + TIMERGROUP1_CLK_EN + Set this bit to enable clock of timer group1. 15 1 read-write - SPI3_RST - Set this bit to reset SPI3. + SPI3_CLK_EN + Set this bit to enable clock of SPI3. 16 1 read-write - PWM0_RST - Set this bit to reset PWM0. + PWM0_CLK_EN + Set this bit to enable clock of PWM0. 17 1 read-write - I2C_EXT1_RST - Set this bit to reset I2C EXT1. + I2C_EXT1_CLK_EN + Set this bit to enable clock of I2C EXT1. 18 1 read-write - CAN_RST - Set this bit to reset CAN. + TWAI_CLK_EN + Set this bit to enable clock of CAN. 19 1 read-write - PWM1_RST - Set this bit to reset PWM1. + PWM1_CLK_EN + Set this bit to enable clock of PWM1. 20 1 read-write - I2S1_RST - Set this bit to reset I2S1. + I2S1_CLK_EN + Set this bit to enable clock of I2S1. 21 1 read-write - SPI2_DMA_RST - Set this bit to reset SPI2 DMA. + SPI2_DMA_CLK_EN + Set this bit to enable clock of SPI2 DMA. 22 1 read-write - USB_RST - Set this bit to reset USB. + USB_CLK_EN + Set this bit to enable clock of USB. 23 1 read-write - UART_MEM_RST - Set this bit to reset UART memory. + UART_MEM_CLK_EN + Set this bit to enable clock of UART memory. 24 1 read-write - PWM2_RST - Set this bit to reset PWM2. + PWM2_CLK_EN + Set this bit to enable clock of PWM2. 25 1 read-write - PWM3_RST - Set this bit to reset PWM3. + PWM3_CLK_EN + Set this bit to enable clock of PWM3. 26 1 read-write - SPI3_DMA_RST - Set this bit to reset SPI3 DMA. + SPI3_DMA_CLK_EN + Set this bit to enable clock of SPI3 DMA. 27 1 read-write - APB_SARADC_RST - Set this bit to reset SAR ADC. + APB_SARADC_CLK_EN + Set this bit to enable clock of SAR ADC. 28 1 read-write - SYSTIMER_RST - Set this bit to reset system timer. + SYSTIMER_CLK_EN + Set this bit to enable clock of system timer. 29 1 read-write - ADC2_ARB_RST - Set this bit to reset aribiter of ADC2. + ADC2_ARB_CLK_EN + Set this bit to enable clock of aribiter of ADC2. 30 1 read-write - SPI4_RST - Set this bit to reset SPI4. + SPI4_CLK_EN + Set this bit to enable clock of SPI4. 31 1 read-write @@ -32371,50 +32451,49 @@ I2C_COMD15_REG in Chapter I²C Controller. - PERIP_RST_EN1 - System peripheral (hardware accelerators) reset register 1 - 0x4C + PERIP_CLK_EN1 + System peripheral clock (for hardware accelerators) enable register 1 + 0x44 0x20 - 0x0000007E - CRYPTO_AES_RST - Set this bit to reset cryptography AES. + CRYPTO_AES_CLK_EN + Set this bit to enable clock of cryptography AES. 1 1 read-write - CRYPTO_SHA_RST - Set this bit to reset cryptography SHA. + CRYPTO_SHA_CLK_EN + Set this bit to enable clock of cryptography SHA. 2 1 read-write - CRYPTO_RSA_RST - Set this bit to reset cryptography RSA. + CRYPTO_RSA_CLK_EN + Set this bit to enable clock of cryptography RSA. 3 1 read-write - CRYPTO_DS_RST - Set this bit to reset cryptography digital signature. + CRYPTO_DS_CLK_EN + Set this bit to enable clock of cryptography Digital Signature. 4 1 read-write - CRYPTO_HMAC_RST - Set this bit to reset cryptography HMAC. + CRYPTO_HMAC_CLK_EN + Set this bit to enable clock of cryptography HMAC. 5 1 read-write - CRYPTO_DMA_RST - Set this bit to reset cryptography DMA. + CRYPTO_DMA_CLK_EN + Set this bit to enable clock of cryptography DMA. 6 1 read-write @@ -32422,24 +32501,307 @@ I2C_COMD15_REG in Chapter I²C Controller. - LPCK_DIV_INT - Low power clock divider integer register - 0x50 + PERIP_RST_EN0 + System peripheral (hardware accelerators) reset register 0 + 0x48 0x20 - 0x000000FF - LPCK_DIV_NUM - This field is used to set the integer number of the divider value. + TIMERS_RST + Set this bit to reset timers. 0 - 12 + 1 read-write - - - - BT_LPCK_DIV_FRAC - Divider fraction configuration register for low-power clock + + SPI01_RST + Set this bit to reset SPI0 and SPI1. + 1 + 1 + read-write + + + UART_RST + Set this bit to reset UART0. + 2 + 1 + read-write + + + WDG_RST + Set this bit to reset WDG. + 3 + 1 + read-write + + + I2S0_RST + Set this bit to reset I2S0. + 4 + 1 + read-write + + + UART1_RST + Set this bit to reset UART1. + 5 + 1 + read-write + + + SPI2_RST + Set this bit to reset SPI2. + 6 + 1 + read-write + + + I2C_EXT0_RST + Set this bit to reset I2C EXT0. + 7 + 1 + read-write + + + UHCI0_RST + Set this bit to reset UHCI0. + 8 + 1 + read-write + + + RMT_RST + Set this bit to reset remote controller. + 9 + 1 + read-write + + + PCNT_RST + Set this bit to reset pulse count. + 10 + 1 + read-write + + + LEDC_RST + Set this bit to reset LED PWM. + 11 + 1 + read-write + + + UHCI1_RST + Set this bit to reset UHCI1. + 12 + 1 + read-write + + + TIMERGROUP_RST + Set this bit to reset timer group0. + 13 + 1 + read-write + + + EFUSE_RST + Set this bit to reset eFuse. + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set this bit to reset timer group1. + 15 + 1 + read-write + + + SPI3_RST + Set this bit to reset SPI3. + 16 + 1 + read-write + + + PWM0_RST + Set this bit to reset PWM0. + 17 + 1 + read-write + + + I2C_EXT1_RST + Set this bit to reset I2C EXT1. + 18 + 1 + read-write + + + TWAI_RST + Set this bit to reset CAN. + 19 + 1 + read-write + + + PWM1_RST + Set this bit to reset PWM1. + 20 + 1 + read-write + + + I2S1_RST + Set this bit to reset I2S1. + 21 + 1 + read-write + + + SPI2_DMA_RST + Set this bit to reset SPI2 DMA. + 22 + 1 + read-write + + + USB_RST + Set this bit to reset USB. + 23 + 1 + read-write + + + UART_MEM_RST + Set this bit to reset UART memory. + 24 + 1 + read-write + + + PWM2_RST + Set this bit to reset PWM2. + 25 + 1 + read-write + + + PWM3_RST + Set this bit to reset PWM3. + 26 + 1 + read-write + + + SPI3_DMA_RST + Set this bit to reset SPI3 DMA. + 27 + 1 + read-write + + + APB_SARADC_RST + Set this bit to reset SAR ADC. + 28 + 1 + read-write + + + SYSTIMER_RST + Set this bit to reset system timer. + 29 + 1 + read-write + + + ADC2_ARB_RST + Set this bit to reset aribiter of ADC2. + 30 + 1 + read-write + + + SPI4_RST + Set this bit to reset SPI4. + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + System peripheral (hardware accelerators) reset register 1 + 0x4C + 0x20 + 0x0000007E + + + CRYPTO_AES_RST + Set this bit to reset cryptography AES. + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set this bit to reset cryptography SHA. + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set this bit to reset cryptography RSA. + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set this bit to reset cryptography digital signature. + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set this bit to reset cryptography HMAC. + 5 + 1 + read-write + + + CRYPTO_DMA_RST + Set this bit to reset cryptography DMA. + 6 + 1 + read-write + + + + + LPCK_DIV_INT + Low power clock divider integer register + 0x50 + 0x20 + 0x000000FF + + + LPCK_DIV_NUM + This field is used to set the integer number of the divider value. + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + Divider fraction configuration register for low-power clock 0x54 0x20 0x02000000 @@ -33109,13 +33471,13 @@ alarms mode. - UPDATE + UNIT0_OP Read out system timer value 0x38 0x20 - TIMER_VALUE_VALID + TIMER_UNIT0_VALUE_VALID Check if it is valid to read out timer value from registers. 0: Not ready to read timer value from registers; 1: Ready to read timer value from registers 30 @@ -33123,7 +33485,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi read-only - TIMER_UPDATE + TIMER_UNIT0_UPDATE Update system timer value to registers. 31 1 @@ -33132,7 +33494,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi - VALUE_HI + UNIT0_VALUE_HI System timer value, high 32 bits 0x3C 0x20 @@ -33147,7 +33509,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi - VALUE_LO + UNIT0_VALUE_LO System timer value, low 32 bits 0x40 0x20 @@ -33168,21 +33530,21 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - INT0_ENA + TARGET0_INT_ENA Interrupt enable bit of system timer target 0. 0 1 read-write - INT1_ENA + TARGET1_INT_ENA Interrupt enable bit of system timer target 1. 1 1 read-write - INT2_ENA + TARGET2_INT_ENA Interrupt enable bit of system timer target 2. 2 1 @@ -33226,21 +33588,21 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - INT0_CLR + TARGET0_INT_CLR Interrupt clear bit of system timer target 0. 0 1 write-only - INT1_CLR + TARGET1_INT_CLR Interrupt clear bit of system timer target 1. 1 1 write-only - INT2_CLR + TARGET2_INT_CLR Interrupt clear bit of system timer target 2. 2 1 @@ -33268,7 +33630,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi TIMG0 - Timer Group + Timer Group 0 TIMG 0x3F41F000 @@ -33319,56 +33681,56 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x60002000 - T0_USE_XTAL + USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. 9 1 read-write - T0_ALARM_EN + ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. 10 1 read-write - T0_LEVEL_INT_EN + LEVEL_INT_EN When set, an alarm will generate a level type interrupt. 11 1 read-write - T0_EDGE_INT_EN + EDGE_INT_EN When set, an alarm will generate an edge type interrupt. 12 1 read-write - T0_DIVIDER + DIVIDER Timer %s clock (T%s_clk) prescaler value. 13 16 read-write - T0_AUTORELOAD + AUTORELOAD When set, timer %s auto-reload at alarm is enabled. 29 1 read-write - T0_INCREASE + INCREASE When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. 30 1 read-write - T0_EN + EN When set, the timer %s time-base counter is enabled. 31 1 @@ -33385,7 +33747,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - T0_LO + LO After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. 0 32 @@ -33402,7 +33764,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - T0_HI + HI After writing to TIMG_T%sUPDATE_REG, the high 32 bits of the time-base counter of timer %s can be read here. 0 32 @@ -33419,7 +33781,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - T0_UPDATE + UPDATE After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 @@ -33436,7 +33798,7 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - T0_ALARM_LO + ALARM_LO Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 @@ -33453,9 +33815,8 @@ ready to read timer value from registers; 1: Ready to read timer value from regi 0x20 - T0_ALARM_HI - -Timer %s alarm trigger time-base counter value, high 32 bits. + ALARM_HI + Timer %s alarm trigger time-base counter value, high 32 bits. 0 32 read-write @@ -33471,7 +33832,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. 0x20 - T0_LOAD_LO + LOAD_LO Low 32 bits of the value that a reload will load onto timer %s time-base counter. 0 32 @@ -33488,7 +33849,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. 0x20 - T0_LOAD_HI + LOAD_HI High 32 bits of the value that a reload will load onto timer %s time-base counter. 0 32 @@ -33505,7 +33866,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. 0x20 - T0_LOAD + LOAD Write any value to trigger a timer %s time-base counter reload. 0 32 @@ -33614,7 +33975,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. 0x00010000 - WDT_CLK_PRESCALER + WDT_CLK_PRESCALE MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. 16 16 @@ -34213,7 +34574,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. TIMG1 - Timer Group + Timer Group 1 0x3F420000 TG1_T0_LEVEL @@ -34249,7 +34610,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. - TWAI + TWAI0 Two-Wire Automotive Interface TWAI 0x3F42B000 @@ -34259,7 +34620,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. registers - CAN + TWAI0 47 @@ -34539,12 +34900,14 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 + read-write @@ -34559,18 +34922,21 @@ Timer %s alarm trigger time-base counter value, high 32 bits. The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -34630,6 +34996,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -34644,6 +35011,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. The RX error counter register, reflects value changes under reception status. 0 8 + read-write @@ -34658,6 +35026,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -34672,7 +35041,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34687,7 +35056,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34702,7 +35071,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34717,7 +35086,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34732,7 +35101,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34747,7 +35116,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34762,7 +35131,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34777,7 +35146,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34792,7 +35161,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34807,7 +35176,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34822,7 +35191,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34837,7 +35206,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34852,7 +35221,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34889,6 +35258,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 + read-write @@ -34896,7 +35266,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x3F400000 @@ -36384,16 +36754,20 @@ The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes mor UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x3F410000 UART1 38 + + UART2 + 39 + UHCI0 - Universal Host Controller Interface + Universal Host Controller Interface 0 UHCI 0x3F414000 @@ -36405,6 +36779,10 @@ The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes mor UHCI0 13 + + UHCI1 + 14 + CONF0 @@ -38122,6 +38500,8006 @@ If this bit is set to 0, UHCI decoder stops receiving payload data upon receivi + + USB0 + USB OTG (On-The-Go) + USB + 0x60080000 + + 0x0 + 0x2A0 + registers + + + USB + 48 + + + + GOTGCTL + 0x0 + 0x20 + + + SESREQSCS + 0 + 1 + read-only + + + SESREQ + 1 + 1 + read-write + + + VBVALIDOVEN + 2 + 1 + read-write + + + VBVALIDOVVAL + 3 + 1 + read-write + + + AVALIDOVEN + 4 + 1 + read-write + + + AVALIDOVVAL + 5 + 1 + read-write + + + BVALIDOVEN + 6 + 1 + read-write + + + BVALIDOVVAL + 7 + 1 + read-write + + + HSTNEGSCS + 8 + 1 + read-only + + + HNPREQ + 9 + 1 + read-write + + + HSTSETHNPEN + 10 + 1 + read-write + + + DEVHNPEN + 11 + 1 + read-write + + + EHEN + 12 + 1 + read-write + + + DBNCEFLTRBYPASS + 15 + 1 + read-write + + + CONIDSTS + 16 + 1 + read-only + + + DBNCTIME + 17 + 1 + read-only + + + ASESVLD + 18 + 1 + read-only + + + BSESVLD + 19 + 1 + read-only + + + OTGVER + 20 + 1 + read-write + + + CURMOD + 21 + 1 + read-only + + + + + GOTGINT + 0x4 + 0x20 + + + SESENDDET + 2 + 1 + read-write + + + SESREQSUCSTSCHNG + 8 + 1 + read-write + + + HSTNEGSUCSTSCHNG + 9 + 1 + read-write + + + HSTNEGDET + 17 + 1 + read-write + + + ADEVTOUTCHG + 18 + 1 + read-write + + + DBNCEDONE + 19 + 1 + read-write + + + + + GAHBCFG + 0x8 + 0x20 + + + GLBLLNTRMSK + 0 + 1 + read-write + + + HBSTLEN + 1 + 4 + read-write + + + DMAEN + 5 + 1 + read-write + + + NPTXFEMPLVL + 7 + 1 + read-write + + + PTXFEMPLVL + 8 + 1 + read-write + + + REMMEMSUPP + 21 + 1 + read-write + + + NOTIALLDMAWRIT + 22 + 1 + read-write + + + AHBSINGLE + 23 + 1 + read-write + + + INVDESCENDIANESS + 24 + 1 + read-write + + + + + GUSBCFG + 0xC + 0x20 + 0x00001440 + + + TOUTCAL + 0 + 3 + read-write + + + PHYIF + 3 + 1 + read-write + + + ULPI_UTMI_SEL + 4 + 1 + read-only + + + FSINTF + 5 + 1 + read-write + + + PHYSEL + 6 + 1 + read-only + + + SRPCAP + 8 + 1 + read-write + + + HNPCAP + 9 + 1 + read-write + + + USBTRDTIM + 10 + 4 + read-write + + + TERMSELDLPULSE + 22 + 1 + read-write + + + TXENDDELAY + 28 + 1 + read-write + + + FORCEHSTMODE + 29 + 1 + read-write + + + FORCEDEVMODE + 30 + 1 + read-write + + + CORRUPTTXPKT + 31 + 1 + read-write + + + + + GRSTCTL + 0x10 + 0x20 + + + CSFTRST + 0 + 1 + read-write + + + PIUFSSFTRST + 1 + 1 + read-write + + + FRMCNTRRST + 2 + 1 + read-write + + + RXFFLSH + 4 + 1 + read-write + + + TXFFLSH + 5 + 1 + read-write + + + TXFNUM + 6 + 5 + read-write + + + DMAREQ + 30 + 1 + read-only + + + AHBIDLE + 31 + 1 + read-only + + + + + GINTSTS + 0x14 + 0x20 + + + CURMOD_INT + 0 + 1 + read-only + + + MODEMIS + 1 + 1 + read-write + + + OTGINT + 2 + 1 + read-only + + + SOF + 3 + 1 + read-write + + + RXFLVI + 4 + 1 + read-only + + + NPTXFEMP + 5 + 1 + read-only + + + GINNAKEFF + 6 + 1 + read-only + + + GOUTNAKEFF + 7 + 1 + read-only + + + ERLYSUSP + 10 + 1 + read-write + + + USBSUSP + 11 + 1 + read-write + + + USBRST + 12 + 1 + read-write + + + ENUMDONE + 13 + 1 + read-write + + + ISOOUTDROP + 14 + 1 + read-write + + + EOPF + 15 + 1 + read-write + + + EPMIS + 17 + 1 + read-write + + + IEPINT + 18 + 1 + read-only + + + OEPINT + 19 + 1 + read-only + + + INCOMPISOIN + 20 + 1 + read-write + + + INCOMPIP + 21 + 1 + read-write + + + FETSUSP + 22 + 1 + read-write + + + RESETDET + 23 + 1 + read-write + + + PRTLNT + 24 + 1 + read-only + + + HCHLNT + 25 + 1 + read-only + + + PTXFEMP + 26 + 1 + read-only + + + CONIDSTSCHNG + 28 + 1 + read-write + + + DISCONNINT + 29 + 1 + read-write + + + SESSREQINT + 30 + 1 + read-write + + + WKUPINT + 31 + 1 + read-write + + + + + GINTMSK + 0x18 + 0x20 + + + MODEMISMSK + 1 + 1 + read-write + + + OTGINTMSK + 2 + 1 + read-write + + + SOFMSK + 3 + 1 + read-write + + + RXFLVIMSK + 4 + 1 + read-write + + + NPTXFEMPMSK + 5 + 1 + read-write + + + GINNAKEFFMSK + 6 + 1 + read-write + + + GOUTNACKEFFMSK + 7 + 1 + read-write + + + ERLYSUSPMSK + 10 + 1 + read-write + + + USBSUSPMSK + 11 + 1 + read-write + + + USBRSTMSK + 12 + 1 + read-write + + + ENUMDONEMSK + 13 + 1 + read-write + + + ISOOUTDROPMSK + 14 + 1 + read-write + + + EOPFMSK + 15 + 1 + read-write + + + EPMISMSK + 17 + 1 + read-write + + + IEPINTMSK + 18 + 1 + read-write + + + OEPINTMSK + 19 + 1 + read-write + + + INCOMPISOINMSK + 20 + 1 + read-write + + + INCOMPIPMSK + 21 + 1 + read-write + + + FETSUSPMSK + 22 + 1 + read-write + + + RESETDETMSK + 23 + 1 + read-write + + + PRTLNTMSK + 24 + 1 + read-write + + + HCHINTMSK + 25 + 1 + read-write + + + PTXFEMPMSK + 26 + 1 + read-write + + + CONIDSTSCHNGMSK + 28 + 1 + read-write + + + DISCONNINTMSK + 29 + 1 + read-write + + + SESSREQINTMSK + 30 + 1 + read-write + + + WKUPINTMSK + 31 + 1 + read-write + + + + + GRXSTSR + 0x1C + 0x20 + + + G_CHNUM + 0 + 4 + read-only + + + G_BCNT + 4 + 11 + read-only + + + G_DPID + 15 + 2 + read-only + + + G_PKTSTS + 17 + 4 + read-only + + + G_FN + 21 + 4 + read-only + + + + + GRXSTSP + 0x20 + 0x20 + + + CHNUM + 0 + 4 + read-only + + + BCNT + 4 + 11 + read-only + + + DPID + 15 + 2 + read-only + + + PKTSTS + 17 + 4 + read-only + + + FN + 21 + 4 + read-only + + + + + GRXFSIZ + 0x24 + 0x20 + 0x00000100 + + + RXFDEP + 0 + 16 + read-write + + + + + GNPTXFSIZ + 0x28 + 0x20 + 0x01000100 + + + NPTXFSTADDR + 0 + 16 + read-write + + + NPTXFDEP + 16 + 16 + read-write + + + + + GNPTXSTS + 0x2C + 0x20 + 0x00040100 + + + NPTXFSPCAVAIL + 0 + 16 + read-only + + + NPTXQSPCAVAIL + 16 + 4 + read-only + + + NPTXQTOP + 24 + 7 + read-only + + + + + GSNPSID + 0x40 + 0x20 + 0x4F54400A + + + SYNOPSYSID + 0 + 32 + read-only + + + + + GHWCFG1 + 0x44 + 0x20 + + + EPDIR + 0 + 32 + read-only + + + + + GHWCFG2 + 0x48 + 0x20 + 0x224DD930 + + + OTGMODE + 0 + 3 + read-only + + + OTGARCH + 3 + 2 + read-only + + + SINGPNT + 5 + 1 + read-only + + + HSPHYTYPE + 6 + 2 + read-only + + + FSPHYTYPE + 8 + 2 + read-only + + + NUMDEVEPS + 10 + 4 + read-only + + + NUMHSTCHNL + 14 + 4 + read-only + + + PERIOSUPPORT + 18 + 1 + read-only + + + DYNFIFOSIZING + 19 + 1 + read-only + + + MULTIPROCINTRPT + 20 + 1 + read-only + + + NPTXQDEPTH + 22 + 2 + read-only + + + PTXQDEPTH + 24 + 2 + read-only + + + TKNQDEPTH + 26 + 5 + read-only + + + OTG_ENABLE_IC_USB + 31 + 1 + read-only + + + + + GHWCFG3 + 0x4C + 0x20 + 0x010004B5 + + + XFERSIZEWIDTH + 0 + 4 + read-only + + + PKTSIZEWIDTH + 4 + 3 + read-only + + + OTGEN + 7 + 1 + read-only + + + I2CINTSEL + 8 + 1 + read-only + + + VNDCTLSUPT + 9 + 1 + read-only + + + OPTFEATURE + 10 + 1 + read-only + + + RSTTYPE + 11 + 1 + read-only + + + ADPSUPPORT + 12 + 1 + read-only + + + HSICMODE + 13 + 1 + read-only + + + BCSUPPORT + 14 + 1 + read-only + + + LPMMODE + 15 + 1 + read-only + + + DFIFODEPTH + 16 + 16 + read-only + + + + + GHWCFG4 + 0x50 + 0x20 + 0xD3F0A030 + + + G_NUMDEVPERIOEPS + 0 + 4 + read-only + + + G_PARTIALPWRDN + 4 + 1 + read-only + + + G_AHBFREQ + 5 + 1 + read-only + + + G_HIBERNATION + 6 + 1 + read-only + + + G_EXTENDEDHIBERNATION + 7 + 1 + read-only + + + G_ACGSUPT + 12 + 1 + read-only + + + G_ENHANCEDLPMSUPT + 13 + 1 + read-only + + + G_PHYDATAWIDTH + 14 + 2 + read-only + + + G_NUMCTLEPS + 16 + 4 + read-only + + + G_IDDQFLTR + 20 + 1 + read-only + + + G_VBUSVALIDFLTR + 21 + 1 + read-only + + + G_AVALIDFLTR + 22 + 1 + read-only + + + G_BVALIDFLTR + 23 + 1 + read-only + + + G_SESSENDFLTR + 24 + 1 + read-only + + + G_DEDFIFOMODE + 25 + 1 + read-only + + + G_INEPS + 26 + 4 + read-only + + + G_DESCDMAENABLED + 30 + 1 + read-only + + + G_DESCDMA + 31 + 1 + read-only + + + + + GDFIFOCFG + 0x5C + 0x20 + + + GDFIFOCFG + 0 + 16 + read-write + + + EPINFOBASEADDR + 16 + 16 + read-write + + + + + HPTXFSIZ + 0x100 + 0x20 + 0x10000200 + + + PTXFSTADDR + 0 + 16 + read-write + + + PTXFSIZE + 16 + 16 + read-write + + + + + DIEPTXF1 + 0x104 + 0x20 + 0x10000200 + + + INEP1TXFSTADDR + 0 + 16 + read-write + + + INEP1TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF2 + 0x108 + 0x20 + 0x10000200 + + + INEP2TXFSTADDR + 0 + 16 + read-write + + + INEP2TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF3 + 0x10C + 0x20 + 0x10000200 + + + INEP3TXFSTADDR + 0 + 16 + read-write + + + INEP3TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF4 + 0x110 + 0x20 + 0x10000200 + + + INEP4TXFSTADDR + 0 + 16 + read-write + + + INEP4TXFDEP + 16 + 16 + read-write + + + + + HCFG + 0x400 + 0x20 + + + H_FSLSPCLKSEL + 0 + 2 + read-write + + + H_FSLSSUPP + 2 + 1 + read-write + + + H_ENA32KHZS + 7 + 1 + read-write + + + H_DESCDMA + 23 + 1 + read-write + + + H_FRLISTEN + 24 + 2 + read-write + + + H_PERSCHEDENA + 26 + 1 + read-write + + + H_MODECHTIMEN + 31 + 1 + read-write + + + + + HFIR + 0x404 + 0x20 + 0x000017D7 + + + FRINT + 0 + 16 + read-write + + + HFIRRLDCTRL + 16 + 1 + read-write + + + + + HFNUM + 0x408 + 0x20 + 0x00003FFF + + + FRNUM + 0 + 14 + read-only + + + FRREM + 16 + 16 + read-only + + + + + HPTXSTS + 0x410 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + 0 + 16 + read-only + + + PTXQSPCAVAIL + 16 + 5 + read-only + + + PTXQTOP + 24 + 8 + read-only + + + + + HAINT + 0x414 + 0x20 + + + HAINT + 0 + 8 + read-only + + + + + HAINTMSK + 0x418 + 0x20 + + + HAINTMSK + 0 + 8 + read-write + + + + + HFLBADDR + 0x41C + 0x20 + + + HFLBADDR + 0 + 32 + read-write + + + + + HPRT + 0x440 + 0x20 + + + PRTCONNSTS + 0 + 1 + read-only + + + PRTCONNDET + 1 + 1 + read-write + + + PRTENA + 2 + 1 + read-write + + + PRTENCHNG + 3 + 1 + read-write + + + PRTOVRCURRACT + 4 + 1 + read-only + + + PRTOVRCURRCHNG + 5 + 1 + read-write + + + PRTRES + 6 + 1 + read-write + + + PRTSUSP + 7 + 1 + read-write + + + PRTRST + 8 + 1 + read-write + + + PRTLNSTS + 10 + 2 + read-only + + + PRTPWR + 12 + 1 + read-write + + + PRTTSTCTL + 13 + 4 + read-write + + + PRTSPD + 17 + 2 + read-only + + + + + HCCHAR0 + 0x500 + 0x20 + + + H_MPS0 + 0 + 11 + read-write + + + H_EPNUM0 + 11 + 4 + read-write + + + H_EPDIR0 + 15 + 1 + read-write + + + H_LSPDDEV0 + 17 + 1 + read-write + + + H_EPTYPE0 + 18 + 2 + read-write + + + H_EC0 + 21 + 1 + read-write + + + H_DEVADDR0 + 22 + 7 + read-write + + + H_ODDFRM0 + 29 + 1 + read-write + + + H_CHDIS0 + 30 + 1 + read-write + + + H_CHENA0 + 31 + 1 + read-write + + + + + HCINT0 + 0x508 + 0x20 + + + H_XFERCOMPL0 + 0 + 1 + read-write + + + H_CHHLTD0 + 1 + 1 + read-write + + + H_AHBERR0 + 2 + 1 + read-write + + + H_STALL0 + 3 + 1 + read-write + + + H_NACK0 + 4 + 1 + read-write + + + H_ACK0 + 5 + 1 + read-write + + + H_NYET0 + 6 + 1 + read-write + + + H_XACTERR0 + 7 + 1 + read-write + + + H_BBLERR0 + 8 + 1 + read-write + + + H_FRMOVRUN0 + 9 + 1 + read-write + + + H_DATATGLERR0 + 10 + 1 + read-write + + + H_BNAINTR0 + 11 + 1 + read-write + + + H_XCS_XACT_ERR0 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR0 + 13 + 1 + read-write + + + + + HCINTMSK0 + 0x50C + 0x20 + + + H_XFERCOMPLMSK0 + 0 + 1 + read-write + + + H_CHHLTDMSK0 + 1 + 1 + read-write + + + H_AHBERRMSK0 + 2 + 1 + read-write + + + H_STALLMSK0 + 3 + 1 + read-write + + + H_NAKMSK0 + 4 + 1 + read-write + + + H_ACKMSK0 + 5 + 1 + read-write + + + H_NYETMSK0 + 6 + 1 + read-write + + + H_XACTERRMSK0 + 7 + 1 + read-write + + + H_BBLERRMSK0 + 8 + 1 + read-write + + + H_FRMOVRUNMSK0 + 9 + 1 + read-write + + + H_DATATGLERRMSK0 + 10 + 1 + read-write + + + H_BNAINTRMSK0 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK0 + 13 + 1 + read-write + + + + + HCTSIZ0 + 0x510 + 0x20 + + + H_XFERSIZE0 + 0 + 19 + read-write + + + H_PKTCNT0 + 19 + 10 + read-write + + + H_PID0 + 29 + 2 + read-write + + + H_DOPNG0 + 31 + 1 + read-write + + + + + HCDMA0 + 0x514 + 0x20 + + + H_DMAADDR0 + 0 + 32 + read-write + + + + + HCDMAB0 + 0x51C + 0x20 + + + H_HCDMAB0 + 0 + 32 + read-only + + + + + HCCHAR1 + 0x520 + 0x20 + + + H_MPS1 + 0 + 11 + read-write + + + H_EPNUM1 + 11 + 4 + read-write + + + H_EPDIR1 + 15 + 1 + read-write + + + H_LSPDDEV1 + 17 + 1 + read-write + + + H_EPTYPE1 + 18 + 2 + read-write + + + H_EC1 + 21 + 1 + read-write + + + H_DEVADDR1 + 22 + 7 + read-write + + + H_ODDFRM1 + 29 + 1 + read-write + + + H_CHDIS1 + 30 + 1 + read-write + + + H_CHENA1 + 31 + 1 + read-write + + + + + HCINT1 + 0x528 + 0x20 + + + H_XFERCOMPL1 + 0 + 1 + read-write + + + H_CHHLTD1 + 1 + 1 + read-write + + + H_AHBERR1 + 2 + 1 + read-write + + + H_STALL1 + 3 + 1 + read-write + + + H_NACK1 + 4 + 1 + read-write + + + H_ACK1 + 5 + 1 + read-write + + + H_NYET1 + 6 + 1 + read-write + + + H_XACTERR1 + 7 + 1 + read-write + + + H_BBLERR1 + 8 + 1 + read-write + + + H_FRMOVRUN1 + 9 + 1 + read-write + + + H_DATATGLERR1 + 10 + 1 + read-write + + + H_BNAINTR1 + 11 + 1 + read-write + + + H_XCS_XACT_ERR1 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR1 + 13 + 1 + read-write + + + + + HCINTMSK1 + 0x52C + 0x20 + + + H_XFERCOMPLMSK1 + 0 + 1 + read-write + + + H_CHHLTDMSK1 + 1 + 1 + read-write + + + H_AHBERRMSK1 + 2 + 1 + read-write + + + H_STALLMSK1 + 3 + 1 + read-write + + + H_NAKMSK1 + 4 + 1 + read-write + + + H_ACKMSK1 + 5 + 1 + read-write + + + H_NYETMSK1 + 6 + 1 + read-write + + + H_XACTERRMSK1 + 7 + 1 + read-write + + + H_BBLERRMSK1 + 8 + 1 + read-write + + + H_FRMOVRUNMSK1 + 9 + 1 + read-write + + + H_DATATGLERRMSK1 + 10 + 1 + read-write + + + H_BNAINTRMSK1 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK1 + 13 + 1 + read-write + + + + + HCTSIZ1 + 0x530 + 0x20 + + + H_XFERSIZE1 + 0 + 19 + read-write + + + H_PKTCNT1 + 19 + 10 + read-write + + + H_PID1 + 29 + 2 + read-write + + + H_DOPNG1 + 31 + 1 + read-write + + + + + HCDMA1 + 0x534 + 0x20 + + + H_DMAADDR1 + 0 + 32 + read-write + + + + + HCDMAB1 + 0x53C + 0x20 + + + H_HCDMAB1 + 0 + 32 + read-only + + + + + HCCHAR2 + 0x540 + 0x20 + + + H_MPS2 + 0 + 11 + read-write + + + H_EPNUM2 + 11 + 4 + read-write + + + H_EPDIR2 + 15 + 1 + read-write + + + H_LSPDDEV2 + 17 + 1 + read-write + + + H_EPTYPE2 + 18 + 2 + read-write + + + H_EC2 + 21 + 1 + read-write + + + H_DEVADDR2 + 22 + 7 + read-write + + + H_ODDFRM2 + 29 + 1 + read-write + + + H_CHDIS2 + 30 + 1 + read-write + + + H_CHENA2 + 31 + 1 + read-write + + + + + HCINT2 + 0x548 + 0x20 + + + H_XFERCOMPL2 + 0 + 1 + read-write + + + H_CHHLTD2 + 1 + 1 + read-write + + + H_AHBERR2 + 2 + 1 + read-write + + + H_STALL2 + 3 + 1 + read-write + + + H_NACK2 + 4 + 1 + read-write + + + H_ACK2 + 5 + 1 + read-write + + + H_NYET2 + 6 + 1 + read-write + + + H_XACTERR2 + 7 + 1 + read-write + + + H_BBLERR2 + 8 + 1 + read-write + + + H_FRMOVRUN2 + 9 + 1 + read-write + + + H_DATATGLERR2 + 10 + 1 + read-write + + + H_BNAINTR2 + 11 + 1 + read-write + + + H_XCS_XACT_ERR2 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR2 + 13 + 1 + read-write + + + + + HCINTMSK2 + 0x54C + 0x20 + + + H_XFERCOMPLMSK2 + 0 + 1 + read-write + + + H_CHHLTDMSK2 + 1 + 1 + read-write + + + H_AHBERRMSK2 + 2 + 1 + read-write + + + H_STALLMSK2 + 3 + 1 + read-write + + + H_NAKMSK2 + 4 + 1 + read-write + + + H_ACKMSK2 + 5 + 1 + read-write + + + H_NYETMSK2 + 6 + 1 + read-write + + + H_XACTERRMSK2 + 7 + 1 + read-write + + + H_BBLERRMSK2 + 8 + 1 + read-write + + + H_FRMOVRUNMSK2 + 9 + 1 + read-write + + + H_DATATGLERRMSK2 + 10 + 1 + read-write + + + H_BNAINTRMSK2 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK2 + 13 + 1 + read-write + + + + + HCTSIZ2 + 0x550 + 0x20 + + + H_XFERSIZE2 + 0 + 19 + read-write + + + H_PKTCNT2 + 19 + 10 + read-write + + + H_PID2 + 29 + 2 + read-write + + + H_DOPNG2 + 31 + 1 + read-write + + + + + HCDMA2 + 0x554 + 0x20 + + + H_DMAADDR2 + 0 + 32 + read-write + + + + + HCDMAB2 + 0x55C + 0x20 + + + H_HCDMAB2 + 0 + 32 + read-only + + + + + HCCHAR3 + 0x560 + 0x20 + + + H_MPS3 + 0 + 11 + read-write + + + H_EPNUM3 + 11 + 4 + read-write + + + H_EPDIR3 + 15 + 1 + read-write + + + H_LSPDDEV3 + 17 + 1 + read-write + + + H_EPTYPE3 + 18 + 2 + read-write + + + H_EC3 + 21 + 1 + read-write + + + H_DEVADDR3 + 22 + 7 + read-write + + + H_ODDFRM3 + 29 + 1 + read-write + + + H_CHDIS3 + 30 + 1 + read-write + + + H_CHENA3 + 31 + 1 + read-write + + + + + HCINT3 + 0x568 + 0x20 + + + H_XFERCOMPL3 + 0 + 1 + read-write + + + H_CHHLTD3 + 1 + 1 + read-write + + + H_AHBERR3 + 2 + 1 + read-write + + + H_STALL3 + 3 + 1 + read-write + + + H_NACK3 + 4 + 1 + read-write + + + H_ACK3 + 5 + 1 + read-write + + + H_NYET3 + 6 + 1 + read-write + + + H_XACTERR3 + 7 + 1 + read-write + + + H_BBLERR3 + 8 + 1 + read-write + + + H_FRMOVRUN3 + 9 + 1 + read-write + + + H_DATATGLERR3 + 10 + 1 + read-write + + + H_BNAINTR3 + 11 + 1 + read-write + + + H_XCS_XACT_ERR3 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR3 + 13 + 1 + read-write + + + + + HCINTMSK3 + 0x56C + 0x20 + + + H_XFERCOMPLMSK3 + 0 + 1 + read-write + + + H_CHHLTDMSK3 + 1 + 1 + read-write + + + H_AHBERRMSK3 + 2 + 1 + read-write + + + H_STALLMSK3 + 3 + 1 + read-write + + + H_NAKMSK3 + 4 + 1 + read-write + + + H_ACKMSK3 + 5 + 1 + read-write + + + H_NYETMSK3 + 6 + 1 + read-write + + + H_XACTERRMSK3 + 7 + 1 + read-write + + + H_BBLERRMSK3 + 8 + 1 + read-write + + + H_FRMOVRUNMSK3 + 9 + 1 + read-write + + + H_DATATGLERRMSK3 + 10 + 1 + read-write + + + H_BNAINTRMSK3 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK3 + 13 + 1 + read-write + + + + + HCTSIZ3 + 0x570 + 0x20 + + + H_XFERSIZE3 + 0 + 19 + read-write + + + H_PKTCNT3 + 19 + 10 + read-write + + + H_PID3 + 29 + 2 + read-write + + + H_DOPNG3 + 31 + 1 + read-write + + + + + HCDMA3 + 0x574 + 0x20 + + + H_DMAADDR3 + 0 + 32 + read-write + + + + + HCDMAB3 + 0x57C + 0x20 + + + H_HCDMAB3 + 0 + 32 + read-only + + + + + HCCHAR4 + 0x580 + 0x20 + + + H_MPS4 + 0 + 11 + read-write + + + H_EPNUM4 + 11 + 4 + read-write + + + H_EPDIR4 + 15 + 1 + read-write + + + H_LSPDDEV4 + 17 + 1 + read-write + + + H_EPTYPE4 + 18 + 2 + read-write + + + H_EC4 + 21 + 1 + read-write + + + H_DEVADDR4 + 22 + 7 + read-write + + + H_ODDFRM4 + 29 + 1 + read-write + + + H_CHDIS4 + 30 + 1 + read-write + + + H_CHENA4 + 31 + 1 + read-write + + + + + HCINT4 + 0x588 + 0x20 + + + H_XFERCOMPL4 + 0 + 1 + read-write + + + H_CHHLTD4 + 1 + 1 + read-write + + + H_AHBERR4 + 2 + 1 + read-write + + + H_STALL4 + 3 + 1 + read-write + + + H_NACK4 + 4 + 1 + read-write + + + H_ACK4 + 5 + 1 + read-write + + + H_NYET4 + 6 + 1 + read-write + + + H_XACTERR4 + 7 + 1 + read-write + + + H_BBLERR4 + 8 + 1 + read-write + + + H_FRMOVRUN4 + 9 + 1 + read-write + + + H_DATATGLERR4 + 10 + 1 + read-write + + + H_BNAINTR4 + 11 + 1 + read-write + + + H_XCS_XACT_ERR4 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR4 + 13 + 1 + read-write + + + + + HCINTMSK4 + 0x58C + 0x20 + + + H_XFERCOMPLMSK4 + 0 + 1 + read-write + + + H_CHHLTDMSK4 + 1 + 1 + read-write + + + H_AHBERRMSK4 + 2 + 1 + read-write + + + H_STALLMSK4 + 3 + 1 + read-write + + + H_NAKMSK4 + 4 + 1 + read-write + + + H_ACKMSK4 + 5 + 1 + read-write + + + H_NYETMSK4 + 6 + 1 + read-write + + + H_XACTERRMSK4 + 7 + 1 + read-write + + + H_BBLERRMSK4 + 8 + 1 + read-write + + + H_FRMOVRUNMSK4 + 9 + 1 + read-write + + + H_DATATGLERRMSK4 + 10 + 1 + read-write + + + H_BNAINTRMSK4 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK4 + 13 + 1 + read-write + + + + + HCTSIZ4 + 0x590 + 0x20 + + + H_XFERSIZE4 + 0 + 19 + read-write + + + H_PKTCNT4 + 19 + 10 + read-write + + + H_PID4 + 29 + 2 + read-write + + + H_DOPNG4 + 31 + 1 + read-write + + + + + HCDMA4 + 0x594 + 0x20 + + + H_DMAADDR4 + 0 + 32 + read-write + + + + + HCDMAB4 + 0x59C + 0x20 + + + H_HCDMAB4 + 0 + 32 + read-only + + + + + HCCHAR5 + 0x5A0 + 0x20 + + + H_MPS5 + 0 + 11 + read-write + + + H_EPNUM5 + 11 + 4 + read-write + + + H_EPDIR5 + 15 + 1 + read-write + + + H_LSPDDEV5 + 17 + 1 + read-write + + + H_EPTYPE5 + 18 + 2 + read-write + + + H_EC5 + 21 + 1 + read-write + + + H_DEVADDR5 + 22 + 7 + read-write + + + H_ODDFRM5 + 29 + 1 + read-write + + + H_CHDIS5 + 30 + 1 + read-write + + + H_CHENA5 + 31 + 1 + read-write + + + + + HCINT5 + 0x5A8 + 0x20 + + + H_XFERCOMPL5 + 0 + 1 + read-write + + + H_CHHLTD5 + 1 + 1 + read-write + + + H_AHBERR5 + 2 + 1 + read-write + + + H_STALL5 + 3 + 1 + read-write + + + H_NACK5 + 4 + 1 + read-write + + + H_ACK5 + 5 + 1 + read-write + + + H_NYET5 + 6 + 1 + read-write + + + H_XACTERR5 + 7 + 1 + read-write + + + H_BBLERR5 + 8 + 1 + read-write + + + H_FRMOVRUN5 + 9 + 1 + read-write + + + H_DATATGLERR5 + 10 + 1 + read-write + + + H_BNAINTR5 + 11 + 1 + read-write + + + H_XCS_XACT_ERR5 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR5 + 13 + 1 + read-write + + + + + HCINTMSK5 + 0x5AC + 0x20 + + + H_XFERCOMPLMSK5 + 0 + 1 + read-write + + + H_CHHLTDMSK5 + 1 + 1 + read-write + + + H_AHBERRMSK5 + 2 + 1 + read-write + + + H_STALLMSK5 + 3 + 1 + read-write + + + H_NAKMSK5 + 4 + 1 + read-write + + + H_ACKMSK5 + 5 + 1 + read-write + + + H_NYETMSK5 + 6 + 1 + read-write + + + H_XACTERRMSK5 + 7 + 1 + read-write + + + H_BBLERRMSK5 + 8 + 1 + read-write + + + H_FRMOVRUNMSK5 + 9 + 1 + read-write + + + H_DATATGLERRMSK5 + 10 + 1 + read-write + + + H_BNAINTRMSK5 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK5 + 13 + 1 + read-write + + + + + HCTSIZ5 + 0x5B0 + 0x20 + + + H_XFERSIZE5 + 0 + 19 + read-write + + + H_PKTCNT5 + 19 + 10 + read-write + + + H_PID5 + 29 + 2 + read-write + + + H_DOPNG5 + 31 + 1 + read-write + + + + + HCDMA5 + 0x5B4 + 0x20 + + + H_DMAADDR5 + 0 + 32 + read-write + + + + + HCDMAB5 + 0x5BC + 0x20 + + + H_HCDMAB5 + 0 + 32 + read-only + + + + + HCCHAR6 + 0x5C0 + 0x20 + + + H_MPS6 + 0 + 11 + read-write + + + H_EPNUM6 + 11 + 4 + read-write + + + H_EPDIR6 + 15 + 1 + read-write + + + H_LSPDDEV6 + 17 + 1 + read-write + + + H_EPTYPE6 + 18 + 2 + read-write + + + H_EC6 + 21 + 1 + read-write + + + H_DEVADDR6 + 22 + 7 + read-write + + + H_ODDFRM6 + 29 + 1 + read-write + + + H_CHDIS6 + 30 + 1 + read-write + + + H_CHENA6 + 31 + 1 + read-write + + + + + HCINT6 + 0x5C8 + 0x20 + + + H_XFERCOMPL6 + 0 + 1 + read-write + + + H_CHHLTD6 + 1 + 1 + read-write + + + H_AHBERR6 + 2 + 1 + read-write + + + H_STALL6 + 3 + 1 + read-write + + + H_NACK6 + 4 + 1 + read-write + + + H_ACK6 + 5 + 1 + read-write + + + H_NYET6 + 6 + 1 + read-write + + + H_XACTERR6 + 7 + 1 + read-write + + + H_BBLERR6 + 8 + 1 + read-write + + + H_FRMOVRUN6 + 9 + 1 + read-write + + + H_DATATGLERR6 + 10 + 1 + read-write + + + H_BNAINTR6 + 11 + 1 + read-write + + + H_XCS_XACT_ERR6 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR6 + 13 + 1 + read-write + + + + + HCINTMSK6 + 0x5CC + 0x20 + + + H_XFERCOMPLMSK6 + 0 + 1 + read-write + + + H_CHHLTDMSK6 + 1 + 1 + read-write + + + H_AHBERRMSK6 + 2 + 1 + read-write + + + H_STALLMSK6 + 3 + 1 + read-write + + + H_NAKMSK6 + 4 + 1 + read-write + + + H_ACKMSK6 + 5 + 1 + read-write + + + H_NYETMSK6 + 6 + 1 + read-write + + + H_XACTERRMSK6 + 7 + 1 + read-write + + + H_BBLERRMSK6 + 8 + 1 + read-write + + + H_FRMOVRUNMSK6 + 9 + 1 + read-write + + + H_DATATGLERRMSK6 + 10 + 1 + read-write + + + H_BNAINTRMSK6 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK6 + 13 + 1 + read-write + + + + + HCTSIZ6 + 0x5D0 + 0x20 + + + H_XFERSIZE6 + 0 + 19 + read-write + + + H_PKTCNT6 + 19 + 10 + read-write + + + H_PID6 + 29 + 2 + read-write + + + H_DOPNG6 + 31 + 1 + read-write + + + + + HCDMA6 + 0x5D4 + 0x20 + + + H_DMAADDR6 + 0 + 32 + read-write + + + + + HCDMAB6 + 0x5DC + 0x20 + + + H_HCDMAB6 + 0 + 32 + read-only + + + + + HCCHAR7 + 0x5E0 + 0x20 + + + H_MPS7 + 0 + 11 + read-write + + + H_EPNUM7 + 11 + 4 + read-write + + + H_EPDIR7 + 15 + 1 + read-write + + + H_LSPDDEV7 + 17 + 1 + read-write + + + H_EPTYPE7 + 18 + 2 + read-write + + + H_EC7 + 21 + 1 + read-write + + + H_DEVADDR7 + 22 + 7 + read-write + + + H_ODDFRM7 + 29 + 1 + read-write + + + H_CHDIS7 + 30 + 1 + read-write + + + H_CHENA7 + 31 + 1 + read-write + + + + + HCINT7 + 0x5E8 + 0x20 + + + H_XFERCOMPL7 + 0 + 1 + read-write + + + H_CHHLTD7 + 1 + 1 + read-write + + + H_AHBERR7 + 2 + 1 + read-write + + + H_STALL7 + 3 + 1 + read-write + + + H_NACK7 + 4 + 1 + read-write + + + H_ACK7 + 5 + 1 + read-write + + + H_NYET7 + 6 + 1 + read-write + + + H_XACTERR7 + 7 + 1 + read-write + + + H_BBLERR7 + 8 + 1 + read-write + + + H_FRMOVRUN7 + 9 + 1 + read-write + + + H_DATATGLERR7 + 10 + 1 + read-write + + + H_BNAINTR7 + 11 + 1 + read-write + + + H_XCS_XACT_ERR7 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR7 + 13 + 1 + read-write + + + + + HCINTMSK7 + 0x5EC + 0x20 + + + H_XFERCOMPLMSK7 + 0 + 1 + read-write + + + H_CHHLTDMSK7 + 1 + 1 + read-write + + + H_AHBERRMSK7 + 2 + 1 + read-write + + + H_STALLMSK7 + 3 + 1 + read-write + + + H_NAKMSK7 + 4 + 1 + read-write + + + H_ACKMSK7 + 5 + 1 + read-write + + + H_NYETMSK7 + 6 + 1 + read-write + + + H_XACTERRMSK7 + 7 + 1 + read-write + + + H_BBLERRMSK7 + 8 + 1 + read-write + + + H_FRMOVRUNMSK7 + 9 + 1 + read-write + + + H_DATATGLERRMSK7 + 10 + 1 + read-write + + + H_BNAINTRMSK7 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK7 + 13 + 1 + read-write + + + + + HCTSIZ7 + 0x5F0 + 0x20 + + + H_XFERSIZE7 + 0 + 19 + read-write + + + H_PKTCNT7 + 19 + 10 + read-write + + + H_PID7 + 29 + 2 + read-write + + + H_DOPNG7 + 31 + 1 + read-write + + + + + HCDMA7 + 0x5F4 + 0x20 + + + H_DMAADDR7 + 0 + 32 + read-write + + + + + HCDMAB7 + 0x5FC + 0x20 + + + H_HCDMAB7 + 0 + 32 + read-only + + + + + DCFG + 0x800 + 0x20 + 0x08100000 + + + NZSTSOUTHSHK + 2 + 1 + read-write + + + ENA32KHZSUSP + 3 + 1 + read-write + + + DEVADDR + 4 + 7 + read-write + + + PERFRLINT + 11 + 2 + read-write + + + ENDEVOUTNAK + 13 + 1 + read-write + + + XCVRDLY + 14 + 1 + read-write + + + ERRATICINTMSK + 15 + 1 + read-write + + + EPMISCNT + 18 + 5 + read-write + + + DESCDMA + 23 + 1 + read-write + + + PERSCHINTVL + 24 + 2 + read-write + + + RESVALID + 26 + 6 + read-write + + + + + DCTL + 0x804 + 0x20 + 0x00002000 + + + RMTWKUPSIG + 0 + 1 + read-write + + + SFTDISCON + 1 + 1 + read-write + + + GNPINNAKSTS + 2 + 1 + read-only + + + GOUTNAKSTS + 3 + 1 + read-only + + + TSTCTL + 4 + 3 + read-write + + + SGNPINNAK + 7 + 1 + write-only + + + CGNPINNAK + 8 + 1 + write-only + + + SGOUTNAK + 9 + 1 + write-only + + + CGOUTNAK + 10 + 1 + write-only + + + PWRONPRGDONE + 11 + 1 + read-write + + + GMC + 13 + 2 + read-write + + + IGNRFRMNUM + 15 + 1 + read-write + + + NAKONBBLE + 16 + 1 + read-write + + + ENCOUNTONBNA + 17 + 1 + read-write + + + DEEPSLEEPBESLREJECT + 18 + 1 + read-write + + + + + DSTS + 0x808 + 0x20 + 0x00000002 + + + SUSPSTS + 0 + 1 + read-only + + + ENUMSPD + 1 + 2 + read-only + + + ERRTICERR + 3 + 1 + read-only + + + SOFFN + 8 + 14 + read-only + + + DEVLNSTS + 22 + 2 + read-only + + + + + DIEPMSK + 0x810 + 0x20 + + + DI_XFERCOMPLMSK + 0 + 1 + read-write + + + DI_EPDISBLDMSK + 1 + 1 + read-write + + + DI_AHBERMSK + 2 + 1 + read-write + + + TIMEOUTMSK + 3 + 1 + read-write + + + INTKNTXFEMPMSK + 4 + 1 + read-write + + + INTKNEPMISMSK + 5 + 1 + read-write + + + INEPNAKEFFMSK + 6 + 1 + read-write + + + TXFIFOUNDRNMSK + 8 + 1 + read-write + + + BNAININTRMSK + 9 + 1 + read-write + + + DI_NAKMSK + 13 + 1 + read-write + + + + + DOEPMSK + 0x814 + 0x20 + + + XFERCOMPLMSK + 0 + 1 + read-write + + + EPDISBLDMSK + 1 + 1 + read-write + + + AHBERMSK + 2 + 1 + read-write + + + SETUPMSK + 3 + 1 + read-write + + + OUTTKNEPDISMSK + 4 + 1 + read-write + + + STSPHSERCVDMSK + 5 + 1 + read-write + + + BACK2BACKSETUP + 6 + 1 + read-write + + + OUTPKTERRMSK + 8 + 1 + read-write + + + BNAOUTINTRMSK + 9 + 1 + read-write + + + BBLEERRMSK + 12 + 1 + read-write + + + NAKMSK + 13 + 1 + read-write + + + NYETMSK + 14 + 1 + read-write + + + + + DAINT + 0x818 + 0x20 + + + INEPINT0 + 0 + 1 + read-only + + + INEPINT1 + 1 + 1 + read-only + + + INEPINT2 + 2 + 1 + read-only + + + INEPINT3 + 3 + 1 + read-only + + + INEPINT4 + 4 + 1 + read-only + + + INEPINT5 + 5 + 1 + read-only + + + INEPINT6 + 6 + 1 + read-only + + + OUTEPINT0 + 16 + 1 + read-only + + + OUTEPINT1 + 17 + 1 + read-only + + + OUTEPINT2 + 18 + 1 + read-only + + + OUTEPINT3 + 19 + 1 + read-only + + + OUTEPINT4 + 20 + 1 + read-only + + + OUTEPINT5 + 21 + 1 + read-only + + + OUTEPINT6 + 22 + 1 + read-only + + + + + DAINTMSK + 0x81C + 0x20 + + + INEPMSK0 + 0 + 1 + read-write + + + INEPMSK1 + 1 + 1 + read-write + + + INEPMSK2 + 2 + 1 + read-write + + + INEPMSK3 + 3 + 1 + read-write + + + INEPMSK4 + 4 + 1 + read-write + + + INEPMSK5 + 5 + 1 + read-write + + + INEPMSK6 + 6 + 1 + read-write + + + OUTEPMSK0 + 16 + 1 + read-write + + + OUTEPMSK1 + 17 + 1 + read-write + + + OUTEPMSK2 + 18 + 1 + read-write + + + OUTEPMSK3 + 19 + 1 + read-write + + + OUTEPMSK4 + 20 + 1 + read-write + + + OUTEPMSK5 + 21 + 1 + read-write + + + OUTEPMSK6 + 22 + 1 + read-write + + + + + DVBUSDIS + 0x828 + 0x20 + 0x000017D7 + + + DVBUSDIS + 0 + 16 + read-write + + + + + DVBUSPULSE + 0x82C + 0x20 + 0x000005B8 + + + DVBUSPULSE + 0 + 12 + read-write + + + + + DTHRCTL + 0x830 + 0x20 + 0x08020020 + + + NONISOTHREN + 0 + 1 + read-write + + + ISOTHREN + 1 + 1 + read-write + + + TXTHRLEN + 2 + 9 + read-write + + + AHBTHRRATIO + 11 + 2 + read-write + + + RXTHREN + 16 + 1 + read-write + + + RXTHRLEN + 17 + 9 + read-write + + + ARBPRKEN + 27 + 1 + read-write + + + + + DIEPEMPMSK + 0x834 + 0x20 + + + D_INEPTXFEMPMSK + 0 + 16 + read-write + + + + + DIEPCTL0 + 0x900 + 0x20 + 0x00008000 + + + D_MPS0 + 0 + 2 + read-write + + + D_USBACTEP0 + 15 + 1 + read-only + + + D_NAKSTS0 + 17 + 1 + read-only + + + D_EPTYPE0 + 18 + 2 + read-only + + + D_STALL0 + 21 + 1 + read-write + + + D_TXFNUM0 + 22 + 4 + read-write + + + D_CNAK0 + 26 + 1 + write-only + + + DI_SNAK0 + 27 + 1 + write-only + + + D_EPDIS0 + 30 + 1 + read-write + + + D_EPENA0 + 31 + 1 + read-write + + + + + DIEPINT0 + 0x908 + 0x20 + + + D_XFERCOMPL0 + 0 + 1 + read-write + + + D_EPDISBLD0 + 1 + 1 + read-write + + + D_AHBERR0 + 2 + 1 + read-write + + + D_TIMEOUT0 + 3 + 1 + read-write + + + D_INTKNTXFEMP0 + 4 + 1 + read-write + + + D_INTKNEPMIS0 + 5 + 1 + read-write + + + D_INEPNAKEFF0 + 6 + 1 + read-write + + + D_TXFEMP0 + 7 + 1 + read-only + + + D_TXFIFOUNDRN0 + 8 + 1 + read-write + + + D_BNAINTR0 + 9 + 1 + read-write + + + D_PKTDRPSTS0 + 11 + 1 + read-write + + + D_BBLEERR0 + 12 + 1 + read-write + + + D_NAKINTRPT0 + 13 + 1 + read-write + + + D_NYETINTRPT0 + 14 + 1 + read-write + + + + + DIEPTSIZ0 + 0x910 + 0x20 + + + D_XFERSIZE0 + 0 + 7 + read-write + + + D_PKTCNT0 + 19 + 2 + read-write + + + + + DIEPDMA0 + 0x914 + 0x20 + + + D_DMAADDR0 + 0 + 32 + read-write + + + + + DTXFSTS0 + 0x918 + 0x20 + + + D_INEPTXFSPCAVAIL0 + 0 + 16 + read-only + + + + + DIEPDMAB0 + 0x91C + 0x20 + + + D_DMABUFFERADDR0 + 0 + 32 + read-only + + + + + DIEPCTL1 + 0x920 + 0x20 + 0x00008000 + + + D_MPS1 + 0 + 2 + read-write + + + D_USBACTEP1 + 15 + 1 + read-only + + + D_NAKSTS1 + 17 + 1 + read-only + + + D_EPTYPE1 + 18 + 2 + read-only + + + D_STALL1 + 21 + 1 + read-write + + + D_TXFNUM1 + 22 + 4 + read-write + + + D_CNAK1 + 26 + 1 + write-only + + + DI_SNAK1 + 27 + 1 + write-only + + + DI_SETD0PID1 + 28 + 1 + write-only + + + DI_SETD1PID1 + 29 + 1 + write-only + + + D_EPDIS1 + 30 + 1 + read-write + + + D_EPENA1 + 31 + 1 + read-write + + + + + DIEPINT1 + 0x928 + 0x20 + + + D_XFERCOMPL1 + 0 + 1 + read-write + + + D_EPDISBLD1 + 1 + 1 + read-write + + + D_AHBERR1 + 2 + 1 + read-write + + + D_TIMEOUT1 + 3 + 1 + read-write + + + D_INTKNTXFEMP1 + 4 + 1 + read-write + + + D_INTKNEPMIS1 + 5 + 1 + read-write + + + D_INEPNAKEFF1 + 6 + 1 + read-write + + + D_TXFEMP1 + 7 + 1 + read-only + + + D_TXFIFOUNDRN1 + 8 + 1 + read-write + + + D_BNAINTR1 + 9 + 1 + read-write + + + D_PKTDRPSTS1 + 11 + 1 + read-write + + + D_BBLEERR1 + 12 + 1 + read-write + + + D_NAKINTRPT1 + 13 + 1 + read-write + + + D_NYETINTRPT1 + 14 + 1 + read-write + + + + + DIEPTSIZ1 + 0x930 + 0x20 + + + D_XFERSIZE1 + 0 + 7 + read-write + + + D_PKTCNT1 + 19 + 2 + read-write + + + + + DIEPDMA1 + 0x934 + 0x20 + + + D_DMAADDR1 + 0 + 32 + read-write + + + + + DTXFSTS1 + 0x938 + 0x20 + + + D_INEPTXFSPCAVAIL1 + 0 + 16 + read-only + + + + + DIEPDMAB1 + 0x93C + 0x20 + + + D_DMABUFFERADDR1 + 0 + 32 + read-only + + + + + DIEPCTL2 + 0x940 + 0x20 + 0x00008000 + + + D_MPS2 + 0 + 2 + read-write + + + D_USBACTEP2 + 15 + 1 + read-only + + + D_NAKSTS2 + 17 + 1 + read-only + + + D_EPTYPE2 + 18 + 2 + read-only + + + D_STALL2 + 21 + 1 + read-write + + + D_TXFNUM2 + 22 + 4 + read-write + + + D_CNAK2 + 26 + 1 + write-only + + + DI_SNAK2 + 27 + 1 + write-only + + + DI_SETD0PID2 + 28 + 1 + write-only + + + DI_SETD1PID2 + 29 + 1 + write-only + + + D_EPDIS2 + 30 + 1 + read-write + + + D_EPENA2 + 31 + 1 + read-write + + + + + DIEPINT2 + 0x948 + 0x20 + + + D_XFERCOMPL2 + 0 + 1 + read-write + + + D_EPDISBLD2 + 1 + 1 + read-write + + + D_AHBERR2 + 2 + 1 + read-write + + + D_TIMEOUT2 + 3 + 1 + read-write + + + D_INTKNTXFEMP2 + 4 + 1 + read-write + + + D_INTKNEPMIS2 + 5 + 1 + read-write + + + D_INEPNAKEFF2 + 6 + 1 + read-write + + + D_TXFEMP2 + 7 + 1 + read-only + + + D_TXFIFOUNDRN2 + 8 + 1 + read-write + + + D_BNAINTR2 + 9 + 1 + read-write + + + D_PKTDRPSTS2 + 11 + 1 + read-write + + + D_BBLEERR2 + 12 + 1 + read-write + + + D_NAKINTRPT2 + 13 + 1 + read-write + + + D_NYETINTRPT2 + 14 + 1 + read-write + + + + + DIEPTSIZ2 + 0x950 + 0x20 + + + D_XFERSIZE2 + 0 + 7 + read-write + + + D_PKTCNT2 + 19 + 2 + read-write + + + + + DIEPDMA2 + 0x954 + 0x20 + + + D_DMAADDR2 + 0 + 32 + read-write + + + + + DTXFSTS2 + 0x958 + 0x20 + + + D_INEPTXFSPCAVAIL2 + 0 + 16 + read-only + + + + + DIEPDMAB2 + 0x95C + 0x20 + + + D_DMABUFFERADDR2 + 0 + 32 + read-only + + + + + DIEPCTL3 + 0x960 + 0x20 + 0x00008000 + + + DI_MPS3 + 0 + 2 + read-write + + + DI_USBACTEP3 + 15 + 1 + read-only + + + DI_NAKSTS3 + 17 + 1 + read-only + + + DI_EPTYPE3 + 18 + 2 + read-only + + + DI_STALL3 + 21 + 1 + read-write + + + DI_TXFNUM3 + 22 + 4 + read-write + + + DI_CNAK3 + 26 + 1 + write-only + + + DI_SNAK3 + 27 + 1 + write-only + + + DI_SETD0PID3 + 28 + 1 + write-only + + + DI_SETD1PID3 + 29 + 1 + write-only + + + DI_EPDIS3 + 30 + 1 + read-write + + + DI_EPENA3 + 31 + 1 + read-write + + + + + DIEPINT3 + 0x968 + 0x20 + + + D_XFERCOMPL3 + 0 + 1 + read-write + + + D_EPDISBLD3 + 1 + 1 + read-write + + + D_AHBERR3 + 2 + 1 + read-write + + + D_TIMEOUT3 + 3 + 1 + read-write + + + D_INTKNTXFEMP3 + 4 + 1 + read-write + + + D_INTKNEPMIS3 + 5 + 1 + read-write + + + D_INEPNAKEFF3 + 6 + 1 + read-write + + + D_TXFEMP3 + 7 + 1 + read-only + + + D_TXFIFOUNDRN3 + 8 + 1 + read-write + + + D_BNAINTR3 + 9 + 1 + read-write + + + D_PKTDRPSTS3 + 11 + 1 + read-write + + + D_BBLEERR3 + 12 + 1 + read-write + + + D_NAKINTRPT3 + 13 + 1 + read-write + + + D_NYETINTRPT3 + 14 + 1 + read-write + + + + + DIEPTSIZ3 + 0x970 + 0x20 + + + D_XFERSIZE3 + 0 + 7 + read-write + + + D_PKTCNT3 + 19 + 2 + read-write + + + + + DIEPDMA3 + 0x974 + 0x20 + + + D_DMAADDR3 + 0 + 32 + read-write + + + + + DTXFSTS3 + 0x978 + 0x20 + + + D_INEPTXFSPCAVAIL3 + 0 + 16 + read-only + + + + + DIEPDMAB3 + 0x97C + 0x20 + + + D_DMABUFFERADDR3 + 0 + 32 + read-only + + + + + DIEPCTL4 + 0x980 + 0x20 + 0x00008000 + + + D_MPS4 + 0 + 2 + read-write + + + D_USBACTEP4 + 15 + 1 + read-only + + + D_NAKSTS4 + 17 + 1 + read-only + + + D_EPTYPE4 + 18 + 2 + read-only + + + D_STALL4 + 21 + 1 + read-write + + + D_TXFNUM4 + 22 + 4 + read-write + + + D_CNAK4 + 26 + 1 + write-only + + + DI_SNAK4 + 27 + 1 + write-only + + + DI_SETD0PID4 + 28 + 1 + write-only + + + DI_SETD1PID4 + 29 + 1 + write-only + + + D_EPDIS4 + 30 + 1 + read-write + + + D_EPENA4 + 31 + 1 + read-write + + + + + DIEPINT4 + 0x988 + 0x20 + + + D_XFERCOMPL4 + 0 + 1 + read-write + + + D_EPDISBLD4 + 1 + 1 + read-write + + + D_AHBERR4 + 2 + 1 + read-write + + + D_TIMEOUT4 + 3 + 1 + read-write + + + D_INTKNTXFEMP4 + 4 + 1 + read-write + + + D_INTKNEPMIS4 + 5 + 1 + read-write + + + D_INEPNAKEFF4 + 6 + 1 + read-write + + + D_TXFEMP4 + 7 + 1 + read-only + + + D_TXFIFOUNDRN4 + 8 + 1 + read-write + + + D_BNAINTR4 + 9 + 1 + read-write + + + D_PKTDRPSTS4 + 11 + 1 + read-write + + + D_BBLEERR4 + 12 + 1 + read-write + + + D_NAKINTRPT4 + 13 + 1 + read-write + + + D_NYETINTRPT4 + 14 + 1 + read-write + + + + + DIEPTSIZ4 + 0x990 + 0x20 + + + D_XFERSIZE4 + 0 + 7 + read-write + + + D_PKTCNT4 + 19 + 2 + read-write + + + + + DIEPDMA4 + 0x994 + 0x20 + + + D_DMAADDR4 + 0 + 32 + read-write + + + + + DTXFSTS4 + 0x998 + 0x20 + + + D_INEPTXFSPCAVAIL4 + 0 + 16 + read-only + + + + + DIEPDMAB4 + 0x99C + 0x20 + + + D_DMABUFFERADDR4 + 0 + 32 + read-only + + + + + DIEPCTL5 + 0x9A0 + 0x20 + 0x00008000 + + + DI_MPS5 + 0 + 2 + read-write + + + DI_USBACTEP5 + 15 + 1 + read-only + + + DI_NAKSTS5 + 17 + 1 + read-only + + + DI_EPTYPE5 + 18 + 2 + read-only + + + DI_STALL5 + 21 + 1 + read-write + + + DI_TXFNUM5 + 22 + 4 + read-write + + + DI_CNAK5 + 26 + 1 + write-only + + + DI_SNAK5 + 27 + 1 + write-only + + + DI_SETD0PID5 + 28 + 1 + write-only + + + DI_SETD1PID5 + 29 + 1 + write-only + + + DI_EPDIS5 + 30 + 1 + read-write + + + DI_EPENA5 + 31 + 1 + read-write + + + + + DIEPINT5 + 0x9A8 + 0x20 + + + D_XFERCOMPL5 + 0 + 1 + read-write + + + D_EPDISBLD5 + 1 + 1 + read-write + + + D_AHBERR5 + 2 + 1 + read-write + + + D_TIMEOUT5 + 3 + 1 + read-write + + + D_INTKNTXFEMP5 + 4 + 1 + read-write + + + D_INTKNEPMIS5 + 5 + 1 + read-write + + + D_INEPNAKEFF5 + 6 + 1 + read-write + + + D_TXFEMP5 + 7 + 1 + read-only + + + D_TXFIFOUNDRN5 + 8 + 1 + read-write + + + D_BNAINTR5 + 9 + 1 + read-write + + + D_PKTDRPSTS5 + 11 + 1 + read-write + + + D_BBLEERR5 + 12 + 1 + read-write + + + D_NAKINTRPT5 + 13 + 1 + read-write + + + D_NYETINTRPT5 + 14 + 1 + read-write + + + + + DIEPTSIZ5 + 0x9B0 + 0x20 + + + D_XFERSIZE5 + 0 + 7 + read-write + + + D_PKTCNT5 + 19 + 2 + read-write + + + + + DIEPDMA5 + 0x9B4 + 0x20 + + + D_DMAADDR5 + 0 + 32 + read-write + + + + + DTXFSTS5 + 0x9B8 + 0x20 + + + D_INEPTXFSPCAVAIL5 + 0 + 16 + read-only + + + + + DIEPDMAB5 + 0x9BC + 0x20 + + + D_DMABUFFERADDR5 + 0 + 32 + read-only + + + + + DIEPCTL6 + 0x9C0 + 0x20 + 0x00008000 + + + D_MPS6 + 0 + 2 + read-write + + + D_USBACTEP6 + 15 + 1 + read-only + + + D_NAKSTS6 + 17 + 1 + read-only + + + D_EPTYPE6 + 18 + 2 + read-only + + + D_STALL6 + 21 + 1 + read-write + + + D_TXFNUM6 + 22 + 4 + read-write + + + D_CNAK6 + 26 + 1 + write-only + + + DI_SNAK6 + 27 + 1 + write-only + + + DI_SETD0PID6 + 28 + 1 + write-only + + + DI_SETD1PID6 + 29 + 1 + write-only + + + D_EPDIS6 + 30 + 1 + read-write + + + D_EPENA6 + 31 + 1 + read-write + + + + + DIEPINT6 + 0x9C8 + 0x20 + + + D_XFERCOMPL6 + 0 + 1 + read-write + + + D_EPDISBLD6 + 1 + 1 + read-write + + + D_AHBERR6 + 2 + 1 + read-write + + + D_TIMEOUT6 + 3 + 1 + read-write + + + D_INTKNTXFEMP6 + 4 + 1 + read-write + + + D_INTKNEPMIS6 + 5 + 1 + read-write + + + D_INEPNAKEFF6 + 6 + 1 + read-write + + + D_TXFEMP6 + 7 + 1 + read-only + + + D_TXFIFOUNDRN6 + 8 + 1 + read-write + + + D_BNAINTR6 + 9 + 1 + read-write + + + D_PKTDRPSTS6 + 11 + 1 + read-write + + + D_BBLEERR6 + 12 + 1 + read-write + + + D_NAKINTRPT6 + 13 + 1 + read-write + + + D_NYETINTRPT6 + 14 + 1 + read-write + + + + + DIEPTSIZ6 + 0x9D0 + 0x20 + + + D_XFERSIZE6 + 0 + 7 + read-write + + + D_PKTCNT6 + 19 + 2 + read-write + + + + + DIEPDMA6 + 0x9D4 + 0x20 + + + D_DMAADDR6 + 0 + 32 + read-write + + + + + DTXFSTS6 + 0x9D8 + 0x20 + + + D_INEPTXFSPCAVAIL6 + 0 + 16 + read-only + + + + + DIEPDMAB6 + 0x9DC + 0x20 + + + D_DMABUFFERADDR6 + 0 + 32 + read-only + + + + + DOEPCTL0 + 0xB00 + 0x20 + 0x00008000 + + + MPS0 + 0 + 2 + read-only + + + USBACTEP0 + 15 + 1 + read-only + + + NAKSTS0 + 17 + 1 + read-only + + + EPTYPE0 + 18 + 2 + read-only + + + SNP0 + 20 + 1 + read-write + + + STALL0 + 21 + 1 + read-write + + + CNAK0 + 26 + 1 + write-only + + + DO_SNAK0 + 27 + 1 + write-only + + + EPDIS0 + 30 + 1 + read-only + + + EPENA0 + 31 + 1 + read-write + + + + + DOEPINT0 + 0xB08 + 0x20 + + + XFERCOMPL0 + 0 + 1 + read-write + + + EPDISBLD0 + 1 + 1 + read-write + + + AHBERR0 + 2 + 1 + read-write + + + SETUP0 + 3 + 1 + read-write + + + OUTTKNEPDIS0 + 4 + 1 + read-write + + + STSPHSERCVD0 + 5 + 1 + read-write + + + BACK2BACKSETUP0 + 6 + 1 + read-write + + + OUTPKTERR0 + 8 + 1 + read-write + + + BNAINTR0 + 9 + 1 + read-write + + + PKTDRPSTS0 + 11 + 1 + read-write + + + BBLEERR0 + 12 + 1 + read-write + + + NAKINTRPT0 + 13 + 1 + read-write + + + NYEPINTRPT0 + 14 + 1 + read-write + + + STUPPKTRCVD0 + 15 + 1 + read-write + + + + + DOEPTSIZ0 + 0xB10 + 0x20 + + + XFERSIZE0 + 0 + 7 + read-write + + + PKTCNT0 + 19 + 1 + read-write + + + SUPCNT0 + 29 + 2 + read-write + + + + + DOEPDMA0 + 0xB14 + 0x20 + + + DMAADDR0 + 0 + 32 + read-write + + + + + DOEPDMAB0 + 0xB1C + 0x20 + + + DMABUFFERADDR0 + 0 + 32 + read-write + + + + + DOEPCTL1 + 0xB20 + 0x20 + 0x00008000 + + + MPS1 + 0 + 11 + read-only + + + USBACTEP1 + 15 + 1 + read-only + + + NAKSTS1 + 17 + 1 + read-only + + + EPTYPE1 + 18 + 2 + read-only + + + SNP1 + 20 + 1 + read-write + + + STALL1 + 21 + 1 + read-write + + + CNAK1 + 26 + 1 + write-only + + + DO_SNAK1 + 27 + 1 + write-only + + + DO_SETD0PID1 + 28 + 1 + write-only + + + DO_SETD1PID1 + 29 + 1 + write-only + + + EPDIS1 + 30 + 1 + read-only + + + EPENA1 + 31 + 1 + read-write + + + + + DOEPINT1 + 0xB28 + 0x20 + + + XFERCOMPL1 + 0 + 1 + read-write + + + EPDISBLD1 + 1 + 1 + read-write + + + AHBERR1 + 2 + 1 + read-write + + + SETUP1 + 3 + 1 + read-write + + + OUTTKNEPDIS1 + 4 + 1 + read-write + + + STSPHSERCVD1 + 5 + 1 + read-write + + + BACK2BACKSETUP1 + 6 + 1 + read-write + + + OUTPKTERR1 + 8 + 1 + read-write + + + BNAINTR1 + 9 + 1 + read-write + + + PKTDRPSTS1 + 11 + 1 + read-write + + + BBLEERR1 + 12 + 1 + read-write + + + NAKINTRPT1 + 13 + 1 + read-write + + + NYEPINTRPT1 + 14 + 1 + read-write + + + STUPPKTRCVD1 + 15 + 1 + read-write + + + + + DOEPTSIZ1 + 0xB30 + 0x20 + + + XFERSIZE1 + 0 + 7 + read-write + + + PKTCNT1 + 19 + 1 + read-write + + + SUPCNT1 + 29 + 2 + read-write + + + + + DOEPDMA1 + 0xB34 + 0x20 + + + DMAADDR1 + 0 + 32 + read-write + + + + + DOEPDMAB1 + 0xB3C + 0x20 + + + DMABUFFERADDR1 + 0 + 32 + read-write + + + + + DOEPCTL2 + 0xB40 + 0x20 + 0x00008000 + + + MPS2 + 0 + 11 + read-only + + + USBACTEP2 + 15 + 1 + read-only + + + NAKSTS2 + 17 + 1 + read-only + + + EPTYPE2 + 18 + 2 + read-only + + + SNP2 + 20 + 1 + read-write + + + STALL2 + 21 + 1 + read-write + + + CNAK2 + 26 + 1 + write-only + + + DO_SNAK2 + 27 + 1 + write-only + + + DO_SETD0PID2 + 28 + 1 + write-only + + + DO_SETD1PID2 + 29 + 1 + write-only + + + EPDIS2 + 30 + 1 + read-only + + + EPENA2 + 31 + 1 + read-write + + + + + DOEPINT2 + 0xB48 + 0x20 + + + XFERCOMPL2 + 0 + 1 + read-write + + + EPDISBLD2 + 1 + 1 + read-write + + + AHBERR2 + 2 + 1 + read-write + + + SETUP2 + 3 + 1 + read-write + + + OUTTKNEPDIS2 + 4 + 1 + read-write + + + STSPHSERCVD2 + 5 + 1 + read-write + + + BACK2BACKSETUP2 + 6 + 1 + read-write + + + OUTPKTERR2 + 8 + 1 + read-write + + + BNAINTR2 + 9 + 1 + read-write + + + PKTDRPSTS2 + 11 + 1 + read-write + + + BBLEERR2 + 12 + 1 + read-write + + + NAKINTRPT2 + 13 + 1 + read-write + + + NYEPINTRPT2 + 14 + 1 + read-write + + + STUPPKTRCVD2 + 15 + 1 + read-write + + + + + DOEPTSIZ2 + 0xB50 + 0x20 + + + XFERSIZE2 + 0 + 7 + read-write + + + PKTCNT2 + 19 + 1 + read-write + + + SUPCNT2 + 29 + 2 + read-write + + + + + DOEPDMA2 + 0xB54 + 0x20 + + + DMAADDR2 + 0 + 32 + read-write + + + + + DOEPDMAB2 + 0xB5C + 0x20 + + + DMABUFFERADDR2 + 0 + 32 + read-write + + + + + DOEPCTL3 + 0xB60 + 0x20 + 0x00008000 + + + MPS3 + 0 + 11 + read-only + + + USBACTEP3 + 15 + 1 + read-only + + + NAKSTS3 + 17 + 1 + read-only + + + EPTYPE3 + 18 + 2 + read-only + + + SNP3 + 20 + 1 + read-write + + + STALL3 + 21 + 1 + read-write + + + CNAK3 + 26 + 1 + write-only + + + DO_SNAK3 + 27 + 1 + write-only + + + DO_SETD0PID3 + 28 + 1 + write-only + + + DO_SETD1PID3 + 29 + 1 + write-only + + + EPDIS3 + 30 + 1 + read-only + + + EPENA3 + 31 + 1 + read-write + + + + + DOEPINT3 + 0xB68 + 0x20 + + + XFERCOMPL3 + 0 + 1 + read-write + + + EPDISBLD3 + 1 + 1 + read-write + + + AHBERR3 + 2 + 1 + read-write + + + SETUP3 + 3 + 1 + read-write + + + OUTTKNEPDIS3 + 4 + 1 + read-write + + + STSPHSERCVD3 + 5 + 1 + read-write + + + BACK2BACKSETUP3 + 6 + 1 + read-write + + + OUTPKTERR3 + 8 + 1 + read-write + + + BNAINTR3 + 9 + 1 + read-write + + + PKTDRPSTS3 + 11 + 1 + read-write + + + BBLEERR3 + 12 + 1 + read-write + + + NAKINTRPT3 + 13 + 1 + read-write + + + NYEPINTRPT3 + 14 + 1 + read-write + + + STUPPKTRCVD3 + 15 + 1 + read-write + + + + + DOEPTSIZ3 + 0xB70 + 0x20 + + + XFERSIZE3 + 0 + 7 + read-write + + + PKTCNT3 + 19 + 1 + read-write + + + SUPCNT3 + 29 + 2 + read-write + + + + + DOEPDMA3 + 0xB74 + 0x20 + + + DMAADDR3 + 0 + 32 + read-write + + + + + DOEPDMAB3 + 0xB7C + 0x20 + + + DMABUFFERADDR3 + 0 + 32 + read-write + + + + + DOEPCTL4 + 0xB80 + 0x20 + 0x00008000 + + + MPS4 + 0 + 11 + read-only + + + USBACTEP4 + 15 + 1 + read-only + + + NAKSTS4 + 17 + 1 + read-only + + + EPTYPE4 + 18 + 2 + read-only + + + SNP4 + 20 + 1 + read-write + + + STALL4 + 21 + 1 + read-write + + + CNAK4 + 26 + 1 + write-only + + + DO_SNAK4 + 27 + 1 + write-only + + + DO_SETD0PID4 + 28 + 1 + write-only + + + DO_SETD1PID4 + 29 + 1 + write-only + + + EPDIS4 + 30 + 1 + read-only + + + EPENA4 + 31 + 1 + read-write + + + + + DOEPINT4 + 0xB88 + 0x20 + + + XFERCOMPL4 + 0 + 1 + read-write + + + EPDISBLD4 + 1 + 1 + read-write + + + AHBERR4 + 2 + 1 + read-write + + + SETUP4 + 3 + 1 + read-write + + + OUTTKNEPDIS4 + 4 + 1 + read-write + + + STSPHSERCVD4 + 5 + 1 + read-write + + + BACK2BACKSETUP4 + 6 + 1 + read-write + + + OUTPKTERR4 + 8 + 1 + read-write + + + BNAINTR4 + 9 + 1 + read-write + + + PKTDRPSTS4 + 11 + 1 + read-write + + + BBLEERR4 + 12 + 1 + read-write + + + NAKINTRPT4 + 13 + 1 + read-write + + + NYEPINTRPT4 + 14 + 1 + read-write + + + STUPPKTRCVD4 + 15 + 1 + read-write + + + + + DOEPTSIZ4 + 0xB90 + 0x20 + + + XFERSIZE4 + 0 + 7 + read-write + + + PKTCNT4 + 19 + 1 + read-write + + + SUPCNT4 + 29 + 2 + read-write + + + + + DOEPDMA4 + 0xB94 + 0x20 + + + DMAADDR4 + 0 + 32 + read-write + + + + + DOEPDMAB4 + 0xB9C + 0x20 + + + DMABUFFERADDR4 + 0 + 32 + read-write + + + + + DOEPCTL5 + 0xBA0 + 0x20 + 0x00008000 + + + MPS5 + 0 + 11 + read-only + + + USBACTEP5 + 15 + 1 + read-only + + + NAKSTS5 + 17 + 1 + read-only + + + EPTYPE5 + 18 + 2 + read-only + + + SNP5 + 20 + 1 + read-write + + + STALL5 + 21 + 1 + read-write + + + CNAK5 + 26 + 1 + write-only + + + DO_SNAK5 + 27 + 1 + write-only + + + DO_SETD0PID5 + 28 + 1 + write-only + + + DO_SETD1PID5 + 29 + 1 + write-only + + + EPDIS5 + 30 + 1 + read-only + + + EPENA5 + 31 + 1 + read-write + + + + + DOEPINT5 + 0xBA8 + 0x20 + + + XFERCOMPL5 + 0 + 1 + read-write + + + EPDISBLD5 + 1 + 1 + read-write + + + AHBERR5 + 2 + 1 + read-write + + + SETUP5 + 3 + 1 + read-write + + + OUTTKNEPDIS5 + 4 + 1 + read-write + + + STSPHSERCVD5 + 5 + 1 + read-write + + + BACK2BACKSETUP5 + 6 + 1 + read-write + + + OUTPKTERR5 + 8 + 1 + read-write + + + BNAINTR5 + 9 + 1 + read-write + + + PKTDRPSTS5 + 11 + 1 + read-write + + + BBLEERR5 + 12 + 1 + read-write + + + NAKINTRPT5 + 13 + 1 + read-write + + + NYEPINTRPT5 + 14 + 1 + read-write + + + STUPPKTRCVD5 + 15 + 1 + read-write + + + + + DOEPTSIZ5 + 0xBB0 + 0x20 + + + XFERSIZE5 + 0 + 7 + read-write + + + PKTCNT5 + 19 + 1 + read-write + + + SUPCNT5 + 29 + 2 + read-write + + + + + DOEPDMA5 + 0xBB4 + 0x20 + + + DMAADDR5 + 0 + 32 + read-write + + + + + DOEPDMAB5 + 0xBBC + 0x20 + + + DMABUFFERADDR5 + 0 + 32 + read-write + + + + + DOEPCTL6 + 0xBC0 + 0x20 + 0x00008000 + + + MPS6 + 0 + 11 + read-only + + + USBACTEP6 + 15 + 1 + read-only + + + NAKSTS6 + 17 + 1 + read-only + + + EPTYPE6 + 18 + 2 + read-only + + + SNP6 + 20 + 1 + read-write + + + STALL6 + 21 + 1 + read-write + + + CNAK6 + 26 + 1 + write-only + + + DO_SNAK6 + 27 + 1 + write-only + + + DO_SETD0PID6 + 28 + 1 + write-only + + + DO_SETD1PID6 + 29 + 1 + write-only + + + EPDIS6 + 30 + 1 + read-only + + + EPENA6 + 31 + 1 + read-write + + + + + DOEPINT6 + 0xBC8 + 0x20 + + + XFERCOMPL6 + 0 + 1 + read-write + + + EPDISBLD6 + 1 + 1 + read-write + + + AHBERR6 + 2 + 1 + read-write + + + SETUP6 + 3 + 1 + read-write + + + OUTTKNEPDIS6 + 4 + 1 + read-write + + + STSPHSERCVD6 + 5 + 1 + read-write + + + BACK2BACKSETUP6 + 6 + 1 + read-write + + + OUTPKTERR6 + 8 + 1 + read-write + + + BNAINTR6 + 9 + 1 + read-write + + + PKTDRPSTS6 + 11 + 1 + read-write + + + BBLEERR6 + 12 + 1 + read-write + + + NAKINTRPT6 + 13 + 1 + read-write + + + NYEPINTRPT6 + 14 + 1 + read-write + + + STUPPKTRCVD6 + 15 + 1 + read-write + + + + + DOEPTSIZ6 + 0xBD0 + 0x20 + + + XFERSIZE6 + 0 + 7 + read-write + + + PKTCNT6 + 19 + 1 + read-write + + + SUPCNT6 + 29 + 2 + read-write + + + + + DOEPDMA6 + 0xBD4 + 0x20 + + + DMAADDR6 + 0 + 32 + read-write + + + + + DOEPDMAB6 + 0xBDC + 0x20 + + + DMABUFFERADDR6 + 0 + 32 + read-write + + + + + PCGCCTL + 0xE00 + 0x20 + + + STOPPCLK + 0 + 1 + read-write + + + GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + 2 + 1 + read-write + + + RSTPDWNMODULE + 3 + 1 + read-write + + + PHYSLEEP + 6 + 1 + read-only + + + L1SUSPENDED + 7 + 1 + read-only + + + RESETAFTERSUSP + 8 + 1 + read-write + + + + + + + USB_WRAP + USB_WRAP Peripheral + USB_WRAP + 0x3F439000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB OTG Wrapper Configure Register + 0x0 + 0x20 + 0x001C0000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers + 31 + 1 + read-write + + + + + TEST_CONF + USB Internal PHY Testing Register + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + DATE + Version Control Register + 0x3FC + 0x20 + 0x02102010 + + + USB_WRAP_DATE + Date register + 0 + 32 + read-write + + + + + XTS_AES XTS-AES-128 Flash Encryption @@ -38142,7 +46520,7 @@ If this bit is set to 0, UHCI decoder stops receiving payload data upon receivi 0x20 - PLAIN_0 + PLAIN This register stores %sth 32-bit piece of plaintext. 0 32 diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3-ulp.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3-ulp.svd new file mode 100644 index 000000000..430f2a076 --- /dev/null +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3-ulp.svd @@ -0,0 +1,4665 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S3-ULP + RISC-V ULP + 1 + 32-bit RISC-V MCU + + Copyright 2023 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x00008000 + + 0x0 + 0x15C + registers + + + RISCV_START_INT + 6 + + + SW_INT + 7 + + + SWD_INT + 8 + + + + RTC_ULP_CP_TIMER + configure ulp + 0xFC + 0x20 + + + ULP_CP_PC_INIT + ULP-coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + ULP-coprocessor wakeup by GPIO enable + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + ULP-coprocessor wakeup by GPIO state clear + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP-coprocessor timer enable bit + 31 + 1 + read-write + + + + + RTC_ULP_CP_CTRL + configure ulp + 0x100 + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + No public + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + No public + 11 + 11 + read-write + + + ULP_CP_MEM_OFFST_CLR + No public + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ulp coprocessor clk force on + 28 + 1 + read-write + + + ULP_CP_RESET + ulp coprocessor clk software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + 1: ULP-coprocessor is started by SW + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-coprocessor + 31 + 1 + read-write + + + + + RTC_COCPU_CTRL + configure ulp-riscv + 0x104 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + cocpu clk force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + time from start cocpu to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + time from start cocpu to give start interrupt + 7 + 6 + read-write + + + COCPU_SHUT + to shut cocpu + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + time from shut cocpu to disable clk + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + to reset cocpu + 22 + 1 + read-write + + + COCPU_SEL + 1: old ULP 0: new riscV + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 1: select riscv done 0: select ulp done + 24 + 1 + read-write + + + COCPU_DONE + done signal used by riscv to control timer. + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + trigger cocpu register interrupt + 26 + 1 + write-only + + + COCPU_CLKGATE_EN + open ulp-riscv clk gate + 27 + 1 + read-write + + + + + RTC_ULP_CP_TIMER_1 + configure ulp sleep time + 0x134 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + + + RTC_I2C + Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C + 0x0000EC00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + configure low scl period + 0x0 + 0x20 + 0x00000100 + + + PERIOD + time period that scl =0 + 0 + 20 + read-write + + + + + CTRL + configure i2c ctrl + 0x4 + 0x20 + + + SDA_FORCE_OUT + 1=push pull,0=open drain + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1=push pull,0=open drain + 1 + 1 + read-write + + + MS_MODE + 1=master,0=slave + 2 + 1 + read-write + + + TRANS_START + force start + 3 + 1 + read-write + + + TX_LSB_FIRST + transit lsb first + 4 + 1 + read-write + + + RX_LSB_FIRST + receive lsb first + 5 + 1 + read-write + + + I2C_CTRL_CLK_GATE_EN + configure i2c ctrl clk enable + 29 + 1 + read-write + + + I2C_RESET + rtc i2c sw reset + 30 + 1 + read-write + + + I2CCLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + get i2c status + 0x8 + 0x20 + + + ACK_REC + ack response + 0 + 1 + read-only + + + SLAVE_RW + slave read or write + 1 + 1 + read-only + + + ARB_LOST + arbitration is lost + 2 + 1 + read-only + + + BUS_BUSY + bus is busy + 3 + 1 + read-only + + + SLAVE_ADDRESSED + slave reg sub address + 4 + 1 + read-only + + + BYTE_TRANS + One byte transit done + 5 + 1 + read-only + + + OP_CNT + which operation is working + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + configure time out + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + time out threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + configure slave id + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + i2c 10bit mode enable + 31 + 1 + read-write + + + + + SCL_HIGH + configure high scl period + 0x14 + 0x20 + 0x00000100 + + + PERIOD + time period that scl = 1 + 0 + 20 + read-write + + + + + SDA_DUTY + configure sda duty + 0x18 + 0x20 + 0x00000010 + + + NUM + time period for SDA to toggle after SCL goes low + 0 + 20 + read-write + + + + + SCL_START_PERIOD + configure scl start period + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + time period for SCL to toggle after I2C start is triggered + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + configure scl stop period + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + time period for SCL to stop after I2C end is triggered + 0 + 20 + read-write + + + + + INT_CLR + interrupt clear register + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + clear slave transit complete interrupt + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + clear arbitration lost interrupt + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + clear master transit complete interrupt + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + clear transit complete interrupt + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + clear time out interrupt + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + clear ack error interrupt + 5 + 1 + write-only + + + RX_DATA_INT_CLR + clear receive data interrupt + 6 + 1 + write-only + + + TX_DATA_INT_CLR + clear transit load data complete interrupt + 7 + 1 + write-only + + + DETECT_START_INT_CLR + clear detect start interrupt + 8 + 1 + write-only + + + + + INT_RAW + interrupt raw register + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + slave transit complete interrupt raw + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + arbitration lost interrupt raw + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + master transit complete interrupt raw + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + transit complete interrupt raw + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + time out interrupt raw + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + ack error interrupt raw + 5 + 1 + read-only + + + RX_DATA_INT_RAW + receive data interrupt raw + 6 + 1 + read-only + + + TX_DATA_INT_RAW + transit data interrupt raw + 7 + 1 + read-only + + + DETECT_START_INT_RAW + detect start interrupt raw + 8 + 1 + read-only + + + + + INT_ST + interrupt state register + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + slave transit complete interrupt state + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + arbitration lost interrupt state + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + master transit complete interrupt state + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + transit complete interrupt state + 3 + 1 + read-only + + + TIME_OUT_INT_ST + time out interrupt state + 4 + 1 + read-only + + + ACK_ERR_INT_ST + ack error interrupt state + 5 + 1 + read-only + + + RX_DATA_INT_ST + receive data interrupt state + 6 + 1 + read-only + + + TX_DATA_INT_ST + transit data interrupt state + 7 + 1 + read-only + + + DETECT_START_INT_ST + detect start interrupt state + 8 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + enable slave transit complete interrupt + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + enable arbitration lost interrupt + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + enable master transit complete interrupt + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + enable transit complete interrupt + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + enable time out interrupt + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + enable eack error interrupt + 5 + 1 + read-write + + + RX_DATA_INT_ENA + enable receive data interrupt + 6 + 1 + read-write + + + TX_DATA_INT_ENA + enable transit data interrupt + 7 + 1 + read-write + + + DETECT_START_INT_ENA + enable detect start interrupt + 8 + 1 + read-write + + + + + DATA + get i2c data status + 0x34 + 0x20 + + + I2C_RDATA + data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + data sent by slave + 8 + 8 + read-write + + + I2C_DONE + i2c done + 31 + 1 + read-only + + + + + CMD0 + i2c commond0 register + 0x38 + 0x20 + 0x00000903 + + + COMMAND0 + command0 + 0 + 14 + read-write + + + COMMAND0_DONE + command0_done + 31 + 1 + read-only + + + + + CMD1 + i2c commond1 register + 0x3C + 0x20 + 0x00001901 + + + COMMAND1 + command1 + 0 + 14 + read-write + + + COMMAND1_DONE + command1_done + 31 + 1 + read-only + + + + + CMD2 + i2c commond2 register + 0x40 + 0x20 + 0x00000902 + + + COMMAND2 + command2 + 0 + 14 + read-write + + + COMMAND2_DONE + command2_done + 31 + 1 + read-only + + + + + CMD3 + i2c commond3 register + 0x44 + 0x20 + 0x00000101 + + + COMMAND3 + command3 + 0 + 14 + read-write + + + COMMAND3_DONE + command3_done + 31 + 1 + read-only + + + + + CMD4 + i2c commond4 register + 0x48 + 0x20 + 0x00000901 + + + COMMAND4 + command4 + 0 + 14 + read-write + + + COMMAND4_DONE + command4_done + 31 + 1 + read-only + + + + + CMD5 + i2c commond5_register + 0x4C + 0x20 + 0x00001701 + + + COMMAND5 + command5 + 0 + 14 + read-write + + + COMMAND5_DONE + command5_done + 31 + 1 + read-only + + + + + CMD6 + i2c commond6 register + 0x50 + 0x20 + 0x00001901 + + + COMMAND6 + command6 + 0 + 14 + read-write + + + COMMAND6_DONE + command6_done + 31 + 1 + read-only + + + + + CMD7 + i2c commond7 register + 0x54 + 0x20 + 0x00000904 + + + COMMAND7 + command7 + 0 + 14 + read-write + + + COMMAND7_DONE + command7_done + 31 + 1 + read-only + + + + + CMD8 + i2c commond8 register + 0x58 + 0x20 + 0x00001901 + + + COMMAND8 + command8 + 0 + 14 + read-write + + + COMMAND8_DONE + command8_done + 31 + 1 + read-only + + + + + CMD9 + i2c commond9 register + 0x5C + 0x20 + 0x00000903 + + + COMMAND9 + command9 + 0 + 14 + read-write + + + COMMAND9_DONE + command9_done + 31 + 1 + read-only + + + + + CMD10 + i2c commond10 register + 0x60 + 0x20 + 0x00000101 + + + COMMAND10 + command10 + 0 + 14 + read-write + + + COMMAND10_DONE + command10_done + 31 + 1 + read-only + + + + + CMD11 + i2c commond11 register + 0x64 + 0x20 + 0x00000901 + + + COMMAND11 + command11 + 0 + 14 + read-write + + + COMMAND11_DONE + command11_done + 31 + 1 + read-only + + + + + CMD12 + i2c commond12 register + 0x68 + 0x20 + 0x00001701 + + + COMMAND12 + command12 + 0 + 14 + read-write + + + COMMAND12_DONE + command12_done + 31 + 1 + read-only + + + + + CMD13 + i2c commond13 register + 0x6C + 0x20 + 0x00001901 + + + COMMAND13 + command13 + 0 + 14 + read-write + + + COMMAND13_DONE + command13_done + 31 + 1 + read-only + + + + + CMD14 + i2c commond14 register + 0x70 + 0x20 + + + COMMAND14 + command14 + 0 + 14 + read-write + + + COMMAND14_DONE + command14_done + 31 + 1 + read-only + + + + + CMD15 + i2c commond15 register + 0x74 + 0x20 + + + COMMAND15 + command15 + 0 + 14 + read-write + + + COMMAND15_DONE + command15_done + 31 + 1 + read-only + + + + + DATE + version register + 0xFC + 0x20 + 0x01905310 + + + I2C_DATE + version + 0 + 28 + read-write + + + + + + + RTC_IO + Low-power Input/Output + RTC_IO + 0x0000A400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO 0 ~ 21 output data register + 0x0 + 0x20 + + + DATA + RTC GPIO 0 ~ 21 output data + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + one set RTC GPIO output data + 0x4 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TS + RTC GPIO 0 ~ 21 output data write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + one clear RTC GPIO output data + 0x8 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TC + RTC GPIO 0 ~ 21 output data write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + Configure RTC GPIO output enable + 0xC + 0x20 + + + RTC_GPIO_ENABLE + RTC GPIO 0 ~ 21 enable + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + one set RTC GPIO output enable + 0x10 + 0x20 + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO 0 ~ 21 enable write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE_W1TC + one clear RTC GPIO output enable + 0x14 + 0x20 + + + RTC_GPIO_ENABLE_W1TC + RTC GPIO 0 ~ 21 enable write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO 0 ~ 21 interrupt status + 0x18 + 0x20 + + + INT + RTC GPIO 0 ~ 21 interrupt status + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + One set RTC GPIO 0 ~ 21 interrupt status + 0x1C + 0x20 + + + RTC_GPIO_STATUS_INT_W1TS + RTC GPIO 0 ~ 21 interrupt status write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + One clear RTC GPIO 0 ~ 21 interrupt status + 0x20 + 0x20 + + + RTC_GPIO_STATUS_INT_W1TC + RTC GPIO 0 ~ 21 interrupt status write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input data + 0x24 + 0x20 + + + NEXT + RTC GPIO input data + 10 + 22 + read-only + + + + + RTC_GPIO_PIN0 + configure RTC GPIO0 + 0x28 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN1 + configure RTC GPIO1 + 0x2C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN2 + configure RTC GPIO2 + 0x30 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN3 + configure RTC GPIO3 + 0x34 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN4 + configure RTC GPIO4 + 0x38 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN5 + configure RTC GPIO5 + 0x3C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN6 + configure RTC GPIO6 + 0x40 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN7 + configure RTC GPIO7 + 0x44 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN8 + configure RTC GPIO8 + 0x48 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN9 + configure RTC GPIO9 + 0x4C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN10 + configure RTC GPIO10 + 0x50 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN11 + configure RTC GPIO11 + 0x54 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN12 + configure RTC GPIO12 + 0x58 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN13 + configure RTC GPIO13 + 0x5C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN14 + configure RTC GPIO14 + 0x60 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN15 + configure RTC GPIO15 + 0x64 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN16 + configure RTC GPIO16 + 0x68 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN17 + configure RTC GPIO17 + 0x6C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN18 + configure RTC GPIO18 + 0x70 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN19 + configure RTC GPIO19 + 0x74 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN20 + configure RTC GPIO20 + 0x78 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_GPIO_PIN21 + configure RTC GPIO21 + 0x7C + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + configure rtc debug + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + configure rtc debug + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + configure rtc debug + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + configure rtc debug + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + configure rtc debug + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + configure rtc debug + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + configure rtc debug + 25 + 1 + read-write + + + + + TOUCH_PAD0 + configure RTC PAD0 + 0x84 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD1 + configure RTC PAD1 + 0x88 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD2 + configure RTC PAD2 + 0x8C + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD3 + configure RTC PAD3 + 0x90 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD4 + configure RTC PAD4 + 0x94 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD5 + configure RTC PAD5 + 0x98 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD6 + configure RTC PAD6 + 0x9C + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD7 + configure RTC PAD7 + 0xA0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD8 + configure RTC PAD8 + 0xA4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD9 + configure RTC PAD9 + 0xA8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD10 + configure RTC PAD10 + 0xAC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD11 + configure RTC PAD11 + 0xB0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD12 + configure RTC PAD12 + 0xB4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD13 + configure RTC PAD13 + 0xB8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD14 + configure RTC PAD14 + 0xBC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32P_PAD + configure RTC PAD15 + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32P_FUN_SEL + function sel + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32P_RUE + RUE + 27 + 1 + read-write + + + X32P_RDE + RDE + 28 + 1 + read-write + + + X32P_DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32N_PAD + configure RTC PAD16 + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32N_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32N_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32N_FUN_SEL + function sel + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32N_RUE + RUE + 27 + 1 + read-write + + + X32N_RDE + RDE + 28 + 1 + read-write + + + X32N_DRV + DRV + 29 + 2 + read-write + + + + + PAD_DAC1 + configure RTC PAD17 + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + PDAC1_DAC + 3 + 8 + read-write + + + PDAC1_XPD_DAC + PDAC1_XPD_DAC + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC + 12 + 1 + read-write + + + PDAC1_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC1_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + PDAC1_RUE + 27 + 1 + read-write + + + PDAC1_RDE + PDAC1_RDE + 28 + 1 + read-write + + + PDAC1_DRV + PDAC1_DRV + 29 + 2 + read-write + + + + + PAD_DAC2 + configure RTC PAD18 + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + PDAC2_DAC + 3 + 8 + read-write + + + PDAC2_XPD_DAC + PDAC2_XPD_DAC + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC + 12 + 1 + read-write + + + PDAC2_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC2_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC2_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC2_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC2_RUE + PDAC2_RUE + 27 + 1 + read-write + + + PDAC2_RDE + PDAC2_RDE + 28 + 1 + read-write + + + PDAC2_DRV + PDAC2_DRV + 29 + 2 + read-write + + + + + RTC_PAD19 + configure RTC PAD19 + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD20 + configure RTC PAD20 + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD21 + configure RTC PAD21 + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + configure EXT0 wakeup + 0xDC + 0x20 + + + SEL + ******* Description configure*** + 27 + 5 + read-write + + + + + XTL_EXT_CTR + configure gpio pd XTAL + 0xE0 + 0x20 + + + SEL + select RTC GPIO 0 ~ 17 to control XTAL + 27 + 5 + read-write + + + + + SAR_I2C_IO + configure rtc i2c mux + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + ******* Description configure*** + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + ******* Description configure*** + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + ******* Description configure*** + 30 + 2 + read-write + + + + + TOUCH_CTRL + configure touch pad bufmode + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + BUF_SEL when touch work without fsm + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + BUF_MODE when touch work without fsm + 4 + 1 + read-write + + + + + DATE + version + 0x1FC + 0x20 + 0x02101180 + + + DATE + version + 0 + 28 + read-write + + + + + + + SENS + SENS Peripheral + SENS + 0x0000C800 + + 0x0 + 0x11C + registers + + + TOUCH_DONE_INT + 0 + + + TOUCH_INACTIVE_INT + 1 + + + TOUCH_ACTIVE_INT + 2 + + + SARADC1_DONE_INT + 3 + + + SARADC2_DONE_INT + 4 + + + TSENS_DONE_INT + 5 + + + TOUCH_TIME_OUT_INT + 9 + + + TOUCH_APPROACH_LOOP_DONE_INT + 10 + + + TOUCH_SCAN_DONE_INT + 11 + + + + SAR_SLAVE_ADDR1 + configure i2c slave address + 0x40 + 0x20 + + + SAR_I2C_SLAVE_ADDR1 + configure i2c slave address1 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR0 + configure i2c slave address0 + 11 + 11 + read-write + + + SAR_SARADC_MEAS_STATUS + no public + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + configure i2c slave address + 0x44 + 0x20 + + + SAR_I2C_SLAVE_ADDR3 + configure i2c slave address3 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR2 + configure i2c slave address2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + configure i2c slave address + 0x48 + 0x20 + + + SAR_I2C_SLAVE_ADDR5 + configure i2c slave address5 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR4 + configure i2c slave address4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + configure i2c slave address + 0x4C + 0x20 + + + SAR_I2C_SLAVE_ADDR7 + configure i2c slave address7 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR6 + configure i2c slave address6 + 11 + 11 + read-write + + + + + SAR_I2C_CTRL + configure rtc i2c controller by sw + 0x58 + 0x20 + + + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 + 0 + 28 + read-write + + + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 + 1 + read-write + + + + + SAR_COCPU_INT_RAW + the interrupt raw of ulp + 0xE8 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_RAW + int from touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_RAW + int from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_RAW + int from touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_RAW + int from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_RAW + int from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_RAW + int from tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_RAW + int from start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_RAW + int from software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_RAW + int from super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + int from timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + int from approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + int from touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + the interrupt enable of ulp + 0xEC + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA + int enable of touch done + 0 + 1 + read-write + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA + int enable of from touch inactive + 1 + 1 + read-write + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA + int enable of touch active + 2 + 1 + read-write + + + SAR_COCPU_SARADC1_INT_ENA + int enable of from saradc1 + 3 + 1 + read-write + + + SAR_COCPU_SARADC2_INT_ENA + int enable of from saradc2 + 4 + 1 + read-write + + + SAR_COCPU_TSENS_INT_ENA + int enable of tsens + 5 + 1 + read-write + + + SAR_COCPU_START_INT_ENA + int enable of start + 6 + 1 + read-write + + + SAR_COCPU_SW_INT_ENA + int enable of software + 7 + 1 + read-write + + + SAR_COCPU_SWD_INT_ENA + int enable of super watch dog + 8 + 1 + read-write + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + int enable of timeout done + 9 + 1 + read-write + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + int enable of approach loop done + 10 + 1 + read-write + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + int enable of touch scan done + 11 + 1 + read-write + + + + + SAR_COCPU_INT_ST + the interrupt state of ulp + 0xF0 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ST + int state of touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ST + int state of from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ST + int state of touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_ST + int state of from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_ST + int state of from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_ST + int state of tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_ST + int state of start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_ST + int state of software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_ST + int state of super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ST + int state of timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + int state of approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + int state of touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + the interrupt clear of ulp + 0xF4 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_CLR + int clear of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_CLR + int clear of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_CLR + int clear of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_CLR + int clear of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_CLR + int clear of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_CLR + int clear of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_CLR + int clear of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_CLR + int clear of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_CLR + int clear of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + int clear of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + int clear of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + int clear of touch scan done + 11 + 1 + write-only + + + + + + + \ No newline at end of file diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3.svd b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3.svd index 6ac60ffe3..25594dd42 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3.svd +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/svd/esp32s3.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S3 - ESP32-S3 - 9 + ESP32 S-Series + 21 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. Xtensa LX7 r0p0 little false true - 3 + 0 false 32 @@ -45,21 +43,17 @@ 0xB8 registers - - AES - 77 - 8 0x4 - KEY_%s + KEY[%s] AES key register %s 0x0 0x20 - KEY_0 + KEY Stores AES keys. 0 32 @@ -70,13 +64,13 @@ 4 0x4 - TEXT_IN_%s + TEXT_IN[%s] Source data register %s 0x20 0x20 - TEXT_IN_0 + TEXT_IN Stores the source data when the AES accelerator operates in the Typical AES working mode. 0 32 @@ -87,13 +81,13 @@ 4 0x4 - TEXT_OUT_%s + TEXT_OUT[%s] Result data register %s 0x30 0x20 - TEXT_OUT_0 + TEXT_OUT Stores the result data when the AES accelerator operates in the Typical AES working mode. 0 32 @@ -147,36 +141,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -348,7 +342,7 @@ APB_CTRL - Advanced Peripheral Bus Controller + APB (Advanced Peripheral Bus) Controller APB_CTRL 0x60026000 @@ -1419,7 +1413,7 @@ APB_SARADC - Successive Approximation Register Analog to Digital Converter + SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x60040000 @@ -1800,7 +1794,7 @@ - APB_ADC_ARB_CTRL + ARB_CTRL configure apb saradc arbit 0x38 0x20 @@ -2243,7 +2237,7 @@ - APB_ADC_CLKM_CONF + CLKM_CONF configure apb saradc clock 0x70 0x20 @@ -2320,7 +2314,52 @@ - DEBUG_ASSIST + BB + BB Peripheral + BB + 0x6001D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + + + ASSIST_DEBUG Debug Assist DEBUG_ASSIST 0x600CE000 @@ -2335,7 +2374,7 @@ - CORE_0_INTERRUPT_ENA + CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 @@ -2427,7 +2466,7 @@ - CORE_0_INTERRUPT_RAW + CORE_0_INTR_RAW core0 monitor interrupt status register 0x4 0x20 @@ -2519,90 +2558,90 @@ - CORE_0_INTERRUPT_RLS + CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS + CORE_0_AREA_DRAM0_0_RD_INTR_ENA Core0 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_RLS + CORE_0_AREA_DRAM0_0_WR_INTR_ENA Core0 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_0_AREA_DRAM0_1_RD_RLS + CORE_0_AREA_DRAM0_1_RD_INTR_ENA Core0 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_0_AREA_DRAM0_1_WR_RLS + CORE_0_AREA_DRAM0_1_WR_INTR_ENA Core0 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_0_AREA_PIF_0_RD_RLS + CORE_0_AREA_PIF_0_RD_INTR_ENA Core0 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_0_AREA_PIF_0_WR_RLS + CORE_0_AREA_PIF_0_WR_INTR_ENA Core0 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_0_AREA_PIF_1_RD_RLS + CORE_0_AREA_PIF_1_RD_INTR_ENA Core0 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_0_AREA_PIF_1_WR_RLS + CORE_0_AREA_PIF_1_WR_INTR_ENA Core0 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_0_SP_SPILL_MIN_RLS + CORE_0_SP_SPILL_MIN_INTR_ENA Core0 stackpoint overflow monitor interrupt enable 8 1 read-write - CORE_0_SP_SPILL_MAX_RLS + CORE_0_SP_SPILL_MAX_INTR_ENA Core0 stackpoint underflow monitor interrupt enable 9 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -2611,7 +2650,7 @@ - CORE_0_INTERRUPT_CLR + CORE_0_INTR_CLR core0 monitor interrupt clr register 0xC 0x20 @@ -3234,7 +3273,7 @@ - CORE_1_INTERRUPT_ENA + CORE_1_MONTR_ENA Core1 monitor enable configuration register 0x90 0x20 @@ -3326,7 +3365,7 @@ - CORE_1_INTERRUPT_RAW + CORE_1_INTR_RAW Core1 monitor interrupt status register 0x94 0x20 @@ -3418,90 +3457,90 @@ - CORE_1_INTERRUPT_RLS + CORE_1_INTR_ENA Core1 monitor interrupt enable register 0x98 0x20 - CORE_1_AREA_DRAM0_0_RD_RLS + CORE_1_AREA_DRAM0_0_RD_INTR_ENA Core1 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_1_AREA_DRAM0_0_WR_RLS + CORE_1_AREA_DRAM0_0_WR_INTR_ENA Core1 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_1_AREA_DRAM0_1_RD_RLS + CORE_1_AREA_DRAM0_1_RD_INTR_ENA Core1 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_1_AREA_DRAM0_1_WR_RLS + CORE_1_AREA_DRAM0_1_WR_INTR_ENA Core1 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_1_AREA_PIF_0_RD_RLS + CORE_1_AREA_PIF_0_RD_INTR_ENA Core1 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_1_AREA_PIF_0_WR_RLS + CORE_1_AREA_PIF_0_WR_INTR_ENA Core1 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_1_AREA_PIF_1_RD_RLS + CORE_1_AREA_PIF_1_RD_INTR_ENA Core1 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_1_AREA_PIF_1_WR_RLS + CORE_1_AREA_PIF_1_WR_INTR_ENA Core1 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_1_SP_SPILL_MIN_RLS + CORE_1_SP_SPILL_MIN_INTR_ENA Core1 stackpoint overflow monitor interrupt enable 8 1 read-write - CORE_1_SP_SPILL_MAX_RLS + CORE_1_SP_SPILL_MAX_INTR_ENA Core1 stackpoint underflow monitor interrupt enable 9 1 read-write - CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -3510,7 +3549,7 @@ - CORE_1_INTERRUPT_CLR + CORE_1_INTR_CLR Core1 monitor interrupt clr register 0x9C 0x20 @@ -4427,9 +4466,13 @@ 75 - APB_PMS_MONITOR_VIOLATE + DMA_APBPERI_PMS 84 + + BACKUP_PMS_VIOLATE + 93 + DMA_EXTMEM_REJECT 98 @@ -4444,35 +4487,35 @@ 0x20 - IN_RST_CH + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -4490,21 +4533,21 @@ 0x0000000C - DMA_INFIFO_FULL_THRS_CH + DMA_INFIFO_FULL_THRS This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. 0 12 read-write - IN_CHECK_OWNER_CH + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write - IN_EXT_MEM_BK_SIZE_CH + IN_EXT_MEM_BK_SIZE Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved 13 2 @@ -4521,74 +4564,74 @@ 0x20 - IN_DONE_CH_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 - read-only + read-write - IN_SUC_EOF_CH_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 - read-only + read-write - IN_ERR_EOF_CH_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 - read-only + read-write - IN_DSCR_ERR_CH_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 3 1 - read-only + read-write - IN_DSCR_EMPTY_CH_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 4 1 - read-only + read-write - INFIFO_FULL_WM_CH_INT_RAW + INFIFO_FULL_WM The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. 5 1 - read-only + read-write - INFIFO_OVF_L1_CH_INT_RAW + INFIFO_OVF_L1 This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 6 1 - read-only + read-write - INFIFO_UDF_L1_CH_INT_RAW + INFIFO_UDF_L1 This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 7 1 - read-only + read-write - INFIFO_OVF_L3_CH_INT_RAW + INFIFO_OVF_L3 This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. 8 1 - read-only + read-write - INFIFO_UDF_L3_CH_INT_RAW + INFIFO_UDF_L3 This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. 9 1 - read-only + read-write @@ -4601,70 +4644,70 @@ 0x20 - IN_DONE_CH_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - IN_DSCR_ERR_CH_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - IN_DSCR_EMPTY_CH_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-only - INFIFO_FULL_WM_CH_INT_ST + INFIFO_FULL_WM The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. 5 1 read-only - INFIFO_OVF_L1_CH_INT_ST + INFIFO_OVF_L1 The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 6 1 read-only - INFIFO_UDF_L1_CH_INT_ST + INFIFO_UDF_L1 The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 7 1 read-only - INFIFO_OVF_L3_CH_INT_ST + INFIFO_OVF_L3 The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. 8 1 read-only - INFIFO_UDF_L3_CH_INT_ST + INFIFO_UDF_L3 The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4681,70 +4724,70 @@ 0x20 - IN_DONE_CH_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - IN_DSCR_ERR_CH_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - IN_DSCR_EMPTY_CH_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-write - INFIFO_FULL_WM_CH_INT_ENA + INFIFO_FULL_WM The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. 5 1 read-write - INFIFO_OVF_L1_CH_INT_ENA + INFIFO_OVF_L1 The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 6 1 read-write - INFIFO_UDF_L1_CH_INT_ENA + INFIFO_UDF_L1 The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 7 1 read-write - INFIFO_OVF_L3_CH_INT_ENA + INFIFO_OVF_L3 The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. 8 1 read-write - INFIFO_UDF_L3_CH_INT_ENA + INFIFO_UDF_L3 The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4761,70 +4804,70 @@ 0x20 - IN_DONE_CH_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - IN_DSCR_ERR_CH_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 3 1 write-only - IN_DSCR_EMPTY_CH_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 write-only - DMA_INFIFO_FULL_WM_CH_INT_CLR + DMA_INFIFO_FULL_WM Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. 5 1 write-only - INFIFO_OVF_L1_CH_INT_CLR + INFIFO_OVF_L1 Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 6 1 write-only - INFIFO_UDF_L1_CH_INT_CLR + INFIFO_UDF_L1 Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 7 1 write-only - INFIFO_OVF_L3_CH_INT_CLR + INFIFO_OVF_L3 Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. 8 1 write-only - INFIFO_UDF_L3_CH_INT_CLR + INFIFO_UDF_L3 Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4842,98 +4885,98 @@ 0x0F00003A - INFIFO_FULL_L1_CH + INFIFO_FULL_L1 L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_L1_CH + INFIFO_EMPTY_L1 L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_FULL_L2_CH + INFIFO_FULL_L2 L2 Rx FIFO full signal for Rx channel 0. 2 1 read-only - INFIFO_EMPTY_L2_CH + INFIFO_EMPTY_L2 L2 Rx FIFO empty signal for Rx channel 0. 3 1 read-only - INFIFO_FULL_L3_CH + INFIFO_FULL_L3 L3 Rx FIFO full signal for Rx channel 0. 4 1 read-only - INFIFO_EMPTY_L3_CH + INFIFO_EMPTY_L3 L3 Rx FIFO empty signal for Rx channel 0. 5 1 read-only - INFIFO_CNT_L1_CH + INFIFO_CNT_L1 The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 6 6 read-only - INFIFO_CNT_L2_CH + INFIFO_CNT_L2 The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. 12 7 read-only - INFIFO_CNT_L3_CH + INFIFO_CNT_L3 The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. 19 5 read-only - IN_REMAIN_UNDER_1B_L3_CH + IN_REMAIN_UNDER_1B_L3 reserved 24 1 read-only - IN_REMAIN_UNDER_2B_L3_CH + IN_REMAIN_UNDER_2B_L3 reserved 25 1 read-only - IN_REMAIN_UNDER_3B_L3_CH + IN_REMAIN_UNDER_3B_L3 reserved 26 1 read-only - IN_REMAIN_UNDER_4B_L3_CH + IN_REMAIN_UNDER_4B_L3 reserved 27 1 read-only - IN_BUF_HUNGRY_CH + IN_BUF_HUNGRY reserved 28 1 @@ -4951,14 +4994,14 @@ 0x00000800 - INFIFO_RDATA_CH + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -4976,42 +5019,42 @@ 0x01100000 - INLINK_ADDR_CH + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -5028,21 +5071,21 @@ 0x20 - INLINK_DSCR_ADDR_CH + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH + IN_STATE reserved 20 3 @@ -5059,7 +5102,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5076,7 +5119,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -5093,7 +5136,7 @@ 0x20 - INLINK_DSCR_CH + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -5110,7 +5153,7 @@ 0x20 - INLINK_DSCR_BF0_CH + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -5127,7 +5170,7 @@ 0x20 - INLINK_DSCR_BF1_CH + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5145,7 +5188,7 @@ 0x00000F00 - RX_WEIGHT_CH + RX_WEIGHT The weight of Rx channel 0. 8 4 @@ -5162,7 +5205,7 @@ 0x20 - RX_PRI_CH + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5180,7 +5223,7 @@ 0x0000003F - PERI_IN_SEL_CH + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. 0 6 @@ -5198,42 +5241,42 @@ 0x00000008 - OUT_RST_CH + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -5250,14 +5293,14 @@ 0x20 - OUT_CHECK_OWNER_CH + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write - OUT_EXT_MEM_BK_SIZE_CH + OUT_EXT_MEM_BK_SIZE Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved 13 2 @@ -5274,60 +5317,60 @@ 0x20 - OUT_DONE_CH_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 - read-only + read-write - OUT_EOF_CH_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 1 - read-only + read-write - OUT_DSCR_ERR_CH_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 2 1 - read-only + read-write - OUT_TOTAL_EOF_CH_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 3 1 - read-only + read-write - OUTFIFO_OVF_L1_CH_INT_RAW + OUTFIFO_OVF_L1 This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 4 1 - read-only + read-write - OUTFIFO_UDF_L1_CH_INT_RAW + OUTFIFO_UDF_L1 This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 5 1 - read-only + read-write - OUTFIFO_OVF_L3_CH_INT_RAW + OUTFIFO_OVF_L3 This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. 6 1 - read-only + read-write - OUTFIFO_UDF_L3_CH_INT_RAW + OUTFIFO_UDF_L3 This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. 7 1 - read-only + read-write @@ -5340,56 +5383,56 @@ 0x20 - OUT_DONE_CH_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH_INT_ST + OUTFIFO_OVF_L1 The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH_INT_ST + OUTFIFO_UDF_L1 The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L3_CH_INT_ST + OUTFIFO_OVF_L3 The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L3_CH_INT_ST + OUTFIFO_UDF_L3 The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5406,56 +5449,56 @@ 0x20 - OUT_DONE_CH_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH_INT_ENA + OUTFIFO_OVF_L1 The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH_INT_ENA + OUTFIFO_UDF_L1 The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L3_CH_INT_ENA + OUTFIFO_OVF_L3 The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L3_CH_INT_ENA + OUTFIFO_UDF_L3 The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5472,56 +5515,56 @@ 0x20 - OUT_DONE_CH_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH_INT_CLR + OUTFIFO_OVF_L1 Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH_INT_CLR + OUTFIFO_UDF_L1 Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L3_CH_INT_CLR + OUTFIFO_OVF_L3 Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L3_CH_INT_CLR + OUTFIFO_UDF_L3 Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5539,91 +5582,91 @@ 0x0780002A - OUTFIFO_FULL_L1_CH + OUTFIFO_FULL_L1 L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_L1_CH + OUTFIFO_EMPTY_L1 L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_FULL_L2_CH + OUTFIFO_FULL_L2 L2 Tx FIFO full signal for Tx channel 0. 2 1 read-only - OUTFIFO_EMPTY_L2_CH + OUTFIFO_EMPTY_L2 L2 Tx FIFO empty signal for Tx channel 0. 3 1 read-only - OUTFIFO_FULL_L3_CH + OUTFIFO_FULL_L3 L3 Tx FIFO full signal for Tx channel 0. 4 1 read-only - OUTFIFO_EMPTY_L3_CH + OUTFIFO_EMPTY_L3 L3 Tx FIFO empty signal for Tx channel 0. 5 1 read-only - OUTFIFO_CNT_L1_CH + OUTFIFO_CNT_L1 The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 6 5 read-only - OUTFIFO_CNT_L2_CH + OUTFIFO_CNT_L2 The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. 11 7 read-only - OUTFIFO_CNT_L3_CH + OUTFIFO_CNT_L3 The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. 18 5 read-only - OUT_REMAIN_UNDER_1B_L3_CH + OUT_REMAIN_UNDER_1B_L3 reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_L3_CH + OUT_REMAIN_UNDER_2B_L3 reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_L3_CH + OUT_REMAIN_UNDER_3B_L3 reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_L3_CH + OUT_REMAIN_UNDER_4B_L3 reserved 26 1 @@ -5640,14 +5683,14 @@ 0x20 - OUTFIFO_WDATA_CH + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5665,35 +5708,35 @@ 0x00800000 - OUTLINK_ADDR_CH + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5710,21 +5753,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH + OUT_STATE reserved 20 3 @@ -5741,7 +5784,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5758,7 +5801,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5775,7 +5818,7 @@ 0x20 - OUTLINK_DSCR_CH + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5792,7 +5835,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5809,7 +5852,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5827,7 +5870,7 @@ 0x00000F00 - TX_WEIGHT_CH + TX_WEIGHT The weight of Tx channel 0. 8 4 @@ -5844,7 +5887,7 @@ 0x20 - TX_PRI_CH + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5862,7 +5905,7 @@ 0x0000003F - PERI_OUT_SEL_CH + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. 0 6 @@ -5968,7 +6011,7 @@ 0x0000000E - IN_SIZE_CH + IN_SIZE This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. 0 7 @@ -5986,7 +6029,7 @@ 0x0000000E - OUT_SIZE_CH + OUT_SIZE This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. 0 7 @@ -6049,7 +6092,7 @@ The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control. 0 1 - read-only + read-write @@ -6128,12 +6171,12 @@ - 1584 - 0x1 + 396 + 0x4 C_MEM[%s] Memory C 0x0 - 0x8 + 0x20 4 @@ -6144,7 +6187,7 @@ 0x20 - IV_0 + IV Stores IV block data 0 32 @@ -6153,20 +6196,20 @@ - 512 - 0x1 + 128 + 0x4 X_MEM[%s] Memory X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] Memory Z 0xA00 - 0x8 + 0x20 SET_START @@ -11531,6 +11574,14 @@ GPIO_NMI 17 + + GPIO_INTR_2 + 18 + + + GPIO_NMI_2 + 19 + BT_SELECT @@ -11558,6 +11609,7 @@ GPIO output register for GPIO0-31 0 32 + read-write @@ -11602,6 +11654,7 @@ GPIO output register for GPIO32-53 0 22 + read-write @@ -11968,55 +12021,56 @@ 54 0x4 + 0-53 PIN%s GPIO pin configuration register 0x74 0x20 - PIN_SYNC2_BYPASS - set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write - PIN_PAD_DRIVER - set this bit to select pad driver. 1:open-drain. :normal. + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write - PIN_SYNC1_BYPASS - set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write - PIN_INT_TYPE - set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write - PIN_CONFIG + CONFIG reserved 11 2 read-write - PIN_INT_ENA + INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 @@ -12057,6 +12111,7 @@ 256 0x4 + 0-255 FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 @@ -12064,21 +12119,21 @@ IN_SEL - set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level. + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL - set this bit to invert input signal. 1:invert. :not invert. + set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO. + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write @@ -12088,6 +12143,7 @@ 54 0x4 + 0-53 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 @@ -12096,28 +12152,28 @@ OUT_SEL - The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 9 read-write INV_SEL - set this bit to invert output signal.1:invert.:not invert. + set this bit to invert output signal.1:invert.0:not invert. 9 1 read-write OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal. + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 10 1 read-write OEN_INV_SEL - set this bit to invert output enable signal.1:invert.:not invert. + set this bit to invert output enable signal.1:invert.0:not invert. 11 1 read-write @@ -12159,7 +12215,7 @@ - GPIOSD + GPIO_SD Sigma-Delta Modulation GPIOSD 0x60004F00 @@ -12417,7 +12473,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 @@ -12441,20 +12497,20 @@ - 64 - 0x1 + 16 + 0x4 WR_MESSAGE_MEM[%s] Message block memory. 0x80 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 RD_RESULT_MEM[%s] Result from upstream. 0xC0 - 0x8 + 0x20 SET_MESSAGE_PAD @@ -12536,7 +12592,7 @@ I2C0 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 0 I2C 0x60013000 @@ -12545,7 +12601,7 @@ registers - I2C_MST + I2C_MASTER 11 @@ -13681,6 +13737,7 @@ in I2C module clock cycles, the I2C controller will ignore that pulse. 8 0x4 + 0-7 COMD%s I2C command register %s 0x58 @@ -13688,8 +13745,8 @@ in I2C module clock cycles, the I2C controller will ignore that pulse. COMMAND - This is the content of command . It consists of three parts: -op_code is the command, : RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. @@ -13699,7 +13756,7 @@ Information. COMMAND_DONE - When command is done in I2C Master mode, this bit changes to high + When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 @@ -13868,7 +13925,7 @@ level. I2C1 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 1 0x60027000 I2C_EXT1 @@ -13877,7 +13934,7 @@ level. I2S0 - I2S (Inter-IC Sound) Controller + I2S (Inter-IC Sound) Controller 0 I2S 0x6000F000 @@ -15186,7 +15243,7 @@ level. I2S1 - I2S (Inter-IC Sound) Controller + I2S (Inter-IC Sound) Controller 1 I2S1 0x6002D000 @@ -15200,34 +15257,34 @@ level. - I2S_INT_RAW + INT_RAW I2S interrupt raw register, valid in level. 0xC 0x20 - I2S_RX_DONE_INT_RAW + RX_DONE_INT_RAW The raw interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only - I2S_TX_DONE_INT_RAW + TX_DONE_INT_RAW The raw interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only - I2S_RX_HUNG_INT_RAW + RX_HUNG_INT_RAW The raw interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only - I2S_TX_HUNG_INT_RAW + TX_HUNG_INT_RAW The raw interrupt status bit for the i2s_tx_hung_int interrupt 3 1 @@ -15236,34 +15293,34 @@ level. - I2S_INT_ST + INT_ST I2S interrupt status register. 0x10 0x20 - I2S_RX_DONE_INT_ST + RX_DONE_INT_ST The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only - I2S_TX_DONE_INT_ST + TX_DONE_INT_ST The masked interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only - I2S_RX_HUNG_INT_ST + RX_HUNG_INT_ST The masked interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only - I2S_TX_HUNG_INT_ST + TX_HUNG_INT_ST The masked interrupt status bit for the i2s_tx_hung_int interrupt 3 1 @@ -15272,34 +15329,34 @@ level. - I2S_INT_ENA + INT_ENA I2S interrupt enable register. 0x14 0x20 - I2S_RX_DONE_INT_ENA + RX_DONE_INT_ENA The interrupt enable bit for the i2s_rx_done_int interrupt 0 1 read-write - I2S_TX_DONE_INT_ENA + TX_DONE_INT_ENA The interrupt enable bit for the i2s_tx_done_int interrupt 1 1 read-write - I2S_RX_HUNG_INT_ENA + RX_HUNG_INT_ENA The interrupt enable bit for the i2s_rx_hung_int interrupt 2 1 read-write - I2S_TX_HUNG_INT_ENA + TX_HUNG_INT_ENA The interrupt enable bit for the i2s_tx_hung_int interrupt 3 1 @@ -15308,34 +15365,34 @@ level. - I2S_INT_CLR + INT_CLR I2S interrupt clear register. 0x18 0x20 - I2S_RX_DONE_INT_CLR + RX_DONE_INT_CLR Set this bit to clear the i2s_rx_done_int interrupt 0 1 write-only - I2S_TX_DONE_INT_CLR + TX_DONE_INT_CLR Set this bit to clear the i2s_tx_done_int interrupt 1 1 write-only - I2S_RX_HUNG_INT_CLR + RX_HUNG_INT_CLR Set this bit to clear the i2s_rx_hung_int interrupt 2 1 write-only - I2S_TX_HUNG_INT_CLR + TX_HUNG_INT_CLR Set this bit to clear the i2s_tx_hung_int interrupt 3 1 @@ -15344,126 +15401,126 @@ level. - I2S_RX_CONF + RX_CONF I2S RX configure register 0x20 0x20 0x00009600 - I2S_RX_RESET + RX_RESET Set this bit to reset receiver 0 1 write-only - I2S_RX_FIFO_RESET + RX_FIFO_RESET Set this bit to reset Rx AFIFO 1 1 write-only - I2S_RX_START + RX_START Set this bit to start receiving data 2 1 read-write - I2S_RX_SLAVE_MOD + RX_SLAVE_MOD Set this bit to enable slave receiver mode 3 1 read-write - I2S_RX_MONO + RX_MONO Set this bit to enable receiver in mono mode 5 1 read-write - I2S_RX_BIG_ENDIAN + RX_BIG_ENDIAN I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - I2S_RX_UPDATE + RX_UPDATE Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - I2S_RX_MONO_FST_VLD + RX_MONO_FST_VLD 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write - I2S_RX_PCM_CONF + RX_PCM_CONF I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - I2S_RX_PCM_BYPASS + RX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for received data. 12 1 read-write - I2S_RX_STOP_MODE + RX_STOP_MODE 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 13 2 read-write - I2S_RX_LEFT_ALIGN + RX_LEFT_ALIGN 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. 15 1 read-write - I2S_RX_24_FILL_EN + RX_24_FILL_EN 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. 16 1 read-write - I2S_RX_WS_IDLE_POL + RX_WS_IDLE_POL 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. 17 1 read-write - I2S_RX_BIT_ORDER + RX_BIT_ORDER I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. 18 1 read-write - I2S_RX_TDM_EN + RX_TDM_EN 1: Enable I2S TDM Rx mode . 0: Disable. 19 1 read-write - I2S_RX_PDM_EN + RX_PDM_EN 1: Enable I2S PDM Rx mode . 0: Disable. 20 1 @@ -15472,147 +15529,147 @@ level. - I2S_TX_CONF + TX_CONF I2S TX configure register 0x24 0x20 0x0000B200 - I2S_TX_RESET + TX_RESET Set this bit to reset transmitter 0 1 write-only - I2S_TX_FIFO_RESET + TX_FIFO_RESET Set this bit to reset Tx AFIFO 1 1 write-only - I2S_TX_START + TX_START Set this bit to start transmitting data 2 1 read-write - I2S_TX_SLAVE_MOD + TX_SLAVE_MOD Set this bit to enable slave transmitter mode 3 1 read-write - I2S_TX_MONO + TX_MONO Set this bit to enable transmitter in mono mode 5 1 read-write - I2S_TX_CHAN_EQUAL + TX_CHAN_EQUAL 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 6 1 read-write - I2S_TX_BIG_ENDIAN + TX_BIG_ENDIAN I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - I2S_TX_UPDATE + TX_UPDATE Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - I2S_TX_MONO_FST_VLD + TX_MONO_FST_VLD 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. 9 1 read-write - I2S_TX_PCM_CONF + TX_PCM_CONF I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - I2S_TX_PCM_BYPASS + TX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for transmitted data. 12 1 read-write - I2S_TX_STOP_EN + TX_STOP_EN Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 13 1 read-write - I2S_TX_LEFT_ALIGN + TX_LEFT_ALIGN 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. 15 1 read-write - I2S_TX_24_FILL_EN + TX_24_FILL_EN 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode 16 1 read-write - I2S_TX_WS_IDLE_POL + TX_WS_IDLE_POL 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. 17 1 read-write - I2S_TX_BIT_ORDER + TX_BIT_ORDER I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. 18 1 read-write - I2S_TX_TDM_EN + TX_TDM_EN 1: Enable I2S TDM Tx mode . 0: Disable. 19 1 read-write - I2S_TX_PDM_EN + TX_PDM_EN 1: Enable I2S PDM Tx mode . 0: Disable. 20 1 read-write - I2S_TX_CHAN_MOD + TX_CHAN_MOD I2S transmitter channel mode configuration bits. 24 3 read-write - I2S_SIG_LOOPBACK + SIG_LOOPBACK Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. 27 1 @@ -15621,49 +15678,49 @@ level. - I2S_RX_CONF1 + RX_CONF1 I2S RX configure register 1 0x28 0x20 0x2F3DE300 - I2S_RX_TDM_WS_WIDTH + RX_TDM_WS_WIDTH The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write - I2S_RX_BCK_DIV_NUM + RX_BCK_DIV_NUM Bit clock configuration bits in receiver mode. 7 6 read-write - I2S_RX_BITS_MOD + RX_BITS_MOD Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write - I2S_RX_HALF_SAMPLE_BITS + RX_HALF_SAMPLE_BITS I2S Rx half sample bits -1. 18 6 read-write - I2S_RX_TDM_CHAN_BITS + RX_TDM_CHAN_BITS The Rx bit number for each channel minus 1in TDM mode. 24 5 read-write - I2S_RX_MSB_SHIFT + RX_MSB_SHIFT Set this bit to enable receiver in Phillips standard mode 29 1 @@ -15672,56 +15729,56 @@ level. - I2S_TX_CONF1 + TX_CONF1 I2S TX configure register 1 0x2C 0x20 0x6F3DE300 - I2S_TX_TDM_WS_WIDTH + TX_TDM_WS_WIDTH The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write - I2S_TX_BCK_DIV_NUM + TX_BCK_DIV_NUM Bit clock configuration bits in transmitter mode. 7 6 read-write - I2S_TX_BITS_MOD + TX_BITS_MOD Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write - I2S_TX_HALF_SAMPLE_BITS + TX_HALF_SAMPLE_BITS I2S Tx half sample bits -1. 18 6 read-write - I2S_TX_TDM_CHAN_BITS + TX_TDM_CHAN_BITS The Tx bit number for each channel minus 1in TDM mode. 24 5 read-write - I2S_TX_MSB_SHIFT + TX_MSB_SHIFT Set this bit to enable transmitter in Phillips standard mode 29 1 read-write - I2S_TX_BCK_NO_DLY + TX_BCK_NO_DLY 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. 30 1 @@ -15730,35 +15787,35 @@ level. - I2S_RX_CLKM_CONF + RX_CLKM_CONF I2S RX clock configure register 0x30 0x20 0x00000002 - I2S_RX_CLKM_DIV_NUM + RX_CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write - I2S_RX_CLK_ACTIVE + RX_CLK_ACTIVE I2S Rx module clock enable signal. 26 1 read-write - I2S_RX_CLK_SEL + RX_CLK_SEL Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write - I2S_MCLK_SEL + MCLK_SEL 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. 29 1 @@ -15767,35 +15824,35 @@ level. - I2S_TX_CLKM_CONF + TX_CLKM_CONF I2S TX clock configure register 0x34 0x20 0x00000002 - I2S_TX_CLKM_DIV_NUM + TX_CLKM_DIV_NUM Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. 0 8 read-write - I2S_TX_CLK_ACTIVE + TX_CLK_ACTIVE I2S Tx module clock enable signal. 26 1 read-write - I2S_TX_CLK_SEL + TX_CLK_SEL Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write - I2S_CLK_EN + CLK_EN Set this bit to enable clk gate 29 1 @@ -15804,35 +15861,35 @@ level. - I2S_RX_CLKM_DIV_CONF + RX_CLKM_DIV_CONF I2S RX module clock divider configure register 0x38 0x20 0x00000200 - I2S_RX_CLKM_DIV_Z + RX_CLKM_DIV_Z For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). 0 9 read-write - I2S_RX_CLKM_DIV_Y + RX_CLKM_DIV_Y For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write - I2S_RX_CLKM_DIV_X + RX_CLKM_DIV_X For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write - I2S_RX_CLKM_DIV_YN1 + RX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. 27 1 @@ -15841,35 +15898,35 @@ level. - I2S_TX_CLKM_DIV_CONF + TX_CLKM_DIV_CONF I2S TX module clock divider configure register 0x3C 0x20 0x00000200 - I2S_TX_CLKM_DIV_Z + TX_CLKM_DIV_Z For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). 0 9 read-write - I2S_TX_CLKM_DIV_Y + TX_CLKM_DIV_Y For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write - I2S_TX_CLKM_DIV_X + TX_CLKM_DIV_X For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write - I2S_TX_CLKM_DIV_YN1 + TX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. 27 1 @@ -15878,126 +15935,126 @@ level. - I2S_RX_TDM_CTRL + RX_TDM_CTRL I2S TX TDM mode control register 0x50 0x20 0x0000FFFF - I2S_RX_TDM_PDM_CHAN0_EN + RX_TDM_PDM_CHAN0_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 read-write - I2S_RX_TDM_PDM_CHAN1_EN + RX_TDM_PDM_CHAN1_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 read-write - I2S_RX_TDM_PDM_CHAN2_EN + RX_TDM_PDM_CHAN2_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 read-write - I2S_RX_TDM_PDM_CHAN3_EN + RX_TDM_PDM_CHAN3_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 read-write - I2S_RX_TDM_PDM_CHAN4_EN + RX_TDM_PDM_CHAN4_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 read-write - I2S_RX_TDM_PDM_CHAN5_EN + RX_TDM_PDM_CHAN5_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 1 read-write - I2S_RX_TDM_PDM_CHAN6_EN + RX_TDM_PDM_CHAN6_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. 6 1 read-write - I2S_RX_TDM_PDM_CHAN7_EN + RX_TDM_PDM_CHAN7_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 read-write - I2S_RX_TDM_CHAN8_EN + RX_TDM_CHAN8_EN 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 read-write - I2S_RX_TDM_CHAN9_EN + RX_TDM_CHAN9_EN 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 read-write - I2S_RX_TDM_CHAN10_EN + RX_TDM_CHAN10_EN 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 1 read-write - I2S_RX_TDM_CHAN11_EN + RX_TDM_CHAN11_EN 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. 11 1 read-write - I2S_RX_TDM_CHAN12_EN + RX_TDM_CHAN12_EN 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 1 read-write - I2S_RX_TDM_CHAN13_EN + RX_TDM_CHAN13_EN 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. 13 1 read-write - I2S_RX_TDM_CHAN14_EN + RX_TDM_CHAN14_EN 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. 14 1 read-write - I2S_RX_TDM_CHAN15_EN + RX_TDM_CHAN15_EN 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 read-write - I2S_RX_TDM_TOT_CHAN_NUM + RX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 @@ -16006,133 +16063,133 @@ level. - I2S_TX_TDM_CTRL + TX_TDM_CTRL I2S TX TDM mode control register 0x54 0x20 0x0000FFFF - I2S_TX_TDM_CHAN0_EN + TX_TDM_CHAN0_EN 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 read-write - I2S_TX_TDM_CHAN1_EN + TX_TDM_CHAN1_EN 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 read-write - I2S_TX_TDM_CHAN2_EN + TX_TDM_CHAN2_EN 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 read-write - I2S_TX_TDM_CHAN3_EN + TX_TDM_CHAN3_EN 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 read-write - I2S_TX_TDM_CHAN4_EN + TX_TDM_CHAN4_EN 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 read-write - I2S_TX_TDM_CHAN5_EN + TX_TDM_CHAN5_EN 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 1 read-write - I2S_TX_TDM_CHAN6_EN + TX_TDM_CHAN6_EN 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. 6 1 read-write - I2S_TX_TDM_CHAN7_EN + TX_TDM_CHAN7_EN 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 read-write - I2S_TX_TDM_CHAN8_EN + TX_TDM_CHAN8_EN 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 read-write - I2S_TX_TDM_CHAN9_EN + TX_TDM_CHAN9_EN 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 read-write - I2S_TX_TDM_CHAN10_EN + TX_TDM_CHAN10_EN 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 1 read-write - I2S_TX_TDM_CHAN11_EN + TX_TDM_CHAN11_EN 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. 11 1 read-write - I2S_TX_TDM_CHAN12_EN + TX_TDM_CHAN12_EN 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. 12 1 read-write - I2S_TX_TDM_CHAN13_EN + TX_TDM_CHAN13_EN 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. 13 1 read-write - I2S_TX_TDM_CHAN14_EN + TX_TDM_CHAN14_EN 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. 14 1 read-write - I2S_TX_TDM_CHAN15_EN + TX_TDM_CHAN15_EN 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. 15 1 read-write - I2S_TX_TDM_TOT_CHAN_NUM + TX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write - I2S_TX_TDM_SKIP_MSK_EN + TX_TDM_SKIP_MSK_EN When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. 20 1 @@ -16141,41 +16198,41 @@ level. - I2S_RX_TIMING + RX_TIMING I2S RX timing control register 0x58 0x20 - I2S_RX_SD_IN_DM + RX_SD_IN_DM The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write - I2S_RX_WS_OUT_DM + RX_WS_OUT_DM The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write - I2S_RX_BCK_OUT_DM + RX_BCK_OUT_DM The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write - I2S_RX_WS_IN_DM + RX_WS_IN_DM The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write - I2S_RX_BCK_IN_DM + RX_BCK_IN_DM The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 @@ -16184,48 +16241,48 @@ level. - I2S_TX_TIMING + TX_TIMING I2S TX timing control register 0x5C 0x20 - I2S_TX_SD_OUT_DM + TX_SD_OUT_DM The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write - I2S_TX_SD1_OUT_DM + TX_SD1_OUT_DM The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 2 read-write - I2S_TX_WS_OUT_DM + TX_WS_OUT_DM The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write - I2S_TX_BCK_OUT_DM + TX_BCK_OUT_DM The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write - I2S_TX_WS_IN_DM + TX_WS_IN_DM The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write - I2S_TX_BCK_IN_DM + TX_BCK_IN_DM The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 @@ -16234,28 +16291,28 @@ level. - I2S_LC_HUNG_CONF + LC_HUNG_CONF I2S HUNG configure register. 0x60 0x20 0x00000810 - I2S_LC_FIFO_TIMEOUT + LC_FIFO_TIMEOUT the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value 0 8 read-write - I2S_LC_FIFO_TIMEOUT_SHIFT + LC_FIFO_TIMEOUT_SHIFT The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift 8 3 read-write - I2S_LC_FIFO_TIMEOUT_ENA + LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout 11 1 @@ -16264,14 +16321,14 @@ level. - I2S_RXEOF_NUM + RXEOF_NUM I2S RX data number control register. 0x64 0x20 0x00000040 - I2S_RX_EOF_NUM + RX_EOF_NUM The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 0 12 @@ -16280,13 +16337,13 @@ level. - I2S_CONF_SIGLE_DATA + CONF_SIGLE_DATA I2S signal data register 0x68 0x20 - I2S_SINGLE_DATA + SINGLE_DATA The configured constant channel data to be sent out. 0 32 @@ -16295,14 +16352,14 @@ level. - I2S_STATE + STATE I2S TX status register 0x6C 0x20 0x00000001 - I2S_TX_IDLE + TX_IDLE 1: i2s_tx is idle state. 0: i2s_tx is working. 0 1 @@ -16311,14 +16368,14 @@ level. - I2S_DATE + DATE Version control register 0x80 0x20 0x02009070 - I2S_DATE + DATE I2S version control register 0 28 @@ -16330,7 +16387,7 @@ level. INTERRUPT_CORE0 - Interrupt Core + Interrupt Controller (Core 0) INTERRUPT_CORE0 0x600C2000 @@ -16339,19 +16396,115 @@ level. registers - CORE_0_IRAM0_PMS_MONITOR_VIOLATE + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SLC0 + 12 + + + SLC1 + 13 + + + SDIO_HOST + 30 + + + WDT + 47 + + + CACHE_IA + 56 + + + DCACHE_PRELOAD0 + 61 + + + ICACHE_PRELOAD0 + 62 + + + DCACHE_SYNC0 + 63 + + + ICACHE_SYNC0 + 64 + + + FROM_CPU_INTR0 + 79 + + + FROM_CPU_INTR1 + 80 + + + FROM_CPU_INTR2 + 81 + + + FROM_CPU_INTR3 + 82 + + + CORE0_IRAM0_PMS 85 - CORE_0_DRAM0_PMS_MONITOR_VIOLATE + CORE0_DRAM0_PMS 86 - CORE_0_PIF_PMS_MONITOR_VIOLATE + CORE0_PIF_PMS 87 - CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE + CORE0_PIF_PMS_SIZE 88 @@ -17989,7 +18142,7 @@ level. - INTR_STATUS_3 + PRO_INTR_STATUS_3 interrupt status register 0x198 0x20 @@ -18039,28 +18192,28 @@ level. INTERRUPT_CORE1 - Interrupt Core + Interrupt Controller (Core 1) INTERRUPT_CORE1 - 0x600C2800 + 0x600C2000 0x0 0x1A4 registers - CORE_1_IRAM0_PMS_MONITOR_VIOLATE + CORE1_IRAM0_PMS 89 - CORE_1_DRAM0_PMS_MONITOR_VIOLATE + CORE1_DRAM0_PMS 90 - CORE_1_PIF_PMS_MONITOR_VIOLATE + CORE1_PIF_PMS 91 - CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE + CORE1_PIF_PMS_SIZE 92 @@ -19698,7 +19851,7 @@ level. - INTR_STATUS_3 + APP_INTR_STATUS_3 interrupt status register 0x998 0x20 @@ -19895,7 +20048,7 @@ level. LCD_CAM - Peripheral LCD_CAM + Camera/LCD Controller LCD_CAM 0x60041000 @@ -19903,73 +20056,79 @@ level. 0x48 registers + + LCD_CAM + 24 + LCD_CLOCK - LCD clock register + LCD clock configuration register 0x0 0x20 - 0x00000843 LCD_CLKCNT_N - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + f<SUB>LCD_PCLK</SUB> + = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0. 0 6 read-write LCD_CLK_EQU_SYSCLK - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 1: f<SUB>LCD_PCLK</SUB> += f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> + = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1). 6 1 read-write LCD_CK_IDLE_EDGE - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle. 7 1 read-write LCD_CK_OUT_EDGE - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle. + 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle. 8 1 read-write LCD_CLKM_DIV_NUM - Integral LCD clock divider value + Integral LCD clock divider value. 9 8 read-write LCD_CLKM_DIV_B - Fractional clock divider numerator value + Fractional clock divider numerator value. 17 6 read-write LCD_CLKM_DIV_A - Fractional clock divider denominator value + Fractional clock divider denominator value. 23 6 read-write LCD_CLK_SEL - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. 29 2 read-write CLK_EN - Set this bit to enable clk gate + Set this bit to force enable the clock for all configuration registers. Clock gate is not used. 31 1 read-write @@ -19978,14 +20137,13 @@ level. CAM_CTRL - Camera configuration register + Camera clock configuration register 0x4 0x20 - 0x00000800 CAM_STOP_EN - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop. 0 1 read-write @@ -19999,63 +20157,63 @@ level. CAM_UPDATE - 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 1: Update camera registers. This bit is cleared by hardware. 0: Do not care. 4 1 read-write CAM_BYTE_ORDER - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change. 5 1 read-write CAM_BIT_ORDER - 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. 6 1 read-write CAM_LINE_INT_EN - 1: Enable to generate CAM_HS_INT. 0: Disable. + 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable. 7 1 read-write CAM_VS_EOF_EN - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN. 8 1 read-write CAM_CLKM_DIV_NUM - Integral Camera clock divider value + Integral camera clock divider value. 9 8 read-write CAM_CLKM_DIV_B - Fractional clock divider numerator value + Fractional clock divider numerator value. 17 6 read-write CAM_CLKM_DIV_A - Fractional clock divider denominator value + Fractional clock divider denominator value. 23 6 read-write CAM_CLK_SEL - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. 29 2 read-write @@ -20064,41 +20222,41 @@ level. CAM_CTRL1 - Camera configuration register + Camera control register 0x8 0x20 CAM_REC_DATA_BYTELEN - Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered. 0 16 read-write CAM_LINE_INT_NUM - The line number minus 1 to generate cam_hs_int. + Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered. 16 6 read-write CAM_CLK_INV - 1: Invert the input signal CAM_PCLK. 0: Not invert. + 1: Invert the input signal CAM_PCLK. 0: Do not invert. 22 1 read-write CAM_VSYNC_FILTER_EN - 1: Enable CAM_VSYNC filter function. 0: bypass. + 1: Enable CAM_VSYNC filter function. 0: Bypass. 23 1 read-write CAM_2BYTE_EN - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 1: The width of input data is 16 bits. 0: The width of input data is 8 bits. 24 1 read-write @@ -20126,7 +20284,7 @@ level. CAM_VH_DE_MODE_EN - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + 1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same time. 28 1 read-write @@ -20147,7 +20305,7 @@ level. CAM_AFIFO_RESET - Camera AFIFO reset signal. + Camera Async Rx FIFO reset signal. 31 1 write-only @@ -20156,63 +20314,62 @@ level. CAM_RGB_YUV - Camera configuration register + Camera data format conversion register 0xC 0x20 - 0x00C00000 CAM_CONV_8BITS_DATA_INV - 1:invert every two 8bits input data. 2. disabled. + Swap every two 8-bit input data. 1: Enabled. 0: Disabled. 21 1 read-write CAM_CONV_YUV2YUV_MODE - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1. 22 2 read-write CAM_CONV_YUV_MODE - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 24 2 read-write CAM_CONV_PROTOCOL_MODE - 0:BT601. 1:BT709. + 0: BT601. 1: BT709. 26 1 read-write CAM_CONV_DATA_OUT_MODE - LIMIT or FULL mode of Data out. 0: limit. 1: full + Configure color range for output data. 0: limited color range. 1: full color range. 27 1 read-write CAM_CONV_DATA_IN_MODE - LIMIT or FULL mode of Data in. 0: limit. 1: full + Configure color range for input data. 0: limited color range. 1: full color range. 28 1 read-write CAM_CONV_MODE_8BITS_ON - 0: 16bits mode. 1: 8bits mode. + 0: 16-bit mode. 1: 8-bit mode. 29 1 read-write CAM_CONV_TRANS_MODE - 0: YUV to RGB. 1: RGB to YUV. + 0: converted to RGB format. 1: converted to YUV format. 30 1 read-write @@ -20228,70 +20385,62 @@ level. LCD_RGB_YUV - LCD configuration register + LCD data format conversion register 0x10 0x20 - 0x00C00000 LCD_CONV_8BITS_DATA_INV - 1:invert every two 8bits input data. 2. disabled. + Swap every two 8-bit input data. 1: Enabled. 0: Disabled. 20 1 read-write - - LCD_CONV_TXTORX - 0: txtorx mode off. 1: txtorx mode on. - 21 - 1 - read-write - LCD_CONV_YUV2YUV_MODE - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1. 22 2 read-write LCD_CONV_YUV_MODE - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 24 2 read-write LCD_CONV_PROTOCOL_MODE - 0:BT601. 1:BT709. + 0: BT601. 1: BT709. 26 1 read-write LCD_CONV_DATA_OUT_MODE - LIMIT or FULL mode of Data out. 0: limit. 1: full + Configure color range for output data. 0: limited color range. 1: full color range. 27 1 read-write LCD_CONV_DATA_IN_MODE - LIMIT or FULL mode of Data in. 0: limit. 1: full + Configure color range for input data. 0: limited color range. 1: full color range. 28 1 read-write LCD_CONV_MODE_8BITS_ON - 0: 16bits mode. 1: 8bits mode. + 0: 16-bit mode. 1: 8-bit mode. 29 1 read-write LCD_CONV_TRANS_MODE - 0: YUV to RGB. 1: RGB to YUV. + 0: converted to RGB format. 1: converted to YUV format. 30 1 read-write @@ -20307,56 +20456,55 @@ level. LCD_USER - LCD configuration register + LCD user configuration register 0x14 0x20 - 0x00000001 LCD_DOUT_CYCLELEN - The output data cycles minus 1 of LCD module. + Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1. 0 13 read-write LCD_ALWAYS_OUT_EN - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set. 13 1 read-write LCD_8BITS_ORDER - 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap. 19 1 read-write LCD_UPDATE - 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 1: Update LCD registers. This bit is cleared by hardware. 0: Do not care. 20 1 read-write LCD_BIT_ORDER - 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 1: Change data bit order. Change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. 21 1 read-write LCD_BYTE_ORDER - 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert. 22 1 read-write LCD_2BYTE_EN - 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8. + 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits. 23 1 read-write @@ -20384,28 +20532,28 @@ level. LCD_START - LCD start sending data enable signal, valid in high level. + LCD starts sending data enable signal, valid in high level. 27 1 read-write LCD_RESET - The value of command. + Reset LCD module. 28 1 write-only LCD_DUMMY_CYCLELEN - The dummy cycle length minus 1. + Configure DUMMY cycles. DUMMY cycles = this value + 1. 29 2 read-write LCD_CMD_2_CYCLE_EN - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. 31 1 read-write @@ -20414,28 +20562,28 @@ level. LCD_MISC - LCD configuration register + LCD MISC configuration register 0x18 0x20 - 0x000000D6 + 0x00000022 LCD_AFIFO_THRESHOLD_NUM - The awfull threshold number of lcd_afifo. + Set the threshold for Async Tx FIFO full event. 1 5 read-write LCD_VFK_CYCLELEN - The setup cycle length minus 1 in LCD non-RGB mode. + Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1. 6 6 read-write LCD_VBK_CYCLELEN - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1. 12 13 read-write @@ -20456,28 +20604,28 @@ level. LCD_AFIFO_RESET - LCD AFIFO reset signal. + Async Tx FIFO reset signal. 27 1 write-only LCD_CD_DATA_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE. 28 1 read-write LCD_CD_DUMMY_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE. 29 1 read-write LCD_CD_CMD_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE. 30 1 read-write @@ -20493,7 +20641,7 @@ level. LCD_CTRL - LCD configuration register + LCD signal configuration register 0x1C 0x20 @@ -20520,7 +20668,7 @@ level. LCD_RGB_MODE_EN - 1: Enable reg mode input vsync, hsync, de. 0: Disable. + 1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable. 31 1 read-write @@ -20529,7 +20677,7 @@ level. LCD_CTRL1 - LCD configuration register + LCD signal configuration register 1 0x20 0x20 @@ -20558,14 +20706,13 @@ level. LCD_CTRL2 - LCD configuration register + LCD signal configuration register 2 0x24 0x20 - 0x00010001 LCD_VSYNC_WIDTH - It is the position of LCD_VSYNC active pulse in a line. + It is the width of LCD_VSYNC active pulse in a line. 0 7 read-write @@ -20586,14 +20733,14 @@ level. LCD_HS_BLANK_EN - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. 9 1 read-write LCD_HSYNC_WIDTH - It is the position of LCD_HSYNC active pulse in a line. + It is the width of LCD_HSYNC active pulse in a line. 16 7 read-write @@ -20616,7 +20763,7 @@ level. LCD_CMD_VAL - LCD configuration register + LCD command value configuration register 0x28 0x20 @@ -20631,34 +20778,34 @@ level. LCD_DLY_MODE - LCD configuration register + LCD signal delay configuration register 0x30 0x20 LCD_CD_MODE - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 0 2 read-write LCD_DE_MODE - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 2 2 read-write LCD_HSYNC_MODE - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 4 2 read-write LCD_VSYNC_MODE - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK. 6 2 read-write @@ -20667,118 +20814,118 @@ level. LCD_DATA_DOUT_MODE - LCD configuration register + LCD data delay configuration register 0x38 0x20 DOUT0_MODE - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 0 2 read-write DOUT1_MODE - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 2 2 read-write DOUT2_MODE - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 4 2 read-write DOUT3_MODE - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 6 2 read-write DOUT4_MODE - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 8 2 read-write DOUT5_MODE - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 10 2 read-write DOUT6_MODE - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 12 2 read-write DOUT7_MODE - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 14 2 read-write DOUT8_MODE - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 16 2 read-write DOUT9_MODE - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 18 2 read-write DOUT10_MODE - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 20 2 read-write DOUT11_MODE - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 22 2 read-write DOUT12_MODE - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 24 2 read-write DOUT13_MODE - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 26 2 read-write DOUT14_MODE - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 28 2 read-write DOUT15_MODE - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. 30 2 read-write @@ -20787,34 +20934,34 @@ level. LC_DMA_INT_ENA - LCD_camera DMA inturrupt enable register + LCD_CAM GDMA interrupt enable register 0x64 0x20 LCD_VSYNC_INT_ENA - The enable bit for LCD frame end interrupt. + The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt. 0 1 read-write LCD_TRANS_DONE_INT_ENA - The enable bit for lcd transfer end interrupt. + The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. 1 1 read-write CAM_VSYNC_INT_ENA - The enable bit for Camera frame end interrupt. + The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt. 2 1 read-write CAM_HS_INT_ENA - The enable bit for Camera line interrupt. + The enable bit for LCD_CAM_CAM_HS_INT interrupt. 3 1 read-write @@ -20823,34 +20970,34 @@ level. LC_DMA_INT_RAW - LCD_camera DMA raw inturrupt status register + LCD_CAM GDMA raw interrupt status register 0x68 0x20 LCD_VSYNC_INT_RAW - The raw bit for LCD frame end interrupt. + The raw bit for LCD_CAM_LCD_VSYNC_INT interrupt. 0 1 read-only LCD_TRANS_DONE_INT_RAW - The raw bit for lcd transfer end interrupt. + The raw bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. 1 1 read-only CAM_VSYNC_INT_RAW - The raw bit for Camera frame end interrupt. + The raw bit for LCD_CAM_CAM_VSYNC_INT interrupt. 2 1 read-only CAM_HS_INT_RAW - The raw bit for Camera line interrupt. + The raw bit for LCD_CAM_CAM_HS_INT interrupt. 3 1 read-only @@ -20859,34 +21006,34 @@ level. LC_DMA_INT_ST - LCD_camera DMA masked inturrupt status register + LCD_CAM GDMA masked interrupt status register 0x6C 0x20 LCD_VSYNC_INT_ST - The status bit for LCD frame end interrupt. + The status bit for LCD_CAM_LCD_VSYNC_INT interrupt. 0 1 read-only LCD_TRANS_DONE_INT_ST - The status bit for lcd transfer end interrupt. + The status bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. 1 1 read-only CAM_VSYNC_INT_ST - The status bit for Camera frame end interrupt. + The status bit for LCD_CAM_CAM_VSYNC_INT interrupt. 2 1 read-only CAM_HS_INT_ST - The status bit for Camera transfer end interrupt. + The status bit for LCD_CAM_CAM_HS_INT interrupt. 3 1 read-only @@ -20895,34 +21042,34 @@ level. LC_DMA_INT_CLR - LCD_camera DMA inturrupt clear register + LCD_CAM GDMA interrupt clear register 0x70 0x20 LCD_VSYNC_INT_CLR - The clear bit for LCD frame end interrupt. + The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt. 0 1 write-only LCD_TRANS_DONE_INT_CLR - The clear bit for lcd transfer end interrupt. + The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. 1 1 write-only CAM_VSYNC_INT_CLR - The clear bit for Camera frame end interrupt. + The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt. 2 1 write-only CAM_HS_INT_CLR - The clear bit for Camera line interrupt. + The clear bit for LCD_CAM_CAM_HS_INT interrupt. 3 1 write-only @@ -20931,14 +21078,14 @@ level. LC_REG_DATE - Version register + Version control register 0xFC 0x20 0x02003020 LC_DATE - LCD_CAM version control register + Version control register 0 28 read-write @@ -20949,7 +21096,7 @@ level. LEDC - LED PWM (Pulse Width Modulation) Controller + LED Control PWM (Pulse Width Modulation) LEDC 0x60019000 @@ -20961,6 +21108,14 @@ level. LEDC 35 + + TIMER1 + 48 + + + TIMER2 + 49 + 8 @@ -20971,7 +21126,7 @@ level. 0x20 - TIMER_SEL_CH0 + TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer0 @@ -20986,28 +21141,28 @@ level. read-write - SIG_OUT_EN_CH0 + SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write - IDLE_LV_CH0 + IDLE_LV This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write - PARA_UP_CH0 + PARA_UP This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only - OVF_NUM_CH0 + OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. @@ -21016,25 +21171,25 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows read-write - OVF_CNT_EN_CH0 + OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write - OVF_CNT_RESET_CH0 + OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only - OVF_CNT_RESET_ST_CH0 + OVF_CNT_RESET_ST This is the status bit of LEDC_OVF_CNT_RESET_CH%s. 17 1 - read-only + read-write @@ -21047,7 +21202,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - HPOINT_CH0 + HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 @@ -21064,7 +21219,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - DUTY_CH0 + DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. @@ -21084,35 +21239,35 @@ The output value turns to low when the selected timers has reached the Lpoint.0x40000000 - DUTY_SCALE_CH0 + DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write - DUTY_CYCLE_CH0 + DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write - DUTY_NUM_CH0 + DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write - DUTY_INC_CH0 + DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. 30 1 read-write - DUTY_START_CH0 + DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 @@ -21129,7 +21284,7 @@ The output value turns to low when the selected timers has reached the Lpoint.0x20 - DUTY_R_CH0 + DUTY_R This register stores the current duty of output signal on channel %s. 0 19 @@ -21147,14 +21302,14 @@ The output value turns to low when the selected timers has reached the Lpoint.0x00800000 - TIMER0_DUTY_RES + DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write - CLK_DIV_TIMER0 + CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. @@ -21163,21 +21318,21 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PAUSE + PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write - TIMER0_RST + RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write - TICK_SEL_TIMER0 + TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK @@ -21186,7 +21341,7 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PARA_UP + PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 @@ -21203,7 +21358,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_CNT + CNT This register stores the current counter value of timer %s. 0 14 @@ -21222,140 +21377,140 @@ The least significant eight bits represent the fractional part. Triggered when the timer0 has reached its maximum counter value. 0 1 - read-only + read-write TIMER1_OVF_INT_RAW Triggered when the timer1 has reached its maximum counter value. 1 1 - read-only + read-write TIMER2_OVF_INT_RAW Triggered when the timer2 has reached its maximum counter value. 2 1 - read-only + read-write TIMER3_OVF_INT_RAW Triggered when the timer3 has reached its maximum counter value. 3 1 - read-only + read-write DUTY_CHNG_END_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 - read-only + read-write DUTY_CHNG_END_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 - read-only + read-write DUTY_CHNG_END_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. 6 1 - read-only + read-write DUTY_CHNG_END_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. 7 1 - read-only + read-write DUTY_CHNG_END_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. 8 1 - read-only + read-write DUTY_CHNG_END_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. 9 1 - read-only + read-write DUTY_CHNG_END_CH6_INT_RAW Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. 10 1 - read-only + read-write DUTY_CHNG_END_CH7_INT_RAW Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. 11 1 - read-only + read-write OVF_CNT_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 12 1 - read-only + read-write OVF_CNT_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 13 1 - read-only + read-write OVF_CNT_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. 14 1 - read-only + read-write OVF_CNT_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. 15 1 - read-only + read-write OVF_CNT_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. 16 1 - read-only + read-write OVF_CNT_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. 17 1 - read-only + read-write OVF_CNT_CH6_INT_RAW Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. 18 1 - read-only + read-write OVF_CNT_CH7_INT_RAW Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. 19 1 - read-only + read-write @@ -21872,7 +22027,7 @@ The least significant eight bits represent the fractional part. 0x00003C10 - FILTER_THRES_U + FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. @@ -21881,49 +22036,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - FILTER_EN_U + FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write - THR_ZERO_EN_U + THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write - THR_H_LIM_EN_U + THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. 12 1 read-write - THR_L_LIM_EN_U + THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. 13 1 read-write - THR_THRES0_EN_U + THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write - THR_THRES1_EN_U + THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write - CH0_NEG_MODE_U + CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter @@ -21932,7 +22087,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_POS_MODE_U + CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter @@ -21941,7 +22096,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_HCTRL_MODE_U + CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -21950,7 +22105,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_LCTRL_MODE_U + CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -21959,7 +22114,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_NEG_MODE_U + CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter @@ -21968,7 +22123,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_POS_MODE_U + CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter @@ -21977,7 +22132,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_HCTRL_MODE_U + CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -21986,7 +22141,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_LCTRL_MODE_U + CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -22005,14 +22160,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THRES0_U + CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write - CNT_THRES1_U + CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 @@ -22029,14 +22184,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_H_LIM_U + CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. 0 16 read-write - CNT_L_LIM_U + CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. 16 16 @@ -22053,7 +22208,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - PULSE_CNT_U + CNT This register stores the current pulse count value for unit %s. 0 16 @@ -22068,28 +22223,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22104,28 +22259,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22140,28 +22295,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22176,28 +22331,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22214,42 +22369,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_ZERO_MODE_U + ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only - CNT_THR_THRES1_LAT_U + THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others 2 1 read-only - CNT_THR_THRES0_LAT_U + THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others 3 1 read-only - CNT_THR_L_LIM_LAT_U + L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others 4 1 read-only - CNT_THR_H_LIM_LAT_U + H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others 5 1 read-only - CNT_THR_ZERO_LAT_U + ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others 6 1 @@ -22265,7 +22420,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000001 - PULSE_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 @@ -22279,7 +22434,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit 1's counter. 2 1 @@ -22293,7 +22448,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit 2's counter. 4 1 @@ -22307,7 +22462,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit 3's counter. 6 1 @@ -22349,7 +22504,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. PERI_BACKUP - Peripheral PERI_BACKUP + PERI_BACKUP Peripheral PERI_BACKUP 0x6002A000 @@ -22631,8 +22786,8 @@ Any pulses with width less than this will be ignored when the filter is enabled. - PWM0 - Peripheral PWM0 + MCPWM0 + Motor Control Pulse-Width Modulation 0 PWM 0x6001E000 @@ -22641,7 +22796,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. registers - PWM0 + MCPWM0 31 @@ -22743,7 +22898,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER0_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -22853,7 +23015,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER1_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -22963,7 +23132,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER2_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -23094,14 +23270,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value 8 1 - read-only + read-write CMPR0_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value 9 1 - read-only + read-write @@ -23782,14 +23958,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value 8 1 - read-only + read-write CMPR1_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value 9 1 - read-only + read-write @@ -24470,14 +24646,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value 8 1 - read-only + read-write CMPR2_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value 9 1 - read-only + read-write @@ -25752,210 +25928,210 @@ Any pulses with width less than this will be ignored when the filter is enabled. The raw status bit for the interrupt triggered when the timer 0 stops. 0 1 - read-only + read-write TIMER1_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 1 stops. 1 1 - read-only + read-write TIMER2_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 2 stops. 2 1 - read-only + read-write TIMER0_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. 3 1 - read-only + read-write TIMER1_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. 4 1 - read-only + read-write TIMER2_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. 5 1 - read-only + read-write TIMER0_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. 6 1 - read-only + read-write TIMER1_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. 7 1 - read-only + read-write TIMER2_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. 8 1 - read-only + read-write FAULT0_INT_RAW The raw status bit for the interrupt triggered when event_f0 starts. 9 1 - read-only + read-write FAULT1_INT_RAW The raw status bit for the interrupt triggered when event_f1 starts. 10 1 - read-only + read-write FAULT2_INT_RAW The raw status bit for the interrupt triggered when event_f2 starts. 11 1 - read-only + read-write FAULT0_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f0 ends. 12 1 - read-only + read-write FAULT1_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f1 ends. 13 1 - read-only + read-write FAULT2_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f2 ends. 14 1 - read-only + read-write CMPR0_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEA event 15 1 - read-only + read-write CMPR1_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEA event 16 1 - read-only + read-write CMPR2_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEA event 17 1 - read-only + read-write CMPR0_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEB event 18 1 - read-only + read-write CMPR1_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEB event 19 1 - read-only + read-write CMPR2_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEB event 20 1 - read-only + read-write TZ0_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. 21 1 - read-only + read-write TZ1_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. 22 1 - read-only + read-write TZ2_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. 23 1 - read-only + read-write TZ0_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. 24 1 - read-only + read-write TZ1_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. 25 1 - read-only + read-write TZ2_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. 26 1 - read-only + read-write CAP0_INT_RAW The raw status bit for the interrupt triggered by capture on channel 0. 27 1 - read-only + read-write CAP1_INT_RAW The raw status bit for the interrupt triggered by capture on channel 1. 28 1 - read-only + read-write CAP2_INT_RAW The raw status bit for the interrupt triggered by capture on channel 2. 29 1 - read-only + read-write @@ -26428,17 +26604,18 @@ Any pulses with width less than this will be ignored when the filter is enabled. - - PWM1 + + MCPWM1 + Motor Control Pulse-Width Modulation 1 0x6002C000 - PWM1 + MCPWM1 32 RMT - Remote control + Remote Control RMT 0x60016000 @@ -26452,36 +26629,19 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 4 + 8 0x4 - TX_CH%sDATA + CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 - CHDATA + DATA Read and write data for channel %s via APB FIFO. 0 32 - read-only - - - - - 4 - 0x4 - RX_CH%sDATA - The read and write data register for CHANNEL$n by apb fifo access. - 0x10 - 0x20 - - - CHDATA - Read and write data for channel 0 via APB FIFO. - 0 - 32 - read-only + read-write @@ -26608,6 +26768,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x8 + 4-7 CH%s_RX_CONF0 Channel %s configure register 0 0x30 @@ -26658,6 +26819,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x8 + 4-7 CH%s_RX_CONF1 Channel %s configure register 1 0x34 @@ -26841,103 +27003,85 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_RAW + CH%s_TX_END The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 - read-only + read-write 4 0x1 0-3 - CH%s_TX_ERR_INT_RAW + CH%s_TX_ERR The interrupt raw bit for CHANNEL%s. Triggered when error occurs. 4 1 - read-only + read-write 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 8 1 - read-only + read-write 4 0x1 0-3 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 12 1 - read-only + read-write 4 0x1 - 0-3 - CH%s_RX_END_INT_RAW - The interrupt raw bit for CHANNEL%s. Triggered when reception done. + 4-7 + CH%s_RX_END + The interrupt raw bit for CHANNEL4. Triggered when reception done. 16 1 - read-only + read-write 4 0x1 - 0-3 - CH%s_RX_ERR_INT_RAW - The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + 4-7 + CH%s_RX_ERR + The interrupt raw bit for CHANNEL4. Triggered when error occurs. 20 1 - read-only + read-write - CH0_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when receiver receive more data than configured value. + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. 24 1 - read-only - - - CH1_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when receiver receive more data than configured value. - 25 - 1 - read-only - - - CH2_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. - 26 - 1 - read-only - - - CH3_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. - 27 - 1 - read-only + read-write - TX_CH0_DMA_ACCESS_FAIL_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when dma accessing CHANNEL0 fails. + TX_CH3_DMA_ACCESS_FAIL + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. 28 1 - read-only + read-write - RX_CH0_DMA_ACCESS_FAIL_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when dma accessing CHANNEL0 fails. + RX_CH7_DMA_ACCESS_FAIL + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. 29 1 - read-only + read-write @@ -26951,7 +27095,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_ST + CH%s_TX_END The masked interrupt status bit for CH%s_TX_END_INT. 0 1 @@ -26961,7 +27105,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_ST + CH%s_TX_ERR The masked interrupt status bit for CH%s_ERR_INT. 4 1 @@ -26971,7 +27115,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 8 1 @@ -26981,7 +27125,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ST + CH%s_TX_LOOP The masked interrupt status bit for CH%s_TX_LOOP_INT. 12 1 @@ -26990,9 +27134,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - 0-3 - CH%s_RX_END_INT_ST - The masked interrupt status bit for CH%s_RX_END_INT. + 4-7 + CH%s_RX_END + The masked interrupt status bit for CH4_RX_END_INT. 16 1 read-only @@ -27000,51 +27144,33 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - 0-3 - CH%s_RX_ERR_INT_ST - The masked interrupt status bit for CH%s_ERR_INT. + 4-7 + CH%s_RX_ERR + The masked interrupt status bit for CH4_ERR_INT. 20 1 read-only - CH0_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH0_RX_THR_EVENT_INT. + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. 24 1 read-only - CH1_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH1_RX_THR_EVENT_INT. - 25 - 1 - read-only - - - CH2_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH2_RX_THR_EVENT_INT. - 26 - 1 - read-only - - - CH3_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH3_RX_THR_EVENT_INT. - 27 - 1 - read-only - - - TX_CH0_DMA_ACCESS_FAIL_INT_ST - The masked interrupt status bit for CH0_DMA_ACCESS_FAIL_INT. + TX_CH3_DMA_ACCESS_FAIL + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. 28 1 read-only - RX_CH0_DMA_ACCESS_FAIL_INT_ST - The masked interrupt status bit for CH0_DMA_ACCESS_FAIL_INT. + RX_CH7_DMA_ACCESS_FAIL + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. 29 1 read-only @@ -27061,7 +27187,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_ENA + CH%s_TX_END The interrupt enable bit for CH%s_TX_END_INT. 0 1 @@ -27071,7 +27197,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_ENA + CH%s_TX_ERR The interrupt enable bit for CH%s_ERR_INT. 4 1 @@ -27081,7 +27207,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT The interrupt enable bit for CH%s_TX_THR_EVENT_INT. 8 1 @@ -27091,7 +27217,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ENA + CH%s_TX_LOOP The interrupt enable bit for CH%s_TX_LOOP_INT. 12 1 @@ -27100,9 +27226,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - 0-3 - CH%s_RX_END_INT_ENA - The interrupt enable bit for CH%s_RX_END_INT. + 4-7 + CH%s_RX_END + The interrupt enable bit for CH4_RX_END_INT. 16 1 read-write @@ -27110,51 +27236,33 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - 0-3 - CH%s_RX_ERR_INT_ENA - The interrupt enable bit for CH%s_ERR_INT. + 4-7 + CH%s_RX_ERR + The interrupt enable bit for CH4_ERR_INT. 20 1 read-write - CH0_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH0_RX_THR_EVENT_INT. + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT + The interrupt enable bit for CH4_RX_THR_EVENT_INT. 24 1 read-write - CH1_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH1_RX_THR_EVENT_INT. - 25 - 1 - read-write - - - CH2_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH2_RX_THR_EVENT_INT. - 26 - 1 - read-write - - - CH3_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH3_RX_THR_EVENT_INT. - 27 - 1 - read-write - - - TX_CH0_DMA_ACCESS_FAIL_INT_ENA - The interrupt enable bit for CH0_DMA_ACCESS_FAIL_INT. + TX_CH3_DMA_ACCESS_FAIL + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. 28 1 read-write - RX_CH0_DMA_ACCESS_FAIL_INT_ENA - The interrupt enable bit for CH0_DMA_ACCESS_FAIL_INT. + RX_CH7_DMA_ACCESS_FAIL + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. 29 1 read-write @@ -27171,7 +27279,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_CLR + CH%s_TX_END Set this bit to clear theCH%s_TX_END_INT interrupt. 0 1 @@ -27181,7 +27289,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_CLR + CH%s_TX_ERR Set this bit to clear theCH%s_ERR_INT interrupt. 4 1 @@ -27191,7 +27299,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. 8 1 @@ -27201,7 +27309,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_CLR + CH%s_TX_LOOP Set this bit to clear theCH%s_TX_LOOP_INT interrupt. 12 1 @@ -27210,9 +27318,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - 0-3 - CH%s_RX_END_INT_CLR - Set this bit to clear theCH%s_RX_END_INT interrupt. + 4-7 + CH%s_RX_END + Set this bit to clear theCH4_RX_END_INT interrupt. 16 1 write-only @@ -27220,51 +27328,33 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - RX_CH0,RX_CH1,RX_CH2,RX_CH3 - CH%s_RX_ERR_INT_CLR - Set this bit to clear theCH0_ERR_INT interrupt. + 4-7 + CH%s_RX_ERR + Set this bit to clear theCH4_ERR_INT interrupt. 20 1 write-only - CH0_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH0_RX_THR_EVENT_INT interrupt. + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. 24 1 write-only - CH1_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH1_RX_THR_EVENT_INT interrupt. - 25 - 1 - write-only - - - CH2_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. - 26 - 1 - write-only - - - CH3_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. - 27 - 1 - write-only - - - TX_CH0_DMA_ACCESS_FAIL_INT_CLR - Set this bit to clear the CH0_DMA_ACCESS_FAIL_INT interrupt. + TX_CH3_DMA_ACCESS_FAIL + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. 28 1 write-only - RX_CH0_DMA_ACCESS_FAIL_INT_CLR - Set this bit to clear the CH0_DMA_ACCESS_FAIL_INT interrupt. + RX_CH7_DMA_ACCESS_FAIL + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. 29 1 write-only @@ -27515,9 +27605,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. 8 0x1 - TX_CH0,TX_CH1,TX_CH2,TX_CH3,RX_CH0,RX_CH1,RX_CH2,RX_CH3 + 0-7 CH%s - This register is used to reset the clock divider of CHANNEL0. + This register is used to reset the clock divider of CHANNEL%s. 0 1 write-only @@ -27544,7 +27634,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RNG - Hardware random number generator + Hardware Random Number Generator RNG 0x60034F6C @@ -27558,6 +27648,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. Random number data 0x110 0x20 + read-only @@ -27577,36 +27668,40 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 512 - 0x1 + 128 + 0x4 M_MEM[%s] Memory M 0x0 - 0x8 + 0x20 + write-only - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] Memory Z 0x200 - 0x8 + 0x20 + read-write - 512 - 0x1 + 128 + 0x4 Y_MEM[%s] Memory Y 0x400 - 0x8 + 0x20 + write-only - 512 - 0x1 + 128 + 0x4 X_MEM[%s] Memory X 0x600 - 0x8 + 0x20 + write-only M_PRIME @@ -27809,7 +27904,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_CNTL - Real Time Controller + Real-Time Clock Control RTC_CNTL 0x60008000 @@ -28014,7 +28109,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_MAIN_TIMER_ALARM_EN + MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 @@ -28050,7 +28145,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_TIME_UPDATE + TIME_UPDATE Set 1: to update register with RTC timer 31 1 @@ -28065,7 +28160,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_TIMER_VALUE0_LOW + TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 @@ -28080,7 +28175,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_TIMER_VALUE0_HIGH + TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 @@ -28095,14 +28190,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SW_CPU_INT + SW_CPU_INT rtc software interrupt to main cpu 0 1 write-only - RTC_SLP_REJECT_CAUSE_CLR + SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 @@ -28257,14 +28352,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x10200A08 - RTC_WAIT_TIMER + WAIT_TIMER No public 0 9 read-write - RTC_POWERUP_TIMER + POWERUP_TIMER No public 9 7 @@ -28538,14 +28633,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. write-only - RTC_APP_DRESET_MASK + APP_DRESET_MASK bypass cpu1 dreset 24 1 read-write - RTC_PRO_DRESET_MASK + PRO_DRESET_MASK bypass cpu0 dreset 25 1 @@ -28561,7 +28656,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00060000 - RTC_WAKEUP_ENA + WAKEUP_ENA wakeup enable bitmap 15 17 @@ -28597,126 +28692,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_WDT_INT_ENA + WDT_INT_ENA enable RTC WDT interrupt 3 1 read-write - RTC_TOUCH_SCAN_DONE_INT_ENA + TOUCH_SCAN_DONE_INT_ENA enable touch scan done interrupt 4 1 read-write - RTC_ULP_CP_INT_ENA + ULP_CP_INT_ENA enable ULP-coprocessor interrupt 5 1 read-write - RTC_TOUCH_DONE_INT_ENA + TOUCH_DONE_INT_ENA enable touch done interrupt 6 1 read-write - RTC_TOUCH_ACTIVE_INT_ENA + TOUCH_ACTIVE_INT_ENA enable touch active interrupt 7 1 read-write - RTC_TOUCH_INACTIVE_INT_ENA + TOUCH_INACTIVE_INT_ENA enable touch inactive interrupt 8 1 read-write - RTC_BROWN_OUT_INT_ENA + BROWN_OUT_INT_ENA enable brown out interrupt 9 1 read-write - RTC_MAIN_TIMER_INT_ENA + MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 read-write - RTC_SARADC1_INT_ENA + SARADC1_INT_ENA enable saradc1 interrupt 11 1 read-write - RTC_TSENS_INT_ENA + TSENS_INT_ENA enable tsens interrupt 12 1 read-write - RTC_COCPU_INT_ENA + COCPU_INT_ENA enable riscV cocpu interrupt 13 1 read-write - RTC_SARADC2_INT_ENA + SARADC2_INT_ENA enable saradc2 interrupt 14 1 read-write - RTC_SWD_INT_ENA + SWD_INT_ENA enable super watch dog interrupt 15 1 read-write - RTC_XTAL32K_DEAD_INT_ENA + XTAL32K_DEAD_INT_ENA enable xtal32k_dead interrupt 16 1 read-write - RTC_COCPU_TRAP_INT_ENA + COCPU_TRAP_INT_ENA enable cocpu trap interrupt 17 1 read-write - RTC_TOUCH_TIMEOUT_INT_ENA + TOUCH_TIMEOUT_INT_ENA enable touch timeout interrupt 18 1 read-write - RTC_GLITCH_DET_INT_ENA + GLITCH_DET_INT_ENA enbale gitch det interrupt 19 1 read-write - RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA + TOUCH_APPROACH_LOOP_DONE_INT_ENA touch approach mode loop interrupt 20 1 @@ -28752,126 +28847,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-only - RTC_WDT_INT_RAW + WDT_INT_RAW RTC WDT interrupt raw 3 1 read-only - RTC_TOUCH_SCAN_DONE_INT_RAW + TOUCH_SCAN_DONE_INT_RAW enable touch scan done interrupt raw 4 1 read-only - RTC_ULP_CP_INT_RAW + ULP_CP_INT_RAW ULP-coprocessor interrupt raw 5 1 read-only - RTC_TOUCH_DONE_INT_RAW + TOUCH_DONE_INT_RAW touch interrupt raw 6 1 read-only - RTC_TOUCH_ACTIVE_INT_RAW + TOUCH_ACTIVE_INT_RAW touch active interrupt raw 7 1 read-only - RTC_TOUCH_INACTIVE_INT_RAW + TOUCH_INACTIVE_INT_RAW touch inactive interrupt raw 8 1 read-only - RTC_BROWN_OUT_INT_RAW + BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-only - RTC_MAIN_TIMER_INT_RAW + MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-only - RTC_SARADC1_INT_RAW + SARADC1_INT_RAW saradc1 interrupt raw 11 1 read-only - RTC_TSENS_INT_RAW + TSENS_INT_RAW tsens interrupt raw 12 1 read-only - RTC_COCPU_INT_RAW + COCPU_INT_RAW riscV cocpu interrupt raw 13 1 read-only - RTC_SARADC2_INT_RAW + SARADC2_INT_RAW saradc2 interrupt raw 14 1 read-only - RTC_SWD_INT_RAW + SWD_INT_RAW super watch dog interrupt raw 15 1 read-only - RTC_XTAL32K_DEAD_INT_RAW + XTAL32K_DEAD_INT_RAW xtal32k dead detection interrupt raw 16 1 read-only - RTC_COCPU_TRAP_INT_RAW + COCPU_TRAP_INT_RAW cocpu trap interrupt raw 17 1 read-only - RTC_TOUCH_TIMEOUT_INT_RAW + TOUCH_TIMEOUT_INT_RAW touch timeout interrupt raw 18 1 read-only - RTC_GLITCH_DET_INT_RAW + GLITCH_DET_INT_RAW glitch_det_interrupt_raw 19 1 read-only - RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW + TOUCH_APPROACH_LOOP_DONE_INT_RAW touch approach mode loop interrupt raw 20 1 @@ -28907,126 +29002,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-only - RTC_WDT_INT_ST + WDT_INT_ST RTC WDT interrupt state 3 1 read-only - RTC_TOUCH_SCAN_DONE_INT_ST + TOUCH_SCAN_DONE_INT_ST enable touch scan done interrupt raw 4 1 read-only - RTC_ULP_CP_INT_ST + ULP_CP_INT_ST ULP-coprocessor interrupt state 5 1 read-only - RTC_TOUCH_DONE_INT_ST + TOUCH_DONE_INT_ST touch done interrupt state 6 1 read-only - RTC_TOUCH_ACTIVE_INT_ST + TOUCH_ACTIVE_INT_ST touch active interrupt state 7 1 read-only - RTC_TOUCH_INACTIVE_INT_ST + TOUCH_INACTIVE_INT_ST touch inactive interrupt state 8 1 read-only - RTC_BROWN_OUT_INT_ST + BROWN_OUT_INT_ST brown out interrupt state 9 1 read-only - RTC_MAIN_TIMER_INT_ST + MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-only - RTC_SARADC1_INT_ST + SARADC1_INT_ST saradc1 interrupt state 11 1 read-only - RTC_TSENS_INT_ST + TSENS_INT_ST tsens interrupt state 12 1 read-only - RTC_COCPU_INT_ST + COCPU_INT_ST riscV cocpu interrupt state 13 1 read-only - RTC_SARADC2_INT_ST + SARADC2_INT_ST saradc2 interrupt state 14 1 read-only - RTC_SWD_INT_ST + SWD_INT_ST super watch dog interrupt state 15 1 read-only - RTC_XTAL32K_DEAD_INT_ST + XTAL32K_DEAD_INT_ST xtal32k dead detection interrupt state 16 1 read-only - RTC_COCPU_TRAP_INT_ST + COCPU_TRAP_INT_ST cocpu trap interrupt state 17 1 read-only - RTC_TOUCH_TIMEOUT_INT_ST + TOUCH_TIMEOUT_INT_ST Touch timeout interrupt state 18 1 read-only - RTC_GLITCH_DET_INT_ST + GLITCH_DET_INT_ST glitch_det_interrupt state 19 1 read-only - RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST + TOUCH_APPROACH_LOOP_DONE_INT_ST touch approach mode loop interrupt state 20 1 @@ -29062,126 +29157,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. write-only - RTC_WDT_INT_CLR + WDT_INT_CLR Clear RTC WDT interrupt state 3 1 write-only - RTC_TOUCH_SCAN_DONE_INT_CLR + TOUCH_SCAN_DONE_INT_CLR clear touch scan done interrupt raw 4 1 write-only - RTC_ULP_CP_INT_CLR + ULP_CP_INT_CLR Clear ULP-coprocessor interrupt state 5 1 write-only - RTC_TOUCH_DONE_INT_CLR + TOUCH_DONE_INT_CLR Clear touch done interrupt state 6 1 write-only - RTC_TOUCH_ACTIVE_INT_CLR + TOUCH_ACTIVE_INT_CLR Clear touch active interrupt state 7 1 write-only - RTC_TOUCH_INACTIVE_INT_CLR + TOUCH_INACTIVE_INT_CLR Clear touch inactive interrupt state 8 1 write-only - RTC_BROWN_OUT_INT_CLR + BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 write-only - RTC_MAIN_TIMER_INT_CLR + MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 write-only - RTC_SARADC1_INT_CLR + SARADC1_INT_CLR Clear saradc1 interrupt state 11 1 write-only - RTC_TSENS_INT_CLR + TSENS_INT_CLR Clear tsens interrupt state 12 1 write-only - RTC_COCPU_INT_CLR + COCPU_INT_CLR Clear riscV cocpu interrupt state 13 1 write-only - RTC_SARADC2_INT_CLR + SARADC2_INT_CLR Clear saradc2 interrupt state 14 1 write-only - RTC_SWD_INT_CLR + SWD_INT_CLR Clear super watch dog interrupt state 15 1 write-only - RTC_XTAL32K_DEAD_INT_CLR + XTAL32K_DEAD_INT_CLR Clear RTC WDT interrupt state 16 1 write-only - RTC_COCPU_TRAP_INT_CLR + COCPU_TRAP_INT_CLR Clear cocpu trap interrupt state 17 1 write-only - RTC_TOUCH_TIMEOUT_INT_CLR + TOUCH_TIMEOUT_INT_CLR Clear touch timeout interrupt state 18 1 write-only - RTC_GLITCH_DET_INT_CLR + GLITCH_DET_INT_CLR Clear glitch det interrupt state 19 1 write-only - RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR + TOUCH_APPROACH_LOOP_DONE_INT_CLR cleartouch approach mode loop interrupt state 20 1 @@ -29196,7 +29291,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH0 + SCRATCH0 Reserved register 0 32 @@ -29211,7 +29306,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH1 + SCRATCH1 Reserved register 0 32 @@ -29226,7 +29321,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH2 + SCRATCH2 Reserved register 0 32 @@ -29241,7 +29336,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH3 + SCRATCH3 Reserved register 0 32 @@ -29355,14 +29450,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_WDT_STATE + WDT_STATE state of 32k_wdt 20 3 read-only - RTC_XTAL32K_GPIO_SEL + XTAL32K_GPIO_SEL XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C 23 1 @@ -29420,7 +29515,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SLEEP_REJECT_ENA + SLEEP_REJECT_ENA sleep reject enable 12 18 @@ -29449,14 +29544,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_CPUSEL_CONF + CPUSEL_CONF CPU sel option 29 1 read-write - RTC_CPUPERIOD_SEL + CPUPERIOD_SEL conigure cpu freq 30 2 @@ -29629,21 +29724,21 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00400000 - RTC_ANA_CLK_DIV_VLD + ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk 22 1 read-write - RTC_ANA_CLK_DIV + ANA_CLK_DIV rtc clk div 23 8 read-write - RTC_SLOW_CLK_NEXT_EDGE + SLOW_CLK_NEXT_EDGE No public 31 1 @@ -29859,7 +29954,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. - REG + RTC configure rtc regulator 0x84 0x20 @@ -29880,28 +29975,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_DBOOST_FORCE_PD + DBOOST_FORCE_PD RTC_DBOOST force power down 28 1 read-write - RTC_DBOOST_FORCE_PU + DBOOST_FORCE_PU RTC_DBOOST force power up 29 1 read-write - RTC_REGULATOR_FORCE_PD + REGULATOR_FORCE_PD RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) 30 1 read-write - RTC_REGULATOR_FORCE_PU + REGULATOR_FORCE_PU RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower ) 31 1 @@ -29917,112 +30012,112 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000925 - RTC_FASTMEM_FORCE_NOISO + FASTMEM_FORCE_NOISO Fast RTC memory force no ISO 0 1 read-write - RTC_FASTMEM_FORCE_ISO + FASTMEM_FORCE_ISO Fast RTC memory force ISO 1 1 read-write - RTC_SLOWMEM_FORCE_NOISO + SLOWMEM_FORCE_NOISO RTC memory force no ISO 2 1 read-write - RTC_SLOWMEM_FORCE_ISO + SLOWMEM_FORCE_ISO RTC memory force ISO 3 1 read-write - RTC_FORCE_ISO + FORCE_ISO rtc_peri force ISO 4 1 read-write - RTC_FORCE_NOISO + FORCE_NOISO rtc_peri force no ISO 5 1 read-write - RTC_FASTMEM_FOLW_CPU + FASTMEM_FOLW_CPU 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine 6 1 read-write - RTC_FASTMEM_FORCE_LPD + FASTMEM_FORCE_LPD Fast RTC memory force PD 7 1 read-write - RTC_FASTMEM_FORCE_LPU + FASTMEM_FORCE_LPU Fast RTC memory force no PD 8 1 read-write - RTC_SLOWMEM_FOLW_CPU + SLOWMEM_FOLW_CPU 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine 9 1 read-write - RTC_SLOWMEM_FORCE_LPD + SLOWMEM_FORCE_LPD RTC memory force PD 10 1 read-write - RTC_SLOWMEM_FORCE_LPU + SLOWMEM_FORCE_LPU RTC memory force no PD 11 1 read-write - RTC_FORCE_PD + FORCE_PD rtc_peri force power down 18 1 read-write - RTC_FORCE_PU + FORCE_PU rtc_peri force power up 19 1 read-write - RTC_PD_EN + PD_EN enable power down rtc_peri in sleep 20 1 read-write - RTC_PAD_FORCE_HOLD + PAD_FORCE_HOLD rtc pad force hold 21 1 @@ -30037,14 +30132,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_REGULATOR_DRV_B_MONITOR + REGULATOR_DRV_B_MONITOR No public 0 6 read-write - RTC_REGULATOR_DRV_B_SLP + REGULATOR_DRV_B_SLP No public 6 6 @@ -30507,7 +30602,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_WDT_FEED + WDT_FEED rtc wdt feed 31 1 @@ -30641,7 +30736,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH4 + SCRATCH4 reserved register 0 32 @@ -30656,7 +30751,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH5 + SCRATCH5 reserved register 0 32 @@ -30671,7 +30766,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH6 + SCRATCH6 reserved register 0 32 @@ -30686,7 +30781,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_SCRATCH7 + SCRATCH7 reserved register 0 32 @@ -30715,7 +30810,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-only - RTC_PERI_ISO + PERI_ISO rtc peripheral iso 3 1 @@ -30757,140 +30852,140 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-only - RTC_TOUCH_STATE_START + TOUCH_STATE_START touch should start to work 9 1 read-only - RTC_TOUCH_STATE_SWITCH + TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-only - RTC_TOUCH_STATE_SLP + TOUCH_STATE_SLP touch is in sleep state 11 1 read-only - RTC_TOUCH_STATE_DONE + TOUCH_STATE_DONE touch is done 12 1 read-only - RTC_COCPU_STATE_START + COCPU_STATE_START ulp/cocpu should start to work 13 1 read-only - RTC_COCPU_STATE_SWITCH + COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-only - RTC_COCPU_STATE_SLP + COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-only - RTC_COCPU_STATE_DONE + COCPU_STATE_DONE ulp/cocpu is done 16 1 read-only - RTC_MAIN_STATE_XTAL_ISO + MAIN_STATE_XTAL_ISO no use any more 17 1 read-only - RTC_MAIN_STATE_PLL_ON + MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-only - RTC_RDY_FOR_WAKEUP + RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-only - RTC_MAIN_STATE_WAIT_END + MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-only - RTC_IN_WAKEUP_STATE + IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-only - RTC_IN_LOW_POWER_STATE + IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-only - RTC_MAIN_STATE_IN_WAIT_8M + MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-only - RTC_MAIN_STATE_IN_WAIT_PLL + MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-only - RTC_MAIN_STATE_IN_WAIT_XTL + MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-only - RTC_MAIN_STATE_IN_SLP + MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-only - RTC_MAIN_STATE_IN_IDLE + MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-only - RTC_MAIN_STATE + MAIN_STATE rtc main state machine status 28 4 @@ -30905,7 +31000,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_LOW_POWER_DIAG1 + LOW_POWER_DIAG1 No public 0 32 @@ -31053,21 +31148,21 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - RTC_PAD19_HOLD + PAD19_HOLD hold rtc pad-19 19 1 read-write - RTC_PAD20_HOLD + PAD20_HOLD hold rtc pad-20 20 1 read-write - RTC_PAD21_HOLD + PAD21_HOLD hold rtc pad-21 21 1 @@ -31097,14 +31192,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SEL + EXT_WAKEUP1_SEL Bitmap to select RTC pads for ext wakeup1 0 22 read-write - STATUS_CLR + EXT_WAKEUP1_STATUS_CLR clear ext wakeup1 status 22 1 @@ -31135,70 +31230,70 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x43FF0010 - INT_WAIT + BROWN_OUT_INT_WAIT brown out interrupt wait cycles 4 10 read-write - CLOSE_FLASH_ENA + BROWN_OUT_CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write - PD_RF_ENA + BROWN_OUT_PD_RF_ENA enable power down RF when brown out happens 15 1 read-write - RST_WAIT + BROWN_OUT_RST_WAIT brown out reset wait cycles 16 10 read-write - RST_ENA + BROWN_OUT_RST_ENA enable brown out reset 26 1 read-write - RST_SEL + BROWN_OUT_RST_SEL 1: 4-pos reset, 0: sys_reset 27 1 read-write - ANA_RST_EN + BROWN_OUT_ANA_RST_EN enable brown out reset en 28 1 read-write - CNT_CLR + BROWN_OUT_CNT_CLR clear brown out counter 29 1 write-only - ENA + BROWN_OUT_ENA enable brown out 30 1 read-write - RTC_BROWN_OUT_DET + DET get brown out detect 31 1 @@ -31213,7 +31308,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_TIMER_VALUE1_LOW + TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 @@ -31228,7 +31323,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - RTC_TIMER_VALUE1_HIGH + TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 @@ -31715,7 +31810,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. write-only - MEAS_TIME + TOUCH_APPROACH_MEAS_TIME approach pads total meas times 24 8 @@ -32062,126 +32157,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. write-only - RTC_WDT_INT_ENA_W1TS + WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 write-only - RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS + TOUCH_SCAN_DONE_INT_ENA_W1TS enable touch scan done interrupt 4 1 write-only - RTC_ULP_CP_INT_ENA_W1TS + ULP_CP_INT_ENA_W1TS enable ULP-coprocessor interrupt 5 1 write-only - RTC_TOUCH_DONE_INT_ENA_W1TS + TOUCH_DONE_INT_ENA_W1TS enable touch done interrupt 6 1 write-only - RTC_TOUCH_ACTIVE_INT_ENA_W1TS + TOUCH_ACTIVE_INT_ENA_W1TS enable touch active interrupt 7 1 write-only - RTC_TOUCH_INACTIVE_INT_ENA_W1TS + TOUCH_INACTIVE_INT_ENA_W1TS enable touch inactive interrupt 8 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TS + BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TS + MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 write-only - RTC_SARADC1_INT_ENA_W1TS + SARADC1_INT_ENA_W1TS enable saradc1 interrupt 11 1 write-only - RTC_TSENS_INT_ENA_W1TS + TSENS_INT_ENA_W1TS enable tsens interrupt 12 1 write-only - RTC_COCPU_INT_ENA_W1TS + COCPU_INT_ENA_W1TS enable riscV cocpu interrupt 13 1 write-only - RTC_SARADC2_INT_ENA_W1TS + SARADC2_INT_ENA_W1TS enable saradc2 interrupt 14 1 write-only - RTC_SWD_INT_ENA_W1TS + SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TS + XTAL32K_DEAD_INT_ENA_W1TS enable xtal32k_dead interrupt 16 1 write-only - RTC_COCPU_TRAP_INT_ENA_W1TS + COCPU_TRAP_INT_ENA_W1TS enable cocpu trap interrupt 17 1 write-only - RTC_TOUCH_TIMEOUT_INT_ENA_W1TS + TOUCH_TIMEOUT_INT_ENA_W1TS enable touch timeout interrupt 18 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TS + GLITCH_DET_INT_ENA_W1TS enbale gitch det interrupt 19 1 write-only - RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS enbale touch approach_loop done interrupt 20 1 @@ -32217,126 +32312,126 @@ Any pulses with width less than this will be ignored when the filter is enabled. write-only - RTC_WDT_INT_ENA_W1TC + WDT_INT_ENA_W1TC enable RTC WDT interrupt 3 1 write-only - RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC + TOUCH_SCAN_DONE_INT_ENA_W1TC enable touch scan done interrupt 4 1 write-only - RTC_ULP_CP_INT_ENA_W1TC + ULP_CP_INT_ENA_W1TC enable ULP-coprocessor interrupt 5 1 write-only - RTC_TOUCH_DONE_INT_ENA_W1TC + TOUCH_DONE_INT_ENA_W1TC enable touch done interrupt 6 1 write-only - RTC_TOUCH_ACTIVE_INT_ENA_W1TC + TOUCH_ACTIVE_INT_ENA_W1TC enable touch active interrupt 7 1 write-only - RTC_TOUCH_INACTIVE_INT_ENA_W1TC + TOUCH_INACTIVE_INT_ENA_W1TC enable touch inactive interrupt 8 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TC + BROWN_OUT_INT_ENA_W1TC enable brown out interrupt 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TC + MAIN_TIMER_INT_ENA_W1TC enable RTC main timer interrupt 10 1 write-only - RTC_SARADC1_INT_ENA_W1TC + SARADC1_INT_ENA_W1TC enable saradc1 interrupt 11 1 write-only - RTC_TSENS_INT_ENA_W1TC + TSENS_INT_ENA_W1TC enable tsens interrupt 12 1 write-only - RTC_COCPU_INT_ENA_W1TC + COCPU_INT_ENA_W1TC enable riscV cocpu interrupt 13 1 write-only - RTC_SARADC2_INT_ENA_W1TC + SARADC2_INT_ENA_W1TC enable saradc2 interrupt 14 1 write-only - RTC_SWD_INT_ENA_W1TC + SWD_INT_ENA_W1TC enable super watch dog interrupt 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TC + XTAL32K_DEAD_INT_ENA_W1TC enable xtal32k_dead interrupt 16 1 write-only - RTC_COCPU_TRAP_INT_ENA_W1TC + COCPU_TRAP_INT_ENA_W1TC enable cocpu trap interrupt 17 1 write-only - RTC_TOUCH_TIMEOUT_INT_ENA_W1TC + TOUCH_TIMEOUT_INT_ENA_W1TC enable touch timeout interrupt 18 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TC + GLITCH_DET_INT_ENA_W1TC enbale gitch det interrupt 19 1 write-only - RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC enbale touch approach_loop done interrupt 20 1 @@ -32453,7 +32548,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000007 - RTC_FIB_SEL + FIB_SEL No public 0 3 @@ -32617,7 +32712,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_I2C - Peripheral RTC_I2C + Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x60008C00 @@ -33592,7 +33687,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_IO - Peripheral RTC_IO + Low-power Input/Output RTC_IO 0x60008400 @@ -33677,13 +33772,13 @@ Any pulses with width less than this will be ignored when the filter is enabled. - RTC_GPIO_ENABLE_W1TC + ENABLE_W1TC one clear RTC GPIO output enable 0x14 0x20 - RTC_GPIO_ENABLE_W1TC + ENABLE_W1TC RTC GPIO 0 ~ 21 enable write 1 to clear 10 22 @@ -33752,8 +33847,11 @@ Any pulses with width less than this will be ignored when the filter is enabled. - RTC_GPIO_PIN0 - configure RTC GPIO0 + 22 + 0x4 + 0-21 + PIN%s + configure RTC GPIO%s 0x28 0x20 @@ -33781,670 +33879,433 @@ Any pulses with width less than this will be ignored when the filter is enabled. - RTC_GPIO_PIN1 - configure RTC GPIO1 - 0x2C + RTC_DEBUG_SEL + configure rtc debug + 0x80 0x20 - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 - 1 + RTC_DEBUG_SEL0 + configure rtc debug + 0 + 5 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RTC_DEBUG_SEL1 + configure rtc debug + 5 + 5 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit + RTC_DEBUG_SEL2 + configure rtc debug 10 - 1 + 5 read-write - - - - RTC_GPIO_PIN2 - configure RTC GPIO2 - 0x30 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 - 1 + RTC_DEBUG_SEL3 + configure rtc debug + 15 + 5 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RTC_DEBUG_SEL4 + configure rtc debug + 20 + 5 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + RTC_DEBUG_12M_NO_GATING + configure rtc debug + 25 1 read-write - RTC_GPIO_PIN3 - configure RTC GPIO3 - 0x34 + TOUCH_PAD0 + configure RTC PAD0 + 0x84 0x20 + 0x50000000 - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + FUN_IE + input enable in work mode + 13 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + SLP_OE + output enable in sleep mode + 14 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + SLP_IE + input enable in sleep mode + 15 1 read-write - - - - RTC_GPIO_PIN4 - configure RTC GPIO4 - 0x38 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + FUN_SEL + function sel + 17 + 2 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 1 read-write - - - - RTC_GPIO_PIN5 - configure RTC GPIO5 - 0x3C - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + XPD + TOUCH_XPD + 20 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + START + TOUCH_START + 22 1 read-write - - - - RTC_GPIO_PIN6 - configure RTC GPIO6 - 0x40 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + RUE + RUE + 27 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RDE + RDE + 28 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 + DRV + DRV + 29 + 2 read-write - RTC_GPIO_PIN7 - configure RTC GPIO7 - 0x44 + TOUCH_PAD1 + configure RTC PAD1 + 0x88 0x20 + 0x48000000 - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + FUN_IE + input enable in work mode + 13 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + SLP_OE + output enable in sleep mode + 14 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + SLP_IE + input enable in sleep mode + 15 1 read-write - - - - RTC_GPIO_PIN8 - configure RTC GPIO8 - 0x48 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + FUN_SEL + function sel + 17 + 2 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 1 read-write - - - - RTC_GPIO_PIN9 - configure RTC GPIO9 - 0x4C - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + XPD + TOUCH_XPD + 20 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + START + TOUCH_START + 22 1 read-write - - - - RTC_GPIO_PIN10 - configure RTC GPIO10 - 0x50 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + RUE + RUE + 27 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RDE + RDE + 28 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 + DRV + DRV + 29 + 2 read-write - RTC_GPIO_PIN11 - configure RTC GPIO11 - 0x54 + TOUCH_PAD2 + configure RTC PAD2 + 0x8C 0x20 + 0x50000000 - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + FUN_IE + input enable in work mode + 13 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + SLP_OE + output enable in sleep mode + 14 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + SLP_IE + input enable in sleep mode + 15 1 read-write - - - - RTC_GPIO_PIN12 - configure RTC GPIO12 - 0x58 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + FUN_SEL + function sel + 17 + 2 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 1 read-write - - - - RTC_GPIO_PIN13 - configure RTC GPIO13 - 0x5C - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + XPD + TOUCH_XPD + 20 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + START + TOUCH_START + 22 1 read-write - - - - RTC_GPIO_PIN14 - configure RTC GPIO14 - 0x60 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + RUE + RUE + 27 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RDE + RDE + 28 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 + DRV + DRV + 29 + 2 read-write - RTC_GPIO_PIN15 - configure RTC GPIO15 - 0x64 + TOUCH_PAD3 + configure RTC PAD3 + 0x90 0x20 + 0x48000000 - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + FUN_IE + input enable in work mode + 13 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + SLP_OE + output enable in sleep mode + 14 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + SLP_IE + input enable in sleep mode + 15 1 read-write - - - - RTC_GPIO_PIN16 - configure RTC GPIO16 - 0x68 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + FUN_SEL + function sel + 17 + 2 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 1 read-write - - - - RTC_GPIO_PIN17 - configure RTC GPIO17 - 0x6C - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + XPD + TOUCH_XPD + 20 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 + START + TOUCH_START + 22 1 read-write - - - - RTC_GPIO_PIN18 - configure RTC GPIO18 - 0x70 - 0x20 - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 + RUE + RUE + 27 1 read-write - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 + RDE + RDE + 28 + 1 read-write - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 + DRV + DRV + 29 + 2 read-write - RTC_GPIO_PIN19 - configure RTC GPIO19 - 0x74 + TOUCH_PAD4 + configure RTC PAD4 + 0x94 0x20 - - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 - 1 - read-write - - - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 - read-write - - - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 - read-write - - - - - RTC_GPIO_PIN20 - configure RTC GPIO20 - 0x78 - 0x20 - - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 - 1 - read-write - - - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 - read-write - - - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 - read-write - - - - - RTC_GPIO_PIN21 - configure RTC GPIO21 - 0x7C - 0x20 - - - PAD_DRIVER - if set to 0: normal output, if set to 1: open drain - 2 - 1 - read-write - - - INT_TYPE - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger - 7 - 3 - read-write - - - WAKEUP_ENABLE - RTC GPIO wakeup enable bit - 10 - 1 - read-write - - - - - RTC_DEBUG_SEL - configure rtc debug - 0x80 - 0x20 - - - RTC_DEBUG_SEL0 - configure rtc debug - 0 - 5 - read-write - - - RTC_DEBUG_SEL1 - configure rtc debug - 5 - 5 - read-write - - - RTC_DEBUG_SEL2 - configure rtc debug - 10 - 5 - read-write - - - RTC_DEBUG_SEL3 - configure rtc debug - 15 - 5 - read-write - - - RTC_DEBUG_SEL4 - configure rtc debug - 20 - 5 - read-write - - - RTC_DEBUG_12M_NO_GATING - configure rtc debug - 25 - 1 - read-write - - - - - TOUCH_PAD0 - configure RTC PAD0 - 0x84 - 0x20 - 0x50000000 + 0x50000000 FUN_IE @@ -34533,102 +34394,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD1 - configure RTC PAD1 - 0x88 - 0x20 - 0x48000000 - - - FUN_IE - input enable in work mode - 13 - 1 - read-write - - - SLP_OE - output enable in sleep mode - 14 - 1 - read-write - - - SLP_IE - input enable in sleep mode - 15 - 1 - read-write - - - SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 16 - 1 - read-write - - - FUN_SEL - function sel - 17 - 2 - read-write - - - MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 - 1 - read-write - - - XPD - TOUCH_XPD - 20 - 1 - read-write - - - TIE_OPT - TOUCH_TIE_OPT - 21 - 1 - read-write - - - START - TOUCH_START - 22 - 1 - read-write - - - RUE - RUE - 27 - 1 - read-write - - - RDE - RDE - 28 - 1 - read-write - - - DRV - DRV - 29 - 2 - read-write - - - - - TOUCH_PAD2 - configure RTC PAD2 - 0x8C + TOUCH_PAD5 + configure RTC PAD5 + 0x98 0x20 0x50000000 @@ -34719,9 +34487,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD3 - configure RTC PAD3 - 0x90 + TOUCH_PAD6 + configure RTC PAD6 + 0x9C 0x20 0x48000000 @@ -34812,11 +34580,11 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD4 - configure RTC PAD4 - 0x94 + TOUCH_PAD7 + configure RTC PAD7 + 0xA0 0x20 - 0x50000000 + 0x40000000 FUN_IE @@ -34905,11 +34673,11 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD5 - configure RTC PAD5 - 0x98 + TOUCH_PAD8 + configure RTC PAD8 + 0xA4 0x20 - 0x50000000 + 0x40000000 FUN_IE @@ -34998,11 +34766,11 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD6 - configure RTC PAD6 - 0x9C + TOUCH_PAD9 + configure RTC PAD9 + 0xA8 0x20 - 0x48000000 + 0x40000000 FUN_IE @@ -35091,9 +34859,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD7 - configure RTC PAD7 - 0xA0 + TOUCH_PAD10 + configure RTC PAD10 + 0xAC 0x20 0x40000000 @@ -35184,9 +34952,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD8 - configure RTC PAD8 - 0xA4 + TOUCH_PAD11 + configure RTC PAD11 + 0xB0 0x20 0x40000000 @@ -35277,9 +35045,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD9 - configure RTC PAD9 - 0xA8 + TOUCH_PAD12 + configure RTC PAD12 + 0xB4 0x20 0x40000000 @@ -35370,9 +35138,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD10 - configure RTC PAD10 - 0xAC + TOUCH_PAD13 + configure RTC PAD13 + 0xB8 0x20 0x40000000 @@ -35463,9 +35231,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD11 - configure RTC PAD11 - 0xB0 + TOUCH_PAD14 + configure RTC PAD14 + 0xBC 0x20 0x40000000 @@ -35556,91 +35324,142 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD12 - configure RTC PAD12 - 0xB4 + XTAL_32P_PAD + configure RTC PAD15 + 0xC0 0x20 0x40000000 - FUN_IE + X32P_FUN_IE input enable in work mode 13 1 read-write - SLP_OE + X32P_SLP_OE output enable in sleep mode 14 1 read-write - SLP_IE + X32P_SLP_IE input enable in sleep mode 15 1 read-write - SLP_SEL + X32P_SLP_SEL 1: enable sleep mode during sleep,0: no sleep mode 16 1 read-write - FUN_SEL + X32P_FUN_SEL function sel 17 2 read-write - MUX_SEL + X32P_MUX_SEL 1: use RTC GPIO,0: use digital GPIO 19 1 read-write - XPD - TOUCH_XPD - 20 + X32P_RUE + RUE + 27 1 read-write - TIE_OPT - TOUCH_TIE_OPT - 21 + X32P_RDE + RDE + 28 1 read-write - START - TOUCH_START - 22 + X32P_DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32N_PAD + configure RTC PAD16 + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + input enable in work mode + 13 1 read-write - RUE + X32N_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32N_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32N_FUN_SEL + function sel + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32N_RUE RUE 27 1 read-write - RDE + X32N_RDE RDE 28 1 read-write - DRV + X32N_DRV DRV 29 2 @@ -35649,92 +35468,185 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD13 - configure RTC PAD13 - 0xB8 + PAD_DAC1 + configure RTC PAD17 + 0xC8 0x20 0x40000000 - FUN_IE + PDAC1_DAC + PDAC1_DAC + 3 + 8 + read-write + + + PDAC1_XPD_DAC + PDAC1_XPD_DAC + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC + 12 + 1 + read-write + + + PDAC1_FUN_IE input enable in work mode 13 1 read-write - SLP_OE + PDAC1_SLP_OE output enable in sleep mode 14 1 read-write - SLP_IE + PDAC1_SLP_IE input enable in sleep mode 15 1 read-write - SLP_SEL + PDAC1_SLP_SEL 1: enable sleep mode during sleep,0: no sleep mode 16 1 read-write - FUN_SEL - function sel + PDAC1_FUN_SEL + PDAC1 function sel 17 2 read-write - MUX_SEL + PDAC1_MUX_SEL 1: use RTC GPIO,0: use digital GPIO 19 1 read-write - XPD - TOUCH_XPD - 20 + PDAC1_RUE + PDAC1_RUE + 27 1 read-write - TIE_OPT - TOUCH_TIE_OPT - 21 + PDAC1_RDE + PDAC1_RDE + 28 1 read-write - START - TOUCH_START - 22 + PDAC1_DRV + PDAC1_DRV + 29 + 2 + read-write + + + + + PAD_DAC2 + configure RTC PAD18 + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + PDAC2_DAC + 3 + 8 + read-write + + + PDAC2_XPD_DAC + PDAC2_XPD_DAC + 11 1 read-write - RUE - RUE + PDAC2_DAC_XPD_FORCE + 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC + 12 + 1 + read-write + + + PDAC2_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC2_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC2_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC2_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC2_RUE + PDAC2_RUE 27 1 read-write - RDE - RDE + PDAC2_RDE + PDAC2_RDE 28 1 read-write - DRV - DRV + PDAC2_DRV + PDAC2_DRV 29 2 read-write @@ -35742,11 +35654,11 @@ Any pulses with width less than this will be ignored when the filter is enabled. - TOUCH_PAD14 - configure RTC PAD14 - 0xBC + RTC_PAD19 + configure RTC PAD19 + 0xD0 0x20 - 0x40000000 + 0x50000000 FUN_IE @@ -35790,27 +35702,6 @@ Any pulses with width less than this will be ignored when the filter is enabled. 1 read-write - - XPD - TOUCH_XPD - 20 - 1 - read-write - - - TIE_OPT - TOUCH_TIE_OPT - 21 - 1 - read-write - - - START - TOUCH_START - 22 - 1 - read-write - RUE RUE @@ -35835,70 +35726,70 @@ Any pulses with width less than this will be ignored when the filter is enabled. - XTAL_32P_PAD - configure RTC PAD15 - 0xC0 + RTC_PAD20 + configure RTC PAD20 + 0xD4 0x20 - 0x40000000 + 0x50000000 - X32P_FUN_IE + FUN_IE input enable in work mode 13 1 read-write - X32P_SLP_OE + SLP_OE output enable in sleep mode 14 1 read-write - X32P_SLP_IE + SLP_IE input enable in sleep mode 15 1 read-write - X32P_SLP_SEL + SLP_SEL 1: enable sleep mode during sleep,0: no sleep mode 16 1 read-write - X32P_FUN_SEL + FUN_SEL function sel 17 2 read-write - X32P_MUX_SEL + MUX_SEL 1: use RTC GPIO,0: use digital GPIO 19 1 read-write - X32P_RUE + RUE RUE 27 1 read-write - X32P_RDE + RDE RDE 28 1 read-write - X32P_DRV + DRV DRV 29 2 @@ -35907,70 +35798,70 @@ Any pulses with width less than this will be ignored when the filter is enabled. - XTAL_32N_PAD - configure RTC PAD16 - 0xC4 + RTC_PAD21 + configure RTC PAD21 + 0xD8 0x20 - 0x40000000 + 0x50000000 - X32N_FUN_IE + FUN_IE input enable in work mode 13 1 read-write - X32N_SLP_OE + SLP_OE output enable in sleep mode 14 1 read-write - X32N_SLP_IE + SLP_IE input enable in sleep mode 15 1 read-write - X32N_SLP_SEL + SLP_SEL 1: enable sleep mode during sleep,0: no sleep mode 16 1 read-write - X32N_FUN_SEL + FUN_SEL function sel 17 2 read-write - X32N_MUX_SEL + MUX_SEL 1: use RTC GPIO,0: use digital GPIO 19 1 read-write - X32N_RUE + RUE RUE 27 1 read-write - X32N_RDE + RDE RDE 28 1 read-write - X32N_DRV + DRV DRV 29 2 @@ -35979,654 +35870,1020 @@ Any pulses with width less than this will be ignored when the filter is enabled. - PAD_DAC1 - configure RTC PAD17 - 0xC8 + EXT_WAKEUP0 + configure EXT0 wakeup + 0xDC 0x20 - 0x40000000 - PDAC1_DAC - PDAC1_DAC - 3 - 8 + SEL + ******* Description configure*** + 27 + 5 read-write + + + + XTL_EXT_CTR + configure gpio pd XTAL + 0xE0 + 0x20 + - PDAC1_XPD_DAC - PDAC1_XPD_DAC - 11 - 1 + SEL + select RTC GPIO 0 ~ 17 to control XTAL + 27 + 5 read-write + + + + SAR_I2C_IO + configure rtc i2c mux + 0xE4 + 0x20 + - PDAC1_DAC_XPD_FORCE - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC - 12 - 1 + SAR_DEBUG_BIT_SEL + ******* Description configure*** + 23 + 5 read-write - PDAC1_FUN_IE - input enable in work mode - 13 - 1 + SAR_I2C_SCL_SEL + ******* Description configure*** + 28 + 2 read-write - PDAC1_SLP_OE - output enable in sleep mode - 14 - 1 + SAR_I2C_SDA_SEL + ******* Description configure*** + 30 + 2 read-write + + + + TOUCH_CTRL + configure touch pad bufmode + 0xE8 + 0x20 + - PDAC1_SLP_IE - input enable in sleep mode - 15 - 1 + IO_TOUCH_BUFSEL + BUF_SEL when touch work without fsm + 0 + 4 read-write - PDAC1_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 16 + IO_TOUCH_BUFMODE + BUF_MODE when touch work without fsm + 4 1 read-write + + + + DATE + version + 0x1FC + 0x20 + 0x02101180 + - PDAC1_FUN_SEL - PDAC1 function sel - 17 - 2 + DATE + version + 0 + 28 read-write + + + + + + SDHOST + SD/MMC Host Controller + SDHOST + 0x60028000 + + 0x0 + 0xA4 + registers + + + + CTRL + Control register + 0x0 + 0x20 + - PDAC1_MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 1 read-write - PDAC1_RUE - PDAC1_RUE - 27 + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 1 read-write - PDAC1_RDE - PDAC1_RDE - 28 + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 1 read-write - PDAC1_DRV - PDAC1_DRV - 29 - 2 + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 read-write - - - - PAD_DAC2 - configure RTC PAD18 - 0xCC - 0x20 - 0x40000000 - - PDAC2_DAC - PDAC2_DAC - 3 - 8 + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 read-write - PDAC2_XPD_DAC - PDAC2_XPD_DAC - 11 + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 1 read-write - PDAC2_DAC_XPD_FORCE - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC - 12 + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 1 read-write - PDAC2_FUN_IE - input enable in work mode - 13 + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 1 read-write - PDAC2_SLP_OE - output enable in sleep mode - 14 + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 1 read-write - PDAC2_SLP_IE - input enable in sleep mode - 15 + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 1 read-write + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + - PDAC2_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 16 - 1 + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 read-write - PDAC2_FUN_SEL - PDAC1 function sel - 17 - 2 + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 read-write - PDAC2_MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 - 1 + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 read-write - PDAC2_RUE - PDAC2_RUE - 27 - 1 + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 read-write + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + - PDAC2_RDE - PDAC2_RDE - 28 - 1 + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 read-write - PDAC2_DRV - PDAC2_DRV - 29 + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 2 read-write - RTC_PAD19 - configure RTC PAD19 - 0xD0 + TMOUT + Data and response timeout configuration register + 0x14 0x20 - 0x50000000 + 0xFFFFFF40 - FUN_IE - input enable in work mode - 13 - 1 + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 read-write - SLP_OE - output enable in sleep mode - 14 - 1 + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 read-write + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + - SLP_IE - input enable in sleep mode - 15 - 1 + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 read-write - SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. 16 - 1 - read-write - - - FUN_SEL - function sel - 17 2 read-write + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + - MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 - 1 + BLOCK_SIZE + Block size. + 0 + 16 read-write + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + - RUE - RUE - 27 - 1 + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 read-write + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + - RDE - RDE - 28 - 1 + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 read-write - DRV - DRV - 29 + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 2 read-write - RTC_PAD20 - configure RTC PAD20 - 0xD4 + CMDARG + Command argument data register + 0x28 0x20 - 0x50000000 - FUN_IE - input enable in work mode - 13 - 1 + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 read-write + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + - SLP_OE - output enable in sleep mode - 14 - 1 + INDEX + Command index. + 0 + 6 read-write - SLP_IE - input enable in sleep mode - 15 + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 1 read-write - SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 16 + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 1 read-write - FUN_SEL - function sel - 17 - 2 + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 read-write - MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 1 read-write - RUE - RUE - 27 + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 1 read-write - RDE - RDE - 28 + TRANSFER_MODE + 0: Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 1 read-write - DRV - DRV - 29 - 2 + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 read-write - - - - RTC_PAD21 - configure RTC PAD21 - 0xD8 - 0x20 - 0x50000000 - - FUN_IE - input enable in work mode + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. 13 1 read-write - SLP_OE - output enable in sleep mode + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. 14 1 read-write - SLP_IE - input enable in sleep mode + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. 15 1 read-write - SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. 16 - 1 + 5 read-write - FUN_SEL - function sel - 17 - 2 + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 read-write - MUX_SEL - 1: use RTC GPIO,0: use digital GPIO - 19 + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 1 read-write - RUE - RUE - 27 + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 1 read-write - RDE - RDE - 28 + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 1 read-write - DRV - DRV - 29 - 2 + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 read-write - EXT_WAKEUP0 - configure EXT0 wakeup - 0xDC + RESP0 + Response data register + 0x30 0x20 - SEL - ******* Description configure*** - 27 - 5 - read-write + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only - XTL_EXT_CTR - configure gpio pd XTAL - 0xE0 + RESP1 + Long response data register + 0x34 0x20 - SEL - select RTC GPIO 0 ~ 17 to control XTAL - 27 - 5 - read-write + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only - SAR_I2C_IO - configure rtc i2c mux - 0xE4 + RESP2 + Long response data register + 0x38 0x20 - SAR_DEBUG_BIT_SEL - ******* Description configure*** - 23 - 5 - read-write + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + RESP3 + Long response data register + 0x3C + 0x20 + - SAR_I2C_SCL_SEL - ******* Description configure*** - 28 + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 read-write - SAR_I2C_SDA_SEL - ******* Description configure*** - 30 + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 2 read-write - TOUCH_CTRL - configure touch pad bufmode - 0xE8 + STATUS + SD/MMC status register + 0x48 0x20 + 0x00000716 - IO_TOUCH_BUFSEL - BUF_SEL when touch work without fsm + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. 0 - 4 - read-write + 1 + read-only - IO_TOUCH_BUFMODE - BUF_MODE when touch work without fsm + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 1 - read-write + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only - DATE - version - 0x1FC + FIFOTH + FIFO configuration register + 0x4C 0x20 - 0x02101180 - DATE - version + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 0 - 28 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 read-write - - - - SENSITIVE - Peripheral SENSITIVE - SENSITIVE - 0x600C1000 - - 0x0 - 0x314 - registers - - - CACHE_DATAARRAY_CONNECT_0 - Cache data array configuration register 0. - 0x0 + CDETECT + Card detect register + 0x50 0x20 - CACHE_DATAARRAY_CONNECT_LOCK - Set 1 to lock cache data array registers. + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. 0 - 1 - read-write + 2 + read-only - CACHE_DATAARRAY_CONNECT_1 - Cache data array configuration register 1. - 0x4 + WRTPRT + Card write protection (WP) status register + 0x54 0x20 - 0x000000FF - CACHE_DATAARRAY_CONNECT_FLATTEN - Cache data array connection configuration. + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. 0 - 8 - read-write + 2 + read-only - APB_PERIPHERAL_ACCESS_0 - APB peripheral configuration register 0. - 0x8 + TCBCNT + Transferred byte count register + 0x5C 0x20 - APB_PERIPHERAL_ACCESS_LOCK - Set 1 to lock APB peripheral Configuration Register. + TCBCNT + Number of bytes transferred by CIU unit to card. 0 - 1 - read-write + 32 + read-only - APB_PERIPHERAL_ACCESS_1 - APB peripheral configuration register 1. - 0xC + TBBCNT + Transferred byte count register + 0x60 0x20 - 0x00000001 - APB_PERIPHERAL_ACCESS_SPLIT_BURST - Set 1 to support split function for AHB access to APB peripherals. + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. 0 - 1 - read-write + 32 + read-only - INTERNAL_SRAM_USAGE_0 - Internal SRAM configuration register 0. - 0x10 + DEBNCE + Debounce filter time configuration register + 0x64 0x20 - INTERNAL_SRAM_USAGE_LOCK - Set 1 to lock internal SRAM Configuration Register. + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. 0 - 1 + 24 read-write - INTERNAL_SRAM_USAGE_1 - Internal SRAM configuration register 1. - 0x14 + USRID + User ID (scratchpad) register + 0x68 0x20 - 0x000007FF - INTERNAL_SRAM_ICACHE_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. 0 - 2 - read-write - - - INTERNAL_SRAM_DCACHE_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. - 2 - 2 + 32 read-write + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + - INTERNAL_SRAM_CPU_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. - 4 - 7 - read-write + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only - INTERNAL_SRAM_USAGE_2 - Internal SRAM configuration register 2. - 0x18 + HCON + Hardware feature register + 0x70 0x20 + 0x03444CC3 - INTERNAL_SRAM_CORE0_TRACE_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + CARD_TYPE + Hardware support SDIO and MMC. 0 - 7 - read-write + 1 + read-only - INTERNAL_SRAM_CORE1_TRACE_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. 7 - 7 - read-write + 3 + read-only - INTERNAL_SRAM_CORE0_TRACE_ALLOC - Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. - 14 + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 2 - read-write + read-only + + + + UHS + UHS-1 register + 0x74 + 0x20 + - INTERNAL_SRAM_CORE1_TRACE_ALLOC - Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. 16 2 read-write @@ -36634,3207 +36891,3774 @@ Any pulses with width less than this will be ignored when the filter is enabled. - INTERNAL_SRAM_USAGE_3 - Internal SRAM configuration register 3. - 0x1C + RST_N + Card reset register + 0x78 0x20 + 0x00000001 - INTERNAL_SRAM_MAC_DUMP_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. 0 - 4 + 2 read-write - INTERNAL_SRAM_USAGE_4 - Internal SRAM configuration register 4. - 0x20 + BMOD + Burst mode transfer configuration register + 0x80 0x20 - INTERNAL_SRAM_LOG_USAGE - Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. 0 - 7 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 read-write - RETENTION_DISABLE - Retention configuration register. - 0x24 + PLDMND + Poll demand configuration register + 0x84 0x20 - RETENTION_DISABLE - Set 1 to disable retention function and lock disable state. + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . 0 - 1 - read-write + 32 + write-only - CACHE_TAG_ACCESS_0 - Cache tag configuration register 0. - 0x28 + DBADDR + Descriptor base address register + 0x88 0x20 - CACHE_TAG_ACCESS_LOCK - Set 1 to lock cache tag Configuration Register. + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. 0 - 1 + 32 read-write - CACHE_TAG_ACCESS_1 - Cache tag configuration register 1. - 0x2C + IDSTS + IDMAC status register + 0x8C 0x20 - 0x0000000F - PRO_I_TAG_RD_ACS - Set 1 to enable Icache read access tag memory. + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. 0 1 read-write - PRO_I_TAG_WR_ACS - Set 1 to enable Icache wrtie access tag memory. + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. 1 1 read-write - PRO_D_TAG_RD_ACS - Set 1 to enable Dcache read access tag memory. + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. 2 1 read-write - PRO_D_TAG_WR_ACS - Set 1 to enable Dcache wrtie access tag memory. - 3 + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 1 read-write - - - - CACHE_MMU_ACCESS_0 - Cache MMU configuration register 0. - 0x30 - 0x20 - - CACHE_MMU_ACCESS_LOCK - Set 1 to lock cache MMU registers. - 0 + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 1 read-write - - - - CACHE_MMU_ACCESS_1 - Cache MMU configuration register 1. - 0x34 - 0x20 - 0x00000003 - - PRO_MMU_RD_ACS - Set 1 to enable read access MMU memory. - 0 + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 1 read-write - PRO_MMU_WR_ACS - Set 1 to enable write access MMU memory. - 1 + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 1 read-write + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + - DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 - spi2 dma permission configuration register 0. - 0x38 + IDINTEN + IDMAC interrupt enable register + 0x90 0x20 - DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK - Set 1 to lock spi2 dma permission Configuration Register. + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. 0 1 read-write - - - - DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 - spi2 dma permission configuration register 1. - 0x3C - 0x20 - 0x00000FFF - - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 - spi2's permission(store,load) in data region0 of SRAM - 0 - 2 + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 read-write - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 - spi2's permission(store,load) in data region1 of SRAM + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. 2 - 2 + 1 read-write - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 - spi2's permission(store,load) in data region2 of SRAM + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. 4 - 2 + 1 read-write - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 - spi2's permission(store,load) in data region3 of SRAM - 6 - 2 + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 read-write - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - spi2's permission(store,load) in dcache data sram block0 + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. 8 - 2 + 1 read-write - DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - spi2's permission(store,load) in dcache data sram block1 - 10 - 2 + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 read-write - DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 - spi3 dma permission configuration register 0. - 0x40 + DSCADDR + Host descriptor address pointer + 0x94 0x20 - DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK - Set 1 to lock spi3 dma permission Configuration Register. + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. 0 - 1 - read-write + 32 + read-only - DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 - spi3 dma permission configuration register 1. - 0x44 + BUFADDR + Host buffer address pointer register + 0x98 0x20 - 0x00000FFF - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 - spi3's permission(store,load) in data region0 of SRAM + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. 0 - 2 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 read-write - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 - spi3's permission(store,load) in data region1 of SRAM + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. 2 - 2 + 1 read-write - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 - spi3's permission(store,load) in data region2 of SRAM - 4 - 2 + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 read-write + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 - spi3's permission(store,load) in data region3 of SRAM - 6 + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 2 read-write - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - spi3's permission(store,load) in dcache data sram block0 - 8 - 2 + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 read-write + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + - DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - spi3's permission(store,load) in dcache data sram block1 - 10 - 2 + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 - uhci0 dma permission configuration register 0. - 0x48 + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 0x20 - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK - Set 1 to lock uhci0 dma permission Configuration Register. + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . 0 - 1 + 32 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 - uhci0 dma permission configuration register 1. - 0x4C + CLK_EDGE_SEL + SDIO control register. + 0x800 0x20 - 0x00000FFF + 0x00820200 - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 - uhci0's permission(store,load) in data region0 of SRAM + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. 0 - 2 + 3 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 - uhci0's permission(store,load) in data region1 of SRAM - 2 - 2 + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 - uhci0's permission(store,load) in data region2 of SRAM - 4 - 2 + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 - uhci0's permission(store,load) in data region3 of SRAM - 6 - 2 + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - uhci0's permission(store,load) in dcache data sram block0 - 8 - 2 + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 read-write - DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - uhci0's permission(store,load) in dcache data sram block1 - 10 - 2 + CCLLKIN_EDGE_N + The clock division of cclk_in. + 17 + 4 read-write - - - - DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 - i2s0 dma permission configuration register 0. - 0x50 - 0x20 - - DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK - Set 1 to lock i2s0 dma permission Configuration Register. - 0 + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable. + 23 1 read-write + + + + SENS + SENS Peripheral + SENS + 0x60008800 + + 0x0 + 0x11C + registers + + - DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 - i2s0 dma permission configuration register 1. - 0x54 + SAR_READER1_CTRL + configure saradc1 reader + 0x0 0x20 - 0x00000FFF + 0x20040002 - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 - i2s0's permission(store,load) in data region0 of SRAM + SAR_SAR1_CLK_DIV + clock divider 0 - 2 - read-write - - - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 - i2s0's permission(store,load) in data region1 of SRAM - 2 - 2 + 8 read-write - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 - i2s0's permission(store,load) in data region2 of SRAM - 4 - 2 + SAR_SAR1_CLK_GATED + no public + 18 + 1 read-write - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 - i2s0's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR_SAR1_SAMPLE_NUM + no public + 19 + 8 read-write - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - i2s0's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR_SAR1_DATA_INV + Invert SAR ADC1 data + 28 + 1 read-write - DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - i2s0's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_SAR1_INT_EN + enable saradc1 to send out interrupt + 29 + 1 read-write - DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 - i2s1 dma permission configuration register 0. - 0x58 + SAR_READER1_STATUS + get saradc1 reader controller status + 0x4 0x20 - DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK - Set 1 to lock i2s1 dma permission Configuration Register. + SAR_SAR1_READER_STATUS + get saradc1 reader controller status 0 - 1 - read-write + 32 + read-only - DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 - i2s1 dma permission configuration register 1. - 0x5C + SAR_MEAS1_CTRL1 + no public + 0x8 0x20 - 0x00000FFF - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 - i2s1's permission(store,load) in data region0 of SRAM - 0 - 2 - read-write - - - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 - i2s1's permission(store,load) in data region1 of SRAM - 2 - 2 - read-write - - - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 - i2s1's permission(store,load) in data region2 of SRAM - 4 + FORCE_XPD_AMP + no public + 24 2 read-write - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 - i2s1's permission(store,load) in data region3 of SRAM - 6 + AMP_RST_FB_FORCE + no public + 26 2 read-write - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - i2s1's permission(store,load) in dcache data sram block0 - 8 + AMP_SHORT_REF_FORCE + no public + 28 2 read-write - DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - i2s1's permission(store,load) in dcache data sram block1 - 10 + AMP_SHORT_REF_GND_FORCE + no public + 30 2 read-write - DMA_APBPERI_MAC_PMS_CONSTRAIN_0 - mac dma permission configuration register 0. - 0x60 + SAR_MEAS1_CTRL2 + configure saradc1 controller + 0xC 0x20 - DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK - Set 1 to lock mac dma permission Configuration Register. + MEAS1_DATA_SAR + SAR ADC1 data 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication + 16 1 - read-write + read-only - - - - DMA_APBPERI_MAC_PMS_CONSTRAIN_1 - mac dma permission configuration register 1. - 0x64 - 0x20 - 0x00000FFF - - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 - mac's permission(store,load) in data region0 of SRAM - 0 - 2 + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion + 17 + 1 read-write - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 - mac's permission(store,load) in data region1 of SRAM - 2 - 2 + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW + 18 + 1 read-write - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 - mac's permission(store,load) in data region2 of SRAM - 4 - 2 + SAR1_EN_PAD + SAR ADC1 pad enable bitmap + 19 + 12 read-write - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 - mac's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW + 31 + 1 read-write + + + + SAR_MEAS1_MUX + configure saradc1 controller + 0x10 + 0x20 + - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - mac's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL + 31 + 1 read-write + + + + SAR_ATTEN1 + configure saradc1 controller + 0x14 + 0x20 + 0xFFFFFFFF + - DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - mac's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR1_ATTEN + 2-bit attenuation for each pad + 0 + 32 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 - backup dma permission configuration register 0. - 0x68 + SAR_AMP_CTRL1 + no public + 0x18 0x20 + 0x000A000A - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK - Set 1 to lock backup dma permission Configuration Register. + SAR_AMP_WAIT1 + no public 0 - 1 + 16 + read-write + + + SAR_AMP_WAIT2 + no public + 16 + 16 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 - backup dma permission configuration register 1. - 0x6C + SAR_AMP_CTRL2 + no public + 0x1C 0x20 - 0x00000FFF + 0x000A0000 - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 - backup's permission(store,load) in data region0 of SRAM + SAR_SAR1_DAC_XPD_FSM_IDLE + no public 0 - 2 + 1 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 - backup's permission(store,load) in data region1 of SRAM - 2 - 2 + SAR_XPD_SAR_AMP_FSM_IDLE + no public + 1 + 1 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 - backup's permission(store,load) in data region2 of SRAM - 4 - 2 + SAR_AMP_RST_FB_FSM_IDLE + no public + 2 + 1 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 - backup's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR_AMP_SHORT_REF_FSM_IDLE + no public + 3 + 1 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - backup's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR_AMP_SHORT_REF_GND_FSM_IDLE + no public + 4 + 1 read-write - DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - backup's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_XPD_SAR_FSM_IDLE + no public + 5 + 1 read-write - - - - DMA_APBPERI_AES_PMS_CONSTRAIN_0 - aes dma permission configuration register 0. - 0x70 - 0x20 - - DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK - Set 1 to lock aes dma permission Configuration Register. - 0 + SAR_RSTB_FSM_IDLE + no public + 6 1 read-write + + SAR_AMP_WAIT3 + no public + 16 + 16 + read-write + - DMA_APBPERI_AES_PMS_CONSTRAIN_1 - aes dma permission configuration register 1. - 0x74 + SAR_AMP_CTRL3 + no public + 0x20 0x20 - 0x00000FFF + 0x007338F3 - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 - aes's permission(store,load) in data region0 of SRAM + SAR1_DAC_XPD_FSM + no public 0 - 2 + 4 read-write - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 - aes's permission(store,load) in data region1 of SRAM - 2 - 2 + XPD_SAR_AMP_FSM + no public + 4 + 4 read-write - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 - aes's permission(store,load) in data region2 of SRAM - 4 - 2 + AMP_RST_FB_FSM + no public + 8 + 4 read-write - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 - aes's permission(store,load) in data region3 of SRAM - 6 - 2 + AMP_SHORT_REF_FSM + no public + 12 + 4 read-write - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - aes's permission(store,load) in dcache data sram block0 - 8 - 2 + AMP_SHORT_REF_GND_FSM + no public + 16 + 4 read-write - DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - aes's permission(store,load) in dcache data sram block1 - 10 - 2 + XPD_SAR_FSM + no public + 20 + 4 read-write - - - - DMA_APBPERI_SHA_PMS_CONSTRAIN_0 - sha dma permission configuration register 0. - 0x78 - 0x20 - - DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK - Set 1 to lock sha dma permission Configuration Register. - 0 - 1 + RSTB_FSM + no public + 24 + 4 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_1 - sha dma permission configuration register 1. - 0x7C + SAR_READER2_CTRL + configure saradc2 reader + 0x24 0x20 - 0x00000FFF + 0x40050002 - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 - sha's permission(store,load) in data region0 of SRAM + SAR_SAR2_CLK_DIV + clock divider 0 - 2 + 8 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 - sha's permission(store,load) in data region1 of SRAM - 2 + SAR_SAR2_WAIT_ARB_CYCLE + wait arbit stable after sar_done + 16 2 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 - sha's permission(store,load) in data region2 of SRAM - 4 - 2 + SAR_SAR2_CLK_GATED + ******* Description *********** + 18 + 1 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 - sha's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR_SAR2_SAMPLE_NUM + ******* Description *********** + 19 + 8 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - sha's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR_SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 read-write - DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - sha's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_SAR2_INT_EN + enable saradc2 to send out interrupt + 30 + 1 read-write - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 - adc_dac dma permission configuration register 0. - 0x80 + SAR_READER2_STATUS + get saradc1 reader controller status + 0x28 0x20 - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK - Set 1 to lock adc_dac dma permission Configuration Register. + SAR_SAR2_READER_STATUS + get saradc1 reader controller status 0 - 1 - read-write + 32 + read-only - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 - adc_dac dma permission configuration register 1. - 0x84 + SAR_MEAS2_CTRL1 + configure saradc2 controller + 0x2C 0x20 - 0x00000FFF + 0x07020200 - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 - adc_dac's permission(store,load) in data region0 of SRAM + SAR_SAR2_CNTL_STATE + saradc2_cntl_fsm 0 - 2 - read-write + 3 + read-only - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 - adc_dac's permission(store,load) in data region1 of SRAM - 2 - 2 + SAR_SAR2_PWDET_CAL_EN + rtc control pwdet enable + 3 + 1 read-write - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 - adc_dac's permission(store,load) in data region2 of SRAM + SAR_SAR2_PKDET_CAL_EN + rtc control pkdet enable 4 - 2 + 1 read-write - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 - adc_dac's permission(store,load) in data region3 of SRAM + SAR_SAR2_EN_TEST + SAR2_EN_TEST + 5 + 1 + read-write + + + SAR_SAR2_RSTB_FORCE + no public 6 2 read-write - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - adc_dac's permission(store,load) in dcache data sram block0 + SAR_SAR2_STANDBY_WAIT + no public 8 - 2 + 8 read-write - DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - adc_dac's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_SAR2_RSTB_WAIT + no public + 16 + 8 read-write - - - - DMA_APBPERI_RMT_PMS_CONSTRAIN_0 - rmt dma permission configuration register 0. - 0x88 - 0x20 - - DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK - Set 1 to lock rmt dma permission Configuration Register. - 0 - 1 + SAR_SAR2_XPD_WAIT + no public + 24 + 8 read-write - DMA_APBPERI_RMT_PMS_CONSTRAIN_1 - rmt dma permission configuration register 1. - 0x8C + SAR_MEAS2_CTRL2 + configure saradc2 controller + 0x30 0x20 - 0x00000FFF - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 - rmt's permission(store,load) in data region0 of SRAM + MEAS2_DATA_SAR + SAR ADC2 data 0 - 2 - read-write + 16 + read-only - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 - rmt's permission(store,load) in data region1 of SRAM - 2 - 2 - read-write + MEAS2_DONE_SAR + SAR ADC2 conversion done indication + 16 + 1 + read-only - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 - rmt's permission(store,load) in data region2 of SRAM - 4 - 2 + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion + 17 + 1 read-write - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 - rmt's permission(store,load) in data region3 of SRAM - 6 - 2 + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW + 18 + 1 read-write - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - rmt's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR2_EN_PAD + SAR ADC2 pad enable bitmap + 19 + 12 read-write - DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - rmt's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW + 31 + 1 read-write - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 - lcd_cam dma permission configuration register 0. - 0x90 + SAR_MEAS2_MUX + configure saradc2 controller + 0x34 0x20 - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK - Set 1 to lock lcd_cam dma permission Configuration Register. - 0 + SAR2_PWDET_CCT + SAR2_PWDET_CCT + 28 + 3 + read-write + + + SAR2_RTC_FORCE + in sleep, force to use rtc to control ADC + 31 1 read-write - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 - lcd_cam dma permission configuration register 1. - 0x94 + SAR_ATTEN2 + configure saradc2 controller + 0x38 0x20 - 0x00000FFF + 0xFFFFFFFF - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 - lcd_cam's permission(store,load) in data region0 of SRAM + SAR2_ATTEN + 2-bit attenuation for each pad 0 - 2 + 32 read-write + + + + SAR_POWER_XPD_SAR + configure power of saradc + 0x3C + 0x20 + - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 - lcd_cam's permission(store,load) in data region1 of SRAM - 2 + FORCE_XPD_SAR + force power on/off saradc + 29 2 read-write - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 - lcd_cam's permission(store,load) in data region2 of SRAM - 4 - 2 + SARCLK_EN + no public + 31 + 1 read-write + + + + SAR_SLAVE_ADDR1 + configure i2c slave address + 0x40 + 0x20 + - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 - lcd_cam's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR_I2C_SLAVE_ADDR1 + configure i2c slave address1 + 0 + 11 read-write - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - lcd_cam's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR_I2C_SLAVE_ADDR0 + configure i2c slave address0 + 11 + 11 read-write - DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - lcd_cam's permission(store,load) in dcache data sram block1 - 10 - 2 - read-write + SAR_SARADC_MEAS_STATUS + no public + 22 + 8 + read-only - DMA_APBPERI_USB_PMS_CONSTRAIN_0 - usb dma permission configuration register 0. - 0x98 + SAR_SLAVE_ADDR2 + configure i2c slave address + 0x44 0x20 - DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK - Set 1 to lock usb dma permission Configuration Register. + SAR_I2C_SLAVE_ADDR3 + configure i2c slave address3 0 - 1 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR2 + configure i2c slave address2 + 11 + 11 read-write - DMA_APBPERI_USB_PMS_CONSTRAIN_1 - usb dma permission configuration register 1. - 0x9C + SAR_SLAVE_ADDR3 + configure i2c slave address + 0x48 0x20 - 0x00000FFF - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 - usb's permission(store,load) in data region0 of SRAM + SAR_I2C_SLAVE_ADDR5 + configure i2c slave address5 0 - 2 - read-write - - - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 - usb's permission(store,load) in data region1 of SRAM - 2 - 2 - read-write - - - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 - usb's permission(store,load) in data region2 of SRAM - 4 - 2 - read-write - - - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 - usb's permission(store,load) in data region3 of SRAM - 6 - 2 - read-write - - - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - usb's permission(store,load) in dcache data sram block0 - 8 - 2 + 11 read-write - DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - usb's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_I2C_SLAVE_ADDR4 + configure i2c slave address4 + 11 + 11 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_0 - lc dma permission configuration register 0. - 0xA0 + SAR_SLAVE_ADDR4 + configure i2c slave address + 0x4C 0x20 - DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK - Set 1 to lock lc dma permission Configuration Register. + SAR_I2C_SLAVE_ADDR7 + configure i2c slave address7 0 - 1 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR6 + configure i2c slave address6 + 11 + 11 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_1 - lc dma permission configuration register 1. - 0xA4 + SAR_TSENS_CTRL + configure tsens controller + 0x50 0x20 - 0x00000FFF + 0x00019000 - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 - lc's permission(store,load) in data region0 of SRAM + SAR_TSENS_OUT + temperature sensor data out 0 - 2 - read-write + 8 + read-only - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 - lc's permission(store,load) in data region1 of SRAM - 2 - 2 + SAR_TSENS_READY + indicate temperature sensor out ready + 8 + 1 + read-only + + + SAR_TSENS_INT_EN + enable temperature sensor to send out interrupt + 12 + 1 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 - lc's permission(store,load) in data region2 of SRAM - 4 - 2 + SAR_TSENS_IN_INV + invert temperature sensor data + 13 + 1 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 - lc's permission(store,load) in data region3 of SRAM - 6 - 2 + SAR_TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - lc's permission(store,load) in dcache data sram block0 - 8 - 2 + SAR_TSENS_POWER_UP + temperature sensor power up + 22 + 1 read-write - DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - lc's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_TSENS_POWER_UP_FORCE + 1: dump out & power up controlled by SW 0: by FSM + 23 + 1 read-write - - - - DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 - sdio dma permission configuration register 0. - 0xA8 - 0x20 - - DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK - Set 1 to lock sdio dma permission Configuration Register. - 0 + SAR_TSENS_DUMP_OUT + temperature sensor dump out only active when reg_tsens_power_up_force = 1 + 24 1 read-write - DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 - sdio dma permission configuration register 1. - 0xAC + SAR_TSENS_CTRL2 + configure tsens controller + 0x54 0x20 - 0x00000FFF + 0x00004002 - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 - sdio's permission(store,load) in data region0 of SRAM + SAR_TSENS_XPD_WAIT + no public 0 - 2 - read-write - - - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 - sdio's permission(store,load) in data region1 of SRAM - 2 - 2 - read-write - - - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 - sdio's permission(store,load) in data region2 of SRAM - 4 - 2 - read-write - - - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 - sdio's permission(store,load) in data region3 of SRAM - 6 - 2 + 12 read-write - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 - sdio's permission(store,load) in dcache data sram block0 - 8 + SAR_TSENS_XPD_FORCE + no public + 12 2 read-write - DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 - sdio's permission(store,load) in dcache data sram block1 - 10 - 2 + SAR_TSENS_CLK_INV + no public + 14 + 1 read-write - DMA_APBPERI_PMS_MONITOR_0 - dma permission monitor configuration register 0. - 0xB0 + SAR_I2C_CTRL + configure rtc i2c controller by sw + 0x58 0x20 - DMA_APBPERI_PMS_MONITOR_LOCK - Set 1 to lock dma permission monitor Configuration Register. + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 0 - 1 + 28 read-write - - - - DMA_APBPERI_PMS_MONITOR_1 - dma permission monitor configuration register 1. - 0xB4 - 0x20 - 0x00000003 - - DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear dma_pms_monitor_violate interrupt - 0 + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 1 read-write - DMA_APBPERI_PMS_MONITOR_VIOLATE_EN - Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt. - 1 + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 1 read-write - DMA_APBPERI_PMS_MONITOR_2 - dma permission monitor configuration register 2. - 0xB8 + SAR_TOUCH_CONF + configure touch controller + 0x5C 0x20 + 0xFFF07FFF - DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR - recorded dma's interrupt status when dma access violated permission + SAR_TOUCH_OUTEN + touch controller output enable 0 + 15 + read-write + + + SAR_TOUCH_STATUS_CLR + clear all touch active status + 15 1 - read-only + write-only - DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD - recorded dma's world status when dma access violated permission - 1 + SAR_TOUCH_DATA_SEL + 3: smooth data 2: baseline 1,0: raw_data + 16 2 + read-write + + + SAR_TOUCH_DENOISE_END + touch_denoise_done + 18 + 1 read-only - DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR - recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16 - 3 - 22 + SAR_TOUCH_UNIT_END + touch_unit_done + 19 + 1 read-only + + SAR_TOUCH_APPROACH_PAD2 + indicate which pad is approach pad2 + 20 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD1 + indicate which pad is approach pad1 + 24 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD0 + indicate which pad is approach pad0 + 28 + 4 + read-write + - DMA_APBPERI_PMS_MONITOR_3 - dma permission monitor configuration register 3. - 0xBC + SAR_TOUCH_DENOISE + configure touch controller + 0x60 0x20 - DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR - recorded dma's write status when dma access violated permission, 1(write), 0(read) + DATA + configure touch controller 0 - 1 - read-only - - - DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN - recorded dma's byte enable status when dma access violated permission - 1 - 16 + 22 read-only - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 - sram split line configuration register 0 - 0xC0 + SAR_TOUCH_THRES1 + configure touch thres of touch pad + 0x64 0x20 - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK - Set 1 to lock sram split configuration register + SAR_TOUCH_OUT_TH1 + Finger threshold for touch pad 1 0 - 1 + 22 read-write - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 - sram split line configuration register 1 - 0xC4 + SAR_TOUCH_THRES2 + configure touch thres of touch pad + 0x68 0x20 - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + SAR_TOUCH_OUT_TH2 + Finger threshold for touch pad 2 0 - 2 + 22 read-write + + + + SAR_TOUCH_THRES3 + configure touch thres of touch pad + 0x6C + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 - 2 - 2 + SAR_TOUCH_OUT_TH3 + Finger threshold for touch pad 3 + 0 + 22 read-write + + + + SAR_TOUCH_THRES4 + configure touch thres of touch pad + 0x70 + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 - 4 - 2 + SAR_TOUCH_OUT_TH4 + Finger threshold for touch pad 4 + 0 + 22 read-write + + + + SAR_TOUCH_THRES5 + configure touch thres of touch pad + 0x74 + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 - 6 - 2 + SAR_TOUCH_OUT_TH5 + Finger threshold for touch pad 5 + 0 + 22 read-write + + + + SAR_TOUCH_THRES6 + configure touch thres of touch pad + 0x78 + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 - 8 - 2 + SAR_TOUCH_OUT_TH6 + Finger threshold for touch pad 6 + 0 + 22 read-write + + + + SAR_TOUCH_THRES7 + configure touch thres of touch pad + 0x7C + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 - 10 - 2 + SAR_TOUCH_OUT_TH7 + Finger threshold for touch pad 7 + 0 + 22 read-write + + + + SAR_TOUCH_THRES8 + configure touch thres of touch pad + 0x80 + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 - 12 - 2 + SAR_TOUCH_OUT_TH8 + Finger threshold for touch pad 8 + 0 + 22 read-write + + + + SAR_TOUCH_THRES9 + configure touch thres of touch pad + 0x84 + 0x20 + - CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR - splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address - 14 - 8 + SAR_TOUCH_OUT_TH9 + Finger threshold for touch pad 9 + 0 + 22 read-write - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 - sram split line configuration register 1 - 0xC8 + SAR_TOUCH_THRES10 + configure touch thres of touch pad + 0x88 0x20 - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + SAR_TOUCH_OUT_TH10 + Finger threshold for touch pad 10 0 - 2 + 22 read-write + + + + SAR_TOUCH_THRES11 + configure touch thres of touch pad + 0x8C + 0x20 + - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 - 2 - 2 + SAR_TOUCH_OUT_TH11 + Finger threshold for touch pad 11 + 0 + 22 read-write + + + + SAR_TOUCH_THRES12 + configure touch thres of touch pad + 0x90 + 0x20 + - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 - 4 - 2 + SAR_TOUCH_OUT_TH12 + Finger threshold for touch pad 12 + 0 + 22 read-write + + + + SAR_TOUCH_THRES13 + configure touch thres of touch pad + 0x94 + 0x20 + - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 - 6 - 2 + SAR_TOUCH_OUT_TH13 + Finger threshold for touch pad 13 + 0 + 22 read-write + + + + SAR_TOUCH_THRES14 + configure touch thres of touch pad + 0x98 + 0x20 + - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 - 8 - 2 + SAR_TOUCH_OUT_TH14 + Finger threshold for touch pad 14 + 0 + 22 read-write + + + + SAR_TOUCH_CHN_ST + Get touch channel status + 0x9C + 0x20 + - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 - 10 - 2 - read-write + SAR_TOUCH_PAD_ACTIVE + touch active status + 0 + 15 + read-only - CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 - 12 - 2 - read-write + SAR_TOUCH_CHANNEL_CLR + Clear touch channel + 15 + 15 + write-only - CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR - splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address - 14 - 8 - read-write + SAR_TOUCH_MEAS_DONE + get touch meas done + 31 + 1 + read-only - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 - sram split line configuration register 1 - 0xCC + SAR_TOUCH_STATUS0 + get touch scan status + 0xA0 0x20 - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 - 0 - 2 - read-write - - - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 - 2 - 2 - read-write - - - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 - 4 - 2 - read-write - - - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 - 6 - 2 - read-write + SAR_TOUCH_SCAN_CURR + current sample channel + 22 + 4 + read-only + + + + SAR_TOUCH_STATUS1 + touch channel status of touch pad 1 + 0xA4 + 0x20 + - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 - 8 - 2 - read-write + SAR_TOUCH_PAD1_DATA + touch data debounce of touch pad 1 + 0 + 22 + read-only - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 - 10 - 2 - read-write + SAR_TOUCH_PAD1_DEBOUNCE + touch current debounce of touch pad 1 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS2 + touch channel status of touch pad 2 + 0xA8 + 0x20 + - CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 - 12 - 2 - read-write + SAR_TOUCH_PAD2_DATA + touch data debounce of touch pad 2 + 0 + 22 + read-only - CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR - splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address - 14 - 8 - read-write + SAR_TOUCH_PAD2_DEBOUNCE + touch current debounce of touch pad 2 + 29 + 3 + read-only - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 - sram split line configuration register 1 - 0xD0 + SAR_TOUCH_STATUS3 + touch channel status of touch pad 3 + 0xAC 0x20 - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + SAR_TOUCH_PAD3_DATA + touch data debounce of touch pad 3 0 - 2 - read-write + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 - 2 - 2 - read-write + SAR_TOUCH_PAD3_DEBOUNCE + touch current debounce of touch pad 3 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS4 + touch channel status of touch pad 4 + 0xB0 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 - 4 - 2 - read-write + SAR_TOUCH_PAD4_DATA + touch data debounce of touch pad 4 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 - 6 - 2 - read-write + SAR_TOUCH_PAD4_DEBOUNCE + touch current debounce of touch pad 4 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS5 + touch channel status of touch pad 5 + 0xB4 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 - 8 - 2 - read-write + SAR_TOUCH_PAD5_DATA + touch data debounce of touch pad 5 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 - 10 - 2 - read-write + SAR_TOUCH_PAD5_DEBOUNCE + touch current debounce of touch pad 5 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS6 + touch channel status of touch pad 6 + 0xB8 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 - 12 - 2 - read-write + SAR_TOUCH_PAD6_DATA + touch data debounce of touch pad 6 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR - splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address - 14 - 8 - read-write + SAR_TOUCH_PAD6_DEBOUNCE + touch current debounce of touch pad 6 + 29 + 3 + read-only - CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 - sram split line configuration register 1 - 0xD4 + SAR_TOUCH_STATUS7 + touch channel status of touch pad 7 + 0xBC 0x20 - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + SAR_TOUCH_PAD7_DATA + touch data debounce of touch pad 7 0 - 2 - read-write + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 - 2 - 2 - read-write + SAR_TOUCH_PAD7_DEBOUNCE + touch current debounce of touch pad 7 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS8 + touch channel status of touch pad 8 + 0xC0 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 - 4 - 2 - read-write + SAR_TOUCH_PAD8_DATA + touch data debounce of touch pad 8 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 - 6 - 2 - read-write + SAR_TOUCH_PAD8_DEBOUNCE + touch current debounce of touch pad 8 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS9 + touch channel status of touch pad 9 + 0xC4 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 - 8 - 2 - read-write + SAR_TOUCH_PAD9_DATA + touch data debounce of touch pad 9 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 - 10 - 2 - read-write + SAR_TOUCH_PAD9_DEBOUNCE + touch current debounce of touch pad 9 + 29 + 3 + read-only + + + + SAR_TOUCH_STATUS10 + touch channel status of touch pad 10 + 0xC8 + 0x20 + - CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 - 12 - 2 - read-write + SAR_TOUCH_PAD10_DATA + touch data debounce of touch pad 10 + 0 + 22 + read-only - CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR - splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address - 14 - 8 - read-write + SAR_TOUCH_PAD10_DEBOUNCE + touch current debounce of touch pad 10 + 29 + 3 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_0 - corex iram0 permission configuration register 0 - 0xD8 + SAR_TOUCH_STATUS11 + touch channel status of touch pad 11 + 0xCC 0x20 - CORE_X_IRAM0_PMS_CONSTRAIN_LOCK - Set 1 to lock corex iram0 permission configuration register + SAR_TOUCH_PAD11_DATA + touch data debounce of touch pad 11 0 - 1 - read-write + 22 + read-only + + + SAR_TOUCH_PAD11_DEBOUNCE + touch current debounce of touch pad 11 + 29 + 3 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_1 - corex iram0 permission configuration register 0 - 0xDC + SAR_TOUCH_STATUS12 + touch channel status of touch pad 12 + 0xD0 0x20 - 0x001FFFFF - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 - core0/core1's permission of instruction region0 of SRAM in world1 + SAR_TOUCH_PAD12_DATA + touch data debounce of touch pad 12 0 - 3 - read-write - - - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 - core0/core1's permission of instruction region1 of SRAM in world1 - 3 - 3 - read-write + 22 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 - core0/core1's permission of instruction region2 of SRAM in world1 - 6 + SAR_TOUCH_PAD12_DEBOUNCE + touch current debounce of touch pad 12 + 29 3 - read-write + read-only + + + + SAR_TOUCH_STATUS13 + touch channel status of touch pad 13 + 0xD4 + 0x20 + - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 - core0/core1's permission of instruction region3 of SRAM in world1 - 9 - 3 - read-write + SAR_TOUCH_PAD13_DATA + touch data debounce of touch pad 13 + 0 + 22 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 - core0/core1's permission of icache data sram block0 in world1 - 12 + SAR_TOUCH_PAD13_DEBOUNCE + touch current debounce of touch pad 13 + 29 3 - read-write + read-only + + + + SAR_TOUCH_STATUS14 + touch channel status of touch pad 14 + 0xD8 + 0x20 + - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 - core0/core1's permission of icache data sram block1 in world1 - 15 - 3 - read-write + SAR_TOUCH_PAD14_DATA + touch data debounce of touch pad 14 + 0 + 22 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS - core0/core1's permission of rom in world1 - 18 + SAR_TOUCH_PAD14_DEBOUNCE + touch current debounce of touch pad 14 + 29 3 - read-write + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_2 - corex iram0 permission configuration register 1 - 0xE0 + SAR_TOUCH_STATUS15 + touch channel status of sleep pad + 0xDC 0x20 - 0x001FFFFF - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 - core0/core1's permission of instruction region0 of SRAM in world1 + SAR_TOUCH_SLP_DATA + touch data debounce of sleep pad 0 - 3 - read-write - - - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 - core0/core1's permission of instruction region1 of SRAM in world1 - 3 - 3 - read-write + 22 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 - core0/core1's permission of instruction region2 of SRAM in world1 - 6 + SAR_TOUCH_SLP_DEBOUNCE + touch current debounce of sleep pad + 29 3 - read-write + read-only + + + + SAR_TOUCH_STATUS16 + touch channel status of approach mode + 0xE0 + 0x20 + - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 - core0/core1's permission of instruction region3 of SRAM in world1 - 9 - 3 - read-write + SAR_TOUCH_APPROACH_PAD2_CNT + touch current approach count of approach pad2 + 0 + 8 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 - core0/core1's permission of icache data sram block0 in world1 - 12 - 3 - read-write + SAR_TOUCH_APPROACH_PAD1_CNT + touch current approach count of approach pad1 + 8 + 8 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 - core0/core1's permission of icache data sram block1 in world1 - 15 - 3 - read-write + SAR_TOUCH_APPROACH_PAD0_CNT + touch current approach count of approach pad0 + 16 + 8 + read-only - CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS - core0/core1's permission of rom in world1 - 18 - 3 - read-write + SAR_TOUCH_SLP_APPROACH_CNT + touch current approach count of slp pad + 24 + 8 + read-only - CORE_0_IRAM0_PMS_MONITOR_0 - core0 iram0 permission monitor configuration register 0 + SAR_COCPU_STATE + get cocpu status 0xE4 0x20 - CORE_0_IRAM0_PMS_MONITOR_LOCK - Set 1 to lock core0 iram0 permission monitor register - 0 + SAR_COCPU_DBG_TRIGGER + trigger cocpu debug registers + 25 1 - read-write + write-only - - - - CORE_0_IRAM0_PMS_MONITOR_1 - core0 iram0 permission monitor configuration register 1 - 0xE8 - 0x20 - 0x00000003 - - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear core0 iram0 permission violated interrupt - 0 + SAR_COCPU_CLK_EN_ST + check cocpu whether clk on + 26 1 - read-write + read-only - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt - 1 + SAR_COCPU_RESET_N + check cocpu whether in reset state + 27 1 - read-write + read-only + + + SAR_COCPU_EOI + check cocpu whether in interrupt state + 28 + 1 + read-only + + + SAR_COCPU_TRAP + check cocpu whether in trap state + 29 + 1 + read-only + + + SAR_COCPU_EBREAK + check cocpu whether in ebreak + 30 + 1 + read-only - CORE_0_IRAM0_PMS_MONITOR_2 - core0 iram0 permission monitor configuration register 2 - 0xEC + SAR_COCPU_INT_RAW + the interrupt raw of ulp + 0xE8 0x20 - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR - recorded core0 iram0 pms monitor interrupt status. + SAR_COCPU_TOUCH_DONE_INT_RAW + int from touch done 0 1 read-only - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR - recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + SAR_COCPU_TOUCH_INACTIVE_INT_RAW + int from touch inactive 1 1 read-only - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE - recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + SAR_COCPU_TOUCH_ACTIVE_INT_RAW + int from touch active 2 1 read-only - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD - recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + SAR_COCPU_SARADC1_INT_RAW + int from saradc1 3 - 2 - read-only - - - CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR - recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4 - 5 - 24 + 1 read-only - - - - CORE_1_IRAM0_PMS_MONITOR_0 - core1 iram0 permission monitor configuration register 0 - 0xF0 - 0x20 - - CORE_1_IRAM0_PMS_MONITOR_LOCK - Set 1 to lock core1 iram0 permission monitor register - 0 + SAR_COCPU_SARADC2_INT_RAW + int from saradc2 + 4 1 - read-write + read-only - - - - CORE_1_IRAM0_PMS_MONITOR_1 - core1 iram0 permission monitor configuration register 1 - 0xF4 - 0x20 - 0x00000003 - - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear core1 iram0 permission violated interrupt - 0 + SAR_COCPU_TSENS_INT_RAW + int from tsens + 5 1 - read-write + read-only - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt - 1 + SAR_COCPU_START_INT_RAW + int from start + 6 1 - read-write + read-only - - - - CORE_1_IRAM0_PMS_MONITOR_2 - core1 iram0 permission monitor configuration register 2 - 0xF8 - 0x20 - - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR - recorded core1 iram0 pms monitor interrupt status. - 0 + SAR_COCPU_SW_INT_RAW + int from software + 7 1 read-only - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR - recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). - 1 + SAR_COCPU_SWD_INT_RAW + int from super watch dog + 8 1 read-only - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE - recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). - 2 + SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + int from timeout done + 9 1 read-only - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD - recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. - 3 - 2 + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + int from approach loop done + 10 + 1 read-only - CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR - recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4 - 5 - 24 + SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + int from touch scan done + 11 + 1 read-only - CORE_X_DRAM0_PMS_CONSTRAIN_0 - corex dram0 permission configuration register 0 - 0xFC + SAR_COCPU_INT_ENA + the interrupt enable of ulp + 0xEC 0x20 - CORE_X_DRAM0_PMS_CONSTRAIN_LOCK - Set 1 to lock corex dram0 permission configuration register + SAR_COCPU_TOUCH_DONE_INT_ENA + int enable of touch done 0 1 read-write - - - - CORE_X_DRAM0_PMS_CONSTRAIN_1 - corex dram0 permission configuration register 1 - 0x100 - 0x20 - 0x0FFFFFFF - - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 - core0/core1's permission of data region0 of SRAM in world0. - 0 - 2 + SAR_COCPU_TOUCH_INACTIVE_INT_ENA + int enable of from touch inactive + 1 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 - core0/core1's permission of data region1 of SRAM in world0. + SAR_COCPU_TOUCH_ACTIVE_INT_ENA + int enable of touch active 2 - 2 - read-write - - - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 - core0/core1's permission of data region2 of SRAM in world0. - 4 - 2 - read-write - - - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 - core0/core1's permission of data region3 of SRAM in world0. - 6 - 2 - read-write - - - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 - core0/core1's permission of dcache data sram block0 in world0. - 8 - 2 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 - core0/core1's permission of dcache data sram block1 in world0. - 10 - 2 + SAR_COCPU_SARADC1_INT_ENA + int enable of from saradc1 + 3 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 - core0/core1's permission of data region0 of SRAM in world1. - 12 - 2 + SAR_COCPU_SARADC2_INT_ENA + int enable of from saradc2 + 4 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 - core0/core1's permission of data region1 of SRAM in world1. - 14 - 2 + SAR_COCPU_TSENS_INT_ENA + int enable of tsens + 5 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 - core0/core1's permission of data region2 of SRAM in world1. - 16 - 2 + SAR_COCPU_START_INT_ENA + int enable of start + 6 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 - core0/core1's permission of data region3 of SRAM in world1. - 18 - 2 + SAR_COCPU_SW_INT_ENA + int enable of software + 7 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 - core0/core1's permission of dcache data sram block0 in world1. - 20 - 2 + SAR_COCPU_SWD_INT_ENA + int enable of super watch dog + 8 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 - core0/core1's permission of dcache data sram block1 in world1. - 22 - 2 + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + int enable of timeout done + 9 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS - core0/core1's permission(sotre,load) of rom in world0. - 24 - 2 + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + int enable of approach loop done + 10 + 1 read-write - CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS - core0/core1's permission(sotre,load) of rom in world1. - 26 - 2 + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + int enable of touch scan done + 11 + 1 read-write - CORE_0_DRAM0_PMS_MONITOR_0 - core0 dram0 permission monitor configuration register 0 - 0x104 + SAR_COCPU_INT_ST + the interrupt state of ulp + 0xF0 0x20 - CORE_0_DRAM0_PMS_MONITOR_LOCK - Set 1 to lock core0 dram0 permission monitor configuration register. + SAR_COCPU_TOUCH_DONE_INT_ST + int state of touch done 0 1 - read-write + read-only - - - - CORE_0_DRAM0_PMS_MONITOR_1 - core0 dram0 permission monitor configuration register 1 - 0x108 - 0x20 - 0x00000003 - - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear core0 dram0 permission monior interrupt. - 0 + SAR_COCPU_TOUCH_INACTIVE_INT_ST + int state of from touch inactive + 1 1 - read-write + read-only - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN - Set 1 to enable core0 dram0 permission monitor interrupt. - 1 + SAR_COCPU_TOUCH_ACTIVE_INT_ST + int state of touch active + 2 1 - read-write + read-only - - - - CORE_0_DRAM0_PMS_MONITOR_2 - core0 dram0 permission monitor configuration register 2. - 0x10C - 0x20 - - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR - recorded core0 dram0 permission monitor interrupt status. - 0 + SAR_COCPU_SARADC1_INT_ST + int state of from saradc1 + 3 1 read-only - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK - recorded core0 dram0 lock status, 1 means s32c1i access. - 1 + SAR_COCPU_SARADC2_INT_ST + int state of from saradc2 + 4 1 read-only - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD - recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. - 2 - 2 + SAR_COCPU_TSENS_INT_ST + int state of tsens + 5 + 1 read-only - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR - recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16 - 4 - 22 + SAR_COCPU_START_INT_ST + int state of start + 6 + 1 read-only - - - - CORE_0_DRAM0_PMS_MONITOR_3 - core0 dram0 permission monitor configuration register 3. - 0x110 - 0x20 - - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR - recorded core0 dram0 wr status, 1 means store, 0 means load. - 0 + SAR_COCPU_SW_INT_ST + int state of software + 7 1 read-only - CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN - recorded core0 dram0 byteen status. - 1 - 16 + SAR_COCPU_SWD_INT_ST + int state of super watch dog + 8 + 1 read-only - - - - CORE_1_DRAM0_PMS_MONITOR_0 - core1 dram0 permission monitor configuration register 0 - 0x114 - 0x20 - - CORE_1_DRAM0_PMS_MONITOR_LOCK - Set 1 to lock core1 dram0 permission monitor configuration register. - 0 + SAR_COCPU_TOUCH_TIMEOUT_INT_ST + int state of timeout done + 9 1 - read-write + read-only - - - - CORE_1_DRAM0_PMS_MONITOR_1 - core1 dram0 permission monitor configuration register 1 - 0x118 - 0x20 - 0x00000003 - - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear core1 dram0 permission monior interrupt. - 0 + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + int state of approach loop done + 10 1 - read-write + read-only - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN - Set 1 to enable core1 dram0 permission monitor interrupt. - 1 + SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + int state of touch scan done + 11 1 - read-write + read-only - CORE_1_DRAM0_PMS_MONITOR_2 - core1 dram0 permission monitor configuration register 2. - 0x11C + SAR_COCPU_INT_CLR + the interrupt clear of ulp + 0xF4 0x20 - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR - recorded core1 dram0 permission monitor interrupt status. + SAR_COCPU_TOUCH_DONE_INT_CLR + int clear of touch done 0 1 - read-only + write-only - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK - recorded core1 dram0 lock status, 1 means s32c1i access. + SAR_COCPU_TOUCH_INACTIVE_INT_CLR + int clear of from touch inactive 1 1 - read-only + write-only - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD - recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. + SAR_COCPU_TOUCH_ACTIVE_INT_CLR + int clear of touch active 2 - 2 - read-only + 1 + write-only - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR - recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16 + SAR_COCPU_SARADC1_INT_CLR + int clear of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_CLR + int clear of from saradc2 4 - 22 - read-only + 1 + write-only + + + SAR_COCPU_TSENS_INT_CLR + int clear of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_CLR + int clear of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_CLR + int clear of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_CLR + int clear of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + int clear of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + int clear of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + int clear of touch scan done + 11 + 1 + write-only - CORE_1_DRAM0_PMS_MONITOR_3 - core1 dram0 permission monitor configuration register 3. - 0x120 + SAR_COCPU_DEBUG + Ulp-riscv debug signal + 0xF8 0x20 - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR - recorded core1 dram0 wr status, 1 means store, 0 means load. + SAR_COCPU_PC + cocpu Program counter 0 - 1 + 13 read-only - CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN - recorded core1 dram0 byteen status. - 1 - 16 + SAR_COCPU_MEM_VLD + cocpu mem valid output + 13 + 1 read-only - - - - CORE_0_PIF_PMS_CONSTRAIN_0 - Core0 access peripherals permission configuration register 0. - 0x124 - 0x20 - - CORE_0_PIF_PMS_CONSTRAIN_LOCK - Set 1 to lock core0 access peripherals permission Configuration Register. - 0 + SAR_COCPU_MEM_RDY + cocpu mem ready input + 14 1 - read-write + read-only + + + SAR_COCPU_MEM_WEN + cocpu mem write enable output + 15 + 4 + read-only + + + SAR_COCPU_MEM_ADDR + cocpu mem address output + 19 + 13 + read-only - CORE_0_PIF_PMS_CONSTRAIN_1 - Core0 access peripherals permission configuration register 1. - 0x128 + SAR_HALL_CTRL + no public + 0xFC 0x20 - 0xFF33CFFF + 0xA0000000 - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART - Core0 access uart permission in world0. - 0 - 2 + XPD_HALL + Power on hall sensor and connect to VP and VN + 28 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 - Core0 access g0spi_1 permission in world0. - 2 - 2 + XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 29 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 - Core0 access g0spi_0 permission in world0. - 4 - 2 + HALL_PHASE + Reverse phase of hall sensor + 30 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO - Core0 access gpio permission in world0. - 6 - 2 + HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 31 + 1 read-write + + + + SAR_NOUSE + no public + 0x100 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 - Core0 access fe2 permission in world0. - 8 - 2 + SAR_NOUSE + no public + 0 + 32 read-write + + + + SAR_PERI_CLK_GATE_CONF + the peri clock gate of rtc peri + 0x104 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE - Core0 access fe permission in world0. - 10 - 2 + RTC_I2C_CLK_EN + enable rtc i2c clock + 27 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC - Core0 access rtc permission in world0. - 14 - 2 + TSENS_CLK_EN + enable tsens clock + 29 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX - Core0 access io_mux permission in world0. - 16 - 2 + SARADC_CLK_EN + enbale saradc clock + 30 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF - Core0 access hinf permission in world0. - 20 - 2 + IOMUX_CLK_EN + enable io_mux clock + 31 + 1 read-write + + + + SAR_PERI_RESET_CONF + the peri reset of rtc peri + 0x108 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC - Core0 access misc permission in world0. - 24 - 2 + SAR_COCPU_RESET + enable ulp-riscv reset + 25 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C - Core0 access i2c permission in world0. - 26 - 2 + SAR_RTC_I2C_RESET + Reserved. + 27 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 - Core0 access i2s0 permission in world0. - 28 - 2 + SAR_TSENS_RESET + enbale saradc reset + 29 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 - Core0 access uart1 permission in world0. + SAR_SARADC_RESET + enable io_mux reset 30 - 2 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_2 - Core0 access peripherals permission configuration register 2. - 0x12C + SAR_COCPU_INT_ENA_W1TS + the interrupt enable of ulp + 0x10C 0x20 - 0xFFCFFFF3 - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT - Core0 access bt permission in world0. + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS + int enable of touch done 0 - 2 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 - Core0 access i2c_ext0 permission in world0. - 4 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 - Core0 access uhci0 permission in world0. - 6 - 2 - read-write + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS + int enable of from touch inactive + 1 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST - Core0 access slchost permission in world0. - 8 - 2 - read-write + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS + int enable of touch active + 2 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT - Core0 access rmt permission in world0. - 10 - 2 - read-write + SAR_COCPU_SARADC1_INT_ENA_W1TS + int enable of from saradc1 + 3 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT - Core0 access pcnt permission in world0. - 12 - 2 - read-write + SAR_COCPU_SARADC2_INT_ENA_W1TS + int enable of from saradc2 + 4 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC - Core0 access slc permission in world0. - 14 - 2 - read-write + SAR_COCPU_TSENS_INT_ENA_W1TS + int enable of tsens + 5 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC - Core0 access ledc permission in world0. - 16 - 2 - read-write + SAR_COCPU_START_INT_ENA_W1TS + int enable of start + 6 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP - Core0 access backup permission in world0. - 18 - 2 - read-write + SAR_COCPU_SW_INT_ENA_W1TS + int enable of software + 7 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB - Core0 access bb permission in world0. - 22 - 2 - read-write + SAR_COCPU_SWD_INT_ENA_W1TS + int enable of super watch dog + 8 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 - Core0 access pwm0 permission in world0. - 24 - 2 - read-write + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS + int enable of timeout done + 9 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP - Core0 access timergroup permission in world0. - 26 - 2 - read-write + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + int enable of approach loop done + 10 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 - Core0 access timergroup1 permission in world0. - 28 - 2 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER - Core0 access systimer permission in world0. - 30 - 2 - read-write + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS + int enable of touch scan done + 11 + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_3 - Core0 access peripherals permission configuration register 3. - 0x130 + SAR_COCPU_INT_ENA_W1TC + the interrupt enable clear of ulp + 0x110 0x20 - 0x3CC3FFFF - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 - Core0 access spi_2 permission in world0. + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC + Clear int enable of touch done 0 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 - Core0 access spi_3 permission in world0. + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC + Clear int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC + Clear int enable of touch active 2 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL - Core0 access apb_ctrl permission in world0. + SAR_COCPU_SARADC1_INT_ENA_W1TC + Clear int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TC + Clear int enable of from saradc2 4 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 - Core0 access i2c_ext1 permission in world0. + SAR_COCPU_TSENS_INT_ENA_W1TC + Clear int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TC + Clear int enable of start 6 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST - Core0 access sdio_host permission in world0. + SAR_COCPU_SW_INT_ENA_W1TC + Clear int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TC + Clear int enable of super watch dog 8 - 2 - read-write + 1 + write-only - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN - Core0 access can permission in world0. + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC + Clear int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + Clear int enable of approach loop done 10 - 2 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC + Clear int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_DEBUG_CONF + rtc peri debug configure + 0x114 + 0x20 + + + SAR_DEBUG_BIT_SEL + no public + 0 + 5 read-write + + + + SAR_SARDATE + version + 0x1FC + 0x20 + 0x02101180 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 - Core0 access pwm1 permission in world0. - 12 - 2 + SAR_DATE + version + 0 + 28 read-write + + + + + + SENSITIVE + SENSITIVE Peripheral + SENSITIVE + 0x600C1000 + + 0x0 + 0x314 + registers + + + + CACHE_DATAARRAY_CONNECT_0 + Cache data array configuration register 0. + 0x0 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 - Core0 access i2s1 permission in world0. - 14 - 2 + CACHE_DATAARRAY_CONNECT_LOCK + Set 1 to lock cache data array registers. + 0 + 1 read-write + + + + CACHE_DATAARRAY_CONNECT_1 + Cache data array configuration register 1. + 0x4 + 0x20 + 0x000000FF + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 - Core0 access uart2 permission in world0. - 16 - 2 + CACHE_DATAARRAY_CONNECT_FLATTEN + Cache data array connection configuration. + 0 + 8 read-write + + + + APB_PERIPHERAL_ACCESS_0 + APB peripheral configuration register 0. + 0x8 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT - Core0 access rwbt permission in world0. - 22 - 2 + APB_PERIPHERAL_ACCESS_LOCK + Set 1 to lock APB peripheral Configuration Register. + 0 + 1 read-write + + + + APB_PERIPHERAL_ACCESS_1 + APB peripheral configuration register 1. + 0xC + 0x20 + 0x00000001 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC - Core0 access wifimac permission in world0. - 26 - 2 + APB_PERIPHERAL_ACCESS_SPLIT_BURST + Set 1 to support split function for AHB access to APB peripherals. + 0 + 1 read-write + + + + INTERNAL_SRAM_USAGE_0 + Internal SRAM configuration register 0. + 0x10 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR - Core0 access pwr permission in world0. - 28 - 2 + INTERNAL_SRAM_USAGE_LOCK + Set 1 to lock internal SRAM Configuration Register. + 0 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_4 - Core0 access peripherals permission configuration register 4. - 0x134 + INTERNAL_SRAM_USAGE_1 + Internal SRAM configuration register 1. + 0x14 0x20 - 0xFFFFFFFF + 0x000007FF - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE - Core0 access usb_device permission in world0. + INTERNAL_SRAM_ICACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP - Core0 access usb_wrap permission in world0. + INTERNAL_SRAM_DCACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI - Core0 access crypto_peri permission in world0. + INTERNAL_SRAM_CPU_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. 4 - 2 + 7 read-write + + + + INTERNAL_SRAM_USAGE_2 + Internal SRAM configuration register 2. + 0x18 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA - Core0 access crypto_dma permission in world0. - 6 - 2 + INTERNAL_SRAM_CORE0_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + 0 + 7 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC - Core0 access apb_adc permission in world0. - 8 - 2 + INTERNAL_SRAM_CORE1_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + 7 + 7 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM - Core0 access lcd_cam permission in world0. - 10 + INTERNAL_SRAM_CORE0_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. + 14 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR - Core0 access bt_pwr permission in world0. - 12 + INTERNAL_SRAM_CORE1_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + 16 2 read-write + + + + INTERNAL_SRAM_USAGE_3 + Internal SRAM configuration register 3. + 0x1C + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB - Core0 access usb permission in world0. - 14 - 2 + INTERNAL_SRAM_MAC_DUMP_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + 0 + 4 read-write + + + + INTERNAL_SRAM_USAGE_4 + Internal SRAM configuration register 4. + 0x20 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM - Core0 access system permission in world0. - 16 - 2 + INTERNAL_SRAM_LOG_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + 0 + 7 read-write + + + + RETENTION_DISABLE + Retention configuration register. + 0x24 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE - Core0 access sensitive permission in world0. - 18 - 2 + RETENTION_DISABLE + Set 1 to disable retention function and lock disable state. + 0 + 1 read-write + + + + CACHE_TAG_ACCESS_0 + Cache tag configuration register 0. + 0x28 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT - Core0 access interrupt permission in world0. - 20 - 2 + CACHE_TAG_ACCESS_LOCK + Set 1 to lock cache tag Configuration Register. + 0 + 1 read-write + + + + CACHE_TAG_ACCESS_1 + Cache tag configuration register 1. + 0x2C + 0x20 + 0x0000000F + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY - Core0 access dma_copy permission in world0. - 22 - 2 + PRO_I_TAG_RD_ACS + Set 1 to enable Icache read access tag memory. + 0 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG - Core0 access cache_config permission in world0. - 24 - 2 + PRO_I_TAG_WR_ACS + Set 1 to enable Icache wrtie access tag memory. + 1 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD - Core0 access ad permission in world0. - 26 - 2 + PRO_D_TAG_RD_ACS + Set 1 to enable Dcache read access tag memory. + 2 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO - Core0 access dio permission in world0. - 28 - 2 + PRO_D_TAG_WR_ACS + Set 1 to enable Dcache wrtie access tag memory. + 3 + 1 read-write + + + + CACHE_MMU_ACCESS_0 + Cache MMU configuration register 0. + 0x30 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER - Core0 access world_controller permission in world0. - 30 - 2 + CACHE_MMU_ACCESS_LOCK + Set 1 to lock cache MMU registers. + 0 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_5 - Core0 access peripherals permission configuration register 5. - 0x138 + CACHE_MMU_ACCESS_1 + Cache MMU configuration register 1. + 0x34 0x20 - 0xFF33CFFF + 0x00000003 - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART - Core0 access uart permission in world1. + PRO_MMU_RD_ACS + Set 1 to enable read access MMU memory. + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Set 1 to enable write access MMU memory. + 1 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + spi2 dma permission configuration register 0. + 0x38 + 0x20 + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + Set 1 to lock spi2 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + spi2 dma permission configuration register 1. + 0x3C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 + spi2's permission(store,load) in data region0 of SRAM 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 - Core0 access g0spi_1 permission in world1. + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 + spi2's permission(store,load) in data region1 of SRAM 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 - Core0 access g0spi_0 permission in world1. + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 + spi2's permission(store,load) in data region2 of SRAM 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO - Core0 access gpio permission in world1. + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 + spi2's permission(store,load) in data region3 of SRAM 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 - Core0 access fe2 permission in world1. + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi2's permission(store,load) in dcache data sram block0 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE - Core0 access fe permission in world1. + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi2's permission(store,load) in dcache data sram block1 10 2 read-write + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 + spi3 dma permission configuration register 0. + 0x40 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC - Core0 access rtc permission in world1. - 14 - 2 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK + Set 1 to lock spi3 dma permission Configuration Register. + 0 + 1 read-write + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 + spi3 dma permission configuration register 1. + 0x44 + 0x20 + 0x00000FFF + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX - Core0 access io_mux permission in world1. - 16 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 + spi3's permission(store,load) in data region0 of SRAM + 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF - Core0 access hinf permission in world1. - 20 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 + spi3's permission(store,load) in data region1 of SRAM + 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC - Core0 access misc permission in world1. - 24 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 + spi3's permission(store,load) in data region2 of SRAM + 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C - Core0 access i2c permission in world1. - 26 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 + spi3's permission(store,load) in data region3 of SRAM + 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 - Core0 access i2s0 permission in world1. - 28 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi3's permission(store,load) in dcache data sram block0 + 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 - Core0 access uart1 permission in world1. - 30 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi3's permission(store,load) in dcache data sram block1 + 10 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_6 - Core0 access peripherals permission configuration register 6. - 0x13C + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 + uhci0 dma permission configuration register 0. + 0x48 0x20 - 0xFFCFFFF3 - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT - Core0 access bt permission in world1. + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK + Set 1 to lock uhci0 dma permission Configuration Register. 0 - 2 + 1 read-write + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 + uhci0 dma permission configuration register 1. + 0x4C + 0x20 + 0x00000FFF + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 - Core0 access i2c_ext0 permission in world1. - 4 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 + uhci0's permission(store,load) in data region0 of SRAM + 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 - Core0 access uhci0 permission in world1. - 6 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 + uhci0's permission(store,load) in data region1 of SRAM + 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST - Core0 access slchost permission in world1. - 8 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 + uhci0's permission(store,load) in data region2 of SRAM + 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT - Core0 access rmt permission in world1. - 10 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 + uhci0's permission(store,load) in data region3 of SRAM + 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT - Core0 access pcnt permission in world1. - 12 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + uhci0's permission(store,load) in dcache data sram block0 + 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC - Core0 access slc permission in world1. - 14 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + uhci0's permission(store,load) in dcache data sram block1 + 10 2 read-write + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + i2s0 dma permission configuration register 0. + 0x50 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC - Core0 access ledc permission in world1. - 16 - 2 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s0 dma permission Configuration Register. + 0 + 1 read-write + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + i2s0 dma permission configuration register 1. + 0x54 + 0x20 + 0x00000FFF + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP - Core0 access backup permission in world1. - 18 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 + i2s0's permission(store,load) in data region0 of SRAM + 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB - Core0 access bb permission in world1. - 22 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 + i2s0's permission(store,load) in data region1 of SRAM + 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 - Core0 access pwm0 permission in world1. - 24 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 + i2s0's permission(store,load) in data region2 of SRAM + 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP - Core0 access timergroup permission in world1. - 26 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 + i2s0's permission(store,load) in data region3 of SRAM + 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 - Core0 access timergroup1 permission in world1. - 28 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s0's permission(store,load) in dcache data sram block0 + 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER - Core0 access systimer permission in world1. - 30 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s0's permission(store,load) in dcache data sram block1 + 10 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_7 - Core0 access peripherals permission configuration register 7. - 0x140 + DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 + i2s1 dma permission configuration register 0. + 0x58 0x20 - 0x3CC3FFFF - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 - Core0 access spi_2 permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s1 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 + i2s1 dma permission configuration register 1. + 0x5C + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 + i2s1's permission(store,load) in data region0 of SRAM 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 - Core0 access spi_3 permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 + i2s1's permission(store,load) in data region1 of SRAM 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL - Core0 access apb_ctrl permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 + i2s1's permission(store,load) in data region2 of SRAM 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 - Core0 access i2c_ext1 permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 + i2s1's permission(store,load) in data region3 of SRAM 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST - Core0 access sdio_host permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s1's permission(store,load) in dcache data sram block0 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN - Core0 access can permission in world1. + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s1's permission(store,load) in dcache data sram block1 10 2 read-write + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + mac dma permission configuration register 0. + 0x60 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 - Core0 access pwm1 permission in world1. - 12 + DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + Set 1 to lock mac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + mac dma permission configuration register 1. + 0x64 + 0x20 + 0x00000FFF + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 + mac's permission(store,load) in data region0 of SRAM + 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 - Core0 access i2s1 permission in world1. - 14 + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 + mac's permission(store,load) in data region1 of SRAM + 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 - Core0 access uart2 permission in world1. - 16 + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 + mac's permission(store,load) in data region2 of SRAM + 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT - Core0 access rwbt permission in world1. - 22 + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 + mac's permission(store,load) in data region3 of SRAM + 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC - Core0 access wifimac permission in world1. - 26 + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + mac's permission(store,load) in dcache data sram block0 + 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR - Core0 access pwr permission in world1. - 28 + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + mac's permission(store,load) in dcache data sram block1 + 10 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_8 - Core0 access peripherals permission configuration register 8. - 0x144 + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + backup dma permission configuration register 0. + 0x68 0x20 - 0xFFFFFFFF - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE - Core0 access usb_device permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + Set 1 to lock backup dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + backup dma permission configuration register 1. + 0x6C + 0x20 + 0x00000FFF + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 + backup's permission(store,load) in data region0 of SRAM 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP - Core0 access usb_wrap permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 + backup's permission(store,load) in data region1 of SRAM 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI - Core0 access crypto_peri permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 + backup's permission(store,load) in data region2 of SRAM 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA - Core0 access crypto_dma permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 + backup's permission(store,load) in data region3 of SRAM 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC - Core0 access apb_adc permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + backup's permission(store,load) in dcache data sram block0 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM - Core0 access lcd_cam permission in world1. + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + backup's permission(store,load) in dcache data sram block1 10 2 read-write + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_0 + aes dma permission configuration register 0. + 0x70 + 0x20 + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR - Core0 access bt_pwr permission in world1. - 12 - 2 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB - Core0 access usb permission in world1. - 14 - 2 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM - Core0 access system permission in world1. - 16 - 2 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE - Core0 access sensitive permission in world1. - 18 - 2 + DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + Set 1 to lock aes dma permission Configuration Register. + 0 + 1 read-write + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_1 + aes dma permission configuration register 1. + 0x74 + 0x20 + 0x00000FFF + - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT - Core0 access interrupt permission in world1. - 20 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 + aes's permission(store,load) in data region0 of SRAM + 0 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY - Core0 access dma_copy permission in world1. - 22 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 + aes's permission(store,load) in data region1 of SRAM + 2 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG - Core0 access cache_config permission in world1. - 24 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 + aes's permission(store,load) in data region2 of SRAM + 4 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD - Core0 access ad permission in world1. - 26 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 + aes's permission(store,load) in data region3 of SRAM + 6 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO - Core0 access dio permission in world1. - 28 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + aes's permission(store,load) in dcache data sram block0 + 8 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER - Core0 access world_controller permission in world1. - 30 + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + aes's permission(store,load) in dcache data sram block1 + 10 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_9 - Core0 access peripherals permission configuration register 9. - 0x148 + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + sha dma permission configuration register 0. + 0x78 0x20 - 0x003FFFFF - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 - RTCFast memory split address in world 0 for core0. + DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + Set 1 to lock sha dma permission Configuration Register. 0 - 11 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 - RTCFast memory split address in world 1 for core0. - 11 - 11 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_10 - Core0 access peripherals permission configuration register 10. - 0x14C + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + sha dma permission configuration register 1. + 0x7C 0x20 0x00000FFF - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L - RTCFast memory low region permission in world 0 for core0. + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 + sha's permission(store,load) in data region0 of SRAM 0 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H - RTCFast memory high region permission in world 0 for core0. - 3 - 3 + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 + sha's permission(store,load) in data region1 of SRAM + 2 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L - RTCFast memory low region permission in world 1 for core0. + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 + sha's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 + sha's permission(store,load) in data region3 of SRAM 6 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H - RTCFast memory high region permission in world 1 for core0. - 9 - 3 + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sha's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sha's permission(store,load) in dcache data sram block1 + 10 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_11 - Core0 access peripherals permission configuration register 11. - 0x150 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + adc_dac dma permission configuration register 0. + 0x80 0x20 - 0x003FFFFF - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 - RTCSlow_0 memory split address in world 0 for core0. + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + Set 1 to lock adc_dac dma permission Configuration Register. 0 - 11 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 - RTCSlow_0 memory split address in world 1 for core0. - 11 - 11 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_12 - Core0 access peripherals permission configuration register 12. - 0x154 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + adc_dac dma permission configuration register 1. + 0x84 0x20 0x00000FFF - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L - RTCSlow_0 memory low region permission in world 0 for core0. + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 + adc_dac's permission(store,load) in data region0 of SRAM 0 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H - RTCSlow_0 memory high region permission in world 0 for core0. - 3 - 3 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 + adc_dac's permission(store,load) in data region1 of SRAM + 2 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L - RTCSlow_0 memory low region permission in world 1 for core0. + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 + adc_dac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 + adc_dac's permission(store,load) in data region3 of SRAM 6 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H - RTCSlow_0 memory high region permission in world 1 for core0. - 9 - 3 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + adc_dac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + adc_dac's permission(store,load) in dcache data sram block1 + 10 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_13 - Core0 access peripherals permission configuration register 13. - 0x158 + DMA_APBPERI_RMT_PMS_CONSTRAIN_0 + rmt dma permission configuration register 0. + 0x88 0x20 - 0x003FFFFF - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 - RTCSlow_1 memory split address in world 0 for core0. + DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK + Set 1 to lock rmt dma permission Configuration Register. 0 - 11 - read-write - - - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 - RTCSlow_1 memory split address in world 1 for core0. - 11 - 11 + 1 read-write - CORE_0_PIF_PMS_CONSTRAIN_14 - Core0 access peripherals permission configuration register 14. - 0x15C + DMA_APBPERI_RMT_PMS_CONSTRAIN_1 + rmt dma permission configuration register 1. + 0x8C 0x20 0x00000FFF - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L - RTCSlow_1 memory low region permission in world 0 for core0. + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 + rmt's permission(store,load) in data region0 of SRAM 0 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H - RTCSlow_1 memory high region permission in world 0 for core0. - 3 - 3 + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 + rmt's permission(store,load) in data region1 of SRAM + 2 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L - RTCSlow_1 memory low region permission in world 1 for core0. + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 + rmt's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 + rmt's permission(store,load) in data region3 of SRAM 6 - 3 + 2 read-write - CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H - RTCSlow_1 memory high region permission in world 1 for core0. - 9 - 3 + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + rmt's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + rmt's permission(store,load) in dcache data sram block1 + 10 + 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_0 - Core0 region permission register 0. - 0x160 + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 + lcd_cam dma permission configuration register 0. + 0x90 0x20 - CORE_0_REGION_PMS_CONSTRAIN_LOCK - Set 1 to lock core0 region permission registers. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK + Set 1 to lock lcd_cam dma permission Configuration Register. 0 1 read-write @@ -39842,366 +40666,263 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CORE_0_REGION_PMS_CONSTRAIN_1 - Core0 region permission register 1. - 0x164 + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 + lcd_cam dma permission configuration register 1. + 0x94 0x20 - 0x003FFFFF + 0x00000FFF - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 - Region 0 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 + lcd_cam's permission(store,load) in data region0 of SRAM 0 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 - Region 1 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 + lcd_cam's permission(store,load) in data region1 of SRAM 2 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 - Region 2 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 + lcd_cam's permission(store,load) in data region2 of SRAM 4 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 - Region 3 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 + lcd_cam's permission(store,load) in data region3 of SRAM 6 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 - Region 4 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lcd_cam's permission(store,load) in dcache data sram block0 8 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 - Region 5 permission in world 0 for core0. + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lcd_cam's permission(store,load) in dcache data sram block1 10 2 read-write + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_0 + usb dma permission configuration register 0. + 0x98 + 0x20 + - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 - Region 6 permission in world 0 for core0. - 12 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 - Region 7 permission in world 0 for core0. - 14 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 - Region 8 permission in world 0 for core0. - 16 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 - Region 9 permission in world 0 for core0. - 18 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 - Region 10 permission in world 0 for core0. - 20 - 2 + DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK + Set 1 to lock usb dma permission Configuration Register. + 0 + 1 read-write - CORE_0_REGION_PMS_CONSTRAIN_2 - Core0 region permission register 2. - 0x168 + DMA_APBPERI_USB_PMS_CONSTRAIN_1 + usb dma permission configuration register 1. + 0x9C 0x20 - 0x003FFFFF + 0x00000FFF - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 - Region 0 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 + usb's permission(store,load) in data region0 of SRAM 0 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 - Region 1 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 + usb's permission(store,load) in data region1 of SRAM 2 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 - Region 2 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 + usb's permission(store,load) in data region2 of SRAM 4 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 - Region 3 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 + usb's permission(store,load) in data region3 of SRAM 6 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 - Region 4 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + usb's permission(store,load) in dcache data sram block0 8 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 - Region 5 permission in world 1 for core0. + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + usb's permission(store,load) in dcache data sram block1 10 2 read-write - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 - Region 6 permission in world 1 for core0. - 12 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 - Region 7 permission in world 1 for core0. - 14 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 - Region 8 permission in world 1 for core0. - 16 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 - Region 9 permission in world 1 for core0. - 18 - 2 - read-write - - - CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 - Region 10 permission in world 1 for core0. - 20 - 2 - read-write - - CORE_0_REGION_PMS_CONSTRAIN_3 - Core0 region permission register 3. - 0x16C + DMA_APBPERI_LC_PMS_CONSTRAIN_0 + lc dma permission configuration register 0. + 0xA0 0x20 - CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 - Region 0 start address for core0. + DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + Set 1 to lock lc dma permission Configuration Register. 0 - 30 + 1 read-write - CORE_0_REGION_PMS_CONSTRAIN_4 - Core0 region permission register 4. - 0x170 + DMA_APBPERI_LC_PMS_CONSTRAIN_1 + lc dma permission configuration register 1. + 0xA4 0x20 + 0x00000FFF - CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 - Region 0 end address and Region 1 start address for core0. + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 + lc's permission(store,load) in data region0 of SRAM 0 - 30 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_5 - Core0 region permission register 5. - 0x174 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 - Region 1 end address and Region 2 start address for core0. - 0 - 30 + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 + lc's permission(store,load) in data region1 of SRAM + 2 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_6 - Core0 region permission register 6. - 0x178 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 - Region 2 end address and Region 3 start address for core0. - 0 - 30 + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 + lc's permission(store,load) in data region2 of SRAM + 4 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_7 - Core0 region permission register 7. - 0x17C - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 - Region 3 end address and Region 4 start address for core0. - 0 - 30 + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 + lc's permission(store,load) in data region3 of SRAM + 6 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_8 - Core0 region permission register 8. - 0x180 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 - Region 4 end address and Region 5 start address for core0. - 0 - 30 + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lc's permission(store,load) in dcache data sram block0 + 8 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_9 - Core0 region permission register 9. - 0x184 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 - Region 5 end address and Region 6 start address for core0. - 0 - 30 + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lc's permission(store,load) in dcache data sram block1 + 10 + 2 read-write - CORE_0_REGION_PMS_CONSTRAIN_10 - Core0 region permission register 10. - 0x188 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 + sdio dma permission configuration register 0. + 0xA8 0x20 - CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 - Region 6 end address and Region 7 start address for core0. + DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK + Set 1 to lock sdio dma permission Configuration Register. 0 - 30 + 1 read-write - CORE_0_REGION_PMS_CONSTRAIN_11 - Core0 region permission register 11. - 0x18C + DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 + sdio dma permission configuration register 1. + 0xAC 0x20 + 0x00000FFF - CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 - Region 7 end address and Region 8 start address for core0. + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 + sdio's permission(store,load) in data region0 of SRAM 0 - 30 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_12 - Core0 region permission register 12. - 0x190 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 - Region 8 end address and Region 9 start address for core0. - 0 - 30 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 + sdio's permission(store,load) in data region1 of SRAM + 2 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_13 - Core0 region permission register 13. - 0x194 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 - Region 9 end address and Region 10 start address for core0. - 0 - 30 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 + sdio's permission(store,load) in data region2 of SRAM + 4 + 2 read-write - - - - CORE_0_REGION_PMS_CONSTRAIN_14 - Core0 region permission register 14. - 0x198 - 0x20 - - CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 - Region 10 end address for core0. - 0 - 30 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 + sdio's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sdio's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sdio's permission(store,load) in dcache data sram block1 + 10 + 2 read-write - CORE_0_PIF_PMS_MONITOR_0 - Core0 permission report register 0. - 0x19C + DMA_APBPERI_PMS_MONITOR_0 + dma permission monitor configuration register 0. + 0xB0 0x20 - CORE_0_PIF_PMS_MONITOR_LOCK - Set 1 to lock core0 permission report registers. + DMA_APBPERI_PMS_MONITOR_LOCK + Set 1 to lock dma permission monitor Configuration Register. 0 1 read-write @@ -40209,22 +40930,22 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CORE_0_PIF_PMS_MONITOR_1 - Core0 permission report register 1. - 0x1A0 + DMA_APBPERI_PMS_MONITOR_1 + dma permission monitor configuration register 1. + 0xB4 0x20 0x00000003 - CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear dma_pms_monitor_violate interrupt 0 1 read-write - CORE_0_PIF_PMS_MONITOR_VIOLATE_EN - Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt. 1 1 read-write @@ -40232,2111 +40953,1849 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CORE_0_PIF_PMS_MONITOR_2 - Core0 permission report register 2. - 0x1A4 + DMA_APBPERI_PMS_MONITOR_2 + dma permission monitor configuration register 2. + 0xB8 0x20 - CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR - Record core0 illegal access interrupt state. + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + recorded dma's interrupt status when dma access violated permission 0 1 read-only - CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 - Record hport information when core0 initiate illegal access. + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded dma's world status when dma access violated permission 1 - 1 - read-only - - - CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE - Record access type when core0 initate illegal access. - 2 - 3 - read-only - - - CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE - Record access direction when core0 initiate illegal access. - 5 - 1 + 2 read-only - CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD - Record world information when core0 initiate illegal access. - 6 - 2 + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16 + 3 + 22 read-only - CORE_0_PIF_PMS_MONITOR_3 - Core0 permission report register 3. - 0x1A8 + DMA_APBPERI_PMS_MONITOR_3 + dma permission monitor configuration register 3. + 0xBC 0x20 - CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR - Record address information when core0 initiate illegal access. + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + recorded dma's write status when dma access violated permission, 1(write), 0(read) 0 - 32 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded dma's byte enable status when dma access violated permission + 1 + 16 read-only - CORE_0_PIF_PMS_MONITOR_4 - Core0 permission report register 4. - 0x1AC + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + sram split line configuration register 0 + 0xC0 0x20 - 0x00000003 - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR - Set 1 to clear interrupt that core0 initiate unsupported access type. + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + Set 1 to lock sram split configuration register 0 1 read-write - - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN - Set 1 to enable interrupt that core0 initiate unsupported access type. - 1 - 1 - read-write - - CORE_0_PIF_PMS_MONITOR_5 - Core0 permission report register 5. - 0x1B0 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + sram split line configuration register 1 + 0xC4 0x20 - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR - Record core0 unsupported access type interrupt state. + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 0 - 1 - read-only + 2 + read-write - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE - Record access type when core0 initiate unsupported access type. - 1 - 2 - read-only - - - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD - Record world information when core0 initiate unsupported access type. - 3 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 2 - read-only - - - - - CORE_0_PIF_PMS_MONITOR_6 - Core0 permission report register 6. - 0x1B4 - 0x20 - - - CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR - Record address information when core0 initiate unsupported access type. - 0 - 32 - read-only - - - - - CORE_0_VECBASE_OVERRIDE_LOCK - core0 vecbase override configuration register 0 - 0x1B8 - 0x20 - - - CORE_0_VECBASE_OVERRIDE_LOCK - Set 1 to lock core0 vecbase configuration register - 0 - 1 - read-write - - - - - CORE_0_VECBASE_OVERRIDE_0 - core0 vecbase override configuration register 0 - 0x1BC - 0x20 - 0x00000001 - - - CORE_0_VECBASE_WORLD_MASK - Set 1 to mask world, then only world0_value will work. - 0 - 1 read-write - - - - CORE_0_VECBASE_OVERRIDE_1 - core0 vecbase override configuration register 1 - 0x1C0 - 0x20 - - CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register. - 0 - 22 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 read-write - CORE_0_VECBASE_OVERRIDE_SEL - Set 0x3 to sel vecbase_override to override vecbase register. - 22 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 2 read-write - - - - CORE_0_VECBASE_OVERRIDE_2 - core0 vecbase override configuration register 1 - 0x1C4 - 0x20 - - CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register. - 0 - 22 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 read-write - - - - CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 - core0 toomanyexception override configuration register 0. - 0x1C8 - 0x20 - - CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK - Set 1 to lock core0 toomanyexception override configuration register - 0 - 1 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 read-write - - - - CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 - core0 toomanyexception override configuration register 1. - 0x1CC - 0x20 - 0x00000001 - - CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE - Set 1 to mask toomanyexception. - 0 - 1 + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 read-write - - - - CORE_1_PIF_PMS_CONSTRAIN_0 - Core1 access peripherals permission configuration register 0. - 0x1D0 - 0x20 - - CORE_1_PIF_PMS_CONSTRAIN_LOCK - Set 1 to lock core1 pif permission configuration register. - 0 - 1 + CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 read-write - CORE_1_PIF_PMS_CONSTRAIN_1 - Core1 access peripherals permission configuration register 1. - 0x1D4 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + sram split line configuration register 1 + 0xC8 0x20 - 0xFF33CFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART - Core1 access uart permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 - Core1 access g0spi_1 permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 2 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 - Core1 access g0spi_0 permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO - Core1 access gpio permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 - Core1 access fe2 permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE - Core1 access fe permission in world0. + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC - Core1 access rtc permission in world0. - 14 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX - Core1 access io_mux permission in world0. - 16 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF - Core1 access hinf permission in world0. - 20 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC - Core1 access misc permission in world0. - 24 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C - Core1 access i2c permission in world0. - 26 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 - Core1 access i2s0 permission in world0. - 28 + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 - Core1 access uart1 permission in world0. - 30 - 2 + CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 read-write - CORE_1_PIF_PMS_CONSTRAIN_2 - Core1 access peripherals permission configuration register 2. - 0x1D8 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + sram split line configuration register 1 + 0xCC 0x20 - 0xFFCFFFF3 - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT - Core1 access bt permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 - Core1 access i2c_ext0 permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 - Core1 access uhci0 permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST - Core1 access slchost permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT - Core1 access rmt permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT - Core1 access pcnt permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 12 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC - Core1 access slc permission in world0. + CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address 14 - 2 + 8 read-write + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + sram split line configuration register 1 + 0xD0 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC - Core1 access ledc permission in world0. - 16 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP - Core1 access backup permission in world0. - 18 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB - Core1 access bb permission in world0. - 22 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 - Core1 access pwm0 permission in world0. - 24 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP - Core1 access timergroup permission in world0. - 26 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 - Core1 access timergroup1 permission in world0. - 28 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER - Core1 access systimer permission in world0. - 30 + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 2 read-write + + CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + - CORE_1_PIF_PMS_CONSTRAIN_3 - Core1 access peripherals permission configuration register 3. - 0x1DC + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + sram split line configuration register 1 + 0xD4 0x20 - 0x3CC3FFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 - Core1 access spi_2 permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 - Core1 access spi_3 permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 2 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL - Core1 access apb_ctrl permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 - Core1 access i2c_ext1 permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST - Core1 access sdio_host permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN - Core1 access can permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 - Core1 access pwm1 permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 12 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 - Core1 access i2s1 permission in world0. + CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address 14 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 - Core1 access uart2 permission in world0. - 16 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT - Core1 access rwbt permission in world0. - 22 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC - Core1 access wifimac permission in world0. - 26 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR - Core1 access pwr permission in world0. - 28 - 2 + 8 read-write - CORE_1_PIF_PMS_CONSTRAIN_4 - Core1 access peripherals permission configuration register 4. - 0x1E0 + CORE_X_IRAM0_PMS_CONSTRAIN_0 + corex iram0 permission configuration register 0 + 0xD8 0x20 - 0xFFFFFFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE - Core1 access usb_device permission in world0. + CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex iram0 permission configuration register 0 - 2 + 1 read-write + + + + CORE_X_IRAM0_PMS_CONSTRAIN_1 + corex iram0 permission configuration register 0 + 0xDC + 0x20 + 0x001FFFFF + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP - Core1 access usb_wrap permission in world0. - 2 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI - Core1 access crypto_peri permission in world0. - 4 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA - Core1 access crypto_dma permission in world0. + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 6 - 2 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC - Core1 access apb_adc permission in world0. - 8 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM - Core1 access lcd_cam permission in world0. - 10 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR - Core1 access bt_pwr permission in world0. - 12 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB - Core1 access usb permission in world0. - 14 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission of rom in world1 + 18 + 3 read-write + + + + CORE_X_IRAM0_PMS_CONSTRAIN_2 + corex iram0 permission configuration register 1 + 0xE0 + 0x20 + 0x001FFFFF + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM - Core1 access system permission in world0. - 16 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE - Core1 access sensitive permission in world0. - 18 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT - Core1 access interrupt permission in world0. - 20 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY - Core1 access dma_copy permission in world0. - 22 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG - Core1 access cache_config permission in world0. - 24 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD - Core1 access ad permission in world0. - 26 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO - Core1 access dio permission in world0. - 28 - 2 + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission of rom in world1 + 18 + 3 read-write + + + + CORE_0_IRAM0_PMS_MONITOR_0 + core0 iram0 permission monitor configuration register 0 + 0xE4 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER - Core1 access world_controller permission in world0. - 30 - 2 + CORE_0_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 iram0 permission monitor register + 0 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_5 - Core1 access peripherals permission configuration register 5. - 0x1E4 + CORE_0_IRAM0_PMS_MONITOR_1 + core0 iram0 permission monitor configuration register 1 + 0xE8 0x20 - 0xFF33CFFF + 0x00000003 - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART - Core1 access uart permission in world1. + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 iram0 permission violated interrupt 0 - 2 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 - Core1 access g0spi_1 permission in world1. - 2 - 2 + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt + 1 + 1 read-write + + + + CORE_0_IRAM0_PMS_MONITOR_2 + core0 iram0 permission monitor configuration register 2 + 0xEC + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 - Core1 access g0spi_0 permission in world1. - 4 - 2 - read-write + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 iram0 pms monitor interrupt status. + 0 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO - Core1 access gpio permission in world1. - 6 - 2 - read-write + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 - Core1 access fe2 permission in world1. - 8 - 2 - read-write + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE - Core1 access fe permission in world1. - 10 + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 2 - read-write + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC - Core1 access rtc permission in world1. - 14 - 2 - read-write + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + CORE_1_IRAM0_PMS_MONITOR_0 + core1 iram0 permission monitor configuration register 0 + 0xF0 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX - Core1 access io_mux permission in world1. - 16 - 2 + CORE_1_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 iram0 permission monitor register + 0 + 1 read-write + + + + CORE_1_IRAM0_PMS_MONITOR_1 + core1 iram0 permission monitor configuration register 1 + 0xF4 + 0x20 + 0x00000003 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF - Core1 access hinf permission in world1. - 20 - 2 + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 iram0 permission violated interrupt + 0 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC - Core1 access misc permission in world1. - 24 - 2 + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt + 1 + 1 read-write + + + + CORE_1_IRAM0_PMS_MONITOR_2 + core1 iram0 permission monitor configuration register 2 + 0xF8 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C - Core1 access i2c permission in world1. - 26 - 2 - read-write + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 iram0 pms monitor interrupt status. + 0 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 - Core1 access i2s0 permission in world1. - 28 - 2 - read-write + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 - Core1 access uart1 permission in world1. - 30 + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 2 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_0 + corex dram0 permission configuration register 0 + 0xFC + 0x20 + + + CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex dram0 permission configuration register + 0 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_6 - Core1 access peripherals permission configuration register 6. - 0x1E8 + CORE_X_DRAM0_PMS_CONSTRAIN_1 + corex dram0 permission configuration register 1 + 0x100 0x20 - 0xFFCFFFF3 + 0x0FFFFFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT - Core1 access bt permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of data region0 of SRAM in world0. 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 - Core1 access i2c_ext0 permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of data region1 of SRAM in world0. + 2 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of data region2 of SRAM in world0. 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 - Core1 access uhci0 permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of data region3 of SRAM in world0. 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST - Core1 access slchost permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world0. 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT - Core1 access rmt permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world0. 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT - Core1 access pcnt permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of data region0 of SRAM in world1. 12 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC - Core1 access slc permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of data region1 of SRAM in world1. 14 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC - Core1 access ledc permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of data region2 of SRAM in world1. 16 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP - Core1 access backup permission in world1. + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of data region3 of SRAM in world1. 18 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB - Core1 access bb permission in world1. - 22 - 2 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 - Core1 access pwm0 permission in world1. - 24 + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world1. + 20 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP - Core1 access timergroup permission in world1. - 26 + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world1. + 22 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 - Core1 access timergroup1 permission in world1. - 28 + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission(sotre,load) of rom in world0. + 24 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER - Core1 access systimer permission in world1. - 30 + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission(sotre,load) of rom in world1. + 26 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_7 - Core1 access peripherals permission configuration register 7. - 0x1EC + CORE_0_DRAM0_PMS_MONITOR_0 + core0 dram0 permission monitor configuration register 0 + 0x104 0x20 - 0x3CC3FFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 - Core1 access spi_2 permission in world1. + CORE_0_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 dram0 permission monitor configuration register. 0 - 2 + 1 read-write + + + + CORE_0_DRAM0_PMS_MONITOR_1 + core0 dram0 permission monitor configuration register 1 + 0x108 + 0x20 + 0x00000003 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 - Core1 access spi_3 permission in world1. - 2 - 2 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 dram0 permission monior interrupt. + 0 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL - Core1 access apb_ctrl permission in world1. - 4 - 2 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 dram0 permission monitor interrupt. + 1 + 1 read-write + + + + CORE_0_DRAM0_PMS_MONITOR_2 + core0 dram0 permission monitor configuration register 2. + 0x10C + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 - Core1 access i2c_ext1 permission in world1. - 6 - 2 - read-write + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 dram0 permission monitor interrupt status. + 0 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST - Core1 access sdio_host permission in world1. - 8 - 2 - read-write + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core0 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN - Core1 access can permission in world1. - 10 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 2 - read-write + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 - Core1 access pwm1 permission in world1. - 12 - 2 - read-write + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + CORE_0_DRAM0_PMS_MONITOR_3 + core0 dram0 permission monitor configuration register 3. + 0x110 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 - Core1 access i2s1 permission in world1. - 14 - 2 - read-write + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 - Core1 access uart2 permission in world1. - 16 - 2 - read-write + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core0 dram0 byteen status. + 1 + 16 + read-only + + + + CORE_1_DRAM0_PMS_MONITOR_0 + core1 dram0 permission monitor configuration register 0 + 0x114 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT - Core1 access rwbt permission in world1. - 22 - 2 + CORE_1_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 dram0 permission monitor configuration register. + 0 + 1 read-write + + + + CORE_1_DRAM0_PMS_MONITOR_1 + core1 dram0 permission monitor configuration register 1 + 0x118 + 0x20 + 0x00000003 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC - Core1 access wifimac permission in world1. - 26 - 2 + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 dram0 permission monior interrupt. + 0 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR - Core1 access pwr permission in world1. - 28 - 2 + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 dram0 permission monitor interrupt. + 1 + 1 read-write - CORE_1_PIF_PMS_CONSTRAIN_8 - Core1 access peripherals permission configuration register 8. - 0x1F0 + CORE_1_DRAM0_PMS_MONITOR_2 + core1 dram0 permission monitor configuration register 2. + 0x11C 0x20 - 0xFFFFFFFF - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE - Core1 access usb_device permission in world1. + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 dram0 permission monitor interrupt status. 0 - 2 - read-write + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP - Core1 access usb_wrap permission in world1. + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core1 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. 2 2 - read-write + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI - Core1 access crypto_peri permission in world1. + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16 4 - 2 - read-write + 22 + read-only + + + + CORE_1_DRAM0_PMS_MONITOR_3 + core1 dram0 permission monitor configuration register 3. + 0x120 + 0x20 + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA - Core1 access crypto_dma permission in world1. - 6 - 2 - read-write + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC - Core1 access apb_adc permission in world1. - 8 - 2 + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core1 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_0_PIF_PMS_CONSTRAIN_0 + Core0 access peripherals permission configuration register 0. + 0x124 + 0x20 + + + CORE_0_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 access peripherals permission Configuration Register. + 0 + 1 read-write + + + + CORE_0_PIF_PMS_CONSTRAIN_1 + Core0 access peripherals permission configuration register 1. + 0x128 + 0x20 + 0xFF33CFFF + - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM - Core1 access lcd_cam permission in world1. - 10 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core0 access uart permission in world0. + 0 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR - Core1 access bt_pwr permission in world1. - 12 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core0 access g0spi_1 permission in world0. + 2 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB - Core1 access usb permission in world1. - 14 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core0 access g0spi_0 permission in world0. + 4 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM - Core1 access system permission in world1. - 16 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core0 access gpio permission in world0. + 6 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE - Core1 access sensitive permission in world1. - 18 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core0 access fe2 permission in world0. + 8 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT - Core1 access interrupt permission in world1. - 20 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core0 access fe permission in world0. + 10 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY - Core1 access dma_copy permission in world1. - 22 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core0 access rtc permission in world0. + 14 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG - Core1 access cache_config permission in world1. - 24 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core0 access io_mux permission in world0. + 16 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD - Core1 access ad permission in world1. - 26 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core0 access hinf permission in world0. + 20 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO - Core1 access dio permission in world1. - 28 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core0 access misc permission in world0. + 24 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER - Core1 access world_controller permission in world1. - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core0 access i2c permission in world0. + 26 2 read-write - - - - CORE_1_PIF_PMS_CONSTRAIN_9 - Core1 access peripherals permission configuration register 9. - 0x1F4 - 0x20 - 0x003FFFFF - - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 - RTCFast memory split address in world 0 for core1. - 0 - 11 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core0 access i2s0 permission in world0. + 28 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 - RTCFast memory split address in world 1 for core1. - 11 - 11 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core0 access uart1 permission in world0. + 30 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_10 - core1 access peripherals permission configuration register 10. - 0x1F8 + CORE_0_PIF_PMS_CONSTRAIN_2 + Core0 access peripherals permission configuration register 2. + 0x12C 0x20 - 0x00000FFF + 0xFFCFFFF3 - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L - RTCFast memory low region permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core0 access bt permission in world0. 0 - 3 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H - RTCFast memory high region permission in world 0 for core1. - 3 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core0 access i2c_ext0 permission in world0. + 4 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L - RTCFast memory low region permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core0 access uhci0 permission in world0. 6 - 3 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H - RTCFast memory high region permission in world 1 for core1. - 9 - 3 - read-write - - - - - CORE_1_PIF_PMS_CONSTRAIN_11 - core1 access peripherals permission configuration register 11. - 0x1FC - 0x20 - 0x003FFFFF - - - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 - RTCSlow_0 memory split address in world 0 for core1. - 0 - 11 - read-write - - - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 - RTCSlow_0 memory split address in world 1 for core1. - 11 - 11 + 2 read-write - - - - CORE_1_PIF_PMS_CONSTRAIN_12 - core1 access peripherals permission configuration register 12. - 0x200 - 0x20 - 0x00000FFF - - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L - RTCSlow_0 memory low region permission in world 0 for core1. - 0 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core0 access slchost permission in world0. + 8 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H - RTCSlow_0 memory high region permission in world 0 for core1. - 3 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core0 access rmt permission in world0. + 10 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L - RTCSlow_0 memory low region permission in world 1 for core1. - 6 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core0 access pcnt permission in world0. + 12 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H - RTCSlow_0 memory high region permission in world 1 for core1. - 9 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core0 access slc permission in world0. + 14 + 2 read-write - - - - CORE_1_PIF_PMS_CONSTRAIN_13 - core1 access peripherals permission configuration register 13. - 0x204 - 0x20 - 0x003FFFFF - - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 - RTCSlow_1 memory split address in world 0 for core1. - 0 - 11 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core0 access ledc permission in world0. + 16 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 - RTCSlow_1 memory split address in world 1 for core1. - 11 - 11 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core0 access backup permission in world0. + 18 + 2 read-write - - - - CORE_1_PIF_PMS_CONSTRAIN_14 - core1 access peripherals permission configuration register 14. - 0x208 - 0x20 - 0x00000FFF - - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L - RTCSlow_1 memory low region permission in world 0 for core1. - 0 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core0 access bb permission in world0. + 22 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H - RTCSlow_1 memory high region permission in world 0 for core1. - 3 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core0 access pwm0 permission in world0. + 24 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L - RTCSlow_1 memory low region permission in world 1 for core1. - 6 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core0 access timergroup permission in world0. + 26 + 2 read-write - CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H - RTCSlow_1 memory high region permission in world 1 for core1. - 9 - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core0 access timergroup1 permission in world0. + 28 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_0 - core1 region permission register 0. - 0x20C - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_LOCK - Set 1 to lock core1 region permission registers. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core0 access systimer permission in world0. + 30 + 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_1 - core1 region permission register 1. - 0x210 + CORE_0_PIF_PMS_CONSTRAIN_3 + Core0 access peripherals permission configuration register 3. + 0x130 0x20 - 0x003FFFFF + 0x3CC3FFFF - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 - Region 0 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core0 access spi_2 permission in world0. 0 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 - Region 1 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core0 access spi_3 permission in world0. 2 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 - Region 2 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core0 access apb_ctrl permission in world0. 4 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 - Region 3 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core0 access i2c_ext1 permission in world0. 6 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 - Region 4 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core0 access sdio_host permission in world0. 8 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 - Region 5 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core0 access can permission in world0. 10 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 - Region 6 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core0 access pwm1 permission in world0. 12 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 - Region 7 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core0 access i2s1 permission in world0. 14 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 - Region 8 permission in world 0 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core0 access uart2 permission in world0. 16 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 - Region 9 permission in world 0 for core1. - 18 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core0 access rwbt permission in world0. + 22 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 - Region 10 permission in world 0 for core1. - 20 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core0 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core0 access pwr permission in world0. + 28 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_2 - core1 region permission register 2. - 0x214 + CORE_0_PIF_PMS_CONSTRAIN_4 + Core0 access peripherals permission configuration register 4. + 0x134 0x20 - 0x003FFFFF + 0xFFFFFFFF - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 - Region 0 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core0 access usb_device permission in world0. 0 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 - Region 1 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core0 access usb_wrap permission in world0. 2 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 - Region 2 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core0 access crypto_peri permission in world0. 4 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 - Region 3 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core0 access crypto_dma permission in world0. 6 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 - Region 4 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core0 access apb_adc permission in world0. 8 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 - Region 5 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core0 access lcd_cam permission in world0. 10 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 - Region 6 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core0 access bt_pwr permission in world0. 12 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 - Region 7 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core0 access usb permission in world0. 14 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 - Region 8 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core0 access system permission in world0. 16 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 - Region 9 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core0 access sensitive permission in world0. 18 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 - Region 10 permission in world 1 for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core0 access interrupt permission in world0. 20 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_3 - core1 region permission register 3. - 0x218 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 - Region 0 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core0 access dma_copy permission in world0. + 22 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_4 - core1 region permission register 4. - 0x21C - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 - Region 0 end address and Region 1 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core0 access cache_config permission in world0. + 24 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_5 - core1 region permission register 5. - 0x220 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 - Region 1 end address and Region 2 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core0 access ad permission in world0. + 26 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_6 - core1 region permission register 6. - 0x224 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 - Region 2 end address and Region 3 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core0 access dio permission in world0. + 28 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_7 - core1 region permission register 7. - 0x228 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 - Region 3 end address and Region 4 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core0 access world_controller permission in world0. + 30 + 2 read-write - CORE_1_REGION_PMS_CONSTRAIN_8 - core1 region permission register 8. - 0x22C + CORE_0_PIF_PMS_CONSTRAIN_5 + Core0 access peripherals permission configuration register 5. + 0x138 0x20 + 0xFF33CFFF - CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 - Region 4 end address and Region 5 start address for core1. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core0 access uart permission in world1. 0 - 30 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_9 - core1 region permission register 9. - 0x230 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 - Region 5 end address and Region 6 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core0 access g0spi_1 permission in world1. + 2 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_10 - core1 region permission register 10. - 0x234 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 - Region 6 end address and Region 7 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core0 access g0spi_0 permission in world1. + 4 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_11 - core1 region permission register 11. - 0x238 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 - Region 7 end address and Region 8 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core0 access gpio permission in world1. + 6 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_12 - core1 region permission register 12. - 0x23C - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 - Region 8 end address and Region 9 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core0 access fe2 permission in world1. + 8 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_13 - core1 region permission register 13. - 0x240 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 - Region 9 end address and Region 10 start address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core0 access fe permission in world1. + 10 + 2 read-write - - - - CORE_1_REGION_PMS_CONSTRAIN_14 - core1 region permission register 14. - 0x244 - 0x20 - - CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 - Region 10 end address for core1. - 0 - 30 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core0 access rtc permission in world1. + 14 + 2 read-write - - - - CORE_1_PIF_PMS_MONITOR_0 - core1 permission report register 0. - 0x248 - 0x20 - - CORE_1_PIF_PMS_MONITOR_LOCK - Set 1 to lock core1 permission report registers. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core0 access io_mux permission in world1. + 16 + 2 read-write - - - - CORE_1_PIF_PMS_MONITOR_1 - core1 permission report register 1. - 0x24C - 0x20 - 0x00000003 - - CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear interrupt that core1 initiate illegal PIF bus access. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core0 access hinf permission in world1. + 20 + 2 read-write - CORE_1_PIF_PMS_MONITOR_VIOLATE_EN - Set 1 to enable interrupt that core1 initiate illegal PIF bus access. - 1 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core0 access misc permission in world1. + 24 + 2 read-write - - - - CORE_1_PIF_PMS_MONITOR_2 - core1 permission report register 2. - 0x250 - 0x20 - - - CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR - Record core1 illegal access interrupt state. - 0 - 1 - read-only - - - CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 - Record hport information when core1 initiate illegal access. - 1 - 1 - read-only - - - CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE - Record access type when core1 initate illegal access. - 2 - 3 - read-only - - CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE - Record access direction when core1 initiate illegal access. - 5 - 1 - read-only + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core0 access i2c permission in world1. + 26 + 2 + read-write - CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD - Record world information when core1 initiate illegal access. - 6 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core0 access i2s0 permission in world1. + 28 2 - read-only + read-write - - - - CORE_1_PIF_PMS_MONITOR_3 - core1 permission report register 3. - 0x254 - 0x20 - - CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR - Record address information when core1 initiate illegal access. - 0 - 32 - read-only + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core0 access uart1 permission in world1. + 30 + 2 + read-write - CORE_1_PIF_PMS_MONITOR_4 - core1 permission report register 4. - 0x258 + CORE_0_PIF_PMS_CONSTRAIN_6 + Core0 access peripherals permission configuration register 6. + 0x13C 0x20 - 0x00000003 + 0xFFCFFFF3 - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR - Set 1 to clear interrupt that core1 initiate unsupported access type. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core0 access bt permission in world1. 0 - 1 + 2 read-write - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN - Set 1 to enable interrupt that core1 initiate unsupported access type. - 1 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core0 access i2c_ext0 permission in world1. + 4 + 2 read-write - - - - CORE_1_PIF_PMS_MONITOR_5 - core1 permission report register 5. - 0x25C - 0x20 - - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR - Record core1 unsupported access type interrupt state. - 0 - 1 - read-only + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core0 access uhci0 permission in world1. + 6 + 2 + read-write - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE - Record access type when core1 initiate unsupported access type. - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core0 access slchost permission in world1. + 8 2 - read-only + read-write - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD - Record world information when core1 initiate unsupported access type. - 3 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core0 access rmt permission in world1. + 10 2 - read-only + read-write - - - - CORE_1_PIF_PMS_MONITOR_6 - core1 permission report register 6. - 0x260 - 0x20 - - CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR - Record address information when core1 initiate unsupported access type. - 0 - 32 - read-only + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core0 access pcnt permission in world1. + 12 + 2 + read-write - - - - CORE_1_VECBASE_OVERRIDE_LOCK - core1 vecbase override configuration register 0 - 0x264 - 0x20 - - CORE_1_VECBASE_OVERRIDE_LOCK - Set 1 to lock core1 vecbase configuration register - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core0 access slc permission in world1. + 14 + 2 read-write - - - - CORE_1_VECBASE_OVERRIDE_0 - core1 vecbase override configuration register 0 - 0x268 - 0x20 - 0x00000001 - - CORE_1_VECBASE_WORLD_MASK - Set 1 to mask world, then only world0_value will work. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core0 access ledc permission in world1. + 16 + 2 read-write - - - - CORE_1_VECBASE_OVERRIDE_1 - core1 vecbase override configuration register 1 - 0x26C - 0x20 - - CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE - world0 vecbase_override register, when core1 in world0 use this register to override vecbase register. - 0 - 22 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core0 access backup permission in world1. + 18 + 2 read-write - CORE_1_VECBASE_OVERRIDE_SEL - Set 0x3 to sel vecbase_override to override vecbase register. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core0 access bb permission in world1. 22 2 read-write - - - - CORE_1_VECBASE_OVERRIDE_2 - core1 vecbase override configuration register 1 - 0x270 - 0x20 - - CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE - world1 vecbase_override register, when core1 in world1 use this register to override vecbase register. - 0 - 22 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core0 access pwm0 permission in world1. + 24 + 2 read-write - - - - CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 - core1 toomanyexception override configuration register 0. - 0x274 - 0x20 - - CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK - Set 1 to lock core1 toomanyexception override configuration register - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core0 access timergroup permission in world1. + 26 + 2 read-write - - - - CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 - core1 toomanyexception override configuration register 1. - 0x278 - 0x20 - 0x00000001 - - CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE - Set 1 to mask toomanyexception. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core0 access timergroup1 permission in world1. + 28 + 2 read-write - - - - BACKUP_BUS_PMS_CONSTRAIN_0 - BackUp access peripherals permission configuration register 0. - 0x27C - 0x20 - - BACKUP_BUS_PMS_CONSTRAIN_LOCK - Set 1 to lock BackUp permission configuration registers. - 0 - 1 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core0 access systimer permission in world1. + 30 + 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_1 - BackUp access peripherals permission configuration register 1. - 0x280 + CORE_0_PIF_PMS_CONSTRAIN_7 + Core0 access peripherals permission configuration register 7. + 0x140 0x20 - 0xFF33CFFF + 0x3CC3FFFF - BACKUP_BUS_PMS_CONSTRAIN_UART - BackUp access uart permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core0 access spi_2 permission in world1. 0 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 - BackUp access g0spi_1 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core0 access spi_3 permission in world1. 2 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 - BackUp access g0spi_0 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core0 access apb_ctrl permission in world1. 4 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_GPIO - BackUp access gpio permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core0 access i2c_ext1 permission in world1. 6 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_FE2 - BackUp access fe2 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core0 access sdio_host permission in world1. 8 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_FE - BackUp access fe permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core0 access can permission in world1. 10 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_RTC - BackUp access rtc permission. - 14 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core0 access pwm1 permission in world1. + 12 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_IO_MUX - BackUp access io_mux permission. - 16 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core0 access i2s1 permission in world1. + 14 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_HINF - BackUp access hinf permission. - 20 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core0 access uart2 permission in world1. + 16 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_MISC - BackUp access misc permission. - 24 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core0 access rwbt permission in world1. + 22 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_I2C - BackUp access i2c permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core0 access wifimac permission in world1. 26 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_I2S0 - BackUp access i2s0 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core0 access pwr permission in world1. 28 2 read-write - - BACKUP_BUS_PMS_CONSTRAIN_UART1 - BackUp access uart1 permission. - 30 - 2 - read-write - - BACKUP_BUS_PMS_CONSTRAIN_2 - BackUp access peripherals permission configuration register 2. - 0x284 + CORE_0_PIF_PMS_CONSTRAIN_8 + Core0 access peripherals permission configuration register 8. + 0x144 0x20 - 0xFFCFFFF3 + 0xFFFFFFFF - BACKUP_BUS_PMS_CONSTRAIN_BT - BackUp access bt permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core0 access usb_device permission in world1. 0 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 - BackUp access i2c_ext0 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core0 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core0 access crypto_peri permission in world1. 4 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_UHCI0 - BackUp access uhci0 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core0 access crypto_dma permission in world1. 6 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_SLCHOST - BackUp access slchost permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core0 access apb_adc permission in world1. 8 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_RMT - BackUp access rmt permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core0 access lcd_cam permission in world1. 10 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_PCNT - BackUp access pcnt permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core0 access bt_pwr permission in world1. 12 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_SLC - BackUp access slc permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core0 access usb permission in world1. 14 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_LEDC - BackUp access ledc permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core0 access system permission in world1. 16 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_BACKUP - BackUp access backup permission. - 18 + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core0 access sensitive permission in world1. + 18 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_BB - BackUp access bb permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core0 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core0 access dma_copy permission in world1. 22 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_PWM0 - BackUp access pwm0 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core0 access cache_config permission in world1. 24 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP - BackUp access timergroup permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core0 access ad permission in world1. 26 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 - BackUp access timergroup1 permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core0 access dio permission in world1. 28 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER - BackUp access systimer permission. + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core0 access world_controller permission in world1. 30 2 read-write @@ -42344,532 +42803,561 @@ Any pulses with width less than this will be ignored when the filter is enabled. - BACKUP_BUS_PMS_CONSTRAIN_3 - BackUp access peripherals permission configuration register 3. - 0x288 + CORE_0_PIF_PMS_CONSTRAIN_9 + Core0 access peripherals permission configuration register 9. + 0x148 0x20 - 0x3CC3FFFF + 0x003FFFFF - BACKUP_BUS_PMS_CONSTRAIN_SPI_2 - BackUp access spi_2 permission. + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core0. 0 - 2 + 11 read-write - BACKUP_BUS_PMS_CONSTRAIN_SPI_3 - BackUp access spi_3 permission. - 2 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core0. + 11 + 11 read-write + + + + CORE_0_PIF_PMS_CONSTRAIN_10 + Core0 access peripherals permission configuration register 10. + 0x14C + 0x20 + 0x00000FFF + - BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL - BackUp access apb_ctrl permission. - 4 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core0. + 0 + 3 read-write - BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 - BackUp access i2c_ext1 permission. + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core0. 6 - 2 + 3 read-write - BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST - BackUp access sdio_host permission. - 8 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core0. + 9 + 3 read-write + + + + CORE_0_PIF_PMS_CONSTRAIN_11 + Core0 access peripherals permission configuration register 11. + 0x150 + 0x20 + 0x003FFFFF + - BACKUP_BUS_PMS_CONSTRAIN_CAN - BackUp access can permission. - 10 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core0. + 0 + 11 read-write - BACKUP_BUS_PMS_CONSTRAIN_PWM1 - BackUp access pwm1 permission. - 12 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core0. + 11 + 11 read-write + + + + CORE_0_PIF_PMS_CONSTRAIN_12 + Core0 access peripherals permission configuration register 12. + 0x154 + 0x20 + 0x00000FFF + - BACKUP_BUS_PMS_CONSTRAIN_I2S1 - BackUp access i2s1 permission. - 14 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core0. + 0 + 3 read-write - BACKUP_BUS_PMS_CONSTRAIN_UART2 - BackUp access uart2 permission. - 16 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core0. + 3 + 3 read-write - BACKUP_BUS_PMS_CONSTRAIN_RWBT - BackUp access rwbt permission. - 22 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core0. + 6 + 3 read-write - BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC - BackUp access wifimac permission. - 26 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_13 + Core0 access peripherals permission configuration register 13. + 0x158 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core0. + 0 + 11 read-write - BACKUP_BUS_PMS_CONSTRAIN_PWR - BackUp access pwr permission. - 28 - 2 + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core0. + 11 + 11 read-write - BACKUP_BUS_PMS_CONSTRAIN_4 - BackUp access peripherals permission configuration register 4. - 0x28C + CORE_0_PIF_PMS_CONSTRAIN_14 + Core0 access peripherals permission configuration register 14. + 0x15C 0x20 - 0xFFFFFFFF + 0x00000FFF - BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE - BackUp access usb_device permission. + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_0 + Core0 region permission register 0. + 0x160 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 region permission registers. + 0 + 1 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_1 + Core0 region permission register 1. + 0x164 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core0. 0 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP - BackUp access usb_wrap permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core0. 2 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI - BackUp access crypto_peri permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core0. 4 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA - BackUp access crypto_dma permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core0. 6 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_APB_ADC - BackUp access apb_adc permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core0. 8 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM - BackUp access lcd_cam permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core0. 10 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_BT_PWR - BackUp access bt_pwr permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core0. 12 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_USB - BackUp access usb permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core0. 14 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_SYSTEM - BackUp access system permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core0. 16 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE - BackUp access sensitive permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core0. 18 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT - BackUp access interrupt permission. + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core0. 20 2 read-write + + + + CORE_0_REGION_PMS_CONSTRAIN_2 + Core0 region permission register 2. + 0x168 + 0x20 + 0x003FFFFF + - BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY - BackUp access dma_copy permission. - 22 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core0. + 0 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG - BackUp access cache_config permission. - 24 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core0. + 2 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_AD - BackUp access ad permission. - 26 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core0. + 4 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_DIO - BackUp access dio permission. - 28 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core0. + 6 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER - BackUp access world_controller permission. - 30 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core0. + 8 2 read-write - - - - BACKUP_BUS_PMS_CONSTRAIN_5 - BackUp access peripherals permission configuration register 5. - 0x290 - 0x20 - 0x000007FF - - BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR - BackUp access rtcfast_spltaddr permission. - 0 - 11 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core0. + 10 + 2 read-write - - - - BACKUP_BUS_PMS_CONSTRAIN_6 - BackUp access peripherals permission configuration register 6. - 0x294 - 0x20 - 0x0000003F - - BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L - BackUp access rtcfast_l permission. - 0 - 3 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core0. + 12 + 2 read-write - BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H - BackUp access rtcfast_h permission. - 3 - 3 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core0. + 14 + 2 read-write - - - - BACKUP_BUS_PMS_MONITOR_0 - BackUp permission report register 0. - 0x298 - 0x20 - - BACKUP_BUS_PMS_MONITOR_LOCK - Set 1 to lock BackUp permission report registers. - 0 - 1 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core0. + 16 + 2 read-write - - - - BACKUP_BUS_PMS_MONITOR_1 - BackUp permission report register 1. - 0x29C - 0x20 - 0x00000003 - - BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR - Set 1 to clear interrupt that BackUp initiate illegal access. - 0 - 1 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core0. + 18 + 2 read-write - BACKUP_BUS_PMS_MONITOR_VIOLATE_EN - Set 1 to enable interrupt that BackUp initiate illegal access. - 1 - 1 + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core0. + 20 + 2 read-write - BACKUP_BUS_PMS_MONITOR_2 - BackUp permission report register 2. - 0x2A0 + CORE_0_REGION_PMS_CONSTRAIN_3 + Core0 region permission register 3. + 0x16C 0x20 - BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR - Record BackUp illegal access interrupt state. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core0. 0 - 1 - read-only - - - BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS - Record htrans when BackUp initate illegal access. - 1 - 2 - read-only - - - BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE - Record access type when BackUp initate illegal access. - 3 - 3 - read-only - - - BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE - Record access direction when BackUp initiate illegal access. - 6 - 1 - read-only + 30 + read-write - BACKUP_BUS_PMS_MONITOR_3 - BackUp permission report register 3. - 0x2A4 + CORE_0_REGION_PMS_CONSTRAIN_4 + Core0 region permission register 4. + 0x170 0x20 - BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR - Record address information when BackUp initiate illegal access. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core0. 0 - 32 - read-only + 30 + read-write - EDMA_BOUNDARY_LOCK - EDMA boundary lock register. - 0x2A8 + CORE_0_REGION_PMS_CONSTRAIN_5 + Core0 region permission register 5. + 0x174 0x20 - EDMA_BOUNDARY_LOCK - Set 1 to lock EDMA boundary registers. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core0. 0 - 1 + 30 read-write - EDMA_BOUNDARY_0 - EDMA boundary 0 configuration - 0x2AC + CORE_0_REGION_PMS_CONSTRAIN_6 + Core0 region permission register 6. + 0x178 0x20 - EDMA_BOUNDARY_0 - This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core0. 0 - 14 + 30 read-write - EDMA_BOUNDARY_1 - EDMA boundary 1 configuration - 0x2B0 + CORE_0_REGION_PMS_CONSTRAIN_7 + Core0 region permission register 7. + 0x17C 0x20 - 0x00002000 - EDMA_BOUNDARY_1 - This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core0. 0 - 14 + 30 read-write - EDMA_BOUNDARY_2 - EDMA boundary 2 configuration - 0x2B4 + CORE_0_REGION_PMS_CONSTRAIN_8 + Core0 region permission register 8. + 0x180 0x20 - 0x00002000 - EDMA_BOUNDARY_2 - This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core0. 0 - 14 + 30 read-write - EDMA_PMS_SPI2_LOCK - EDMA-SPI2 permission lock register. - 0x2B8 + CORE_0_REGION_PMS_CONSTRAIN_9 + Core0 region permission register 9. + 0x184 0x20 - EDMA_PMS_SPI2_LOCK - Set 1 to lock EDMA-SPI2 permission control registers. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core0. 0 - 1 + 30 read-write - EDMA_PMS_SPI2 - EDMA-SPI2 permission control register. - 0x2BC + CORE_0_REGION_PMS_CONSTRAIN_10 + Core0 region permission register 10. + 0x188 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core0. 0 - 2 - read-write - - - ATTR2 - This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + 30 read-write - EDMA_PMS_SPI3_LOCK - EDMA-SPI3 permission lock register. - 0x2C0 + CORE_0_REGION_PMS_CONSTRAIN_11 + Core0 region permission register 11. + 0x18C 0x20 - EDMA_PMS_SPI3_LOCK - Set 1 to lock EDMA-SPI3 permission control registers. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core0. 0 - 1 + 30 read-write - EDMA_PMS_SPI3 - EDMA-SPI3 permission control register. - 0x2C4 + CORE_0_REGION_PMS_CONSTRAIN_12 + Core0 region permission register 12. + 0x190 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core0. 0 - 2 - read-write - - - ATTR2 - This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + 30 read-write - EDMA_PMS_UHCI0_LOCK - EDMA-UHCI0 permission lock register. - 0x2C8 + CORE_0_REGION_PMS_CONSTRAIN_13 + Core0 region permission register 13. + 0x194 0x20 - EDMA_PMS_UHCI0_LOCK - Set 1 to lock EDMA-UHCI0 permission control registers. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core0. 0 - 1 + 30 read-write - EDMA_PMS_UHCI0 - EDMA-UHCI0 permission control register. - 0x2CC + CORE_0_REGION_PMS_CONSTRAIN_14 + Core0 region permission register 14. + 0x198 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core0. 0 - 2 - read-write - - - ATTR2 - This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + 30 read-write - EDMA_PMS_I2S0_LOCK - EDMA-I2S0 permission lock register. - 0x2D0 + CORE_0_PIF_PMS_MONITOR_0 + Core0 permission report register 0. + 0x19C 0x20 - EDMA_PMS_I2S0_LOCK - Set 1 to lock EDMA-I2S0 permission control registers. + CORE_0_PIF_PMS_MONITOR_LOCK + Set 1 to lock core0 permission report registers. 0 1 read-write @@ -42877,189 +43365,178 @@ Any pulses with width less than this will be ignored when the filter is enabled. - EDMA_PMS_I2S0 - EDMA-I2S0 permission control register. - 0x2D4 + CORE_0_PIF_PMS_MONITOR_1 + Core0 permission report register 1. + 0x1A0 0x20 - 0x0000000F + 0x00000003 - ATTR1 - This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate illegal PIF bus access. 0 - 2 + 1 read-write - ATTR2 - This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + 1 + 1 read-write - EDMA_PMS_I2S1_LOCK - EDMA-I2S1 permission lock register. - 0x2D8 + CORE_0_PIF_PMS_MONITOR_2 + Core0 permission report register 2. + 0x1A4 0x20 - EDMA_PMS_I2S1_LOCK - Set 1 to lock EDMA-I2S1 permission control registers. + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + Record core0 illegal access interrupt state. 0 1 - read-write + read-only - - - - EDMA_PMS_I2S1 - EDMA-I2S1 permission control register. - 0x2DC - 0x20 - 0x0000000F - - ATTR1 - This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 0 - 2 - read-write + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core0 initiate illegal access. + 1 + 1 + read-only - ATTR2 - This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core0 initate illegal access. 2 + 3 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core0 initiate illegal access. + 5 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate illegal access. + 6 2 - read-write + read-only - EDMA_PMS_LCD_CAM_LOCK - EDMA-LCD/CAM permission lock register. - 0x2E0 + CORE_0_PIF_PMS_MONITOR_3 + Core0 permission report register 3. + 0x1A8 0x20 - EDMA_PMS_LCD_CAM_LOCK - Set 1 to lock EDMA-LCD/CAM permission control registers. + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core0 initiate illegal access. 0 - 1 - read-write + 32 + read-only - EDMA_PMS_LCD_CAM - EDMA-LCD/CAM permission control register. - 0x2E4 + CORE_0_PIF_PMS_MONITOR_4 + Core0 permission report register 4. + 0x1AC 0x20 - 0x0000000F + 0x00000003 - ATTR1 - This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate unsupported access type. 0 - 2 + 1 read-write - ATTR2 - This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate unsupported access type. + 1 + 1 read-write - EDMA_PMS_AES_LOCK - EDMA-AES permission lock register. - 0x2E8 + CORE_0_PIF_PMS_MONITOR_5 + Core0 permission report register 5. + 0x1B0 0x20 - EDMA_PMS_AES_LOCK - Set 1 to lock EDMA-AES permission control registers. + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core0 unsupported access type interrupt state. 0 1 - read-write + read-only - - - - EDMA_PMS_AES - EDMA-AES permission control register. - 0x2EC - 0x20 - 0x0000000F - - ATTR1 - This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 0 + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core0 initiate unsupported access type. + 1 2 - read-write + read-only - ATTR2 - This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate unsupported access type. + 3 2 - read-write + read-only - EDMA_PMS_SHA_LOCK - EDMA-SHA permission lock register. - 0x2F0 + CORE_0_PIF_PMS_MONITOR_6 + Core0 permission report register 6. + 0x1B4 0x20 - EDMA_PMS_SHA_LOCK - Set 1 to lock EDMA-SHA permission control registers. + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core0 initiate unsupported access type. 0 - 1 - read-write + 32 + read-only - EDMA_PMS_SHA - EDMA-SHA permission control register. - 0x2F4 + CORE_0_VECBASE_OVERRIDE_LOCK + core0 vecbase override configuration register 0 + 0x1B8 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_VECBASE_OVERRIDE_LOCK + Set 1 to lock core0 vecbase configuration register 0 - 2 - read-write - - - ATTR2 - This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + 1 read-write - EDMA_PMS_ADC_DAC_LOCK - EDMA-ADC/DAC permission lock register. - 0x2F8 + CORE_0_VECBASE_OVERRIDE_0 + core0 vecbase override configuration register 0 + 0x1BC 0x20 + 0x00000001 - EDMA_PMS_ADC_DAC_LOCK - Set 1 to lock EDMA-ADC/DAC permission control registers. + CORE_0_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. 0 1 read-write @@ -43067,76 +43544,67 @@ Any pulses with width less than this will be ignored when the filter is enabled. - EDMA_PMS_ADC_DAC - EDMA-ADC/DAC permission control register. - 0x2FC + CORE_0_VECBASE_OVERRIDE_1 + core0 vecbase override configuration register 1 + 0x1C0 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core0 in world0 use this register to override vecbase register. 0 - 2 + 22 read-write - ATTR2 - This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 + CORE_0_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 2 read-write - EDMA_PMS_RMT_LOCK - EDMA-RMT permission lock register. - 0x300 + CORE_0_VECBASE_OVERRIDE_2 + core0 vecbase override configuration register 1 + 0x1C4 0x20 - EDMA_PMS_RMT_LOCK - Set 1 to lock EDMA-RMT permission control registers. + CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core0 in world1 use this register to override vecbase register. 0 - 1 + 22 read-write - EDMA_PMS_RMT - EDMA-RMT permission control register. - 0x304 + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core0 toomanyexception override configuration register 0. + 0x1C8 0x20 - 0x0000000F - ATTR1 - This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core0 toomanyexception override configuration register 0 - 2 - read-write - - - ATTR2 - This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. - 2 - 2 + 1 read-write - CLOCK_GATE_REG - Sensitive module clock gate configuration register. - 0x308 + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core0 toomanyexception override configuration register 1. + 0x1CC 0x20 0x00000001 - REG_CLK_EN - Set 1 to enable clock gate function. + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. 0 1 read-write @@ -43144,14 +43612,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. - RTC_PMS - RTC coprocessor permission register. - 0x30C + CORE_1_PIF_PMS_CONSTRAIN_0 + Core1 access peripherals permission configuration register 0. + 0x1D0 0x20 - DIS_RTC_CPU - Set 1 to disable rtc coprocessor. + CORE_1_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 pif permission configuration register. 0 1 read-write @@ -43159,2746 +43627,13638 @@ Any pulses with width less than this will be ignored when the filter is enabled. - DATE - Sensitive version register. - 0xFFC + CORE_1_PIF_PMS_CONSTRAIN_1 + Core1 access peripherals permission configuration register 1. + 0x1D4 0x20 - 0x02101280 + 0xFF33CFFF - DATE - Sensitive Date register. + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core1 access uart permission in world0. 0 - 28 + 2 read-write - - - - - - SHA - SHA (Secure Hash Algorithm) Accelerator - SHA - 0x6003B000 - - 0x0 - 0xB0 - registers - - - SHA - 78 - - - - MODE - Initial configuration register. - 0x0 - 0x20 - - MODE - sha mode - 0 - 3 + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core1 access g0spi_1 permission in world0. + 2 + 2 read-write - - - - T_STRING - SHA 512/t configuration register 0. - 0x4 - 0x20 - - T_STRING - sha t_string(used if and only if mode == sha_256/t) - 0 - 32 + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core1 access g0spi_0 permission in world0. + 4 + 2 read-write - - - - T_LENGTH - SHA 512/t configuration register 1. - 0x8 - 0x20 - - T_LENGTH - sha t_length(used if and only if mode == sha_256/t) - 0 - 6 + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core1 access gpio permission in world0. + 6 + 2 read-write - - - - DMA_BLOCK_NUM - DMA configuration register 0. - 0xC - 0x20 - - DMA_BLOCK_NUM - dma-sha block number - 0 - 6 + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core1 access fe2 permission in world0. + 8 + 2 read-write - - - - START - Typical SHA configuration register 0. - 0x10 - 0x20 - - START - reserved. - 1 - 31 - read-only + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core1 access fe permission in world0. + 10 + 2 + read-write - - - - CONTINUE - Typical SHA configuration register 1. - 0x14 - 0x20 - - CONTINUE - reserved. - 1 - 31 - read-only + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core1 access rtc permission in world0. + 14 + 2 + read-write - - - - BUSY - Busy register. - 0x18 - 0x20 - - STATE - sha busy state. 1'b0: idle 1'b1: busy - 0 - 1 - read-only + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core1 access io_mux permission in world0. + 16 + 2 + read-write - - - - DMA_START + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core1 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core1 access misc permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core1 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core1 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core1 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_2 + Core1 access peripherals permission configuration register 2. + 0x1D8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core1 access bt permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core1 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core1 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core1 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core1 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core1 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core1 access slc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core1 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core1 access backup permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core1 access bb permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core1 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core1 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core1 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core1 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_3 + Core1 access peripherals permission configuration register 3. + 0x1DC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core1 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core1 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core1 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core1 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core1 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core1 access can permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core1 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core1 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core1 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core1 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core1 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core1 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_4 + Core1 access peripherals permission configuration register 4. + 0x1E0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core1 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core1 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core1 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core1 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core1 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core1 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core1 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core1 access usb permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core1 access system permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core1 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core1 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core1 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core1 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core1 access ad permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core1 access dio permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core1 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_5 + Core1 access peripherals permission configuration register 5. + 0x1E4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core1 access uart permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core1 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core1 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core1 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core1 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core1 access fe permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core1 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core1 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core1 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core1 access misc permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core1 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core1 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core1 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_6 + Core1 access peripherals permission configuration register 6. + 0x1E8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core1 access bt permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core1 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core1 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core1 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core1 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core1 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core1 access slc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core1 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core1 access backup permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core1 access bb permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core1 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core1 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core1 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core1 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_7 + Core1 access peripherals permission configuration register 7. + 0x1EC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core1 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core1 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core1 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core1 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core1 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core1 access can permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core1 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core1 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core1 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core1 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core1 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core1 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_8 + Core1 access peripherals permission configuration register 8. + 0x1F0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core1 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core1 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core1 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core1 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core1 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core1 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core1 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core1 access usb permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core1 access system permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core1 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core1 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core1 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core1 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core1 access ad permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core1 access dio permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core1 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_9 + Core1 access peripherals permission configuration register 9. + 0x1F4 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_10 + core1 access peripherals permission configuration register 10. + 0x1F8 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_11 + core1 access peripherals permission configuration register 11. + 0x1FC + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_12 + core1 access peripherals permission configuration register 12. + 0x200 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_13 + core1 access peripherals permission configuration register 13. + 0x204 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_14 + core1 access peripherals permission configuration register 14. + 0x208 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_0 + core1 region permission register 0. + 0x20C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 region permission registers. + 0 + 1 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_1 + core1 region permission register 1. + 0x210 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_2 + core1 region permission register 2. + 0x214 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_3 + core1 region permission register 3. + 0x218 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_4 + core1 region permission register 4. + 0x21C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_5 + core1 region permission register 5. + 0x220 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_6 + core1 region permission register 6. + 0x224 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_7 + core1 region permission register 7. + 0x228 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_8 + core1 region permission register 8. + 0x22C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_9 + core1 region permission register 9. + 0x230 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_10 + core1 region permission register 10. + 0x234 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_11 + core1 region permission register 11. + 0x238 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_12 + core1 region permission register 12. + 0x23C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_13 + core1 region permission register 13. + 0x240 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_14 + core1 region permission register 14. + 0x244 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core1. + 0 + 30 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_0 + core1 permission report register 0. + 0x248 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_LOCK + Set 1 to lock core1 permission report registers. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_1 + core1 permission report register 1. + 0x24C + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_2 + core1 permission report register 2. + 0x250 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR + Record core1 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core1 initiate illegal access. + 1 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core1 initate illegal access. + 2 + 3 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core1 initiate illegal access. + 5 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_3 + core1 permission report register 3. + 0x254 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core1 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_4 + core1 permission report register 4. + 0x258 + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_5 + core1 permission report register 5. + 0x25C + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core1 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core1 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_6 + core1 permission report register 6. + 0x260 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core1 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_1_VECBASE_OVERRIDE_LOCK + core1 vecbase override configuration register 0 + 0x264 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_LOCK + Set 1 to lock core1 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_0 + core1 vecbase override configuration register 0 + 0x268 + 0x20 + 0x00000001 + + + CORE_1_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_1 + core1 vecbase override configuration register 1 + 0x26C + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core1 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_1_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_2 + core1 vecbase override configuration register 1 + 0x270 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core1 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core1 toomanyexception override configuration register 0. + 0x274 + 0x20 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core1 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core1 toomanyexception override configuration register 1. + 0x278 + 0x20 + 0x00000001 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_0 + BackUp access peripherals permission configuration register 0. + 0x27C + 0x20 + + + BACKUP_BUS_PMS_CONSTRAIN_LOCK + Set 1 to lock BackUp permission configuration registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_1 + BackUp access peripherals permission configuration register 1. + 0x280 + 0x20 + 0xFF33CFFF + + + BACKUP_BUS_PMS_CONSTRAIN_UART + BackUp access uart permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + BackUp access g0spi_1 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + BackUp access g0spi_0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_GPIO + BackUp access gpio permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE2 + BackUp access fe2 permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE + BackUp access fe permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTC + BackUp access rtc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + BackUp access io_mux permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_HINF + BackUp access hinf permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_MISC + BackUp access misc permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C + BackUp access i2c permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S0 + BackUp access i2s0 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART1 + BackUp access uart1 permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_2 + BackUp access peripherals permission configuration register 2. + 0x284 + 0x20 + 0xFFCFFFF3 + + + BACKUP_BUS_PMS_CONSTRAIN_BT + BackUp access bt permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + BackUp access i2c_ext0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + BackUp access uhci0 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLCHOST + BackUp access slchost permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RMT + BackUp access rmt permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PCNT + BackUp access pcnt permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLC + BackUp access slc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LEDC + BackUp access ledc permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BACKUP + BackUp access backup permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BB + BackUp access bb permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM0 + BackUp access pwm0 permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + BackUp access timergroup permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + BackUp access timergroup1 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + BackUp access systimer permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_3 + BackUp access peripherals permission configuration register 3. + 0x288 + 0x20 + 0x3CC3FFFF + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + BackUp access spi_2 permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_3 + BackUp access spi_3 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + BackUp access apb_ctrl permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 + BackUp access i2c_ext1 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST + BackUp access sdio_host permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CAN + BackUp access can permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM1 + BackUp access pwm1 permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S1 + BackUp access i2s1 permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART2 + BackUp access uart2 permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RWBT + BackUp access rwbt permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + BackUp access wifimac permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWR + BackUp access pwr permission. + 28 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_4 + BackUp access peripherals permission configuration register 4. + 0x28C + 0x20 + 0xFFFFFFFF + + + BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + BackUp access usb_device permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + BackUp access usb_wrap permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + BackUp access crypto_peri permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + BackUp access crypto_dma permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + BackUp access apb_adc permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM + BackUp access lcd_cam permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + BackUp access bt_pwr permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB + BackUp access usb permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTEM + BackUp access system permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE + BackUp access sensitive permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT + BackUp access interrupt permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY + BackUp access dma_copy permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG + BackUp access cache_config permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_AD + BackUp access ad permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DIO + BackUp access dio permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER + BackUp access world_controller permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_5 + BackUp access peripherals permission configuration register 5. + 0x290 + 0x20 + 0x000007FF + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR + BackUp access rtcfast_spltaddr permission. + 0 + 11 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_6 + BackUp access peripherals permission configuration register 6. + 0x294 + 0x20 + 0x0000003F + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L + BackUp access rtcfast_l permission. + 0 + 3 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H + BackUp access rtcfast_h permission. + 3 + 3 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_0 + BackUp permission report register 0. + 0x298 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_LOCK + Set 1 to lock BackUp permission report registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_1 + BackUp permission report register 1. + 0x29C + 0x20 + 0x00000003 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that BackUp initiate illegal access. + 0 + 1 + read-write + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that BackUp initiate illegal access. + 1 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_2 + BackUp permission report register 2. + 0x2A0 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + Record BackUp illegal access interrupt state. + 0 + 1 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + Record htrans when BackUp initate illegal access. + 1 + 2 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when BackUp initate illegal access. + 3 + 3 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when BackUp initiate illegal access. + 6 + 1 + read-only + + + + + BACKUP_BUS_PMS_MONITOR_3 + BackUp permission report register 3. + 0x2A4 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + Record address information when BackUp initiate illegal access. + 0 + 32 + read-only + + + + + EDMA_BOUNDARY_LOCK + EDMA boundary lock register. + 0x2A8 + 0x20 + + + EDMA_BOUNDARY_LOCK + Set 1 to lock EDMA boundary registers. + 0 + 1 + read-write + + + + + EDMA_BOUNDARY_0 + EDMA boundary 0 configuration + 0x2AC + 0x20 + + + EDMA_BOUNDARY_0 + This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_1 + EDMA boundary 1 configuration + 0x2B0 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_1 + This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_2 + EDMA boundary 2 configuration + 0x2B4 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_2 + This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_PMS_SPI2_LOCK + EDMA-SPI2 permission lock register. + 0x2B8 + 0x20 + + + EDMA_PMS_SPI2_LOCK + Set 1 to lock EDMA-SPI2 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI2 + EDMA-SPI2 permission control register. + 0x2BC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SPI3_LOCK + EDMA-SPI3 permission lock register. + 0x2C0 + 0x20 + + + EDMA_PMS_SPI3_LOCK + Set 1 to lock EDMA-SPI3 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI3 + EDMA-SPI3 permission control register. + 0x2C4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_UHCI0_LOCK + EDMA-UHCI0 permission lock register. + 0x2C8 + 0x20 + + + EDMA_PMS_UHCI0_LOCK + Set 1 to lock EDMA-UHCI0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_UHCI0 + EDMA-UHCI0 permission control register. + 0x2CC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S0_LOCK + EDMA-I2S0 permission lock register. + 0x2D0 + 0x20 + + + EDMA_PMS_I2S0_LOCK + Set 1 to lock EDMA-I2S0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S0 + EDMA-I2S0 permission control register. + 0x2D4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S1_LOCK + EDMA-I2S1 permission lock register. + 0x2D8 + 0x20 + + + EDMA_PMS_I2S1_LOCK + Set 1 to lock EDMA-I2S1 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S1 + EDMA-I2S1 permission control register. + 0x2DC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_LCD_CAM_LOCK + EDMA-LCD/CAM permission lock register. + 0x2E0 + 0x20 + + + EDMA_PMS_LCD_CAM_LOCK + Set 1 to lock EDMA-LCD/CAM permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_LCD_CAM + EDMA-LCD/CAM permission control register. + 0x2E4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_AES_LOCK + EDMA-AES permission lock register. + 0x2E8 + 0x20 + + + EDMA_PMS_AES_LOCK + Set 1 to lock EDMA-AES permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_AES + EDMA-AES permission control register. + 0x2EC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SHA_LOCK + EDMA-SHA permission lock register. + 0x2F0 + 0x20 + + + EDMA_PMS_SHA_LOCK + Set 1 to lock EDMA-SHA permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SHA + EDMA-SHA permission control register. + 0x2F4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_ADC_DAC_LOCK + EDMA-ADC/DAC permission lock register. + 0x2F8 + 0x20 + + + EDMA_PMS_ADC_DAC_LOCK + Set 1 to lock EDMA-ADC/DAC permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_ADC_DAC + EDMA-ADC/DAC permission control register. + 0x2FC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_RMT_LOCK + EDMA-RMT permission lock register. + 0x300 + 0x20 + + + EDMA_PMS_RMT_LOCK + Set 1 to lock EDMA-RMT permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_RMT + EDMA-RMT permission control register. + 0x304 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + CLOCK_GATE + Sensitive module clock gate configuration register. + 0x308 + 0x20 + 0x00000001 + + + REG_CLK_EN + Set 1 to enable clock gate function. + 0 + 1 + read-write + + + + + RTC_PMS + RTC coprocessor permission register. + 0x30C + 0x20 + + + DIS_RTC_CPU + Set 1 to disable rtc coprocessor. + 0 + 1 + read-write + + + + + DATE + Sensitive version register. + 0xFFC + 0x20 + 0x02101280 + + + DATE + Sensitive Date register. + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 77 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + sha mode + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + sha t_string(used if and only if mode == sha_256/t) + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + sha t_length(used if and only if mode == sha_256/t) + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + dma-sha block number + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + reserved. + 1 + 31 + write-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + reserved. + 1 + 31 + write-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + sha busy state. 1'b0: idle 1'b1: busy + 0 + 1 + read-only + + + + + DMA_START DMA configuration register 1. 0x1C 0x20 - DMA_START - start dma-sha + DMA_START + start dma-sha + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + continue dma-sha + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + clear sha interrupt + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + sha interrupt enable register. 1'b0: disable(default) 1'b1: enable + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20190402 + + + DATE + sha date information/ sha version information + 0 + 30 + read-write + + + + + 16 + 0x4 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x20 + + + 16 + 0x4 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x20 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x60003000 + + 0x0 + 0x98 + registers + + + SPI_MEM_REJECT_CACHE + 60 + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control 1 register. + 0xC + 0x20 + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. + 30 + 1 + read-write + + + + + CTRL2 + SPI0 control 2 register. + 0x10 + 0x20 + 0x00002C21 + + + CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI0 accesses to flash. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 6 + 1 + read-write + + + CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 7 + 1 + read-write + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the DUMMY phase of an SPI transfer. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI0 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + FSUB_PIN + Flash is connected to SPI SUBPIN bus. + 7 + 1 + read-write + + + SSUB_PIN + Ext_RAM is connected to SPI SUBPIN bus. + 8 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 external RAM bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + Set this bit to enable Cache's access and SPI0's transfer. + 0 + 1 + read-write + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. + 2 + 1 + read-write + + + FDIN_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + CACHE_USR_SCMD_4BYTE + Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + 0 + 1 + read-write + + + USR_SRAM_DIO + Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + 1 + 1 + read-write + + + USR_SRAM_QIO + Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + 2 + 1 + read-write + + + USR_WR_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations. + 3 + 1 + read-write + + + USR_RD_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations. + 4 + 1 + read-write + + + CACHE_SRAM_USR_RCMD + 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2. + 5 + 1 + read-write + + + SRAM_RDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer. + 6 + 6 + read-write + + + SRAM_ADDR_BITLEN + When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + CACHE_SRAM_USR_WCMD + 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3. + 20 + 1 + read-write + + + SRAM_OCT + Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. + 21 + 1 + read-write + + + SRAM_WDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer. + 22 + 6 + read-write + + + + + SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + + + SCLK_MODE + SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + SWB_MODE + Mode bits when SPI0 accesses to Ext_RAM. + 2 + 8 + read-write + + + SDIN_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. + 10 + 1 + read-write + + + SDOUT_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 11 + 1 + read-write + + + SADDR_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 12 + 1 + read-write + + + SCMD_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. + 13 + 1 + read-write + + + SDIN_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. + 14 + 1 + read-write + + + SDOUT_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 15 + 1 + read-write + + + SADDR_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 16 + 1 + read-write + + + SCMD_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. + 17 + 1 + read-write + + + SDIN_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. + 18 + 1 + read-write + + + SDOUT_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. + 19 + 1 + read-write + + + SADDR_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. + 20 + 1 + read-write + + + SCMD_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. + 21 + 1 + read-write + + + SDUMMY_OUT + When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 22 + 1 + read-write + + + + + SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + CACHE_SRAM_USR_RD_CMD_VALUE + When SPI0 reads Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_RD_CMD_BITLEN + When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + CACHE_SRAM_USR_WR_CMD_VALUE + When SPI0 writes Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_WR_CMD_BITLEN + When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_CLK + SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + 0x50 + 0x20 + 0x00030103 + + + SCLKCNT_L + It must equal to the value of SPI_MEM_SCLKCNT_N. + 0 + 8 + read-write + + + SCLKCNT_H + It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + SCLKCNT_N + When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + 16 + 8 + read-write + + + SCLK_EQU_SYSCLK + When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + FSM + SPI0 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + TIMING_CALI + SPI0 timing compensation register when accesses to flash. + 0xA8 + 0x20 + + + TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DIN_MODE + MSPI input timing delay mode control register when accesses to flash. + 0xAC + 0x20 + + + DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + DIN_NUM + MSPI input timing delay number control register when accesses to flash. + 0xB0 + 0x20 + + + DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + DOUT_MODE + MSPI output timing delay mode control register when accesses to flash. + 0xB4 + 0x20 + + + DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + SPI0 Ext_RAM timing compensation register. + 0xBC + 0x20 + + + SPI_SMEM_TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI input timing delay mode control register when accesses to Ext_RAM. + 0xC0 + 0x20 + + + SPI_SMEM_DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI input timing delay number control register when accesses to Ext_RAM. + 0xC4 + 0x20 + + + SPI_SMEM_DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI output timing delay mode control register when accesses to Ext_RAM. + 0xC8 + 0x20 + + + SPI_SMEM_DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + ECC_CTRL + MSPI ECC control register + 0xCC + 0x20 + 0x0000000A + + + ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 0 + 8 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 8 + 1 + read-write + + + + + ECC_ERR_ADDR + MSPI ECC error address register + 0xD0 + 0x20 + + + ECC_ERR_ADDR + These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 32 + read-only + + + + + ECC_ERR_BIT + MSPI ECC error bits register + 0xD4 + 0x20 + + + ECC_DATA_ERR_BIT + It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 6 + 7 + read-only + + + ECC_CHK_ERR_BIT + When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte. + 13 + 3 + read-only + + + ECC_BYTE_ERR + It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 16 + 1 + read-only + + + ECC_ERR_CNT + This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 17 + 8 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0xDC + 0x20 + 0x0000B084 + + + SPI_SMEM_CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + 16 + 1 + read-write + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 24 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + + + DDR + SPI0 flash DDR mode control register + 0xE0 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to swap TX data of a word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xE4 + 0x20 + 0x00003020 + + + EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the ddr psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + DQS_LOOP_MODE + When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xEC + 0x20 + + + CORE_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. + 4 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-write + + + ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. + 4 + 1 + read-write + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + SPI_SMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM. + 0 + 2 + read-write + + + SPI_FMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash. + 2 + 2 + read-write + + + SPI_SPICLK_PAD_DRV_CTL_EN + SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. + 4 + 1 + read-write + + + DATE + SPI register version. + 5 + 23 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x60002000 + + 0x0 + 0xB4 + registers + + + SPI1 + 20 + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + Two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + FWRITE_DUAL + Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + 12 + 1 + read-write + + + FWRITE_QUAD + Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + 13 + 1 + read-write + + + FWRITE_DIO + Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + 14 + 1 + read-write + + + FWRITE_QIO + Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + Set this bit to enable the DOUT phase of an write-data operation. + 27 + 1 + read-write + + + USR_MISO + Set this bit to enable enable the DIN phase of a read-data operation. + 28 + 1 + read-write + + + USR_DUMMY + Set this bit to enable enable the DUMMY phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + Set this bit to enable enable the ADDR phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + Set this bit to enable enable the CMD phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 write-data bit length register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of DOUT phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 read-data bit length register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of DIN phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 read control register. + 0x2C + 0x20 + + + STATUS + The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI1 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI1 misc register. + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. + 0 + 1 + read-write + + + CS1_DIS + Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + AUTO_PER + Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + 11 + 1 + read-write + + + + + TX_CRC + SPI1 CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + FDIN_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + FSM + SPI1 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_EN + Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + 0 + 1 + read-write + + + WAITI_DUMMY + Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + 1 + 1 + read-write + + + WAITI_CMD + The command value of auto wait flash idle transfer(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend control register + 0x9C + 0x20 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + Set this bit to add delay time after program erase resume(PER) is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + Set this bit to add delay time after program erase suspend(PES) command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES transfer trigger PES transfer option. + 4 + 1 + read-write + + + PESR_IDLE_EN + 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. + 5 + 1 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0000EAF4 + + + FLASH_PES_EN + Set this bit to enable auto-suspend function. + 0 + 1 + read-write + + + FLASH_PER_COMMAND + Program/Erase resume command value. + 1 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command value. + 9 + 8 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + 0 + 1 + read-write + + + FLASH_HPM_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_256 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_256 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing compensation register when accesses to flash or Ext_RAM. + 0xA8 + 0x20 + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DDR + SPI1 DDR control register + 0xE0 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0: in SDR mode. + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDRmode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder TX data of the word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-write + + + BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 3 + 1 + read-write + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI2 + 21 + + + SPI2_DMA + 44 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02101190 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller 3 + 0x60025000 + + SPI3 + 22 + + + SPI3_DMA + 45 + + + + SYSTEM + System Configuration Registers + SYSTEM + 0x600C0000 + + 0x0 + 0xA8 + registers + + + + CORE_1_CONTROL_0 + Core0 control regiter 0 + 0x0 + 0x20 + 0x00000004 + + + CONTROL_CORE_1_RUNSTALL + Set 1 to stall core1 + 0 + 1 + read-write + + + CONTROL_CORE_1_CLKGATE_EN + Set 1 to open core1 clock + 1 + 1 + read-write + + + CONTROL_CORE_1_RESETING + Set 1 to let core1 reset + 2 + 1 + read-write + + + + + CORE_1_CONTROL_1 + Core0 control regiter 1 + 0x4 + 0x20 + + + CONTROL_CORE_1_MESSAGE + it's only a R/W register, no function, software can write any value + 0 + 32 + read-write + + + + + CPU_PERI_CLK_EN + cpu_peripheral clock configuration register + 0x8 + 0x20 + + + CLK_EN_ASSIST_DEBUG + Set 1 to open assist_debug module clock + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + Set 1 to open dedicated_gpio module clk + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset configuration regsiter + 0xC + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + Set 1 to let assist_debug module reset + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + Set 1 to let dedicated_gpio module reset + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu peripheral clock configuration register + 0x10 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field used to sel cpu clock frequent. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field used to sel pll frequent. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask configuration register + 0x14 + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set 1 to mask memory power down. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock configuration regsiter 0 + 0x18 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + Set 1 to enable TIMERS clock + 0 + 1 + read-write + + + SPI01_CLK_EN + Set 1 to enable SPI01 clock + 1 + 1 + read-write + + + UART_CLK_EN + Set 1 to enable UART clock + 2 + 1 + read-write + + + WDG_CLK_EN + Set 1 to enable WDG clock + 3 + 1 + read-write + + + I2S0_CLK_EN + Set 1 to enable I2S0 clock + 4 + 1 + read-write + + + UART1_CLK_EN + Set 1 to enable UART1 clock + 5 + 1 + read-write + + + SPI2_CLK_EN + Set 1 to enable SPI2 clock + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set 1 to enable I2C_EXT0 clock + 7 + 1 + read-write + + + UHCI0_CLK_EN + Set 1 to enable UHCI0 clock + 8 + 1 + read-write + + + RMT_CLK_EN + Set 1 to enable RMT clock + 9 + 1 + read-write + + + PCNT_CLK_EN + Set 1 to enable PCNT clock + 10 + 1 + read-write + + + LEDC_CLK_EN + Set 1 to enable LEDC clock + 11 + 1 + read-write + + + UHCI1_CLK_EN + Set 1 to enable UHCI1 clock + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set 1 to enable TIMERGROUP clock + 13 + 1 + read-write + + + EFUSE_CLK_EN + Set 1 to enable EFUSE clock + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + Set 1 to enable TIMERGROUP1 clock + 15 + 1 + read-write + + + SPI3_CLK_EN + Set 1 to enable SPI3 clock + 16 + 1 + read-write + + + PWM0_CLK_EN + Set 1 to enable PWM0 clock + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + Set 1 to enable I2C_EXT1 clock + 18 + 1 + read-write + + + TWAI_CLK_EN + Set 1 to enable CAN clock + 19 + 1 + read-write + + + PWM1_CLK_EN + Set 1 to enable PWM1 clock + 20 + 1 + read-write + + + I2S1_CLK_EN + Set 1 to enable I2S1 clock + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + Set 1 to enable SPI2_DMA clock + 22 + 1 + read-write + + + USB_CLK_EN + Set 1 to enable USB clock + 23 + 1 + read-write + + + UART_MEM_CLK_EN + Set 1 to enable UART_MEM clock + 24 + 1 + read-write + + + PWM2_CLK_EN + Set 1 to enable PWM2 clock + 25 + 1 + read-write + + + PWM3_CLK_EN + Set 1 to enable PWM3 clock + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + Set 1 to enable SPI4 clock + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + Set 1 to enable APB_SARADC clock + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set 1 to enable SYSTEMTIMER clock + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set 1 to enable ADC2_ARB clock + 30 + 1 + read-write + + + SPI4_CLK_EN + Set 1 to enable SPI4 clock + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock configuration regsiter 1 + 0x1C + 0x20 + 0x00000600 + + + PERI_BACKUP_CLK_EN + Set 1 to enable BACKUP clock + 0 + 1 + read-write + + + CRYPTO_AES_CLK_EN + Set 1 to enable AES clock + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set 1 to enable SHA clock + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + Set 1 to enable RSA clock + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + Set 1 to enable DS clock + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + Set 1 to enable HMAC clock + 5 + 1 + read-write + + + DMA_CLK_EN + Set 1 to enable DMA clock + 6 + 1 + read-write + + + SDIO_HOST_CLK_EN + Set 1 to enable SDIO_HOST clock + 7 + 1 + read-write + + + LCD_CAM_CLK_EN + Set 1 to enable LCD_CAM clock + 8 + 1 + read-write + + + UART2_CLK_EN + Set 1 to enable UART2 clock + 9 + 1 + read-write + + + USB_DEVICE_CLK_EN + Set 1 to enable USB_DEVICE clock + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + peripheral reset configuration register0 + 0x20 + 0x20 + + + TIMERS_RST + Set 1 to let TIMERS reset + 0 + 1 + read-write + + + SPI01_RST + Set 1 to let SPI01 reset + 1 + 1 + read-write + + + UART_RST + Set 1 to let UART reset + 2 + 1 + read-write + + + WDG_RST + Set 1 to let WDG reset + 3 + 1 + read-write + + + I2S0_RST + Set 1 to let I2S0 reset + 4 + 1 + read-write + + + UART1_RST + Set 1 to let UART1 reset + 5 + 1 + read-write + + + SPI2_RST + Set 1 to let SPI2 reset + 6 + 1 + read-write + + + I2C_EXT0_RST + Set 1 to let I2C_EXT0 reset + 7 + 1 + read-write + + + UHCI0_RST + Set 1 to let UHCI0 reset + 8 + 1 + read-write + + + RMT_RST + Set 1 to let RMT reset + 9 + 1 + read-write + + + PCNT_RST + Set 1 to let PCNT reset + 10 + 1 + read-write + + + LEDC_RST + Set 1 to let LEDC reset + 11 + 1 + read-write + + + UHCI1_RST + Set 1 to let UHCI1 reset + 12 + 1 + read-write + + + TIMERGROUP_RST + Set 1 to let TIMERGROUP reset + 13 + 1 + read-write + + + EFUSE_RST + Set 1 to let EFUSE reset + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set 1 to let TIMERGROUP1 reset + 15 + 1 + read-write + + + SPI3_RST + Set 1 to let SPI3 reset + 16 + 1 + read-write + + + PWM0_RST + Set 1 to let PWM0 reset + 17 + 1 + read-write + + + I2C_EXT1_RST + Set 1 to let I2C_EXT1 reset + 18 + 1 + read-write + + + TWAI_RST + Set 1 to let CAN reset + 19 + 1 + read-write + + + PWM1_RST + Set 1 to let PWM1 reset + 20 + 1 + read-write + + + I2S1_RST + Set 1 to let I2S1 reset + 21 + 1 + read-write + + + SPI2_DMA_RST + Set 1 to let SPI2 reset + 22 + 1 + read-write + + + USB_RST + Set 1 to let USB reset + 23 + 1 + read-write + + + UART_MEM_RST + Set 1 to let UART_MEM reset + 24 + 1 + read-write + + + PWM2_RST + Set 1 to let PWM2 reset + 25 + 1 + read-write + + + PWM3_RST + Set 1 to let PWM3 reset + 26 + 1 + read-write + + + SPI3_DMA_RST + Set 1 to let SPI3 reset + 27 + 1 + read-write + + + APB_SARADC_RST + Set 1 to let APB_SARADC reset + 28 + 1 + read-write + + + SYSTIMER_RST + Set 1 to let SYSTIMER reset + 29 + 1 + read-write + + + ADC2_ARB_RST + Set 1 to let ADC2_ARB reset + 30 + 1 + read-write + + + SPI4_RST + Set 1 to let SPI4 reset + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset configuration regsiter 1 + 0x24 + 0x20 + 0x000001FE + + + PERI_BACKUP_RST + Set 1 to let BACKUP reset + 0 + 1 + read-write + + + CRYPTO_AES_RST + Set 1 to let CRYPTO_AES reset + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set 1 to let CRYPTO_SHA reset + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set 1 to let CRYPTO_RSA reset + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set 1 to let CRYPTO_DS reset + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set 1 to let CRYPTO_HMAC reset + 5 + 1 + read-write + + + DMA_RST + Set 1 to let DMA reset + 6 + 1 + read-write + + + SDIO_HOST_RST + Set 1 to let SDIO_HOST reset + 7 + 1 + read-write + + + LCD_CAM_RST + Set 1 to let LCD_CAM reset + 8 + 1 + read-write + + + UART2_RST + Set 1 to let UART2 reset + 9 + 1 + read-write + + + USB_DEVICE_RST + Set 1 to let USB_DEVICE reset + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + low power clock frequent division factor configuration regsiter + 0x28 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + This field is lower power clock frequent division factor + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + low power clock configuration register + 0x2C + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + This field is lower power clock frequent division factor b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + This field is lower power clock frequent division factor a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + Set 1 to select rtc-slow clock as rtc low power clock + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set 1 to select 8m clock as rtc low power clock + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set 1 to select xtal clock as rtc low power clock + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set 1 to select xtal32k clock as low power clock + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set 1 to enable RTC low power clock + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt source register 0 + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set 1 to generate cpu interrupt 0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt source register 1 + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set 1 to generate cpu interrupt 1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt source register 2 + 0x38 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set 1 to generate cpu interrupt 2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt source register 3 + 0x3C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set 1 to generate cpu interrupt 3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x40 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set 1 to force power up RSA memory, this bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set 1 to force power down RSA memory,this bit has the highest priority. + 2 + 1 + read-write + + + + + EDMA_CTRL + EDMA control register + 0x44 + 0x20 + 0x00000001 + + + EDMA_CLK_ON + Set 1 to enable EDMA clock. + 0 + 1 + read-write + + + EDMA_RESET + Set 1 to let EDMA reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + Cache control register + 0x48 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + Set 1 to enable icache clock + 0 + 1 + read-write + + + ICACHE_RESET + Set 1 to let icache reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + Set 1 to enable dcache clock + 2 + 1 + read-write + + + DCACHE_RESET + Set 1 to let dcache reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + External memory encrypt and decrypt control register + 0x4C + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set 1 to enable the SPI manual encrypt. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set 1 to enable download DB encrypt. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set 1 to enable download G0CB decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set 1 to enable download manual encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + RTC fast memory configuration register + 0x50 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set 1 to start the CRC of RTC memory + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC.1 means finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + RTC fast memory CRC control register + 0x54 + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + ******* Description *********** + 0x58 + 0x20 + + + REDUNDANT_ECO_DRIVE + ******* Description *********** + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + ******* Description *********** + 1 + 1 + read-only + + + + + CLOCK_GATE + ******* Description *********** + 0x5C + 0x20 + 0x00000001 + + + CLK_EN + ******* Description *********** + 0 + 1 + read-write + + + + + SYSCLK_CONF + System clock configuration register. + 0x60 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select soc clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read xtal frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + Reserved. + 19 + 1 + read-only + + + + + MEM_PVT + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + MEM_PATH_LEN + ******* Description *********** + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + ******* Description *********** + 4 + 1 + write-only + + + MONITOR_EN + ******* Description *********** + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + ******* Description *********** + 6 + 16 + read-only + + + MEM_VT_SEL + ******* Description *********** + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + ******* Description *********** + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_LVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + ******* Description *********** + 0x6C + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_NVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + ******* Description *********** + 0x70 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_HVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + ******* Description *********** + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + ******* Description *********** + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + ******* Description *********** + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + ******* Description *********** + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + ******* Description *********** + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + ******* Description *********** + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + ******* Description *********** + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + ******* Description *********** + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + ******* Description *********** + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + ******* Description *********** + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + ******* Description *********** + 0x9C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + ******* Description *********** + 0xA0 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + DATE + version register + 0xFFC + 0x20 + 0x02101220 + + + DATE + version register + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear 0 1 write-only + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + - DMA_CONTINUE - DMA configuration register 2. + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02012251 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x6001F000 + + 0x0 + 0x8C + registers + + + TG0_T0_LEVEL + 50 + + + TG0_T1_LEVEL + 51 + + + TG0_WDT_LEVEL + 52 + + + + 2 + 0x24 + T%sCONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sLO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sHI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + 2 + 0x24 + T%sUPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG 0x20 0x20 - DMA_CONTINUE - continue dma-sha + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + Reserved + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. 0 - 1 - write-only + 32 + read-write - CLEAR_IRQ - Interrupt clear register. - 0x24 + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C 0x20 + 0x000FFFFF - CLEAR_INTERRUPT - clear sha interrupt + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. 0 - 1 - write-only + 32 + read-write - IRQ_ENA - Interrupt enable register. - 0x28 + WDTFEED + Write to feed the watchdog timer + 0x60 0x20 - INTERRUPT_ENA - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable + WDT_FEED + Write any value to feed the MWDT. (WO) 0 - 1 - read-write + 32 + write-only - DATE - Date register. - 0x2C + WDTWPROTECT + Watchdog write protect register + 0x64 0x20 - 0x20190402 + 0x50D83AA1 - DATE - sha date information/ sha version information + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. 0 - 30 + 32 read-write - 64 - 0x1 - H_MEM[%s] - Sha H memory which contains intermediate hash or finial hash. - 0x40 - 0x8 - - - 64 - 0x1 - M_MEM[%s] - Sha M memory which contains message. - 0x80 - 0x8 - - - - - SPI0 - SPI (Serial Peripheral Interface) Controller - SPI0 - 0x60003000 - - 0x0 - 0x98 - registers - - - SPI_MEM_REJECT - 60 - - - - CTRL - SPI0 control register. - 0x8 + RTCCALICFG + RTC calibration configure register + 0x68 0x20 - 0x002C2000 + 0x00013000 - FDUMMY_OUT - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. - 3 - 1 - read-write - - - FDOUT_OCT - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. - 4 - 1 - read-write - - - FDIN_OCT - Set this bit to enable 8-bit-mode(8-bm) in DIN phase. - 5 + RTC_CALI_START_CYCLING + Reserved + 12 1 read-write - FADDR_OCT - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. - 6 - 1 + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. + 13 + 2 read-write - FCMD_DUAL - Set this bit to enable 2-bit-mode(2-bm) in CMD phase. - 7 + RTC_CALI_RDY + Reserved + 15 1 - read-write + read-only - FCMD_QUAD - Set this bit to enable 4-bit-mode(4-bm) in CMD phase. - 8 - 1 + RTC_CALI_MAX + Reserved + 16 + 15 read-write - FCMD_OCT - Set this bit to enable 8-bit-mode(8-bm) in CMD phase. - 9 + RTC_CALI_START + Reserved + 31 1 read-write + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + - FASTRD_MODE - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. - 13 + RTC_CALI_CYCLING_DATA_VLD + Reserved + 0 1 - read-write + read-only - FREAD_DUAL - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. - 14 - 1 - read-write + RTC_CALI_VALUE + Reserved + 7 + 25 + read-only + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + - Q_POL - The bit is used to set MISO line polarity, 1: high 0, low - 18 + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 1 read-write - D_POL - The bit is used to set MOSI line polarity, 1: high 0, low - 19 + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 1 read-write - FREAD_QUAD - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. - 20 + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 1 read-write + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + - WP - Write protect signal output when SPI is idle. 1: output high, 0: output low. - 21 + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 1 read-write - FREAD_DIO - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. - 23 + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 1 read-write - FREAD_QIO - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. - 24 + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 1 read-write - CTRL1 - SPI0 control 1 register. - 0xC + INT_ST_TIMERS + Masked interrupt status + 0x78 0x20 - CLK_MODE - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. 0 - 2 - read-write + 1 + read-only - RXFIFO_RST - SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. - 30 + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 1 - read-write + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only - CTRL2 - SPI0 control 2 register. - 0x10 + INT_CLR_TIMERS + Interrupt clear bits + 0x7C 0x20 - 0x00002C21 - CS_SETUP_TIME - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. 0 - 5 - read-write - - - CS_HOLD_TIME - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. - 5 - 5 - read-write - - - ECC_CS_HOLD_TIME - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. - 10 - 3 - read-write - - - ECC_SKIP_PAGE_CORNER - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash. - 13 1 - read-write + write-only - ECC_16TO18_BYTE_EN - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. - 14 + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 1 - read-write - - - CS_HOLD_DELAY - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - 25 - 6 - read-write + write-only - SYNC_RESET - The FSM will be reset. - 31 + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 1 - read-write + write-only - CLOCK - SPI_CLK clock division register when SPI0 accesses to flash. - 0x14 + RTCCALICFG2 + Timer group calibration register + 0x80 0x20 - 0x00030103 + 0xFFFFFF98 - CLKCNT_L - It must equal to the value of SPI_MEM_CLKCNT_N. + RTC_CALI_TIMEOUT + RTC calibration timeout indicator 0 - 8 - read-write + 1 + read-only - CLKCNT_H - It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). - 8 - 8 + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 read-write - CLKCNT_N - When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) - 16 - 8 + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 read-write + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02003071 + - CLK_EQU_SYSCLK - When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. - 31 - 1 + NTIMERS_DATE + Timer version control register + 0 + 28 read-write - USER - SPI0 user register. - 0x18 + REGCLK + Timer group clock gate register + 0xFC 0x20 - CS_HOLD - Set this bit to keep SPI_CS low when MSPI is in DONE state. - 6 + CLK_EN + Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens. + 31 1 read-write + + + + + + TIMG1 + Timer Group 1 + 0x60020000 + + TG1_T0_LEVEL + 53 + + + TG1_T1_LEVEL + 54 + + + TG1_WDT_LEVEL + 55 + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x6C + registers + + + TWAI0 + 37 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + - CS_SETUP - Set this bit to keep SPI_CS low when MSPI is in PREP state. - 7 + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 1 read-write - CK_OUT_EDGE - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. - 9 + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 1 read-write - USR_DUMMY_IDLE - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. - 26 + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 1 read-write - USR_DUMMY - This bit enable the DUMMY phase of an SPI transfer. - 29 + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 1 read-write - USER1 - SPI0 user1 register. - 0x1C + CMD + Command Register + 0x4 0x20 - 0x5C000007 - USR_DUMMY_CYCLELEN - The SPI_CLK cycle length minus 1 of DUMMY phase. + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. 0 - 6 - read-write - - - USR_ADDR_BITLEN - The length in bits of ADDR phase. The register value shall be (bit_num-1). - 26 - 6 - read-write + 1 + write-only - - - - USER2 - SPI0 user2 register. - 0x20 - 0x20 - 0x70000000 - - USR_COMMAND_VALUE - The value of user defined(USR) command. - 0 - 16 - read-write + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only - USR_COMMAND_BITLEN - The length in bits of CMD phase. The register value shall be (bit_num-1) - 28 - 4 - read-write + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only - - - - RD_STATUS - SPI0 read control register. - 0x2C - 0x20 - - WB_MODE - Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. - 16 - 8 - read-write + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only - - - - EXT_ADDR - SPI0 extended address register. - 0x30 - 0x20 - - EXT_ADDR - The register are the higher 32bits in the 64 bits address mode. - 0 - 32 - read-write + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only - MISC - SPI0 misc register - 0x34 + STATUS + Status register + 0x8 0x20 - FSUB_PIN - Flash is connected to SPI SUBPIN bus. - 7 + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 1 - read-write + read-only - SSUB_PIN - Ext_RAM is connected to SPI SUBPIN bus. - 8 + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 1 - read-write + read-only - CK_IDLE_EDGE - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle - 9 + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 1 - read-write + read-only - CS_KEEP_ACTIVE - SPI_CS line keep low when the bit is set. - 10 + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 1 - read-write + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only - CACHE_FCTRL - SPI0 external RAM bit mode control register. - 0x3C + INT_RAW + Interrupt Register + 0xC 0x20 - CACHE_REQ_EN - Set this bit to enable Cache's access and SPI0's transfer. + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. 0 1 - read-write + read-only - CACHE_USR_CMD_4BYTE - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. 1 1 - read-write + read-only - CACHE_FLASH_USR_CMD - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). 2 1 - read-write + read-only - FDIN_DUAL - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. 3 1 - read-write - - - FDOUT_DUAL - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. - 4 - 1 - read-write + read-only - FADDR_DUAL - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. 5 1 - read-write + read-only - FDIN_QUAD - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. 6 1 - read-write + read-only - FDOUT_QUAD - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. 7 1 - read-write - - - FADDR_QUAD - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. - 8 - 1 - read-write + read-only - CACHE_SCTRL - SPI0 external RAM control register - 0x40 + INT_ENA + Interrupt Enable Register + 0x10 0x20 - 0x0055C070 - CACHE_USR_SCMD_4BYTE - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. 0 1 read-write - USR_SRAM_DIO - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. 1 1 read-write - USR_SRAM_QIO - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. 2 1 read-write - USR_WR_SRAM_DUMMY - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations. + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. 3 1 read-write - USR_RD_SRAM_DUMMY - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations. - 4 + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 1 read-write - CACHE_SRAM_USR_RCMD - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2. - 5 + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 1 read-write - SRAM_RDUMMY_CYCLELEN - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer. - 6 - 6 + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 read-write + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + - SRAM_ADDR_BITLEN - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1). + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 - 6 + 2 read-write + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + - CACHE_SRAM_USR_WCMD - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3. - 20 - 1 + TIME_SEG1 + The width of PBS1. + 0 + 4 read-write - SRAM_OCT - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. - 21 - 1 + TIME_SEG2 + The width of PBS2. + 4 + 3 read-write - SRAM_WDUMMY_CYCLELEN - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer. - 22 - 6 + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 read-write - SRAM_CMD - SPI0 external RAM mode control register - 0x44 + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C 0x20 - SCLK_MODE - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. 0 - 2 - read-write + 5 + read-only + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + - SWB_MODE - Mode bits when SPI0 accesses to Ext_RAM. - 2 - 8 - read-write + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only - SDIN_DUAL - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. - 10 + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 read-write + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + - SDOUT_DUAL - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. - 11 - 1 + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 read-write + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + - SADDR_DUAL - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. - 12 - 1 + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 read-write + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + - SCMD_DUAL - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. - 13 - 1 + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + - SDIN_QUAD - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. - 14 - 1 + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + - SDOUT_QUAD - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. - 15 - 1 + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + - SADDR_QUAD - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. - 16 - 1 + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + - SCMD_QUAD - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. - 17 - 1 + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + - SDIN_OCT - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. - 18 - 1 + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + - SDOUT_OCT - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. - 19 - 1 + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + - SADDR_OCT - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. - 20 - 1 + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + - SCMD_OCT - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. - 21 - 1 + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + - SDUMMY_OUT - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. - 22 - 1 + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write - SRAM_DRD_CMD - SPI0 external RAM DDR read command control register - 0x48 + DATA_10 + Data register 10 + 0x68 0x20 - CACHE_SRAM_USR_RD_CMD_VALUE - When SPI0 reads Ext_RAM, it is the command value of CMD phase. + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. 0 - 16 + 8 read-write + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + - CACHE_SRAM_USR_RD_CMD_BITLEN - When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). - 28 - 4 + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 read-write - SRAM_DWR_CMD - SPI0 external RAM DDR write command control register - 0x4C + DATA_12 + Data register 12 + 0x70 0x20 - CACHE_SRAM_USR_WR_CMD_VALUE - When SPI0 writes Ext_RAM, it is the command value of CMD phase. + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. 0 - 16 + 8 read-write + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + - CACHE_SRAM_USR_WR_CMD_BITLEN - When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). - 28 - 4 - read-write + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only - SRAM_CLK - SPI_CLK clock division register when SPI0 accesses to Ext_RAM. - 0x50 + CLOCK_DIVIDER + Clock Divider register + 0x7C 0x20 - 0x00030103 - SCLKCNT_L - It must equal to the value of SPI_MEM_SCLKCNT_N. + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. 0 8 read-write - SCLKCNT_H - It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 - 8 - read-write - - - SCLKCNT_N - When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) - 16 - 8 - read-write - - - SCLK_EQU_SYSCLK - When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. - 31 1 read-write + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 27 + + - FSM - SPI0 state machine(FSM) status register. - 0x54 + FIFO + FIFO data register + 0x0 0x20 - ST - The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. 0 - 3 - read-only + 8 + read-write - TIMING_CALI - SPI0 timing compensation register when accesses to flash. - 0xA8 + INT_RAW + Raw interrupt status + 0x4 0x20 + 0x00000002 - TIMING_CLK_ENA - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 read-write - TIMING_CALI - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 read-write - EXTRA_DUMMY_CYCLELEN - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set. + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 - 3 - read-write - - - - - DIN_MODE - MSPI input timing delay mode control register when accesses to flash. - 0xAC - 0x20 - - - DIN0_MODE - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 0 - 3 + 1 read-write - DIN1_MODE - SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . 3 - 3 + 1 read-write - DIN2_MODE - SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 6 - 3 + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 read-write - DIN3_MODE - SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 9 - 3 + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 read-write - DIN4_MODE - SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 12 - 3 + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 read-write - DIN5_MODE - SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 15 - 3 + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 read-write - DIN6_MODE - SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 18 - 3 + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 read-write - DIN7_MODE - SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 21 - 3 + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 read-write - DINS_MODE - SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 24 - 3 + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 read-write - - - - DIN_NUM - MSPI input timing delay number control register when accesses to flash. - 0xB0 - 0x20 - - DIN0_NUM - SPI_D input delay number. - 0 - 2 + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 read-write - DIN1_NUM - SPI_Q input delay number. - 2 - 2 + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 read-write - DIN2_NUM - SPI_WP input delay number. - 4 - 2 + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 read-write - DIN3_NUM - SPI_HD input delay number. - 6 - 2 + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 read-write - DIN4_NUM - SPI_IO4 input delay number. - 8 - 2 + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 read-write - DIN5_NUM - SPI_IO5 input delay number. - 10 - 2 + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 read-write - DIN6_NUM - SPI_IO6 input delay number. - 12 - 2 + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 read-write - DIN7_NUM - SPI_IO7 input delay number. - 14 - 2 + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 read-write - DINS_NUM - SPI_DQS input delay number. - 16 - 2 + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 read-write - DOUT_MODE - MSPI output timing delay mode control register when accesses to flash. - 0xB4 + INT_ST + Masked interrupt status + 0x8 0x20 - DOUT0_MODE - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 - read-write + read-only - DOUT1_MODE - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 - read-write + read-only - DOUT2_MODE - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 - read-write + read-only - DOUT3_MODE - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 3 1 - read-write + read-only - DOUT4_MODE - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 - read-write + read-only - DOUT5_MODE - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 - read-write + read-only - DOUT6_MODE - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 - read-write + read-only - DOUT7_MODE - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 - read-write + read-only - DOUTS_MODE - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 - read-write + read-only - - - - SPI_SMEM_TIMING_CALI - SPI0 Ext_RAM timing compensation register. - 0xBC - 0x20 - - SPI_SMEM_TIMING_CLK_ENA - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. - 0 + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 1 - read-write + read-only - SPI_SMEM_TIMING_CALI - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. - 1 + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 1 - read-write - - - SPI_SMEM_EXTRA_DUMMY_CYCLELEN - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. - 2 - 3 - read-write - - - - - SPI_SMEM_DIN_MODE - MSPI input timing delay mode control register when accesses to Ext_RAM. - 0xC0 - 0x20 - - - SPI_SMEM_DIN0_MODE - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 0 - 3 - read-write - - - SPI_SMEM_DIN1_MODE - SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 3 - 3 - read-write - - - SPI_SMEM_DIN2_MODE - SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 6 - 3 - read-write + read-only - SPI_SMEM_DIN3_MODE - SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 9 - 3 - read-write + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only - SPI_SMEM_DIN4_MODE - SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 - 3 - read-write - - - SPI_SMEM_DIN5_MODE - SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 15 - 3 - read-write - - - SPI_SMEM_DIN6_MODE - SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 18 - 3 - read-write - - - SPI_SMEM_DIN7_MODE - SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 21 - 3 - read-write - - - SPI_SMEM_DINS_MODE - SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - 24 - 3 - read-write - - - - - SPI_SMEM_DIN_NUM - MSPI input timing delay number control register when accesses to Ext_RAM. - 0xC4 - 0x20 - - - SPI_SMEM_DIN0_NUM - SPI_D input delay number. - 0 - 2 - read-write - - - SPI_SMEM_DIN1_NUM - SPI_Q input delay number. - 2 - 2 - read-write - - - SPI_SMEM_DIN2_NUM - SPI_WP input delay number. - 4 - 2 - read-write + 1 + read-only - SPI_SMEM_DIN3_NUM - SPI_HD input delay number. - 6 - 2 - read-write + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only - SPI_SMEM_DIN4_NUM - SPI_IO4 input delay number. - 8 - 2 - read-write + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only - SPI_SMEM_DIN5_NUM - SPI_IO5 input delay number. - 10 - 2 - read-write + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only - SPI_SMEM_DIN6_NUM - SPI_IO6 input delay number. - 12 - 2 - read-write + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only - SPI_SMEM_DIN7_NUM - SPI_IO7 input delay number. - 14 - 2 - read-write + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only - SPI_SMEM_DINS_NUM - SPI_DQS input delay number. - 16 - 2 - read-write + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only - SPI_SMEM_DOUT_MODE - MSPI output timing delay mode control register when accesses to Ext_RAM. - 0xC8 + INT_ENA + Interrupt enable bits + 0xC 0x20 - SPI_SMEM_DOUT0_MODE - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. 0 1 read-write - SPI_SMEM_DOUT1_MODE - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. 1 1 read-write - SPI_SMEM_DOUT2_MODE - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. 2 1 read-write - SPI_SMEM_DOUT3_MODE - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. 3 1 read-write - SPI_SMEM_DOUT4_MODE - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write - SPI_SMEM_DOUT5_MODE - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. 5 1 read-write - SPI_SMEM_DOUT6_MODE - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. 6 1 read-write - SPI_SMEM_DOUT7_MODE - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. 7 1 read-write - SPI_SMEM_DOUTS_MODE - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write - - - - ECC_CTRL - MSPI ECC control register - 0xCC - 0x20 - 0x0000000A - - ECC_ERR_INT_NUM - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - 0 - 8 + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 read-write - SPI_FMEM_ECC_ERR_INT_EN - Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - 8 + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 1 read-write - - - - ECC_ERR_ADDR - MSPI ECC error address register - 0xD0 - 0x20 - - ECC_ERR_ADDR - These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. - 0 - 32 - read-only + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write - - - - ECC_ERR_BIT - MSPI ECC error bits register - 0xD4 - 0x20 - - ECC_DATA_ERR_BIT - It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. - 6 - 7 - read-only + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write - ECC_CHK_ERR_BIT - When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte. + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. 13 - 3 - read-only + 1 + read-write - ECC_BYTE_ERR - It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. 16 1 - read-only + read-write - ECC_ERR_CNT - This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. 17 - 8 - read-only + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write - SPI_SMEM_AC - MSPI external RAM ECC and SPI CS timing control register - 0xDC + INT_CLR + Interrupt clear bits + 0x10 0x20 - 0x0000B084 - SPI_SMEM_CS_SETUP - Set this bit to keep SPI_CS low when MSPI is in PREP state. + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 - read-write + write-only - SPI_SMEM_CS_HOLD - Set this bit to keep SPI_CS low when MSPI is in DONE state. + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 - read-write + write-only - SPI_SMEM_CS_SETUP_TIME - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. 2 - 5 - read-write + 1 + write-only - SPI_SMEM_CS_HOLD_TIME - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. 7 - 5 - read-write + 1 + write-only - SPI_SMEM_ECC_CS_HOLD_TIME - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 - 3 - read-write + 1 + write-only - SPI_SMEM_ECC_SKIP_PAGE_CORNER - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. 15 1 - read-write + write-only - SPI_SMEM_ECC_16TO18_BYTE_EN - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. 16 1 - read-write + write-only - SPI_SMEM_ECC_ERR_INT_EN - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. - 24 + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 read-write - SPI_SMEM_CS_HOLD_DELAY - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - 25 - 6 + FRAG + The decimal part of the frequency divider factor. + 20 + 4 read-write - DDR - SPI0 flash DDR mode control register - 0xE0 + RX_FILT + Rx Filter configuration + 0x18 0x20 - 0x00003020 + 0x00000008 - SPI_FMEM_DDR_EN - 1: in ddr mode, 0 in sdr mode + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. 0 - 1 + 8 read-write - SPI_FMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in DDR mode. - 1 + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 1 read-write + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + - SPI_FMEM_DDR_RDAT_SWP - Set the bit to reorder RX data of the word in DDR mode. - 2 + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 1 - read-write + read-only - SPI_FMEM_DDR_WDAT_SWP - Set the bit to swap TX data of a word in DDR mode. - 3 + CTSN + This register represent the level value of the internal uart cts signal. + 14 1 - read-write + read-only - SPI_FMEM_DDR_CMD_DIS - the bit is used to disable dual edge in CMD phase when ddr mode. - 4 + RXD + This register represent the level value of the internal uart rxd signal. + 15 1 - read-write + read-only - SPI_FMEM_OUTMINBYTELEN - It is the minimum output data length in the panda device. - 5 - 7 - read-write + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only - SPI_FMEM_TX_DDR_MSK_EN - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash. - 12 + DTRN + This bit represents the level of the internal uart dtr signal. + 29 1 - read-write + read-only - SPI_FMEM_RX_DDR_MSK_EN - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash. - 13 + RTSN + This bit represents the level of the internal uart rts signal. + 30 1 - read-write + read-only - SPI_FMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI_CLK. - 14 - 7 - read-write + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + - SPI_FMEM_DDR_DQS_LOOP - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module - 21 + PARITY + This register is used to configure the parity check mode. + 0 1 read-write - SPI_FMEM_DDR_DQS_LOOP_MODE - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. - 22 + PARITY_EN + Set this bit to enable uart parity check. + 1 1 read-write - SPI_FMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 - 1 + BIT_NUM + This register is used to set the length of data. + 2 + 2 read-write - SPI_FMEM_HYPERBUS_MODE - Set this bit to enable the SPI HyperBus mode. - 25 - 1 + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 read-write - SPI_FMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 1 read-write - SPI_FMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. - 27 + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 1 read-write - SPI_FMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to flash. . - 28 + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 1 read-write - SPI_FMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 1 read-write - SPI_FMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 1 read-write - - - - SPI_SMEM_DDR - SPI0 external RAM DDR mode control register - 0xE4 - 0x20 - 0x00003020 - - EN - 1: in ddr mode, 0 in sdr mode - 0 + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 1 read-write - SPI_SMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in spi ddr mode. - 1 + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 1 read-write - RDAT_SWP - Set the bit to reorder rx data of the word in spi ddr mode. - 2 + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 1 read-write - WDAT_SWP - Set the bit to reorder tx data of the word in spi ddr mode. - 3 + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 1 read-write - CMD_DIS - the bit is used to disable dual edge in CMD phase when ddr mode. - 4 + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 1 read-write - SPI_SMEM_OUTMINBYTELEN - It is the minimum output data length in the ddr psram. - 5 - 7 + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 read-write - SPI_SMEM_TX_DDR_MSK_EN - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM. - 12 + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 1 read-write - SPI_SMEM_RX_DDR_MSK_EN - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM. - 13 + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 1 read-write - SPI_SMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI_CLK. - 14 - 7 + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 read-write - DQS_LOOP - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module - 21 + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 1 read-write - DQS_LOOP_MODE - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. - 22 + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 1 read-write - SPI_SMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 1 read-write - SPI_SMEM_HYPERBUS_MODE - Set this bit to enable the SPI HyperBus mode. - 25 + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 1 read-write - SPI_SMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 1 read-write - SPI_SMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. - 27 + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 1 read-write - SPI_SMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to external RAM. . - 28 + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 1 read-write - SPI_SMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 1 read-write - SPI_SMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 + MEM_CLK_EN + UART memory clock gate enable signal. + 28 1 read-write - CLOCK_GATE - SPI0 clk_gate register - 0xE8 + CONF1 + Configuration register 1 + 0x24 0x20 - 0x00000001 + 0x00018060 - CLK_EN - Register clock gate enable signal. 1: Enable. 0: Disable. + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. 0 - 1 + 10 read-write - - - - CORE_CLK_SEL - SPI0 module clock select register - 0xEC - 0x20 - - CORE_CLK_SEL - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. - 0 - 2 + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 10 + 10 read-write - - - - INT_ENA - SPI1 interrupt enable register - 0xF0 - 0x20 - - TOTAL_TRANS_END_INT_ENA - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 20 1 read-write - ECC_ERR_INT_ENA - The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - 4 + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 21 1 read-write - - - - INT_CLR - SPI1 interrupt clear register - 0xF4 - 0x20 - - TOTAL_TRANS_END_INT_CLR - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 22 1 - write-only + read-write - ECC_ERR_INT_CLR - The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. - 4 + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 23 1 - write-only + read-write - INT_RAW - SPI1 interrupt raw register - 0xF8 + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 0x20 + 0x00000FFF - TOTAL_TRANS_END_INT_RAW - The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. - 2 - 1 - read-only - - - ECC_ERR_INT_RAW - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. - 4 - 1 + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 read-only - INT_ST - SPI1 interrupt status register - 0xFC + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C 0x20 + 0x00000FFF - TOTAL_TRANS_END_INT_ST - The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 - 1 - read-only - - - ECC_ERR_INT_ST - The status bit for SPI_MEM_ECC_ERR_INT interrupt. - 4 - 1 + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 read-only - DATE - SPI0 version control register - 0x3FC + RXD_CNT + Autobaud edge change count register + 0x30 0x20 - 0x02101040 - SPI_SMEM_SPICLK_FUN_DRV - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM. + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. 0 - 2 - read-write - - - SPI_FMEM_SPICLK_FUN_DRV - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash. - 2 - 2 - read-write - - - SPI_SPICLK_PAD_DRV_CTL_EN - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. - 4 - 1 - read-write - - - DATE - SPI register version. - 5 - 23 - read-write + 10 + read-only - - - - SPI1 - SPI (Serial Peripheral Interface) Controller - SPI1 - 0x60002000 - - 0x0 - 0xB4 - registers - - - SPI1 - 20 - - - CMD - SPI1 memory command register - 0x0 + FLOW_CONF + Software flow-control configuration + 0x34 0x20 - FLASH_PE - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. - 17 - 1 - read-write - - - USR - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 18 - 1 - read-write - - - FLASH_HPM - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. - 19 - 1 - read-write - - - FLASH_RES - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. - 20 - 1 - read-write - - - FLASH_DP - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 21 + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 1 read-write - FLASH_CE - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 22 + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 1 read-write - FLASH_BE - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 23 + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 1 read-write - FLASH_SE - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 24 + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 1 read-write - FLASH_PP - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. - 25 + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 1 read-write - FLASH_WRSR - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 26 + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 1 read-write + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + - FLASH_RDSR - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 27 - 1 + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 read-write + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00004CE0 + - FLASH_RDID - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 28 - 1 + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 10 read-write - FLASH_WRDI - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 29 - 1 + XOFF_CHAR + This register stores the Xoff flow control char. + 10 + 8 read-write + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00004400 + - FLASH_WREN - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 30 - 1 + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 10 read-write - FLASH_READ - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 31 - 1 + XON_CHAR + This register stores the Xon flow control char. + 10 + 8 read-write - ADDR - SPI1 address register - 0x4 + TXBRK_CONF + Tx Break character configuration + 0x44 0x20 + 0x0000000A - USR_ADDR_VALUE - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. 0 - 32 + 8 read-write - CTRL - SPI1 control register - 0x8 + IDLE_CONF + Frame-end idle configuration + 0x48 0x20 - 0x002CA000 + 0x00040100 - FDUMMY_OUT - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. - 3 - 1 + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 read-write - FDOUT_OCT - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. - 4 - 1 + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 read-write + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + - FDIN_OCT - Set this bit to enable 8-bit-mode(8-bm) in DIN phase. - 5 + RS485_EN + Set this bit to choose the rs485 mode. + 0 1 read-write - FADDR_OCT - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. - 6 + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 1 read-write - FCMD_DUAL - Set this bit to enable 2-bit-mode(2-bm) in CMD phase. - 7 + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 1 read-write - FCMD_QUAD - Set this bit to enable 4-bit-mode(4-bm) in CMD phase. - 8 + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 1 read-write - FCMD_OCT - Set this bit to enable 8-bit-mode(8-bm) in CMD phase. - 9 + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 1 read-write - FCS_CRC_EN - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. - 10 + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 1 read-write - TX_CRC_EN - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable - 11 - 1 + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 read-write + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + - FASTRD_MODE - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. - 13 - 1 + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 read-write + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + - FREAD_DUAL - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. - 14 - 1 + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 read-write + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + - RESANDRES - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. - 15 - 1 + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 read-write - Q_POL - The bit is used to set MISO line polarity, 1: high 0, low - 18 - 1 + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 read-write + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x00140012 + - D_POL - The bit is used to set MOSI line polarity, 1: high 0, low - 19 - 1 + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 read-write - FREAD_QUAD - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. - 20 - 1 + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 read-write - WP - Write protect signal output when SPI is idle. 1: output high, 0: output low. - 21 - 1 + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 10 read-write - WRSR_2B - Two bytes data will be written to status register when it is set. 1: enable 0: disable. - 22 - 1 + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 17 + 10 read-write - FREAD_DIO - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. - 23 + MEM_FORCE_PD + Set this bit to force power down UART memory. + 27 1 read-write - FREAD_QIO - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. - 24 + MEM_FORCE_PU + Set this bit to force power up UART memory. + 28 1 read-write - CTRL1 - SPI1 control1 register - 0xC + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 0x20 - 0x00000FFC - CLK_MODE - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. 0 - 2 - read-write + 10 + read-only - CS_HOLD_DLY_RES - After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. - 2 + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 10 - read-write + read-only - CTRL2 - SPI1 control2 register - 0x10 + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 0x20 + 0x00100200 - SYNC_RESET - The FSM will be reset. - 31 - 1 - read-write + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 11 + 10 + read-only - CLOCK - SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. - 0x14 + FSM_STATUS + UART transmit and receive status. + 0x6C 0x20 - 0x00030103 - CLKCNT_L - It must equal to the value of SPI_MEM_CLKCNT_N. + ST_URX_OUT + This is the status register of receiver. 0 - 8 - read-write + 4 + read-only - CLKCNT_H - It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). - 8 - 8 - read-write + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + - CLKCNT_N - When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) - 16 - 8 - read-write + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + - CLK_EQU_SYSCLK - When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. - 31 - 1 - read-write + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only - USER - SPI1 user register. - 0x18 + CLK_CONF + UART core clock configuration + 0x78 0x20 - 0x80000000 + 0x03701000 - CK_OUT_EDGE - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. - 9 - 1 + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 read-write - FWRITE_DUAL - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. 12 - 1 + 8 read-write - FWRITE_QUAD - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. - 13 - 1 + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 read-write - FWRITE_DIO - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. - 14 + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 1 read-write - FWRITE_QIO - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. - 15 + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 1 read-write - USR_MISO_HIGHPART - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + TX_SCLK_EN + Set this bit to enable UART Tx clock. 24 1 read-write - USR_MOSI_HIGHPART - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + RX_SCLK_EN + Set this bit to enable UART Rx clock. 25 1 read-write - USR_DUMMY_IDLE - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. 26 1 read-write - USR_MOSI - Set this bit to enable the DOUT phase of an write-data operation. + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. 27 1 read-write + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + - USR_MISO - Set this bit to enable enable the DIN phase of a read-data operation. - 28 - 1 + DATE + This is the version register. + 0 + 32 read-write + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + - USR_DUMMY - Set this bit to enable enable the DUMMY phase of an operation. - 29 - 1 + ID + This register is used to configure the uart_id. + 0 + 30 read-write - USR_ADDR - Set this bit to enable enable the ADDR phase of an operation. + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. 30 1 read-write - USR_COMMAND - Set this bit to enable enable the CMD phase of an operation. + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. 31 1 read-write + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x60010000 + + UART1 + 28 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + 0x6002E000 + + UART2 + 29 + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x60014000 + + 0x0 + 0x88 + registers + + + UHCI0 + 14 + + - USER1 - SPI1 user1 register. - 0x1C - 0x20 - 0x5C000007 - - - USR_DUMMY_CYCLELEN - The SPI_CLK cycle length minus 1 of DUMMY phase. - 0 - 6 - read-write - - - USR_ADDR_BITLEN - The length in bits of ADDR phase. The register value shall be (bit_num-1). - 26 - 6 - read-write - - - - - USER2 - SPI1 user2 register. - 0x20 + CONF0 + UHCI configuration register + 0x0 0x20 - 0x70000000 + 0x000006E0 - USR_COMMAND_VALUE - The value of user defined(USR) command. + TX_RST + Write 1, then write 0 to this bit to reset decode state machine. 0 - 16 + 1 read-write - USR_COMMAND_BITLEN - The length in bits of CMD phase. The register value shall be (bit_num-1) - 28 - 4 + RX_RST + Write 1, then write 0 to this bit to reset encode state machine. + 1 + 1 read-write - - - - MOSI_DLEN - SPI1 write-data bit length register. - 0x24 - 0x20 - - USR_MOSI_DBITLEN - The length in bits of DOUT phase. The register value shall be (bit_num-1). - 0 - 10 + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 read-write - - - - MISO_DLEN - SPI1 read-data bit length register. - 0x28 - 0x20 - - USR_MISO_DBITLEN - The length in bits of DIN phase. The register value shall be (bit_num-1). - 0 - 10 + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 read-write - - - - RD_STATUS - SPI1 read control register. - 0x2C - 0x20 - - STATUS - The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. - 0 - 16 + UART2_CE + Set this bit to link up HCI and UART2. + 4 + 1 read-write - WB_MODE - Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. - 16 - 8 + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 read-write - - - - EXT_ADDR - SPI1 extended address register. - 0x30 - 0x20 - - EXT_ADDR - The register are the higher 32bits in the 64 bits address mode. - 0 - 32 + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 read-write - - - - MISC - SPI1 misc register. - 0x34 - 0x20 - 0x00000002 - - CS0_DIS - Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. - 0 + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 1 read-write - CS1_DIS - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. - 1 + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 8 1 read-write - CK_IDLE_EDGE - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + LEN_EOF_EN + If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. 9 1 read-write - CS_KEEP_ACTIVE - SPI_CS line keep low when the bit is set. + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. 10 1 read-write - AUTO_PER - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. 11 1 read-write + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + - TX_CRC - SPI1 CRC data register. - 0x38 + INT_RAW + Raw interrupt status + 0x4 0x20 - 0xFFFFFFFF - DATA - For SPI1, the value of crc32. + RX_START_INT_RAW + This is the interrupt raw bit. Triggered when a separator char has been sent. 0 - 32 - read-only + 1 + read-write - - - - CACHE_FCTRL - SPI1 bit mode control register. - 0x3C - 0x20 - - CACHE_USR_CMD_4BYTE - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + TX_START_INT_RAW + This is the interrupt raw bit. Triggered when UHCI detects a separator char. 1 1 read-write - FDIN_DUAL - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + RX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. 3 1 read-write - FDOUT_DUAL - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + SEND_S_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. 4 1 read-write - FADDR_DUAL - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + SEND_A_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. 5 1 read-write - FDIN_QUAD - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. 6 1 read-write - FDOUT_QUAD - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + APP_CTRL0_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. 7 1 read-write - FADDR_QUAD - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + APP_CTRL1_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. 8 1 read-write @@ -45906,801 +57266,631 @@ Any pulses with width less than this will be ignored when the filter is enabled. - FSM - SPI1 state machine(FSM) status register. - 0x54 + INT_ST + Masked interrupt status + 0x8 0x20 - ST - The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + RX_START_INT_ST + This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. 0 - 3 + 1 read-only - - - - W0 - SPI1 memory data buffer0 - 0x58 - 0x20 - - BUF0 - data buffer - 0 - 32 - read-write + TX_START_INT_ST + This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + 1 + 1 + read-only - - - - W1 - SPI1 memory data buffer1 - 0x5C - 0x20 - - BUF1 - data buffer - 0 - 32 - read-write + RX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + 2 + 1 + read-only - - - - W2 - SPI1 memory data buffer2 - 0x60 - 0x20 - - BUF2 - data buffer - 0 - 32 - read-write + TX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + 3 + 1 + read-only - - - - W3 - SPI1 memory data buffer3 - 0x64 - 0x20 - - BUF3 - data buffer - 0 - 32 - read-write + SEND_S_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. + 4 + 1 + read-only - - - - W4 - SPI1 memory data buffer4 - 0x68 - 0x20 - - BUF4 - data buffer - 0 - 32 - read-write + SEND_A_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. + 5 + 1 + read-only - - - - W5 - SPI1 memory data buffer5 - 0x6C - 0x20 - - BUF5 - data buffer - 0 - 32 - read-write + OUTLINK_EOF_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + 6 + 1 + read-only - - - - W6 - SPI1 memory data buffer6 - 0x70 - 0x20 - - BUF6 - data buffer - 0 - 32 - read-write + APP_CTRL0_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. + 8 + 1 + read-only - W7 - SPI1 memory data buffer7 - 0x74 + INT_ENA + Interrupt enable bits + 0xC 0x20 - BUF7 - data buffer + RX_START_INT_ENA + This is the interrupt enable bit for UHCI_RX_START_INT interrupt. 0 - 32 + 1 read-write - - - - W8 - SPI1 memory data buffer8 - 0x78 - 0x20 - - BUF8 - data buffer - 0 - 32 + TX_START_INT_ENA + This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + 1 + 1 read-write - - - - W9 - SPI1 memory data buffer9 - 0x7C - 0x20 - - BUF9 - data buffer - 0 - 32 + RX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + 2 + 1 read-write - - - - W10 - SPI1 memory data buffer10 - 0x80 - 0x20 - - BUF10 - data buffer - 0 - 32 + TX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + 3 + 1 read-write - - - - W11 - SPI1 memory data buffer11 - 0x84 - 0x20 - - BUF11 - data buffer - 0 - 32 + SEND_S_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 read-write - - - - W12 - SPI1 memory data buffer12 - 0x88 - 0x20 - - BUF12 - data buffer - 0 - 32 + SEND_A_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 read-write - - - - W13 - SPI1 memory data buffer13 - 0x8C - 0x20 - - BUF13 - data buffer - 0 - 32 + OUTLINK_EOF_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 read-write - - - - W14 - SPI1 memory data buffer14 - 0x90 - 0x20 - - BUF14 - data buffer - 0 - 32 + APP_CTRL0_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. + 7 + 1 read-write - - - - W15 - SPI1 memory data buffer15 - 0x94 - 0x20 - - BUF15 - data buffer - 0 - 32 + APP_CTRL1_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + 8 + 1 read-write - FLASH_WAITI_CTRL - SPI1 wait idle control register - 0x98 + INT_CLR + Interrupt clear bits + 0x10 0x20 - 0x00000014 - WAITI_EN - Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + RX_START_INT_CLR + Set this bit to clear UHCI_RX_START_INT interrupt. 0 1 - read-write + write-only - WAITI_DUMMY - Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + TX_START_INT_CLR + Set this bit to clear UHCI_TX_START_INT interrupt. 1 1 - read-write + write-only - WAITI_CMD - The command value of auto wait flash idle transfer(RDSR). + RX_HUNG_INT_CLR + Set this bit to clear UHCI_RX_HUNG_INT interrupt. 2 - 8 - read-write - - - WAITI_DUMMY_CYCLELEN - The dummy cycle length when wait flash idle(RDSR). - 10 - 6 - read-write + 1 + write-only - - - - FLASH_SUS_CMD - SPI1 flash suspend control register - 0x9C - 0x20 - - FLASH_PER - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 0 + TX_HUNG_INT_CLR + Set this bit to clear UHCI_TX_HUNG_INT interrupt. + 3 1 - read-write + write-only - FLASH_PES - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 1 + SEND_S_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. + 4 1 - read-write + write-only - FLASH_PER_WAIT_EN - Set this bit to add delay time after program erase resume(PER) is sent. - 2 + SEND_A_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. + 5 1 - read-write + write-only - FLASH_PES_WAIT_EN - Set this bit to add delay time after program erase suspend(PES) command is sent. - 3 + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 1 - read-write + write-only - PES_PER_EN - Set this bit to enable PES transfer trigger PES transfer option. - 4 + APP_CTRL0_INT_CLR + Set this bit to clear UHCI_APP_CTRL0_INT interrupt. + 7 1 - read-write + write-only - PESR_IDLE_EN - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. - 5 + APP_CTRL1_INT_CLR + Set this bit to clear UHCI_APP_CTRL1_INT interrupt. + 8 1 - read-write + write-only - FLASH_SUS_CTRL - SPI1 flash suspend command register - 0xA0 + APP_INT_SET + Software interrupt trigger source + 0x14 0x20 - 0x0000EAF4 - FLASH_PES_EN - Set this bit to enable auto-suspend function. + APP_CTRL0_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. 0 1 - read-write + write-only - FLASH_PER_COMMAND - Program/Erase resume command value. + APP_CTRL1_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. 1 - 8 - read-write - - - FLASH_PES_COMMAND - Program/Erase suspend command value. - 9 - 8 - read-write + 1 + write-only - SUS_STATUS - SPI1 flash suspend status register - 0xA4 + CONF1 + UHCI configuration register + 0x18 0x20 + 0x00000033 - FLASH_SUS - The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + CHECK_SUM_EN + This is the enable bit to check header checksum when UHCI receives a data packet. 0 1 read-write - FLASH_HPM_DLY_256 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + CHECK_SEQ_EN + This is the enable bit to check sequence number when UHCI receives a data packet. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. 2 1 read-write - FLASH_RES_DLY_256 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + SAVE_HEAD + Set this bit to save the packet header when HCI receives a data packet. 3 1 read-write - FLASH_DP_DLY_256 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + TX_CHECK_SUM_RE + Set this bit to encode the data packet with a checksum. 4 1 read-write - FLASH_PER_DLY_256 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. - 5 + TX_ACK_NUM_RE + Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. + 5 + 1 + read-write + + + WAIT_SW_START + The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. + 7 1 read-write - FLASH_PES_DLY_256 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. - 6 + SW_START + If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. + 8 1 read-write - TIMING_CALI - SPI1 timing compensation register when accesses to flash or Ext_RAM. - 0xA8 + STATE0 + UHCI receive status + 0x1C 0x20 - TIMING_CALI - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. - 1 - 1 - read-write + RX_ERR_CAUSE + This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error. + 0 + 3 + read-only - EXTRA_DUMMY_CYCLELEN - Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. - 2 + DECODE_STATE + UHCI decoder status. + 3 3 - read-write + read-only - DDR - SPI1 DDR control register - 0xE0 + STATE1 + UHCI transmit status + 0x20 0x20 - 0x00000020 - SPI_FMEM_DDR_EN - 1: in DDR mode, 0: in SDR mode. + ENCODE_STATE + UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + Escape character configuration + 0x24 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable decoding char 0xc0 when DMA receives data. 0 1 read-write - SPI_FMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in DDRmode. + TX_DB_ESC_EN + Set this bit to enable decoding char 0xdb when DMA receives data. 1 1 read-write - SPI_FMEM_DDR_RDAT_SWP - Set the bit to reorder RX data of the word in DDR mode. + TX_11_ESC_EN + Set this bit to enable decoding flow control char 0x11 when DMA receives data. 2 1 read-write - SPI_FMEM_DDR_WDAT_SWP - Set the bit to reorder TX data of the word in DDR mode. + TX_13_ESC_EN + Set this bit to enable decoding flow control char 0x13 when DMA receives data. 3 1 read-write - SPI_FMEM_DDR_CMD_DIS - the bit is used to disable dual edge in command phase when DDR mode. + RX_C0_ESC_EN + Set this bit to enable replacing 0xc0 by special char when DMA sends data. 4 1 read-write - SPI_FMEM_OUTMINBYTELEN - It is the minimum output data length in the panda device. + RX_DB_ESC_EN + Set this bit to enable replacing 0xdb by special char when DMA sends data. 5 - 7 + 1 read-write - SPI_FMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI_CLK. - 14 - 7 + RX_11_ESC_EN + Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + 6 + 1 read-write - SPI_FMEM_DDR_DQS_LOOP - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module - 21 + RX_13_ESC_EN + Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. + 7 1 read-write + + + + HUNG_CONF + Timeout configuration + 0x28 + 0x20 + 0x00810810 + - SPI_FMEM_DDR_DQS_LOOP_MODE - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. - 22 - 1 + TXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + 0 + 8 read-write - SPI_FMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 - 1 + TXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 8 + 3 read-write - SPI_FMEM_HYPERBUS_MODE - Set this bit to enable the SPI HyperBus mode. - 25 + TXFIFO_TIMEOUT_ENA + This is the enable bit for Tx-FIFO receive-data timeout. + 11 1 read-write - SPI_FMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 - 1 + RXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + 12 + 8 read-write - SPI_FMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - 27 - 1 + RXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 20 + 3 read-write - SPI_FMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to flash. . - 28 + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send-data timeout. + 23 1 read-write + + + + ACK_NUM + UHCI ACK number configuration + 0x2C + 0x20 + 0x00000008 + - SPI_FMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 - 1 + ACK_NUM + This ACK number used in software flow control. + 0 + 3 read-write - SPI_FMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 + LOAD + Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded. + 3 1 - read-write + write-only - CLOCK_GATE - SPI1 clk_gate register - 0xE8 + RX_HEAD + UHCI packet header register + 0x30 0x20 - 0x00000001 - CLK_EN - Register clock gate enable signal. 1: Enable. 0: Disable. + RX_HEAD + This register stores the header of the current received packet. 0 - 1 - read-write + 32 + read-only - INT_ENA - SPI1 interrupt enable register - 0xF0 + QUICK_SENT + UHCI quick send configuration register + 0x34 0x20 - PER_END_INT_ENA - The enable bit for SPI_MEM_PER_END_INT interrupt. + SINGLE_SEND_NUM + This register is used to specify the single_send register. 0 - 1 + 3 read-write - PES_END_INT_ENA - The enable bit for SPI_MEM_PES_END_INT interrupt. - 1 + SINGLE_SEND_EN + Set this bit to enable single_send mode to send short packet. + 3 1 read-write - TOTAL_TRANS_END_INT_ENA - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 - 1 + ALWAYS_SEND_NUM + This register is used to specify the always_send register. + 4 + 3 read-write - BROWN_OUT_INT_ENA - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. - 3 + ALWAYS_SEND_EN + Set this bit to enable always_send mode to send short packet. + 7 1 read-write - INT_CLR - SPI1 interrupt clear register - 0xF4 + REG_Q0_WORD0 + Q0_WORD0 quick_sent register + 0x38 0x20 - PER_END_INT_CLR - The clear bit for SPI_MEM_PER_END_INT interrupt. + SEND_Q0_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 - 1 - write-only - - - PES_END_INT_CLR - The clear bit for SPI_MEM_PES_END_INT interrupt. - 1 - 1 - write-only - - - TOTAL_TRANS_END_INT_CLR - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 - 1 - write-only - - - BROWN_OUT_INT_CLR - The status bit for SPI_MEM_BROWN_OUT_INT interrupt. - 3 - 1 - write-only + 32 + read-write - INT_RAW - SPI1 interrupt raw register - 0xF8 + REG_Q0_WORD1 + Q0_WORD1 quick_sent register + 0x3C 0x20 - PER_END_INT_RAW - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + SEND_Q0_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 - 1 - read-only - - - PES_END_INT_RAW - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. - 1 - 1 - read-only - - - TOTAL_TRANS_END_INT_RAW - The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. - 2 - 1 - read-only - - - BROWN_OUT_INT_RAW - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. - 3 - 1 - read-only + 32 + read-write - INT_ST - SPI1 interrupt status register - 0xFC + REG_Q1_WORD0 + Q1_WORD0 quick_sent register + 0x40 0x20 - PER_END_INT_ST - The status bit for SPI_MEM_PER_END_INT interrupt. + SEND_Q1_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 - 1 - read-only - - - PES_END_INT_ST - The status bit for SPI_MEM_PES_END_INT interrupt. - 1 - 1 - read-only - - - TOTAL_TRANS_END_INT_ST - The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - 2 - 1 - read-only - - - BROWN_OUT_INT_ST - The status bit for SPI_MEM_BROWN_OUT_INT interrupt. - 3 - 1 - read-only + 32 + read-write - DATE - SPI0 version control register - 0x3FC + REG_Q1_WORD1 + Q1_WORD1 quick_sent register + 0x44 0x20 - 0x02101040 - DATE - SPI register version. + SEND_Q1_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 - 28 + 32 read-write - - - - SPI2 - SPI (Serial Peripheral Interface) Controller - SPI2 - 0x60024000 - - 0x0 - 0x98 - registers - - - SPI2 - 21 - - - CMD - Command control register - 0x0 + REG_Q2_WORD0 + Q2_WORD0 quick_sent register + 0x48 0x20 - CONF_BITLEN - Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + SEND_Q2_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 - 18 - read-write - - - UPDATE - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. - 23 - 1 + 32 read-write + + + + REG_Q2_WORD1 + Q2_WORD1 quick_sent register + 0x4C + 0x20 + - USR - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. - 24 - 1 + SEND_Q2_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write - ADDR - Address value register - 0x4 + REG_Q3_WORD0 + Q3_WORD0 quick_sent register + 0x50 0x20 - USR_ADDR_VALUE - Address to slave. Can be configured in CONF state. + SEND_Q3_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write @@ -46708,1769 +57898,2092 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CTRL - SPI control register - 0x8 + REG_Q3_WORD1 + Q3_WORD1 quick_sent register + 0x54 0x20 - 0x003C0000 - DUMMY_OUT - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. - 3 - 1 + SEND_Q3_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + REG_Q4_WORD0 + Q4_WORD0 quick_sent register + 0x58 + 0x20 + - FADDR_DUAL - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 5 - 1 + SEND_Q4_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + REG_Q4_WORD1 + Q4_WORD1 quick_sent register + 0x5C + 0x20 + - FADDR_QUAD - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 6 - 1 + SEND_Q4_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + REG_Q5_WORD0 + Q5_WORD0 quick_sent register + 0x60 + 0x20 + - FADDR_OCT - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 7 - 1 + SEND_Q5_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + REG_Q5_WORD1 + Q5_WORD1 quick_sent register + 0x64 + 0x20 + - FCMD_DUAL - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 8 - 1 + SEND_Q5_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + REG_Q6_WORD0 + Q6_WORD0 quick_sent register + 0x68 + 0x20 + - FCMD_QUAD - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 9 - 1 + SEND_Q6_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write - - FCMD_OCT - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 10 - 1 + + + + REG_Q6_WORD1 + Q6_WORD1 quick_sent register + 0x6C + 0x20 + + + SEND_Q6_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 read-write + + + + ESC_CONF0 + Escape sequence configuration register 0 + 0x70 + 0x20 + 0x00DCDBC0 + - FREAD_DUAL - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. - 14 - 1 + SEPER_CHAR + This register is used to define the separate char that need to be encoded, default is 0xc0. + 0 + 8 read-write - FREAD_QUAD - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. - 15 - 1 + SEPER_ESC_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb. + 8 + 8 read-write - FREAD_OCT - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + SEPER_ESC_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc. 16 - 1 + 8 read-write + + + + ESC_CONF1 + Escape sequence configuration register 1 + 0x74 + 0x20 + 0x00DDDBDB + - Q_POL - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. - 18 - 1 + ESC_SEQ0 + This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence. + 0 + 8 read-write - D_POL - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. - 19 - 1 + ESC_SEQ0_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb. + 8 + 8 read-write - HOLD_POL - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 20 - 1 + ESC_SEQ0_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd. + 16 + 8 read-write + + + + ESC_CONF2 + Escape sequence configuration register 2 + 0x78 + 0x20 + 0x00DEDB11 + - WP_POL - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 21 - 1 + ESC_SEQ1 + This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char. + 0 + 8 read-write - RD_BIT_ORDER - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. - 23 - 2 + ESC_SEQ1_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb. + 8 + 8 read-write - WR_BIT_ORDER - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. - 25 - 2 + ESC_SEQ1_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde. + 16 + 8 read-write - CLOCK - SPI clock control register - 0xC + ESC_CONF3 + Escape sequence configuration register 3 + 0x7C 0x20 - 0x80003043 + 0x00DFDB13 - CLKCNT_L - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + ESC_SEQ2 + This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char. 0 - 6 + 8 read-write - CLKCNT_H - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. - 6 - 6 + ESC_SEQ2_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb. + 8 + 8 read-write - CLKCNT_N - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. - 12 - 6 + ESC_SEQ2_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf. + 16 + 8 read-write + + + + PKT_THRES + Configure register for packet length + 0x80 + 0x20 + 0x00000080 + - CLKDIV_PRE - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. - 18 - 4 + PKT_THRS + This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + 0 + 13 read-write + + + + DATE + UHCI version control register + 0x84 + 0x20 + 0x02010090 + - CLK_EQU_SYSCLK - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. - 31 - 1 + DATE + This is the version control register. + 0 + 32 read-write + + + + UHCI1 + Universal Host Controller Interface 1 + 0x6000C000 + + UHCI1 + 15 + + + + USB0 + USB OTG (On-The-Go) + USB + 0x60080000 + + 0x0 + 0x2A0 + registers + + + USB + 38 + + - USER - SPI USER control register - 0x10 + GOTGCTL + 0x0 0x20 - 0x800000C0 - DOUTDIN - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + SESREQSCS 0 1 + read-only + + + SESREQ + 1 + 1 read-write - QPI_MODE - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + VBVALIDOVEN + 2 + 1 + read-write + + + VBVALIDOVVAL 3 1 read-write - OPI_MODE - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + AVALIDOVEN 4 1 read-write - TSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + AVALIDOVVAL 5 1 read-write - CS_HOLD - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + BVALIDOVEN 6 1 read-write - CS_SETUP - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + BVALIDOVVAL 7 1 read-write - RSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + HSTNEGSCS 8 1 - read-write + read-only - CK_OUT_EDGE - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + HNPREQ 9 1 read-write - FWRITE_DUAL - In the write operations read-data phase apply 2 signals. Can be configured in CONF state. - 12 + HSTSETHNPEN + 10 1 read-write - FWRITE_QUAD - In the write operations read-data phase apply 4 signals. Can be configured in CONF state. - 13 + DEVHNPEN + 11 1 read-write - FWRITE_OCT - In the write operations read-data phase apply 8 signals. Can be configured in CONF state. - 14 + EHEN + 12 1 read-write - USR_CONF_NXT - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + DBNCEFLTRBYPASS 15 1 read-write - SIO - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. - 17 - 1 - read-write - - - USR_MISO_HIGHPART - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 24 - 1 - read-write - - - USR_MOSI_HIGHPART - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 25 - 1 - read-write - - - USR_DUMMY_IDLE - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. - 26 + CONIDSTS + 16 1 - read-write + read-only - USR_MOSI - This bit enable the write-data phase of an operation. Can be configured in CONF state. - 27 + DBNCTIME + 17 1 - read-write + read-only - USR_MISO - This bit enable the read-data phase of an operation. Can be configured in CONF state. - 28 + ASESVLD + 18 1 - read-write + read-only - USR_DUMMY - This bit enable the dummy phase of an operation. Can be configured in CONF state. - 29 + BSESVLD + 19 1 - read-write + read-only - USR_ADDR - This bit enable the address phase of an operation. Can be configured in CONF state. - 30 + OTGVER + 20 1 read-write - USR_COMMAND - This bit enable the command phase of an operation. Can be configured in CONF state. - 31 + CURMOD + 21 1 - read-write + read-only - USER1 - SPI USER control register 1 - 0x14 + GOTGINT + 0x4 0x20 - 0xB8410007 - USR_DUMMY_CYCLELEN - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. - 0 - 8 - read-write - - - MST_WFULL_ERR_END_EN - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. - 16 + SESENDDET + 2 1 read-write - CS_SETUP_TIME - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. - 17 - 5 - read-write - - - CS_HOLD_TIME - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. - 22 - 5 - read-write - - - USR_ADDR_BITLEN - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 27 - 5 + SESREQSUCSTSCHNG + 8 + 1 read-write - - - - USER2 - SPI USER control register 2 - 0x18 - 0x20 - 0x78000000 - - USR_COMMAND_VALUE - The value of command. Can be configured in CONF state. - 0 - 16 + HSTNEGSUCSTSCHNG + 9 + 1 read-write - MST_REMPTY_ERR_END_EN - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. - 27 + HSTNEGDET + 17 1 read-write - USR_COMMAND_BITLEN - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 28 - 4 + ADEVTOUTCHG + 18 + 1 read-write - - - - MS_DLEN - SPI data bit length control register - 0x1C - 0x20 - - MS_DATA_BITLEN - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. - 0 - 18 + DBNCEDONE + 19 + 1 read-write - MISC - SPI misc register - 0x20 + GAHBCFG + 0x8 0x20 - 0x0000003E - CS0_DIS - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + GLBLLNTRMSK 0 1 read-write - CS1_DIS - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + HBSTLEN 1 - 1 + 4 read-write - CS2_DIS - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. - 2 + DMAEN + 5 1 read-write - CS3_DIS - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. - 3 + NPTXFEMPLVL + 7 1 read-write - CS4_DIS - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. - 4 + PTXFEMPLVL + 8 1 read-write - CS5_DIS - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. - 5 + REMMEMSUPP + 21 1 read-write - CK_DIS - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - 6 + NOTIALLDMAWRIT + 22 1 read-write - MASTER_CS_POL - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - 7 - 6 - read-write - - - CLK_DATA_DTR_EN - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. - 16 + AHBSINGLE + 23 1 read-write - DATA_DTR_EN - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. - 17 + INVDESCENDIANESS + 24 1 read-write + + + + GUSBCFG + 0xC + 0x20 + 0x00001440 + - ADDR_DTR_EN - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. - 18 - 1 + TOUTCAL + 0 + 3 read-write - CMD_DTR_EN - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. - 19 + PHYIF + 3 1 read-write - SLAVE_CS_POL - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. - 23 + ULPI_UTMI_SEL + 4 1 - read-write + read-only - DQS_IDLE_EDGE - The default value of spi_dqs. Can be configured in CONF state. - 24 + FSINTF + 5 1 read-write - CK_IDLE_EDGE - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. - 29 + PHYSEL + 6 1 - read-write + read-only - CS_KEEP_ACTIVE - spi cs line keep low when the bit is set. Can be configured in CONF state. - 30 + SRPCAP + 8 1 read-write - QUAD_DIN_PIN_SWAP - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. - 31 + HNPCAP + 9 1 read-write - - - - DIN_MODE - SPI input delay mode configuration - 0x24 - 0x20 - - - DIN0_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 0 - 2 - read-write - - - DIN1_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 2 - 2 - read-write - - - DIN2_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 4 - 2 - read-write - - DIN3_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 6 - 2 + USBTRDTIM + 10 + 4 read-write - DIN4_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 8 - 2 + TERMSELDLPULSE + 22 + 1 read-write - DIN5_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 10 - 2 + TXENDDELAY + 28 + 1 read-write - DIN6_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 12 - 2 + FORCEHSTMODE + 29 + 1 read-write - DIN7_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 14 - 2 + FORCEDEVMODE + 30 + 1 read-write - TIMING_HCLK_ACTIVE - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. - 16 + CORRUPTTXPKT + 31 1 read-write - - DIN_NUM - SPI input delay number configuration - 0x28 + + GRSTCTL + 0x10 0x20 - DIN0_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + CSFTRST 0 - 2 + 1 read-write - DIN1_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 2 - 2 + PIUFSSFTRST + 1 + 1 read-write - DIN2_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 4 - 2 + FRMCNTRRST + 2 + 1 read-write - DIN3_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 6 - 2 + RXFFLSH + 4 + 1 read-write - DIN4_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 8 - 2 + TXFFLSH + 5 + 1 read-write - DIN5_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 10 - 2 + TXFNUM + 6 + 5 read-write - DIN6_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 12 - 2 - read-write + DMAREQ + 30 + 1 + read-only - DIN7_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 14 - 2 - read-write + AHBIDLE + 31 + 1 + read-only - DOUT_MODE - SPI output delay mode configuration - 0x2C + GINTSTS + 0x14 0x20 - DOUT0_MODE - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + CURMOD_INT 0 1 - read-write + read-only - DOUT1_MODE - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + MODEMIS 1 1 read-write - DOUT2_MODE - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + OTGINT 2 1 - read-write + read-only - DOUT3_MODE - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + SOF 3 1 read-write - DOUT4_MODE - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + RXFLVI 4 1 - read-write + read-only - DOUT5_MODE - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + NPTXFEMP 5 1 - read-write + read-only - DOUT6_MODE - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + GINNAKEFF 6 1 - read-write + read-only - DOUT7_MODE - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + GOUTNAKEFF 7 1 + read-only + + + ERLYSUSP + 10 + 1 read-write - D_DQS_MODE - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 8 + USBSUSP + 11 1 read-write - - - - DMA_CONF - SPI DMA control register - 0x30 - 0x20 - 0x00000003 - - DMA_OUTFIFO_EMPTY - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. - 0 + USBRST + 12 1 - read-only + read-write - DMA_INFIFO_FULL - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. - 1 + ENUMDONE + 13 1 - read-only + read-write - DMA_SLV_SEG_TRANS_EN - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. - 18 + ISOOUTDROP + 14 1 read-write - SLV_RX_SEG_TRANS_CLR_EN - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. - 19 + EOPF + 15 1 read-write - SLV_TX_SEG_TRANS_CLR_EN - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + EPMIS + 17 + 1 + read-write + + + IEPINT + 18 + 1 + read-only + + + OEPINT + 19 + 1 + read-only + + + INCOMPISOIN 20 1 read-write - RX_EOF_EN - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + INCOMPIP 21 1 read-write - DMA_RX_ENA - Set this bit to enable SPI DMA controlled receive data mode. - 27 + FETSUSP + 22 1 read-write - DMA_TX_ENA - Set this bit to enable SPI DMA controlled send data mode. + RESETDET + 23 + 1 + read-write + + + PRTLNT + 24 + 1 + read-only + + + HCHLNT + 25 + 1 + read-only + + + PTXFEMP + 26 + 1 + read-only + + + CONIDSTSCHNG 28 1 read-write - RX_AFIFO_RST - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + DISCONNINT 29 1 - write-only + read-write - BUF_AFIFO_RST - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + SESSREQINT 30 1 - write-only + read-write - DMA_AFIFO_RST - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + WKUPINT 31 1 - write-only + read-write - DMA_INT_ENA - SPI interrupt enable register - 0x34 + GINTMSK + 0x18 0x20 - DMA_INFIFO_FULL_ERR_INT_ENA - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - read-write - - - DMA_OUTFIFO_EMPTY_ERR_INT_ENA - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + MODEMISMSK 1 1 read-write - SLV_EX_QPI_INT_ENA - The enable bit for SPI slave Ex_QPI interrupt. + OTGINTMSK 2 1 read-write - SLV_EN_QPI_INT_ENA - The enable bit for SPI slave En_QPI interrupt. + SOFMSK 3 1 read-write - SLV_CMD7_INT_ENA - The enable bit for SPI slave CMD7 interrupt. + RXFLVIMSK 4 1 read-write - SLV_CMD8_INT_ENA - The enable bit for SPI slave CMD8 interrupt. + NPTXFEMPMSK 5 1 read-write - SLV_CMD9_INT_ENA - The enable bit for SPI slave CMD9 interrupt. + GINNAKEFFMSK 6 1 read-write - SLV_CMDA_INT_ENA - The enable bit for SPI slave CMDA interrupt. + GOUTNACKEFFMSK 7 1 read-write - SLV_RD_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 + ERLYSUSPMSK + 10 1 read-write - SLV_WR_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 + USBSUSPMSK + 11 1 read-write - SLV_RD_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 + USBRSTMSK + 12 1 read-write - SLV_WR_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 + ENUMDONEMSK + 13 1 read-write - TRANS_DONE_INT_ENA - The enable bit for SPI_TRANS_DONE_INT interrupt. - 12 + ISOOUTDROPMSK + 14 1 read-write - DMA_SEG_TRANS_DONE_INT_ENA - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 + EOPFMSK + 15 1 read-write - SEG_MAGIC_ERR_INT_ENA - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 + EPMISMSK + 17 1 read-write - SLV_BUF_ADDR_ERR_INT_ENA - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 + IEPINTMSK + 18 1 read-write - SLV_CMD_ERR_INT_ENA - The enable bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 + OEPINTMSK + 19 1 read-write - MST_RX_AFIFO_WFULL_ERR_INT_ENA - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 + INCOMPISOINMSK + 20 1 read-write - MST_TX_AFIFO_REMPTY_ERR_INT_ENA - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 + INCOMPIPMSK + 21 1 read-write - APP2_INT_ENA - The enable bit for SPI_APP2_INT interrupt. - 19 + FETSUSPMSK + 22 1 read-write - APP1_INT_ENA - The enable bit for SPI_APP1_INT interrupt. - 20 + RESETDETMSK + 23 + 1 + read-write + + + PRTLNTMSK + 24 + 1 + read-write + + + HCHINTMSK + 25 + 1 + read-write + + + PTXFEMPMSK + 26 + 1 + read-write + + + CONIDSTSCHNGMSK + 28 + 1 + read-write + + + DISCONNINTMSK + 29 + 1 + read-write + + + SESSREQINTMSK + 30 + 1 + read-write + + + WKUPINTMSK + 31 1 read-write - DMA_INT_CLR - SPI interrupt clear register - 0x38 + GRXSTSR + 0x1C 0x20 - DMA_INFIFO_FULL_ERR_INT_CLR - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + G_CHNUM 0 - 1 - write-only + 4 + read-only - DMA_OUTFIFO_EMPTY_ERR_INT_CLR - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 + G_BCNT + 4 + 11 + read-only + + + G_DPID + 15 + 2 + read-only + + + G_PKTSTS + 17 + 4 + read-only + + + G_FN + 21 + 4 + read-only + + + + + GRXSTSP + 0x20 + 0x20 + + + CHNUM + 0 + 4 + read-only + + + BCNT + 4 + 11 + read-only + + + DPID + 15 + 2 + read-only + + + PKTSTS + 17 + 4 + read-only + + + FN + 21 + 4 + read-only + + + + + GRXFSIZ + 0x24 + 0x20 + 0x00000100 + + + RXFDEP + 0 + 16 + read-write + + + + + GNPTXFSIZ + 0x28 + 0x20 + 0x01000100 + + + NPTXFSTADDR + 0 + 16 + read-write + + + NPTXFDEP + 16 + 16 + read-write + + + + + GNPTXSTS + 0x2C + 0x20 + 0x00040100 + + + NPTXFSPCAVAIL + 0 + 16 + read-only + + + NPTXQSPCAVAIL + 16 + 4 + read-only + + + NPTXQTOP + 24 + 7 + read-only + + + + + GSNPSID + 0x40 + 0x20 + 0x4F54400A + + + SYNOPSYSID + 0 + 32 + read-only + + + + + GHWCFG1 + 0x44 + 0x20 + + + EPDIR + 0 + 32 + read-only + + + + + GHWCFG2 + 0x48 + 0x20 + 0x224DD930 + + + OTGMODE + 0 + 3 + read-only + + + OTGARCH + 3 + 2 + read-only + + + SINGPNT + 5 1 - write-only + read-only - SLV_EX_QPI_INT_CLR - The clear bit for SPI slave Ex_QPI interrupt. - 2 + HSPHYTYPE + 6 + 2 + read-only + + + FSPHYTYPE + 8 + 2 + read-only + + + NUMDEVEPS + 10 + 4 + read-only + + + NUMHSTCHNL + 14 + 4 + read-only + + + PERIOSUPPORT + 18 1 - write-only + read-only - SLV_EN_QPI_INT_CLR - The clear bit for SPI slave En_QPI interrupt. - 3 + DYNFIFOSIZING + 19 1 - write-only + read-only - SLV_CMD7_INT_CLR - The clear bit for SPI slave CMD7 interrupt. - 4 + MULTIPROCINTRPT + 20 1 - write-only + read-only - SLV_CMD8_INT_CLR - The clear bit for SPI slave CMD8 interrupt. - 5 + NPTXQDEPTH + 22 + 2 + read-only + + + PTXQDEPTH + 24 + 2 + read-only + + + TKNQDEPTH + 26 + 5 + read-only + + + OTG_ENABLE_IC_USB + 31 1 - write-only + read-only + + + + + GHWCFG3 + 0x4C + 0x20 + 0x010004B5 + + + XFERSIZEWIDTH + 0 + 4 + read-only - SLV_CMD9_INT_CLR - The clear bit for SPI slave CMD9 interrupt. - 6 - 1 - write-only + PKTSIZEWIDTH + 4 + 3 + read-only - SLV_CMDA_INT_CLR - The clear bit for SPI slave CMDA interrupt. + OTGEN 7 1 - write-only + read-only - SLV_RD_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + I2CINTSEL 8 1 - write-only + read-only - SLV_WR_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + VNDCTLSUPT 9 1 - write-only + read-only - SLV_RD_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + OPTFEATURE 10 1 - write-only + read-only - SLV_WR_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + RSTTYPE 11 1 - write-only + read-only - TRANS_DONE_INT_CLR - The clear bit for SPI_TRANS_DONE_INT interrupt. + ADPSUPPORT 12 1 - write-only + read-only - DMA_SEG_TRANS_DONE_INT_CLR - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + HSICMODE 13 1 - write-only + read-only - SEG_MAGIC_ERR_INT_CLR - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + BCSUPPORT 14 1 - write-only + read-only - SLV_BUF_ADDR_ERR_INT_CLR - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + LPMMODE 15 1 - write-only + read-only - SLV_CMD_ERR_INT_CLR - The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + DFIFODEPTH 16 - 1 - write-only + 16 + read-only + + + + GHWCFG4 + 0x50 + 0x20 + 0xD3F0A030 + - MST_RX_AFIFO_WFULL_ERR_INT_CLR - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - write-only + G_NUMDEVPERIOEPS + 0 + 4 + read-only - MST_TX_AFIFO_REMPTY_ERR_INT_CLR - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 + G_PARTIALPWRDN + 4 1 - write-only + read-only - APP2_INT_CLR - The clear bit for SPI_APP2_INT interrupt. - 19 + G_AHBFREQ + 5 1 - write-only + read-only - APP1_INT_CLR - The clear bit for SPI_APP1_INT interrupt. - 20 + G_HIBERNATION + 6 1 - write-only + read-only - - - - DMA_INT_RAW - SPI interrupt raw register - 0x3C - 0x20 - - DMA_INFIFO_FULL_ERR_INT_RAW - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. - 0 + G_EXTENDEDHIBERNATION + 7 1 read-only - DMA_OUTFIFO_EMPTY_ERR_INT_RAW - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. - 1 + G_ACGSUPT + 12 1 read-only - SLV_EX_QPI_INT_RAW - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. - 2 + G_ENHANCEDLPMSUPT + 13 1 read-only - SLV_EN_QPI_INT_RAW - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. - 3 - 1 + G_PHYDATAWIDTH + 14 + 2 read-only - SLV_CMD7_INT_RAW - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. - 4 - 1 + G_NUMCTLEPS + 16 + 4 read-only - SLV_CMD8_INT_RAW - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. - 5 + G_IDDQFLTR + 20 1 read-only - SLV_CMD9_INT_RAW - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. - 6 + G_VBUSVALIDFLTR + 21 1 read-only - SLV_CMDA_INT_RAW - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. - 7 + G_AVALIDFLTR + 22 1 read-only - SLV_RD_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. - 8 + G_BVALIDFLTR + 23 1 read-only - SLV_WR_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. - 9 + G_SESSENDFLTR + 24 1 read-only - SLV_RD_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. - 10 + G_DEDFIFOMODE + 25 1 read-only - SLV_WR_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. - 11 - 1 + G_INEPS + 26 + 4 read-only - TRANS_DONE_INT_RAW - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. - 12 + G_DESCDMAENABLED + 30 1 read-only - DMA_SEG_TRANS_DONE_INT_RAW - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. - 13 + G_DESCDMA + 31 1 read-only + + + + GDFIFOCFG + 0x5C + 0x20 + + + GDFIFOCFG + 0 + 16 + read-write + - SEG_MAGIC_ERR_INT_RAW - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. - 14 + EPINFOBASEADDR + 16 + 16 + read-write + + + + + HPTXFSIZ + 0x100 + 0x20 + 0x10000200 + + + PTXFSTADDR + 0 + 16 + read-write + + + PTXFSIZE + 16 + 16 + read-write + + + + + DIEPTXF1 + 0x104 + 0x20 + 0x10000200 + + + INEP1TXFSTADDR + 0 + 16 + read-write + + + INEP1TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF2 + 0x108 + 0x20 + 0x10000200 + + + INEP2TXFSTADDR + 0 + 16 + read-write + + + INEP2TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF3 + 0x10C + 0x20 + 0x10000200 + + + INEP3TXFSTADDR + 0 + 16 + read-write + + + INEP3TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF4 + 0x110 + 0x20 + 0x10000200 + + + INEP4TXFSTADDR + 0 + 16 + read-write + + + INEP4TXFDEP + 16 + 16 + read-write + + + + + HCFG + 0x400 + 0x20 + + + H_FSLSPCLKSEL + 0 + 2 + read-write + + + H_FSLSSUPP + 2 1 - read-only + read-write - SLV_BUF_ADDR_ERR_INT_RAW - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. - 15 + H_ENA32KHZS + 7 1 - read-only + read-write - SLV_CMD_ERR_INT_RAW - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + H_DESCDMA + 23 + 1 + read-write + + + H_FRLISTEN + 24 + 2 + read-write + + + H_PERSCHEDENA + 26 + 1 + read-write + + + H_MODECHTIMEN + 31 + 1 + read-write + + + + + HFIR + 0x404 + 0x20 + 0x000017D7 + + + FRINT + 0 + 16 + read-write + + + HFIRRLDCTRL 16 1 + read-write + + + + + HFNUM + 0x408 + 0x20 + 0x00003FFF + + + FRNUM + 0 + 14 read-only - MST_RX_AFIFO_WFULL_ERR_INT_RAW - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. - 17 - 1 + FRREM + 16 + 16 read-only + + + + HPTXSTS + 0x410 + 0x20 + 0x00080100 + - MST_TX_AFIFO_REMPTY_ERR_INT_RAW - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. - 18 - 1 + PTXFSPCAVAIL + 0 + 16 read-only - APP2_INT_RAW - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. - 19 - 1 + PTXQSPCAVAIL + 16 + 5 read-only - APP1_INT_RAW - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. - 20 - 1 + PTXQTOP + 24 + 8 read-only - DMA_INT_ST - SPI interrupt status register - 0x40 + HAINT + 0x414 0x20 - DMA_INFIFO_FULL_ERR_INT_ST - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + HAINT + 0 + 8 + read-only + + + + + HAINTMSK + 0x418 + 0x20 + + + HAINTMSK + 0 + 8 + read-write + + + + + HFLBADDR + 0x41C + 0x20 + + + HFLBADDR + 0 + 32 + read-write + + + + + HPRT + 0x440 + 0x20 + + + PRTCONNSTS 0 1 read-only - DMA_OUTFIFO_EMPTY_ERR_INT_ST - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + PRTCONNDET 1 1 - read-only + read-write - SLV_EX_QPI_INT_ST - The status bit for SPI slave Ex_QPI interrupt. + PRTENA 2 1 - read-only + read-write - SLV_EN_QPI_INT_ST - The status bit for SPI slave En_QPI interrupt. + PRTENCHNG 3 1 - read-only + read-write - SLV_CMD7_INT_ST - The status bit for SPI slave CMD7 interrupt. + PRTOVRCURRACT 4 1 read-only - SLV_CMD8_INT_ST - The status bit for SPI slave CMD8 interrupt. + PRTOVRCURRCHNG 5 1 - read-only + read-write - SLV_CMD9_INT_ST - The status bit for SPI slave CMD9 interrupt. + PRTRES 6 1 - read-only + read-write - SLV_CMDA_INT_ST - The status bit for SPI slave CMDA interrupt. + PRTSUSP 7 1 - read-only + read-write - SLV_RD_DMA_DONE_INT_ST - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + PRTRST 8 1 - read-only + read-write - SLV_WR_DMA_DONE_INT_ST - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 + PRTLNSTS + 10 + 2 read-only - SLV_RD_BUF_DONE_INT_ST - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 + PRTPWR + 12 1 - read-only + read-write - SLV_WR_BUF_DONE_INT_ST - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - read-only + PRTTSTCTL + 13 + 4 + read-write - TRANS_DONE_INT_ST - The status bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 + PRTSPD + 17 + 2 read-only + + + + HCCHAR0 + 0x500 + 0x20 + - DMA_SEG_TRANS_DONE_INT_ST - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - read-only + H_MPS0 + 0 + 11 + read-write - SEG_MAGIC_ERR_INT_ST - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 - 1 - read-only + H_EPNUM0 + 11 + 4 + read-write - SLV_BUF_ADDR_ERR_INT_ST - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + H_EPDIR0 15 1 - read-only + read-write - SLV_CMD_ERR_INT_ST - The status bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 + H_LSPDDEV0 + 17 1 - read-only + read-write - MST_RX_AFIFO_WFULL_ERR_INT_ST - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 + H_EPTYPE0 + 18 + 2 + read-write + + + H_EC0 + 21 1 - read-only + read-write - MST_TX_AFIFO_REMPTY_ERR_INT_ST - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 + H_DEVADDR0 + 22 + 7 + read-write + + + H_ODDFRM0 + 29 1 - read-only + read-write - APP2_INT_ST - The status bit for SPI_APP2_INT interrupt. - 19 + H_CHDIS0 + 30 1 - read-only + read-write - APP1_INT_ST - The status bit for SPI_APP1_INT interrupt. - 20 + H_CHENA0 + 31 1 - read-only + read-write - - DMA_INT_SET - SPI interrupt software set register - 0x44 + + HCINT0 + 0x508 0x20 - DMA_INFIFO_FULL_ERR_INT_SET - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + H_XFERCOMPL0 0 1 - write-only + read-write - DMA_OUTFIFO_EMPTY_ERR_INT_SET - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + H_CHHLTD0 1 1 - write-only + read-write - SLV_EX_QPI_INT_SET - The software set bit for SPI slave Ex_QPI interrupt. + H_AHBERR0 2 1 - write-only + read-write - SLV_EN_QPI_INT_SET - The software set bit for SPI slave En_QPI interrupt. + H_STALL0 3 1 - write-only + read-write - SLV_CMD7_INT_SET - The software set bit for SPI slave CMD7 interrupt. + H_NACK0 4 1 - write-only + read-write - SLV_CMD8_INT_SET - The software set bit for SPI slave CMD8 interrupt. + H_ACK0 5 1 - write-only + read-write - SLV_CMD9_INT_SET - The software set bit for SPI slave CMD9 interrupt. + H_NYET0 6 1 - write-only + read-write - SLV_CMDA_INT_SET - The software set bit for SPI slave CMDA interrupt. + H_XACTERR0 7 1 - write-only + read-write - SLV_RD_DMA_DONE_INT_SET - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + H_BBLERR0 8 1 - write-only + read-write - SLV_WR_DMA_DONE_INT_SET - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + H_FRMOVRUN0 9 1 - write-only + read-write - SLV_RD_BUF_DONE_INT_SET - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + H_DATATGLERR0 10 1 - write-only + read-write - SLV_WR_BUF_DONE_INT_SET - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + H_BNAINTR0 11 1 - write-only + read-write - TRANS_DONE_INT_SET - The software set bit for SPI_TRANS_DONE_INT interrupt. + H_XCS_XACT_ERR0 12 1 - write-only + read-write - DMA_SEG_TRANS_DONE_INT_SET - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + H_DESC_LST_ROLLINTR0 13 1 - write-only + read-write + + + + HCINTMSK0 + 0x50C + 0x20 + - SEG_MAGIC_ERR_INT_SET - The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 + H_XFERCOMPLMSK0 + 0 1 - write-only + read-write - SLV_BUF_ADDR_ERR_INT_SET - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 + H_CHHLTDMSK0 + 1 1 - write-only + read-write - SLV_CMD_ERR_INT_SET - The software set bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 + H_AHBERRMSK0 + 2 1 - write-only + read-write - MST_RX_AFIFO_WFULL_ERR_INT_SET - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 + H_STALLMSK0 + 3 1 - write-only + read-write - MST_TX_AFIFO_REMPTY_ERR_INT_SET - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 + H_NAKMSK0 + 4 1 - write-only + read-write - APP2_INT_SET - The software set bit for SPI_APP2_INT interrupt. - 19 + H_ACKMSK0 + 5 1 - write-only + read-write - APP1_INT_SET - The software set bit for SPI_APP1_INT interrupt. - 20 + H_NYETMSK0 + 6 1 - write-only + read-write - - - - W0 - SPI CPU-controlled buffer0 - 0x98 - 0x20 - - BUF0 - data buffer - 0 - 32 + H_XACTERRMSK0 + 7 + 1 read-write - - - - W1 - SPI CPU-controlled buffer1 - 0x9C - 0x20 - - BUF1 - data buffer - 0 - 32 + H_BBLERRMSK0 + 8 + 1 read-write - - - - W2 - SPI CPU-controlled buffer2 - 0xA0 - 0x20 - - BUF2 - data buffer - 0 - 32 + H_FRMOVRUNMSK0 + 9 + 1 read-write - - - - W3 - SPI CPU-controlled buffer3 - 0xA4 - 0x20 - - BUF3 - data buffer - 0 - 32 + H_DATATGLERRMSK0 + 10 + 1 read-write - - - - W4 - SPI CPU-controlled buffer4 - 0xA8 - 0x20 - - BUF4 - data buffer - 0 - 32 + H_BNAINTRMSK0 + 11 + 1 read-write - - - - W5 - SPI CPU-controlled buffer5 - 0xAC - 0x20 - - BUF5 - data buffer - 0 - 32 + H_DESC_LST_ROLLINTRMSK0 + 13 + 1 read-write - W6 - SPI CPU-controlled buffer6 - 0xB0 + HCTSIZ0 + 0x510 0x20 - BUF6 - data buffer + H_XFERSIZE0 0 - 32 + 19 read-write - - - - W7 - SPI CPU-controlled buffer7 - 0xB4 - 0x20 - - BUF7 - data buffer - 0 - 32 + H_PKTCNT0 + 19 + 10 read-write - - - - W8 - SPI CPU-controlled buffer8 - 0xB8 - 0x20 - - BUF8 - data buffer - 0 - 32 + H_PID0 + 29 + 2 read-write - - - - W9 - SPI CPU-controlled buffer9 - 0xBC - 0x20 - - BUF9 - data buffer - 0 - 32 + H_DOPNG0 + 31 + 1 read-write - W10 - SPI CPU-controlled buffer10 - 0xC0 + HCDMA0 + 0x514 0x20 - BUF10 - data buffer + H_DMAADDR0 0 32 read-write @@ -48478,301 +59991,299 @@ Any pulses with width less than this will be ignored when the filter is enabled. - W11 - SPI CPU-controlled buffer11 - 0xC4 + HCDMAB0 + 0x51C 0x20 - BUF11 - data buffer + H_HCDMAB0 0 32 - read-write + read-only - W12 - SPI CPU-controlled buffer12 - 0xC8 + HCCHAR1 + 0x520 0x20 - BUF12 - data buffer + H_MPS1 0 - 32 + 11 read-write - - - - W13 - SPI CPU-controlled buffer13 - 0xCC - 0x20 - - BUF13 - data buffer - 0 - 32 + H_EPNUM1 + 11 + 4 read-write - - - - W14 - SPI CPU-controlled buffer14 - 0xD0 - 0x20 - - BUF14 - data buffer - 0 - 32 + H_EPDIR1 + 15 + 1 read-write - - - - W15 - SPI CPU-controlled buffer15 - 0xD4 - 0x20 - - BUF15 - data buffer - 0 - 32 + H_LSPDDEV1 + 17 + 1 + read-write + + + H_EPTYPE1 + 18 + 2 + read-write + + + H_EC1 + 21 + 1 + read-write + + + H_DEVADDR1 + 22 + 7 + read-write + + + H_ODDFRM1 + 29 + 1 + read-write + + + H_CHDIS1 + 30 + 1 + read-write + + + H_CHENA1 + 31 + 1 read-write - SLAVE - SPI slave control register - 0xE0 + HCINT1 + 0x528 0x20 - 0x02800000 - CLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + H_XFERCOMPL1 0 - 2 + 1 read-write - CLK_MODE_13 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. - 2 + H_CHHLTD1 + 1 1 read-write - RSCK_DATA_OUT - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge - 3 + H_AHBERR1 + 2 1 read-write - SLV_RDDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others - 8 + H_STALL1 + 3 1 read-write - SLV_WRDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others - 9 + H_NACK1 + 4 1 read-write - SLV_RDBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others - 10 + H_ACK1 + 5 1 read-write - SLV_WRBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others - 11 + H_NYET1 + 6 1 read-write - DMA_SEG_MAGIC_VALUE - The magic value of BM table in master DMA seg-trans. - 22 - 4 + H_XACTERR1 + 7 + 1 read-write - MODE - Set SPI work mode. 1: slave mode 0: master mode. - 26 + H_BBLERR1 + 8 1 read-write - SOFT_RESET - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. - 27 + H_FRMOVRUN1 + 9 1 - write-only + read-write - USR_CONF - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. - 28 + H_DATATGLERR1 + 10 1 read-write - - - - SLAVE1 - SPI slave control register 1 - 0xE4 - 0x20 - - SLV_DATA_BITLEN - The transferred data bit length in SPI slave FD and HD mode. - 0 - 18 + H_BNAINTR1 + 11 + 1 read-write - SLV_LAST_COMMAND - In the slave mode it is the value of command. - 18 - 8 + H_XCS_XACT_ERR1 + 12 + 1 read-write - SLV_LAST_ADDR - In the slave mode it is the value of address. - 26 - 6 + H_DESC_LST_ROLLINTR1 + 13 + 1 read-write - CLK_GATE - SPI module clock and register clock control - 0xE8 + HCINTMSK1 + 0x52C 0x20 - CLK_EN - Set this bit to enable clk gate + H_XFERCOMPLMSK1 0 1 read-write - MST_CLK_ACTIVE - Set this bit to power on the SPI module clock. + H_CHHLTDMSK1 1 1 read-write - MST_CLK_SEL - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + H_AHBERRMSK1 2 1 read-write - - - - DATE - Version control - 0xF0 - 0x20 - 0x02101190 - - DATE - SPI register version. - 0 - 28 + H_STALLMSK1 + 3 + 1 + read-write + + + H_NAKMSK1 + 4 + 1 + read-write + + + H_ACKMSK1 + 5 + 1 + read-write + + + H_NYETMSK1 + 6 + 1 + read-write + + + H_XACTERRMSK1 + 7 + 1 + read-write + + + H_BBLERRMSK1 + 8 + 1 + read-write + + + H_FRMOVRUNMSK1 + 9 + 1 + read-write + + + H_DATATGLERRMSK1 + 10 + 1 + read-write + + + H_BNAINTRMSK1 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK1 + 13 + 1 read-write - - - - SPI3 - SPI (Serial Peripheral Interface) Controller - 0x60025000 - - SPI3 - 22 - - - - SYSTEM - System - SYSTEM - 0x600C0000 - - 0x0 - 0xA8 - registers - - - CORE_1_CONTROL_0 - Core0 control regiter 0 - 0x0 + HCTSIZ1 + 0x530 0x20 - 0x00000004 - CONTROL_CORE_1_RUNSTALL - Set 1 to stall core1 + H_XFERSIZE1 0 - 1 + 19 read-write - CONTROL_CORE_1_CLKGATE_EN - Set 1 to open core1 clock - 1 - 1 + H_PKTCNT1 + 19 + 10 + read-write + + + H_PID1 + 29 + 2 read-write - CONTROL_CORE_1_RESETING - Set 1 to let core1 reset - 2 + H_DOPNG1 + 31 1 read-write - CORE_1_CONTROL_1 - Core0 control regiter 1 - 0x4 + HCDMA1 + 0x534 0x20 - CONTROL_CORE_1_MESSAGE - it's only a R/W register, no function, software can write any value + H_DMAADDR1 0 32 read-write @@ -48780,330 +60291,379 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CPU_PERI_CLK_EN - cpu_peripheral clock configuration register - 0x8 + HCDMAB1 + 0x53C 0x20 - CLK_EN_ASSIST_DEBUG - Set 1 to open assist_debug module clock - 6 - 1 - read-write - - - CLK_EN_DEDICATED_GPIO - Set 1 to open dedicated_gpio module clk - 7 - 1 - read-write + H_HCDMAB1 + 0 + 32 + read-only - CPU_PERI_RST_EN - cpu_peripheral reset configuration regsiter - 0xC + HCCHAR2 + 0x540 0x20 - 0x000000C0 - RST_EN_ASSIST_DEBUG - Set 1 to let assist_debug module reset - 6 + H_MPS2 + 0 + 11 + read-write + + + H_EPNUM2 + 11 + 4 + read-write + + + H_EPDIR2 + 15 1 read-write - RST_EN_DEDICATED_GPIO - Set 1 to let dedicated_gpio module reset - 7 + H_LSPDDEV2 + 17 1 read-write - - - - CPU_PER_CONF - cpu peripheral clock configuration register - 0x10 - 0x20 - 0x0000000C - - CPUPERIOD_SEL - This field used to sel cpu clock frequent. - 0 + H_EPTYPE2 + 18 2 read-write - PLL_FREQ_SEL - This field used to sel pll frequent. - 2 + H_EC2 + 21 1 read-write - CPU_WAIT_MODE_FORCE_ON - Set 1 to force cpu_waiti_clk enable. - 3 + H_DEVADDR2 + 22 + 7 + read-write + + + H_ODDFRM2 + 29 1 read-write - CPU_WAITI_DELAY_NUM - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close - 4 - 4 + H_CHDIS2 + 30 + 1 read-write - - - - MEM_PD_MASK - memory power down mask configuration register - 0x14 - 0x20 - 0x00000001 - - LSLP_MEM_PD_MASK - Set 1 to mask memory power down. - 0 + H_CHENA2 + 31 1 read-write - PERIP_CLK_EN0 - peripheral clock configuration regsiter 0 - 0x18 + HCINT2 + 0x548 0x20 - 0xF9C1E06F - TIMERS_CLK_EN - Set 1 to enable TIMERS clock + H_XFERCOMPL2 0 1 read-write - SPI01_CLK_EN - Set 1 to enable SPI01 clock + H_CHHLTD2 1 1 read-write - UART_CLK_EN - Set 1 to enable UART clock + H_AHBERR2 2 1 read-write - WDG_CLK_EN - Set 1 to enable WDG clock + H_STALL2 3 1 read-write - I2S0_CLK_EN - Set 1 to enable I2S0 clock + H_NACK2 4 1 read-write - UART1_CLK_EN - Set 1 to enable UART1 clock + H_ACK2 5 1 read-write - SPI2_CLK_EN - Set 1 to enable SPI2 clock + H_NYET2 6 1 read-write - I2C_EXT0_CLK_EN - Set 1 to enable I2C_EXT0 clock + H_XACTERR2 7 1 read-write - UHCI0_CLK_EN - Set 1 to enable UHCI0 clock + H_BBLERR2 8 1 read-write - RMT_CLK_EN - Set 1 to enable RMT clock + H_FRMOVRUN2 9 1 read-write - PCNT_CLK_EN - Set 1 to enable PCNT clock + H_DATATGLERR2 10 1 read-write - LEDC_CLK_EN - Set 1 to enable LEDC clock + H_BNAINTR2 11 1 read-write - UHCI1_CLK_EN - Set 1 to enable UHCI1 clock + H_XCS_XACT_ERR2 12 1 read-write - TIMERGROUP_CLK_EN - Set 1 to enable TIMERGROUP clock + H_DESC_LST_ROLLINTR2 13 1 read-write + + + + HCINTMSK2 + 0x54C + 0x20 + - EFUSE_CLK_EN - Set 1 to enable EFUSE clock - 14 + H_XFERCOMPLMSK2 + 0 1 read-write - TIMERGROUP1_CLK_EN - Set 1 to enable TIMERGROUP1 clock - 15 + H_CHHLTDMSK2 + 1 1 read-write - SPI3_CLK_EN - Set 1 to enable SPI3 clock - 16 + H_AHBERRMSK2 + 2 1 read-write - PWM0_CLK_EN - Set 1 to enable PWM0 clock - 17 + H_STALLMSK2 + 3 1 read-write - I2C_EXT1_CLK_EN - Set 1 to enable I2C_EXT1 clock - 18 + H_NAKMSK2 + 4 1 read-write - CAN_CLK_EN - Set 1 to enable CAN clock - 19 + H_ACKMSK2 + 5 1 read-write - PWM1_CLK_EN - Set 1 to enable PWM1 clock - 20 + H_NYETMSK2 + 6 1 read-write - I2S1_CLK_EN - Set 1 to enable I2S1 clock - 21 + H_XACTERRMSK2 + 7 1 read-write - SPI2_DMA_CLK_EN - Set 1 to enable SPI2_DMA clock - 22 + H_BBLERRMSK2 + 8 1 read-write - USB_CLK_EN - Set 1 to enable USB clock - 23 + H_FRMOVRUNMSK2 + 9 1 read-write - UART_MEM_CLK_EN - Set 1 to enable UART_MEM clock - 24 + H_DATATGLERRMSK2 + 10 1 read-write - PWM2_CLK_EN - Set 1 to enable PWM2 clock - 25 + H_BNAINTRMSK2 + 11 1 read-write - PWM3_CLK_EN - Set 1 to enable PWM3 clock - 26 + H_DESC_LST_ROLLINTRMSK2 + 13 1 read-write + + + + HCTSIZ2 + 0x550 + 0x20 + + + H_XFERSIZE2 + 0 + 19 + read-write + - SPI3_DMA_CLK_EN - Set 1 to enable SPI4 clock - 27 + H_PKTCNT2 + 19 + 10 + read-write + + + H_PID2 + 29 + 2 + read-write + + + H_DOPNG2 + 31 1 read-write + + + + HCDMA2 + 0x554 + 0x20 + - APB_SARADC_CLK_EN - Set 1 to enable APB_SARADC clock - 28 + H_DMAADDR2 + 0 + 32 + read-write + + + + + HCDMAB2 + 0x55C + 0x20 + + + H_HCDMAB2 + 0 + 32 + read-only + + + + + HCCHAR3 + 0x560 + 0x20 + + + H_MPS3 + 0 + 11 + read-write + + + H_EPNUM3 + 11 + 4 + read-write + + + H_EPDIR3 + 15 1 read-write - SYSTIMER_CLK_EN - Set 1 to enable SYSTEMTIMER clock + H_LSPDDEV3 + 17 + 1 + read-write + + + H_EPTYPE3 + 18 + 2 + read-write + + + H_EC3 + 21 + 1 + read-write + + + H_DEVADDR3 + 22 + 7 + read-write + + + H_ODDFRM3 29 1 read-write - ADC2_ARB_CLK_EN - Set 1 to enable ADC2_ARB clock + H_CHDIS3 30 1 read-write - SPI4_CLK_EN - Set 1 to enable SPI4 clock + H_CHENA3 31 1 read-write @@ -49111,1512 +60671,1106 @@ Any pulses with width less than this will be ignored when the filter is enabled. - PERIP_CLK_EN1 - peripheral clock configuration regsiter 1 - 0x1C + HCINT3 + 0x568 0x20 - 0x00000600 - PERI_BACKUP_CLK_EN - Set 1 to enable BACKUP clock + H_XFERCOMPL3 0 1 read-write - CRYPTO_AES_CLK_EN - Set 1 to enable AES clock + H_CHHLTD3 1 1 read-write - CRYPTO_SHA_CLK_EN - Set 1 to enable SHA clock + H_AHBERR3 2 1 read-write - CRYPTO_RSA_CLK_EN - Set 1 to enable RSA clock + H_STALL3 3 1 read-write - CRYPTO_DS_CLK_EN - Set 1 to enable DS clock + H_NACK3 4 1 read-write - CRYPTO_HMAC_CLK_EN - Set 1 to enable HMAC clock + H_ACK3 5 1 read-write - DMA_CLK_EN - Set 1 to enable DMA clock + H_NYET3 6 1 read-write - SDIO_HOST_CLK_EN - Set 1 to enable SDIO_HOST clock + H_XACTERR3 7 1 read-write - LCD_CAM_CLK_EN - Set 1 to enable LCD_CAM clock + H_BBLERR3 8 1 read-write - UART2_CLK_EN - Set 1 to enable UART2 clock + H_FRMOVRUN3 9 1 read-write - USB_DEVICE_CLK_EN - Set 1 to enable USB_DEVICE clock + H_DATATGLERR3 10 1 read-write + + H_BNAINTR3 + 11 + 1 + read-write + + + H_XCS_XACT_ERR3 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR3 + 13 + 1 + read-write + - PERIP_RST_EN0 - peripheral reset configuration register0 - 0x20 + HCINTMSK3 + 0x56C 0x20 - TIMERS_RST - Set 1 to let TIMERS reset + H_XFERCOMPLMSK3 0 1 read-write - SPI01_RST - Set 1 to let SPI01 reset + H_CHHLTDMSK3 1 1 read-write - UART_RST - Set 1 to let UART reset + H_AHBERRMSK3 2 1 read-write - WDG_RST - Set 1 to let WDG reset + H_STALLMSK3 3 1 read-write - I2S0_RST - Set 1 to let I2S0 reset + H_NAKMSK3 4 1 read-write - UART1_RST - Set 1 to let UART1 reset + H_ACKMSK3 5 1 read-write - SPI2_RST - Set 1 to let SPI2 reset + H_NYETMSK3 6 1 read-write - I2C_EXT0_RST - Set 1 to let I2C_EXT0 reset + H_XACTERRMSK3 7 1 read-write - UHCI0_RST - Set 1 to let UHCI0 reset + H_BBLERRMSK3 8 1 read-write - RMT_RST - Set 1 to let RMT reset + H_FRMOVRUNMSK3 9 1 read-write - PCNT_RST - Set 1 to let PCNT reset + H_DATATGLERRMSK3 10 1 read-write - LEDC_RST - Set 1 to let LEDC reset + H_BNAINTRMSK3 11 1 read-write - UHCI1_RST - Set 1 to let UHCI1 reset - 12 + H_DESC_LST_ROLLINTRMSK3 + 13 1 read-write + + + + HCTSIZ3 + 0x570 + 0x20 + + + H_XFERSIZE3 + 0 + 19 + read-write + - TIMERGROUP_RST - Set 1 to let TIMERGROUP reset - 13 - 1 + H_PKTCNT3 + 19 + 10 read-write - EFUSE_RST - Set 1 to let EFUSE reset - 14 - 1 + H_PID3 + 29 + 2 read-write - TIMERGROUP1_RST - Set 1 to let TIMERGROUP1 reset - 15 + H_DOPNG3 + 31 1 read-write + + + + HCDMA3 + 0x574 + 0x20 + - SPI3_RST - Set 1 to let SPI3 reset - 16 + H_DMAADDR3 + 0 + 32 + read-write + + + + + HCDMAB3 + 0x57C + 0x20 + + + H_HCDMAB3 + 0 + 32 + read-only + + + + + HCCHAR4 + 0x580 + 0x20 + + + H_MPS4 + 0 + 11 + read-write + + + H_EPNUM4 + 11 + 4 + read-write + + + H_EPDIR4 + 15 1 read-write - PWM0_RST - Set 1 to let PWM0 reset + H_LSPDDEV4 17 1 read-write - I2C_EXT1_RST - Set 1 to let I2C_EXT1 reset + H_EPTYPE4 18 + 2 + read-write + + + H_EC4 + 21 1 read-write - CAN_RST - Set 1 to let CAN reset - 19 + H_DEVADDR4 + 22 + 7 + read-write + + + H_ODDFRM4 + 29 1 read-write - PWM1_RST - Set 1 to let PWM1 reset - 20 + H_CHDIS4 + 30 1 read-write - I2S1_RST - Set 1 to let I2S1 reset - 21 + H_CHENA4 + 31 + 1 + read-write + + + + + HCINT4 + 0x588 + 0x20 + + + H_XFERCOMPL4 + 0 1 read-write - SPI2_DMA_RST - Set 1 to let SPI2 reset - 22 + H_CHHLTD4 + 1 1 read-write - USB_RST - Set 1 to let USB reset - 23 + H_AHBERR4 + 2 1 read-write - UART_MEM_RST - Set 1 to let UART_MEM reset - 24 + H_STALL4 + 3 1 read-write - PWM2_RST - Set 1 to let PWM2 reset - 25 + H_NACK4 + 4 1 read-write - PWM3_RST - Set 1 to let PWM3 reset - 26 + H_ACK4 + 5 1 read-write - SPI3_DMA_RST - Set 1 to let SPI3 reset - 27 + H_NYET4 + 6 1 read-write - APB_SARADC_RST - Set 1 to let APB_SARADC reset - 28 + H_XACTERR4 + 7 1 read-write - SYSTIMER_RST - Set 1 to let SYSTIMER reset - 29 + H_BBLERR4 + 8 1 read-write - ADC2_ARB_RST - Set 1 to let ADC2_ARB reset - 30 + H_FRMOVRUN4 + 9 1 read-write - SPI4_RST - Set 1 to let SPI4 reset - 31 + H_DATATGLERR4 + 10 + 1 + read-write + + + H_BNAINTR4 + 11 + 1 + read-write + + + H_XCS_XACT_ERR4 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR4 + 13 1 read-write - PERIP_RST_EN1 - peripheral reset configuration regsiter 1 - 0x24 + HCINTMSK4 + 0x58C 0x20 - 0x000001FE - PERI_BACKUP_RST - Set 1 to let BACKUP reset + H_XFERCOMPLMSK4 0 1 read-write - CRYPTO_AES_RST - Set 1 to let CRYPTO_AES reset + H_CHHLTDMSK4 1 1 read-write - CRYPTO_SHA_RST - Set 1 to let CRYPTO_SHA reset + H_AHBERRMSK4 2 1 read-write - CRYPTO_RSA_RST - Set 1 to let CRYPTO_RSA reset + H_STALLMSK4 3 1 read-write - CRYPTO_DS_RST - Set 1 to let CRYPTO_DS reset + H_NAKMSK4 4 1 read-write - CRYPTO_HMAC_RST - Set 1 to let CRYPTO_HMAC reset + H_ACKMSK4 5 1 read-write - DMA_RST - Set 1 to let DMA reset + H_NYETMSK4 6 1 read-write - SDIO_HOST_RST - Set 1 to let SDIO_HOST reset + H_XACTERRMSK4 7 1 read-write - LCD_CAM_RST - Set 1 to let LCD_CAM reset + H_BBLERRMSK4 8 1 read-write - UART2_RST - Set 1 to let UART2 reset + H_FRMOVRUNMSK4 9 1 read-write - USB_DEVICE_RST - Set 1 to let USB_DEVICE reset + H_DATATGLERRMSK4 10 1 read-write - - - - BT_LPCK_DIV_INT - low power clock frequent division factor configuration regsiter - 0x28 - 0x20 - 0x000000FF - - BT_LPCK_DIV_NUM - This field is lower power clock frequent division factor - 0 - 12 + H_BNAINTRMSK4 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK4 + 13 + 1 read-write - BT_LPCK_DIV_FRAC - low power clock configuration register - 0x2C + HCTSIZ4 + 0x590 0x20 - 0x02001001 - BT_LPCK_DIV_B - This field is lower power clock frequent division factor b + H_XFERSIZE4 0 - 12 - read-write - - - BT_LPCK_DIV_A - This field is lower power clock frequent division factor a - 12 - 12 - read-write - - - LPCLK_SEL_RTC_SLOW - Set 1 to select rtc-slow clock as rtc low power clock - 24 - 1 - read-write - - - LPCLK_SEL_8M - Set 1 to select 8m clock as rtc low power clock - 25 - 1 - read-write - - - LPCLK_SEL_XTAL - Set 1 to select xtal clock as rtc low power clock - 26 - 1 + 19 read-write - LPCLK_SEL_XTAL32K - Set 1 to select xtal32k clock as low power clock - 27 - 1 + H_PKTCNT4 + 19 + 10 read-write - LPCLK_RTC_EN - Set 1 to enable RTC low power clock - 28 - 1 + H_PID4 + 29 + 2 read-write - - - - CPU_INTR_FROM_CPU_0 - interrupt source register 0 - 0x30 - 0x20 - - CPU_INTR_FROM_CPU_0 - Set 1 to generate cpu interrupt 0 - 0 + H_DOPNG4 + 31 1 read-write - CPU_INTR_FROM_CPU_1 - interrupt source register 1 - 0x34 + HCDMA4 + 0x594 0x20 - CPU_INTR_FROM_CPU_1 - Set 1 to generate cpu interrupt 1 + H_DMAADDR4 0 - 1 + 32 read-write - CPU_INTR_FROM_CPU_2 - interrupt source register 2 - 0x38 + HCDMAB4 + 0x59C 0x20 - CPU_INTR_FROM_CPU_2 - Set 1 to generate cpu interrupt 2 + H_HCDMAB4 0 - 1 - read-write + 32 + read-only - CPU_INTR_FROM_CPU_3 - interrupt source register 3 - 0x3C + HCCHAR5 + 0x5A0 0x20 - CPU_INTR_FROM_CPU_3 - Set 1 to generate cpu interrupt 3 + H_MPS5 0 - 1 + 11 read-write - - - - RSA_PD_CTRL - rsa memory power control register - 0x40 - 0x20 - 0x00000001 - - RSA_MEM_PD - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid. - 0 - 1 + H_EPNUM5 + 11 + 4 read-write - RSA_MEM_FORCE_PU - Set 1 to force power up RSA memory, this bit has the second highest priority. - 1 + H_EPDIR5 + 15 1 read-write - RSA_MEM_FORCE_PD - Set 1 to force power down RSA memory,this bit has the highest priority. - 2 + H_LSPDDEV5 + 17 1 read-write - - - - EDMA_CTRL - EDMA control register - 0x44 - 0x20 - 0x00000001 - - EDMA_CLK_ON - Set 1 to enable EDMA clock. - 0 - 1 + H_EPTYPE5 + 18 + 2 read-write - EDMA_RESET - Set 1 to let EDMA reset - 1 + H_EC5 + 21 1 read-write - - - - CACHE_CONTROL - Cache control register - 0x48 - 0x20 - 0x00000005 - - ICACHE_CLK_ON - Set 1 to enable icache clock - 0 - 1 + H_DEVADDR5 + 22 + 7 read-write - ICACHE_RESET - Set 1 to let icache reset - 1 + H_ODDFRM5 + 29 1 read-write - DCACHE_CLK_ON - Set 1 to enable dcache clock - 2 + H_CHDIS5 + 30 1 read-write - DCACHE_RESET - Set 1 to let dcache reset - 3 + H_CHENA5 + 31 1 read-write - EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL - External memory encrypt and decrypt control register - 0x4C + HCINT5 + 0x5A8 0x20 - ENABLE_SPI_MANUAL_ENCRYPT - Set 1 to enable the SPI manual encrypt. + H_XFERCOMPL5 0 1 read-write - ENABLE_DOWNLOAD_DB_ENCRYPT - Set 1 to enable download DB encrypt. + H_CHHLTD5 1 1 read-write - ENABLE_DOWNLOAD_G0CB_DECRYPT - Set 1 to enable download G0CB decrypt + H_AHBERR5 2 1 read-write - ENABLE_DOWNLOAD_MANUAL_ENCRYPT - Set 1 to enable download manual encrypt + H_STALL5 3 1 read-write - - - - RTC_FASTMEM_CONFIG - RTC fast memory configuration register - 0x50 - 0x20 - 0x7FF00000 - - RTC_MEM_CRC_START - Set 1 to start the CRC of RTC memory - 8 + H_NACK5 + 4 1 read-write - RTC_MEM_CRC_ADDR - This field is used to set address of RTC memory for CRC. - 9 - 11 - read-write - - - RTC_MEM_CRC_LEN - This field is used to set length of RTC memory for CRC based on start address. - 20 - 11 + H_ACK5 + 5 + 1 read-write - RTC_MEM_CRC_FINISH - This bit stores the status of RTC memory CRC.1 means finished. - 31 + H_NYET5 + 6 1 - read-only - - - - - RTC_FASTMEM_CRC - RTC fast memory CRC control register - 0x54 - 0x20 - - - RTC_MEM_CRC_RES - This field stores the CRC result of RTC memory. - 0 - 32 - read-only + read-write - - - - REDUNDANT_ECO_CTRL - ******* Description *********** - 0x58 - 0x20 - - REDUNDANT_ECO_DRIVE - ******* Description *********** - 0 + H_XACTERR5 + 7 1 read-write - REDUNDANT_ECO_RESULT - ******* Description *********** - 1 + H_BBLERR5 + 8 1 - read-only + read-write - - - - CLOCK_GATE - ******* Description *********** - 0x5C - 0x20 - 0x00000001 - - CLK_EN - ******* Description *********** - 0 + H_FRMOVRUN5 + 9 1 read-write - - - - SYSCLK_CONF - System clock configuration register. - 0x60 - 0x20 - 0x00000001 - - PRE_DIV_CNT - This field is used to set the count of prescaler of XTAL_CLK. - 0 - 10 + H_DATATGLERR5 + 10 + 1 read-write - SOC_CLK_SEL - This field is used to select soc clock. - 10 - 2 + H_BNAINTR5 + 11 + 1 read-write - CLK_XTAL_FREQ - This field is used to read xtal frequency in MHz. + H_XCS_XACT_ERR5 12 - 7 - read-only + 1 + read-write - CLK_DIV_EN - Reserved. - 19 + H_DESC_LST_ROLLINTR5 + 13 1 - read-only + read-write - MEM_PVT - ******* Description *********** - 0x64 + HCINTMSK5 + 0x5AC 0x20 - 0x00000003 - MEM_PATH_LEN - ******* Description *********** + H_XFERCOMPLMSK5 0 - 4 + 1 read-write - MEM_ERR_CNT_CLR - ******* Description *********** - 4 + H_CHHLTDMSK5 + 1 1 - write-only + read-write - MONITOR_EN - ******* Description *********** - 5 + H_AHBERRMSK5 + 2 1 read-write - MEM_TIMING_ERR_CNT - ******* Description *********** - 6 - 16 - read-only - - - MEM_VT_SEL - ******* Description *********** - 22 - 2 + H_STALLMSK5 + 3 + 1 read-write - - - - COMB_PVT_LVT_CONF - ******* Description *********** - 0x68 - 0x20 - 0x00000003 - - COMB_PATH_LEN_LVT - ******* Description *********** - 0 - 5 + H_NAKMSK5 + 4 + 1 read-write - COMB_ERR_CNT_CLR_LVT - ******* Description *********** + H_ACKMSK5 5 1 - write-only + read-write - COMB_PVT_MONITOR_EN_LVT - ******* Description *********** + H_NYETMSK5 6 1 read-write - - - - COMB_PVT_NVT_CONF - ******* Description *********** - 0x6C - 0x20 - 0x00000003 - - - COMB_PATH_LEN_NVT - ******* Description *********** - 0 - 5 - read-write - - - COMB_ERR_CNT_CLR_NVT - ******* Description *********** - 5 - 1 - write-only - - COMB_PVT_MONITOR_EN_NVT - ******* Description *********** - 6 + H_XACTERRMSK5 + 7 1 read-write - - - - COMB_PVT_HVT_CONF - ******* Description *********** - 0x70 - 0x20 - 0x00000003 - - COMB_PATH_LEN_HVT - ******* Description *********** - 0 - 5 + H_BBLERRMSK5 + 8 + 1 read-write - COMB_ERR_CNT_CLR_HVT - ******* Description *********** - 5 + H_FRMOVRUNMSK5 + 9 1 - write-only + read-write - COMB_PVT_MONITOR_EN_HVT - ******* Description *********** - 6 + H_DATATGLERRMSK5 + 10 1 read-write - - - - COMB_PVT_ERR_LVT_SITE0 - ******* Description *********** - 0x74 - 0x20 - - - COMB_TIMING_ERR_CNT_LVT_SITE0 - ******* Description *********** - 0 - 16 - read-only - - - - - COMB_PVT_ERR_NVT_SITE0 - ******* Description *********** - 0x78 - 0x20 - - - COMB_TIMING_ERR_CNT_NVT_SITE0 - ******* Description *********** - 0 - 16 - read-only - - - - - COMB_PVT_ERR_HVT_SITE0 - ******* Description *********** - 0x7C - 0x20 - - - COMB_TIMING_ERR_CNT_HVT_SITE0 - ******* Description *********** - 0 - 16 - read-only - - - - - COMB_PVT_ERR_LVT_SITE1 - ******* Description *********** - 0x80 - 0x20 - - - COMB_TIMING_ERR_CNT_LVT_SITE1 - ******* Description *********** - 0 - 16 - read-only - - - - - COMB_PVT_ERR_NVT_SITE1 - ******* Description *********** - 0x84 - 0x20 - - - COMB_TIMING_ERR_CNT_NVT_SITE1 - ******* Description *********** - 0 - 16 - read-only - - - - - COMB_PVT_ERR_HVT_SITE1 - ******* Description *********** - 0x88 - 0x20 - - COMB_TIMING_ERR_CNT_HVT_SITE1 - ******* Description *********** - 0 - 16 - read-only + H_BNAINTRMSK5 + 11 + 1 + read-write - - - - COMB_PVT_ERR_LVT_SITE2 - ******* Description *********** - 0x8C - 0x20 - - COMB_TIMING_ERR_CNT_LVT_SITE2 - ******* Description *********** - 0 - 16 - read-only + H_DESC_LST_ROLLINTRMSK5 + 13 + 1 + read-write - COMB_PVT_ERR_NVT_SITE2 - ******* Description *********** - 0x90 + HCTSIZ5 + 0x5B0 0x20 - COMB_TIMING_ERR_CNT_NVT_SITE2 - ******* Description *********** + H_XFERSIZE5 0 - 16 - read-only + 19 + read-write - - - - COMB_PVT_ERR_HVT_SITE2 - ******* Description *********** - 0x94 - 0x20 - - COMB_TIMING_ERR_CNT_HVT_SITE2 - ******* Description *********** - 0 - 16 - read-only + H_PKTCNT5 + 19 + 10 + read-write - - - - COMB_PVT_ERR_LVT_SITE3 - ******* Description *********** - 0x98 - 0x20 - - COMB_TIMING_ERR_CNT_LVT_SITE3 - ******* Description *********** - 0 - 16 - read-only + H_PID5 + 29 + 2 + read-write + + + H_DOPNG5 + 31 + 1 + read-write - COMB_PVT_ERR_NVT_SITE3 - ******* Description *********** - 0x9C + HCDMA5 + 0x5B4 0x20 - COMB_TIMING_ERR_CNT_NVT_SITE3 - ******* Description *********** + H_DMAADDR5 0 - 16 - read-only + 32 + read-write - COMB_PVT_ERR_HVT_SITE3 - ******* Description *********** - 0xA0 + HCDMAB5 + 0x5BC 0x20 - COMB_TIMING_ERR_CNT_HVT_SITE3 - ******* Description *********** + H_HCDMAB5 0 - 16 + 32 read-only - DATE - version register - 0xFFC + HCCHAR6 + 0x5C0 0x20 - 0x02101220 - DATE - version register + H_MPS6 0 - 28 + 11 read-write - - - - - - SYSTIMER - System Timer - SYSTIMER - 0x60023000 - - 0x0 - 0x90 - registers - - - SYSTIMER_TARGET0 - 57 - - - SYSTIMER_TARGET1 - 58 - - - SYSTIMER_TARGET2 - 59 - - - - CONF - Configure system timer clock - 0x0 - 0x20 - 0x46000000 - - SYSTIMER_CLK_FO - systimer clock force on - 0 + H_EPNUM6 + 11 + 4 + read-write + + + H_EPDIR6 + 15 1 read-write - TARGET2_WORK_EN - target2 work enable + H_LSPDDEV6 + 17 + 1 + read-write + + + H_EPTYPE6 + 18 + 2 + read-write + + + H_EC6 + 21 + 1 + read-write + + + H_DEVADDR6 22 + 7 + read-write + + + H_ODDFRM6 + 29 1 read-write - TARGET1_WORK_EN - target1 work enable - 23 + H_CHDIS6 + 30 1 read-write - TARGET0_WORK_EN - target0 work enable - 24 + H_CHENA6 + 31 1 read-write + + + + HCINT6 + 0x5C8 + 0x20 + - TIMER_UNIT1_CORE1_STALL_EN - If timer unit1 is stalled when core1 stalled - 25 + H_XFERCOMPL6 + 0 1 read-write - TIMER_UNIT1_CORE0_STALL_EN - If timer unit1 is stalled when core0 stalled - 26 + H_CHHLTD6 + 1 1 read-write - TIMER_UNIT0_CORE1_STALL_EN - If timer unit0 is stalled when core1 stalled - 27 + H_AHBERR6 + 2 1 read-write - TIMER_UNIT0_CORE0_STALL_EN - If timer unit0 is stalled when core0 stalled - 28 + H_STALL6 + 3 1 read-write - TIMER_UNIT1_WORK_EN - timer unit1 work enable - 29 + H_NACK6 + 4 1 read-write - TIMER_UNIT0_WORK_EN - timer unit0 work enable - 30 + H_ACK6 + 5 1 read-write - CLK_EN - register file clk gating - 31 + H_NYET6 + 6 1 read-write - - - - UNIT0_OP - system timer unit0 value update register - 0x4 - 0x20 - - TIMER_UNIT0_VALUE_VALID - timer value is sync and valid - 29 + H_XACTERR6 + 7 1 - read-only + read-write - TIMER_UNIT0_UPDATE - update timer_unit0 - 30 + H_BBLERR6 + 8 1 - write-only + read-write - - - - UNIT1_OP - system timer unit1 value update register - 0x8 - 0x20 - - TIMER_UNIT1_VALUE_VALID - timer value is sync and valid - 29 + H_FRMOVRUN6 + 9 1 - read-only + read-write - TIMER_UNIT1_UPDATE - update timer unit1 - 30 + H_DATATGLERR6 + 10 1 - write-only + read-write - - - - UNIT0_LOAD_HI - system timer unit0 value high load register - 0xC - 0x20 - - TIMER_UNIT0_LOAD_HI - timer unit0 load high 20 bits - 0 - 20 + H_BNAINTR6 + 11 + 1 read-write - - - - UNIT0_LOAD_LO - system timer unit0 value low load register - 0x10 - 0x20 - - TIMER_UNIT0_LOAD_LO - timer unit0 load low 32 bits - 0 - 32 + H_XCS_XACT_ERR6 + 12 + 1 read-write - - - - UNIT1_LOAD_HI - system timer unit1 value high load register - 0x14 - 0x20 - - TIMER_UNIT1_LOAD_HI - timer unit1 load high 20 bits - 0 - 20 + H_DESC_LST_ROLLINTR6 + 13 + 1 read-write - UNIT1_LOAD_LO - system timer unit1 value low load register - 0x18 + HCINTMSK6 + 0x5CC 0x20 - TIMER_UNIT1_LOAD_LO - timer unit1 load low 32 bits + H_XFERCOMPLMSK6 0 - 32 + 1 read-write - - - - TARGET0_HI - system timer comp0 value high register - 0x1C - 0x20 - - TIMER_TARGET0_HI - timer taget0 high 20 bits - 0 - 20 + H_CHHLTDMSK6 + 1 + 1 read-write - - - - TARGET0_LO - system timer comp0 value low register - 0x20 - 0x20 - - TIMER_TARGET0_LO - timer taget0 low 32 bits - 0 - 32 + H_AHBERRMSK6 + 2 + 1 read-write - - - - TARGET1_HI - system timer comp1 value high register - 0x24 - 0x20 - - TIMER_TARGET1_HI - timer taget1 high 20 bits - 0 - 20 + H_STALLMSK6 + 3 + 1 read-write - - - - TARGET1_LO - system timer comp1 value low register - 0x28 - 0x20 - - TIMER_TARGET1_LO - timer taget1 low 32 bits - 0 - 32 + H_NAKMSK6 + 4 + 1 read-write - - - - TARGET2_HI - system timer comp2 value high register - 0x2C - 0x20 - - TIMER_TARGET2_HI - timer taget2 high 20 bits - 0 - 20 + H_ACKMSK6 + 5 + 1 read-write - - - - TARGET2_LO - system timer comp2 value low register - 0x30 - 0x20 - - TIMER_TARGET2_LO - timer taget2 low 32 bits - 0 - 32 + H_NYETMSK6 + 6 + 1 read-write - - - - TARGET0_CONF - system timer comp0 target mode register - 0x34 - 0x20 - - TARGET0_PERIOD - target0 period - 0 - 26 + H_XACTERRMSK6 + 7 + 1 read-write - TARGET0_PERIOD_MODE - Set target0 to period mode - 30 + H_BBLERRMSK6 + 8 1 read-write - TARGET0_TIMER_UNIT_SEL - select which unit to compare - 31 + H_FRMOVRUNMSK6 + 9 1 read-write - - - - TARGET1_CONF - system timer comp1 target mode register - 0x38 - 0x20 - - TARGET1_PERIOD - target1 period - 0 - 26 + H_DATATGLERRMSK6 + 10 + 1 read-write - TARGET1_PERIOD_MODE - Set target1 to period mode - 30 + H_BNAINTRMSK6 + 11 1 read-write - TARGET1_TIMER_UNIT_SEL - select which unit to compare - 31 + H_DESC_LST_ROLLINTRMSK6 + 13 1 read-write - TARGET2_CONF - system timer comp2 target mode register - 0x3C + HCTSIZ6 + 0x5D0 0x20 - TARGET2_PERIOD - target2 period + H_XFERSIZE6 0 - 26 + 19 read-write - TARGET2_PERIOD_MODE - Set target2 to period mode - 30 - 1 + H_PKTCNT6 + 19 + 10 read-write - TARGET2_TIMER_UNIT_SEL - select which unit to compare + H_PID6 + 29 + 2 + read-write + + + H_DOPNG6 31 1 read-write @@ -50624,29 +61778,25 @@ Any pulses with width less than this will be ignored when the filter is enabled. - UNIT0_VALUE_HI - system timer unit0 value high register - 0x40 + HCDMA6 + 0x5D4 0x20 - TIMER_UNIT0_VALUE_HI - timer read value high 20bits + H_DMAADDR6 0 - 20 - read-only + 32 + read-write - UNIT0_VALUE_LO - system timer unit0 value low register - 0x44 + HCDMAB6 + 0x5DC 0x20 - TIMER_UNIT0_VALUE_LO - timer read value low 32bits + H_HCDMAB6 0 32 read-only @@ -50654,3207 +61804,3173 @@ Any pulses with width less than this will be ignored when the filter is enabled. - UNIT1_VALUE_HI - system timer unit1 value high register - 0x48 + HCCHAR7 + 0x5E0 0x20 - TIMER_UNIT1_VALUE_HI - timer read value high 20bits + H_MPS7 0 - 20 - read-only + 11 + read-write - - - - UNIT1_VALUE_LO - system timer unit1 value low register - 0x4C - 0x20 - - TIMER_UNIT1_VALUE_LO - timer read value low 32bits - 0 - 32 - read-only + H_EPNUM7 + 11 + 4 + read-write + + + H_EPDIR7 + 15 + 1 + read-write + + + H_LSPDDEV7 + 17 + 1 + read-write + + + H_EPTYPE7 + 18 + 2 + read-write + + + H_EC7 + 21 + 1 + read-write + + + H_DEVADDR7 + 22 + 7 + read-write + + + H_ODDFRM7 + 29 + 1 + read-write + + + H_CHDIS7 + 30 + 1 + read-write - - - - COMP0_LOAD - system timer comp0 conf sync register - 0x50 - 0x20 - - TIMER_COMP0_LOAD - timer comp0 sync enable signal - 0 + H_CHENA7 + 31 1 - write-only + read-write - COMP1_LOAD - system timer comp1 conf sync register - 0x54 + HCINT7 + 0x5E8 0x20 - TIMER_COMP1_LOAD - timer comp1 sync enable signal + H_XFERCOMPL7 0 1 - write-only + read-write - - - - COMP2_LOAD - system timer comp2 conf sync register - 0x58 - 0x20 - - TIMER_COMP2_LOAD - timer comp2 sync enable signal - 0 + H_CHHLTD7 + 1 1 - write-only + read-write - - - - UNIT0_LOAD - system timer unit0 conf sync register - 0x5C - 0x20 - - TIMER_UNIT0_LOAD - timer unit0 sync enable signal - 0 + H_AHBERR7 + 2 1 - write-only + read-write - - - - UNIT1_LOAD - system timer unit1 conf sync register - 0x60 - 0x20 - - TIMER_UNIT1_LOAD - timer unit1 sync enable signal - 0 + H_STALL7 + 3 1 - write-only + read-write - - - - INT_ENA - systimer interrupt enable register - 0x64 - 0x20 - - TARGET0_INT_ENA - interupt0 enable - 0 + H_NACK7 + 4 1 read-write - TARGET1_INT_ENA - interupt1 enable - 1 + H_ACK7 + 5 1 read-write - TARGET2_INT_ENA - interupt2 enable - 2 + H_NYET7 + 6 1 read-write - - - - INT_RAW - systimer interrupt raw register - 0x68 - 0x20 - - TARGET0_INT_RAW - interupt0 raw - 0 + H_XACTERR7 + 7 1 - read-only + read-write - TARGET1_INT_RAW - interupt1 raw - 1 + H_BBLERR7 + 8 1 - read-only + read-write - TARGET2_INT_RAW - interupt2 raw - 2 + H_FRMOVRUN7 + 9 1 - read-only + read-write - - - - INT_CLR - systimer interrupt clear register - 0x6C - 0x20 - - TARGET0_INT_CLR - interupt0 clear - 0 + H_DATATGLERR7 + 10 1 - write-only + read-write - TARGET1_INT_CLR - interupt1 clear - 1 + H_BNAINTR7 + 11 1 - write-only + read-write - TARGET2_INT_CLR - interupt2 clear - 2 + H_XCS_XACT_ERR7 + 12 1 - write-only + read-write + + + H_DESC_LST_ROLLINTR7 + 13 + 1 + read-write - INT_ST - systimer interrupt status register - 0x70 + HCINTMSK7 + 0x5EC 0x20 - TARGET0_INT_ST - interupt0 status + H_XFERCOMPLMSK7 0 1 - read-only + read-write - TARGET1_INT_ST - interupt1 status + H_CHHLTDMSK7 1 1 - read-only + read-write - TARGET2_INT_ST - interupt2 status + H_AHBERRMSK7 2 1 - read-only + read-write - - - - REAL_TARGET0_LO - system timer comp0 actual target value low register - 0x74 - 0x20 - - TARGET0_LO_RO - actual target value value low 32bits - 0 - 32 - read-only + H_STALLMSK7 + 3 + 1 + read-write - - - - REAL_TARGET0_HI - system timer comp0 actual target value high register - 0x78 - 0x20 - - TARGET0_HI_RO - actual target value value high 20bits - 0 - 20 - read-only + H_NAKMSK7 + 4 + 1 + read-write - - - - REAL_TARGET1_LO - system timer comp1 actual target value low register - 0x7C - 0x20 - - TARGET1_LO_RO - actual target value value low 32bits - 0 - 32 - read-only + H_ACKMSK7 + 5 + 1 + read-write + + + H_NYETMSK7 + 6 + 1 + read-write + + + H_XACTERRMSK7 + 7 + 1 + read-write + + + H_BBLERRMSK7 + 8 + 1 + read-write + + + H_FRMOVRUNMSK7 + 9 + 1 + read-write + + + H_DATATGLERRMSK7 + 10 + 1 + read-write + + + H_BNAINTRMSK7 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK7 + 13 + 1 + read-write - REAL_TARGET1_HI - system timer comp1 actual target value high register - 0x80 + HCTSIZ7 + 0x5F0 0x20 - TARGET1_HI_RO - actual target value value high 20bits + H_XFERSIZE7 0 - 20 - read-only + 19 + read-write + + + H_PKTCNT7 + 19 + 10 + read-write + + + H_PID7 + 29 + 2 + read-write + + + H_DOPNG7 + 31 + 1 + read-write - REAL_TARGET2_LO - system timer comp2 actual target value low register - 0x84 + HCDMA7 + 0x5F4 0x20 - TARGET2_LO_RO - actual target value value low 32bits + H_DMAADDR7 0 32 - read-only + read-write - REAL_TARGET2_HI - system timer comp2 actual target value high register - 0x88 + HCDMAB7 + 0x5FC 0x20 - TARGET2_HI_RO - actual target value value high 20bits + H_HCDMAB7 0 - 20 + 32 read-only - DATE - system timer version control register - 0xFC + DCFG + 0x800 0x20 - 0x02012251 + 0x08100000 - DATE - systimer register version - 0 - 32 + NZSTSOUTHSHK + 2 + 1 read-write - - - - - - TIMG0 - Timer Group - TIMG - 0x6001F000 - - 0x0 - 0x8C - registers - - - TG0_T0_LEVEL - 50 - - - TG0_T1_LEVEL - 51 - - - TG0_WDT_LEVEL - 52 - - - - 2 - 0x24 - T%sCONFIG - Timer %s configuration register - 0x0 - 0x20 - 0x60002000 - - T0_USE_XTAL - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. - 9 + ENA32KHZSUSP + 3 1 read-write - T0_ALARM_EN - When set, the alarm is enabled. This bit is automatically cleared once an -alarm occurs. - 10 - 1 + DEVADDR + 4 + 7 read-write - T0_DIVIDER - Timer %s clock (T%s_clk) prescaler value. + PERFRLINT + 11 + 2 + read-write + + + ENDEVOUTNAK 13 - 16 + 1 read-write - T0_AUTORELOAD - When set, timer %s auto-reload at alarm is enabled. - 29 + XCVRDLY + 14 1 read-write - T0_INCREASE - When set, the timer %s time-base counter will increment every clock tick. When -cleared, the timer %s time-base counter will decrement. - 30 + ERRATICINTMSK + 15 1 read-write - T0_EN - When set, the timer %s time-base counter is enabled. - 31 + EPMISCNT + 18 + 5 + read-write + + + DESCDMA + 23 1 read-write + + PERSCHINTVL + 24 + 2 + read-write + + + RESVALID + 26 + 6 + read-write + - 2 - 0x24 - T%sLO - Timer %s current value, low 32 bits - 0x4 + DCTL + 0x804 0x20 + 0x00002000 - T0_LO - After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter -of timer %s can be read here. + RMTWKUPSIG 0 - 32 + 1 + read-write + + + SFTDISCON + 1 + 1 + read-write + + + GNPINNAKSTS + 2 + 1 read-only - - - - 2 - 0x24 - T%sHI - Timer %s current value, high 22 bits - 0x8 - 0x20 - - T0_HI - After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter -of timer %s can be read here. - 0 - 22 + GOUTNAKSTS + 3 + 1 read-only - - - - 2 - 0x24 - T%sUPDATE - Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG - 0xC - 0x20 - - T0_UPDATE - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. - 31 + TSTCTL + 4 + 3 + read-write + + + SGNPINNAK + 7 + 1 + write-only + + + CGNPINNAK + 8 + 1 + write-only + + + SGOUTNAK + 9 + 1 + write-only + + + CGOUTNAK + 10 + 1 + write-only + + + PWRONPRGDONE + 11 1 read-write - - - - 2 - 0x24 - T%sALARMLO - Timer %s alarm value, low 32 bits - 0x10 - 0x20 - - T0_ALARM_LO - Timer %s alarm trigger time-base counter value, low 32 bits. - 0 - 32 + GMC + 13 + 2 read-write - - - - 2 - 0x24 - T%sALARMHI - Timer %s alarm value, high bits - 0x14 - 0x20 - - T0_ALARM_HI - Timer %s alarm trigger time-base counter value, high 22 bits. - 0 - 22 + IGNRFRMNUM + 15 + 1 read-write - - - - 2 - 0x24 - T%sLOADLO - Timer %s reload value, low 32 bits - 0x18 - 0x20 - - T0_LOAD_LO - Low 32 bits of the value that a reload will load onto timer %s time-base -Counter. - 0 - 32 + NAKONBBLE + 16 + 1 + read-write + + + ENCOUNTONBNA + 17 + 1 + read-write + + + DEEPSLEEPBESLREJECT + 18 + 1 read-write - 2 - 0x24 - T%sLOADHI - Timer %s reload value, high 22 bits - 0x1C + DSTS + 0x808 0x20 + 0x00000002 - T0_LOAD_HI - High 22 bits of the value that a reload will load onto timer %s time-base -counter. + SUSPSTS 0 - 22 - read-write + 1 + read-only + + + ENUMSPD + 1 + 2 + read-only + + + ERRTICERR + 3 + 1 + read-only + + + SOFFN + 8 + 14 + read-only - - - - 2 - 0x24 - T%sLOAD - Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG - 0x20 - 0x20 - - T0_LOAD - -Write any value to trigger a timer %s time-base counter reload. - 0 - 32 - write-only + DEVLNSTS + 22 + 2 + read-only - WDTCONFIG0 - Watchdog timer configuration register - 0x48 + DIEPMSK + 0x810 0x20 - 0x0004C000 - WDT_APPCPU_RESET_EN - Reserved - 12 + DI_XFERCOMPLMSK + 0 1 read-write - WDT_PROCPU_RESET_EN - WDT reset CPU enable. - 13 + DI_EPDISBLDMSK + 1 1 read-write - WDT_FLASHBOOT_MOD_EN - When set, Flash boot protection is enabled. - 14 + DI_AHBERMSK + 2 1 read-write - WDT_SYS_RESET_LENGTH - System reset signal length selection. 0: 100 ns, 1: 200 ns, -2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - 15 - 3 + TIMEOUTMSK + 3 + 1 read-write - WDT_CPU_RESET_LENGTH - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, -2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - 18 - 3 + INTKNTXFEMPMSK + 4 + 1 read-write - WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - - 23 - 2 + INTKNEPMISMSK + 5 + 1 read-write - WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - - 25 - 2 + INEPNAKEFFMSK + 6 + 1 read-write - WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - - 27 - 2 + TXFIFOUNDRNMSK + 8 + 1 read-write - WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - - 29 - 2 + BNAININTRMSK + 9 + 1 read-write - WDT_EN - When set, MWDT is enabled. - 31 + DI_NAKMSK + 13 1 read-write - WDTCONFIG1 - Watchdog timer prescaler register - 0x4C + DOEPMSK + 0x814 0x20 - 0x00010000 - WDT_CLK_PRESCALE - MWDT clock prescaler value. MWDT clock period = 12.5 ns * -TIMG_WDT_CLK_PRESCALE. - 16 - 16 + XFERCOMPLMSK + 0 + 1 read-write - - - - WDTCONFIG2 - Watchdog timer stage 0 timeout value - 0x50 - 0x20 - 0x018CBA80 - - WDT_STG0_HOLD - Stage 0 timeout value, in MWDT clock cycles. - 0 - 32 + EPDISBLDMSK + 1 + 1 read-write - - - - WDTCONFIG3 - Watchdog timer stage 1 timeout value - 0x54 - 0x20 - 0x07FFFFFF - - WDT_STG1_HOLD - Stage 1 timeout value, in MWDT clock cycles. - 0 - 32 + AHBERMSK + 2 + 1 read-write - - - - WDTCONFIG4 - Watchdog timer stage 2 timeout value - 0x58 - 0x20 - 0x000FFFFF - - WDT_STG2_HOLD - Stage 2 timeout value, in MWDT clock cycles. - 0 - 32 + SETUPMSK + 3 + 1 read-write - - - - WDTCONFIG5 - Watchdog timer stage 3 timeout value - 0x5C - 0x20 - 0x000FFFFF - - WDT_STG3_HOLD - Stage 3 timeout value, in MWDT clock cycles. - 0 - 32 + OUTTKNEPDISMSK + 4 + 1 read-write - - - - WDTFEED - Write to feed the watchdog timer - 0x60 - 0x20 - - WDT_FEED - Write any value to feed the MWDT. (WO) - 0 - 32 - write-only + STSPHSERCVDMSK + 5 + 1 + read-write - - - - WDTWPROTECT - Watchdog write protect register - 0x64 - 0x20 - 0x50D83AA1 - - WDT_WKEY - If the register contains a different value than its reset value, write -protection is enabled. - 0 - 32 + BACK2BACKSETUP + 6 + 1 read-write - - - - RTCCALICFG - RTC calibration configure register - 0x68 - 0x20 - 0x00013000 - - RTC_CALI_START_CYCLING - Reserved - 12 + OUTPKTERRMSK + 8 1 read-write - RTC_CALI_CLK_SEL - 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. - 13 - 2 + BNAOUTINTRMSK + 9 + 1 read-write - RTC_CALI_RDY - Reserved - 15 + BBLEERRMSK + 12 1 - read-only + read-write - RTC_CALI_MAX - Reserved - 16 - 15 + NAKMSK + 13 + 1 read-write - RTC_CALI_START - Reserved - 31 + NYETMSK + 14 1 read-write - RTCCALICFG1 - RTC calibration configure1 register - 0x6C + DAINT + 0x818 0x20 - RTC_CALI_CYCLING_DATA_VLD - Reserved + INEPINT0 0 1 read-only - RTC_CALI_VALUE - Reserved - 7 - 25 + INEPINT1 + 1 + 1 read-only - - - - INT_ENA_TIMERS - Interrupt enable bits - 0x70 - 0x20 - - T0_INT_ENA - The interrupt enable bit for the TIMG_T0_INT interrupt. - 0 + INEPINT2 + 2 1 - read-write + read-only - T1_INT_ENA - The interrupt enable bit for the TIMG_T1_INT interrupt. - 1 + INEPINT3 + 3 1 - read-write + read-only - WDT_INT_ENA - The interrupt enable bit for the TIMG_WDT_INT interrupt. - 2 + INEPINT4 + 4 1 - read-write + read-only - - - - INT_RAW_TIMERS - Raw interrupt status - 0x74 - 0x20 - - T0_INT_RAW - The raw interrupt status bit for the TIMG_T0_INT interrupt. - 0 + INEPINT5 + 5 1 read-only - T1_INT_RAW - The raw interrupt status bit for the TIMG_T1_INT interrupt. - 1 + INEPINT6 + 6 1 read-only - WDT_INT_RAW - The raw interrupt status bit for the TIMG_WDT_INT interrupt. - 2 + OUTEPINT0 + 16 1 read-only - - - - INT_ST_TIMERS - Masked interrupt status - 0x78 - 0x20 - - T0_INT_ST - The masked interrupt status bit for the TIMG_T0_INT interrupt. - 0 + OUTEPINT1 + 17 1 read-only - T1_INT_ST - The masked interrupt status bit for the TIMG_T1_INT interrupt. - 1 + OUTEPINT2 + 18 1 read-only - WDT_INT_ST - The masked interrupt status bit for the TIMG_WDT_INT interrupt. - 2 + OUTEPINT3 + 19 + 1 + read-only + + + OUTEPINT4 + 20 + 1 + read-only + + + OUTEPINT5 + 21 + 1 + read-only + + + OUTEPINT6 + 22 1 read-only - INT_CLR_TIMERS - Interrupt clear bits - 0x7C + DAINTMSK + 0x81C 0x20 - T0_INT_CLR - Set this bit to clear the TIMG_T0_INT interrupt. + INEPMSK0 0 1 - write-only + read-write - T1_INT_CLR - Set this bit to clear the TIMG_T1_INT interrupt. + INEPMSK1 1 1 - write-only + read-write - WDT_INT_CLR - Set this bit to clear the TIMG_WDT_INT interrupt. + INEPMSK2 2 1 - write-only + read-write + + + INEPMSK3 + 3 + 1 + read-write + + + INEPMSK4 + 4 + 1 + read-write + + + INEPMSK5 + 5 + 1 + read-write + + + INEPMSK6 + 6 + 1 + read-write + + + OUTEPMSK0 + 16 + 1 + read-write + + + OUTEPMSK1 + 17 + 1 + read-write + + + OUTEPMSK2 + 18 + 1 + read-write + + + OUTEPMSK3 + 19 + 1 + read-write + + + OUTEPMSK4 + 20 + 1 + read-write + + + OUTEPMSK5 + 21 + 1 + read-write + + + OUTEPMSK6 + 22 + 1 + read-write - RTCCALICFG2 - Timer group calibration register - 0x80 + DVBUSDIS + 0x828 0x20 - 0xFFFFFF98 + 0x000017D7 - RTC_CALI_TIMEOUT - RTC calibration timeout indicator + DVBUSDIS 0 - 1 - read-only - - - RTC_CALI_TIMEOUT_RST_CNT - Cycles that release calibration timeout reset - 3 - 4 + 16 read-write + + + + DVBUSPULSE + 0x82C + 0x20 + 0x000005B8 + - RTC_CALI_TIMEOUT_THRES - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. - 7 - 25 + DVBUSPULSE + 0 + 12 read-write - NTIMERS_DATE - Timer version control register - 0xF8 + DTHRCTL + 0x830 0x20 - 0x02003071 + 0x08020020 - NTIMERS_DATE - Timer version control register + NONISOTHREN 0 - 28 + 1 + read-write + + + ISOTHREN + 1 + 1 + read-write + + + TXTHRLEN + 2 + 9 + read-write + + + AHBTHRRATIO + 11 + 2 + read-write + + + RXTHREN + 16 + 1 + read-write + + + RXTHRLEN + 17 + 9 + read-write + + + ARBPRKEN + 27 + 1 read-write - REGCLK - Timer group clock gate register - 0xFC + DIEPEMPMSK + 0x834 0x20 - CLK_EN - Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens. - 31 - 1 + D_INEPTXFEMPMSK + 0 + 16 read-write - - - - TIMG1 - Timer Group - 0x60020000 - - TG1_T0_LEVEL - 53 - - - TG1_T1_LEVEL - 54 - - - TG1_WDT_LEVEL - 55 - - - - TWAI - Two-Wire Automotive Interface - TWAI - 0x6002B000 - - 0x0 - 0x6C - registers - - - TWAI - 45 - - - MODE - Mode Register - 0x0 + DIEPCTL0 + 0x900 0x20 - 0x00000001 + 0x00008000 - RESET_MODE - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. - 0 + D_MPS0 + 0 + 2 + read-write + + + D_USBACTEP0 + 15 + 1 + read-only + + + D_NAKSTS0 + 17 + 1 + read-only + + + D_EPTYPE0 + 18 + 2 + read-only + + + D_STALL0 + 21 1 read-write - LISTEN_ONLY_MODE - 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. - 1 - 1 + D_TXFNUM0 + 22 + 4 read-write - SELF_TEST_MODE - 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. - 2 + D_CNAK0 + 26 + 1 + write-only + + + DI_SNAK0 + 27 + 1 + write-only + + + D_EPDIS0 + 30 1 read-write - RX_FILTER_MODE - This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. - 3 + D_EPENA0 + 31 1 read-write - CMD - Command Register - 0x4 + DIEPINT0 + 0x908 0x20 - TX_REQ - Set the bit to 1 to allow the driving nodes start transmission. + D_XFERCOMPL0 0 1 - write-only + read-write - ABORT_TX - Set the bit to 1 to cancel a pending transmission request. + D_EPDISBLD0 1 1 - write-only + read-write - RELEASE_BUF - Set the bit to 1 to release the RX buffer. + D_AHBERR0 2 1 - write-only + read-write - CLR_OVERRUN - Set the bit to 1 to clear the data overrun status bit. + D_TIMEOUT0 3 1 - write-only + read-write - SELF_RX_REQ - Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + D_INTKNTXFEMP0 4 1 - write-only + read-write - - - - STATUS - Status register - 0x8 - 0x20 - - RX_BUF_ST - 1: The data in the RX buffer is not empty, with at least one received data packet. - 0 + D_INTKNEPMIS0 + 5 1 - read-only + read-write - OVERRUN_ST - 1: The RX FIFO is full and data overrun has occurred. - 1 + D_INEPNAKEFF0 + 6 1 - read-only + read-write - TX_BUF_ST - 1: The TX buffer is empty, the CPU may write a message into it. - 2 + D_TXFEMP0 + 7 1 read-only - TX_COMPLETE - 1: The TWAI controller has successfully received a packet from the bus. - 3 + D_TXFIFOUNDRN0 + 8 1 - read-only + read-write - RX_ST - 1: The TWAI Controller is receiving a message from the bus. - 4 + D_BNAINTR0 + 9 1 - read-only + read-write - TX_ST - 1: The TWAI Controller is transmitting a message to the bus. - 5 + D_PKTDRPSTS0 + 11 1 - read-only + read-write - ERR_ST - 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. - 6 + D_BBLEERR0 + 12 1 - read-only + read-write - BUS_OFF_ST - 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. - 7 + D_NAKINTRPT0 + 13 1 - read-only + read-write - MISS_ST - This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete - 8 + D_NYETINTRPT0 + 14 1 + read-write + + + + + DIEPTSIZ0 + 0x910 + 0x20 + + + D_XFERSIZE0 + 0 + 7 + read-write + + + D_PKTCNT0 + 19 + 2 + read-write + + + + + DIEPDMA0 + 0x914 + 0x20 + + + D_DMAADDR0 + 0 + 32 + read-write + + + + + DTXFSTS0 + 0x918 + 0x20 + + + D_INEPTXFSPCAVAIL0 + 0 + 16 read-only - INT_RAW - Interrupt Register - 0xC + DIEPDMAB0 + 0x91C 0x20 - RX_INT_ST - Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + D_DMABUFFERADDR0 0 - 1 + 32 read-only + + + + DIEPCTL1 + 0x920 + 0x20 + 0x00008000 + + + D_MPS1 + 0 + 2 + read-write + - TX_INT_ST - Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. - 1 + D_USBACTEP1 + 15 1 read-only - ERR_WARN_INT_ST - Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). - 2 + D_NAKSTS1 + 17 1 read-only - OVERRUN_INT_ST - Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. - 3 - 1 + D_EPTYPE1 + 18 + 2 read-only - ERR_PASSIVE_INT_ST - Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. - 5 + D_STALL1 + 21 1 - read-only + read-write - ARB_LOST_INT_ST - Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. - 6 + D_TXFNUM1 + 22 + 4 + read-write + + + D_CNAK1 + 26 1 - read-only + write-only - BUS_ERR_INT_ST - Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. - 7 + DI_SNAK1 + 27 1 - read-only + write-only + + + DI_SETD0PID1 + 28 + 1 + write-only + + + DI_SETD1PID1 + 29 + 1 + write-only + + + D_EPDIS1 + 30 + 1 + read-write + + + D_EPENA1 + 31 + 1 + read-write - INT_ENA - Interrupt Enable Register - 0x10 + DIEPINT1 + 0x928 0x20 - RX_INT_ENA - Set this bit to 1 to enable receive interrupt. + D_XFERCOMPL1 0 1 read-write - TX_INT_ENA - Set this bit to 1 to enable transmit interrupt. + D_EPDISBLD1 1 1 read-write - ERR_WARN_INT_ENA - Set this bit to 1 to enable error warning interrupt. + D_AHBERR1 2 1 read-write - OVERRUN_INT_ENA - Set this bit to 1 to enable data overrun interrupt. + D_TIMEOUT1 3 1 read-write - ERR_PASSIVE_INT_ENA - Set this bit to 1 to enable error passive interrupt. + D_INTKNTXFEMP1 + 4 + 1 + read-write + + + D_INTKNEPMIS1 5 1 read-write - ARB_LOST_INT_ENA - Set this bit to 1 to enable arbitration lost interrupt. + D_INEPNAKEFF1 6 1 read-write - BUS_ERR_INT_ENA - Set this bit to 1 to enable error interrupt. + D_TXFEMP1 7 1 - read-write + read-only - - - - BUS_TIMING_0 - Bus Timing Register 0 - 0x18 - 0x20 - - BAUD_PRESC - Baud Rate Prescaler, determines the frequency dividing ratio. - 0 - 13 + D_TXFIFOUNDRN1 + 8 + 1 + read-write - SYNC_JUMP_WIDTH - Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. - 14 - 2 + D_BNAINTR1 + 9 + 1 + read-write - - - - BUS_TIMING_1 - Bus Timing Register 1 - 0x1C - 0x20 - - TIME_SEG1 - The width of PBS1. - 0 - 4 + D_PKTDRPSTS1 + 11 + 1 + read-write - TIME_SEG2 - The width of PBS2. - 4 - 3 + D_BBLEERR1 + 12 + 1 + read-write - TIME_SAMP - The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times - 7 + D_NAKINTRPT1 + 13 1 + read-write - - - - ARB_LOST_CAP - Arbitration Lost Capture Register - 0x2C - 0x20 - - ARB_LOST_CAP - This register contains information about the bit position of lost arbitration. - 0 - 5 - read-only + D_NYETINTRPT1 + 14 + 1 + read-write - ERR_CODE_CAP - Error Code Capture Register - 0x30 + DIEPTSIZ1 + 0x930 0x20 - ECC_SEGMENT - This register contains information about the location of errors, see Table 181 for details. + D_XFERSIZE1 0 - 5 - read-only - - - ECC_DIRECTION - This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message - 5 - 1 - read-only + 7 + read-write - ECC_TYPE - This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error - 6 + D_PKTCNT1 + 19 2 - read-only + read-write - ERR_WARNING_LIMIT - Error Warning Limit Register - 0x34 + DIEPDMA1 + 0x934 0x20 - 0x00000060 - ERR_WARNING_LIMIT - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + D_DMAADDR1 0 - 8 + 32 + read-write - RX_ERR_CNT - Receive Error Counter Register - 0x38 + DTXFSTS1 + 0x938 0x20 - RX_ERR_CNT - The RX error counter register, reflects value changes under reception status. + D_INEPTXFSPCAVAIL1 0 - 8 + 16 + read-only - TX_ERR_CNT - Transmit Error Counter Register - 0x3C + DIEPDMAB1 + 0x93C 0x20 - TX_ERR_CNT - The TX error counter register, reflects value changes under transmission status. + D_DMABUFFERADDR1 0 - 8 + 32 + read-only - DATA_0 - Data register 0 - 0x40 + DIEPCTL2 + 0x940 0x20 + 0x00008000 - TX_BYTE_0 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + D_MPS2 0 - 8 + 2 + read-write + + + D_USBACTEP2 + 15 + 1 + read-only + + + D_NAKSTS2 + 17 + 1 + read-only + + + D_EPTYPE2 + 18 + 2 + read-only + + + D_STALL2 + 21 + 1 + read-write + + + D_TXFNUM2 + 22 + 4 + read-write + + + D_CNAK2 + 26 + 1 write-only - - - - DATA_1 - Data register 1 - 0x44 - 0x20 - - TX_BYTE_1 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. - 0 - 8 + DI_SNAK2 + 27 + 1 + write-only + + + DI_SETD0PID2 + 28 + 1 write-only + + DI_SETD1PID2 + 29 + 1 + write-only + + + D_EPDIS2 + 30 + 1 + read-write + + + D_EPENA2 + 31 + 1 + read-write + - DATA_2 - Data register 2 - 0x48 + DIEPINT2 + 0x948 0x20 - TX_BYTE_2 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + D_XFERCOMPL2 0 - 8 - write-only + 1 + read-write + + + D_EPDISBLD2 + 1 + 1 + read-write + + + D_AHBERR2 + 2 + 1 + read-write + + + D_TIMEOUT2 + 3 + 1 + read-write + + + D_INTKNTXFEMP2 + 4 + 1 + read-write + + + D_INTKNEPMIS2 + 5 + 1 + read-write + + + D_INEPNAKEFF2 + 6 + 1 + read-write + + + D_TXFEMP2 + 7 + 1 + read-only + + + D_TXFIFOUNDRN2 + 8 + 1 + read-write + + + D_BNAINTR2 + 9 + 1 + read-write + + + D_PKTDRPSTS2 + 11 + 1 + read-write + + + D_BBLEERR2 + 12 + 1 + read-write + + + D_NAKINTRPT2 + 13 + 1 + read-write + + + D_NYETINTRPT2 + 14 + 1 + read-write - DATA_3 - Data register 3 - 0x4C + DIEPTSIZ2 + 0x950 0x20 - TX_BYTE_3 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + D_XFERSIZE2 0 - 8 - write-only + 7 + read-write - - - - DATA_4 - Data register 4 - 0x50 - 0x20 - - TX_BYTE_4 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. - 0 - 8 - write-only + D_PKTCNT2 + 19 + 2 + read-write - DATA_5 - Data register 5 - 0x54 + DIEPDMA2 + 0x954 0x20 - TX_BYTE_5 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + D_DMAADDR2 0 - 8 - write-only + 32 + read-write - DATA_6 - Data register 6 - 0x58 + DTXFSTS2 + 0x958 0x20 - TX_BYTE_6 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + D_INEPTXFSPCAVAIL2 0 - 8 - write-only + 16 + read-only - DATA_7 - Data register 7 - 0x5C + DIEPDMAB2 + 0x95C 0x20 - TX_BYTE_7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + D_DMABUFFERADDR2 0 - 8 - write-only + 32 + read-only - DATA_8 - Data register 8 - 0x60 + DIEPCTL3 + 0x960 0x20 + 0x00008000 - TX_BYTE_8 - Stored the 8th byte information of the data to be transmitted under operating mode. + DI_MPS3 0 - 8 - write-only + 2 + read-write - - - - DATA_9 - Data register 9 - 0x64 - 0x20 - - TX_BYTE_9 - Stored the 9th byte information of the data to be transmitted under operating mode. - 0 - 8 - write-only + DI_USBACTEP3 + 15 + 1 + read-only - - - - DATA_10 - Data register 10 - 0x68 - 0x20 - - TX_BYTE_10 - Stored the 10th byte information of the data to be transmitted under operating mode. - 0 - 8 - write-only + DI_NAKSTS3 + 17 + 1 + read-only - - - - DATA_11 - Data register 11 - 0x6C - 0x20 - - TX_BYTE_11 - Stored the 11th byte information of the data to be transmitted under operating mode. - 0 - 8 + DI_EPTYPE3 + 18 + 2 + read-only + + + DI_STALL3 + 21 + 1 + read-write + + + DI_TXFNUM3 + 22 + 4 + read-write + + + DI_CNAK3 + 26 + 1 write-only - - - - DATA_12 - Data register 12 - 0x70 - 0x20 - - TX_BYTE_12 - Stored the 12th byte information of the data to be transmitted under operating mode. - 0 - 8 + DI_SNAK3 + 27 + 1 write-only - - - - RX_MESSAGE_CNT - Receive Message Counter Register - 0x74 - 0x20 - - RX_MESSAGE_COUNTER - This register reflects the number of messages available within the RX FIFO. - 0 - 7 - read-only + DI_SETD0PID3 + 28 + 1 + write-only - - - - CLOCK_DIVIDER - Clock Divider register - 0x7C - 0x20 - - CD - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. - 0 - 8 - read-write + DI_SETD1PID3 + 29 + 1 + write-only - CLOCK_OFF - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin - 8 + DI_EPDIS3 + 30 1 + read-write - - - - - - UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller - UART - 0x60000000 - - 0x0 - 0x84 - registers - - - UART0 - 27 - - - - FIFO - FIFO data register - 0x0 - 0x20 - - RXFIFO_RD_BYTE - UART 0 accesses FIFO via this register. - 0 - 8 + DI_EPENA3 + 31 + 1 read-write - INT_RAW - Raw interrupt status - 0x4 + DIEPINT3 + 0x968 0x20 - 0x00000002 - RXFIFO_FULL_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + D_XFERCOMPL3 0 1 - read-only + read-write - TXFIFO_EMPTY_INT_RAW - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + D_EPDISBLD3 1 1 - read-only + read-write - PARITY_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a parity error in the data. + D_AHBERR3 2 1 - read-only + read-write - FRM_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a data frame error . + D_TIMEOUT3 3 1 - read-only + read-write - RXFIFO_OVF_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + D_INTKNTXFEMP3 4 1 - read-only + read-write - DSR_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + D_INTKNEPMIS3 5 1 - read-only + read-write - CTS_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + D_INEPNAKEFF3 6 1 - read-only + read-write - BRK_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + D_TXFEMP3 7 1 read-only - RXFIFO_TOUT_INT_RAW - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + D_TXFIFOUNDRN3 8 1 - read-only + read-write - SW_XON_INT_RAW - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + D_BNAINTR3 9 1 - read-only - - - SW_XOFF_INT_RAW - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. - 10 - 1 - read-only + read-write - GLITCH_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + D_PKTDRPSTS3 11 1 - read-only + read-write - TX_BRK_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + D_BBLEERR3 12 1 - read-only + read-write - TX_BRK_IDLE_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + D_NAKINTRPT3 13 1 - read-only + read-write - TX_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + D_NYETINTRPT3 14 1 - read-only + read-write + + + + DIEPTSIZ3 + 0x970 + 0x20 + - RS485_PARITY_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. - 15 - 1 - read-only + D_XFERSIZE3 + 0 + 7 + read-write - RS485_FRM_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. - 16 - 1 - read-only + D_PKTCNT3 + 19 + 2 + read-write + + + + DIEPDMA3 + 0x974 + 0x20 + - RS485_CLASH_INT_RAW - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. - 17 - 1 - read-only + D_DMAADDR3 + 0 + 32 + read-write + + + + DTXFSTS3 + 0x978 + 0x20 + - AT_CMD_CHAR_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. - 18 - 1 + D_INEPTXFSPCAVAIL3 + 0 + 16 read-only + + + + DIEPDMAB3 + 0x97C + 0x20 + - WAKEUP_INT_RAW - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. - 19 - 1 + D_DMABUFFERADDR3 + 0 + 32 read-only - INT_ST - Masked interrupt status - 0x8 + DIEPCTL4 + 0x980 0x20 + 0x00008000 - RXFIFO_FULL_INT_ST - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + D_MPS4 0 - 1 - read-only + 2 + read-write - TXFIFO_EMPTY_INT_ST - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. - 1 + D_USBACTEP4 + 15 1 read-only - PARITY_ERR_INT_ST - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - 2 + D_NAKSTS4 + 17 1 read-only - FRM_ERR_INT_ST - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - 3 - 1 + D_EPTYPE4 + 18 + 2 read-only - RXFIFO_OVF_INT_ST - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - 4 + D_STALL4 + 21 1 - read-only + read-write - DSR_CHG_INT_ST - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - 5 - 1 - read-only + D_TXFNUM4 + 22 + 4 + read-write - CTS_CHG_INT_ST - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - 6 + D_CNAK4 + 26 1 - read-only + write-only - BRK_DET_INT_ST - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - 7 + DI_SNAK4 + 27 1 - read-only + write-only - RXFIFO_TOUT_INT_ST - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - 8 + DI_SETD0PID4 + 28 1 - read-only + write-only - SW_XON_INT_ST - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - 9 + DI_SETD1PID4 + 29 1 - read-only + write-only - SW_XOFF_INT_ST - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - 10 + D_EPDIS4 + 30 1 - read-only + read-write - GLITCH_DET_INT_ST - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - 11 + D_EPENA4 + 31 1 - read-only + read-write + + + + DIEPINT4 + 0x988 + 0x20 + - TX_BRK_DONE_INT_ST - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - 12 + D_XFERCOMPL4 + 0 1 - read-only + read-write - TX_BRK_IDLE_DONE_INT_ST - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. - 13 + D_EPDISBLD4 + 1 1 - read-only + read-write - TX_DONE_INT_ST - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - 14 + D_AHBERR4 + 2 1 - read-only + read-write - RS485_PARITY_ERR_INT_ST - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. - 15 + D_TIMEOUT4 + 3 1 - read-only + read-write - RS485_FRM_ERR_INT_ST - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. - 16 + D_INTKNTXFEMP4 + 4 1 - read-only + read-write - RS485_CLASH_INT_ST - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - 17 + D_INTKNEPMIS4 + 5 1 - read-only + read-write - AT_CMD_CHAR_DET_INT_ST - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. - 18 + D_INEPNAKEFF4 + 6 1 - read-only + read-write - WAKEUP_INT_ST - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - 19 + D_TXFEMP4 + 7 1 read-only - - - - INT_ENA - Interrupt enable bits - 0xC - 0x20 - - RXFIFO_FULL_INT_ENA - This is the enable bit for rxfifo_full_int_st register. - 0 + D_TXFIFOUNDRN4 + 8 1 read-write - TXFIFO_EMPTY_INT_ENA - This is the enable bit for txfifo_empty_int_st register. - 1 + D_BNAINTR4 + 9 1 read-write - PARITY_ERR_INT_ENA - This is the enable bit for parity_err_int_st register. - 2 + D_PKTDRPSTS4 + 11 1 read-write - FRM_ERR_INT_ENA - This is the enable bit for frm_err_int_st register. - 3 + D_BBLEERR4 + 12 1 read-write - RXFIFO_OVF_INT_ENA - This is the enable bit for rxfifo_ovf_int_st register. - 4 + D_NAKINTRPT4 + 13 1 read-write - DSR_CHG_INT_ENA - This is the enable bit for dsr_chg_int_st register. - 5 + D_NYETINTRPT4 + 14 1 read-write + + + + DIEPTSIZ4 + 0x990 + 0x20 + + + D_XFERSIZE4 + 0 + 7 + read-write + + + D_PKTCNT4 + 19 + 2 + read-write + + + + + DIEPDMA4 + 0x994 + 0x20 + - CTS_CHG_INT_ENA - This is the enable bit for cts_chg_int_st register. - 6 - 1 + D_DMAADDR4 + 0 + 32 read-write + + + + DTXFSTS4 + 0x998 + 0x20 + - BRK_DET_INT_ENA - This is the enable bit for brk_det_int_st register. - 7 - 1 - read-write + D_INEPTXFSPCAVAIL4 + 0 + 16 + read-only + + + + DIEPDMAB4 + 0x99C + 0x20 + - RXFIFO_TOUT_INT_ENA - This is the enable bit for rxfifo_tout_int_st register. - 8 - 1 - read-write + D_DMABUFFERADDR4 + 0 + 32 + read-only + + + + DIEPCTL5 + 0x9A0 + 0x20 + 0x00008000 + - SW_XON_INT_ENA - This is the enable bit for sw_xon_int_st register. - 9 - 1 + DI_MPS5 + 0 + 2 read-write - SW_XOFF_INT_ENA - This is the enable bit for sw_xoff_int_st register. - 10 + DI_USBACTEP5 + 15 1 - read-write + read-only - GLITCH_DET_INT_ENA - This is the enable bit for glitch_det_int_st register. - 11 + DI_NAKSTS5 + 17 1 - read-write + read-only - TX_BRK_DONE_INT_ENA - This is the enable bit for tx_brk_done_int_st register. - 12 + DI_EPTYPE5 + 18 + 2 + read-only + + + DI_STALL5 + 21 1 read-write - TX_BRK_IDLE_DONE_INT_ENA - This is the enable bit for tx_brk_idle_done_int_st register. - 13 - 1 + DI_TXFNUM5 + 22 + 4 read-write - TX_DONE_INT_ENA - This is the enable bit for tx_done_int_st register. - 14 + DI_CNAK5 + 26 1 - read-write + write-only - RS485_PARITY_ERR_INT_ENA - This is the enable bit for rs485_parity_err_int_st register. - 15 + DI_SNAK5 + 27 1 - read-write + write-only - RS485_FRM_ERR_INT_ENA - This is the enable bit for rs485_parity_err_int_st register. - 16 + DI_SETD0PID5 + 28 1 - read-write + write-only - RS485_CLASH_INT_ENA - This is the enable bit for rs485_clash_int_st register. - 17 + DI_SETD1PID5 + 29 1 - read-write + write-only - AT_CMD_CHAR_DET_INT_ENA - This is the enable bit for at_cmd_char_det_int_st register. - 18 + DI_EPDIS5 + 30 1 read-write - WAKEUP_INT_ENA - This is the enable bit for uart_wakeup_int_st register. - 19 + DI_EPENA5 + 31 1 read-write - INT_CLR - Interrupt clear bits - 0x10 + DIEPINT5 + 0x9A8 0x20 - RXFIFO_FULL_INT_CLR - Set this bit to clear the rxfifo_full_int_raw interrupt. + D_XFERCOMPL5 0 1 - write-only + read-write - TXFIFO_EMPTY_INT_CLR - Set this bit to clear txfifo_empty_int_raw interrupt. + D_EPDISBLD5 1 1 - write-only + read-write - PARITY_ERR_INT_CLR - Set this bit to clear parity_err_int_raw interrupt. + D_AHBERR5 2 1 - write-only + read-write - FRM_ERR_INT_CLR - Set this bit to clear frm_err_int_raw interrupt. + D_TIMEOUT5 3 1 - write-only + read-write - RXFIFO_OVF_INT_CLR - Set this bit to clear rxfifo_ovf_int_raw interrupt. + D_INTKNTXFEMP5 4 1 - write-only + read-write - DSR_CHG_INT_CLR - Set this bit to clear the dsr_chg_int_raw interrupt. + D_INTKNEPMIS5 5 1 - write-only + read-write - CTS_CHG_INT_CLR - Set this bit to clear the cts_chg_int_raw interrupt. + D_INEPNAKEFF5 6 1 - write-only + read-write - BRK_DET_INT_CLR - Set this bit to clear the brk_det_int_raw interrupt. + D_TXFEMP5 7 1 - write-only + read-only - RXFIFO_TOUT_INT_CLR - Set this bit to clear the rxfifo_tout_int_raw interrupt. + D_TXFIFOUNDRN5 8 1 - write-only + read-write - SW_XON_INT_CLR - Set this bit to clear the sw_xon_int_raw interrupt. + D_BNAINTR5 9 1 - write-only - - - SW_XOFF_INT_CLR - Set this bit to clear the sw_xoff_int_raw interrupt. - 10 - 1 - write-only + read-write - GLITCH_DET_INT_CLR - Set this bit to clear the glitch_det_int_raw interrupt. + D_PKTDRPSTS5 11 1 - write-only + read-write - TX_BRK_DONE_INT_CLR - Set this bit to clear the tx_brk_done_int_raw interrupt.. + D_BBLEERR5 12 1 - write-only + read-write - TX_BRK_IDLE_DONE_INT_CLR - Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + D_NAKINTRPT5 13 1 - write-only + read-write - TX_DONE_INT_CLR - Set this bit to clear the tx_done_int_raw interrupt. + D_NYETINTRPT5 14 1 - write-only - - - RS485_PARITY_ERR_INT_CLR - Set this bit to clear the rs485_parity_err_int_raw interrupt. - 15 - 1 - write-only - - - RS485_FRM_ERR_INT_CLR - Set this bit to clear the rs485_frm_err_int_raw interrupt. - 16 - 1 - write-only - - - RS485_CLASH_INT_CLR - Set this bit to clear the rs485_clash_int_raw interrupt. - 17 - 1 - write-only - - - AT_CMD_CHAR_DET_INT_CLR - Set this bit to clear the at_cmd_char_det_int_raw interrupt. - 18 - 1 - write-only - - - WAKEUP_INT_CLR - Set this bit to clear the uart_wakeup_int_raw interrupt. - 19 - 1 - write-only + read-write - CLKDIV - Clock divider configuration - 0x14 + DIEPTSIZ5 + 0x9B0 0x20 - 0x000002B6 - CLKDIV - The integral part of the frequency divider factor. + D_XFERSIZE5 0 - 12 + 7 read-write - FRAG - The decimal part of the frequency divider factor. - 20 - 4 + D_PKTCNT5 + 19 + 2 read-write - RX_FILT - Rx Filter configuration - 0x18 + DIEPDMA5 + 0x9B4 0x20 - 0x00000008 - GLITCH_FILT - when input pulse width is lower than this value, the pulse is ignored. + D_DMAADDR5 0 - 8 + 32 read-write + + + + DTXFSTS5 + 0x9B8 + 0x20 + - GLITCH_FILT_EN - Set this bit to enable Rx signal filter. - 8 - 1 - read-write + D_INEPTXFSPCAVAIL5 + 0 + 16 + read-only - STATUS - UART status register - 0x1C + DIEPDMAB5 + 0x9BC 0x20 - 0xE000C000 - RXFIFO_CNT - Stores the byte number of valid data in Rx-FIFO. + D_DMABUFFERADDR5 0 - 10 + 32 read-only + + + + DIEPCTL6 + 0x9C0 + 0x20 + 0x00008000 + + + D_MPS6 + 0 + 2 + read-write + - DSRN - The register represent the level value of the internal uart dsr signal. - 13 + D_USBACTEP6 + 15 1 read-only - CTSN - This register represent the level value of the internal uart cts signal. - 14 + D_NAKSTS6 + 17 1 read-only - RXD - This register represent the level value of the internal uart rxd signal. - 15 - 1 + D_EPTYPE6 + 18 + 2 read-only - TXFIFO_CNT - Stores the byte number of data in Tx-FIFO. - 16 - 10 - read-only + D_STALL6 + 21 + 1 + read-write - DTRN - This bit represents the level of the internal uart dtr signal. + D_TXFNUM6 + 22 + 4 + read-write + + + D_CNAK6 + 26 + 1 + write-only + + + DI_SNAK6 + 27 + 1 + write-only + + + DI_SETD0PID6 + 28 + 1 + write-only + + + DI_SETD1PID6 29 1 - read-only + write-only - RTSN - This bit represents the level of the internal uart rts signal. + D_EPDIS6 30 1 - read-only + read-write - TXD - This bit represents the level of the internal uart txd signal. + D_EPENA6 31 1 - read-only + read-write - CONF0 - a - 0x20 + DIEPINT6 + 0x9C8 0x20 - 0x1000001C - PARITY - This register is used to configure the parity check mode. + D_XFERCOMPL6 0 1 read-write - PARITY_EN - Set this bit to enable uart parity check. + D_EPDISBLD6 1 1 read-write - BIT_NUM - This register is used to set the length of data. + D_AHBERR6 2 - 2 + 1 read-write - STOP_BIT_NUM - This register is used to set the length of stop bit. - 4 - 2 + D_TIMEOUT6 + 3 + 1 read-write - SW_RTS - This register is used to configure the software rts signal which is used in software flow control. - 6 + D_INTKNTXFEMP6 + 4 1 read-write - SW_DTR - This register is used to configure the software dtr signal which is used in software flow control. - 7 + D_INTKNEPMIS6 + 5 1 read-write - TXD_BRK - Set this bit to enbale transmitter to send NULL when the process of sending data is done. - 8 + D_INEPNAKEFF6 + 6 1 read-write - IRDA_DPLX - Set this bit to enable IrDA loopback mode. - 9 + D_TXFEMP6 + 7 + 1 + read-only + + + D_TXFIFOUNDRN6 + 8 1 read-write - IRDA_TX_EN - This is the start enable bit for IrDA transmitter. - 10 + D_BNAINTR6 + 9 1 read-write - IRDA_WCTL - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + D_PKTDRPSTS6 11 1 read-write - IRDA_TX_INV - Set this bit to invert the level of IrDA transmitter. + D_BBLEERR6 12 1 read-write - IRDA_RX_INV - Set this bit to invert the level of IrDA receiver. + D_NAKINTRPT6 13 1 read-write - LOOPBACK - Set this bit to enable uart loopback test mode. + D_NYETINTRPT6 14 1 read-write + + + + DIEPTSIZ6 + 0x9D0 + 0x20 + - TX_FLOW_EN - Set this bit to enable flow control function for transmitter. - 15 - 1 + D_XFERSIZE6 + 0 + 7 read-write - IRDA_EN - Set this bit to enable IrDA protocol. - 16 - 1 + D_PKTCNT6 + 19 + 2 read-write + + + + DIEPDMA6 + 0x9D4 + 0x20 + - RXFIFO_RST - Set this bit to reset the uart receive-FIFO. + D_DMAADDR6 + 0 + 32 + read-write + + + + + DTXFSTS6 + 0x9D8 + 0x20 + + + D_INEPTXFSPCAVAIL6 + 0 + 16 + read-only + + + + + DIEPDMAB6 + 0x9DC + 0x20 + + + D_DMABUFFERADDR6 + 0 + 32 + read-only + + + + + DOEPCTL0 + 0xB00 + 0x20 + 0x00008000 + + + MPS0 + 0 + 2 + read-only + + + USBACTEP0 + 15 + 1 + read-only + + + NAKSTS0 17 1 - read-write + read-only - TXFIFO_RST - Set this bit to reset the uart transmit-FIFO. + EPTYPE0 18 + 2 + read-only + + + SNP0 + 20 1 read-write - RXD_INV - Set this bit to inverse the level value of uart rxd signal. - 19 + STALL0 + 21 1 read-write - CTS_INV - Set this bit to inverse the level value of uart cts signal. - 20 + CNAK0 + 26 1 - read-write + write-only - DSR_INV - Set this bit to inverse the level value of uart dsr signal. - 21 + DO_SNAK0 + 27 + 1 + write-only + + + EPDIS0 + 30 + 1 + read-only + + + EPENA0 + 31 1 read-write + + + + DOEPINT0 + 0xB08 + 0x20 + - TXD_INV - Set this bit to inverse the level value of uart txd signal. - 22 + XFERCOMPL0 + 0 1 read-write - RTS_INV - Set this bit to inverse the level value of uart rts signal. - 23 + EPDISBLD0 + 1 1 read-write - DTR_INV - Set this bit to inverse the level value of uart dtr signal. - 24 + AHBERR0 + 2 1 read-write - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 25 + SETUP0 + 3 1 read-write - ERR_WR_MASK - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. - 26 + OUTTKNEPDIS0 + 4 1 read-write - AUTOBAUD_EN - This is the enable bit for detecting baudrate. - 27 + STSPHSERCVD0 + 5 1 read-write - MEM_CLK_EN - UART memory clock gate enable signal. - 28 + BACK2BACKSETUP0 + 6 + 1 + read-write + + + OUTPKTERR0 + 8 1 read-write - - - - CONF1 - Configuration register 1 - 0x24 - 0x20 - 0x00018060 - - RXFIFO_FULL_THRHD - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. - 0 - 10 + BNAINTR0 + 9 + 1 read-write - TXFIFO_EMPTY_THRHD - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. - 10 - 10 + PKTDRPSTS0 + 11 + 1 read-write - DIS_RX_DAT_OVF - Disable UART Rx data overflow detect. - 20 + BBLEERR0 + 12 1 read-write - RX_TOUT_FLOW_DIS - Set this bit to stop accumulating idle_cnt when hardware flow control works. - 21 + NAKINTRPT0 + 13 1 read-write - RX_FLOW_EN - This is the flow enable bit for UART receiver. - 22 + NYEPINTRPT0 + 14 1 read-write - RX_TOUT_EN - This is the enble bit for uart receiver's timeout function. - 23 + STUPPKTRCVD0 + 15 1 read-write - LOWPULSE - Autobaud minimum low pulse duration register - 0x28 + DOEPTSIZ0 + 0xB10 0x20 - 0x00000FFF - MIN_CNT - This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + XFERSIZE0 0 - 12 - read-only + 7 + read-write + + + PKTCNT0 + 19 + 1 + read-write + + + SUPCNT0 + 29 + 2 + read-write - HIGHPULSE - Autobaud minimum high pulse duration register - 0x2C + DOEPDMA0 + 0xB14 0x20 - 0x00000FFF - MIN_CNT - This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + DMAADDR0 0 - 12 - read-only + 32 + read-write - RXD_CNT - Autobaud edge change count register - 0x30 + DOEPDMAB0 + 0xB1C 0x20 - RXD_EDGE_CNT - This register stores the count of rxd edge change. It is used in baud rate-detect process. + DMABUFFERADDR0 0 - 10 - read-only + 32 + read-write - FLOW_CONF - Software flow-control configuration - 0x34 + DOEPCTL1 + 0xB20 0x20 + 0x00008000 - SW_FLOW_CON_EN - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + MPS1 0 + 11 + read-only + + + USBACTEP1 + 15 1 - read-write + read-only - XONOFF_DEL - Set this bit to remove flow control char from the received data. - 1 + NAKSTS1 + 17 1 - read-write + read-only - FORCE_XON - Set this bit to enable the transmitter to go on sending data. - 2 + EPTYPE1 + 18 + 2 + read-only + + + SNP1 + 20 1 read-write - FORCE_XOFF - Set this bit to stop the transmitter from sending data. - 3 + STALL1 + 21 1 read-write - SEND_XON - Set this bit to send Xon char. It is cleared by hardware automatically. - 4 + CNAK1 + 26 1 - read-write + write-only - SEND_XOFF - Set this bit to send Xoff char. It is cleared by hardware automatically. - 5 + DO_SNAK1 + 27 1 - read-write + write-only - - - - SLEEP_CONF - Sleep-mode configuration - 0x38 - 0x20 - 0x000000F0 - - ACTIVE_THRESHOLD - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. - 0 - 10 + DO_SETD0PID1 + 28 + 1 + write-only + + + DO_SETD1PID1 + 29 + 1 + write-only + + + EPDIS1 + 30 + 1 + read-only + + + EPENA1 + 31 + 1 read-write - SWFC_CONF0 - Software flow-control character configuration - 0x3C + DOEPINT1 + 0xB28 0x20 - 0x00004CE0 - XOFF_THRESHOLD - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + XFERCOMPL1 0 - 10 + 1 read-write - XOFF_CHAR - This register stores the Xoff flow control char. - 10 - 8 + EPDISBLD1 + 1 + 1 read-write - - - - SWFC_CONF1 - Software flow-control character configuration - 0x40 - 0x20 - 0x00004400 - - XON_THRESHOLD - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. - 0 - 10 + AHBERR1 + 2 + 1 read-write - XON_CHAR - This register stores the Xon flow control char. - 10 - 8 + SETUP1 + 3 + 1 read-write - - - - TXBRK_CONF - Tx Break character configuration - 0x44 - 0x20 - 0x0000000A - - TX_BRK_NUM - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. - 0 - 8 + OUTTKNEPDIS1 + 4 + 1 read-write - - - - IDLE_CONF - Frame-end idle configuration - 0x48 - 0x20 - 0x00040100 - - RX_IDLE_THRHD - It will produce frame end signal when receiver takes more time to receive one byte data than this register value. - 0 - 10 + STSPHSERCVD1 + 5 + 1 read-write - TX_IDLE_NUM - This register is used to configure the duration time between transfers. - 10 - 10 + BACK2BACKSETUP1 + 6 + 1 read-write - - - - RS485_CONF - RS485 mode configuration - 0x4C - 0x20 - - RS485_EN - Set this bit to choose the rs485 mode. - 0 + OUTPKTERR1 + 8 1 read-write - DL0_EN - Set this bit to delay the stop bit by 1 bit. - 1 + BNAINTR1 + 9 1 read-write - DL1_EN - Set this bit to delay the stop bit by 1 bit. - 2 + PKTDRPSTS1 + 11 1 read-write - RS485TX_RX_EN - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. - 3 + BBLEERR1 + 12 1 read-write - RS485RXBY_TX_EN - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - 4 + NAKINTRPT1 + 13 1 read-write - RS485_RX_DLY_NUM - This register is used to delay the receiver's internal data signal. - 5 + NYEPINTRPT1 + 14 1 read-write - RS485_TX_DLY_NUM - This register is used to delay the transmitter's internal data signal. - 6 - 4 + STUPPKTRCVD1 + 15 + 1 read-write - AT_CMD_PRECNT - Pre-sequence timing configuration - 0x50 + DOEPTSIZ1 + 0xB30 0x20 - 0x00000901 - PRE_IDLE_NUM - This register is used to configure the idle duration time before the first at_cmd is received by receiver. + XFERSIZE1 0 - 16 + 7 + read-write + + + PKTCNT1 + 19 + 1 + read-write + + + SUPCNT1 + 29 + 2 read-write - AT_CMD_POSTCNT - Post-sequence timing configuration - 0x54 + DOEPDMA1 + 0xB34 0x20 - 0x00000901 - POST_IDLE_NUM - This register is used to configure the duration time between the last at_cmd and the next data. + DMAADDR1 0 - 16 + 32 read-write - AT_CMD_GAPTOUT - Timeout configuration - 0x58 + DOEPDMAB1 + 0xB3C 0x20 - 0x0000000B - RX_GAP_TOUT - This register is used to configure the duration time between the at_cmd chars. + DMABUFFERADDR1 0 - 16 + 32 read-write - AT_CMD_CHAR - AT escape sequence detection configuration - 0x5C + DOEPCTL2 + 0xB40 0x20 - 0x0000032B + 0x00008000 - AT_CMD_CHAR - This register is used to configure the content of at_cmd char. + MPS2 0 - 8 - read-write + 11 + read-only - CHAR_NUM - This register is used to configure the num of continuous at_cmd chars received by receiver. - 8 - 8 - read-write + USBACTEP2 + 15 + 1 + read-only - - - - MEM_CONF - UART threshold and allocation configuration - 0x60 - 0x20 - 0x00140012 - - RX_SIZE - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. - 1 - 3 - read-write + NAKSTS2 + 17 + 1 + read-only - TX_SIZE - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. - 4 - 3 - read-write + EPTYPE2 + 18 + 2 + read-only - RX_FLOW_THRHD - This register is used to configure the maximum amount of data that can be received when hardware flow control works. - 7 - 10 + SNP2 + 20 + 1 read-write - RX_TOUT_THRHD - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. - 17 - 10 + STALL2 + 21 + 1 read-write - MEM_FORCE_PD - Set this bit to force power down UART memory. + CNAK2 + 26 + 1 + write-only + + + DO_SNAK2 27 1 - read-write + write-only - MEM_FORCE_PU - Set this bit to force power up UART memory. + DO_SETD0PID2 28 1 - read-write + write-only - - - - MEM_TX_STATUS - Tx-FIFO write and read offset address. - 0x64 - 0x20 - - APB_TX_WADDR - This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. - 0 - 10 - read-only + DO_SETD1PID2 + 29 + 1 + write-only - TX_RADDR - This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. - 11 - 10 + EPDIS2 + 30 + 1 read-only + + EPENA2 + 31 + 1 + read-write + - MEM_RX_STATUS - Rx-FIFO write and read offset address. - 0x68 + DOEPINT2 + 0xB48 0x20 - 0x00100200 - APB_RX_RADDR - This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + XFERCOMPL2 0 - 10 - read-only + 1 + read-write - RX_WADDR - This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. - 11 - 10 - read-only + EPDISBLD2 + 1 + 1 + read-write - - - - FSM_STATUS - UART transmit and receive status. - 0x6C - 0x20 - - ST_URX_OUT - This is the status register of receiver. - 0 - 4 - read-only + AHBERR2 + 2 + 1 + read-write - ST_UTX_OUT - This is the status register of transmitter. + SETUP2 + 3 + 1 + read-write + + + OUTTKNEPDIS2 4 - 4 - read-only + 1 + read-write - - - - POSPULSE - Autobaud high pulse register - 0x70 - 0x20 - 0x00000FFF - - POSEDGE_MIN_CNT - This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. - 0 - 12 - read-only + STSPHSERCVD2 + 5 + 1 + read-write - - - - NEGPULSE - Autobaud low pulse register - 0x74 - 0x20 - 0x00000FFF - - NEGEDGE_MIN_CNT - This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. - 0 - 12 - read-only + BACK2BACKSETUP2 + 6 + 1 + read-write - - - - CLK_CONF - UART core clock configuration - 0x78 - 0x20 - 0x03701000 - - SCLK_DIV_B - The denominator of the frequency divider factor. - 0 - 6 + OUTPKTERR2 + 8 + 1 read-write - SCLK_DIV_A - The numerator of the frequency divider factor. - 6 - 6 + BNAINTR2 + 9 + 1 read-write - SCLK_DIV_NUM - The integral part of the frequency divider factor. + PKTDRPSTS2 + 11 + 1 + read-write + + + BBLEERR2 12 - 8 + 1 read-write - SCLK_SEL - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. - 20 - 2 + NAKINTRPT2 + 13 + 1 read-write - SCLK_EN - Set this bit to enable UART Tx/Rx clock. - 22 + NYEPINTRPT2 + 14 1 read-write - RST_CORE - Write 1 then write 0 to this bit, reset UART Tx/Rx. - 23 + STUPPKTRCVD2 + 15 1 read-write + + + + DOEPTSIZ2 + 0xB50 + 0x20 + - TX_SCLK_EN - Set this bit to enable UART Tx clock. - 24 - 1 + XFERSIZE2 + 0 + 7 read-write - RX_SCLK_EN - Set this bit to enable UART Rx clock. - 25 + PKTCNT2 + 19 1 read-write - TX_RST_CORE - Write 1 then write 0 to this bit, reset UART Tx. - 26 - 1 + SUPCNT2 + 29 + 2 read-write + + + + DOEPDMA2 + 0xB54 + 0x20 + - RX_RST_CORE - Write 1 then write 0 to this bit, reset UART Rx. - 27 - 1 + DMAADDR2 + 0 + 32 read-write - DATE - UART Version register - 0x7C + DOEPDMAB2 + 0xB5C 0x20 - 0x02008270 - DATE - This is the version register. + DMABUFFERADDR2 0 32 read-write @@ -53862,777 +64978,652 @@ protection is enabled. - ID - UART ID register - 0x80 + DOEPCTL3 + 0xB60 0x20 - 0x40000500 + 0x00008000 - ID - This register is used to configure the uart_id. + MPS3 0 - 30 + 11 + read-only + + + USBACTEP3 + 15 + 1 + read-only + + + NAKSTS3 + 17 + 1 + read-only + + + EPTYPE3 + 18 + 2 + read-only + + + SNP3 + 20 + 1 read-write - HIGH_SPEED - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. - 30 + STALL3 + 21 1 read-write - REG_UPDATE - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + CNAK3 + 26 + 1 + write-only + + + DO_SNAK3 + 27 + 1 + write-only + + + DO_SETD0PID3 + 28 + 1 + write-only + + + DO_SETD1PID3 + 29 + 1 + write-only + + + EPDIS3 + 30 + 1 + read-only + + + EPENA3 31 1 read-write - - - - UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller - 0x60010000 - - UART1 - 28 - - - - UART2 - UART (Universal Asynchronous Receiver-Transmitter) Controller - 0x6002E000 - - UART2 - 29 - - - - UHCI0 - Universal Host Controller Interface - UHCI - 0x60014000 - - 0x0 - 0x88 - registers - - - UHCI0 - 14 - - - CONF0 - UHCI configuration register - 0x0 + DOEPINT3 + 0xB68 0x20 - 0x000006E0 - TX_RST - Write 1, then write 0 to this bit to reset decode state machine. + XFERCOMPL3 0 1 read-write - RX_RST - Write 1, then write 0 to this bit to reset encode state machine. + EPDISBLD3 1 1 read-write - UART0_CE - Set this bit to link up HCI and UART0. + AHBERR3 2 1 read-write - UART1_CE - Set this bit to link up HCI and UART1. + SETUP3 3 1 read-write - UART2_CE - Set this bit to link up HCI and UART2. + OUTTKNEPDIS3 4 1 read-write - SEPER_EN - Set this bit to separate the data frame using a special char. + STSPHSERCVD3 5 1 read-write - HEAD_EN - Set this bit to encode the data packet with a formatting header. + BACK2BACKSETUP3 6 1 read-write - CRC_REC_EN - Set this bit to enable UHCI to receive the 16 bit CRC. - 7 + OUTPKTERR3 + 8 1 read-write - UART_IDLE_EOF_EN - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. - 8 + BNAINTR3 + 9 1 read-write - LEN_EOF_EN - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. - 9 + PKTDRPSTS3 + 11 1 read-write - ENCODE_CRC_EN - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. - 10 + BBLEERR3 + 12 1 read-write - CLK_EN - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. - 11 + NAKINTRPT3 + 13 1 read-write - UART_RX_BRK_EOF_EN - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. - 12 + NYEPINTRPT3 + 14 + 1 + read-write + + + STUPPKTRCVD3 + 15 1 read-write - INT_RAW - Raw interrupt status - 0x4 + DOEPTSIZ3 + 0xB70 0x20 - RX_START_INT_RAW - This is the interrupt raw bit. Triggered when a separator char has been sent. + XFERSIZE3 0 - 1 - read-only - - - TX_START_INT_RAW - This is the interrupt raw bit. Triggered when UHCI detects a separator char. - 1 - 1 - read-only - - - RX_HUNG_INT_RAW - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. - 2 - 1 - read-only - - - TX_HUNG_INT_RAW - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. - 3 - 1 - read-only - - - SEND_S_REG_Q_INT_RAW - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. - 4 - 1 - read-only + 7 + read-write - SEND_A_REG_Q_INT_RAW - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. - 5 + PKTCNT3 + 19 1 - read-only + read-write - OUT_EOF_INT_RAW - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. - 6 - 1 - read-only + SUPCNT3 + 29 + 2 + read-write + + + + DOEPDMA3 + 0xB74 + 0x20 + - APP_CTRL0_INT_RAW - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. - 7 - 1 + DMAADDR3 + 0 + 32 read-write + + + + DOEPDMAB3 + 0xB7C + 0x20 + - APP_CTRL1_INT_RAW - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. - 8 - 1 + DMABUFFERADDR3 + 0 + 32 read-write - INT_ST - Masked interrupt status - 0x8 + DOEPCTL4 + 0xB80 0x20 + 0x00008000 - RX_START_INT_ST - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + MPS4 0 - 1 + 11 read-only - TX_START_INT_ST - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. - 1 + USBACTEP4 + 15 1 read-only - RX_HUNG_INT_ST - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. - 2 + NAKSTS4 + 17 1 read-only - TX_HUNG_INT_ST - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. - 3 - 1 + EPTYPE4 + 18 + 2 read-only - SEND_S_REG_Q_INT_ST - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. - 4 + SNP4 + 20 1 - read-only + read-write - SEND_A_REG_Q_INT_ST - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. - 5 + STALL4 + 21 1 - read-only + read-write - OUTLINK_EOF_ERR_INT_ST - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. - 6 + CNAK4 + 26 1 - read-only + write-only - APP_CTRL0_INT_ST - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. - 7 + DO_SNAK4 + 27 1 - read-only + write-only - APP_CTRL1_INT_ST - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. - 8 + DO_SETD0PID4 + 28 + 1 + write-only + + + DO_SETD1PID4 + 29 + 1 + write-only + + + EPDIS4 + 30 1 read-only + + EPENA4 + 31 + 1 + read-write + - INT_ENA - Interrupt enable bits - 0xC + DOEPINT4 + 0xB88 0x20 - RX_START_INT_ENA - This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + XFERCOMPL4 0 1 read-write - TX_START_INT_ENA - This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + EPDISBLD4 1 1 read-write - RX_HUNG_INT_ENA - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + AHBERR4 2 1 read-write - TX_HUNG_INT_ENA - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + SETUP4 3 1 read-write - SEND_S_REG_Q_INT_ENA - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + OUTTKNEPDIS4 4 1 read-write - SEND_A_REG_Q_INT_ENA - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + STSPHSERCVD4 5 1 read-write - OUTLINK_EOF_ERR_INT_ENA - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + BACK2BACKSETUP4 6 1 read-write - APP_CTRL0_INT_ENA - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. - 7 - 1 - read-write - - - APP_CTRL1_INT_ENA - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + OUTPKTERR4 8 1 read-write - - - - INT_CLR - Interrupt clear bits - 0x10 - 0x20 - - RX_START_INT_CLR - Set this bit to clear UHCI_RX_START_INT interrupt. - 0 + BNAINTR4 + 9 1 - write-only + read-write - TX_START_INT_CLR - Set this bit to clear UHCI_TX_START_INT interrupt. - 1 + PKTDRPSTS4 + 11 1 - write-only + read-write - RX_HUNG_INT_CLR - Set this bit to clear UHCI_RX_HUNG_INT interrupt. - 2 + BBLEERR4 + 12 1 - write-only + read-write - TX_HUNG_INT_CLR - Set this bit to clear UHCI_TX_HUNG_INT interrupt. - 3 + NAKINTRPT4 + 13 1 - write-only + read-write - SEND_S_REG_Q_INT_CLR - Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. - 4 + NYEPINTRPT4 + 14 1 - write-only + read-write - SEND_A_REG_Q_INT_CLR - Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. - 5 + STUPPKTRCVD4 + 15 1 - write-only + read-write + + + + DOEPTSIZ4 + 0xB90 + 0x20 + - OUTLINK_EOF_ERR_INT_CLR - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. - 6 - 1 - write-only + XFERSIZE4 + 0 + 7 + read-write - APP_CTRL0_INT_CLR - Set this bit to clear UHCI_APP_CTRL0_INT interrupt. - 7 + PKTCNT4 + 19 1 - write-only + read-write - APP_CTRL1_INT_CLR - Set this bit to clear UHCI_APP_CTRL1_INT interrupt. - 8 - 1 - write-only + SUPCNT4 + 29 + 2 + read-write - APP_INT_SET - Software interrupt trigger source - 0x14 + DOEPDMA4 + 0xB94 0x20 - APP_CTRL0_INT_SET - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. + DMAADDR4 0 - 1 - write-only + 32 + read-write + + + + DOEPDMAB4 + 0xB9C + 0x20 + - APP_CTRL1_INT_SET - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. - 1 - 1 - write-only + DMABUFFERADDR4 + 0 + 32 + read-write - CONF1 - UHCI configuration register - 0x18 + DOEPCTL5 + 0xBA0 0x20 - 0x00000033 + 0x00008000 - CHECK_SUM_EN - This is the enable bit to check header checksum when UHCI receives a data packet. + MPS5 0 - 1 - read-write + 11 + read-only - CHECK_SEQ_EN - This is the enable bit to check sequence number when UHCI receives a data packet. - 1 + USBACTEP5 + 15 1 - read-write + read-only - CRC_DISABLE - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. - 2 + NAKSTS5 + 17 1 - read-write + read-only - SAVE_HEAD - Set this bit to save the packet header when HCI receives a data packet. - 3 - 1 - read-write + EPTYPE5 + 18 + 2 + read-only - TX_CHECK_SUM_RE - Set this bit to encode the data packet with a checksum. - 4 + SNP5 + 20 1 read-write - TX_ACK_NUM_RE - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. - 5 + STALL5 + 21 1 read-write - WAIT_SW_START - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. - 7 + CNAK5 + 26 1 - read-write + write-only - SW_START - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. - 8 + DO_SNAK5 + 27 1 - read-write + write-only - - - - STATE0 - UHCI receive status - 0x1C - 0x20 - - RX_ERR_CAUSE - This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error. - 0 - 3 - read-only + DO_SETD0PID5 + 28 + 1 + write-only - DECODE_STATE - UHCI decoder status. - 3 - 3 - read-only - - - - - STATE1 - UHCI transmit status - 0x20 - 0x20 - + DO_SETD1PID5 + 29 + 1 + write-only + - ENCODE_STATE - UHCI encoder status. - 0 - 3 + EPDIS5 + 30 + 1 read-only + + EPENA5 + 31 + 1 + read-write + - ESCAPE_CONF - Escape character configuration - 0x24 + DOEPINT5 + 0xBA8 0x20 - 0x00000033 - TX_C0_ESC_EN - Set this bit to enable decoding char 0xc0 when DMA receives data. + XFERCOMPL5 0 1 read-write - TX_DB_ESC_EN - Set this bit to enable decoding char 0xdb when DMA receives data. + EPDISBLD5 1 1 read-write - TX_11_ESC_EN - Set this bit to enable decoding flow control char 0x11 when DMA receives data. + AHBERR5 2 1 read-write - TX_13_ESC_EN - Set this bit to enable decoding flow control char 0x13 when DMA receives data. + SETUP5 3 1 read-write - RX_C0_ESC_EN - Set this bit to enable replacing 0xc0 by special char when DMA sends data. + OUTTKNEPDIS5 4 1 read-write - RX_DB_ESC_EN - Set this bit to enable replacing 0xdb by special char when DMA sends data. + STSPHSERCVD5 5 1 read-write - RX_11_ESC_EN - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + BACK2BACKSETUP5 6 1 read-write - RX_13_ESC_EN - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. - 7 + OUTPKTERR5 + 8 1 read-write - - - - HUNG_CONF - Timeout configuration - 0x28 - 0x20 - 0x00810810 - - - TXFIFO_TIMEOUT - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. - 0 - 8 - read-write - - TXFIFO_TIMEOUT_SHIFT - This register is used to configure the tick count maximum value. - 8 - 3 + BNAINTR5 + 9 + 1 read-write - TXFIFO_TIMEOUT_ENA - This is the enable bit for Tx-FIFO receive-data timeout. + PKTDRPSTS5 11 1 read-write - RXFIFO_TIMEOUT - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + BBLEERR5 12 - 8 - read-write - - - RXFIFO_TIMEOUT_SHIFT - This register is used to configure the tick count maximum value. - 20 - 3 + 1 read-write - RXFIFO_TIMEOUT_ENA - This is the enable bit for DMA send-data timeout. - 23 + NAKINTRPT5 + 13 1 read-write - - - - ACK_NUM - UHCI ACK number configuration - 0x2C - 0x20 - 0x00000008 - - ACK_NUM - This ACK number used in software flow control. - 0 - 3 + NYEPINTRPT5 + 14 + 1 read-write - LOAD - Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded. - 3 + STUPPKTRCVD5 + 15 1 - write-only - - - - - RX_HEAD - UHCI packet header register - 0x30 - 0x20 - - - RX_HEAD - This register stores the header of the current received packet. - 0 - 32 - read-only + read-write - QUICK_SENT - UHCI quick send configuration register - 0x34 + DOEPTSIZ5 + 0xBB0 0x20 - SINGLE_SEND_NUM - This register is used to specify the single_send register. + XFERSIZE5 0 - 3 + 7 read-write - SINGLE_SEND_EN - Set this bit to enable single_send mode to send short packet. - 3 + PKTCNT5 + 19 1 read-write - ALWAYS_SEND_NUM - This register is used to specify the always_send register. - 4 - 3 - read-write - - - ALWAYS_SEND_EN - Set this bit to enable always_send mode to send short packet. - 7 - 1 + SUPCNT5 + 29 + 2 read-write - REG_Q0_WORD0 - Q0_WORD0 quick_sent register - 0x38 + DOEPDMA5 + 0xBB4 0x20 - SEND_Q0_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + DMAADDR5 0 32 read-write @@ -54640,14 +65631,12 @@ protection is enabled. - REG_Q0_WORD1 - Q0_WORD1 quick_sent register - 0x3C + DOEPDMAB5 + 0xBBC 0x20 - SEND_Q0_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + DMABUFFERADDR5 0 32 read-write @@ -54655,347 +65644,281 @@ protection is enabled. - REG_Q1_WORD0 - Q1_WORD0 quick_sent register - 0x40 + DOEPCTL6 + 0xBC0 0x20 + 0x00008000 - SEND_Q1_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + MPS6 0 - 32 - read-write + 11 + read-only - - - - REG_Q1_WORD1 - Q1_WORD1 quick_sent register - 0x44 - 0x20 - - SEND_Q1_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + USBACTEP6 + 15 + 1 + read-only + + + NAKSTS6 + 17 + 1 + read-only + + + EPTYPE6 + 18 + 2 + read-only + + + SNP6 + 20 + 1 read-write - - - - REG_Q2_WORD0 - Q2_WORD0 quick_sent register - 0x48 - 0x20 - - SEND_Q2_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + STALL6 + 21 + 1 read-write - - - - REG_Q2_WORD1 - Q2_WORD1 quick_sent register - 0x4C - 0x20 - - SEND_Q2_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + CNAK6 + 26 + 1 + write-only + + + DO_SNAK6 + 27 + 1 + write-only + + + DO_SETD0PID6 + 28 + 1 + write-only + + + DO_SETD1PID6 + 29 + 1 + write-only + + + EPDIS6 + 30 + 1 + read-only + + + EPENA6 + 31 + 1 read-write - REG_Q3_WORD0 - Q3_WORD0 quick_sent register - 0x50 + DOEPINT6 + 0xBC8 0x20 - SEND_Q3_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + XFERCOMPL6 0 - 32 + 1 read-write - - - - REG_Q3_WORD1 - Q3_WORD1 quick_sent register - 0x54 - 0x20 - - SEND_Q3_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + EPDISBLD6 + 1 + 1 read-write - - - - REG_Q4_WORD0 - Q4_WORD0 quick_sent register - 0x58 - 0x20 - - SEND_Q4_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + AHBERR6 + 2 + 1 read-write - - - - REG_Q4_WORD1 - Q4_WORD1 quick_sent register - 0x5C - 0x20 - - SEND_Q4_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + SETUP6 + 3 + 1 read-write - - - - REG_Q5_WORD0 - Q5_WORD0 quick_sent register - 0x60 - 0x20 - - SEND_Q5_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + OUTTKNEPDIS6 + 4 + 1 read-write - - - - REG_Q5_WORD1 - Q5_WORD1 quick_sent register - 0x64 - 0x20 - - SEND_Q5_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + STSPHSERCVD6 + 5 + 1 read-write - - - - REG_Q6_WORD0 - Q6_WORD0 quick_sent register - 0x68 - 0x20 - - SEND_Q6_WORD0 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + BACK2BACKSETUP6 + 6 + 1 read-write - - - - REG_Q6_WORD1 - Q6_WORD1 quick_sent register - 0x6C - 0x20 - - SEND_Q6_WORD1 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 + OUTPKTERR6 + 8 + 1 read-write - - - - ESC_CONF0 - Escape sequence configuration register 0 - 0x70 - 0x20 - 0x00DCDBC0 - - SEPER_CHAR - This register is used to define the separate char that need to be encoded, default is 0xc0. - 0 - 8 + BNAINTR6 + 9 + 1 read-write - SEPER_ESC_CHAR0 - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb. - 8 - 8 + PKTDRPSTS6 + 11 + 1 read-write - SEPER_ESC_CHAR1 - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc. - 16 - 8 + BBLEERR6 + 12 + 1 read-write - - - - ESC_CONF1 - Escape sequence configuration register 1 - 0x74 - 0x20 - 0x00DDDBDB - - ESC_SEQ0 - This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence. - 0 - 8 + NAKINTRPT6 + 13 + 1 read-write - ESC_SEQ0_CHAR0 - This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb. - 8 - 8 + NYEPINTRPT6 + 14 + 1 read-write - ESC_SEQ0_CHAR1 - This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd. - 16 - 8 + STUPPKTRCVD6 + 15 + 1 read-write - ESC_CONF2 - Escape sequence configuration register 2 - 0x78 + DOEPTSIZ6 + 0xBD0 0x20 - 0x00DEDB11 - ESC_SEQ1 - This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char. + XFERSIZE6 0 - 8 + 7 read-write - ESC_SEQ1_CHAR0 - This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb. - 8 - 8 + PKTCNT6 + 19 + 1 read-write - ESC_SEQ1_CHAR1 - This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde. - 16 - 8 + SUPCNT6 + 29 + 2 read-write - ESC_CONF3 - Escape sequence configuration register 3 - 0x7C + DOEPDMA6 + 0xBD4 0x20 - 0x00DFDB13 - ESC_SEQ2 - This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char. + DMAADDR6 0 - 8 - read-write - - - ESC_SEQ2_CHAR0 - This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb. - 8 - 8 - read-write - - - ESC_SEQ2_CHAR1 - This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf. - 16 - 8 + 32 read-write - PKT_THRES - Configure register for packet length - 0x80 + DOEPDMAB6 + 0xBDC 0x20 - 0x00000080 - PKT_THRS - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + DMABUFFERADDR6 0 - 13 + 32 read-write - DATE - UHCI version control register - 0x84 + PCGCCTL + 0xE00 0x20 - 0x02010090 - DATE - This is the version control register. + STOPPCLK 0 - 32 + 1 + read-write + + + GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + 2 + 1 + read-write + + + RSTPDWNMODULE + 3 + 1 + read-write + + + PHYSLEEP + 6 + 1 + read-only + + + L1SUSPENDED + 7 + 1 + read-only + + + RESETAFTERSUSP + 8 + 1 read-write - - UHCI1 - Universal Host Controller Interface - 0x6000C000 - USB_DEVICE - Peripheral USB_DEVICE + Full-speed USB Serial/JTAG Controller USB_DEVICE 0x60038000 @@ -55065,84 +65988,84 @@ protection is enabled. The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 - read-only + read-write SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 - read-only + read-write SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 - read-only + read-write SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 - read-only + read-write PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 - read-only + read-write CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 - read-only + read-write CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 - read-only + read-write STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 - read-only + read-write IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 - read-only + read-write USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 - read-only + read-write OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 - read-only + read-write OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 - read-only + read-write @@ -55945,7 +66868,7 @@ protection is enabled. USB_WRAP - Peripheral USB_WRAP + USB_WRAP Peripheral USB_WRAP 0x60039000 @@ -56194,7 +67117,7 @@ protection is enabled. WCL - Peripheral WCL + WCL Peripheral WCL 0x600D0000 @@ -57953,7 +68876,7 @@ protection is enabled. 0x20 - PLAIN_0 + PLAIN Stores the nth 32-bit piece of plaintext. 0 32 From ea6ae8b32e15731da3f4d3128db530683dcb454b Mon Sep 17 00:00:00 2001 From: Denys Almazov Date: Tue, 15 Jul 2025 06:37:04 +0300 Subject: [PATCH 03/10] IEP-1559 Add SWT Tests to Verify Syntax Highlighting Functionality (#1255) * feat: added swt test to check for exceptions * feat: added lsp cdt func tests * fix: try to fix NewEspressifIDFProjectTest on runner * fix: trying to wait until widgets appear * feat: added SyntaxHighlighting_ColorsApplied test --- .../IDFProjectLspCdtFunctionalityTest.java | 177 ++++++++++++++++++ .../project/NewEspressifIDFProjectTest.java | 56 ++++++ .../operations/ProjectTestOperations.java | 28 ++- 3 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/IDFProjectLspCdtFunctionalityTest.java diff --git a/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/IDFProjectLspCdtFunctionalityTest.java b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/IDFProjectLspCdtFunctionalityTest.java new file mode 100644 index 000000000..917894f01 --- /dev/null +++ b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/IDFProjectLspCdtFunctionalityTest.java @@ -0,0 +1,177 @@ +/******************************************************************************* + * Copyright 2025 Espressif Systems (Shanghai) PTE LTD. + * All rights reserved. Use is subject to license terms. + *******************************************************************************/ + +package com.espressif.idf.ui.test.executable.cases.project; + +import static org.junit.Assert.assertTrue; + +import java.util.List; + +import org.eclipse.jface.bindings.keys.KeyStroke; +import org.eclipse.jface.bindings.keys.ParseException; +import org.eclipse.swt.SWT; +import org.eclipse.swt.custom.StyleRange; +import org.eclipse.swt.custom.StyledText; +import org.eclipse.swt.widgets.Display; +import org.eclipse.swtbot.eclipse.finder.SWTWorkbenchBot; +import org.eclipse.swtbot.eclipse.finder.widgets.SWTBotEditor; +import org.eclipse.swtbot.eclipse.finder.widgets.SWTBotView; +import org.eclipse.swtbot.swt.finder.junit.SWTBotJunit4ClassRunner; +import org.eclipse.swtbot.swt.finder.widgets.SWTBotStyledText; +import org.junit.AfterClass; +import org.junit.BeforeClass; +import org.junit.FixMethodOrder; +import org.junit.Test; +import org.junit.runner.RunWith; +import org.junit.runners.MethodSorters; + +import com.espressif.idf.ui.test.common.WorkBenchSWTBot; +import com.espressif.idf.ui.test.common.utility.TestWidgetWaitUtility; +import com.espressif.idf.ui.test.operations.EnvSetupOperations; +import com.espressif.idf.ui.test.operations.ProjectTestOperations; + +/** + * Test LSP features like content assist (proposals), hover and diagnostics. + */ +@SuppressWarnings("restriction") +@RunWith(SWTBotJunit4ClassRunner.class) +@FixMethodOrder(MethodSorters.NAME_ASCENDING) +public class IDFProjectLspCdtFunctionalityTest +{ + + private static SWTWorkbenchBot bot; + private static final String PROJECT_NAME = "LspTestProject"; //$NON-NLS-1$ + + @BeforeClass + public static void setupEnv() throws Exception + { + bot = WorkBenchSWTBot.getBot(); + EnvSetupOperations.setupEspressifEnv(bot); + ProjectTestOperations.deleteAllProjects(bot); + ProjectTestOperations.setupProjectWithReconfigureCommand(PROJECT_NAME, "EspressIf", "Espressif IDF Project", //$NON-NLS-1$ //$NON-NLS-2$ + bot); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + } + + @AfterClass + public static void tearDown() + { + TestWidgetWaitUtility.waitForOperationsInProgressToFinishAsync(bot); + ProjectTestOperations.closeAllProjects(bot); + ProjectTestOperations.deleteAllProjects(bot); + } + + @Test + public void test_ContentAssist_ProposalsAppear() + { + openMainCFile(); + + SWTBotEditor editor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + editor.setFocus(); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + editor.toTextEditor().insertText(5, 5, "\n"); //$NON-NLS-1$ + editor.toTextEditor().click(5, 5); + List proposals = editor.toTextEditor().getAutoCompleteProposals(""); //$NON-NLS-1$ + bot.sleep(3000); + + assertTrue("Expected LSP proposals not found", !proposals.isEmpty()); //$NON-NLS-1$ + } + + @Test + public void test_HoverInformationAppears() throws ParseException + { + openMainCFile(); + SWTBotEditor editor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + editor.setFocus(); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + + bot.sleep(2000); + editor.toTextEditor().navigateTo(0, 5); + editor.toTextEditor().pressShortcut(KeyStroke.getInstance("F2")); //$NON-NLS-1$ + bot.sleep(2000); + + // lsp hover contains the code field + boolean hoverShown = editor.toTextEditor().bot().shell("").bot().browser().getText().contains("code"); //$NON-NLS-1$ //$NON-NLS-2$ + + assertTrue("Hover documentation not shown", hoverShown); //$NON-NLS-1$ + } + + @Test + public void test_Diagnostics_NoErrorThenErrorAppears() + { + openMainCFile(); + + SWTBotEditor editor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + editor.setFocus(); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + + editor.toTextEditor().insertText("\n"); //$NON-NLS-1$ + editor.save(); + bot.sleep(4000); + + SWTBotView problemsView = bot.views().stream().filter(v -> v.getTitle().toLowerCase().contains("problem")) //$NON-NLS-1$ + .findFirst().orElseThrow(() -> new RuntimeException("Problems view not found")); //$NON-NLS-1$ + + problemsView.show(); + problemsView.setFocus(); + + assertTrue("No error expected, but found some markers", problemsView.bot().tree().rowCount() == 0); //$NON-NLS-1$ + + editor.toTextEditor().insertText("\nundefined_function();\n"); //$NON-NLS-1$ + editor.save(); + bot.sleep(4000); + + assertTrue("Expected error marker not found after inserting invalid code", //$NON-NLS-1$ + problemsView.bot().tree().rowCount() != 0); + } + + @Test + public void test_SyntaxHighlighting_ColorsApplied() + { + openMainCFile(); + + SWTBotEditor botEditor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + botEditor.setFocus(); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + bot.sleep(2000); // allow LSP highlight to apply + + SWTBotStyledText botStyledText = botEditor.toTextEditor().getStyledText(); + StyledText styledText = botStyledText.widget; + + final StyleRange[][] styleRangesHolder = new StyleRange[1][]; + Display.getDefault().syncExec(() -> styleRangesHolder[0] = styledText.getStyleRanges()); + + StyleRange[] ranges = styleRangesHolder[0]; + + boolean foundColoredText = false; + for (StyleRange range : ranges) + { + if (range.foreground != null || range.background != null || range.fontStyle != SWT.NORMAL) + { + foundColoredText = true; + break; + } + } + + assertTrue("Expected some styled (highlighted) text ranges, but none were found", foundColoredText); //$NON-NLS-1$ + } + + private static void openMainCFile() + { + SWTBotEditor editor; + try + { + editor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + } + catch (Exception e) + { + bot.viewByTitle("Project Explorer").show(); //$NON-NLS-1$ + bot.tree().getTreeItem(PROJECT_NAME).expand().getNode("main").expand().getNode("main.c").doubleClick(); //$NON-NLS-1$ //$NON-NLS-2$ + editor = bot.editorByTitle("main.c"); //$NON-NLS-1$ + } + editor.show(); + editor.setFocus(); + } +} diff --git a/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/NewEspressifIDFProjectTest.java b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/NewEspressifIDFProjectTest.java index 3f2eafd6b..c44048d93 100644 --- a/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/NewEspressifIDFProjectTest.java +++ b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/executable/cases/project/NewEspressifIDFProjectTest.java @@ -20,6 +20,8 @@ import org.eclipse.swtbot.eclipse.finder.widgets.SWTBotView; import org.eclipse.swtbot.swt.finder.exceptions.WidgetNotFoundException; import org.eclipse.swtbot.swt.finder.junit.SWTBotJunit4ClassRunner; +import org.eclipse.swtbot.swt.finder.waits.Conditions; +import org.eclipse.swtbot.swt.finder.widgets.SWTBotTable; import org.eclipse.swtbot.swt.finder.widgets.SWTBotTreeItem; import org.junit.After; import org.junit.BeforeClass; @@ -179,6 +181,15 @@ public void givenNewProjectCreatedBuiltAndThenProjectPythonCleanUsingContextMenu Fixture.checkPythonCLeanCommandDeleteFolder(); } + @Test + public void givenMainCFileOpenedThenNoErrorsShouldBeInErrorLog() throws Exception + { + Fixture.givenNewEspressifIDFProjectIsSelected("EspressIf", "Espressif IDF Project"); + Fixture.givenProjectNameIs("ErrorLogTestProject"); + Fixture.whenNewProjectIsSelected(); + Fixture.openMainCAndCheckIfNoExceptionInErrorLog(); + } + private static class Fixture { private static SWTWorkbenchBot bot; @@ -390,5 +401,50 @@ private static void checkIfProjectFullCleanedFilesInBuildFolder() throws IOExcep { assertTrue(ProjectTestOperations.findProjectFullCleanedFilesInBuildFolder(projectName, bot)); } + + public static void openMainCAndCheckIfNoExceptionInErrorLog() throws Exception + { + // Ensure main.c exists + thenProjectHasTheFile("main.c", "/main"); + + // Open main.c in editor + // Open the file from Project Explorer + SWTBotView projectExplorer = bot.viewByTitle("Project Explorer"); + projectExplorer.show(); + projectExplorer.setFocus(); + + // Expand project and open main.c from /main + SWTBotTreeItem projectNode = projectExplorer.bot().tree().getTreeItem(projectName).expand(); + SWTBotTreeItem mainFolder = projectNode.getNode("main").expand(); + mainFolder.getNode("main.c").doubleClick(); + + // Now main.c is open, get the editor + SWTBotEditor editor = bot.editorByTitle("main.c"); + editor.show(); + editor.setFocus(); + TestWidgetWaitUtility.waitForOperationsInProgressToFinishSync(bot); + + // Open the "Error Log" view + bot.menu("Window").menu("Show View").menu("Other...").click(); + bot.tree().getTreeItem("General").select(); + bot.tree().getTreeItem("General").doubleClick(); + bot.tree().getTreeItem("General").getNode("Error Log").select(); + bot.button("Open").click(); + SWTBotView errorLogView = bot.activeView(); + + try + { + + bot.waitUntil(Conditions.widgetIsEnabled(errorLogView.bot().table())); + SWTBotTable errorTable = errorLogView.bot().table(); + boolean hasErrors = errorTable.containsItem("Exception"); + + assertTrue(!hasErrors); + } + catch (WidgetNotFoundException e) + { + // do nothing + } + } } } diff --git a/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/operations/ProjectTestOperations.java b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/operations/ProjectTestOperations.java index 079dbb80c..1012f68e9 100644 --- a/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/operations/ProjectTestOperations.java +++ b/tests/com.espressif.idf.ui.test/src/com/espressif/idf/ui/test/operations/ProjectTestOperations.java @@ -383,7 +383,33 @@ public static void setupProject(String projectName, String category, String subC bot.button("Finish").click(); SWTBotShell shell1 = bot.shell("New IDF Project"); shell1.activate(); - bot.checkBox("Run idf.py reconfigure after project creation to initialize the CMake build configuration").click(); + bot.checkBox("Run idf.py reconfigure after project creation to initialize the CMake build configuration") + .click(); + bot.textWithLabel("Project name:").setText(projectName); + bot.button("Finish").click(); + TestWidgetWaitUtility.waitUntilViewContainsTheTreeItemWithName(projectName, bot.viewByTitle("Project Explorer"), + 5000); + } + + /** + * Set up a project + * + * @param projectName name of the project + * @param category category of the project + * @param subCategory sub category of the project + * @param bot current SWT bot reference + */ + public static void setupProjectWithReconfigureCommand(String projectName, String category, String subCategory, + SWTWorkbenchBot bot) + { + bot.shell().activate().bot().menu("File").menu("New").menu("Project...").click(); + SWTBotShell shell = bot.shell("New Project"); + shell.activate(); + + bot.tree().expandNode(category).select(subCategory); + bot.button("Finish").click(); + SWTBotShell shell1 = bot.shell("New IDF Project"); + shell1.activate(); bot.textWithLabel("Project name:").setText(projectName); bot.button("Finish").click(); TestWidgetWaitUtility.waitUntilViewContainsTheTreeItemWithName(projectName, bot.viewByTitle("Project Explorer"), From af57f2db1ef6a412ba662c03bf07b06c9a479528 Mon Sep 17 00:00:00 2001 From: Denys Almazov Date: Wed, 16 Jul 2025 14:25:01 +0300 Subject: [PATCH 04/10] IEP-1601 Fix NullPointerException in updateLspQueryDrivers method (#1272) * fix: fixed potential NPE in LspService * feat: added logging after null check --- .../espressif/idf/core/util/LspService.java | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/LspService.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/LspService.java index 25a97858c..4ad33167f 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/LspService.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/LspService.java @@ -17,6 +17,7 @@ import org.eclipse.ui.PlatformUI; import com.espressif.idf.core.ILSPConstants; +import com.espressif.idf.core.logging.Logger; @SuppressWarnings("restriction") public class LspService @@ -47,6 +48,11 @@ public void restartLspServers() public void updateAdditionalOptions(String additionalOptions) { + if (additionalOptions == null) + { + Logger.log("Skipped updating additional options: value is null"); //$NON-NLS-1$ + return; + } String qualifier = configuration.qualifier(); InstanceScope.INSTANCE.getNode(qualifier).put(ClangdMetadata.Predefined.additionalOptions.identifer(), additionalOptions); @@ -54,18 +60,28 @@ public void updateAdditionalOptions(String additionalOptions) public void updateLspQueryDrivers() { + String toolchainPath = IDFUtil.getToolchainExePathForActiveTarget(); String qualifier = configuration.qualifier(); + if (toolchainPath == null) + { + Logger.log("Toolchain path not found. Skipping update of --query-driver for LSP"); //$NON-NLS-1$ + return; + } // By passing --query-driver argument to clangd helps to resolve the // cross-compiler toolchain headers. - String toolchainPath = IDFUtil.getToolchainExePathForActiveTarget(); InstanceScope.INSTANCE.getNode(qualifier).put(ClangdMetadata.Predefined.queryDriver.identifer(), toolchainPath); } public void updateClangdPath() { + String clangdPath = IDFUtil.findCommandFromBuildEnvPath(ILSPConstants.CLANGD_EXECUTABLE); + if (clangdPath == null) + { + Logger.log("clangd executable not found in build environment path. Skipping clangd path update."); //$NON-NLS-1$ + return; + } String qualifier = configuration.qualifier(); - InstanceScope.INSTANCE.getNode(qualifier).put(ClangdMetadata.Predefined.clangdPath.identifer(), - IDFUtil.findCommandFromBuildEnvPath(ILSPConstants.CLANGD_EXECUTABLE)); + InstanceScope.INSTANCE.getNode(qualifier).put(ClangdMetadata.Predefined.clangdPath.identifer(), clangdPath); } public void updateCompileCommandsDir(String buildDir) From 13f90b10545b3c5aa5d7f7b3670f387ab9172a71 Mon Sep 17 00:00:00 2001 From: Kondal Kolipaka Date: Mon, 21 Jul 2025 13:22:31 +0530 Subject: [PATCH 05/10] feat(esp_detect_config.py): integrate devkits detect script in the target wizard and use in OpenOCD (#1226) * feat(esp_detect_config.py): integrate devkits detect script in the target wizard * fix: Show progress monitor while fetching connected boards * fix: set min width for all drop-down to have good ux experience * fix: save the selected board * fix: address PR comments --- .../idf/core/build/IDFLaunchConstants.java | 1 + .../com/espressif/idf/core/util/IDFUtil.java | 77 ++++++++++ .../core/variable/JtagVariableResolver.java | 12 +- .../gdbjtag/openocd/dsf/GdbServerBackend.java | 45 ++++++ .../core/IDFCoreLaunchConfigProvider.java | 1 + .../internal/NewSerialFlashTargetWizard.java | 18 +++ .../NewSerialFlashTargetWizardPage.java | 134 ++++++++++++++++-- 7 files changed, 269 insertions(+), 19 deletions(-) diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFLaunchConstants.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFLaunchConstants.java index 0d0b407e9..1ba1da6b1 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFLaunchConstants.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/build/IDFLaunchConstants.java @@ -18,4 +18,5 @@ public final class IDFLaunchConstants public static final String OPEN_SERIAL_MONITOR = "OPEN_SERIAL_MONITOR"; //$NON-NLS-1$ public static final String SERIAL_MONITOR_ENCODING = "SERIAL_MONITOR_ENCODING"; //$NON-NLS-1$ public static final String BUILD_FOLDER_PATH = "com.espressif.idf.launch.serial.core.idfBuildFolderPath"; //$NON-NLS-1$ + public static final String OPENOCD_USB_LOCATION = "OPENOCD_USB_ADAPTER_LOCATION"; //$NON-NLS-1$ } diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java index 73a38153a..684089661 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java @@ -879,4 +879,81 @@ public static void closeWelcomePage(IWorkbenchWindow activeww) } }); } + + /** + * Checks if esp_detect_config.py exists in the expected OpenOCD tools directory. + * @return true if esp_detect_config.py exists, false otherwise. + */ + public static boolean espDetectConfigScriptExists() { + String openocdBinDir = getOpenOCDLocation(); + if (StringUtil.isEmpty(openocdBinDir)) { + return false; + } + File binDir = new File(openocdBinDir); + File openocdRoot = binDir.getParentFile(); + File toolsDir = Paths.get(openocdRoot.getPath(), "share", "openocd", "espressif", "tools").toFile(); //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ //$NON-NLS-4$ + File scriptFile = new File(toolsDir, "esp_detect_config.py"); //$NON-NLS-1$ + return scriptFile.exists(); + } + + /** + * Runs the esp_detect_config.py script using the OPENOCD_SCRIPTS environment variable to locate the script and config files. + * Returns the JSON output as a string, or null on error. + */ + public static String runEspDetectConfigScript() { + String openocdBinDir = getOpenOCDLocation(); + if (StringUtil.isEmpty(openocdBinDir)) { + Logger.log("OpenOCD location could not be determined."); //$NON-NLS-1$ + return null; + } + // Derive the scripts and tools directories from the bin directory + File binDir = new File(openocdBinDir); + File openocdRoot = binDir.getParentFile(); + File scriptsDir = Paths.get(openocdRoot.getPath(), "share", "openocd", "scripts").toFile(); //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ + File toolsDir = Paths.get(openocdRoot.getPath(), "share", "openocd", "espressif", "tools").toFile(); //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ //$NON-NLS-4$ + File configFile = new File(scriptsDir, "esp-config.json"); //$NON-NLS-1$ + if (!configFile.exists()) { + Logger.log("esp-config.json not found at expected location: " + configFile.getAbsolutePath()); //$NON-NLS-1$ + return null; + } + if (!espDetectConfigScriptExists()) { + Logger.log("esp_detect_config.py not found at expected location: " + new File(toolsDir, "esp_detect_config.py").getAbsolutePath()); //$NON-NLS-1$ //$NON-NLS-2$ + return null; + } + String scriptPath = new File(toolsDir, "esp_detect_config.py").getAbsolutePath(); //$NON-NLS-1$ + String configPath = configFile.getAbsolutePath(); + String openocdExecutable = Platform.getOS().equals(Platform.OS_WIN32) ? "openocd.exe" : "openocd"; //$NON-NLS-1$ //$NON-NLS-2$ + File openocdBin = new File(openocdBinDir, openocdExecutable); + if (!openocdBin.exists()) { + Logger.log("OpenOCD binary not found at expected location."); //$NON-NLS-1$ + return null; + } + + String idfPythonEnvPath = IDFUtil.getIDFPythonEnvPath(); + if (StringUtil.isEmpty(idfPythonEnvPath)) { + Logger.log("IDF_PYTHON_ENV_PATH could not be found."); //$NON-NLS-1$ + return null; + } + + List command = new ArrayList<>(); + command.add(idfPythonEnvPath); + command.add(scriptPath); + command.add("--esp-config"); //$NON-NLS-1$ + command.add(configPath); + command.add("--oocd");//$NON-NLS-1$ + command.add(openocdBin.getAbsolutePath()); + + Map env = new IDFEnvironmentVariables().getSystemEnvMap(); + try { + IStatus status = new ProcessBuilderFactory().runInBackground(command, null, env); + if (status == null) { + Logger.log("esp_detect_config.py did not return a result."); //$NON-NLS-1$ + return null; + } + return status.getMessage(); + } catch (Exception e) { + Logger.log(e); + return null; + } + } } diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/variable/JtagVariableResolver.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/variable/JtagVariableResolver.java index e6fd907ce..9ed6d48a7 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/variable/JtagVariableResolver.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/variable/JtagVariableResolver.java @@ -72,11 +72,15 @@ private String generatePartOfConfigOptionsForBoard() var boardConfigMap = parser.getBoardsConfigs(targetName); var board = activeILaunchTarget.getAttribute(LaunchBarTargetConstants.BOARD, new DefaultBoardProvider().getDefaultBoard(targetName)); - var boardConfigs = boardConfigMap.get(board); + int idx = board.lastIndexOf(" [usb://"); //$NON-NLS-1$ + String boardKey = (idx != -1) ? board.substring(0, idx) : board; + var boardConfigs = boardConfigMap.get(boardKey); var result = new StringBuilder(); - for (Object config : boardConfigs) - { - result.append(String.format("-f %s ", config)); //$NON-NLS-1$ + if (boardConfigs != null) { + for (Object config : boardConfigs) + { + result.append(String.format("-f %s ", config)); //$NON-NLS-1$ + } } return result.toString(); } diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/GdbServerBackend.java b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/GdbServerBackend.java index f9e2710cf..b5798b0bc 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/GdbServerBackend.java +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/GdbServerBackend.java @@ -14,18 +14,28 @@ package com.espressif.idf.debug.gdbjtag.openocd.dsf; +import java.io.File; +import java.util.HashMap; +import java.util.Map; +import java.util.Map.Entry; + import org.eclipse.cdt.dsf.concurrent.RequestMonitor; import org.eclipse.cdt.dsf.service.DsfSession; import org.eclipse.core.runtime.CoreException; +import org.eclipse.core.runtime.IPath; import org.eclipse.core.runtime.IStatus; import org.eclipse.core.runtime.Platform; import org.eclipse.core.runtime.Status; import org.eclipse.debug.core.ILaunchConfiguration; import org.eclipse.embedcdt.core.StringUtils; +import org.eclipse.embedcdt.debug.gdbjtag.core.DebugUtils; import org.eclipse.embedcdt.debug.gdbjtag.core.dsf.GnuMcuGdbServerBackend; +import org.eclipse.launchbar.core.ILaunchBarManager; +import org.eclipse.launchbar.core.target.ILaunchTarget; import org.osgi.framework.BundleContext; import com.espressif.idf.core.IDFCorePlugin; +import com.espressif.idf.core.build.IDFLaunchConstants; import com.espressif.idf.debug.gdbjtag.openocd.Activator; import com.espressif.idf.debug.gdbjtag.openocd.Configuration; @@ -194,4 +204,39 @@ public String prepareMessageBoxText(int exitCode) { } // ------------------------------------------------------------------------ + + @Override + protected Process launchGdbServerProcess(String[] commandLineArray) throws CoreException { + File dir = null; + IPath path = DebugUtils.getGdbWorkingDirectory(fLaunchConfiguration); + if (path != null) { + dir = new File(path.toOSString()); + } + + // Get the default environment + String[] envp = DebugUtils.getLaunchEnvironment(fLaunchConfiguration); + Map envMap = new HashMap<>(); + for (String env : envp) { + int idx = env.indexOf('='); + if (idx > 0) envMap.put(env.substring(0, idx), env.substring(idx + 1)); + } + + // Add custom env var from launch config + ILaunchTarget activeLaunchTarget = Activator.getService(ILaunchBarManager.class).getActiveLaunchTarget(); + if (activeLaunchTarget != null) + { + String openocdLoc = activeLaunchTarget.getAttribute(IDFLaunchConstants.OPENOCD_USB_LOCATION, (String) null); + if (openocdLoc != null) { + envMap.put(IDFLaunchConstants.OPENOCD_USB_LOCATION, openocdLoc); + } + } + + // Convert back to envp + java.util.List envList = new java.util.ArrayList<>(); + for (Entry entry : envMap.entrySet()) { + envList.add(entry.getKey() + "=" + entry.getValue()); + } + + return DebugUtils.exec(commandLineArray, envList.toArray(new String[0]), dir); + } } diff --git a/bundles/com.espressif.idf.launch.serial.core/src/com/espressif/idf/launch/serial/core/IDFCoreLaunchConfigProvider.java b/bundles/com.espressif.idf.launch.serial.core/src/com/espressif/idf/launch/serial/core/IDFCoreLaunchConfigProvider.java index 49b6f5212..337b31679 100644 --- a/bundles/com.espressif.idf.launch.serial.core/src/com/espressif/idf/launch/serial/core/IDFCoreLaunchConfigProvider.java +++ b/bundles/com.espressif.idf.launch.serial.core/src/com/espressif/idf/launch/serial/core/IDFCoreLaunchConfigProvider.java @@ -37,6 +37,7 @@ public ILaunchConfiguration getLaunchConfiguration(ILaunchDescriptor descriptor, .findAppropriateLaunchConfig(descriptor, IDFLaunchConstants.RUN_LAUNCH_CONFIG_TYPE) : configuration; configuration = configuration == null ? createLaunchConfiguration(descriptor, target) : configuration; projectConfigs.put(configuration.getName(), configuration); + return configuration; } diff --git a/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizard.java b/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizard.java index 46a6fdd0b..12bafa65d 100644 --- a/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizard.java +++ b/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizard.java @@ -30,6 +30,7 @@ import com.espressif.idf.core.LaunchBarTargetConstants; import com.espressif.idf.core.build.IDFLaunchConstants; +import com.espressif.idf.core.util.StringUtil; public class NewSerialFlashTargetWizard extends LaunchTargetWizard { @@ -65,6 +66,9 @@ public boolean performFinish() wc.setAttribute(LaunchBarTargetConstants.TARGET, page.getIDFTarget()); wc.setAttribute(LaunchBarTargetConstants.BOARD, page.getBoard()); wc.setAttribute(LaunchBarTargetConstants.FLASH_VOLTAGE, page.getVoltage()); + + setOpenOCDAdaptorLocation(wc); + wc.save(); storeLastUsedSerialPort(); @@ -83,6 +87,20 @@ protected IStatus run(IProgressMonitor monitor) return true; } + private void setOpenOCDAdaptorLocation(ILaunchTargetWorkingCopy wc) + { + String usbLocation = page.getSelectedBoardUsbLocation(); + if (StringUtil.isEmpty(usbLocation)) + { + wc.setAttribute(IDFLaunchConstants.OPENOCD_USB_LOCATION, null); // nullify existing one + } + else if (usbLocation.startsWith("usb://")) //$NON-NLS-1$ + { + usbLocation = usbLocation.substring("usb://".length()); //$NON-NLS-1$ + wc.setAttribute(IDFLaunchConstants.OPENOCD_USB_LOCATION, usbLocation); + } + } + private void storeLastUsedSerialPort() { Preferences preferences = InstanceScope.INSTANCE.getNode(Activator.PLUGIN_ID); diff --git a/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizardPage.java b/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizardPage.java index ae66cffc2..e73c526c7 100644 --- a/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizardPage.java +++ b/bundles/com.espressif.idf.launch.serial.ui/src/com/espressif/idf/launch/serial/ui/internal/NewSerialFlashTargetWizardPage.java @@ -18,6 +18,7 @@ import java.io.BufferedReader; import java.io.InputStream; import java.io.InputStreamReader; +import java.util.ArrayList; import java.util.Collection; import java.util.HashMap; import java.util.List; @@ -31,6 +32,7 @@ import org.eclipse.core.runtime.IStatus; import org.eclipse.core.runtime.Status; import org.eclipse.core.runtime.jobs.Job; +import org.eclipse.jface.dialogs.ProgressMonitorDialog; import org.eclipse.jface.wizard.WizardPage; import org.eclipse.launchbar.core.target.ILaunchTarget; import org.eclipse.swt.SWT; @@ -43,8 +45,11 @@ import org.eclipse.swt.widgets.Display; import org.eclipse.swt.widgets.Group; import org.eclipse.swt.widgets.Label; +import org.eclipse.swt.widgets.Shell; import org.eclipse.swt.widgets.Text; import org.json.simple.JSONArray; +import org.json.simple.JSONObject; +import org.json.simple.parser.JSONParser; import com.espressif.idf.core.DefaultBoardProvider; import com.espressif.idf.core.LaunchBarTargetConstants; @@ -52,6 +57,7 @@ import com.espressif.idf.core.toolchain.ESPToolChainManager; import com.espressif.idf.core.util.EspConfigParser; import com.espressif.idf.core.util.EspToolCommands; +import com.espressif.idf.core.util.IDFUtil; import com.espressif.idf.core.util.StringUtil; public class NewSerialFlashTargetWizardPage extends WizardPage @@ -73,6 +79,7 @@ public class NewSerialFlashTargetWizardPage extends WizardPage private String serialPort; private Combo fBoardCombo; private Combo fFlashVoltage; + private String previousBoard = null; public NewSerialFlashTargetWizardPage(ILaunchTarget launchTarget) { @@ -106,6 +113,9 @@ public void createControl(Composite parent) label.setText(Messages.NewSerialFlashTargetWizardPage_IDFTarget); idfTargetCombo = new Combo(comp, SWT.NONE); + GridData idfTargetComboGridData = new GridData(SWT.FILL, SWT.CENTER, true, false); + idfTargetComboGridData.minimumWidth = 250; + idfTargetCombo.setLayoutData(idfTargetComboGridData); List idfTargetList = getIDFTargetList(); @@ -117,11 +127,77 @@ public void createControl(Composite parent) @Override public void widgetSelected(SelectionEvent e) { - EspConfigParser parser = new EspConfigParser(); String selectedTargetString = idfTargetCombo.getText(); - fBoardCombo.setItems(parser.getBoardsConfigs(selectedTargetString).keySet().toArray(new String[0])); - fBoardCombo.select(new DefaultBoardProvider().getIndexOfDefaultBoard(selectedTargetString, - fBoardCombo.getItems())); + Shell shell = display.getActiveShell(); + final List boardDisplayNames = new ArrayList<>(); + final String[] jsonHolder = new String[1]; + try + { + ProgressMonitorDialog dialog = new ProgressMonitorDialog(shell); + dialog.run(true, false, monitor -> { + monitor.beginTask("Finding the Connected Boards...", IProgressMonitor.UNKNOWN); //$NON-NLS-1$ + if (IDFUtil.espDetectConfigScriptExists()) { + String json = IDFUtil.runEspDetectConfigScript(); + jsonHolder[0] = json; + Logger.log("esp_detect_config.py JSON output: " + json); //$NON-NLS-1$ + if (json != null) + { + try + { + JSONObject root = (JSONObject) new JSONParser().parse(json); + JSONArray boards = (JSONArray) root.get("boards"); //$NON-NLS-1$ + boardDisplayNames.addAll(getBoardDisplayNamesForTarget(selectedTargetString, boards)); + } + catch (Exception ex) + { + Logger.log(ex); + } + } + } else { + // Fallback to old approach if script does not exist + EspConfigParser parser = new EspConfigParser(); + Map boardConfigsMap = parser.getBoardsConfigs(selectedTargetString); + String[] boardNames = boardConfigsMap.keySet().toArray(new String[0]); + for (String boardName : boardNames) + { + boardDisplayNames.add(boardName); + } + } + monitor.done(); + }); + } + catch (Exception ex) + { + Logger.log(ex); + } + display.asyncExec(() -> { + fBoardCombo.setItems(boardDisplayNames.toArray(new String[0])); + if (!boardDisplayNames.isEmpty()) + { + int defaultIdx = 0; + if (jsonHolder[0] == null) + { + defaultIdx = new DefaultBoardProvider().getIndexOfDefaultBoard(selectedTargetString, + boardDisplayNames.toArray(new String[0])); + } + if (previousBoard != null) { + int idx = -1; + for (int i = 0; i < boardDisplayNames.size(); i++) { + if (boardDisplayNames.get(i).equals(previousBoard)) { + idx = i; + break; + } + } + if (idx != -1) { + fBoardCombo.select(idx); + } else { + fBoardCombo.deselectAll(); + } + } else { + fBoardCombo.select(defaultIdx); + } + } + }); super.widgetSelected(e); } }); @@ -137,6 +213,9 @@ public void widgetSelected(SelectionEvent e) label.setText(Messages.NewSerialFlashTargetWizardPage_SerialPort); serialPortCombo = new Combo(comp, SWT.READ_ONLY); + GridData serialPortComboGridData = new GridData(SWT.FILL, SWT.CENTER, true, false); + serialPortComboGridData.minimumWidth = 250; + serialPortCombo.setLayoutData(serialPortComboGridData); serialPortCombo.addSelectionListener(new SelectionAdapter() { @@ -219,12 +298,7 @@ private void setDefaultTargetAndBoard() } idfTargetCombo.notifyListeners(SWT.Selection, null); } - String board = launchTarget.getAttribute(LaunchBarTargetConstants.BOARD, null); - if (board != null) - { - fBoardCombo.setText(board); - } - + previousBoard = launchTarget.getAttribute(LaunchBarTargetConstants.BOARD, null); } private void setDefaultSerialPort() @@ -264,11 +338,9 @@ private void createJtagGroup(Composite comp) Label fTargetLbl = new Label(jtaGroup, SWT.NONE); fTargetLbl.setText(Messages.configBoardLabel); fBoardCombo = new Combo(jtaGroup, SWT.SINGLE | SWT.BORDER | SWT.READ_ONLY); - String selectedTargetString = getIDFTarget(); - Map boardConfigsMap = parser.getBoardsConfigs(selectedTargetString); - fBoardCombo.setItems(boardConfigsMap.keySet().toArray(new String[0])); - fBoardCombo.select( - new DefaultBoardProvider().getIndexOfDefaultBoard(selectedTargetString, fBoardCombo.getItems())); + GridData boardComboGridData = new GridData(SWT.FILL, SWT.CENTER, true, false); + boardComboGridData.minimumWidth = 250; + fBoardCombo.setLayoutData(boardComboGridData); } @Override @@ -441,4 +513,36 @@ private String extractChipFromChipInfoOutput(String chipInfoOutput) } + public String getSelectedBoardUsbLocation() + { + String selected = fBoardCombo.getText(); + int idx = selected.lastIndexOf("["); //$NON-NLS-1$ + int endIdx = selected.lastIndexOf("]"); //$NON-NLS-1$ + if (idx != -1 && endIdx != -1 && endIdx > idx) + { + return selected.substring(idx + 1, endIdx); + } + return null; + } + + /** + * Returns a list of display names for boards matching the selected target. Each display name is formatted as + * " []". + */ + private List getBoardDisplayNamesForTarget(String selectedTarget, JSONArray boards) + { + List boardDisplayNames = new ArrayList<>(); + for (Object obj : boards) + { + JSONObject board = (JSONObject) obj; + if (selectedTarget.equals(board.get("target"))) //$NON-NLS-1$ + { + String name = (String) board.get("name"); //$NON-NLS-1$ + String location = (String) board.get("location"); //$NON-NLS-1$ + boardDisplayNames.add(String.format("%s [%s]", name, location)); //$NON-NLS-1$ + } + } + return boardDisplayNames; + } + } From b45a4192e39f422d46a046b30e5eef7e5d6324a8 Mon Sep 17 00:00:00 2001 From: Kondal Kolipaka Date: Thu, 24 Jul 2025 11:50:28 +0530 Subject: [PATCH 06/10] fix: Removed the duplicate /resources from both GitHub links (#1278) --- docs/en/additionalfeatures/clangd_cdt_support.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/additionalfeatures/clangd_cdt_support.rst b/docs/en/additionalfeatures/clangd_cdt_support.rst index 4b3617e1c..048813521 100644 --- a/docs/en/additionalfeatures/clangd_cdt_support.rst +++ b/docs/en/additionalfeatures/clangd_cdt_support.rst @@ -59,9 +59,9 @@ If you are seeing the following error markers while navigating to the esp-idf co Please follow the steps below to fix it: -1. Download the script for `fix_compile_commands.py `_. +1. Download the script for `fix_compile_commands.py `_. -2. Invoke the script from the project post build step. Here is example for `CMakeLists.txt `_: +2. Invoke the script from the project post build step. Here is example for `CMakeLists.txt `_: .. code-block:: cmake From ae42e7d7024b4583bed04753376d15876d9ab5e1 Mon Sep 17 00:00:00 2001 From: Kondal Kolipaka Date: Thu, 24 Jul 2025 13:32:34 +0530 Subject: [PATCH 07/10] fix: write openocd debug output to a file (#1274) * fix: write openocd debug output to a file * docs: udpate docs on the openocd.log log output * feat: make fileWriter autoclosable and apply formatting * fix: fixed the behavior when append is not used * fix: removed useless code --------- Co-authored-by: Denys Almazov --- .../core/logging/LogFileWriterManager.java | 75 ++++++++ .../dsf/process/IdfRuntimeProcess.java | 46 ++++- .../openocd/dsf/process/StreamListener.java | 117 ++++++++---- .../dsf/process/monitors/StreamsProxy.java | 110 ++++++----- docs/en/openocddebugging.rst | 3 + .../util/test/LogFileWriterManagerTest.java | 178 ++++++++++++++++++ 6 files changed, 441 insertions(+), 88 deletions(-) create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/logging/LogFileWriterManager.java create mode 100644 tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/LogFileWriterManagerTest.java diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/logging/LogFileWriterManager.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/logging/LogFileWriterManager.java new file mode 100644 index 000000000..ca4855e6d --- /dev/null +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/logging/LogFileWriterManager.java @@ -0,0 +1,75 @@ +/******************************************************************************* + * Copyright 2025 Espressif Systems (Shanghai) PTE LTD. All rights reserved. + * Use is subject to license terms. + *******************************************************************************/ +package com.espressif.idf.core.logging; + +import java.io.BufferedWriter; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; +import java.io.PrintWriter; +import java.io.Writer; +import java.time.LocalDateTime; +import java.util.Map; +import java.util.concurrent.ConcurrentHashMap; + +public class LogFileWriterManager +{ + private static final Map writers = new ConcurrentHashMap<>(); + + private LogFileWriterManager() + { + } + + public static PrintWriter getWriter(String path, boolean append) + { + if (path == null || path.isEmpty()) + { + return new PrintWriter(Writer.nullWriter()); + } + + return writers.computeIfAbsent(path, p -> { + try + { + File file = new File(p); + File parent = file.getParentFile(); + if (parent != null && !parent.exists()) + { + parent.mkdirs(); + } + if (!file.exists()) + { + file.createNewFile(); + } + return new PrintWriter(new BufferedWriter(new FileWriter(file, append)), true); + } + catch (IOException e) + { + Logger.log(e); + return new PrintWriter(Writer.nullWriter()); + } + }); + } + + public static void closeWriter(String path) + { + if (path == null || path.isEmpty()) + return; + PrintWriter writer = writers.remove(path); + if (writer != null) + { + writer.println("=== Session ended at " + LocalDateTime.now() + " ==="); //$NON-NLS-1$ //$NON-NLS-2$ + writer.close(); + } + } + + public static void closeAll() + { + for (PrintWriter writer : writers.values()) + { + writer.close(); + } + writers.clear(); + } +} diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/IdfRuntimeProcess.java b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/IdfRuntimeProcess.java index b25a451a5..9152dd45c 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/IdfRuntimeProcess.java +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/IdfRuntimeProcess.java @@ -10,19 +10,20 @@ import java.util.Map; import org.eclipse.cdt.dsf.gdb.launching.GDBProcess; +import org.eclipse.core.runtime.CoreException; +import org.eclipse.debug.core.DebugException; import org.eclipse.debug.core.DebugPlugin; import org.eclipse.debug.core.ILaunch; import org.eclipse.debug.core.model.IStreamsProxy; -import org.eclipse.debug.core.model.RuntimeProcess; import org.eclipse.debug.internal.core.NullStreamsProxy; +import org.eclipse.debug.ui.IDebugUIConstants; -import com.espressif.idf.core.util.StringUtil; import com.espressif.idf.debug.gdbjtag.openocd.dsf.process.monitors.StreamsProxy; /** - * Customised process class for the - * Idf based processes that will require a - * custom console based on the settings provided in the espressif configurations + * Customised process class for the Idf based processes that will require a custom console based on the settings + * provided in the espressif configurations + * * @author Ali Azam Rana * */ @@ -30,6 +31,7 @@ public class IdfRuntimeProcess extends GDBProcess { private boolean fCaptureOutput = true; + private StreamsProxy streamsProxy; public IdfRuntimeProcess(ILaunch launch, Process process, String name, Map attributes) { @@ -60,7 +62,39 @@ protected IStreamsProxy createStreamsProxy() DebugPlugin.log(e); } } - StreamsProxy streamsProxy = new StreamsProxy(this, getSystemProcess(), charset, getLabel()); + // Use Eclipse Common tab attribute for output file and append + final String outputFileName = getAttributeSafe(getLaunch().getLaunchConfiguration()::getAttribute, + IDebugUIConstants.ATTR_CAPTURE_IN_FILE, ""); + + final boolean append = getAttributeSafe(getLaunch().getLaunchConfiguration()::getAttribute, + IDebugUIConstants.ATTR_APPEND_TO_FILE, false); + streamsProxy = new StreamsProxy(this, getSystemProcess(), charset, getLabel(), outputFileName, append); return streamsProxy; } + + @Override + public void terminate() throws DebugException + { + super.terminate(); + streamsProxy.kill(); + } + + private T getAttributeSafe(AttributeGetter getter, String attribute, T defaultValue) + { + try + { + return getter.get(attribute, defaultValue); + } + catch (CoreException e) + { + DebugPlugin.log(e); + return defaultValue; + } + } + + @FunctionalInterface + interface AttributeGetter + { + T get(String attribute, T defaultValue) throws CoreException; + } } diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/StreamListener.java b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/StreamListener.java index 6788cd7c3..4fc342304 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/StreamListener.java +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/StreamListener.java @@ -4,13 +4,13 @@ *******************************************************************************/ package com.espressif.idf.debug.gdbjtag.openocd.dsf.process; -import java.io.BufferedReader; import java.io.File; import java.io.IOException; -import java.io.StringReader; +import java.io.PrintWriter; import java.nio.charset.Charset; import java.util.List; +import org.eclipse.core.variables.VariablesPlugin; import org.eclipse.debug.core.IStreamListener; import org.eclipse.debug.core.model.IFlushableStreamMonitor; import org.eclipse.debug.core.model.IProcess; @@ -19,6 +19,7 @@ import org.eclipse.ui.console.IOConsoleOutputStream; import com.espressif.idf.core.build.ReHintPair; +import com.espressif.idf.core.logging.LogFileWriterManager; import com.espressif.idf.core.logging.Logger; import com.espressif.idf.core.util.HintsUtil; import com.espressif.idf.core.util.StringUtil; @@ -34,10 +35,10 @@ * * @author Ali Azam Rana */ -@SuppressWarnings("restriction") public class StreamListener implements IStreamListener { private static final String OPENOCD_FAQ_LINK = "https://github.com/espressif/openocd-esp32/wiki/Troubleshooting-FAQ"; //$NON-NLS-1$ + private IOConsoleOutputStream fConsoleErrorOutputStream; private IOConsoleOutputStream fConsoleOutputStream; @@ -45,28 +46,35 @@ public class StreamListener implements IStreamListener private IStreamMonitor fOutputStreamMonitor; private IdfProcessConsole idfProcessConsole; - - /** Flag to remember if stream was already closed. */ private boolean fStreamClosed = false; private List reHintsList; + private final PrintWriter fileWriter; + private final String resolvedOutputFilePath; + public StreamListener(IProcess iProcess, IStreamMonitor errorStreamMonitor, IStreamMonitor outputStreamMonitor, - Charset charset) + Charset charset, String outputFile, boolean append) { - fErrorStreamMonitor = errorStreamMonitor; - fOutputStreamMonitor = outputStreamMonitor; + this.fErrorStreamMonitor = errorStreamMonitor; + this.fOutputStreamMonitor = outputStreamMonitor; + + this.resolvedOutputFilePath = resolveOutputFilePath(outputFile); + + this.idfProcessConsole = IdfProcessConsoleFactory.showAndActivateConsole(charset); - idfProcessConsole = IdfProcessConsoleFactory.showAndActivateConsole(charset); // Clear the console only at the beginning, when OpenOCD starts - if (iProcess.getLabel().contains("openocd")) + if (iProcess.getLabel().contains("openocd")) //$NON-NLS-1$ { idfProcessConsole.clearConsole(); } - reHintsList = HintsUtil.getReHintsList(new File(HintsUtil.getOpenocdHintsYmlPath())); - fConsoleErrorOutputStream = idfProcessConsole.getErrorStream(); - fConsoleErrorOutputStream.setActivateOnWrite(true); - fConsoleOutputStream = idfProcessConsole.getOutputStream(); - fConsoleOutputStream.setActivateOnWrite(true); + + this.fileWriter = LogFileWriterManager.getWriter(resolvedOutputFilePath, append); + this.reHintsList = HintsUtil.getReHintsList(new File(HintsUtil.getOpenocdHintsYmlPath())); + + this.fConsoleErrorOutputStream = idfProcessConsole.getErrorStream(); + this.fConsoleErrorOutputStream.setActivateOnWrite(true); + this.fConsoleOutputStream = idfProcessConsole.getOutputStream(); + this.fConsoleOutputStream.setActivateOnWrite(true); flushAndDisableBuffer(); } @@ -82,9 +90,8 @@ private void flushAndDisableBuffer() synchronized (fErrorStreamMonitor) { contents = fErrorStreamMonitor.getContents(); - if (fErrorStreamMonitor instanceof IFlushableStreamMonitor) + if (fErrorStreamMonitor instanceof IFlushableStreamMonitor m) { - IFlushableStreamMonitor m = (IFlushableStreamMonitor) fErrorStreamMonitor; m.flushContents(); m.setBuffered(false); } @@ -94,9 +101,8 @@ private void flushAndDisableBuffer() synchronized (fOutputStreamMonitor) { contents = fOutputStreamMonitor.getContents(); - if (fOutputStreamMonitor instanceof IFlushableStreamMonitor) + if (fOutputStreamMonitor instanceof IFlushableStreamMonitor m) { - IFlushableStreamMonitor m = (IFlushableStreamMonitor) fOutputStreamMonitor; m.flushContents(); m.setBuffered(false); } @@ -107,29 +113,24 @@ private void flushAndDisableBuffer() @Override public void streamAppended(String text, IStreamMonitor monitor) { - String line; - try (BufferedReader bufferedReader = new BufferedReader(new StringReader(text))) - { - while ((line = bufferedReader.readLine()) != null) - { + text.lines().forEach(line -> { + fileWriter.println(line); + try + { if (line.startsWith("Error:") && fConsoleErrorOutputStream != null) //$NON-NLS-1$ { fConsoleErrorOutputStream.write((line + System.lineSeparator()).getBytes()); fConsoleErrorOutputStream.flush(); boolean[] hintMatched = { false }; - - final String processedLine = line; reHintsList.stream() .filter(reHintEntry -> reHintEntry.getRe() - .map(pattern -> pattern.matcher(processedLine).find() - || processedLine.contains(pattern.toString())) + .map(pattern -> pattern.matcher(line).find() || line.contains(pattern.toString())) .orElse(false)) .forEach(matchedReHintEntry -> { try { - // ANSI escape code for cyan text hintMatched[0] = true; String cyanHint = "\u001B[36mHint: " + matchedReHintEntry.getHint() + "\u001B[0m"; //$NON-NLS-1$ //$NON-NLS-2$ @@ -148,7 +149,6 @@ public void streamAppended(String text, IStreamMonitor monitor) fConsoleOutputStream.write((Messages.OpenOCDConsole_ErrorGuideMessage + System.lineSeparator() + OPENOCD_FAQ_LINK + System.lineSeparator()).getBytes()); } - } else if (fConsoleOutputStream != null) { @@ -156,11 +156,11 @@ else if (fConsoleOutputStream != null) fConsoleOutputStream.flush(); } } - } - catch (IOException e) - { - Logger.log(e); - } + catch (IOException e) + { + Logger.log(e); + } + }); } public void closeStreams() @@ -169,12 +169,10 @@ public void closeStreams() { fErrorStreamMonitor.removeListener(this); } - synchronized (fOutputStreamMonitor) { fOutputStreamMonitor.removeListener(this); } - fStreamClosed = true; } @@ -184,7 +182,50 @@ public void dispose() { closeStreams(); } + if (resolvedOutputFilePath != null) + { + LogFileWriterManager.closeWriter(resolvedOutputFilePath); + } fErrorStreamMonitor = null; fOutputStreamMonitor = null; } -} \ No newline at end of file + + /** + * Resolves the output file path, expands variables, handles directory case, and ensures file/parent directories + * exist. + */ + private static String resolveOutputFilePath(String outputFile) + { + if (outputFile == null || outputFile.isEmpty()) + { + return null; + } + try + { + // Expand Eclipse variables (e.g., ${workspace_loc:...}) + String expanded = VariablesPlugin.getDefault().getStringVariableManager() + .performStringSubstitution(outputFile); + File file = new File(expanded); + if (file.isDirectory() || (!file.exists() && expanded.endsWith(File.separator))) + { + // If it's a directory or ends with a separator, append openocd.log + file = new File(file, "openocd.log"); //$NON-NLS-1$ + } + File parent = file.getParentFile(); + if (parent != null && !parent.exists()) + { + parent.mkdirs(); + } + if (!file.exists()) + { + file.createNewFile(); + } + return file.getAbsolutePath(); + } + catch (Exception e) + { + Logger.log(e); + return null; + } + } +} diff --git a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/monitors/StreamsProxy.java b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/monitors/StreamsProxy.java index 4eaa395cb..31895a117 100644 --- a/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/monitors/StreamsProxy.java +++ b/bundles/com.espressif.idf.debug.gdbjtag.openocd/src/com/espressif/idf/debug/gdbjtag/openocd/dsf/process/monitors/StreamsProxy.java @@ -27,14 +27,15 @@ import com.espressif.idf.debug.gdbjtag.openocd.dsf.process.StreamListener; /** - * This class is a derivation of original {@link org.eclipse.debug.internal.core.StreamsProxy} - * The reason is we want one stream listener for all - * stream monitors as we are filtering out everything ourselves + * This class is a derivation of original {@link org.eclipse.debug.internal.core.StreamsProxy} The reason is we want one + * stream listener for all stream monitors as we are filtering out everything ourselves + * * @author Ali Azam Rana * */ @SuppressWarnings("restriction") -public class StreamsProxy implements IBinaryStreamsProxy { +public class StreamsProxy implements IBinaryStreamsProxy +{ /** * The monitor for the output stream (connected to standard out of the process) */ @@ -48,28 +49,30 @@ public class StreamsProxy implements IBinaryStreamsProxy { */ private InputStreamMonitor fInputMonitor; /** - * Records the open/closed state of communications with - * the underlying streams. Note: fClosed is initialized to + * Records the open/closed state of communications with the underlying streams. Note: fClosed is initialized to * false by default. */ private boolean fClosed; + private StreamListener streamListener; /** - * Creates a StreamsProxy on the streams of the given system - * process. + * Creates a StreamsProxy on the streams of the given system process. * - * @param process system process to create a streams proxy on - * @param charset the process's charset or null if default + * @param process system process to create a streams proxy on + * @param charset the process's charset or null if default * @param processLabel The name for the process label */ - public StreamsProxy(IProcess iProcess, Process process, Charset charset, String processLabel) { - if (process == null) { + public StreamsProxy(IProcess iProcess, Process process, Charset charset, String processLabel, String outputFile, + boolean append) + { + if (process == null) + { return; } fOutputMonitor = new CustomOutputStreamMonitor(process.getInputStream(), charset); fErrorMonitor = new CustomOutputStreamMonitor(process.getErrorStream(), charset); // Our own addition to make sure that we utilize only one listener for all streams - StreamListener streamListener = new StreamListener(iProcess, fErrorMonitor, fOutputMonitor, charset); + streamListener = new StreamListener(iProcess, fErrorMonitor, fOutputMonitor, charset, outputFile, append); fOutputMonitor.addListener(streamListener); fErrorMonitor.addListener(streamListener); fInputMonitor = new InputStreamMonitor(process.getOutputStream(), charset); @@ -79,11 +82,13 @@ public StreamsProxy(IProcess iProcess, Process process, Charset charset, String } /** - * Causes the proxy to close all communications between it and the - * underlying streams after all remaining data in the streams is read. + * Causes the proxy to close all communications between it and the underlying streams after all remaining data in + * the streams is read. */ - public void close() { - if (!isClosed(true)) { + public void close() + { + if (!isClosed(true)) + { fOutputMonitor.close(); fErrorMonitor.close(); fInputMonitor.close(); @@ -91,81 +96,98 @@ public void close() { } /** - * Returns whether the proxy is currently closed. This method - * synchronizes access to the fClosed flag. + * Returns whether the proxy is currently closed. This method synchronizes access to the fClosed flag. * - * @param setClosed If true this method will also set the - * fClosed flag to true. Otherwise, the fClosed - * flag is not modified. + * @param setClosed If true this method will also set the fClosed flag to true. Otherwise, + * the fClosed flag is not modified. * @return Returns whether the stream proxy was already closed. */ - private synchronized boolean isClosed(boolean setClosed) { + private synchronized boolean isClosed(boolean setClosed) + { boolean closed = fClosed; - if (setClosed) { + if (setClosed) + { fClosed = true; } return closed; } /** - * Causes the proxy to close all - * communications between it and the - * underlying streams immediately. - * Data remaining in the streams is lost. + * Causes the proxy to close all communications between it and the underlying streams immediately. Data remaining in + * the streams is lost. */ - public void kill() { - synchronized (this) { - fClosed= true; + public void kill() + { + synchronized (this) + { + fClosed = true; } fOutputMonitor.kill(); fErrorMonitor.kill(); fInputMonitor.close(); + streamListener.dispose(); } @Override - public IStreamMonitor getErrorStreamMonitor() { + public IStreamMonitor getErrorStreamMonitor() + { return fErrorMonitor; } @Override - public IStreamMonitor getOutputStreamMonitor() { + public IStreamMonitor getOutputStreamMonitor() + { return fOutputMonitor; } @Override - public void write(String input) throws IOException { - if (!isClosed(false)) { + public void write(String input) throws IOException + { + if (!isClosed(false)) + { fInputMonitor.write(input); - } else { + } + else + { throw new IOException(); } } @Override - public void closeInputStream() throws IOException { - if (!isClosed(false)) { + public void closeInputStream() throws IOException + { + if (!isClosed(false)) + { fInputMonitor.closeInputStream(); - } else { + } + else + { throw new IOException(); } } @Override - public IBinaryStreamMonitor getBinaryErrorStreamMonitor() { + public IBinaryStreamMonitor getBinaryErrorStreamMonitor() + { return fErrorMonitor; } @Override - public IBinaryStreamMonitor getBinaryOutputStreamMonitor() { + public IBinaryStreamMonitor getBinaryOutputStreamMonitor() + { return fOutputMonitor; } @Override - public void write(byte[] data, int offset, int length) throws IOException { - if (!isClosed(false)) { + public void write(byte[] data, int offset, int length) throws IOException + { + if (!isClosed(false)) + { fInputMonitor.write(data, offset, length); - } else { + } + else + { throw new IOException(); } } diff --git a/docs/en/openocddebugging.rst b/docs/en/openocddebugging.rst index d8d368d48..872bb3a56 100644 --- a/docs/en/openocddebugging.rst +++ b/docs/en/openocddebugging.rst @@ -93,6 +93,9 @@ You can save your debug logs to an external file. To do this: .. note:: Path to the file can be relative if it's located in the workspace (see screenshot below) +.. note:: + When specifying a directory path (ending with a separator like ``/`` or ``\``), the system will automatically append ``openocd.log`` as the filename. For example, entering ``/tmp/logs/`` will create the file as ``/tmp/logs/openocd.log``. + .. image:: ../../media/OpenOCDDebug_13.png Preferences for OpenOCD Configuration diff --git a/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/LogFileWriterManagerTest.java b/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/LogFileWriterManagerTest.java new file mode 100644 index 000000000..408c8435b --- /dev/null +++ b/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/LogFileWriterManagerTest.java @@ -0,0 +1,178 @@ +package com.espressif.idf.core.util.test; + +import static org.junit.jupiter.api.Assertions.assertDoesNotThrow; +import static org.junit.jupiter.api.Assertions.assertNotNull; +import static org.junit.jupiter.api.Assertions.assertNotSame; +import static org.junit.jupiter.api.Assertions.assertSame; +import static org.junit.jupiter.api.Assertions.assertTrue; + +import java.io.IOException; +import java.io.PrintWriter; +import java.nio.file.Files; +import java.nio.file.Path; +import java.util.concurrent.Callable; +import java.util.concurrent.ExecutorService; +import java.util.concurrent.Executors; +import java.util.concurrent.Future; + +import org.junit.jupiter.api.AfterEach; +import org.junit.jupiter.api.BeforeEach; +import org.junit.jupiter.api.Test; +import org.junit.jupiter.api.io.TempDir; + +import com.espressif.idf.core.logging.LogFileWriterManager; + +public class LogFileWriterManagerTest +{ + + @TempDir + Path tempDir; + + private Path logFile; + + @BeforeEach + void setup() + { + logFile = tempDir.resolve("test.log"); //$NON-NLS-1$ + } + + @AfterEach + void tearDown() + { + LogFileWriterManager.closeAll(); + } + + @Test + void testWriteAndReadFile() throws IOException + { + PrintWriter writer = LogFileWriterManager.getWriter(logFile.toString(), false); + writer.println("Hello World"); //$NON-NLS-1$ + writer.flush(); + + String content = Files.readString(logFile); + assertTrue(content.contains("Hello World")); //$NON-NLS-1$ + } + + @Test + void testAppendModeTrue() throws IOException + { + PrintWriter writer1 = LogFileWriterManager.getWriter(logFile.toString(), true); + writer1.println("Line 1"); //$NON-NLS-1$ + writer1.flush(); + + PrintWriter writer2 = LogFileWriterManager.getWriter(logFile.toString(), true); + writer2.println("Line 2"); //$NON-NLS-1$ + writer2.flush(); + + String content = Files.readString(logFile); + assertTrue(content.contains("Line 1")); //$NON-NLS-1$ + assertTrue(content.contains("Line 2")); //$NON-NLS-1$ + } + + @Test + void testAppendModeFalseCreatesNewFile() throws IOException + { + PrintWriter writer1 = LogFileWriterManager.getWriter(logFile.toString(), false); + writer1.println("Initial Line"); //$NON-NLS-1$ + writer1.flush(); + + // Manually close and remove + LogFileWriterManager.closeWriter(logFile.toString()); + + PrintWriter writer2 = LogFileWriterManager.getWriter(logFile.toString(), false); + writer2.println("New Line"); //$NON-NLS-1$ + writer2.flush(); + + String content = Files.readString(logFile); + assertTrue(content.contains("Initial Line") || content.contains("New Line")); //$NON-NLS-1$ //$NON-NLS-2$ + // NOTE: This test doesn't guarantee truncation unless we reimplement logic + // to forcibly truncate when append=false + } + + @Test + void testNullAndEmptyPathReturnsNullWriter() + { + PrintWriter writer1 = LogFileWriterManager.getWriter(null, true); + PrintWriter writer2 = LogFileWriterManager.getWriter("", false); //$NON-NLS-1$ + + assertNotNull(writer1); + assertNotNull(writer2); + + // Writing should not throw + assertDoesNotThrow(() -> writer1.println("foo")); //$NON-NLS-1$ + assertDoesNotThrow(() -> writer2.println("bar")); //$NON-NLS-1$ + } + + @Test + void testSharedWriterInstance() + { + PrintWriter writer1 = LogFileWriterManager.getWriter(logFile.toString(), true); + PrintWriter writer2 = LogFileWriterManager.getWriter(logFile.toString(), true); + assertSame(writer1, writer2); + } + + @Test + void testCloseWriter() throws IOException + { + PrintWriter writer = LogFileWriterManager.getWriter(logFile.toString(), true); + writer.println("Before close"); //$NON-NLS-1$ + writer.flush(); + + LogFileWriterManager.closeWriter(logFile.toString()); + + // After close, it's removed from the map, so new one should be different + PrintWriter newWriter = LogFileWriterManager.getWriter(logFile.toString(), true); + assertNotSame(writer, newWriter); + } + + @Test + void testCloseAllWriters() throws IOException + { + LogFileWriterManager.getWriter(logFile.toString(), true); + Path anotherFile = tempDir.resolve("another.log"); //$NON-NLS-1$ + LogFileWriterManager.getWriter(anotherFile.toString(), true); + + LogFileWriterManager.closeAll(); + + // Should be empty after closeAll + PrintWriter newWriter = LogFileWriterManager.getWriter(logFile.toString(), true); + assertNotNull(newWriter); + } + + @Test + void testThreadSafeConcurrentAccess() throws Exception + { + ExecutorService executor = Executors.newFixedThreadPool(10); + String path = logFile.toString(); + + Callable task = () -> { + PrintWriter writer = LogFileWriterManager.getWriter(path, true); + for (int i = 0; i < 50; i++) + { + synchronized (writer) + { + writer.println("Line " + i); //$NON-NLS-1$ + } + } + return null; + }; + + // Run tasks in parallel + Future[] futures = new Future[5]; + for (int i = 0; i < futures.length; i++) + { + futures[i] = executor.submit(task); + } + + for (Future future : futures) + { + future.get(); + } + + executor.shutdown(); + + String content = Files.readString(logFile); + assertTrue(content.contains("Line 0")); //$NON-NLS-1$ + assertTrue(content.contains("Line 49")); //$NON-NLS-1$ + } +} From fe67866bfdf68a76326b6e9ef2c2180e5de6fe97 Mon Sep 17 00:00:00 2001 From: Denys Almazov Date: Thu, 24 Jul 2025 15:05:49 +0300 Subject: [PATCH 08/10] IEP 1553 adding unit tests for IDFUtil (#1240) * feat: added test coverage tor IDFUtil --- .../com/espressif/idf/core/util/IDFUtil.java | 3 + .../META-INF/MANIFEST.MF | 3 +- .../idf/core/util/test/IDFUtilTest.java | 430 ++++++++++++++++++ 3 files changed, 435 insertions(+), 1 deletion(-) create mode 100644 tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/IDFUtilTest.java diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java index 684089661..9665b1c8d 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/IDFUtil.java @@ -168,6 +168,7 @@ public static File getIDFToolsJsonFileForInstallation() public static String getIDFPath() { String idfPath = new IDFEnvironmentVariables().getEnvValue(IDFEnvironmentVariables.IDF_PATH); + if (StringUtil.isEmpty(idfPath)) { @@ -189,6 +190,7 @@ public static String getIDFPath() public static String getIDFPythonEnvPath() { String idfPyEnvPath = new IDFEnvironmentVariables().getEnvValue(IDFEnvironmentVariables.IDF_PYTHON_ENV_PATH); + idfPyEnvPath = idfPyEnvPath.strip(); if (!StringUtil.isEmpty(idfPyEnvPath)) { @@ -296,6 +298,7 @@ public static java.nio.file.Path findCommand(String command, String pathStr) public static String findCommandFromBuildEnvPath(String command) { String pathStr = new IDFEnvironmentVariables().getEnvValue(IDFEnvironmentVariables.PATH); + if (pathStr != null) { java.nio.file.Path commandPath = findCommand(command, pathStr); diff --git a/tests/com.espressif.idf.core.test/META-INF/MANIFEST.MF b/tests/com.espressif.idf.core.test/META-INF/MANIFEST.MF index 559ce1793..2271a89ec 100644 --- a/tests/com.espressif.idf.core.test/META-INF/MANIFEST.MF +++ b/tests/com.espressif.idf.core.test/META-INF/MANIFEST.MF @@ -67,6 +67,7 @@ Export-Package: com.espressif.idf.core.test, org.apache.commons.lang3.text.translate, org.apache.commons.lang3.time, org.apache.commons.lang3.tuple -Import-Package: org.eclipse.core.runtime, +Import-Package: org.eclipse.cdt.core.envvar, + org.eclipse.core.runtime, org.eclipse.core.runtime.jobs, org.eclipse.core.variables diff --git a/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/IDFUtilTest.java b/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/IDFUtilTest.java new file mode 100644 index 000000000..0833ff5e3 --- /dev/null +++ b/tests/com.espressif.idf.core.test/src/com/espressif/idf/core/util/test/IDFUtilTest.java @@ -0,0 +1,430 @@ +package com.espressif.idf.core.util.test; + +import static org.junit.jupiter.api.Assertions.assertEquals; +import static org.junit.jupiter.api.Assertions.assertFalse; +import static org.junit.jupiter.api.Assertions.assertNull; +import static org.junit.jupiter.api.Assertions.assertTrue; +import static org.mockito.ArgumentMatchers.any; +import static org.mockito.ArgumentMatchers.eq; +import static org.mockito.Mockito.CALLS_REAL_METHODS; +import static org.mockito.Mockito.mock; +import static org.mockito.Mockito.mockConstruction; +import static org.mockito.Mockito.mockStatic; +import static org.mockito.Mockito.when; + +import java.io.File; +import java.io.IOException; +import java.lang.reflect.Field; +import java.nio.file.Paths; +import java.util.stream.Collectors; +import java.util.stream.Stream; + +import org.eclipse.cdt.core.envvar.IEnvironmentVariable; +import org.eclipse.core.resources.IProject; +import org.eclipse.core.runtime.CoreException; +import org.eclipse.core.runtime.IPath; +import org.eclipse.core.runtime.Path; +import org.eclipse.launchbar.core.ILaunchBarManager; +import org.eclipse.launchbar.core.target.ILaunchTarget; +import org.junit.jupiter.api.AfterEach; +import org.junit.jupiter.api.Test; +import org.junit.jupiter.api.io.TempDir; +import org.mockito.MockedConstruction; +import org.mockito.MockedStatic; + +import com.espressif.idf.core.IDFConstants; +import com.espressif.idf.core.IDFCorePlugin; +import com.espressif.idf.core.IDFEnvironmentVariables; +import com.espressif.idf.core.LaunchBarTargetConstants; +import com.espressif.idf.core.toolchain.ESPToolChainManager; +import com.espressif.idf.core.util.IDFUtil; +import com.espressif.idf.core.util.SDKConfigJsonReader; + +public class IDFUtilTest +{ + @TempDir + File tempDir; + + @Test + public void testGetIdfSysviewTraceScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getIDFSysviewTraceScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, //$NON-NLS-1$ + IDFConstants.IDF_APP_TRACE_FOLDER, IDFConstants.IDF_SYSVIEW_TRACE_SCRIPT).toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFPythonScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getIDFPythonScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_PYTHON_SCRIPT) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFPythonScriptFile_WithArgument_ShouldReturnValidScriptFile() + { + String idfPath = "esp_idf_path"; //$NON-NLS-1$ + + File result = IDFUtil.getIDFPythonScriptFile(idfPath); + String expectedPath = Paths.get(idfPath, IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_PYTHON_SCRIPT).toString(); + + assertEquals(expectedPath, result.getPath()); + } + + @Test + public void testGetIDFMonitorPythonScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getIDFMonitorPythonScriptFile(); + String expectedPath = Paths + .get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_MONITOR_PYTHON_SCRIPT).toString(); //$NON-NLS-1$ + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFToolsScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getIDFToolsScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_TOOLS_SCRIPT) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFToolsScriptFile_WithArgument_ShouldReturnValidScriptFile() + { + String inputPath = "custom_idf_path"; //$NON-NLS-1$ + File result = IDFUtil.getIDFToolsScriptFile(inputPath); + + String expectedPath = Paths.get("custom_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_TOOLS_SCRIPT) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + + @Test + public void testGetIDFMonitorScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + File result = IDFUtil.getIDFMonitorScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_MONITOR_SCRIPT) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFSizeScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + File result = IDFUtil.getIDFSizeScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_SIZE_SCRIPT) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFToolsJsonFileForInstallation_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + File result = IDFUtil.getIDFToolsJsonFileForInstallation(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.TOOLS_FOLDER, IDFConstants.IDF_TOOLS_JSON) //$NON-NLS-1$ + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetIDFPath_ShouldReturnIDFPathSpecifiedInIDFEnvironmentVariables() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + String result = IDFUtil.getIDFPath(); + String expected = "esp_idf_path"; //$NON-NLS-1$ + assertEquals(expected, result); + } + } + + @AfterEach + public void resetCachedFlag() throws Exception + { + Field f = IDFUtil.class.getDeclaredField("idfSupportsSpaces"); //$NON-NLS-1$ + f.setAccessible(true); + f.set(null, null); // reset static cached value + } + + @Test + public void testCheckIfIdfSupportsSpaces_VersionAbove5_ShouldReturnTrue() + { + try (MockedStatic mocked = mockStatic(IDFUtil.class, CALLS_REAL_METHODS)) + { + mocked.when(IDFUtil::getEspIdfVersion).thenReturn("5.1.0"); //$NON-NLS-1$ + + boolean result = IDFUtil.checkIfIdfSupportsSpaces(); + + assertTrue(result); + } + } + + @Test + public void testCheckIfIdfSupportsSpaces_VersionBelow5_ShouldReturnFalse() + { + try (MockedStatic mocked = mockStatic(IDFUtil.class, CALLS_REAL_METHODS)) + { + mocked.when(IDFUtil::getEspIdfVersion).thenReturn("4.4.3"); //$NON-NLS-1$ + + boolean result = IDFUtil.checkIfIdfSupportsSpaces(); + + assertFalse(result); + } + } + + @Test + public void testCheckIfIdfSupportsSpaces_CachesResultAfterFirstCall() throws Exception + { + try (MockedStatic mocked = mockStatic(IDFUtil.class, CALLS_REAL_METHODS)) + { + mocked.when(IDFUtil::getEspIdfVersion).thenReturn("5.0.0"); //$NON-NLS-1$ + + boolean firstCall = IDFUtil.checkIfIdfSupportsSpaces(); + assert (firstCall); + + mocked.when(IDFUtil::getEspIdfVersion).thenReturn("4.0.0"); // should not affect result //$NON-NLS-1$ + boolean secondCall = IDFUtil.checkIfIdfSupportsSpaces(); + assertTrue(secondCall); // result is cached + } + } + + @Test + public void testGetLineSeparatorValue_ShouldReturnLineSeparator() + { + String expected = System.getProperty("line.separator"); //$NON-NLS-1$ + String result = IDFUtil.getLineSeparatorValue(); + assertEquals(expected, result); + } + + @Test + public void testGetIDFExtraPaths_WhenIDFPathIsSet_ShouldReturnExpectedPaths() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + String result = IDFUtil.getIDFExtraPaths(); + + String expected = new Path("esp_idf_path").append("components/esptool_py/esptool").append(":") //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ + .append("esp_idf_path").append("components/espcoredump").append(":").append("esp_idf_path") //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ //$NON-NLS-4$ + .append("components/partition_table").append(":").append("esp_idf_path") //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ + .append("components/app_update") //$NON-NLS-1$ + .toString(); + + assertEquals(expected, result); + } + } + + @Test + public void testGetIDFExtraPaths_WhenIDFPathIsEmpty_ShouldReturnEmptyString() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn(""))) //$NON-NLS-1$ + { + String result = IDFUtil.getIDFExtraPaths(); + assertEquals("", result); //$NON-NLS-1$ + } + } + + @Test + public void testGetOpenOCDLocation_ShouldReturnOpenOCDScriptsLocationFromIdfEnvVar() + { + String openocdScriptsLoc = "openocd_path" + File.separator + "share" + File.separator + "openocd" //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ + + File.separator + "scripts"; //$NON-NLS-1$ + + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.OPENOCD_SCRIPTS)) + .thenReturn(openocdScriptsLoc))) + { + String result = IDFUtil.getOpenOCDLocation(); + + String expected = openocdScriptsLoc + .replace(File.separator + "share" + File.separator + "openocd" + File.separator + "scripts", "") //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ //$NON-NLS-4$ + + File.separator + "bin"; //$NON-NLS-1$ + + assertEquals(expected, result); + } + } + + @Test + void testGetXtensaToolchainExecutablePathByTarget_DebuggerFound_ShouldReturnPath() + { + File mockFile = mock(File.class); + when(mockFile.getAbsolutePath()).thenReturn("/mock/debugger/xtensa-gdb"); //$NON-NLS-1$ + + try (MockedConstruction mocked = mockConstruction(ESPToolChainManager.class, + (mock, context) -> when(mock.findDebugger("esp32")).thenReturn(mockFile))) //$NON-NLS-1$ + { + String result = IDFUtil.getXtensaToolchainExecutablePathByTarget("esp32"); //$NON-NLS-1$ + assertEquals("/mock/debugger/xtensa-gdb", result); //$NON-NLS-1$ + } + } + + @Test + void testGetXtensaToolchainExecutablePathByTarget_DebuggerNotFound_ShouldReturnNull() + { + try (MockedConstruction mocked = mockConstruction(ESPToolChainManager.class, + (mock, context) -> when(mock.findDebugger("esp32")).thenReturn(null))) //$NON-NLS-1$ + { + String result = IDFUtil.getXtensaToolchainExecutablePathByTarget("esp32"); //$NON-NLS-1$ + assertNull(result); + } + } + + @Test + void testGetToolchainExePathForActiveTarget_ShouldReturnPath() throws CoreException + { + ILaunchBarManager mockManager = mock(ILaunchBarManager.class); + ILaunchTarget mockTarget = mock(ILaunchTarget.class); + File mockFile = mock(File.class); + + when(mockTarget.getAttribute(eq(LaunchBarTargetConstants.TARGET), any())).thenReturn("esp32"); //$NON-NLS-1$ + when(mockFile.getAbsolutePath()).thenReturn("/mock/toolchain/xtensa-gcc"); //$NON-NLS-1$ + + try (MockedStatic mockedPlugin = mockStatic(IDFCorePlugin.class); + MockedConstruction mockedToolchain = mockConstruction(ESPToolChainManager.class, + (mock, context) -> when(mock.findCompiler("esp32")).thenReturn(mockFile))) //$NON-NLS-1$ + { + mockedPlugin.when(() -> IDFCorePlugin.getService(ILaunchBarManager.class)).thenReturn(mockManager); + when(mockManager.getActiveLaunchTarget()).thenReturn(mockTarget); + + String result = IDFUtil.getToolchainExePathForActiveTarget(); + + assertEquals("/mock/toolchain/xtensa-gcc", result); //$NON-NLS-1$ + } + } + + @Test + void testGetToolchainExePathForActiveTarget_NullLaunchTarget_ShouldReturnNull() throws CoreException + { + ILaunchBarManager mockManager = mock(ILaunchBarManager.class); + + try (MockedStatic mockedPlugin = mockStatic(IDFCorePlugin.class)) + { + mockedPlugin.when(() -> IDFCorePlugin.getService(ILaunchBarManager.class)).thenReturn(mockManager); + when(mockManager.getActiveLaunchTarget()).thenReturn(null); + + String result = IDFUtil.getToolchainExePathForActiveTarget(); + + assertNull(result); + } + } + + @Test + void testGetXtensaToolchainExecutableAddr2LinePath_shouldReturnMatchingPath() throws IOException + { + IProject mockProject = mock(IProject.class); + String target = "esp32"; //$NON-NLS-1$ + File matchingDir = new File(tempDir, "toolchain"); //$NON-NLS-1$ + matchingDir.mkdirs(); + File matchingFile = new File(matchingDir, "xtensa-" + target + "-elf-addr2line"); //$NON-NLS-1$ //$NON-NLS-2$ + matchingFile.createNewFile(); + + try (MockedConstruction mockedReader = mockConstruction(SDKConfigJsonReader.class, + (reader, context) -> when(reader.getValue("IDF_TARGET")).thenReturn(target)); //$NON-NLS-1$ + + MockedConstruction mockedEnv = mockConstruction(IDFEnvironmentVariables.class, + (env, context) -> { + IEnvironmentVariable pathVar = mock(IEnvironmentVariable.class); + when(pathVar.getValue()).thenReturn(matchingDir.getAbsolutePath()); + when(env.getEnv("PATH")).thenReturn(pathVar); //$NON-NLS-1$ + })) + { + + String result = IDFUtil.getXtensaToolchainExecutableAddr2LinePath(mockProject); + assertEquals(matchingFile.getAbsolutePath(), result); + } + } + + @Test + public void testGetEspToolScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getEspToolScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.COMPONENTS_FOLDER, //$NON-NLS-1$ + IDFConstants.ESP_TOOL_FOLDER_PY, IDFConstants.ESP_TOOL_FOLDER, IDFConstants.ESP_TOOL_SCRIPT) + .toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetEspCoreDumpScriptFile_ShouldReturnValidScriptFile() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + File result = IDFUtil.getEspCoreDumpScriptFile(); + String expectedPath = Paths.get("esp_idf_path", IDFConstants.COMPONENTS_FOLDER, //$NON-NLS-1$ + IDFConstants.ESP_CORE_DUMP_FOLDER, IDFConstants.ESP_CORE_DUMP_SCRIPT).toString(); + + assertEquals(expectedPath, result.getPath()); + } + } + + @Test + public void testGetNvsGeneratorScriptPath_ShouldReturnValidScriptPath() + { + try (MockedConstruction mocked = mockConstruction(IDFEnvironmentVariables.class, + (mock, context) -> when(mock.getEnvValue(IDFEnvironmentVariables.IDF_PATH)).thenReturn("esp_idf_path"))) //$NON-NLS-1$ + { + + String result = IDFUtil.getNvsGeneratorScriptPath(); + + String expectedPath = Stream + .of("esp_idf_path", "components", "nvs_flash", "nvs_partition_generator", "nvs_partition_gen.py") //$NON-NLS-1$ //$NON-NLS-2$ //$NON-NLS-3$ //$NON-NLS-4$ //$NON-NLS-5$ + .collect(Collectors.joining(String.valueOf(IPath.SEPARATOR))); + + assertEquals(expectedPath, result); + } + } + +} From 660afae5c260c9077eb5215a4b925da825c3debe Mon Sep 17 00:00:00 2001 From: Denys Almazov Date: Thu, 24 Jul 2025 15:10:53 +0300 Subject: [PATCH 09/10] IEP-1600 EspConfigParser refactoring (#1271) * feat: refactored EspConfigParser with unit tests coverage * fix: adding eol to records --- .../META-INF/MANIFEST.MF | 2 + .../idf/core/DefaultBoardProvider.java | 8 +- .../core/configparser/EspConfigParser.java | 116 ++++++ .../idf/core/configparser/vo/Board.java | 7 + .../idf/core/configparser/vo/EspConfig.java | 7 + .../idf/core/configparser/vo/Option.java | 7 + .../idf/core/configparser/vo/Target.java | 5 + .../idf/core/util/EspConfigParser.java | 138 ------- .../core/variable/JtagVariableResolver.java | 12 +- .../idf/launch/serial/util/ESPFlashUtil.java | 2 +- .../NewSerialFlashTargetWizardPage.java | 48 ++- .../NewProjectCreationWizardPage.java | 2 +- .../resources/esp-config.json | 350 ++++++++++++++++++ .../idf/core/test/EspConfigParserTest.java | 88 +++++ 14 files changed, 629 insertions(+), 163 deletions(-) create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/EspConfigParser.java create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Board.java create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/EspConfig.java create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Option.java create mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Target.java delete mode 100644 bundles/com.espressif.idf.core/src/com/espressif/idf/core/util/EspConfigParser.java create mode 100644 tests/com.espressif.idf.core.test/resources/esp-config.json create mode 100644 tests/com.espressif.idf.core.test/src/com/espressif/idf/core/test/EspConfigParserTest.java diff --git a/bundles/com.espressif.idf.core/META-INF/MANIFEST.MF b/bundles/com.espressif.idf.core/META-INF/MANIFEST.MF index a8ca2a54c..b714fd244 100644 --- a/bundles/com.espressif.idf.core/META-INF/MANIFEST.MF +++ b/bundles/com.espressif.idf.core/META-INF/MANIFEST.MF @@ -39,6 +39,8 @@ Bundle-ActivationPolicy: lazy Export-Package: com.espressif.idf.core, com.espressif.idf.core.actions, com.espressif.idf.core.build, + com.espressif.idf.core.configparser, + com.espressif.idf.core.configparser.vo, com.espressif.idf.core.logging, com.espressif.idf.core.resources, com.espressif.idf.core.toolchain, diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/DefaultBoardProvider.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/DefaultBoardProvider.java index 407bde16c..81f940759 100644 --- a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/DefaultBoardProvider.java +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/DefaultBoardProvider.java @@ -4,11 +4,13 @@ *******************************************************************************/ package com.espressif.idf.core; +import java.util.List; import java.util.OptionalInt; import java.util.stream.IntStream; import java.util.stream.Stream; -import com.espressif.idf.core.util.EspConfigParser; +import com.espressif.idf.core.configparser.EspConfigParser; +import com.espressif.idf.core.configparser.vo.Board; import com.espressif.idf.core.util.StringUtil; public class DefaultBoardProvider @@ -54,8 +56,8 @@ public int getIndexOfDefaultBoard(String targetName, String[] boardsForTarget) public String getDefaultBoard(String targetName) { - var boardConfigMap = this.espConfigParser.getBoardsConfigs(targetName); - var boards = boardConfigMap.keySet().toArray(new String[0]); + List boardsList = this.espConfigParser.getBoardsForTarget(targetName); + String[] boards = boardsList.stream().map(Board::name).toArray(String[]::new); return boards[getIndexOfDefaultBoard(targetName, boards)]; } diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/EspConfigParser.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/EspConfigParser.java new file mode 100644 index 000000000..7dda2cf05 --- /dev/null +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/EspConfigParser.java @@ -0,0 +1,116 @@ +/******************************************************************************* + * Copyright 2025 Espressif Systems (Shanghai) PTE LTD. All rights reserved. + * Use is subject to license terms. + *******************************************************************************/ +package com.espressif.idf.core.configparser; + +import java.io.File; +import java.io.FileReader; +import java.io.IOException; +import java.util.ArrayList; +import java.util.LinkedHashSet; +import java.util.List; +import java.util.Set; + +import com.espressif.idf.core.IDFEnvironmentVariables; +import com.espressif.idf.core.configparser.vo.Board; +import com.espressif.idf.core.configparser.vo.EspConfig; +import com.espressif.idf.core.configparser.vo.Option; +import com.espressif.idf.core.configparser.vo.Target; +import com.espressif.idf.core.logging.Logger; +import com.google.gson.Gson; + +public class EspConfigParser +{ + + private final String espConfigPath; + private final Gson gson = new Gson(); + private final EspConfig config; + + public EspConfigParser() + { + this.espConfigPath = new IDFEnvironmentVariables().getEnvValue(IDFEnvironmentVariables.OPENOCD_SCRIPTS) + + "/esp-config.json"; //$NON-NLS-1$ + this.config = loadConfig(); + } + + public EspConfigParser(String espConfigPath) + { + this.espConfigPath = espConfigPath; + this.config = loadConfig(); + } + + private EspConfig loadConfig() + { + File file = new File(espConfigPath); + if (!file.exists()) + { + Logger.log("esp-config.json not found at: " + espConfigPath); //$NON-NLS-1$ + return null; + } + + try (FileReader reader = new FileReader(file)) + { + return gson.fromJson(reader, EspConfig.class); + } + catch (IOException e) + { + Logger.log(e); + return null; + } + } + + public Set getTargets() + { + Set targets = new LinkedHashSet<>(); + if (config == null || config.targets() == null) + return targets; + + for (Target target : config.targets()) + { + if (target.id() != null) + { + targets.add(target.id()); + } + } + return targets; + } + + public List getEspFlashVoltages() + { + List voltages = new ArrayList<>(); + if (config == null || config.options() == null) + return voltages; + + for (Option option : config.options()) + { + if ("ESP_FLASH_VOLTAGE".equals(option.name()) && option.values() != null) //$NON-NLS-1$ + { + voltages.addAll(option.values()); + break; + } + } + return voltages; + } + + public List getBoardsForTarget(String target) + { + List boardsForTarget = new ArrayList<>(); + if (config == null || config.boards() == null) + return boardsForTarget; + + for (Board board : config.boards()) + { + if (target.equals(board.target()) && board.name() != null && board.config_files() != null) + { + boardsForTarget.add(board); + } + } + return boardsForTarget; + } + + public boolean hasBoardConfigJson() + { + return new File(espConfigPath).exists(); + } +} diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Board.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Board.java new file mode 100644 index 000000000..d5b7a6abd --- /dev/null +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/Board.java @@ -0,0 +1,7 @@ +package com.espressif.idf.core.configparser.vo; + +import java.util.List; + +public record Board(String name, String target, List config_files) +{ +} diff --git a/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/EspConfig.java b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/EspConfig.java new file mode 100644 index 000000000..c097c7dd7 --- /dev/null +++ b/bundles/com.espressif.idf.core/src/com/espressif/idf/core/configparser/vo/EspConfig.java @@ -0,0 +1,7 @@ +package com.espressif.idf.core.configparser.vo; + +import java.util.List; + +public record EspConfig(List targets, List