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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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- static DEFINE_SPINLOCK (irq_controller_lock );
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+ static DEFINE_RAW_SPINLOCK (irq_controller_lock );
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/* Address of GIC 0 CPU interface */
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void __iomem * gic_cpu_base_addr __read_mostly ;
@@ -82,30 +82,30 @@ static void gic_mask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (d -> irq % 32 );
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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writel_relaxed (mask , gic_dist_base (d ) + GIC_DIST_ENABLE_CLEAR + (gic_irq (d ) / 32 ) * 4 );
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if (gic_arch_extn .irq_mask )
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gic_arch_extn .irq_mask (d );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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}
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static void gic_unmask_irq (struct irq_data * d )
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{
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u32 mask = 1 << (d -> irq % 32 );
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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if (gic_arch_extn .irq_unmask )
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gic_arch_extn .irq_unmask (d );
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writel_relaxed (mask , gic_dist_base (d ) + GIC_DIST_ENABLE_SET + (gic_irq (d ) / 32 ) * 4 );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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}
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static void gic_eoi_irq (struct irq_data * d )
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{
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if (gic_arch_extn .irq_eoi ) {
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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gic_arch_extn .irq_eoi (d );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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}
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writel_relaxed (gic_irq (d ), gic_cpu_base (d ) + GIC_CPU_EOI );
@@ -129,7 +129,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING )
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return - EINVAL ;
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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if (gic_arch_extn .irq_set_type )
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gic_arch_extn .irq_set_type (d , type );
@@ -154,7 +154,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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if (enabled )
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writel_relaxed (enablemask , base + GIC_DIST_ENABLE_SET + enableoff );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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return 0 ;
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}
@@ -182,10 +182,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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mask = 0xff << shift ;
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bit = 1 << (cpu + shift );
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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val = readl_relaxed (reg ) & ~mask ;
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writel_relaxed (val | bit , reg );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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return IRQ_SET_MASK_OK ;
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}
@@ -215,9 +215,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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chained_irq_enter (chip , desc );
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- spin_lock (& irq_controller_lock );
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+ raw_spin_lock (& irq_controller_lock );
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status = readl_relaxed (chip_data -> cpu_base + GIC_CPU_INTACK );
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- spin_unlock (& irq_controller_lock );
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+ raw_spin_unlock (& irq_controller_lock );
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gic_irq = (status & 0x3ff );
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if (gic_irq == 1023 )
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