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echesakovechesakov
authored
Arm64: Implement ReverseBitOrder (dotnet#233)
1 parent dfcf884 commit c6cf841

23 files changed

+3056
-3
lines changed

‎src/coreclr/src/jit/hwintrinsicarm64.cpp‎

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@@ -367,8 +367,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
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}
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case NI_ArmBase_LeadingZeroCount:
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case NI_ArmBase_ReverseElementBits:
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case NI_ArmBase_Arm64_LeadingSignCount:
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case NI_ArmBase_Arm64_LeadingZeroCount:
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case NI_ArmBase_Arm64_ReverseElementBits:
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case NI_Sha1_FixedRotate:
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{
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assert(numArgs == 1);

‎src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp‎

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@@ -248,8 +248,10 @@ void CodeGen::genSpecialIntrinsic(GenTreeHWIntrinsic* node)
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}
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case NI_ArmBase_LeadingZeroCount:
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case NI_ArmBase_ReverseElementBits:
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case NI_ArmBase_Arm64_LeadingSignCount:
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case NI_ArmBase_Arm64_LeadingZeroCount:
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case NI_ArmBase_Arm64_ReverseElementBits:
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{
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assert(op1 != nullptr);
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assert(op2 == nullptr);

‎src/coreclr/src/jit/hwintrinsiclistarm64.h‎

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@@ -66,6 +66,7 @@ HARDWARE_INTRINSIC(AdvSimd, PopCount, -
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HARDWARE_INTRINSIC(AdvSimd_Arm64, Abs, -1, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_abs, INS_invalid, INS_fabs}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
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HARDWARE_INTRINSIC(AdvSimd_Arm64, AbsScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_abs, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
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HARDWARE_INTRINSIC(AdvSimd_Arm64, Add, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fadd}, HW_Category_SIMDScalar, HW_Flag_NoContainment|HW_Flag_Commutative)
69+
HARDWARE_INTRINSIC(AdvSimd_Arm64, ReverseElementBits, -1, -1, 1, {INS_rbit, INS_rbit, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
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// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
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// ISA Function name ival SIMD size NumArg instructions Category Flags
@@ -83,6 +84,7 @@ HARDWARE_INTRINSIC(Aes, MixColumns, -
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// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
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// Base Intrinsics
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HARDWARE_INTRINSIC(ArmBase, LeadingZeroCount, -1, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_clz, INS_clz, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoContainment|HW_Flag_BaseTypeFromFirstArg)
87+
HARDWARE_INTRINSIC(ArmBase, ReverseElementBits, -1, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rbit, INS_rbit, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoContainment)
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// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
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// ISA Function name ival SIMD size NumArg instructions Category Flags
@@ -91,6 +93,7 @@ HARDWARE_INTRINSIC(ArmBase, LeadingZeroCount, -
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// Base 64-bit only Intrinsics
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HARDWARE_INTRINSIC(ArmBase_Arm64, LeadingSignCount, -1, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cls, INS_invalid, INS_cls, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoContainment|HW_Flag_BaseTypeFromFirstArg)
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HARDWARE_INTRINSIC(ArmBase_Arm64, LeadingZeroCount, -1, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_clz, INS_clz, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoContainment|HW_Flag_BaseTypeFromFirstArg)
96+
HARDWARE_INTRINSIC(ArmBase_Arm64, ReverseElementBits, -1, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rbit, INS_rbit, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoContainment)
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// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
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// ISA Function name ival SIMD size NumArg instructions Category Flags

‎src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_r.csproj‎

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@@ -10,6 +10,10 @@
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<ItemGroup>
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<Compile Include="Abs.Vector128.Double.cs" />
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<Compile Include="Abs.Vector128.UInt64.cs" />
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<Compile Include="ReverseElementBits.Vector128.Byte.cs" />
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<Compile Include="ReverseElementBits.Vector128.SByte.cs" />
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<Compile Include="ReverseElementBits.Vector64.Byte.cs" />
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<Compile Include="ReverseElementBits.Vector64.SByte.cs" />
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<Compile Include="Program.AdvSimd.Arm64.cs" />
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<Compile Include="..\Shared\Helpers.cs" />
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<Compile Include="..\Shared\Program.cs" />

‎src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_ro.csproj‎

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@@ -10,6 +10,10 @@
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<ItemGroup>
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<Compile Include="Abs.Vector128.Double.cs" />
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<Compile Include="Abs.Vector128.UInt64.cs" />
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<Compile Include="ReverseElementBits.Vector128.Byte.cs" />
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<Compile Include="ReverseElementBits.Vector128.SByte.cs" />
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<Compile Include="ReverseElementBits.Vector64.Byte.cs" />
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<Compile Include="ReverseElementBits.Vector64.SByte.cs" />
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<Compile Include="Program.AdvSimd.Arm64.cs" />
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<Compile Include="..\Shared\Helpers.cs" />
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<Compile Include="..\Shared\Program.cs" />

‎src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64.cs‎

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@@ -14,6 +14,10 @@ static Program()
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TestList = new Dictionary<string, Action>() {
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["Abs.Vector128.Double"] = Abs_Vector128_Double,
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["Abs.Vector128.UInt64"] = Abs_Vector128_UInt64,
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["ReverseElementBits.Vector128.Byte"] = ReverseElementBits_Vector128_Byte,
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["ReverseElementBits.Vector128.SByte"] = ReverseElementBits_Vector128_SByte,
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["ReverseElementBits.Vector64.Byte"] = ReverseElementBits_Vector64_Byte,
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["ReverseElementBits.Vector64.SByte"] = ReverseElementBits_Vector64_SByte,
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};
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}
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}

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