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git apple-llvm automerger
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Merge commit '3ba550a05afa' from llvm.org/master into apple/master
2 parents 8186857 + 3ba550a commit d1abe0b

15 files changed

+72
-82
lines changed

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -130,7 +130,7 @@ static inline unsigned getFnStackAlignment(const TargetSubtargetInfo *STI,
130130
const Function &F) {
131131
if (F.hasFnAttribute(Attribute::StackAlignment))
132132
return F.getFnStackAlignment();
133-
return STI->getFrameLowering()->getStackAlignment();
133+
return STI->getFrameLowering()->getStackAlign().value();
134134
}
135135

136136
MachineFunction::MachineFunction(const Function &F,

‎llvm/lib/CodeGen/PrologEpilogInserter.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -438,14 +438,12 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F,
438438
unsigned Size = RegInfo->getSpillSize(*RC);
439439
if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
440440
// Nope, just spill it anywhere convenient.
441-
unsigned Align = RegInfo->getSpillAlignment(*RC);
442-
unsigned StackAlign = TFI->getStackAlignment();
443-
441+
Align Alignment(RegInfo->getSpillAlignment(*RC));
444442
// We may not be able to satisfy the desired alignment specification of
445443
// the TargetRegisterClass if the stack alignment is smaller. Use the
446444
// min.
447-
Align = std::min(Align, StackAlign);
448-
FrameIdx = MFI.CreateStackObject(Size, Align, true);
445+
Alignment = std::min(Alignment, TFI->getStackAlign());
446+
FrameIdx = MFI.CreateStackObject(Size, Alignment, true);
449447
if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
450448
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
451449
} else {

‎llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
8585
TLI = MF->getSubtarget().getTargetLowering();
8686
RegInfo = &MF->getRegInfo();
8787
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
88-
unsigned StackAlign = TFI->getStackAlignment();
8988
DA = DAG->getDivergenceAnalysis();
9089

9190
// Check whether the function can return without sret-demotion.
@@ -130,19 +129,19 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
130129
// Initialize the mapping of values to registers. This is only set up for
131130
// instruction values that are used outside of the block that defines
132131
// them.
132+
const Align StackAlign = TFI->getStackAlign();
133133
for (const BasicBlock &BB : *Fn) {
134134
for (const Instruction &I : BB) {
135135
if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
136136
Type *Ty = AI->getAllocatedType();
137-
unsigned Align =
138-
std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
139-
AI->getAlignment());
137+
Align Alignment =
138+
max(MF->getDataLayout().getPrefTypeAlign(Ty), AI->getAlign());
140139

141140
// Static allocas can be folded into the initial stack frame
142141
// adjustment. For targets that don't realign the stack, don't
143142
// do this if there is an extra alignment requirement.
144143
if (AI->isStaticAlloca() &&
145-
(TFI->isStackRealignable() || (Align <= StackAlign))) {
144+
(TFI->isStackRealignable() || (Alignment <= StackAlign))) {
146145
const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
147146
uint64_t TySize =
148147
MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinSize();
@@ -154,10 +153,10 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
154153
if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
155154
FrameIndex = MF->getFrameInfo().CreateFixedObject(
156155
TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
157-
MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
156+
MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment);
158157
} else {
159-
FrameIndex =
160-
MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
158+
FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment,
159+
false, AI);
161160
}
162161

163162
// Scalable vectors may need a special StackID to distinguish
@@ -176,10 +175,9 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
176175
// FIXME: Overaligned static allocas should be grouped into
177176
// a single dynamic allocation instead of using a separate
178177
// stack allocation for each one.
179-
if (Align <= StackAlign)
180-
Align = 0;
181178
// Inform the Frame Information that we have variable-sized objects.
182-
MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, AI);
179+
MF->getFrameInfo().CreateVariableSizedObject(
180+
Alignment <= StackAlign ? 0 : Alignment.value(), AI);
183181
}
184182
}
185183

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4027,8 +4027,7 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
40274027
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
40284028
auto &DL = DAG.getDataLayout();
40294029
uint64_t TySize = DL.getTypeAllocSize(Ty);
4030-
unsigned Align =
4031-
std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
4030+
MaybeAlign Alignment = max(DL.getPrefTypeAlign(Ty), I.getAlign());
40324031

40334032
SDValue AllocSize = getValue(I.getArraySize());
40344033

@@ -4043,25 +4042,26 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
40434042
// Handle alignment. If the requested alignment is less than or equal to
40444043
// the stack alignment, ignore it. If the size is greater than or equal to
40454044
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
4046-
unsigned StackAlign =
4047-
DAG.getSubtarget().getFrameLowering()->getStackAlignment();
4048-
if (Align <= StackAlign)
4049-
Align = 0;
4045+
Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign();
4046+
if (Alignment <= StackAlign)
4047+
Alignment = None;
40504048

4049+
const uint64_t StackAlignMask = StackAlign.value() - 1U;
40514050
// Round the size of the allocation up to the stack alignment size
40524051
// by add SA-1 to the size. This doesn't overflow because we're computing
40534052
// an address inside an alloca.
40544053
SDNodeFlags Flags;
40554054
Flags.setNoUnsignedWrap(true);
40564055
AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
4057-
DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags);
4056+
DAG.getConstant(StackAlignMask, dl, IntPtr), Flags);
40584057

40594058
// Mask out the low bits for alignment purposes.
4060-
AllocSize =
4061-
DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
4062-
DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr));
4059+
AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
4060+
DAG.getConstant(~StackAlignMask, dl, IntPtr));
40634061

4064-
SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)};
4062+
SDValue Ops[] = {
4063+
getRoot(), AllocSize,
4064+
DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
40654065
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
40664066
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
40674067
setValue(&I, DSA);

‎llvm/lib/Target/AVR/AVRFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -378,7 +378,7 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
378378
// For adjcallstackdown we convert it into an 'adiw reg, <amt>' handling
379379
// the read and write of SP in I/O space.
380380
if (Amount != 0) {
381-
assert(getStackAlignment() == 1 && "Unsupported stack alignment");
381+
assert(getStackAlign() == Align(1) && "Unsupported stack alignment");
382382

383383
if (Opcode == TII.getCallFrameSetupOpcode()) {
384384
fixStackStores(MBB, MI, TII, true);

‎llvm/lib/Target/MSP430/MSP430FrameLowering.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -223,8 +223,6 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
223223
MachineBasicBlock::iterator I) const {
224224
const MSP430InstrInfo &TII =
225225
*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
226-
unsigned StackAlign = getStackAlignment();
227-
228226
if (!hasReservedCallFrame(MF)) {
229227
// If the stack pointer can be changed after prologue, turn the
230228
// adjcallstackup instruction into a 'sub SP, <amt>' and the
@@ -236,7 +234,7 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
236234
// We need to keep the stack aligned properly. To do this, we round the
237235
// amount of space needed for the outgoing arguments up to the next
238236
// alignment boundary.
239-
Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
237+
Amount = alignTo(Amount, getStackAlign());
240238

241239
MachineInstr *New = nullptr;
242240
if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) {

‎llvm/lib/Target/Mips/MipsCallLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,8 +179,9 @@ Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
179179
MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
180180

181181
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
182-
unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
183-
MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
182+
Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
183+
MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
184+
Alignment.value());
184185

185186
return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
186187
}

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -498,9 +498,9 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
498498

499499
// Get stack alignments.
500500
const PPCFrameLowering *TFI = getFrameLowering(MF);
501-
unsigned TargetAlign = TFI->getStackAlignment();
502-
unsigned MaxAlign = MFI.getMaxAlign().value();
503-
assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
501+
Align TargetAlign = TFI->getStackAlign();
502+
Align MaxAlign = MFI.getMaxAlign();
503+
assert(isAligned(MaxAlign, maxCallFrameSize) &&
504504
"Maximum call-frame size not sufficiently aligned");
505505

506506
// Determine the previous frame's address. If FrameSize can't be
@@ -545,7 +545,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
545545
// Unfortunately, there is no andi, only andi., and we can't insert that
546546
// here because we might clobber cr0 while it is live.
547547
BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
548-
.addImm(~(MaxAlign-1));
548+
.addImm(~(MaxAlign.value() - 1));
549549

550550
unsigned NegSizeReg1 = NegSizeReg;
551551
NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
@@ -570,7 +570,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
570570
// Unfortunately, there is no andi, only andi., and we can't insert that
571571
// here because we might clobber cr0 while it is live.
572572
BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
573-
.addImm(~(MaxAlign-1));
573+
.addImm(~(MaxAlign.value() - 1));
574574

575575
unsigned NegSizeReg1 = NegSizeReg;
576576
NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -631,7 +631,6 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
631631
const MachineFrameInfo &MFI = MF.getFrameInfo();
632632
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
633633
uint64_t StackSize = MFI.getStackSize();
634-
uint64_t StackAlign = getStackAlignment();
635634

636635
// Disable SplitSPAdjust if save-restore libcall used. The callee saved
637636
// registers will be pushed by the save-restore libcalls, so we don't have to
@@ -648,7 +647,7 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
648647
// load/store instruction and we have to stick with the stack alignment.
649648
// 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16,
650649
// for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment.
651-
return 2048 - StackAlign;
650+
return 2048 - getStackAlign().value();
652651
}
653652
return 0;
654653
}

‎llvm/lib/Target/X86/X86CallFrameOptimization.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ bool X86CallFrameOptimization::isProfitable(MachineFunction &MF,
198198
if (CannotReserveFrame)
199199
return true;
200200

201-
unsigned StackAlign = TFL->getStackAlignment();
201+
Align StackAlign = TFL->getStackAlign();
202202

203203
int64_t Advantage = 0;
204204
for (auto CC : CallSeqVector) {
@@ -221,7 +221,7 @@ bool X86CallFrameOptimization::isProfitable(MachineFunction &MF,
221221
// We'll need a add after the call.
222222
Advantage -= 3;
223223
// If we have to realign the stack, we'll also need a sub before
224-
if (CC.ExpectedDist % StackAlign)
224+
if (!isAligned(StackAlign, CC.ExpectedDist))
225225
Advantage -= 3;
226226
// Now, for each push, we save ~3 bytes. For small constants, we actually,
227227
// save more (up to 5 bytes), but 3 should be a good approximation.

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