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| 1 | +// Licensed under the Apache License, Version 2.0 (the "License"); |
| 2 | +// you may not use this file except in compliance with the License. |
| 3 | +// You may obtain a copy of the License at |
| 4 | +// |
| 5 | +// http://www.apache.org/licenses/LICENSE-2.0 |
| 6 | +// |
| 7 | +// Unless required by applicable law or agreed to in writing, software |
| 8 | +// distributed under the License is distributed on an "AS IS" BASIS, |
| 9 | +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 10 | +// See the License for the specific language governing permissions and |
| 11 | +// limitations under the License. |
| 12 | + |
| 13 | +#include <assert.h> |
| 14 | +#include <esp_spi_flash.h> |
| 15 | +#include <stdint.h> |
| 16 | +#include <stdio.h> |
| 17 | +#include <string.h> |
| 18 | +#include <sys/param.h> |
| 19 | +#include <unity.h> |
| 20 | + |
| 21 | +#include "FreeRTOS.h" |
| 22 | +#include <driver/hw_timer.h> |
| 23 | +#include "esp8266/timer_register.h" |
| 24 | + |
| 25 | +#define TIMER1_ENABLE_TIMER 0x0080 |
| 26 | +#define TIMER1_INTERRUPT_TYPE_LEVEL 1 |
| 27 | +#define hw_timer_intr_register(a, b) \ |
| 28 | + _xt_isr_attach(ETS_FRC_TIMER1_INUM, (a), (b)) |
| 29 | + |
| 30 | +struct timer_regs { |
| 31 | + uint32_t frc1_load; /* 0x60000600 */ |
| 32 | + uint32_t frc1_count; /* 0x60000604 */ |
| 33 | + uint32_t frc1_ctrl; /* 0x60000608 */ |
| 34 | + uint32_t frc1_int; /* 0x6000060C */ |
| 35 | +}; |
| 36 | +static struct timer_regs *timer = (struct timer_regs *)(PERIPHS_TIMER_BASEDDR); |
| 37 | + |
| 38 | +static void test_timer_cb(void *cpu_clk_cnt) { |
| 39 | + *(uint32_t *)cpu_clk_cnt = soc_get_ccount(); |
| 40 | +} |
| 41 | + |
| 42 | +TEST_CASE("Test interrupt overhead time", "[log]") { |
| 43 | + volatile uint32_t cpu_clk_cnt_interrupt_enter; |
| 44 | + uint32_t cpu_clk_cnt_start; |
| 45 | + uint32_t cpu_clk_cnt_stop; |
| 46 | + |
| 47 | + // Execute the test twice and only take the second result to make sure |
| 48 | + // that IRAM has cached all instructions. |
| 49 | + for (int i = 0; i < 2; i++) { |
| 50 | + cpu_clk_cnt_interrupt_enter = 0; |
| 51 | + hw_timer_init(test_timer_cb, (void *)&cpu_clk_cnt_interrupt_enter); |
| 52 | + hw_timer_intr_register(test_timer_cb, (void *)&cpu_clk_cnt_interrupt_enter); |
| 53 | + |
| 54 | + // Setup the timer, so that it'll trigger exactly once. |
| 55 | + timer->frc1_int = 0; // reset the interrupt status |
| 56 | + timer->frc1_load = 0; // trigger the timer interrupt immediately |
| 57 | + timer->frc1_ctrl = TIMER1_ENABLE_TIMER | TIMER1_INTERRUPT_TYPE_LEVEL; |
| 58 | + cpu_clk_cnt_start = soc_get_ccount(); |
| 59 | + |
| 60 | + // busy wait until the interrupt triggered and updated the variable |
| 61 | + while (!cpu_clk_cnt_interrupt_enter) |
| 62 | + ; |
| 63 | + |
| 64 | + cpu_clk_cnt_stop = soc_get_ccount(); |
| 65 | + hw_timer_deinit(); |
| 66 | + } |
| 67 | + |
| 68 | + uint32_t overhead_enter = cpu_clk_cnt_interrupt_enter - cpu_clk_cnt_start; |
| 69 | + uint32_t overhead_total = cpu_clk_cnt_stop - cpu_clk_cnt_start; |
| 70 | + |
| 71 | +#if CONFIG_OPTIMIZATION_LEVEL_DEBUG |
| 72 | +# define INTERRUPT_OVERHEAD_ENTER_TIME 334 |
| 73 | +# define INTERRUPT_OVERHEAD_TOTAL_TIME 459 |
| 74 | +#else // CONFIG_OPTIMIZATION_LEVEL_RELEASE |
| 75 | +# define INTERRUPT_OVERHEAD_ENTER_TIME 258 |
| 76 | +# define INTERRUPT_OVERHEAD_TOTAL_TIME 385 |
| 77 | +#endif |
| 78 | + |
| 79 | + if (overhead_enter != INTERRUPT_OVERHEAD_ENTER_TIME || |
| 80 | + overhead_total != INTERRUPT_OVERHEAD_TOTAL_TIME) { |
| 81 | + char buf[128]; |
| 82 | + snprintf(buf, sizeof(buf), |
| 83 | + "interrupt overhead times changed. expected (enter=%d, total=%d), " |
| 84 | + "but got (enter=%d, total=%d)", |
| 85 | + INTERRUPT_OVERHEAD_ENTER_TIME, INTERRUPT_OVERHEAD_TOTAL_TIME, |
| 86 | + overhead_enter, overhead_total); |
| 87 | + TEST_FAIL_MESSAGE(buf); |
| 88 | + } |
| 89 | +} |
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