Merge tag 'tags/fpga-wdt-250619' into linux-6.12-mchp

cristibirsan · cristibirsan · commit ce8a34173aea · 2025-06-20T17:17:48.000+03:00
FPGA wdt updates for 250619

* watchdog: microchip: Add support for MPFS WDT (Daire McNamara 2025-05-20)
* dt-bindings: watchdog: microchip: Add bindings for MPFS Watchdogs (Daire McNamara 2025-05-20)

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
diff --git a/Documentation/devicetree/bindings/microchip,mpfs-wdt.yaml b/Documentation/devicetree/bindings/microchip,mpfs-wdt.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/microchip,mpfs-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire SoC Watchdog Timer
+
+allOf:
+  - $ref: "watchdog.yaml#"
+
+maintainers:
+  - Daire McNamara <daire.mcnamara@microchip.com>
+
+properties:
+  compatible:
+      const: microchip,mpfs-wdt
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    items:
+      - description: The MPFS watchdog uses a 24-bit counter that counts every 256 PCLK cycles,
+                     providing a maximum watchdog refresh rate of 13.74 seconds (assuming a
+                     312.5 MHz APB clock rate), 14.32 seconds (assuming a 300 MHz ABP clock rate),
+                     or 28.63 seconds (assuming a 150 MHz ABP clock rate).
+
+  interrupts:
+    maxItems: 2
+    items:
+      - description: an mvrp interrupt indicates that the watchdog is in the period between its
+                     mvrp counter and its trig counter.  This indicates the watchdog can be
+                     serviced in this period.
+      - description: a trig interrupt indicates that the watchdog is in the period between its
+                     trig counter (a maximum of 2^11 - 1 ticks) and 0.  The watchdog cannot be stopped
+                     but any emergency actions can be triggered by handling this interrupt.
+
+  interrupt-names:
+    maxItems: 2
+    items:
+      - const: mvrp
+      - const: trig
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    watchdog@20001000 {
+        compatible = "microchip,mpfs-wdt";
+        reg = <0x20001000 0x1000>;
+        interrupts = <100>, <105>;
+        clocks = <&pclk>;
+    };
+
+...
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
@@ -217,6 +217,18 @@ config DA9052_WATCHDOG
 	  Alternatively say M to compile the driver as a module,
 	  which will be called da9052_wdt.
 
+config MPFS_WATCHDOG
+	tristate "Microchip PolarFire SoC Watchdog"
+	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
+	select WATCHDOG_CORE
+	help
+	  Support for the watchdog in the PolarFire SoC. Watchdog trigger
+	  cause system reset.
+
+	  Say Y here to include support for the PolarFire watchdog.
+	  Alternatively say M to compile the driver as a module,
+	  which will be called mpfs_wdt.
+
 config DA9055_WATCHDOG
 	tristate "Dialog Semiconductor DA9055 Watchdog"
 	depends on MFD_DA9055 || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
@@ -196,6 +196,7 @@ obj-$(CONFIG_PSERIES_WDT) += pseries-wdt.o
 obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o
 
 # RISC-V Architecture
+obj-$(CONFIG_MPFS_WATCHDOG) += mpfs_wdt.o
 obj-$(CONFIG_STARFIVE_WATCHDOG) += starfive-wdt.o
 
 # S390 Architecture
diff --git a/drivers/watchdog/mpfs_wdt.c b/drivers/watchdog/mpfs_wdt.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Watchdog driver for Microchip PolarFire SoC watchdog.
+ *
+ * Copyright (C) 2025 Microchip Corporation
+ */
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/watchdog.h>
+
+#define MPFS_WDT_REFRESH	0x0
+#define  MPFS_WDT_MAGIC_WORD	0xdeadc0de
+#define MPFS_WDT_CONTROL	0x4
+#define MPFS_WDT_STATUS		0x8
+#define  MPFS_MVRP_TRIPPED	0x1
+#define  MPFS_WDOG_TRIPPED	0x2
+#define MPFS_WDT_TIME		0xc
+#define MPFS_WDT_MSVP		0x10
+
+/* 24-bit counter */
+#define MPFS_WDT_LOAD_MAX	0xfffff0
+#define MPFS_WDT_LOAD_MIN	1
+
+#define MPFS_WDT_CLK_PRESCALER	256
+
+struct mpfs_wdt {
+	struct watchdog_device wdd;
+	struct clk *clk;
+	unsigned int rate_hz;
+	int mvrp_irq;
+	int trig_irq;
+	void __iomem *base;
+};
+
+static void mpfs_wdt_set_timeout_reg(struct watchdog_device *wdog)
+{
+	struct mpfs_wdt *mpfs_wdt = watchdog_get_drvdata(wdog);
+	u32 trig_counter = wdog->timeout * mpfs_wdt->rate_hz;
+
+	writel(trig_counter, mpfs_wdt->base + MPFS_WDT_TIME);
+}
+
+static void mpfs_wdt_set_pretimeout_reg(struct watchdog_device *wdog)
+{
+	struct mpfs_wdt *mpfs_wdt = watchdog_get_drvdata(wdog);
+	u32 mvrp_counter = 0;
+	u32 mvrp_secs;
+
+	if (wdog->pretimeout) {
+		mvrp_secs = wdog->timeout - wdog->pretimeout;
+		mvrp_counter = mvrp_secs * mpfs_wdt->rate_hz;
+ 	}
+
+	writel(mvrp_counter, mpfs_wdt->base + MPFS_WDT_MSVP);
+}
+
+static int mpfs_wdt_ping(struct watchdog_device *wdog)
+{
+	struct mpfs_wdt *mpfs_wdt = watchdog_get_drvdata(wdog);
+
+	writel(MPFS_WDT_MAGIC_WORD, mpfs_wdt->base + MPFS_WDT_REFRESH);
+
+	return 0;
+}
+
+static int mpfs_wdt_start(struct watchdog_device *wdog)
+{
+	return mpfs_wdt_ping(wdog);
+}
+
+static int mpfs_wdt_stop(struct watchdog_device *wdog)
+{
+	/* can't stop the dog, just return */
+	return 0;
+}
+
+static int mpfs_wdt_set_timeout(struct watchdog_device *wdog, u32 timeout_secs)
+{
+	wdog->timeout = timeout_secs;
+	mpfs_wdt_set_pretimeout_reg(wdog);
+	mpfs_wdt_set_timeout_reg(wdog);
+
+	return 0;
+}
+
+static int mpfs_wdt_set_pretimeout(struct watchdog_device *wdog, u32 timeout_secs)
+{
+	if (timeout_secs > wdog->timeout)
+		return -EINVAL;
+
+	wdog->pretimeout = timeout_secs;
+	mpfs_wdt_set_pretimeout_reg(wdog);
+
+	return 0;
+}
+
+static unsigned int mpfs_wdt_get_timeleft(struct watchdog_device *wdog)
+{
+	struct mpfs_wdt *mpfs_wdt = watchdog_get_drvdata(wdog);
+	u32 time_secs;
+
+	time_secs = readl(mpfs_wdt->base + MPFS_WDT_REFRESH) / mpfs_wdt->rate_hz;
+
+	return time_secs;
+}
+
+static irqreturn_t mpfs_wdt_trig_isr(int irq, void *dev_id)
+{
+	struct mpfs_wdt *mpfs_wdt = dev_id;
+
+	writel(MPFS_WDOG_TRIPPED, mpfs_wdt->base + MPFS_WDT_STATUS);
+
+	dev_crit(mpfs_wdt->wdd.parent, "Microchip PolarFire SoC wdt tripped\n");
+	emergency_restart();
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mpfs_wdt_mvrp_isr(int irq, void *dev_id)
+{
+	struct mpfs_wdt *mpfs_wdt = dev_id;
+
+	writel(MPFS_MVRP_TRIPPED, mpfs_wdt->base + MPFS_WDT_STATUS);
+	watchdog_notify_pretimeout(&mpfs_wdt->wdd);
+
+	return IRQ_HANDLED;
+}
+
+static const struct watchdog_info mpfs_wdt_info = {
+	.identity = "Microchip PolarFire SoC Watchdog",
+	.options = WDIOF_SETTIMEOUT |
+		   WDIOF_PRETIMEOUT |
+		   WDIOF_MAGICCLOSE |
+		   WDIOF_KEEPALIVEPING,
+};
+
+static const struct watchdog_ops mpfs_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = mpfs_wdt_start,
+	.stop = mpfs_wdt_stop,
+	.ping = mpfs_wdt_ping,
+	.set_timeout = mpfs_wdt_set_timeout,
+	.set_pretimeout = mpfs_wdt_set_pretimeout,
+	.get_timeleft = mpfs_wdt_get_timeleft,
+};
+
+static int mpfs_wdt_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mpfs_wdt *mpfs_wdt;
+	int ret;
+
+	mpfs_wdt = devm_kzalloc(dev, sizeof(*mpfs_wdt), GFP_KERNEL);
+	if (!mpfs_wdt)
+		return -ENOMEM;
+
+	mpfs_wdt->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mpfs_wdt->base))
+		return PTR_ERR(mpfs_wdt->base);
+
+	mpfs_wdt->clk = devm_clk_get_enabled(dev, NULL);
+	if (IS_ERR(mpfs_wdt->clk))
+		return dev_err_probe(dev, PTR_ERR(mpfs_wdt->clk), "Failed to get clock\n");
+
+	mpfs_wdt->rate_hz = clk_get_rate(mpfs_wdt->clk) / MPFS_WDT_CLK_PRESCALER;
+	if (!mpfs_wdt->rate_hz)
+		return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n");
+
+	mpfs_wdt->mvrp_irq = platform_get_irq_byname(pdev, "mvrp");
+	if (mpfs_wdt->mvrp_irq < 0)
+		return dev_err_probe(dev, mpfs_wdt->mvrp_irq, "Failed to get IRQ for mvrp\n");
+
+	ret = devm_request_irq(dev, mpfs_wdt->mvrp_irq, mpfs_wdt_mvrp_isr, 0,
+			       "mpfs-wdt", mpfs_wdt);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request IRQ for trig\n");
+
+	mpfs_wdt->trig_irq = platform_get_irq_byname(pdev, "trig");
+	if (mpfs_wdt->trig_irq < 0)
+		return dev_err_probe(dev, mpfs_wdt->trig_irq, "Failed to get IRQ for trig\n");
+
+	ret = devm_request_irq(dev, mpfs_wdt->trig_irq, mpfs_wdt_trig_isr, 0,
+			       "mpfs-wdt", mpfs_wdt);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request IRQ for timeout\n");
+
+	mpfs_wdt->wdd.parent = dev;
+	mpfs_wdt->wdd.info = &mpfs_wdt_info;
+	mpfs_wdt->wdd.ops = &mpfs_wdt_ops;
+	mpfs_wdt->wdd.min_timeout = MPFS_WDT_LOAD_MIN / mpfs_wdt->rate_hz;
+	mpfs_wdt->wdd.max_timeout = MPFS_WDT_LOAD_MAX / mpfs_wdt->rate_hz;
+	mpfs_wdt->wdd.timeout = MPFS_WDT_LOAD_MAX / mpfs_wdt->rate_hz;
+	mpfs_wdt->wdd.pretimeout = MPFS_WDT_LOAD_MAX / (mpfs_wdt->rate_hz * 2);
+
+	watchdog_set_drvdata(&mpfs_wdt->wdd, mpfs_wdt);
+	watchdog_set_nowayout(&mpfs_wdt->wdd, true);
+	watchdog_init_timeout(&mpfs_wdt->wdd, mpfs_wdt->wdd.timeout, dev);
+	mpfs_wdt_set_pretimeout(&mpfs_wdt->wdd, mpfs_wdt->wdd.pretimeout);
+	mpfs_wdt_set_timeout(&mpfs_wdt->wdd, mpfs_wdt->wdd.timeout);
+
+	ret = devm_watchdog_register_device(dev, &mpfs_wdt->wdd);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to register watchdog device.\n");
+
+	platform_set_drvdata(pdev, mpfs_wdt);
+	dev_info(dev, "timeout %d sec (nowayout=true)\n",
+		mpfs_wdt->wdd.timeout);
+
+	return 0;
+}
+
+static const struct of_device_id mpfs_wdt_match[] = {
+	{ .compatible = "microchip,mpfs-wdt" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mpfs_wdt_match);
+
+static struct platform_driver mpfs_wdt_driver = {
+	.probe	= mpfs_wdt_probe,
+	.driver	= {
+		.name = "mpfs_wdt",
+		.of_match_table	= mpfs_wdt_match,
+	},
+};
+
+module_platform_driver(mpfs_wdt_driver);
+
+MODULE_DESCRIPTION("Microchip PolarFire SoC watchdog driver");
+MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com");
+MODULE_LICENSE("GPL v2");
