Thanks to visit codestin.com
Credit goes to github.com

Skip to content

Commit 149d795

Browse files
paulwalker-armpaulwalker-arm
authored
[LLVM][InstCombine] Enable constant folding for SVE sdiv & udiv intrinsics. (#137966)
1 parent 0fab741 commit 149d795

File tree

4 files changed

+20
-12
lines changed

4 files changed

+20
-12
lines changed

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

+12
Original file line numberDiff line numberDiff line change
@@ -1309,6 +1309,9 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
13091309
.setMatchingIROpcode(Instruction::Mul);
13101310
case Intrinsic::aarch64_sve_sabd:
13111311
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sabd_u);
1312+
case Intrinsic::aarch64_sve_sdiv:
1313+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sdiv_u)
1314+
.setMatchingIROpcode(Instruction::SDiv);
13121315
case Intrinsic::aarch64_sve_smax:
13131316
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_smax_u);
13141317
case Intrinsic::aarch64_sve_smin:
@@ -1320,6 +1323,9 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
13201323
.setMatchingIROpcode(Instruction::Sub);
13211324
case Intrinsic::aarch64_sve_uabd:
13221325
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uabd_u);
1326+
case Intrinsic::aarch64_sve_udiv:
1327+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_udiv_u)
1328+
.setMatchingIROpcode(Instruction::UDiv);
13231329
case Intrinsic::aarch64_sve_umax:
13241330
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_umax_u);
13251331
case Intrinsic::aarch64_sve_umin:
@@ -1387,9 +1393,15 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
13871393
case Intrinsic::aarch64_sve_orr_u:
13881394
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
13891395
Instruction::Or);
1396+
case Intrinsic::aarch64_sve_sdiv_u:
1397+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1398+
Instruction::SDiv);
13901399
case Intrinsic::aarch64_sve_sub_u:
13911400
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
13921401
Instruction::Sub);
1402+
case Intrinsic::aarch64_sve_udiv_u:
1403+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1404+
Instruction::UDiv);
13931405

13941406
case Intrinsic::aarch64_sve_addqv:
13951407
case Intrinsic::aarch64_sve_and_z:

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll

+2-4
Original file line numberDiff line numberDiff line change
@@ -709,8 +709,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vs
709709
define <vscale x 4 x i32> @simplify_sdiv_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
710710
; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sdiv_intrinsic
711711
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {
712-
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
713-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
712+
; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]
714713
;
715714
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
716715
ret <vscale x 4 x i32> %r
@@ -989,8 +988,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vs
989988
define <vscale x 4 x i32> @simplify_udiv_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
990989
; CHECK-LABEL: define <vscale x 4 x i32> @simplify_udiv_intrinsic
991990
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {
992-
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
993-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
991+
; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]
994992
;
995993
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
996994
ret <vscale x 4 x i32> %r

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll

+4-6
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ define <vscale x 4 x i32> @constant_orr_u(<vscale x 4 x i1> %pg) #0 {
312312
define <vscale x 4 x i32> @constant_sdiv(<vscale x 4 x i1> %pg) #0 {
313313
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv(
314314
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
315-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 3))
315+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2), <vscale x 4 x i32> splat (i32 -7)
316316
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
317317
;
318318
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 3))
@@ -344,8 +344,7 @@ define <vscale x 4 x i32> @constant_sdiv_with_overflow(<vscale x 4 x i1> %pg) #0
344344
define <vscale x 4 x i32> @constant_sdiv_u(<vscale x 4 x i1> %pg) #0 {
345345
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u(
346346
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
347-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 -3))
348-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
347+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 2)
349348
;
350349
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 -3))
351350
ret <vscale x 4 x i32> %r
@@ -437,7 +436,7 @@ define <vscale x 4 x i32> @constant_subr(<vscale x 4 x i1> %pg) #0 {
437436
define <vscale x 4 x i32> @constant_udiv(<vscale x 4 x i1> %pg) #0 {
438437
; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv(
439438
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
440-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
439+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> splat (i32 7)
441440
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
442441
;
443442
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
@@ -458,8 +457,7 @@ define <vscale x 4 x i32> @constant_udiv_by_zero(<vscale x 4 x i1> %pg) #0 {
458457
define <vscale x 4 x i32> @constant_udiv_u(<vscale x 4 x i1> %pg) #0 {
459458
; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_u(
460459
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
461-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 3))
462-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
460+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 3)
463461
;
464462
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 3))
465463
ret <vscale x 4 x i32> %r

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-to-u-form.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -317,7 +317,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vs
317317
define <vscale x 4 x i32> @replace_sdiv_intrinsic_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
318318
; CHECK-LABEL: define <vscale x 4 x i32> @replace_sdiv_intrinsic_i32
319319
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {
320-
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
320+
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
321321
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
322322
;
323323
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
@@ -394,7 +394,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vs
394394
define <vscale x 4 x i32> @replace_udiv_intrinsic_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
395395
; CHECK-LABEL: define <vscale x 4 x i32> @replace_udiv_intrinsic_i32
396396
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {
397-
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
397+
; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])
398398
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
399399
;
400400
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)

0 commit comments

Comments
 (0)