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[RISCV] Enable more builtin for zvfhmin without zvfh
This patch enables some fp16 vector type builtins that don't use fp arithmetic instruction for zvfhmin without zvfh. Include following builtins: vector load/store, vector reinterpret, vmerge_vvm, vmv_v. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D151869
1 parent edb211c commit 4d2536c

2 files changed

Lines changed: 247 additions & 16 deletions

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‎clang/include/clang/Basic/riscv_vector.td‎

Lines changed: 57 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -577,7 +577,9 @@ multiclass RVVIndexedLoad<string op> {
577577
foreach eew_list = EEWList[0-2] in {
578578
defvar eew = eew_list[0];
579579
defvar eew_type = eew_list[1];
580-
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask" in {
580+
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
581+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
582+
[]<string>) in {
581583
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
582584
if !not(IsFloat<type>.val) then {
583585
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
@@ -587,7 +589,8 @@ multiclass RVVIndexedLoad<string op> {
587589
defvar eew64 = "64";
588590
defvar eew64_type = "(Log2EEW:6)";
589591
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
590-
RequiredFeatures = ["RV64"] in {
592+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
593+
["RV64"]) in {
591594
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
592595
if !not(IsFloat<type>.val) then {
593596
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -682,7 +685,9 @@ multiclass RVVIndexedStore<string op> {
682685
foreach eew_list = EEWList[0-2] in {
683686
defvar eew = eew_list[0];
684687
defvar eew_type = eew_list[1];
685-
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask" in {
688+
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
689+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
690+
[]<string>) in {
686691
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
687692
if !not(IsFloat<type>.val) then {
688693
def : RVVBuiltin<"Uv", "0PUe" # eew_type # "UvUv", type>;
@@ -692,7 +697,8 @@ multiclass RVVIndexedStore<string op> {
692697
defvar eew64 = "64";
693698
defvar eew64_type = "(Log2EEW:6)";
694699
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
695-
RequiredFeatures = ["RV64"] in {
700+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
701+
["RV64"]) in {
696702
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
697703
if !not(IsFloat<type>.val) then {
698704
def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
@@ -1112,24 +1118,32 @@ let HasBuiltinAlias = false,
11121118
// 7.4. Vector Unit-Stride Instructions
11131119
def vlm: RVVVLEMaskBuiltin;
11141120
defm vle8: RVVVLEBuiltin<["c"]>;
1115-
defm vle16: RVVVLEBuiltin<["s","x"]>;
1121+
defm vle16: RVVVLEBuiltin<["s"]>;
1122+
let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
1123+
defm vle16_h: RVVVLEBuiltin<["x"]>;
11161124
defm vle32: RVVVLEBuiltin<["i","f"]>;
11171125
defm vle64: RVVVLEBuiltin<["l","d"]>;
11181126

11191127
def vsm : RVVVSEMaskBuiltin;
11201128
defm vse8 : RVVVSEBuiltin<["c"]>;
1121-
defm vse16: RVVVSEBuiltin<["s","x"]>;
1129+
defm vse16: RVVVSEBuiltin<["s"]>;
1130+
let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
1131+
defm vse16_h: RVVVSEBuiltin<["x"]>;
11221132
defm vse32: RVVVSEBuiltin<["i","f"]>;
11231133
defm vse64: RVVVSEBuiltin<["l","d"]>;
11241134

11251135
// 7.5. Vector Strided Instructions
11261136
defm vlse8: RVVVLSEBuiltin<["c"]>;
1127-
defm vlse16: RVVVLSEBuiltin<["s","x"]>;
1137+
defm vlse16: RVVVLSEBuiltin<["s"]>;
1138+
let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
1139+
defm vlse16_h: RVVVLSEBuiltin<["x"]>;
11281140
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
11291141
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
11301142

11311143
defm vsse8 : RVVVSSEBuiltin<["c"]>;
1132-
defm vsse16: RVVVSSEBuiltin<["s","x"]>;
1144+
defm vsse16: RVVVSSEBuiltin<["s"]>;
1145+
let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
1146+
defm vsse16_h: RVVVSSEBuiltin<["x"]>;
11331147
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
11341148
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
11351149

@@ -1142,7 +1156,9 @@ defm : RVVIndexedStore<"vsoxei">;
11421156

11431157
// 7.7. Unit-stride Fault-Only-First Loads
11441158
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
1145-
defm vle16ff: RVVVLEFFBuiltin<["s","x"]>;
1159+
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
1160+
let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
1161+
defm vle16ff: RVVVLEFFBuiltin<["x"]>;
11461162
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
11471163
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
11481164

@@ -1160,6 +1176,8 @@ multiclass RVVUnitStridedSegLoadTuple<string op> {
11601176
IRName = op # nf,
11611177
MaskedIRName = op # nf # "_mask",
11621178
NF = nf,
1179+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1180+
[]<string>),
11631181
ManualCodegen = [{
11641182
{
11651183
llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0];
@@ -1220,6 +1238,8 @@ multiclass RVVUnitStridedSegStoreTuple<string op> {
12201238
MaskedIRName = op # nf # "_mask",
12211239
NF = nf,
12221240
HasMaskedOffOperand = false,
1241+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1242+
[]<string>),
12231243
ManualCodegen = [{
12241244
{
12251245
// Masked
@@ -1270,6 +1290,8 @@ multiclass RVVUnitStridedSegLoadFFTuple<string op> {
12701290
IRName = op # nf # "ff",
12711291
MaskedIRName = op # nf # "ff_mask",
12721292
NF = nf,
1293+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1294+
[]<string>),
12731295
ManualCodegen = [{
12741296
{
12751297
llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0];
@@ -1343,6 +1365,8 @@ multiclass RVVStridedSegLoadTuple<string op> {
13431365
IRName = op # nf,
13441366
MaskedIRName = op # nf # "_mask",
13451367
NF = nf,
1368+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1369+
[]<string>),
13461370
ManualCodegen = [{
13471371
{
13481372
llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0];
@@ -1405,6 +1429,8 @@ multiclass RVVStridedSegStoreTuple<string op> {
14051429
NF = nf,
14061430
HasMaskedOffOperand = false,
14071431
MaskedPolicyScheme = NonePolicy,
1432+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1433+
[]<string>),
14081434
ManualCodegen = [{
14091435
{
14101436
// Masked
@@ -1452,6 +1478,8 @@ multiclass RVVIndexedSegLoadTuple<string op> {
14521478
IRName = op # nf,
14531479
MaskedIRName = op # nf # "_mask",
14541480
NF = nf,
1481+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1482+
[]<string>),
14551483
ManualCodegen = [{
14561484
{
14571485
llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0];
@@ -1513,6 +1541,8 @@ multiclass RVVIndexedSegStoreTuple<string op> {
15131541
NF = nf,
15141542
HasMaskedOffOperand = false,
15151543
MaskedPolicyScheme = NonePolicy,
1544+
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1545+
[]<string>),
15161546
ManualCodegen = [{
15171547
{
15181548
// Masked
@@ -1751,8 +1781,11 @@ let HasMasked = false,
17511781
OverloadedName = "vmv_v" in {
17521782
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil",
17531783
[["v", "Uv", "UvUv"]]>;
1754-
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd",
1784+
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd",
17551785
[["v", "v", "vv"]]>;
1786+
let RequiredFeatures = ["ZvfhminOrZvfh"] in
1787+
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
1788+
[["v", "v", "vv"]]>;
17561789
let SupportOverloading = false in
17571790
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
17581791
[["x", "v", "ve"],
@@ -2244,8 +2277,11 @@ let HasMasked = false,
22442277
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
22452278
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops.back()->getType()};
22462279
}] in {
2247-
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "xfd",
2280+
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd",
22482281
[["vvm", "v", "vvvm"]]>;
2282+
let RequiredFeatures = ["ZvfhminOrZvfh"] in
2283+
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
2284+
[["vvm", "v", "vvvm"]]>;
22492285
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
22502286
[["vfm", "v", "vvem"]]>;
22512287
}
@@ -2668,11 +2704,17 @@ let HasMasked = false, HasVL = false, IRName = "" in {
26682704
}] in {
26692705
// Reinterpret between different type under the same SEW and LMUL
26702706
def vreinterpret_i_u : RVVBuiltin<"Uvv", "vUv", "csil", "v">;
2671-
def vreinterpret_i_f : RVVBuiltin<"Fvv", "vFv", "sil", "v">;
2707+
def vreinterpret_i_f : RVVBuiltin<"Fvv", "vFv", "il", "v">;
26722708
def vreinterpret_u_i : RVVBuiltin<"vUv", "Uvv", "csil", "Uv">;
2673-
def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "sil", "Uv">;
2674-
def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "sil", "Fv">;
2675-
def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "sil", "Fv">;
2709+
def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "il", "Uv">;
2710+
def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "il", "Fv">;
2711+
def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "il", "Fv">;
2712+
let RequiredFeatures = ["ZvfhminOrZvfh"] in {
2713+
def vreinterpret_i_h : RVVBuiltin<"Fvv", "vFv", "s", "v">;
2714+
def vreinterpret_u_h : RVVBuiltin<"FvUv", "UvFv", "s", "Uv">;
2715+
def vreinterpret_h_i : RVVBuiltin<"vFv", "Fvv", "s", "Fv">;
2716+
def vreinterpret_h_u : RVVBuiltin<"UvFv", "FvUv", "s", "Fv">;
2717+
}
26762718

26772719
// Reinterpret between different SEW under the same LMUL
26782720
foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)",

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