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[SelectionDAG] Don't convert sextload to zextload through a multi-use freeze (#196700)
Resolves #196590. The patch #189317 to teach DAGCombiner to look through freeze incorrectly introduce a miscompile of sext -> zext. This resolves resolves the miscompile.
1 parent 6004c17 commit c2f7e98

2 files changed

Lines changed: 32 additions & 1 deletion

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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16545,7 +16545,9 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
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// the freeze can depend on the full load value. But its still safe to change
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// the extension type from anyext to zext.
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if (FreezeNode && !FreezeNode.hasOneUse() &&
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(LN0->getMemoryVT().bitsGT(ExtVT) || ExtType != ISD::ZEXTLOAD))
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(LN0->getMemoryVT().bitsGT(ExtVT) || ExtType != ISD::ZEXTLOAD ||
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(LN0->getExtensionType() != ISD::EXTLOAD &&
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LN0->getExtensionType() != ISD::ZEXTLOAD)))
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return SDValue();
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auto AdjustBigEndianShift = [&](unsigned ShAmt) {

llvm/test/CodeGen/X86/reduce-load-width-freeze.ll

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -354,3 +354,32 @@ define i16 @srl_freeze_load_i64_to_i16(ptr %p) {
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%trunc = trunc i64 %srl to i16
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ret i16 %trunc
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}
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@g6 = global i8 0
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@g1 = global i16 0
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; no incorrect sext -> zext
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define i1 @issue196590() {
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; CHECK-LABEL: issue196590:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq g6@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movsbl (%rax), %eax
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; CHECK-NEXT: movzbl %al, %ecx
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; CHECK-NEXT: movq g1@GOTPCREL(%rip), %rdx
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; CHECK-NEXT: movw %cx, (%rdx)
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; CHECK-NEXT: leal (%rax,%rax), %ecx
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; CHECK-NEXT: cmpl %eax, %ecx
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; CHECK-NEXT: setg %al
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; CHECK-NEXT: retq
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%a = load i8, ptr @g6
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%zx = zext i8 %a to i16
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store i16 %zx, ptr @g1
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%sx = sext i8 %a to i32
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%b = load i8, ptr @g6
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%fr = freeze i8 %b
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%fr16 = sext i8 %fr to i16
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%add = add i16 %fr16, %fr16
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%selsx = sext i16 %add to i32
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%cmp = icmp sgt i32 %selsx, %sx
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ret i1 %cmp
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}

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