Thanks to visit codestin.com
Credit goes to github.com

Skip to content

Commit cdc9a4b

Browse files
kazutakahiratakazutakahirata
authored
[CodeGen] Use range-based for loops (NFC) (#138488)
This is a reland of #138434 except that: - the bits for llvm/lib/CodeGen/RenameIndependentSubregs.cpp have been dropped because they caused a test failure under asan, and - the bits for llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp have been improved with structured bindings.
1 parent f81193d commit cdc9a4b

File tree

6 files changed

+18
-25
lines changed

6 files changed

+18
-25
lines changed

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1114,8 +1114,8 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
11141114
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
11151115
else {
11161116
// Ensure that the type will fit the mask value.
1117-
for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) {
1118-
if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) {
1117+
for (const SwitchCG::BitTestCase &Case : B.Cases) {
1118+
if (!isUIntN(SwitchOpTy.getSizeInBits(), Case.Mask)) {
11191119
// Switch table case range are encoded into series of masks.
11201120
// Just use pointer type, it's guaranteed to fit.
11211121
MaskTy = LLT::scalar(PtrTy.getSizeInBits());

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+4-6
Original file line numberDiff line numberDiff line change
@@ -5498,9 +5498,8 @@ LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,
54985498

54995499
// Build new smaller bitcast instructions
55005500
// Not supporting Leftover types for now but will have to
5501-
for (unsigned i = 0; i < SrcVRegs.size(); i++)
5502-
BitcastVRegs.push_back(
5503-
MIRBuilder.buildBitcast(NarrowTy, SrcVRegs[i]).getReg(0));
5501+
for (Register Reg : SrcVRegs)
5502+
BitcastVRegs.push_back(MIRBuilder.buildBitcast(NarrowTy, Reg).getReg(0));
55045503

55055504
MIRBuilder.buildMergeLikeInstr(DstReg, BitcastVRegs);
55065505
MI.eraseFromParent();
@@ -7379,9 +7378,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
73797378
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits() * 2);
73807379
else
73817380
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits());
7382-
for (unsigned I = 0; I < SplitSrcs.size(); ++I) {
7383-
SplitSrcs[I] = MIRBuilder.buildTrunc(InterTy, SplitSrcs[I]).getReg(0);
7384-
}
7381+
for (Register &Src : SplitSrcs)
7382+
Src = MIRBuilder.buildTrunc(InterTy, Src).getReg(0);
73857383

73867384
// Combine the new truncates into one vector
73877385
auto Merge = MIRBuilder.buildMergeLikeInstr(

‎llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

+2-4
Original file line numberDiff line numberDiff line change
@@ -2588,8 +2588,7 @@ void InstrRefBasedLDV::placeMLocPHIs(
25882588
auto CollectPHIsForLoc = [&](LocIdx L) {
25892589
// Collect the set of defs.
25902590
SmallPtrSet<MachineBasicBlock *, 32> DefBlocks;
2591-
for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
2592-
MachineBasicBlock *MBB = OrderToBB[I];
2591+
for (MachineBasicBlock *MBB : OrderToBB) {
25932592
const auto &TransferFunc = MLocTransfer[MBB->getNumber()];
25942593
if (TransferFunc.contains(L))
25952594
DefBlocks.insert(MBB);
@@ -3800,8 +3799,7 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF,
38003799
// To mirror old LiveDebugValues, enumerate variables in RPOT order. Otherwise
38013800
// the order is unimportant, it just has to be stable.
38023801
unsigned VarAssignCount = 0;
3803-
for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
3804-
auto *MBB = OrderToBB[I];
3802+
for (MachineBasicBlock *MBB : OrderToBB) {
38053803
auto *VTracker = &vlocs[MBB->getNumber()];
38063804
// Collect each variable with a DBG_VALUE in this block.
38073805
for (auto &idx : VTracker->Vars) {

‎llvm/lib/CodeGen/MachineCSE.cpp

+4-6
Original file line numberDiff line numberDiff line change
@@ -325,9 +325,8 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
325325
}
326326

327327
// Finally, add all defs to PhysRefs as well.
328-
for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
329-
for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
330-
++AI)
328+
for (const auto &Def : PhysDefs)
329+
for (MCRegAliasIterator AI(Def.second, TRI, true); AI.isValid(); ++AI)
331330
PhysRefs.insert(*AI);
332331

333332
return !PhysRefs.empty();
@@ -348,9 +347,8 @@ bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
348347
if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
349348
return false;
350349

351-
for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
352-
if (MRI->isAllocatable(PhysDefs[i].second) ||
353-
MRI->isReserved(PhysDefs[i].second))
350+
for (const auto &PhysDef : PhysDefs) {
351+
if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second))
354352
// Avoid extending live range of physical registers if they are
355353
//allocatable or reserved.
356354
return false;

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

+4-5
Original file line numberDiff line numberDiff line change
@@ -354,8 +354,8 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
354354
DelDeps.push_back(std::make_pair(SuccSU, D));
355355
}
356356
}
357-
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
358-
RemovePred(DelDeps[i].first, DelDeps[i].second);
357+
for (const auto &[Del, Dep] : DelDeps)
358+
RemovePred(Del, Dep);
359359

360360
++NumDups;
361361
return NewSU;
@@ -389,9 +389,8 @@ void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
389389
DelDeps.push_back(std::make_pair(SuccSU, Succ));
390390
}
391391
}
392-
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
393-
RemovePred(DelDeps[i].first, DelDeps[i].second);
394-
}
392+
for (const auto &[Del, Dep] : DelDeps)
393+
RemovePred(Del, Dep);
395394
SDep FromDep(SU, SDep::Data, Reg);
396395
FromDep.setLatency(SU->Latency);
397396
AddPred(CopyFromSU, FromDep);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -3161,8 +3161,8 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
31613161
if (!TLI.isTypeLegal(VT)) {
31623162
UsePtrType = true;
31633163
} else {
3164-
for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
3165-
if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
3164+
for (const BitTestCase &Case : B.Cases)
3165+
if (!isUIntN(VT.getSizeInBits(), Case.Mask)) {
31663166
// Switch table case range are encoded into series of masks.
31673167
// Just use pointer type, it's guaranteed to fit.
31683168
UsePtrType = true;

0 commit comments

Comments
 (0)