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[SelectionDAG] Split <n x T> vector types for atomic load
`load atomic <n x T>` is not valid. This change splits vector types of atomic load in SelectionDAG so that it can translate vectors of >1 size with type bfloat,half. commit-id:3a045357
1 parent 23c9ff2 commit db674f8

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3 files changed

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3 files changed

+92
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lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -946,6 +946,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
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void SplitVecRes_FPOp_MultiType(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD, SDValue &Lo,

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1146,6 +1146,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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SplitVecRes_STEP_VECTOR(N, Lo, Hi);
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break;
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case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
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case ISD::ATOMIC_LOAD:
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SplitVecRes_ATOMIC_LOAD(cast<AtomicSDNode>(N), Lo, Hi);
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break;
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case ISD::LOAD:
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SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
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break;
@@ -2079,6 +2082,38 @@ void DAGTypeLegalizer::SplitVecRes_VP_SPLAT(SDNode *N, SDValue &Lo,
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Hi = DAG.getNode(N->getOpcode(), dl, HiVT, N->getOperand(0), MaskHi, EVLHi);
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}
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2085+
void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD, SDValue &Lo,
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SDValue &Hi) {
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EVT LoVT, HiVT;
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SDLoc dl(LD);
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std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
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SDValue Ch = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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EVT MemoryVT = LD->getMemoryVT();
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EVT LoMemVT, HiMemVT;
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std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
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Lo = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, LoMemVT, LoMemVT, Ch, Ptr,
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LD->getMemOperand());
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MachinePointerInfo MPI;
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IncrementPointer(LD, LoMemVT, MPI, Ptr);
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Hi = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, HiMemVT, HiMemVT, Ch, Ptr,
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LD->getMemOperand());
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// Build a factor node to remember that this load is independent of the
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// other one.
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Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Legalize the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDValue(LD, 1), Ch);
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}
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void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
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SDValue &Hi) {
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assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");

‎llvm/test/CodeGen/X86/atomic-load-store.ll‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,62 @@ define <2 x float> @atomic_vec2_float_align(ptr %x) {
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ret <2 x float> %ret
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}
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define <2 x half> @atomic_vec2_half(ptr %x) {
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; CHECK3-LABEL: atomic_vec2_half:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzwl (%rdi), %eax
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; CHECK3-NEXT: movzwl 2(%rdi), %ecx
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; CHECK3-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK3-NEXT: pinsrw $0, %ecx, %xmm1
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; CHECK3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; CHECK3-NEXT: retq
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;
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; CHECK0-LABEL: atomic_vec2_half:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movw (%rdi), %dx
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; CHECK0-NEXT: movw 2(%rdi), %cx
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; CHECK0-NEXT: ## implicit-def: $eax
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; CHECK0-NEXT: movw %dx, %ax
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; CHECK0-NEXT: ## implicit-def: $xmm0
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; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK0-NEXT: ## implicit-def: $eax
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; CHECK0-NEXT: movw %cx, %ax
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; CHECK0-NEXT: ## implicit-def: $xmm1
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; CHECK0-NEXT: pinsrw $0, %eax, %xmm1
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; CHECK0-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; CHECK0-NEXT: retq
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%ret = load atomic <2 x half>, ptr %x acquire, align 4
222+
ret <2 x half> %ret
223+
}
224+
225+
define <2 x bfloat> @atomic_vec2_bfloat(ptr %x) {
226+
; CHECK3-LABEL: atomic_vec2_bfloat:
227+
; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzwl (%rdi), %eax
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; CHECK3-NEXT: movzwl 2(%rdi), %ecx
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; CHECK3-NEXT: pinsrw $0, %ecx, %xmm1
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; CHECK3-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
233+
; CHECK3-NEXT: retq
234+
;
235+
; CHECK0-LABEL: atomic_vec2_bfloat:
236+
; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movw (%rdi), %cx
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; CHECK0-NEXT: movw 2(%rdi), %dx
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; CHECK0-NEXT: ## implicit-def: $eax
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; CHECK0-NEXT: movw %dx, %ax
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; CHECK0-NEXT: ## implicit-def: $xmm1
242+
; CHECK0-NEXT: pinsrw $0, %eax, %xmm1
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; CHECK0-NEXT: ## implicit-def: $eax
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; CHECK0-NEXT: movw %cx, %ax
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; CHECK0-NEXT: ## implicit-def: $xmm0
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; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK0-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
248+
; CHECK0-NEXT: retq
249+
%ret = load atomic <2 x bfloat>, ptr %x acquire, align 4
250+
ret <2 x bfloat> %ret
251+
}
252+
197253
define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
198254
; CHECK3-LABEL: atomic_vec1_ptr:
199255
; CHECK3: ## %bb.0:

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