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[VE][TableGen] Corrupted LaneBitmask representing regLiveUnits for few registerClasses #138552
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@llvm/issue-subscribers-bug Author: Vikash Gupta (vg0204) |
CC : @jayfoad @arsenm @Pierre-vh. Can you have a look at it! |
VE uses "ad hoc aliasing", i.e. using the See also #78942 and linked PRs. cc @kaz7 |
Yes, I am seeing it as zero. Also, Is it right to call it fake regUnit, rather than a regunit with 2 root registers Or is it the saying the same thing. Also, if the 2 registers are one in the same, how does it make sense to represent both upper 32bit and lower 32bit part of the sx registers from hardware's perspective, I am quite lost at that part in its visualization. |
Seen the PR, and I too tried your initial experimental patch that solved the issue, but as it's further mentioned it's required to model register usage for VE arch, you suggested a partial revert. Technically, it makes sense. Just I know this case is impossible to occur, but what if all regunits for any register in some other target is dead? This partial revert type patch will overlook that scenario saying all regunits are alive! |
Should the VE case be using RegisterTuples? Last I looked at this we have 2 incompatible ways of expressing subregisters |
VE really not using RegisterTuple, but it's registers such as SX0 are modelled out of subregs, in this scenario specifically those subregs (supposed to be disjoint) are aliases of each other. Can you put more light on suggested incompatible ways! |
It is probably saying the same thing. I am not too familiar with root registers.
I thought RegisterTuples was just some convenience stuff built on top of the core SubRegs machinery. |
See also this comment:
|
I agree with it, in that way its laneBitmask would be generated appropriately. Even your need for it, is identical to my ongoing PR ( mentioned here as well ) about converting MBB LiveIn tracking as regunits rather than registers. So can you look into this comment, telling is it right way to go with. CC : @arsenm |
In VE codegen, the laneBitmask generated corresponding to regUnits (for MCRegister) via MCRegUnitMaskIterator is always corrupted (value being 0x0 irrespective of regunits) for registerClasses dealing with scalar i32 & f32 dataTypes.
Its happening specifically for
SX#index
registers (64-bit) which are constituted from subregsSW#index
(32-bit) andSF#index
(32-bit) respectively with respective subregIndex denoting position assub_i32
andsub_i32
. Now, as in Target.td, the rules for subreg for any registers suggests that these subregs cannot be overlapping(or aliases) with each other. For example, in X86, EAX's Subregs list contains only [AX], not [AX, AH, AL].But, as its defined,
SF#index
is marked as an alias ofSW#index
, which makes them overlapping with each other OR technically the same register, and then also used as subregs forSX#index
vioalating the tableGen rule, which causing the generation of exactly single regunit(with 2 roots register) of formSW#index~SF#index
with consequently corrupted LaneBitmask value, instead of 2 regunits eventually reperesnting upper and lower halves ofSX#index
, with right laneBitmaskThis is acting as a blocker for #129847, where I observed significant downfall in VE's LIT test due to corrupted LaneBitmask, causing incorrect livein addition at ISEL-phase.
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