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[GlobalISel] Port known-bit and known-sign-bits for all operations #150515

@davemgreen

Description

@davemgreen

I was going through the SDAG version of computeKnownBits and computeSignBits to see what was missing from GISel. This is a list of all the nodes that SDAG tries to handle and their current status is GISel. Some nodes have no equivalent in GISel. Missing nodes will presumably need to be ported over, under the assumption that they will eventually be useful somewhere. Some of the examples like #141933 and #142355 make a good example of what kind of thing needs to be added and how tests can be written.

SDAG computeKnownBits Status
MERGE_VALUES Not relavant
SPLAT_VECTOR Done
SPLAT_VECTOR_PARTS Not relavant
STEP_VECTOR
BUILD_VECTOR Done
VECTOR_SHUFFLE Done
VSCALE
CONCAT_VECTORS Done
INSERT_SUBVECTOR
EXTRACT_SUBVECTOR
SCALAR_TO_VECTOR Not relavant
BITCAST
AND Done
OR Done
XOR Done
MUL Done
MULHU
MULHS
ABDU
ABDS
UMUL_LOHI Not relavant
SMUL_LOHI Not relavant
AVGFLOORU
AVGCEILU
AVGFLOORS
AVGCEILS
SELECT Done
VSELECT Not relavant
SELECT_CC Not relavant
SMULO
UMULO
SETCC Done
SETCCCARRY Not relavant
STRICT_FSETCC Not relavant
STRICT_FSETCCS Not relavant
SHL Done
SRL Done
SRA Done
FSHL
FSHR
SHL_PARTS Not relavant
SRA_PARTS Not relavant
SRL_PARTS Not relavant
SIGN_EXTEND_INREG Done
CTTZ
CTTZ_ZERO_UNDEF
CTLZ Done
CTLZ_ZERO_UNDEF Done
CTPOP Done
PARITY
MGATHER
MLOAD
LOAD Done
ZERO_EXTEND_VECTOR_INREG Not relavant
ZERO_EXTEND Done
SIGN_EXTEND_VECTOR_INREG Not relavant
SIGN_EXTEND Done
ANY_EXTEND_VECTOR_INREG Not relavant
ANY_EXTEND Done
TRUNCATE Done
AssertZext Done
AssertAlign Done
FGETSIGN
ADD Done
SUB Done
USUBO Done
SSUBO Done
USUBO_CARRY Done
SSUBO_CARRY Done
SUBC
UADDO Done
SADDO Done
UADDO_CARRY Done
SADDO_CARRY Done
ADDC
ADDE
UDIV
SDIV
SREM
UREM
EXTRACT_ELEMENT
EXTRACT_VECTOR_ELT
INSERT_VECTOR_ELT
BITREVERSE Done
BSWAP Done
ABS #154413
USUBSAT
UMIN Done
UMAX Done
SMIN Done
SMAX Done
UINT_TO_FP
SINT_TO_FP
FP_TO_UINT_SAT
ATOMIC_LOAD
ATOMIC_CMP_SWAP_WITH_SUCCESS
ATOMIC_CMP_SWAP
ATOMIC_SWAP
ATOMIC_LOAD_ADD
ATOMIC_LOAD_SUB
ATOMIC_LOAD_AND
ATOMIC_LOAD_CLR
ATOMIC_LOAD_OR
ATOMIC_LOAD_XOR
ATOMIC_LOAD_NAND
ATOMIC_LOAD_MIN
ATOMIC_LOAD_MAX
ATOMIC_LOAD_UMIN
ATOMIC_LOAD_UMAX
FrameIndex Done
TargetFrameIndex Not relavant
SDAG computeNumSignBits Status
ISD::AssertSext Done
ISD::AssertZext
ISD::MERGE_VALUES Not relavant
ISD::SPLAT_VECTOR Done
ISD::BUILD_VECTOR Done
ISD::VECTOR_SHUFFLE Done
ISD::BITCAST
ISD::FP_TO_SINT_SAT
ISD::SIGN_EXTEND Done
ISD::SIGN_EXTEND_INREG Done
ISD::SIGN_EXTEND_VECTOR_INREG Not relavant
ISD::SRA Done
ISD::SHL #152067
ISD::AND Done
ISD::OR Done
ISD::XOR Done
ISD::SELECT Done
ISD::VSELECT Done
ISD::SMIN Done
ISD::SMAX Done
ISD::UMIN Done
ISD::UMAX Done
ISD::SSUBO_CARRY Done
ISD::USUBO_CARRY Done
ISD::SADDO Done
ISD::UADDO Done
ISD::SADDO_CARRY Done
ISD::UADDO_CARRY Done
ISD::SSUBO Done
ISD::USUBO Done
ISD::SMULO Done
ISD::UMULO Done
ISD::SETCC Done
ISD::SETCCCARRY Not relavant
ISD::STRICT_FSETCC Not relavant
ISD::STRICT_FSETCCS Not relavant
ISD::ROTL
ISD::ROTR
ISD::ADD
ISD::ADDC
ISD::SUB
ISD::MUL
ISD::AVGCEILS
ISD::AVGFLOORS
ISD::SREM
ISD::TRUNCATE Done
ISD::EXTRACT_ELEMENT Not relavant
ISD::INSERT_VECTOR_ELT
ISD::EXTRACT_VECTOR_ELT
ISD::EXTRACT_SUBVECTOR
ISD::CONCAT_VECTORS Done
ISD::INSERT_SUBVECTOR
ISD::LOAD Done
ISD::ATOMIC_CMP_SWAP
ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
ISD::ATOMIC_SWAP
ISD::ATOMIC_LOAD_ADD
ISD::ATOMIC_LOAD_SUB
ISD::ATOMIC_LOAD_AND
ISD::ATOMIC_LOAD_CLR
ISD::ATOMIC_LOAD_OR
ISD::ATOMIC_LOAD_XOR
ISD::ATOMIC_LOAD_NAND
ISD::ATOMIC_LOAD_MIN
ISD::ATOMIC_LOAD_MAX
ISD::ATOMIC_LOAD_UMIN
ISD::ATOMIC_LOAD_UMAX
ISD::ATOMIC_LOAD

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