diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 80b74785473f7..a252f31ec37dd 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -187,9 +187,6 @@ template class CodeGenPassBuilder { } protected: - template - using has_required_t = decltype(std::declval().isRequired()); - template using is_module_pass_t = decltype(std::declval().run( std::declval(), std::declval())); @@ -216,14 +213,12 @@ template class CodeGenPassBuilder { } template - void operator()(PassT &&Pass, StringRef Name = PassT::name()) { + void operator()(PassT &&Pass, bool Force = false, + StringRef Name = PassT::name()) { static_assert((is_detected::value || is_detected::value) && "Only module pass and function pass are supported."); - bool Required = false; - if constexpr (is_detected::value) - Required = PassT::isRequired(); - if (!PB.runBeforeAdding(Name) && !Required) + if (!Force && !PB.runBeforeAdding(Name)) return; // Add Function Pass @@ -571,9 +566,12 @@ Error CodeGenPassBuilder::buildPipeline( { AddIRPass addIRPass(MPM, derived()); - addIRPass(RequireAnalysisPass()); - addIRPass(RequireAnalysisPass()); - addIRPass(RequireAnalysisPass()); + addIRPass(RequireAnalysisPass(), + /*Force=*/true); + addIRPass(RequireAnalysisPass(), + /*Force=*/true); + addIRPass(RequireAnalysisPass(), + /*Force=*/true); addISelPasses(addIRPass); } @@ -689,7 +687,7 @@ void CodeGenPassBuilder::addIRPasses( // Before running any passes, run the verifier to determine if the input // coming from the front-end and/or optimizer is valid. if (!Opt.DisableVerify) - addPass(VerifierPass()); + addPass(VerifierPass(), /*Force=*/true); // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { @@ -826,7 +824,7 @@ void CodeGenPassBuilder::addISelPrepare( // All passes which modify the LLVM IR are now complete; run the verifier // to ensure that the IR is valid. if (!Opt.DisableVerify) - addPass(VerifierPass()); + addPass(VerifierPass(), /*Force=*/true); } template diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 11f4240581b7b..d8a1fd66790bd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -89,6 +89,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -353,6 +354,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -469,6 +471,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index f3b9364fdb92b..db5a1c0ac71aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 1a5f415f906e6..90659adcd13d0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2113,7 +2113,8 @@ void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const { // FIXME: Why isn't this queried as required from AMDGPUISelDAGToDAG, and why // isn't this in addInstSelector? - addPass(RequireAnalysisPass()); + addPass(RequireAnalysisPass(), + /*Force=*/true); } void AMDGPUCodeGenPassBuilder::addILPOpts(AddMachinePass &addPass) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h index 4cd7dea83a061..4c4ac344cb206 100644 --- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h +++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h @@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h index b2c3190b5c6ba..4e97128bdc2d5 100644 --- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h +++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h @@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h index d7551a45887b9..12b87d756e664 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h @@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public PassInfoMixin { SIFixSGPRCopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h index 7b098b71597ff..0637b5d1750f9 100644 --- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h +++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h @@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h index 23803c679c246..478558dfbf97f 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h @@ -16,6 +16,7 @@ class SILowerControlFlowPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h index a9ffb5705d094..55c1e914d9a6a 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h @@ -23,6 +23,7 @@ class SILowerSGPRSpillsPass : public PassInfoMixin { .set(MachineFunctionProperties::Property::IsSSA) .set(MachineFunctionProperties::Property::NoVRegs); } + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h index cfc8100901760..5c17a479d953c 100644 --- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h +++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h @@ -16,6 +16,7 @@ class SILowerWWMCopiesPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h index 9964817649168..6eae4756d59b2 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h @@ -18,6 +18,7 @@ class SIPreAllocateWWMRegsPass public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h index e30b46721841b..b33c7d4a632bb 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h @@ -21,6 +21,7 @@ class SIWholeQuadModePass : public PassInfoMixin { return MachineFunctionProperties().set( MachineFunctionProperties::Property::IsSSA); } + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/test/tools/llc/new-pm/pipeline.mir b/llvm/test/tools/llc/new-pm/pipeline.mir index 761a3a424ee67..8f8e443923b7b 100644 --- a/llvm/test/tools/llc/new-pm/pipeline.mir +++ b/llvm/test/tools/llc/new-pm/pipeline.mir @@ -1,8 +1,10 @@ # RUN: llc -mtriple=x86_64-pc-linux-gnu -x mir -passes=no-op-machine-function --print-pipeline-passes -filetype=null < %s | FileCheck %s --match-full-lines # RUN: llc -mtriple=x86_64-pc-linux-gnu -x mir -passes='require,print' -print-pipeline-passes < %s | FileCheck --check-prefix=ANALYSIS %s +# RUN: llc -mtriple=x86_64-pc-linux-gnu -x mir -enable-new-pm -stop-before=greedy -O3 -filetype=null --print-pipeline-passes < %s | FileCheck %s --check-prefix=CHECK-REQ # CHECK: function(machine-function(no-op-machine-function)),PrintMIRPreparePass,function(machine-function(verify,print)) +# CHECK-REQ-NOT: greedy # ANALYSIS: require,print --- diff --git a/llvm/test/tools/llc/new-pm/start-stop.ll b/llvm/test/tools/llc/new-pm/start-stop.ll index 9c3b9f009178f..13d9663221115 100644 --- a/llvm/test/tools/llc/new-pm/start-stop.ll +++ b/llvm/test/tools/llc/new-pm/start-stop.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -filetype=null %s | FileCheck --match-full-lines %s --check-prefix=NULL ; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -o /dev/null %s | FileCheck --match-full-lines %s --check-prefix=OBJ -; NULL: require,require,require,function(verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,ee-instrument,verify) -; OBJ: require,require,require,function(verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,ee-instrument,verify),PrintMIRPreparePass,function(machine-function(print),invalidate) +; NULL: require,require,require,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify) +; OBJ: require,require,require,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify),PrintMIRPreparePass,function(machine-function(print),invalidate)