diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index a476b191abf62..56ab8f3e3830a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -8684,11 +8684,6 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node, SDValue MinMax = DAG.getSelectCC(DL, LHS, RHS, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT); - // If MinMax is NaN, let's quiet it. - if (!Flags.hasNoNaNs() && !DAG.isKnownNeverNaN(LHS) && - !DAG.isKnownNeverNaN(RHS)) { - MinMax = DAG.getNode(ISD::FCANONICALIZE, DL, VT, MinMax, Flags); - } // Fixup signed zero behavior. if (Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros() || diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll index d458bb2492f23..02ea2cc2a1919 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll @@ -1696,23 +1696,13 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 @@ -1722,22 +1712,14 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_sdwa v1, v2, v0, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1 +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-SDAG-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0: @@ -1753,22 +1735,13 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-SDAG-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v2 @@ -1779,21 +1752,13 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v1, v3 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX900-SDAG-NEXT: v_max_f32_e32 v1, v1, v1 -; GFX900-SDAG-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v3, v3, v1, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v1 +; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-SDAG-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0: @@ -1812,9 +1777,6 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX950-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -1838,9 +1800,6 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX950-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v1, v3 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX950-SDAG-NEXT: v_max_f32_e32 v1, v1, v1 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc @@ -1866,22 +1825,14 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo @@ -1891,21 +1842,13 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0: @@ -1921,61 +1864,38 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4 ; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX11-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0: @@ -1997,72 +1917,47 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v3, v3, v3 -; GFX12-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX12-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call bfloat @llvm.maximumnum.bf16(bfloat %a, bfloat %b) %max3 = call bfloat @llvm.maximumnum.bf16(bfloat %tmp0, bfloat %c) @@ -2134,24 +2029,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -2161,23 +2046,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 @@ -2188,23 +2064,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2214,23 +2081,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -2248,23 +2106,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v5, v6 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-SDAG-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-SDAG-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-SDAG-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -2274,22 +2123,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-SDAG-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-SDAG-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v4 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX900-SDAG-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 @@ -2300,22 +2141,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v5 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX900-SDAG-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2325,21 +2158,13 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-SDAG-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] @@ -2354,15 +2179,12 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cndmask_b32_sdwa v4, v0, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v4 -; GFX950-SDAG-NEXT: s_nop 0 +; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX950-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v5, v6 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-SDAG-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc @@ -2387,9 +2209,6 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX950-SDAG-NEXT: s_nop 0 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc @@ -2413,9 +2232,6 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v5 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc @@ -2439,12 +2255,8 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, v3, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-SDAG-NEXT: s_nop 0 +; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-SDAG-NEXT: s_nop 1 @@ -2479,41 +2291,25 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX10-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc_lo -; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v6, v7, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v6, v4, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo @@ -2530,37 +2326,21 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -2572,120 +2352,82 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6 ; GFX11-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 ; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX11-NEXT: v_bfe_u32 v8, v6, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v8, v8, v6, 0x7fff -; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_lshlrev_b32 v3, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v6, 0xffff0000, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1 ; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v5 +; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX11-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX11-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -2702,144 +2444,102 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> % ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1 +; GFX12-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX12-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v6, v6, v6 -; GFX12-NEXT: v_bfe_u32 v8, v6, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v8, v8, v6, 0x7fff -; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-NEXT: v_lshrrev_b32_e32 v8, 16, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v6 +; GFX12-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_lshlrev_b32 v3, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1 +; GFX12-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v6, 0xffff0000, v2 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3 -; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-NEXT: v_max_num_f32_e32 v4, v4, v4 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX12-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 +; GFX12-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-NEXT: v_add3_u32 v7, v7, v5, 0x7fff +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v5 ; GFX12-NEXT: s_wait_alu 0xfffd +; GFX12-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo +; GFX12-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 +; GFX12-NEXT: s_wait_alu 0xfffd +; GFX12-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX12-NEXT: v_lshrrev_b32_e32 v7, 16, v5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo -; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll index 8a140bdfa42a6..84784745e7661 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll @@ -1695,25 +1695,15 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 @@ -1723,22 +1713,14 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_sdwa v1, v2, v0, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1 +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-SDAG-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0: @@ -1753,24 +1735,15 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v4 +; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-SDAG-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-SDAG-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v2 @@ -1781,21 +1754,13 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v1, v3 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX900-SDAG-NEXT: v_max_f32_e32 v1, v1, v1 -; GFX900-SDAG-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v3, v3, v1, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v1 +; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-SDAG-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0: @@ -1804,7 +1769,7 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX950-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX950-SDAG-NEXT: s_nop 0 +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX950-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 @@ -1814,10 +1779,6 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX950-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 -; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -1841,9 +1802,6 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX950-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v1, v3 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX950-SDAG-NEXT: v_max_f32_e32 v1, v1, v1 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc @@ -1869,22 +1827,14 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo @@ -1894,21 +1844,13 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0: @@ -1924,61 +1866,38 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4 ; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX11-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0: @@ -2000,72 +1919,47 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b, ; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v3, v3, v3 -; GFX12-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v4, v4, v3, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX12-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call bfloat @llvm.minimumnum.bf16(bfloat %a, bfloat %b) %min3 = call bfloat @llvm.minimumnum.bf16(bfloat %tmp0, bfloat %c) @@ -2136,26 +2030,16 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v6 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -2165,23 +2049,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 @@ -2192,23 +2067,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v3, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2218,23 +2084,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v3, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -2251,25 +2108,16 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v5, v6 +; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-SDAG-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-SDAG-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-SDAG-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-SDAG-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -2279,22 +2127,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-SDAG-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-SDAG-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v4 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX900-SDAG-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 @@ -2305,22 +2145,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v5 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 -; GFX900-SDAG-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v3 +; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2330,21 +2162,13 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v4 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-SDAG-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-SDAG-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-SDAG-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-SDAG-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-SDAG-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] @@ -2359,16 +2183,12 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cndmask_b32_sdwa v4, v0, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v4 -; GFX950-SDAG-NEXT: s_nop 0 +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX950-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v5, v6 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-SDAG-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 -; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc @@ -2393,9 +2213,6 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX950-SDAG-NEXT: s_nop 0 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc @@ -2419,9 +2236,6 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v5 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc @@ -2445,9 +2259,6 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX950-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, v3, v4 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-SDAG-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-SDAG-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-SDAG-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -2485,41 +2296,25 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX10-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc_lo -; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v6, v7, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v6, v4, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo @@ -2536,37 +2331,21 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -2578,120 +2357,82 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6 ; GFX11-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 ; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX11-NEXT: v_bfe_u32 v8, v6, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v8, v8, v6, 0x7fff -; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_lshlrev_b32 v3, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v6, 0xffff0000, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1 ; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v5 +; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 ; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX11-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX11-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3 ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -2708,144 +2449,102 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> % ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1 +; GFX12-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX12-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v0 ; GFX12-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_max_num_f32_e32 v6, v6, v6 -; GFX12-NEXT: v_bfe_u32 v8, v6, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_add3_u32 v8, v8, v6, 0x7fff -; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-NEXT: v_lshrrev_b32_e32 v8, 16, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v6 +; GFX12-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc_lo -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_lshlrev_b32 v3, 16, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1 +; GFX12-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v6, 0xffff0000, v2 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-NEXT: s_wait_alu 0xfffd ; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3 -; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v1 -; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-NEXT: v_max_num_f32_e32 v4, v4, v4 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX12-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX12-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 +; GFX12-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-NEXT: v_add3_u32 v7, v7, v5, 0x7fff +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v2 +; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v5 ; GFX12-NEXT: s_wait_alu 0xfffd +; GFX12-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo +; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 +; GFX12-NEXT: s_wait_alu 0xfffd +; GFX12-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3 ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX12-NEXT: v_lshrrev_b32_e32 v7, 16, v5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo -; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX12-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo +; GFX12-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-NEXT: s_wait_alu 0xfffd -; GFX12-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call <2 x bfloat> @llvm.minimumnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll index 9009ec54f174d..415c4bd5384c3 100644 --- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll @@ -34,23 +34,13 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; GFX8-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_maximumnum_bf16: @@ -66,22 +56,13 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX900-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX900-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v3, v3, v2, s4 -; GFX900-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-LABEL: v_maximumnum_bf16: @@ -100,9 +81,6 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX950-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc @@ -128,21 +106,13 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_bf16: @@ -151,39 +121,31 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_bf16: @@ -202,26 +164,14 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_maximumnum_bf16: @@ -234,45 +184,37 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_bf16: @@ -298,29 +240,17 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y) ret bfloat %result @@ -533,24 +463,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -560,23 +480,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -594,23 +505,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -620,21 +522,13 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v2, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -649,15 +543,12 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc @@ -681,12 +572,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 @@ -721,37 +608,21 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v5, v5, v3, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v4, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v4, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -765,66 +636,52 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16: @@ -837,60 +694,39 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -908,71 +744,56 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16: @@ -990,69 +811,48 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -1403,24 +1203,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -1430,23 +1220,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -1456,22 +1237,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -1490,23 +1262,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -1516,22 +1279,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -1541,21 +1296,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v4, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -1570,15 +1317,12 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -1602,9 +1346,6 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -1628,12 +1369,8 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 @@ -1648,180 +1385,125 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX10-LABEL: v_maximumnum_v3bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v5, v5 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v0, vcc_lo -; GFX10-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_or_b32_e32 v11, 0x400000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX10-NEXT: v_bfe_u32 v10, v7, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v10, v10, v7, 0x7fff -; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v9, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v10 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16: @@ -1830,88 +1512,59 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_maximumnum_v3bf16: @@ -1922,104 +1575,77 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v9, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v10 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16: @@ -2032,98 +1658,67 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX12-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 @@ -2131,7 +1726,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) ret <3 x bfloat> %result @@ -2585,24 +2180,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -2614,23 +2199,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, s4, v8 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -2640,23 +2216,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2666,22 +2233,13 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v3 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -2702,23 +2260,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -2730,22 +2279,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v8, v8, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v7 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -2755,22 +2296,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2780,21 +2313,13 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v5, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v4, v1, s4 @@ -2815,11 +2340,8 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v0 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -2843,9 +2365,6 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc @@ -2869,9 +2388,6 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -2885,7 +2401,7 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v4, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v0 @@ -2895,12 +2411,8 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v4, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 @@ -2942,78 +2454,46 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX10-NEXT: v_bfe_u32 v14, v8, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v7, v4, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v12 -; GFX10-NEXT: v_add3_u32 v12, v14, v8, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v13, vcc_lo -; GFX10-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_bfe_u32 v15, v9, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX10-NEXT: v_add3_u32 v12, v12, v11, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_or_b32_e32 v16, 0x400000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_bfe_u32 v12, v6, 16, 1 -; GFX10-NEXT: v_add3_u32 v14, v15, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_add3_u32 v12, v12, v6, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 @@ -3032,225 +2512,155 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v10, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v9, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo @@ -3275,123 +2685,94 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v10, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v9, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v11, v11, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16: @@ -3401,126 +2782,80 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 @@ -3529,21 +2864,22 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) @@ -4133,24 +3469,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v8, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_mul_f32_e32 v8, 1.0, v8 -; GFX8-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v8 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9 -; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v8 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v8 +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v8 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 @@ -4162,23 +3488,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v9, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s4, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 ; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 @@ -4190,23 +3507,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s4, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc @@ -4216,23 +3524,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s4, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc @@ -4242,23 +3541,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v9, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v9, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9 -; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -4268,22 +3558,13 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v8 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v7 @@ -4307,23 +3588,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v8, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX900-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX900-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v9, v9, v8, s4 -; GFX900-NEXT: v_or_b32_e32 v10, 0x400000, v8 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v8 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v8 +; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v8 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 @@ -4335,22 +3607,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v9, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s4 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc -; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 ; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v3 ; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 @@ -4362,22 +3626,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc @@ -4387,22 +3643,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s4 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc @@ -4412,22 +3660,14 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v9, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v9, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v9, v9, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -4437,21 +3677,13 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v8, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v7, v1, s4 @@ -4475,11 +3707,8 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v8, v9 ; GFX950-NEXT: v_lshrrev_b32_e32 v9, 16, v1 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v8, v8, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc @@ -4504,9 +3733,6 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc @@ -4530,9 +3756,6 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc @@ -4556,9 +3779,6 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc @@ -4572,7 +3792,7 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v4 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v2, v6, v2, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v1 @@ -4582,9 +3802,6 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v9, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -4598,7 +3815,7 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v7, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v0 @@ -4608,16 +3825,11 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v7, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX950-NEXT: v_perm_b32 v2, v6, v2, s0 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 @@ -4636,156 +3848,108 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v1 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 ; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v3 ; GFX10-NEXT: v_cndmask_b32_sdwa v12, v2, v7, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v15, v14, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v6, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v14, v8, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v17 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v9, v6, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_bfe_u32 v16, v10, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v16, v16, v10, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8 -; GFX10-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v13 -; GFX10-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v14, v8, v11, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_bfe_u32 v18, v14, 16, 1 -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v14, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v8, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_add3_u32 v9, v18, v14, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v0 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v10 -; GFX10-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v3, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v11, v14, v13, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_bfe_u32 v17, v10, 16, 1 -; GFX10-NEXT: v_add3_u32 v13, v16, v12, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_add3_u32 v16, v17, v10, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v17, 0x400000, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v16, v17, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v15, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v10 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo ; GFX10-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -4793,165 +3957,126 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v1.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.h, v6.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v9.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v14, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s3 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v8.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v7.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14 -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v14, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v14, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v13, v18 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s4 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v16, v20, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v19, v22, s6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s2 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v7.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v3.h, v10.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v9.l, v8.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v6.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v13.l, v8.l, s3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v6.l, s0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v7.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v10.l, s5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v9.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v8 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v2.l, s0 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v7 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v14 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v14, v6, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v16, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v4.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v12 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v1.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v8, v12, v14, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s1 -; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v12, v15, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v10, v14, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v4.l, v1.l, s1 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v0.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v3.h, s2 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v6bf16: @@ -4960,176 +4085,116 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_and_b32 v8, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v7 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v10, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v11 :: v_dual_max_f32 v9, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v14, v11 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v16, v18, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v15, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v14 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v15, v8 :: v_dual_lshlrev_b32 v17, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v18, v6 :: v_dual_lshlrev_b32 v9, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v13, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v8, v10, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v16, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v5, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v8 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v3, v0 :: v_dual_lshlrev_b32 v10, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v16, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add3_u32 v16, v17, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v16, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v15, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v13, v0 :: v_dual_and_b32 v5, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v4, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v1, v7, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -5141,191 +4206,143 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v1.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.h, v6.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v9.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v14, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s3 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v8.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v7.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.h, v10.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v14, v14, v14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14 -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v14, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v14, v14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v13, v18 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s4 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v16, v20, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v19, v22, s6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v6.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v7.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v10.l, s5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v9.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s2 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v8 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v7.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v3.h, v10.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v2.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v9.l, v8.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v6.l, s2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v14 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v14, v6, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v16, v7, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v13.l, v8.l, s3 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v4.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v16 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v12 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v1.h, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v8, v12, v14, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v12, v15, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v7 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v12.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v10, v14, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v4.l, v1.l, s1 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v3.h, s2 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v6bf16: @@ -5338,211 +4355,147 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_and_b32 v8, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v7 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v10, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v11 :: v_dual_max_num_f32 v9, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v14, v11 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v16, v18, v12, 0x7fff -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v14 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v15, v8 :: v_dual_lshlrev_b32 v17, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v18, v6 :: v_dual_lshlrev_b32 v9, 16, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v13, v13, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v13 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v8, v10, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v16, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v5, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v8 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v3, v0 :: v_dual_lshlrev_b32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX12-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v16, v10, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v16, v17, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v16, v17, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v15, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v11 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v13, v0 :: v_dual_and_b32 v5, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v4, 0xffff0000, v10 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_perm_b32 v1, v7, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <6 x bfloat> @llvm.maximumnum.v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) @@ -5618,24 +4571,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s4, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v6 ; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 @@ -5647,23 +4590,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v10 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v11, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_mul_f32_e32 v11, 1.0, v11 -; GFX8-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s4, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 @@ -5675,23 +4609,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s4, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 @@ -5703,23 +4628,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; GFX8-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, s4, v14 -; GFX8-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc @@ -5729,23 +4645,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s4, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc @@ -5755,23 +4662,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v7 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s4, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v7 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc @@ -5781,23 +4679,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -5807,22 +4696,13 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v10 @@ -5848,23 +4728,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v6 ; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 @@ -5876,22 +4747,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v10 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v11, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX900-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX900-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v11, s4 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc -; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v5 ; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 @@ -5903,22 +4766,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s4 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 @@ -5930,22 +4785,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX900-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX900-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX900-NEXT: v_add3_u32 v14, v14, v13, s4 -; GFX900-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc -; GFX900-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc @@ -5955,22 +4802,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s4 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc @@ -5980,22 +4819,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v7 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc @@ -6005,22 +4836,14 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -6030,21 +4853,13 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v11, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v10, v1, s4 @@ -6071,11 +4886,9 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX950-NEXT: v_and_b32_e32 v14, 0xffff0000, v4 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX950-NEXT: s_nop 1 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 +; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX950-NEXT: s_nop 1 @@ -6098,9 +4911,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX950-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v11, v11, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc @@ -6125,9 +4935,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc @@ -6151,9 +4958,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v14 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX950-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v13, v13, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc @@ -6177,9 +4981,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc @@ -6193,7 +4994,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v6 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v3, v8, v3, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v2 @@ -6203,9 +5004,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v12, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc @@ -6219,7 +5017,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v2, v9, v2, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v1 @@ -6229,9 +5027,6 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -6245,7 +5040,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v4 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v10, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v0 @@ -6255,16 +5050,11 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v10, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX950-NEXT: v_perm_b32 v2, v9, v2, s0 -; GFX950-NEXT: v_perm_b32 v3, v8, v3, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 @@ -6280,213 +5070,149 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v3 ; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v6 +; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v8 +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v5 -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX10-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX10-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v22, v19, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_max_f32_e32 v15, v16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX10-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v15 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX10-NEXT: v_add3_u32 v19, v19, v15, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v20 -; GFX10-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 +; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v11, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_add3_u32 v13, v13, v17, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v11, v14, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v9, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v16, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v12, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v12, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v1 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_max_f32_e32 v11, v15, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; GFX10-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v6, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX10-NEXT: v_bfe_u32 v17, v14, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_add3_u32 v17, v17, v14, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v18, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX10-NEXT: v_max_f32_e32 v16, v16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_or_b32_e32 v20, 0x400000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX10-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX10-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX10-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -6494,458 +5220,321 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.h, v6.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v7.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v9.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v1.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v9.l, v8.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v15, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v5.h, v12.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v13, v18 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v14.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v11.l, v10.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v4.h, v13.l, s2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v16, v16 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v17, v18 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v10.l, v8.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v9.l, s3 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v15.l, v12.l, s2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, v19, v22, s2 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v20 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v16, v16, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v19.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v13.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v18, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.l, v13.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v19.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v11.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v15.l, v9.l, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v10.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.h, v11.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v13.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v15.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.h, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v12.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v15.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v12.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v14.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v8.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v9, v18, s2 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v17.h, v8.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v10.h, v13.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v13, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v15, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v9, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v2.l, s3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.h, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v6.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v16, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v13, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v12, v12, v12 :: v_dual_max_f32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v14, v16, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v0.h, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v14, v15, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v16, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v14 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v15 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v1.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v3.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v4.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v1.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v9 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v8 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v8bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v10 :: v_dual_lshlrev_b32 v11, 16, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_and_b32 v16, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v12 :: v_dual_and_b32 v15, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v22, v19 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v15, v16, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v15 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v17, v8 :: v_dual_and_b32 v15, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v17, 16, v17 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v17, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v14 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v18 :: v_dual_lshlrev_b32 v15, 16, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v11, v15, v15 :: v_dual_lshlrev_b32 v18, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v14, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v14, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v18 :: v_dual_lshlrev_b32 v16, 16, v16 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v16, v16, v16 :: v_dual_and_b32 v13, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v14 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -6958,260 +5547,200 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.h, v6.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v7.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v9.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v1.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v9.l, v8.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v12.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v15, v17 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v5.h, v12.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v13, v18 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v14.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v10.l, v8.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v11.l, v10.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v9.l, s3 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v4.h, v13.l, s2 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v16, v16 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v17, v18 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v15.l, v12.l, s2 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v17, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v19, v19, v22, s2 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v20 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v16, v16, v16 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v19.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v13.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v15.l, v9.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.h, v11.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v18, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX12-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.h, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v13.l, v8.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.l, v13.l, s2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v19.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v11.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v15.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.h, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v12.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v15.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v12.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v8.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v14 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v9, v18, s2 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v17.h, v8.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v10.h, v13.l, s3 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v13, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v9, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v16, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v14 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v13, v13, v13 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v0.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v15, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v14, v14, v13, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v12, v12, v12 :: v_dual_max_num_f32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v14, v16, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v2.l, s3 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v0.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v14, v15, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v16, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v6.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v14 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v3.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v1.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v4.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v1.h, s3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v9 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v8 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -7222,256 +5751,170 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v10 :: v_dual_lshlrev_b32 v11, 16, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v11, v11, v11 :: v_dual_and_b32 v16, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v12 :: v_dual_and_b32 v15, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v22, v19 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v15, v16, v16 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX12-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v21 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v15 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v17, v8 :: v_dual_and_b32 v15, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v20 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v17, 16, v17 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v17, v17, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v17, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v14 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v18 :: v_dual_lshlrev_b32 v15, 16, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v11, v15, v15 :: v_dual_lshlrev_b32 v18, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v14, v14, v14 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v14, 16, 1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v17, v14, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v18 :: v_dual_lshlrev_b32 v16, 16, v16 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v16, v16, v16 :: v_dual_and_b32 v13, 0xffff0000, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v13, v13, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v14 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo @@ -7480,25 +5923,26 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <8 x bfloat> @llvm.maximumnum.v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) @@ -7624,24 +6068,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v16 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v18, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX8-NEXT: v_mul_f32_e32 v18, 1.0, v18 -; GFX8-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v18 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v19, vcc, s4, v19 -; GFX8-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v6 @@ -7653,23 +6087,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v19, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_mul_f32_e32 v19, 1.0, v19 -; GFX8-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, s4, v20 -; GFX8-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v5 @@ -7681,23 +6106,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v18 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v20, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX8-NEXT: v_mul_f32_e32 v20, 1.0, v20 -; GFX8-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v20 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, s4, v21 -; GFX8-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v21, v18, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v12 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v4 @@ -7709,23 +6125,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v21, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX8-NEXT: v_mul_f32_e32 v21, 1.0, v21 -; GFX8-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, s4, v22 -; GFX8-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v22, v19, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v11 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v3 @@ -7737,23 +6144,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v20 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v22, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX8-NEXT: v_mul_f32_e32 v22, 1.0, v22 -; GFX8-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v22 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, s4, v23 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v23, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v10 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v2 @@ -7765,23 +6163,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v23, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX8-NEXT: v_mul_f32_e32 v23, 1.0, v23 -; GFX8-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s4, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v24, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v9 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v1 @@ -7793,23 +6182,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s4, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v25, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v8 ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v0 @@ -7821,23 +6201,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v23 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX8-NEXT: v_mul_f32_e32 v25, 1.0, v25 -; GFX8-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, s4, v26 -; GFX8-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc @@ -7847,23 +6218,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s4, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v15 ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc @@ -7873,23 +6235,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_mul_f32_e32 v15, 1.0, v15 -; GFX8-NEXT: v_bfe_u32 v24, v15, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v15 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s4, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v15 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v15 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v14 ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc @@ -7899,23 +6252,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v5 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v15, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_mul_f32_e32 v14, 1.0, v14 -; GFX8-NEXT: v_bfe_u32 v15, v14, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v15, vcc, v15, v14 -; GFX8-NEXT: v_add_u32_e32 v15, vcc, s4, v15 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v14 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v13 ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc @@ -7925,23 +6269,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v14, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; GFX8-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, s4, v14 -; GFX8-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc @@ -7951,23 +6286,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s4, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc @@ -7977,23 +6303,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_mul_f32_e32 v11, 1.0, v11 -; GFX8-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s4, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc @@ -8003,23 +6320,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v11, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s4, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc @@ -8029,22 +6337,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s4, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v23 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v22 @@ -8078,23 +6377,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v16 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v18, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX900-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX900-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v19, v19, v18, s4 -; GFX900-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc -; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX900-NEXT: v_lshrrev_b32_e32 v17, 16, v14 ; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v6 @@ -8106,22 +6396,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v19, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX900-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX900-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX900-NEXT: v_add3_u32 v20, v20, v19, s4 -; GFX900-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc -; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v5 @@ -8133,22 +6415,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v18 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v20, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX900-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX900-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX900-NEXT: v_add3_u32 v21, v21, v20, s4 -; GFX900-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v21, v18, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v12 ; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v4 @@ -8160,22 +6434,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v21, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX900-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX900-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX900-NEXT: v_add3_u32 v22, v22, v21, s4 -; GFX900-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v22, v19, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v11 ; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v3 @@ -8187,22 +6453,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v20 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v22, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX900-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX900-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX900-NEXT: v_add3_u32 v23, v23, v22, s4 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v23, v20, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v10 ; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v2 @@ -8214,22 +6472,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v23, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX900-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX900-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v23, s4 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v24, v21, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v9 ; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v1 @@ -8241,22 +6491,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s4 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v25, v22, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v8 ; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v0 @@ -8268,22 +6510,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v23 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX900-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX900-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX900-NEXT: v_add3_u32 v26, v26, v25, s4 -; GFX900-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX900-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX900-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc @@ -8293,22 +6527,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s4 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX900-NEXT: v_and_b32_e32 v15, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v15 ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc @@ -8318,22 +6544,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX900-NEXT: v_max_f32_e32 v15, v15, v15 -; GFX900-NEXT: v_bfe_u32 v24, v15, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v15, s4 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v15 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v15 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX900-NEXT: v_and_b32_e32 v14, 0xffff0000, v15 +; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v14 ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc @@ -8343,22 +6561,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v5 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v15, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX900-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX900-NEXT: v_bfe_u32 v15, v14, 16, 1 -; GFX900-NEXT: v_add3_u32 v15, v15, v14, s4 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v14 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v15, v24, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v15, 16, v14 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX900-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v13 ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc @@ -8368,22 +6578,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v14, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX900-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX900-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX900-NEXT: v_add3_u32 v14, v14, v13, s4 -; GFX900-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX900-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc @@ -8393,22 +6595,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s4 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc @@ -8418,22 +6612,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX900-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX900-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v11, s4 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc @@ -8443,22 +6629,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v11, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc @@ -8468,21 +6646,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s4 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v23, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v22, v1, s4 @@ -8513,9 +6683,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v19, 16, v6 ; GFX950-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX950-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v18, v18, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 ; GFX950-NEXT: v_and_b32_e32 v23, 0xffff0000, v11 ; GFX950-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 @@ -8527,7 +6694,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX950-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v18, 16, v14 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 @@ -8542,9 +6709,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v20, 16, v5 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v17, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX950-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v19, v19, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc @@ -8569,9 +6733,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v21, 16, v4 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v18, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX950-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v20, v20, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc @@ -8596,9 +6757,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v22, 16, v3 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v19, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX950-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v21, v21, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc @@ -8623,9 +6781,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v23, 16, v2 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v20, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX950-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v22, v22, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc @@ -8650,9 +6805,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v24, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v21, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX950-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v23, v23, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc @@ -8677,9 +6829,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v25, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v22, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc @@ -8703,9 +6852,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v26 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v23, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX950-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v25, v25, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc @@ -8729,9 +6875,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc @@ -8745,7 +6888,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v14 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v7, v16, v7, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v6 @@ -8755,9 +6898,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v24, v15 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX950-NEXT: v_max_f32_e32 v15, v15, v15 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v15, v15, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc @@ -8771,7 +6911,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v13 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v6, v17, v6, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v5 @@ -8781,9 +6921,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v15, v14 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX950-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v14, v14, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc @@ -8797,7 +6934,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v12 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v5, v18, v5, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v4 @@ -8807,9 +6944,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v14, v13 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX950-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v13, v13, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc @@ -8823,7 +6957,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v11 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v4, v19, v4, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v3 @@ -8833,9 +6967,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc @@ -8849,7 +6980,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v10 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v3, v20, v3, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v2 @@ -8859,9 +6990,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v12, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX950-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v11, v11, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc @@ -8875,7 +7003,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v9 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v2, v21, v2, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v1 @@ -8885,9 +7013,6 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v11, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc @@ -8901,7 +7026,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v8 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v22, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v0 @@ -8911,25 +7036,17 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v22, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX950-NEXT: v_perm_b32 v2, v21, v2, s0 -; GFX950-NEXT: v_perm_b32 v3, v20, v3, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX950-NEXT: v_perm_b32 v4, v19, v4, s0 -; GFX950-NEXT: v_perm_b32 v5, v18, v5, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX950-NEXT: v_perm_b32 v0, v23, v0, s0 -; GFX950-NEXT: v_perm_b32 v6, v17, v6, s0 -; GFX950-NEXT: v_perm_b32 v7, v16, v7, s0 ; GFX950-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximumnum_v16bf16: @@ -8943,881 +7060,634 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v14 ; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 +; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v17 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 ; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_max_f32_e32 v18, v18, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_bfe_u32 v23, v18, 16, 1 ; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v19 -; GFX10-NEXT: v_add3_u32 v23, v23, v18, 0x7fff +; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v18 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v22 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v18 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v24, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v27 -; GFX10-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v29, v28, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v24, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v21 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v28 -; GFX10-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v24, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v30, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX10-NEXT: v_max_f32_e32 v19, v21, v21 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v26 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v29 -; GFX10-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v27, 0x400000, v19 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_max_f32_e32 v22, v23, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX10-NEXT: v_bfe_u32 v28, v22, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v30 -; GFX10-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v23, v27, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v11 +; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v25, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v29 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v24, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX10-NEXT: v_max_f32_e32 v24, v25, v25 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 -; GFX10-NEXT: v_bfe_u32 v29, v24, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v33, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v20, v26, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v31 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX10-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_max_f32_e32 v26, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX10-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v29 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v26, v23, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v27, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 ; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 -; GFX10-NEXT: v_add3_u32 v22, v22, v26, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v21, v27, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v31, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v29, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v7, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v31 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v33, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX10-NEXT: v_max_f32_e32 v27, v7, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v21, v23, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 -; GFX10-NEXT: v_bfe_u32 v23, v27, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v28, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31 -; GFX10-NEXT: v_add3_u32 v23, v23, v27, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v15, v33, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v22, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v25, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v14 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v6, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v26, v21, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v5 -; GFX10-NEXT: v_add3_u32 v22, v22, v24, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v21, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v5, v13, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v7 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v31, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v14, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v26, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX10-NEXT: v_max_f32_e32 v23, v24, v24 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v33, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v13, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v15, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_bfe_u32 v21, v23, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_add3_u32 v21, v21, v23, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v6 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v28, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v12 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v26, v15, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v12, v4, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v22, v25, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_or_b32_e32 v30, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v25, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX10-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v5, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 -; GFX10-NEXT: v_add3_u32 v26, v26, v24, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v25, v27, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v27, v13, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v11, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v22, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v25, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_bfe_u32 v23, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_add3_u32 v23, v23, v21, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v24 +; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v24 -; GFX10-NEXT: v_or_b32_e32 v24, 0x400000, v21 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v10 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v23, v24, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v25 -; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v21 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v23 -; GFX10-NEXT: v_max_f32_e32 v24, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v8, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v11, v23, v23 -; GFX10-NEXT: v_add3_u32 v23, v26, v24, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX10-NEXT: v_bfe_u32 v29, v11, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v29, 0x400000, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX10-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_perm_b32 v6, v17, v14, 0x5040100 -; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_perm_b32 v5, v18, v13, 0x5040100 -; GFX10-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_perm_b32 v7, v16, v15, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_v16bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v20, v5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v18, v5 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v14 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.h, v15.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v15.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, s0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v21 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v7.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.h, v13.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v16.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v19.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v4.h, v12.h, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v18.h, v13.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v23, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v23, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v25, v26 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v26, v27, v28, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v22.l, v19.l, s2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v26.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v6.l, v5.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v25, v27, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.h, v21.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v7.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v20.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v26.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.h, v16.l, s0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX11-TRUE16-NEXT: v_add3_u32 v16, v27, v23, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v26 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v24.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v23, v16, v27, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v21.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v3.h, v11.h, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v23.h, v19.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v11.h, v16.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v23 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v28, v19, v19 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v2.h, v10.h, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v10.h, v19.l, s0 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v28 -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v7.l, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v22.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v24, v25 :: v_dual_lshlrev_b32 v27, 16, v27 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v28, v28 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v21.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v26, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v19.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v26, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v9.h, v23.l, s0 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l -; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v26, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v21.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v24.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.h, v5.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v26, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v25, v25, v27, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v25.h, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v21.l, v23.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v8.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v28, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v19.l, v7.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v19.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v24.h, v19.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v19, v26, v26 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v7.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v19, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v19 -; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v19, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v19, v19 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v15 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v22, v22, v30, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v29 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v22.h, v23.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v18.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v25.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v18.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.h, v21.l, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v24.h, v16.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v14 -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v17.l, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_add3_u32 v17, v27, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v22.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.l, v18.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v25 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v4.h, v12.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v11 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v22.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v3.h, v11.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v23.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v26, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v19.l, v22.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v11.h, v20.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v5.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v5.l, s0 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v13.l, vcc_lo +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v10.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v14.l, v16.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-TRUE16-NEXT: v_add3_u32 v20, v22, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v13.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, v20, v22, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v18.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v17.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v20.h, v18.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v21.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v20.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v13.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v15, v22, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v22 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v12.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v17, v17, v17 :: v_dual_lshlrev_b32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.h, v5.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v15.h, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v12.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v21, v23, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v12.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, v21, v22, s0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v21.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v19.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v9.h, v23.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.l, v21.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v22.l, v19.l, vcc_lo +; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v0.h, v8.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v5.l, v23.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v19.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v21.l, v23.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v15 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v20.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.l, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v7.l, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v19.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s0 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v13, v21, v21 :: v_dual_lshlrev_b32 v22, 16, v10 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v14.l, s1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v13, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v20, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, v23, v24, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v20.h, v4.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v19.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v17.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v16.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v5.l, vcc_lo ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v9.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v15 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.l, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v13.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v13.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v16.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v14.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v6.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v12.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.l, v4.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v10.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v12.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v15 -; GFX11-TRUE16-NEXT: v_add3_u32 v15, v23, v13, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v8.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, v17, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v15.h, v3.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v17, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v8.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v12.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, v12, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v13, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v13, v21, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v22, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v11.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v9.h, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v15.h, v1.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v20.h, v0.h, s3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.l, v1.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v10.l, v0.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v13.l, v2.h, s3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v18 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v14 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v16 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v19 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v16bf16: @@ -9827,449 +7697,304 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v15 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v13 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v19, v20 :: v_dual_lshlrev_b32 v18, 16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v18, v18, v18 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v18 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v25, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v27, 16, v22 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v27 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v29, v28 :: v_dual_and_b32 v18, 0xffff0000, v18 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v27, 16, v25 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v19 :: v_dual_lshlrev_b32 v28, 16, v24 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v28 -; GFX11-FAKE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v24, v25 :: v_dual_and_b32 v28, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v26 :: v_dual_lshlrev_b32 v21, 16, v27 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v30, v29 :: v_dual_and_b32 v27, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v18, v19 :: v_dual_lshlrev_b32 v28, 16, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v19, v21, v21 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v29, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v29 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v22, v23, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v22, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX11-FAKE16-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v30 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v29, v23, v27 :: v_dual_and_b32 v30, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v28 :: v_dual_lshlrev_b32 v25, 16, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v28 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v24 :: v_dual_max_f32 v24, v25, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v20, v26 :: v_dual_lshlrev_b32 v31, 16, v25 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v31 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v32, v31 :: v_dual_lshlrev_b32 v29, 16, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v26, v29, v29 :: v_dual_lshlrev_b32 v33, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v28 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v29 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v21, v27 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v31, v32 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v29, v30 :: v_dual_lshlrev_b32 v32, 16, v15 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v23 :: v_dual_and_b32 v22, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v31 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v28 :: v_dual_lshlrev_b32 v32, 16, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v15, v7 :: v_dual_lshlrev_b32 v31, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v25 :: v_dual_lshlrev_b32 v28, 16, v28 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v25, v28, v28 :: v_dual_lshlrev_b32 v32, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v27, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v27, v27, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v27, v30, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v14, v6 :: v_dual_lshlrev_b32 v28, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v25 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v28, v7 :: v_dual_lshlrev_b32 v30, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v29 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v13, v5 :: v_dual_lshlrev_b32 v29, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v27, v27 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v24, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v15, v15, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v26, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v28, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v27 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v12, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_lshlrev_b32 v29, 16, v3 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v14, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v24 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v14, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX11-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v27, v27, v14, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v26, v5 :: v_dual_lshlrev_b32 v28, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v11, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v27, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX11-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v26, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v2 :: v_dual_lshlrev_b32 v25, 16, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v13, v13, v13 :: v_dual_lshlrev_b32 v26, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_add3_u32 v14, v24, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v27, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v14, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v14 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v26, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v8, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v27, v3 :: v_dual_lshlrev_b32 v14, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_max_f32_e32 v11, v14, v14 -; GFX11-FAKE16-NEXT: v_add3_u32 v14, v26, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v26, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -10281,534 +8006,406 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6 -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v20, v5 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v18, v5 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v15 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v14 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.h, v15.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v15.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v18 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v21 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.h, v13.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v18.h, v13.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v16.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v6.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v19.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v20.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v4.h, v12.h, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v23, v23, v23 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v24, v24, v24 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v23, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v27, v27, v23, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v25, v26 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v26, v27, v28, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v22.l, v19.l, s2 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX12-TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v26.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v26 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v19.l, v7.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v19.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.l, v7.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v24, v25, v27, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.h, v21.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v23, v23, v23 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v7.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v26.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v4.h, v12.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.h, v16.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX12-TRUE16-NEXT: v_add3_u32 v16, v27, v23, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v26 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v19.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v24.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v23, v16, v27, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v21.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v3.h, v11.h, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.h, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v23.h, v19.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v11.h, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v23 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v28, v19, v19 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v22.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v2.h, v10.h, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v3.h, v11.h, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v23.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v26, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v19.l, v22.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v10.h, v19.l, s0 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v28 -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v7.l, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v22.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v24, v24, v25 :: v_dual_lshlrev_b32 v27, 16, v27 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v28, v28 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v11.h, v20.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v5.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v21.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v5.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v26, v21, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v19.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v26, 16, 1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v10.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v9.h, v23.l, s0 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l -; GFX12-TRUE16-NEXT: v_add3_u32 v25, v25, v26, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v21.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v21.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v24.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.h, v5.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v26, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v25, v25, v27, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v25.h, v16.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v21.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v21.l, v23.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v19.l, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v8.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v28, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v19.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v9.h, v23.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.l, v21.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v25 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v22.l, v19.l, vcc_lo +; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v24.h, v19.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v19, v26, v26 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v7.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v7.l, v6.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v19, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v18 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v19 -; GFX12-TRUE16-NEXT: v_add3_u32 v22, v22, v19, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v19, v19 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v15 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v0.h, v8.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v22, v22, v30, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v5.l, v23.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v15.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v29 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v19.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v22.h, v23.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v21.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v21.l, v23.l, s0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v15 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v20.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v18.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v25.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v18.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.h, v21.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v24.h, v16.l, s1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.l, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v7.l, v19.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v19.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v14 -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v21, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v23 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v17.l, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_add3_u32 v17, v27, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v22.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.l, v18.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v14.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v19.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v17.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v16.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v21, v21 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v13.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v21, 16, 1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v14.l, v16.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.l, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-TRUE16-NEXT: v_add3_u32 v20, v22, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v13.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v13.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v20, v20, v22, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v18.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v17.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v21, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v13.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v16.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v20.h, v18.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v15.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v13.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v16.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v15, v22, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v22 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v12.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v17, v17, v17 :: v_dual_lshlrev_b32 v22, 16, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v14.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v15.h, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v12.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v21, v23, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v12.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v6.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v17, v21, v22, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v13, v21, v21 :: v_dual_lshlrev_b32 v22, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX12-TRUE16-NEXT: v_add3_u32 v23, v23, v13, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v13 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v20, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v20, v23, v24, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v12.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.l, v4.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v20.h, v4.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v10.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v9.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v15 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v13, v13, v13 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v12.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v15 -; GFX12-TRUE16-NEXT: v_add3_u32 v15, v23, v13, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v9, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v8.l, v0.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, v17, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v15.h, v3.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v17, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v8.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v12.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, v12, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v13, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v3 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v13, v21, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v22, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v11.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v9.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v15.h, v1.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v20.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.l, v1.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v10.l, v0.h, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v13.l, v2.h, s3 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v14 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v18 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v14 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v16 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v19 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v16bf16: @@ -10822,557 +8419,399 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v15 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v13 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v22 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v19, v20 :: v_dual_lshlrev_b32 v18, 16, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v18, v18, v18 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX12-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v21, v21, v21 -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v18 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v25, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v27, 16, v22 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v27 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v25, v29, v28 :: v_dual_and_b32 v18, 0xffff0000, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v27, 16, v25 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v26 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v19 :: v_dual_lshlrev_b32 v28, 16, v24 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v28 -; GFX12-FAKE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v24, v25 :: v_dual_and_b32 v28, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v26 :: v_dual_lshlrev_b32 v21, 16, v27 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v30, v29 :: v_dual_and_b32 v27, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v18, v19 :: v_dual_lshlrev_b32 v28, 16, v26 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v19, v21, v21 :: v_dual_and_b32 v20, 0xffff0000, v20 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v29, 16, v21 -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v29 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v19 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v22, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v22, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX12-FAKE16-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v30 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v29, v23, v27 :: v_dual_and_b32 v30, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v28 :: v_dual_lshlrev_b32 v25, 16, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v24 :: v_dual_max_num_f32 v24, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v24 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 -; GFX12-FAKE16-NEXT: v_bfe_u32 v29, v24, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v20, v26 :: v_dual_lshlrev_b32 v31, 16, v25 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v31 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v32, v31 :: v_dual_lshlrev_b32 v29, 16, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v26, v29, v29 :: v_dual_lshlrev_b32 v33, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX12-FAKE16-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v26 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v29 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v21, v27 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v31, v32 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v31, v29, v30 :: v_dual_lshlrev_b32 v32, 16, v15 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v23 :: v_dual_and_b32 v22, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v31 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v28 :: v_dual_lshlrev_b32 v32, 16, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v26, v26, v26 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v28, v15, v7 :: v_dual_lshlrev_b32 v31, 16, v6 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v25 :: v_dual_lshlrev_b32 v28, 16, v28 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v26 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v25, v28, v28 :: v_dual_lshlrev_b32 v32, 16, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v27, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v25, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v27, v27, v25, 0x7fff +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v27, v30, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v14, v6 :: v_dual_lshlrev_b32 v28, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v25 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v13 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v28, v7 :: v_dual_lshlrev_b32 v30, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v29 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v13, v5 :: v_dual_lshlrev_b32 v29, 16, v12 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v27, v27 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_bfe_u32 v15, v24, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v15, v15, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v26, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v4 +; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v12 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v28, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v27 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v12, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_lshlrev_b32 v29, 16, v3 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v14, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v11 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v24 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v14, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v27, v27, v14, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v26, v5 :: v_dual_lshlrev_b32 v28, 16, v11 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v11, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v27, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v26, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v2 :: v_dual_lshlrev_b32 v25, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v13, v13, v13 :: v_dual_lshlrev_b32 v26, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v13, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_add3_u32 v14, v24, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v27, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v14, v24, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v14 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v26, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v8, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v24, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v27, v3 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v11, v14, v14 -; GFX12-FAKE16-NEXT: v_add3_u32 v14, v26, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v25, v25, v25 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX12-FAKE16-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v11 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v15 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <16 x bfloat> @llvm.maximumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) @@ -11650,94 +9089,76 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 +; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v29 +; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 ; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v31 -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v34 -; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v35, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v34, v31, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v35 -; GFX8-NEXT: v_mul_f32_e32 v35, 1.0, v35 -; GFX8-NEXT: v_bfe_u32 v36, v35, 16, 1 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v36, vcc, v36, v35 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, s4, v36 -; GFX8-NEXT: v_or_b32_e32 v39, 0x400000, v35 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v39, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v35 +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v31 +; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v34 +; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v35 +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v37, v39 +; GFX8-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc +; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v36, v48 +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31 -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v31, v36, v31, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX8-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 +; GFX8-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX8-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v31, v36, v31, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v29 -; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX8-NEXT: s_waitcnt vmcnt(4) -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v55 -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v55 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 +; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55 +; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v33, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX8-NEXT: v_mul_f32_e32 v33, 1.0, v33 -; GFX8-NEXT: v_bfe_u32 v35, v33, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v35, vcc, v35, v33 -; GFX8-NEXT: v_add_u32_e32 v35, vcc, s4, v35 -; GFX8-NEXT: v_or_b32_e32 v36, 0x400000, v33 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v33 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v35 +; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v33, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32 -; GFX8-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v29 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v38, v33, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v34, 16, v33 -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v34, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v35, v33, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; GFX8-NEXT: v_mul_f32_e32 v34, 1.0, v34 -; GFX8-NEXT: v_bfe_u32 v36, v34, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, v36, v34 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, s4, v36 -; GFX8-NEXT: v_or_b32_e32 v37, 0x400000, v34 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v37, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v34 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v33 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 -; GFX8-NEXT: v_and_b32_e32 v34, 0xffff0000, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v34 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX8-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 @@ -11749,27 +9170,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v36, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX8-NEXT: v_mul_f32_e32 v36, 1.0, v36 -; GFX8-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v37, vcc, v37, v36 -; GFX8-NEXT: v_add_u32_e32 v37, vcc, s4, v37 -; GFX8-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v36 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 ; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 +; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v36 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 ; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v27 ; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc @@ -11777,27 +9188,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v36 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v37, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX8-NEXT: v_mul_f32_e32 v37, 1.0, v37 -; GFX8-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v38, vcc, v38, v37 -; GFX8-NEXT: v_add_u32_e32 v38, vcc, s4, v38 -; GFX8-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v37 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36 ; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc -; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 +; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v37 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v36 ; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v26 ; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc @@ -11805,23 +9206,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v38, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX8-NEXT: v_mul_f32_e32 v38, 1.0, v38 -; GFX8-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v39, vcc, v39, v38 -; GFX8-NEXT: v_add_u32_e32 v39, vcc, s4, v39 -; GFX8-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v38 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc -; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v38 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 ; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v25 ; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 @@ -11833,27 +9225,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v39, v48 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX8-NEXT: v_mul_f32_e32 v39, 1.0, v39 -; GFX8-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v48, vcc, v48, v39 -; GFX8-NEXT: v_add_u32_e32 v48, vcc, s4, v48 -; GFX8-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v39 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v37 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc -; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 +; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v39 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v38 ; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v24 ; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc @@ -11861,27 +9243,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v48, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX8-NEXT: v_mul_f32_e32 v48, 1.0, v48 -; GFX8-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v49, vcc, v49, v48 -; GFX8-NEXT: v_add_u32_e32 v49, vcc, s4, v49 -; GFX8-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v48 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc -; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v48 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v23 ; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc @@ -11889,27 +9261,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v48 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v49, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX8-NEXT: v_mul_f32_e32 v49, 1.0, v49 -; GFX8-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v50, vcc, v50, v49 -; GFX8-NEXT: v_add_u32_e32 v50, vcc, s4, v50 -; GFX8-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v49 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v48 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc -; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v49 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 ; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v6 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc @@ -11917,27 +9279,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v49 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v50, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX8-NEXT: v_mul_f32_e32 v50, 1.0, v50 -; GFX8-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v51, vcc, v51, v50 -; GFX8-NEXT: v_add_u32_e32 v51, vcc, s4, v51 -; GFX8-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v50 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v48 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 +; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v50 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v21 ; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v5 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc @@ -11945,27 +9297,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v50 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v51, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX8-NEXT: v_mul_f32_e32 v51, 1.0, v51 -; GFX8-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v52, vcc, v52, v51 -; GFX8-NEXT: v_add_u32_e32 v52, vcc, s4, v52 -; GFX8-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v51 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 +; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v51 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 ; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v20 ; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v4 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc @@ -11973,27 +9315,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v52, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX8-NEXT: v_mul_f32_e32 v52, 1.0, v52 -; GFX8-NEXT: v_bfe_u32 v53, v52, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v53, vcc, v53, v52 -; GFX8-NEXT: v_add_u32_e32 v53, vcc, s4, v53 -; GFX8-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v52 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc -; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 +; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v52 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 ; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v19 ; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v3 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc @@ -12001,27 +9333,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v53, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX8-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; GFX8-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v54, vcc, v54, v53 -; GFX8-NEXT: v_add_u32_e32 v54, vcc, s4, v54 -; GFX8-NEXT: v_or_b32_e32 v40, 0x400000, v53 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v54, v40, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v53 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc -; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v53 +; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc @@ -12029,27 +9351,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v53 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v54, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX8-NEXT: v_mul_f32_e32 v54, 1.0, v54 -; GFX8-NEXT: v_bfe_u32 v40, v54, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, v40, v54 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, s4, v40 -; GFX8-NEXT: v_or_b32_e32 v41, 0x400000, v54 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v40, v41, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v54 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc -; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v54 +; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v54 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53 ; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc @@ -12057,27 +9369,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v54 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v40, v41 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX8-NEXT: v_mul_f32_e32 v40, 1.0, v40 -; GFX8-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, v41, v40 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, s4, v41 -; GFX8-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX8-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc -; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v40 +; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v40 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54 ; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc @@ -12085,23 +9387,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v42, 16, v40 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v41, v42 ; GFX8-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX8-NEXT: v_mul_f32_e32 v41, 1.0, v41 -; GFX8-NEXT: v_bfe_u32 v42, v41, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v42, vcc, v42, v41 -; GFX8-NEXT: v_add_u32_e32 v42, vcc, s4, v42 -; GFX8-NEXT: v_or_b32_e32 v43, 0x400000, v41 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 -; GFX8-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v42, 16, v41 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc -; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v41 +; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v41 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v40 ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc @@ -12111,23 +9404,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v41, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX8-NEXT: v_mul_f32_e32 v40, 1.0, v40 -; GFX8-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, v41, v40 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, s4, v41 -; GFX8-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX8-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc -; GFX8-NEXT: v_and_b32_e32 v55, 0xffff0000, v40 +; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v40 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v55 ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc @@ -12137,23 +9421,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v40, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX8-NEXT: v_mul_f32_e32 v55, 1.0, v55 -; GFX8-NEXT: v_bfe_u32 v40, v55, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, v40, v55 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, s4, v40 -; GFX8-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX8-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v55 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v55 +; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc @@ -12163,23 +9438,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v13 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v55, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX8-NEXT: v_mul_f32_e32 v30, 1.0, v30 -; GFX8-NEXT: v_bfe_u32 v55, v30, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v55, vcc, v55, v30 -; GFX8-NEXT: v_add_u32_e32 v55, vcc, s4, v55 -; GFX8-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX8-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v55, 16, v30 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v30 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v29 ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc @@ -12189,23 +9455,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v12 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v30, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX8-NEXT: v_mul_f32_e32 v29, 1.0, v29 -; GFX8-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v30, vcc, v30, v29 -; GFX8-NEXT: v_add_u32_e32 v30, vcc, s4, v30 -; GFX8-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX8-NEXT: v_cndmask_b32_e32 v29, v30, v55, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v28 ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc @@ -12215,23 +9472,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v29, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX8-NEXT: v_mul_f32_e32 v28, 1.0, v28 -; GFX8-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v29, vcc, v29, v28 -; GFX8-NEXT: v_add_u32_e32 v29, vcc, s4, v29 -; GFX8-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX8-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v27 ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc @@ -12241,23 +9489,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v10 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v28, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX8-NEXT: v_mul_f32_e32 v27, 1.0, v27 -; GFX8-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v28, vcc, v28, v27 -; GFX8-NEXT: v_add_u32_e32 v28, vcc, s4, v28 -; GFX8-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX8-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v27 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v27 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v26 ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc @@ -12267,23 +9506,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v9 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v27, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX8-NEXT: v_mul_f32_e32 v26, 1.0, v26 -; GFX8-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v27, vcc, v27, v26 -; GFX8-NEXT: v_add_u32_e32 v27, vcc, s4, v27 -; GFX8-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX8-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v26 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v25 ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc @@ -12293,23 +9523,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v26, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX8-NEXT: v_mul_f32_e32 v25, 1.0, v25 -; GFX8-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, s4, v26 -; GFX8-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc @@ -12319,23 +9540,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s4, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX8-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX8-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc @@ -12345,23 +9560,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX8-NEXT: v_mul_f32_e32 v23, 1.0, v23 -; GFX8-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s4, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc @@ -12371,23 +9577,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v5 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v23, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX8-NEXT: v_mul_f32_e32 v22, 1.0, v22 -; GFX8-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v22 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, s4, v23 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc @@ -12397,23 +9594,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v22, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX8-NEXT: v_mul_f32_e32 v21, 1.0, v21 -; GFX8-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, s4, v22 -; GFX8-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc @@ -12421,29 +9609,16 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX8-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v21, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX8-NEXT: v_mul_f32_e32 v20, 1.0, v20 -; GFX8-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v20 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, s4, v21 -; GFX8-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc @@ -12453,23 +9628,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v20, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_mul_f32_e32 v19, 1.0, v19 -; GFX8-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, s4, v20 -; GFX8-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc @@ -12479,23 +9645,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v19, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX8-NEXT: v_mul_f32_e32 v18, 1.0, v18 -; GFX8-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v18 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, s4, v19 -; GFX8-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc @@ -12505,22 +9662,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v18, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX8-NEXT: v_mul_f32_e32 v17, 1.0, v17 -; GFX8-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v17 -; GFX8-NEXT: v_add_u32_e32 v18, vcc, s4, v18 -; GFX8-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v17 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v54 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v53 @@ -12570,84 +9718,70 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 ; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc +; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 ; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v31 +; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc ; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v34 +; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v37, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX900-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_bfe_u32 v39, v37, 16, 1 -; GFX900-NEXT: v_or_b32_e32 v49, 0x400000, v37 -; GFX900-NEXT: v_add3_u32 v39, v39, v37, s4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v49, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v37 +; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v36, v48 +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31 -; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v31, v39, v31, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 +; GFX900-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX900-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 +; GFX900-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX900-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX900-NEXT: v_lshrrev_b32_e32 v33, 16, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v31, v39, v31, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 -; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX900-NEXT: s_waitcnt vmcnt(4) -; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v55 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 +; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 +; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 +; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 +; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX900-NEXT: s_mov_b32 s4, 0x5040100 +; GFX900-NEXT: s_waitcnt vmcnt(3) +; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc ; GFX900-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v34 +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v33, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX900-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX900-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX900-NEXT: v_or_b32_e32 v39, 0x400000, v33 -; GFX900-NEXT: v_add3_u32 v37, v37, v33, s4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v37, v39, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v33 +; GFX900-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32 -; GFX900-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v37, v32, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v37, v32, vcc -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v38, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v34, 16, v33 -; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v36, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v33, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; GFX900-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX900-NEXT: v_bfe_u32 v36, v34, 16, 1 -; GFX900-NEXT: v_add3_u32 v36, v36, v34, s4 -; GFX900-NEXT: v_or_b32_e32 v37, 0x400000, v34 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v37, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v34 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v33 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33 -; GFX900-NEXT: v_and_b32_e32 v34, 0xffff0000, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v35, v33, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v34 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX900-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX900-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 @@ -12659,26 +9793,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v36, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX900-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX900-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX900-NEXT: v_add3_u32 v37, v37, v36, s4 -; GFX900-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v36 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 ; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc -; GFX900-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 +; GFX900-NEXT: v_lshlrev_b32_e32 v35, 16, v36 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 ; GFX900-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v27 ; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc @@ -12686,26 +9811,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v36 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v37, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX900-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX900-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX900-NEXT: v_add3_u32 v38, v38, v37, s4 -; GFX900-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v37 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc -; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 +; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v37 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v36 ; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v26 ; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc @@ -12713,22 +9829,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v38, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX900-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX900-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX900-NEXT: v_add3_u32 v39, v39, v38, s4 -; GFX900-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v38 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc -; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v38 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v25 ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 @@ -12740,26 +9848,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v39, v48 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX900-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX900-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX900-NEXT: v_add3_u32 v48, v48, v39, s4 -; GFX900-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v39 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc -; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 +; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v39 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v38 ; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v24 ; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc @@ -12767,26 +9866,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v48, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX900-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX900-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX900-NEXT: v_add3_u32 v49, v49, v48, s4 -; GFX900-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v48 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc -; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 +; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v48 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v23 ; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc @@ -12794,26 +9884,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v48 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v49, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX900-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX900-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX900-NEXT: v_add3_u32 v50, v50, v49, s4 -; GFX900-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v49 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v48 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc -; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v49 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 ; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v6 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc @@ -12821,26 +9902,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v49 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v50, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX900-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX900-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX900-NEXT: v_add3_u32 v51, v51, v50, s4 -; GFX900-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v50 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v48 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 +; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v50 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v21 ; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v5 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc @@ -12848,26 +9920,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v50 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v51, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX900-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX900-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX900-NEXT: v_add3_u32 v52, v52, v51, s4 -; GFX900-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v51 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 +; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v51 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 ; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v20 ; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v4 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc @@ -12875,26 +9938,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v52, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX900-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX900-NEXT: v_bfe_u32 v53, v52, 16, 1 -; GFX900-NEXT: v_add3_u32 v53, v53, v52, s4 -; GFX900-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v52 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc -; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 +; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v52 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 ; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v19 ; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v3 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc @@ -12902,26 +9956,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v53, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX900-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX900-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX900-NEXT: v_add3_u32 v54, v54, v53, s4 -; GFX900-NEXT: v_or_b32_e32 v40, 0x400000, v53 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v54, v40, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v53 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc -; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v53 +; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v18 ; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc @@ -12929,26 +9974,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v53 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v54, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX900-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX900-NEXT: v_bfe_u32 v40, v54, 16, 1 -; GFX900-NEXT: v_add3_u32 v40, v40, v54, s4 -; GFX900-NEXT: v_or_b32_e32 v41, 0x400000, v54 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v40, v41, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v54 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc -; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v54 +; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v54 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53 ; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v17 ; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc @@ -12956,26 +9992,17 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v54 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v40, v41 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX900-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX900-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX900-NEXT: v_add3_u32 v41, v41, v40, s4 -; GFX900-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX900-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc -; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v40 +; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v40 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54 ; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v16 ; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc @@ -12983,22 +10010,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v42, 16, v40 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v41, v42 ; GFX900-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX900-NEXT: v_max_f32_e32 v41, v41, v41 -; GFX900-NEXT: v_bfe_u32 v42, v41, 16, 1 -; GFX900-NEXT: v_add3_u32 v42, v42, v41, s4 -; GFX900-NEXT: v_or_b32_e32 v43, 0x400000, v41 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 -; GFX900-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v42, 16, v41 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc -; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v41 +; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v41 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v40 ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc @@ -13008,22 +10027,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v41, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX900-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX900-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX900-NEXT: v_add3_u32 v41, v41, v40, s4 -; GFX900-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX900-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc -; GFX900-NEXT: v_and_b32_e32 v55, 0xffff0000, v40 +; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v40 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v55 ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc @@ -13033,22 +10044,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v40, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX900-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX900-NEXT: v_bfe_u32 v40, v55, 16, 1 -; GFX900-NEXT: v_add3_u32 v40, v40, v55, s4 -; GFX900-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX900-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v55 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX900-NEXT: v_and_b32_e32 v30, 0xffff0000, v55 +; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc @@ -13058,22 +10061,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v13 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v55, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX900-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX900-NEXT: v_bfe_u32 v55, v30, 16, 1 -; GFX900-NEXT: v_add3_u32 v55, v55, v30, s4 -; GFX900-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX900-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v55, 16, v30 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc -; GFX900-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v30 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v29 ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc @@ -13083,22 +10078,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v12 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v30, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX900-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX900-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX900-NEXT: v_add3_u32 v30, v30, v29, s4 -; GFX900-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX900-NEXT: v_cndmask_b32_e32 v29, v30, v55, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v30, 16, v29 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc -; GFX900-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 +; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v28 ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc @@ -13108,22 +10095,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v29, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX900-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX900-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX900-NEXT: v_add3_u32 v29, v29, v28, s4 -; GFX900-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX900-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc -; GFX900-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v27 ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc @@ -13133,22 +10112,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v10 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v28, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX900-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX900-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX900-NEXT: v_add3_u32 v28, v28, v27, s4 -; GFX900-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX900-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v28, 16, v27 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc -; GFX900-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 +; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v27 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v26 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc @@ -13158,47 +10129,34 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v9 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v27, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX900-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX900-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX900-NEXT: v_add3_u32 v27, v27, v26, s4 -; GFX900-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX900-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v27, 16, v26 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc -; GFX900-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 +; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v25 ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc +; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v26, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX900-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX900-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX900-NEXT: v_add3_u32 v26, v26, v25, s4 -; GFX900-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX900-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc -; GFX900-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc @@ -13208,22 +10166,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s4 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc -; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc @@ -13233,22 +10183,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX900-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX900-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v23, s4 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc -; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc @@ -13258,26 +10200,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v5 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v23, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX900-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX900-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX900-NEXT: v_add3_u32 v23, v23, v22, s4 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX900-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload -; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc -; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc @@ -13287,22 +10217,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v22, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX900-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX900-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX900-NEXT: v_add3_u32 v22, v22, v21, s4 -; GFX900-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc -; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc @@ -13312,22 +10234,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v3 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v21, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX900-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX900-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX900-NEXT: v_add3_u32 v21, v21, v20, s4 -; GFX900-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc -; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc @@ -13337,22 +10251,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v20, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX900-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX900-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX900-NEXT: v_add3_u32 v20, v20, v19, s4 -; GFX900-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc -; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc @@ -13362,22 +10268,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v19, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX900-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX900-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX900-NEXT: v_add3_u32 v19, v19, v18, s4 -; GFX900-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc -; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc @@ -13387,22 +10285,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v18, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX900-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX900-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX900-NEXT: v_add3_u32 v18, v18, v17, s4 -; GFX900-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v17 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc -; GFX900-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX900-NEXT: v_lshlrev_b32_e32 v16, 16, v17 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc -; GFX900-NEXT: s_mov_b32 s4, 0x5040100 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX900-NEXT: v_perm_b32 v0, v54, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v53, v1, s4 ; GFX900-NEXT: v_perm_b32 v2, v52, v2, s4 @@ -13425,7 +10314,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-LABEL: v_maximumnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: scratch_load_dword v51, off, s32 +; GFX950-NEXT: scratch_load_dword v50, off, s32 ; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30 ; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v14 @@ -13447,76 +10336,67 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v34 ; GFX950-NEXT: v_lshrrev_b32_e32 v33, 16, v15 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc -; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v37, v39 ; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v37, v39 ; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v23 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v37 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v36, v48 -; GFX950-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v37, v37, s0 -; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31 ; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v37 -; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX950-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v36, v36, s0 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 -; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX950-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 ; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v22 +; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31 +; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v36 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v21 +; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v20 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 +; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 ; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 +; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 ; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: s_waitcnt vmcnt(0) -; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v51 -; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v51 -; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc +; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50 +; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 ; GFX950-NEXT: v_lshlrev_b32_e32 v33, 16, v32 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v34 +; GFX950-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v33, v37 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX950-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v33, v33, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32 ; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v33 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 -; GFX950-NEXT: v_lshlrev_b32_e32 v34, 16, v36 +; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v28 ; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 -; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 -; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v28 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v34 +; GFX950-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX950-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 ; GFX950-NEXT: s_nop 1 @@ -13530,9 +10410,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX950-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v36, v36, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc @@ -13557,9 +10434,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX950-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v37, v37, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v35 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc @@ -13584,9 +10458,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX950-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v38, v38, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc @@ -13611,9 +10482,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX950-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v39, v39, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v37 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc @@ -13638,9 +10506,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX950-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v48, v48, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc @@ -13656,18 +10521,15 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v48 -; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v49, v50 -; GFX950-NEXT: v_lshrrev_b32_e32 v50, 16, v6 +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v48 +; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v49, v51 +; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v6 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX950-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v49, v49, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc @@ -13682,84 +10544,75 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v49, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v48 +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v48 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v49 -; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v50, v52 +; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v51, v52 ; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v5 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX950-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v50, v50, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v51, v49, v48, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v48 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v51 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc -; GFX950-NEXT: v_lshrrev_b32_e32 v50, 16, v21 +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v21 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v51, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v49 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v49, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v52, v53 ; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v4 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v52, v50, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX950-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v52, v52, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v52, v51, v49, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v52 -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 -; GFX950-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 +; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v51, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v52 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 +; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v4 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v20 -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v52, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v53, v54 ; GFX950-NEXT: v_lshrrev_b32_e32 v54, 16, v3 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v53, v52, v50, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX950-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v53, v53, s0 -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v52, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v3 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v19 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX950-NEXT: s_nop 1 @@ -13773,9 +10626,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v55, 16, v2 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX950-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v54, v54, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc @@ -13800,9 +10650,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v54, v53, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX950-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v55, v55, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc @@ -13827,9 +10674,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v40, v55, v54, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX950-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v40, v40, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v54, v40, v54, vcc @@ -13854,9 +10698,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v41, v40, v55, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX950-NEXT: v_max_f32_e32 v41, v41, v41 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v41, v41, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v55 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc @@ -13869,74 +10710,65 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v50 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v51, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v15, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v51 +; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v15, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v50 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v41, v40 ; GFX950-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v40, v51, v15, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX950-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v40, v40, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v40, v50, v15, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v15 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v50 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v51, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v40 -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v14 +; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v40 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v14 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v30 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v30 +; GFX950-NEXT: v_perm_b32 v15, v32, v15, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v30 -; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v40, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v30 +; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v40, v50 ; GFX950-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v51, v30, v14, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX950-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v51, v51, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v50, v30, v14, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v14, v51, v14, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v30 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v50 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v13 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v14, v51, v14, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v14, v31, v14, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v13 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v13 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v51, v30 +; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v50, v30 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX950-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v30, v30, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc @@ -13950,7 +10782,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v13, v33, v13, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v12 @@ -13960,9 +10792,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v30, v29 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX950-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v29, v29, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc @@ -13976,7 +10805,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v12, v34, v12, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v11 @@ -13986,9 +10815,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v29, v28 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX950-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v28, v28, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc @@ -14002,7 +10828,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v11, v35, v11, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v10 @@ -14012,9 +10838,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v28, v27 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX950-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v27, v27, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc @@ -14028,7 +10851,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v10, v36, v10, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v9 @@ -14038,9 +10861,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v27, v26 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX950-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v26, v26, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc @@ -14054,7 +10874,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v9, v37, v9, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v8 @@ -14064,9 +10884,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v26, v25 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX950-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v25, v25, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc @@ -14080,7 +10897,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v8, v38, v8, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v7 @@ -14090,9 +10907,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v24 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc @@ -14106,7 +10920,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v7, v39, v7, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v6 @@ -14116,9 +10930,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v24, v23 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX950-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v23, v23, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc @@ -14132,7 +10943,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v6, v48, v6, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v5 @@ -14142,9 +10953,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v23, v22 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX950-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v22, v22, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc @@ -14158,7 +10966,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v5, v49, v5, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v4 @@ -14168,9 +10976,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v22, v21 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX950-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v21, v21, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc @@ -14184,7 +10989,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v4, v51, v4, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v3 @@ -14194,9 +10999,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v21, v20 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX950-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v20, v20, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc @@ -14210,7 +11012,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v3, v52, v3, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v2 @@ -14220,9 +11022,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v20, v19 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX950-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v19, v19, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc @@ -14236,7 +11035,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v2, v53, v2, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v1 @@ -14246,9 +11045,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v19, v18 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX950-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v18, v18, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc @@ -14262,7 +11058,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v54, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v0 @@ -14272,3645 +11068,2645 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v18, v17 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX950-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v17, v17, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v54, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16 -; GFX950-NEXT: v_perm_b32 v2, v53, v2, s0 -; GFX950-NEXT: v_perm_b32 v3, v52, v3, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v16, 16, v17 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX950-NEXT: v_perm_b32 v4, v50, v4, s0 -; GFX950-NEXT: v_perm_b32 v5, v49, v5, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX950-NEXT: v_perm_b32 v0, v55, v0, s0 -; GFX950-NEXT: v_perm_b32 v6, v48, v6, s0 -; GFX950-NEXT: v_perm_b32 v7, v39, v7, s0 -; GFX950-NEXT: v_perm_b32 v8, v38, v8, s0 -; GFX950-NEXT: v_perm_b32 v9, v37, v9, s0 -; GFX950-NEXT: v_perm_b32 v10, v36, v10, s0 -; GFX950-NEXT: v_perm_b32 v11, v35, v11, s0 -; GFX950-NEXT: v_perm_b32 v12, v34, v12, s0 -; GFX950-NEXT: v_perm_b32 v13, v33, v13, s0 -; GFX950-NEXT: v_perm_b32 v14, v31, v14, s0 -; GFX950-NEXT: v_perm_b32 v15, v32, v15, s0 ; GFX950-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximumnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 -; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v12 +; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v28 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v53 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v31, v32, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v31 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v33, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v31, v32, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX10-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX10-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_add3_u32 v34, v34, v33, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32 -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v30 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v34, v32, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v32, 0xffff0000, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v14 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v32 -; GFX10-NEXT: v_and_b32_e32 v32, 0xffff0000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v34, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v33, v32, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v32 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v34, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v32, v33, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; GFX10-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX10-NEXT: v_bfe_u32 v35, v34, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_add3_u32 v35, v35, v34, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 +; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v11 ; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v35, v33, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v34 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v13 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v33 -; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v33, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v32 +; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v26 +; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v10 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v51, v51 +; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v34, v48, v39, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v33 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v35, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v33, v34, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v35 -; GFX10-NEXT: v_max_f32_e32 v35, v35, v35 -; GFX10-NEXT: v_bfe_u32 v36, v35, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v37, 0x400000, v35 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_add3_u32 v36, v36, v35, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v23 +; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v7 +; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v22 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v32, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v34 +; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v6 +; GFX10-NEXT: v_lshrrev_b32_e32 v70, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v38, v33, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v37 +; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v3 +; GFX10-NEXT: v_lshrrev_b32_e32 v85, 16, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX10-NEXT: v_cndmask_b32_e32 v35, v39, v34, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v33 +; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v31, v38 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v26 +; GFX10-NEXT: v_cndmask_b32_e64 v38, v53, v52, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v35 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v39, v48 +; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v9 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v25 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v50 +; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v25 +; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e64 v48, v52, v38, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v39, v39 +; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v38 +; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v39, v50, v49, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v39 +; GFX10-NEXT: v_cndmask_b32_e64 v50, v49, v39, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v52, v52 +; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v24 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v54, v53, s6 +; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v51, v55 +; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v49 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v53, v49, s7 +; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v23 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v55, v55 +; GFX10-NEXT: v_cmp_gt_f32_e64 s9, v31, v51 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v65, v64, s7 +; GFX10-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e64 v53, v64, v55, s7 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v65, v65 +; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v53 +; GFX10-NEXT: v_cndmask_b32_e64 v65, v67, v66, s7 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v52 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v64, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v65 +; GFX10-NEXT: v_cmp_gt_f32_e64 s8, v54, v67 +; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v64, v66, v65, s7 +; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v68, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v21 +; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v4 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54 +; GFX10-NEXT: v_lshrrev_b32_e32 v69, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v64 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v67, v66, s10 +; GFX10-NEXT: v_and_b32_e32 v67, 0xffff0000, v21 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v68, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v70, v69, s10 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v67, v67 +; GFX10-NEXT: v_lshlrev_b32_e32 v70, 16, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v66, v54, s10 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v71, v71 +; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v66 +; GFX10-NEXT: v_cndmask_b32_e64 v67, v69, v68, s10 +; GFX10-NEXT: v_and_b32_e32 v69, 0xffff0000, v3 +; GFX10-NEXT: v_cmp_gt_f32_e64 s11, v70, v81 +; GFX10-NEXT: v_and_b32_e32 v70, 0xffff0000, v2 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v69, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v71, s10 +; GFX10-NEXT: v_cmp_gt_f32_e64 s10, v31, v51 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v19 +; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v18 +; GFX10-NEXT: v_cmp_gt_f32_e64 s12, v82, v83 +; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v17 +; GFX10-NEXT: v_lshrrev_b32_e32 v83, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v69 +; GFX10-NEXT: v_cndmask_b32_e64 v71, v71, v69, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v70, v70 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v81, v80, s13 +; GFX10-NEXT: v_and_b32_e32 v81, 0xffff0000, v1 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v71 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v70, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v81, v81 +; GFX10-NEXT: v_and_b32_e32 v81, 0xffff0000, v17 +; GFX10-NEXT: v_cndmask_b32_e64 v83, v83, v82, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s14, v81, v81 +; GFX10-NEXT: v_cmp_gt_f32_e64 s13, v51, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v70 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v80 +; GFX10-NEXT: v_cndmask_b32_e64 v81, v82, v83, s14 +; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s14, v31, v51 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v83 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v81 +; GFX10-NEXT: v_cmp_gt_f32_e64 s15, v31, v51 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v16 +; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v16 +; GFX10-NEXT: v_cndmask_b32_e64 v82, v82, v51, s16 +; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v82 +; GFX10-NEXT: v_cndmask_b32_e64 v51, v51, v82, s16 +; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v51 +; GFX10-NEXT: v_cmp_gt_f32_e64 s16, v31, v84 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 +; GFX10-NEXT: v_lshrrev_b32_e32 v84, 16, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s17, v31, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v84, s17 +; GFX10-NEXT: v_and_b32_e32 v85, 0xffff0000, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s17, v85, v85 +; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v84, v84, v31, s17 +; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84 +; GFX10-NEXT: v_cmp_gt_f32_e64 s17, v85, v86 +; GFX10-NEXT: v_cndmask_b32_e64 v85, v84, v31, s17 +; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s17 +; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0, v84 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v31, v84, s17 +; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v85 +; GFX10-NEXT: v_cmp_eq_f32_e64 s17, 0, v84 +; GFX10-NEXT: v_cndmask_b32_e64 v84, v37, v32, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v32 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s17 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v84, v32, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v32, v37, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v84 +; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v37, v36, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v33 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v84, v32, s5 +; GFX10-NEXT: buffer_load_dword v84, off, s[0:3], s32 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v37, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v36 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v55 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v33, v36, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v37 +; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v36 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34 -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v28 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v35 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v37, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v49 ; GFX10-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v35 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v12 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v34 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v35, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v34 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v34, v35, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX10-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX10-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_add3_u32 v37, v37, v36, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v35, v34, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v11 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v35 -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v35 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v36, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX10-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX10-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v39, 0x400000, v37 +; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v35, v48, v38, s6 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v69 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v38, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v38, v50, v39, s9 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v48, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v38, v39, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v50, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v48, v52, v49, s8 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v48, v49, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v52 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v49, v52, s4 +; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v50 +; GFX10-NEXT: v_cndmask_b32_e64 v50, v53, v55, s7 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v50, v55, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v53 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v52, v53, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v53, v64, v65, s10 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v65 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v53, v65, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v64 +; GFX10-NEXT: v_cndmask_b32_e64 v65, v67, v68, s12 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v55, v64, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v64, v66, v54, s11 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v54 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v64, v54, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v66 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v54, v66, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v65, v68, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v66, v67, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65 +; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v67, v71, v69, s13 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v67, v69, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v71 +; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v70, s14 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v68, v71, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v70 +; GFX10-NEXT: v_cndmask_b32_e64 v71, v81, v83, s15 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v69, v70, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v80 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v70, v80, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v83 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v71, v83, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v81 +; GFX10-NEXT: v_lshrrev_b32_e32 v83, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v81, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v81, v51, v82, s16 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v82 +; GFX10-NEXT: v_cndmask_b32_e64 v82, v81, v82, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v51 +; GFX10-NEXT: v_cndmask_b32_e64 v51, v82, v51, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v36 +; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v82 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v35 +; GFX10-NEXT: v_cndmask_b32_e64 v34, v36, v34, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v14 +; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v82 +; GFX10-NEXT: v_and_b32_e32 v82, 0xffff0000, v15 +; GFX10-NEXT: v_cndmask_b32_e64 v35, v35, v37, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v50 +; GFX10-NEXT: v_cndmask_b32_e64 v85, v14, v30, s6 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v38, v39, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_add3_u32 v38, v38, v37, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36 -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v86, v30, v85, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 -; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v36 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v38, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v36, v37, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX10-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX10-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_add3_u32 v39, v39, v38, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37 -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v37, v36, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e64 v30, v48, v49, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v67 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v69 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v50, v52, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37 -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v37, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v37 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v39, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v37, v38, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX10-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX10-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_add3_u32 v48, v48, v39, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38 -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v38, v37, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v71 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v53, v55, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v38 -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v38 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v48, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v38, v39, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX10-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX10-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_add3_u32 v49, v49, v48, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v39, v38, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v7 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v81 +; GFX10-NEXT: v_cndmask_b32_e32 v38, v64, v54, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v84 +; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v84 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v83, v52, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v39 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v39, v48, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX10-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX10-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_add3_u32 v50, v50, v49, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48 -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v84 +; GFX10-NEXT: v_cndmask_b32_e32 v64, v15, v84, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX10-NEXT: v_cndmask_b32_e64 v15, v65, v66, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v55, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v52 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v84, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48 -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v48 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v48, v49, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX10-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX10-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_add3_u32 v51, v51, v50, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49 -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v49, v48, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v67, v68, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v49, v50, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX10-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX10-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v54, 0x400000, v51 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_add3_u32 v52, v52, v51, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v51, v52, v54, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v50, v49, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v54 +; GFX10-NEXT: v_cndmask_b32_e32 v48, v69, v70, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v66 +; GFX10-NEXT: v_cndmask_b32_e32 v49, v52, v55, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v67, v68 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v49 +; GFX10-NEXT: v_cndmask_b32_e32 v65, v54, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v50 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v50, v51, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX10-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX10-NEXT: v_bfe_u32 v54, v52, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v55, 0x400000, v52 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v52, v54, v55, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51 -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v51, v50, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v54, v50, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v51 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v51, v52, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX10-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX10-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v54, v55, v64, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v50, v71, v80, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v49, v55, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64 +; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 -; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v18 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v54 ; GFX10-NEXT: v_cndmask_b32_e32 v52, v55, v52, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v52, v51, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v54 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v2 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v55, v51, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v54, v52, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v54, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v52 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v52, v54, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX10-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX10-NEXT: v_bfe_u32 v64, v55, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v65, 0x400000, v55 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_add3_u32 v64, v64, v55, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v55, v64, v65, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX10-NEXT: v_and_b32_e32 v65, 0xffff0000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v65 ; GFX10-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v55 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v1 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v64, v52, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v55, v54, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v54 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v65 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v54, v55, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX10-NEXT: v_max_f32_e32 v64, v64, v64 -; GFX10-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v66, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 -; GFX10-NEXT: v_and_b32_e32 v66, 0xffff0000, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v55, v54, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v0 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v66 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v52, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v52, v81, v51, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v65, v54, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v64, v55, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v55 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v66 -; GFX10-NEXT: v_cndmask_b32_e32 v65, v55, v64, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX10-NEXT: v_max_f32_e32 v65, v65, v65 -; GFX10-NEXT: v_bfe_u32 v66, v65, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v67, 0x400000, v65 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX10-NEXT: v_add3_u32 v66, v66, v65, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v65, v66, v67, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64 -; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v65 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v66, v64, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v64, v55, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v65 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v66, v55, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v53, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v53, v53, v15, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v53, v15, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX10-NEXT: v_max_f32_e32 v64, v64, v64 -; GFX10-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v66, 0x400000, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v85 +; GFX10-NEXT: v_cndmask_b32_e32 v51, v65, v54, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v86 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v86, v85, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v66, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v65, v15, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v53, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v64 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v65, v15, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_perm_b32 v15, v31, v15, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v53, v30, v14, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX10-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX10-NEXT: v_bfe_u32 v64, v53, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v65, 0x400000, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v85 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v54, v85, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v53, v64, v65, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v64, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v53 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v64, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_perm_b32 v14, v32, v14, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX10-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX10-NEXT: v_bfe_u32 v53, v30, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v64, 0x400000, v30 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_add3_u32 v53, v53, v30, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v30, v53, v64, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v53, v28, v12, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v86 +; GFX10-NEXT: v_cndmask_b32_e32 v28, v55, v86, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v28, v54, v28, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v65 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v53, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 ; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX10-NEXT: v_perm_b32 v13, v33, v13, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX10-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX10-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v53, 0x400000, v29 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_add3_u32 v30, v30, v29, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v29, v30, v53, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v54 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v11 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v53, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX10-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX10-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_add3_u32 v29, v29, v28, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX10-NEXT: v_perm_b32 v13, v32, v13, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9 +; GFX10-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v29, v27, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v29 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v53, v26, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX10-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX10-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX10-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_add3_u32 v28, v28, v27, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v53 +; GFX10-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX10-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX10-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX10-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_add3_u32 v27, v27, v26, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX10-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX10-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v27, 0x400000, v25 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX10-NEXT: v_perm_b32 v9, v14, v9, 0x5040100 +; GFX10-NEXT: v_perm_b32 v14, v31, v28, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_add3_u32 v26, v26, v25, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v26 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX10-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v23 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX10-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX10-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX10-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_add3_u32 v24, v24, v23, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc_lo +; GFX10-NEXT: v_perm_b32 v8, v30, v8, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX10-NEXT: v_perm_b32 v7, v36, v7, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX10-NEXT: v_perm_b32 v6, v37, v6, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX10-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX10-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v24, 0x400000, v22 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_add3_u32 v23, v23, v22, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v22, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_add3_u32 v22, v22, v21, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX10-NEXT: v_perm_b32 v5, v38, v5, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_perm_b32 v4, v50, v4, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX10-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX10-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_add3_u32 v21, v21, v20, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_perm_b32 v3, v51, v3, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX10-NEXT: v_perm_b32 v3, v39, v3, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX10-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX10-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_add3_u32 v20, v20, v19, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_perm_b32 v2, v52, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX10-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX10-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_add3_u32 v19, v19, v18, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX10-NEXT: v_perm_b32 v1, v54, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX10-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX10-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_add3_u32 v18, v18, v17, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX10-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v55, v0, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_perm_b32 v2, v48, v2, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX10-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX10-NEXT: v_perm_b32 v15, v49, v51, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_v32bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: scratch_load_b32 v51, off, s32 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v69, v69 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v70, v70 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v18.h, v52.l, s25 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v52.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v80, v80 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v82.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v29 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v32, v32 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v38, v38 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134 +; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v30 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v13 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v11 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v10 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v112, v134 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v33, v33 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v13.h, v29.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v10.h, v26.h, s8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v82.l, v52.l, s44 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v55, v55 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v66, v66 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v67, v67 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v29.h, v15.l, s3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v30.h, v32.l, s2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v68, v68 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v39, v39 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v4.h, v20.h, s20 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v71, v71 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v5.h, v21.h, s18 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v26.h, v33.l, s9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v20.h, v39.l, s21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v33.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v55.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v66.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v80.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v48, v48 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v83, v83 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v3.h, v19.h, s22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v21.h, v38.l, s19 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v102, v132 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v19.h, v48.l, s23 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v71.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v80.l, v39.l, s42 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v85, v115 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v55.l, v15.l, s23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v101, v131 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v102, v102, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s26 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v96, v118 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v50 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v101.l, v71.l, v38.l, s41 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v96.l, v66.l, v33.l, s26 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v85, v85, v85 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v30.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v0.h, v16.h, s29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v32.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v55.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v30 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v34, v34 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v54, v54 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v96, v96, v96 :: v_dual_lshlrev_b32 v101, 16, v101 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v31, v31 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v35, v35 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v30.h, v14.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v84, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v12.h, v28.h, s4 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v14.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v101, v101, v101 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v36, v36 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v54.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v37, v37 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v64, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v11.h, v27.h, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v28.h, v31.l, s5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v65, v65 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v27.h, v32.l, s7 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v64.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v84, v114 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.h, v25.h, s10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v32.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v5.h, v21.h, s19 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v4.h, v20.h, s21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v3.h, v19.h, s23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v16.h, v54.l, s40 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v65.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v15 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v14 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v29.h, v33.l, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v28.h, v34.l, s6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v27.h, v35.l, s8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v26.h, v36.l, s10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v25.h, v37.l, s12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v24.h, v38.l, s14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v23.h, v39.l, s16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v22.h, v48.l, s18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v21.h, v49.l, s20 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v20.h, v50.l, s22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v19.h, v51.l, s24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v54.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v86, v118 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v85.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v87, v87 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v96, v96 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v39.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v50.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v51.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v18.h, v52.l, s26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v17.h, v53.l, s28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v64.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v54.l, v14.l, s22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v8.h, v24.h, s12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v25.h, v34.l, s11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v86, v116 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.h, v23.h, s14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v34.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v24.h, v35.l, s13 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v67.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v87, v117 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v64.l, v31.l, s24 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v84, v84, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v6.h, v22.h, s16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v35.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v23.h, v36.l, s15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v68.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v65.l, v32.l, s25 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-TRUE16-NEXT: v_bfe_u32 v114, v84, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v22.h, v37.l, s17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v17.h, v53.l, s27 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v97, v97 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v32.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v37.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v53.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v69.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v97, v119 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v87, 16, v87 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, 0x400000, v84 -; GFX11-TRUE16-NEXT: v_bfe_u32 v116, v85, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v114, v114, v84, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v84, v84 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v84.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v119 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v128 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v129 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v130 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v131 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v132 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v133 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v134 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v135 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v144 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v145 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s63, v116, v86 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v55.l, v32.l, s40 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v55.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v70.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v98, v128 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v97.l, v67.l, v34.l, s27 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v87, v87, v87 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, 0x400000, v85 -; GFX11-TRUE16-NEXT: v_bfe_u32 v118, v86, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v116, v116, v85, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v114, v114, v115, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v85, v85 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v99, v129 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v68.l, v35.l, s28 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v146 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v147 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v87, v118 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v96, v119 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s45, v98, v129 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s56, v101, v132 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s59, v112, v135 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s60, v113, v144 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v86.l, v32.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v86.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v34.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v36.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v39.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v50.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v51.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s46, v99, v130 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s61, v114, v145 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s62, v115, v146 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v96.l, v65.l, v34.l, s43 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v67.l, v36.l, s45 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v101.l, v70.l, v39.l, s56 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v81.l, v50.l, s59 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v113.l, v82.l, v51.l, s60 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v55.l, s16 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v118 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v33.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v37.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v48.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v52.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v53.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v119, 0x400000, v86 -; GFX11-TRUE16-NEXT: v_bfe_u32 v128, v87, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v118, v118, v86, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v116, v116, v117, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v86, v86 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v48.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v81.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v100, v130 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v99.l, v69.l, v36.l, s29 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v97, v97, v97 :: v_dual_lshlrev_b32 v98, 16, v98 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v129, 0x400000, v87 -; GFX11-TRUE16-NEXT: v_bfe_u32 v130, v96, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v118, v118, v119, s22 -; GFX11-TRUE16-NEXT: v_add3_u32 v128, v128, v87, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v87, v87 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v70.l, v37.l, s40 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v98, v98, v98 :: v_dual_lshlrev_b32 v99, 16, v99 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v131, 0x400000, v96 -; GFX11-TRUE16-NEXT: v_bfe_u32 v132, v97, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v130, v130, v96, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v128, v128, v129, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v96, v96 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v103, v133 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v99, v99, v99 :: v_dual_lshlrev_b32 v100, 16, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v133, 0x400000, v97 -; GFX11-TRUE16-NEXT: v_bfe_u32 v134, v98, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v132, v132, v97, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v96, v130, v131, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v97, v97 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v100, v100, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v98 -; GFX11-TRUE16-NEXT: v_bfe_u32 v145, v99, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v134, v134, v98, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v97, v132, v133, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v98, v98 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v99 -; GFX11-TRUE16-NEXT: v_bfe_u32 v147, v100, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v145, v145, v99, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v100 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v98, v134, v144, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v99, v99 -; GFX11-TRUE16-NEXT: v_bfe_u32 v115, v101, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v147, v147, v100, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v99, v145, v146, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v100, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v101 -; GFX11-TRUE16-NEXT: v_add3_u32 v115, v115, v101, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v32.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v116.h, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v84, v147, v84, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v101, v101 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v118.h, v31.l, s5 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v34.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v128.h, v32.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v33.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v35.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v97.h, v34.l, s7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v37.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v96.h, v33.l, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v98.h, v35.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v99.h, v36.l, s8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v38.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v85, v115, v85, s22 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v54.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v55.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v114.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v117, v102, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v64.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v102, v102 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v54.l, s11 -; GFX11-TRUE16-NEXT: v_add3_u32 v117, v117, v102, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v39.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v114 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v64.l, s13 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v65.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v86, v117, v86, s22 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v115, 0xffff0000, v128 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v53.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v66.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v83.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v103.l, v81.l, v48.l, s43 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v116 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v65.l, s14 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v115 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v71.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v70.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v81.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v64.l, v33.l, s42 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v99.l, v68.l, v37.l, s46 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v114.l, v83.l, v52.l, s61 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v115.l, v84.l, v53.l, s62 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v96.l, v34.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v98.l, v36.l, s5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v101.l, v39.l, s8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v101.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v112.l, v50.l, s11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v112.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v113.l, v51.l, s12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v113.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v55 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v38.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v49.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v54.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v97, v128 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v116.l, v85.l, v54.l, s63 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v87.l, v33.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v99.l, v37.l, s6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v114.l, v52.l, s13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v114.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v115.l, v53.l, s14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v115.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v39 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v35.h, v81.l, s26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v35.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v102 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v67.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v68.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v98 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v103, v103, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v70.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s17 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v131 -; GFX11-TRUE16-NEXT: v_bfe_u32 v119, v103, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v132 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v96 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v80.l -; GFX11-TRUE16-NEXT: v_add3_u32 v119, v119, v103, 0x7fff -; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v97 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v69.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v117 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v85 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v133 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s57, v102, v133 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v97.l, v66.l, v35.l, s44 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v116.l, v54.l, s15 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v116.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v51 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v48.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v65.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v66.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s47, v100, v131 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s58, v103, v134 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v71.l, v48.l, s57 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v96.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v97.l, v35.l, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v97.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v52 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v38.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v49.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v64.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v71.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v69.l, v38.l, s47 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v103.l, v80.l, v49.l, s58 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v87.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v102.l, v48.l, s9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v102.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v30.h, v65.l, s18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v128 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v66.l, s19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v129 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v80.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0, v85.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v38.l, s7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v103.l, v49.l, s10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v103.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v14.h, v64.l, s17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v119 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v34.h, v71.l, s24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v48 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v65 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v66 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v86.l, v13.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s25 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v49 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v37.h, v85.l, s41 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v64 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v71 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v96.l, v30.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v97.l, v32.l, s4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v67.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v68.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v98.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v99.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v87.l, v38.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v102.l, v38.h, s9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.h, v67.l, s20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v130 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v131 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0, v84.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v70 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0, v82.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v68 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v84.l, s29 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v101.l, v34.l, s8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v83.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v80 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v82.l, s27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v115.l, v37.l, s14 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v69.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v36.h, v83.l, s28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v103.l, v35.l, s10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v113.l, v36.l, s12 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v100.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.h, v69.l, s22 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v81 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v114.l, v48.l, s13 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v132 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v69 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v33.h, s7 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v51 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v50.h, v51.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v31.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v118 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.h, v31.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v84.h, v37.l, s4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v85.h, v38.l, s9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v101 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v32.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v129 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s19 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v130 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v99 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v35, v36 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v14.h, v55.l, s12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v86.h, v39.l, s10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v86 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v32.l, v31.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v100 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v118.h, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v39 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v114.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v31.h, v66.l, s15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v128.h, v15.h, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v32.h, v67.l, s16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v86.h, v35.l, s9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v96.h, v36.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v33.h, v69.l, s18 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v54, v38, v38 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v34.h, v71.l, s20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v116.h, v35.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v98.h, v33.l, s5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v84.h, v34.l, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v97.h, v37.l, s4 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v130 -; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v99.h, v37.h, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v54, v55, v64, s11 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v64, v112, v112 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v54.h, v31.l, s10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v54 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v32.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v85.h, v38.l, s8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v54.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v135 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v103, v103 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v113, v54 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v119, v87 :: v_dual_and_b32 v54, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v15.h, v31.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v83.l, v53.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v55.h, v48.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v81.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v0.h, v16.h, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v50.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v31.h, v50.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v31 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v98.l, v32.h, s5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v51.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v99.l, v33.l, s6 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v54, v65, v66, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v67 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v16.h, v15.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v81.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v54.h, v52.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v64, v64, v64 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v50.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v53 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v31.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v65 -; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v64, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v66 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v82.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX11-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v65 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v50 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.h, v55.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v64, v66, v67, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v53.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v68 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v64.h, v53.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.l, v50.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v52 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v51.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v50.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v38, v53 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v112.l, v39.l, s11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v51.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v14.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v30.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v50.l, v51.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v83.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.h, v54.h, v32.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v15.h, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v117, v117 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v31.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v116.l, v49.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v52, v52 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v51.l, v33.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v34.l, v83.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v14.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v64 -; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v52, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v49.l, v30.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX11-TRUE16-NEXT: v_add3_u32 v49, v66, v52, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v52 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v65, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v34.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v64.h, v32.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.l, v33.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v30.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v49, v53, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v34.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v32.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v30.l, v14.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v29.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v15.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v52 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v52, v55, v55 :: v_dual_and_b32 v53, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v34.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v13.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v29.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v31.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v15.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v52, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v13.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v12 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v29.l, v13.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v52, v54, v65, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v53, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v15.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v52.h, v33.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v49, v54, v55, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v34.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v52 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v12.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v34.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v31.l, v14.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v64 -; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v53, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v64, v65, v53, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v53 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v66 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v28.l, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v53, v64, v65, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v52, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v30.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v29.l, v13.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v31.l, v12.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v30.l, v13.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v14.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v53.h, v13.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v29.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v27.l, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v28.l, v12.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v53 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v52.h, v12.h, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v49, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v29 -; GFX11-TRUE16-NEXT: v_add3_u32 v27, v55, v49, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v49 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v54, v52 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v53.h, v11.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v26.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v27, v29, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v13.l, v11.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v29.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v49 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v27, v12, v12 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v28.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v25.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v9.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; GFX11-TRUE16-NEXT: v_add3_u32 v28, v28, v27, 0x7fff +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v31.l, v12.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v28.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v31.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v29.h, v9.h, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v27, v28, v53, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8 -; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v27.h, v11.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX11-TRUE16-NEXT: v_add3_u32 v29, v29, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v30.l, v11.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.h, v28.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v27.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v12.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v26.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v26.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v52 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v51, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v31.l, v10.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v27.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v12.l, v10.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v9.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v26.l, v9.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v25.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v25.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v26 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v29, v49, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v24.l, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v12.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v28, v28 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v11.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v13.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v26.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v10, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v26 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v52, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v24.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v10.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v8.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v12.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v24.h, v9.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v25.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v27.h, v8.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v25.l, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.h, v9.h, s1 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v27, v10, v10 :: v_dual_and_b32 v26, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v27, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v27, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v22.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v24.h, v7.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v25.l, v8.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v11.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v12.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v22.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v25, v8, v8 :: v_dual_lshlrev_b32 v24, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v11.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v22 -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v25, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v6.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v11.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v26 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v25, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v22.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v10.l, v7.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.h, v12.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v24, v25, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v25 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v22.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v21, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v11.h, v7.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v11.l, v6.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v10.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v11 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v21 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v9.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v22, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v9, v21 :: v_dual_lshlrev_b32 v9, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v7.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v8.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v11.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v6, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v19 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v12, v20, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_and_b32 v11, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v9.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v10.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v10.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v8.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v18 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v8.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v19, v20, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.h, v4.l, s3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v9.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v6.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v17.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v16.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v7.l, v4.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v18.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v8.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v17 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v12, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v2.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v12 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v19, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v12, v16, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v12.h, v3.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v16, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v8, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v10, v17, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v18, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v12.h, v1.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v11.h, v0.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v5.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v7.h, v2.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v30 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v5.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v8.l, v1.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v6.l, v0.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v9.l, v2.h, s3 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v50 :: v_dual_mov_b32 v4, v48 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v13 :: v_dual_mov_b32 v1, v30 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v51 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v39 :: v_dual_mov_b32 v6, v38 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v37 :: v_dual_mov_b32 v8, v35 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v33 :: v_dual_mov_b32 v10, v32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v31 :: v_dual_mov_b32 v12, v36 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v34 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v37 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v32bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v29 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: scratch_load_b32 v50, off, s32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v52, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v39, v64, v55 :: v_dual_and_b32 v70, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v68, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v80, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v84, v83, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v96, v87, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v100, v99, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v112, v103 :: v_dual_and_b32 v81, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v116, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v128, v119, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v66, v66 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v82, v132, v131 :: v_dual_and_b32 v113, 0xffff0000, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v84, v144, v135 :: v_dual_and_b32 v117, 0xffff0000, v20 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v102, v144, v135, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v34, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v147, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v36, v36, v35, s3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v14, v30, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v51, v51, v52 :: v_dual_lshlrev_b32 v118, 16, v102 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v51 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v51 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v54, v54 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v52 :: v_dual_lshlrev_b32 v118, 16, v67 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v38 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v54, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v64 :: v_dual_lshlrev_b32 v128, 16, v83 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v97, v99, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v103, v68, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v39 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v101, v115, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v113 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v34 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v49 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v87 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v103, v119, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v115, v119, v98, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v71 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v103 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v113, v131, v82, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v86, v114 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v52 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v99 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v113 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v115 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v48, v116 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v85, 16, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v114, v86, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v86 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v55 -; GFX11-FAKE16-NEXT: v_add3_u32 v114, v114, v86, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v117 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v118 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v66 -; GFX11-FAKE16-NEXT: v_bfe_u32 v118, v48, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v119 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v70 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v102, 16, v80 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v71, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v128 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v68 -; GFX11-FAKE16-NEXT: v_add3_u32 v118, v118, v48, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v128, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v129 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v82 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_add3_u32 v128, v128, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v64, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v81, v81, v81 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v81 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v97 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v85, v85, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v96, v130 -; GFX11-FAKE16-NEXT: v_bfe_u32 v146, v85, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v147, 0x400000, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v97, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v98, v131 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v50, v147, v38 :: v_dual_lshlrev_b32 v49, 16, v52 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v39 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v129, v30, v66 :: v_dual_lshlrev_b32 v30, 16, v35 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v130 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v35, v36, s0 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v37, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v51, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add3_u32 v146, v146, v85, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v101 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v99, v68, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v100, v132 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v96, v96, v96 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v100, v101, v70, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v102, v133 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v98, v98, v98 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v102, v103, v80, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v134 -; GFX11-FAKE16-NEXT: v_bfe_u32 v134, v81, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v100, v100, v100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v82, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 -; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v96, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v134, v134, v81, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v114, v114, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v96 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v86, v86, v96, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v69, v69, v69 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v132, v69, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v133, 0x400000, v69 -; GFX11-FAKE16-NEXT: v_add3_u32 v132, v132, v69, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX11-FAKE16-NEXT: v_bfe_u32 v116, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v116, v116, v36, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v98, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v116, v116, v117, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v98 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v100, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v98, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v118, v118, v119 :: v_dual_max_f32 v65, v65, v65 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v100 -; GFX11-FAKE16-NEXT: v_add3_u32 v48, v48, v100, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v130, v65, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v131, 0x400000, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v128, v129, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v130, v130, v65, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v130, v131, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v132, v133, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v134, v144, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v146, v147, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v118 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v114 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v117, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v100, v100 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v116 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v128 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v48, v119, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v114 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v116 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v116, 0xffff0000, v118 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v48, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v128 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v100, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v115, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v117, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v119, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v34, v39, v48, s0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v131 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v54, 16, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v132 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v133 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v134 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v135 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v85, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v81 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v97, v144 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v101, v145 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v146 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v112, v113, v96 :: v_dual_lshlrev_b32 v49, 16, v117 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v114, v147 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v119 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v116, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v118, v130 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v37 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v128, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v50, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v34, v48, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v128, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v130, v54 :: v_dual_and_b32 v65, 0xffff0000, v65 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v37, v52, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v131, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v147, v32, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v132, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v133, v68 :: v_dual_and_b32 v81, 0xffff0000, v81 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v54, v147 :: v_dual_and_b32 v85, 0xffff0000, v85 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v70 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v144, v70, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v80 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v86 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v96 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v98 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v49, 16, v34 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v133, 16, v69 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v102 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v147 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v102, v102, v102 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v128, v38 :: v_dual_lshlrev_b32 v135, 16, v85 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v102, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v102 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v34, v68 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v102, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v54, v147, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v48, v52, v51 :: v_dual_lshlrev_b32 v145, 16, v101 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v37, v37, v55 :: v_dual_lshlrev_b32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v64, v55 :: v_dual_lshlrev_b32 v147, 16, v114 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v39, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v51, 16, v128 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83 -; GFX11-FAKE16-NEXT: v_add3_u32 v55, v55, v34, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v52, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v87 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v87, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v97 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v31, v97, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v99 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v32, v99, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v98 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v48, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v100, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v116 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v115, v36 :: v_dual_and_b32 v86, 0xffff0000, v86 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v118 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v117, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v119, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v128, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v130, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0, v147 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v147, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v131, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v132, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v103 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v86, v103, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v113 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v117 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v119 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v38, v50, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v130 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v133, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v112 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v15, v31, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v67, v51, v51 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v135, v84, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v53, v129 :: v_dual_lshlrev_b32 v55, 16, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v84 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v101 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v101, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v52 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v54, v84, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v80 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v66, v80, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v80, 16, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v144, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v67, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v103 -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v67, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v103, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v70, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v66, v55, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v69, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v65, v82 :: v_dual_lshlrev_b32 v70, 16, v55 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v68, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v70 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v50 :: v_dual_lshlrev_b32 v64, 16, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v50, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v31, v53 :: v_dual_lshlrev_b32 v55, 16, v52 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v54 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v55 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v52, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v65 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v54, v53 :: v_dual_lshlrev_b32 v65, 16, v55 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v55, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v15, v50 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v50 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v113 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v113 :: v_dual_lshlrev_b32 v80, 16, v68 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v68, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v70, v84, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v65, v69, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v64, v53, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v80, v71 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v65, v50, v68 :: v_dual_lshlrev_b32 v80, 16, v30 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v14, v30, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v65, v65, v65 :: v_dual_max_f32 v66, v66, v66 -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v66, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v66 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v66, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v64, v71 :: v_dual_lshlrev_b32 v71, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v70, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v69 -; GFX11-FAKE16-NEXT: v_bfe_u32 v54, v65, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v67, v53, v67 :: v_dual_lshlrev_b32 v66, 16, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v54, v54, v65, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v70, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v30, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v13, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v29 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v80, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v29, v71, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v67, v55, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v66 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v54 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v66, v13, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v53, v29 :: v_dual_lshlrev_b32 v70, 16, v71 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v68, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v70, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v71, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v66, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v50, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v54 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v53, v66, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v50, v50, v53 :: v_dual_max_f32 v53, v55, v55 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v53 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v66 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v53, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v129 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v54, 16, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v129, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v53, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v53, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v12 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v69 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0, v129 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v55, v129, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v64 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v65 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v54, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v64, v67 :: v_dual_lshlrev_b32 v68, 16, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v28, v12 :: v_dual_lshlrev_b32 v67, 16, v11 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v27, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v55, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v30, v71 :: v_dual_lshlrev_b32 v55, 16, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v66 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v67, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v54, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v68, v65 :: v_dual_max_f32 v55, v55, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v55, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v55 -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v50, v55, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v65, v26, v10 :: v_dual_lshlrev_b32 v64, 16, v64 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v64, v64, v64 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v30, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v50 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v65 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v30, v12 :: v_dual_lshlrev_b32 v67, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v67, v55 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v65, v10 :: v_dual_lshlrev_b32 v55, 16, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX11-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v53 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v54, 16, v26 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v25 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v25, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v54, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v54, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 +; GFX11-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v24, v8 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v50, 16, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v50, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v53, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_and_b32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v65 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v54, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v23, v7 :: v_dual_lshlrev_b32 v55, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v26, 16, v8 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_add3_u32 v25, v28, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v28, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v8 :: v_dual_lshlrev_b32 v29, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v54, v9 :: v_dual_lshlrev_b32 v64, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v5 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_perm_b32 v9, v36, v9, 0x5040100 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v23, v7 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v50, v8 :: v_dual_lshlrev_b32 v55, 16, v22 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v22, v6 :: v_dual_lshlrev_b32 v54, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v24 :: v_dual_lshlrev_b32 v53, 16, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v50, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v26, v8 :: v_dual_lshlrev_b32 v25, 16, v22 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v25, v7 :: v_dual_lshlrev_b32 v50, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v21, v5 :: v_dual_lshlrev_b32 v53, 16, v20 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v50 :: v_dual_lshlrev_b32 v50, 16, v20 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v20, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v28, 16, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v22 :: v_dual_lshlrev_b32 v53, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v22, v28, v28 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v3 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v22, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v28, v5 :: v_dual_lshlrev_b32 v50, 16, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX11-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v22, 0x7fff -; GFX11-FAKE16-NEXT: v_perm_b32 v8, v37, v8, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v17 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v19, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v30, v54 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_lshlrev_b32 v30, 16, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v28, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v24, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v28, 16, v18 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v24, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v17, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v24, v28, v28 :: v_dual_lshlrev_b32 v25, 16, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v16, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v24, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v25, v25, v25 :: v_dual_lshlrev_b32 v22, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v24, v3 :: v_dual_lshlrev_b32 v20, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v25, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_max_f32_e32 v19, v22, v22 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v28, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v50, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v19, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v53, v19, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v50, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v20, 16, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v20 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v17, v1 :: v_dual_lshlrev_b32 v25, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v21, v1 :: v_dual_and_b32 v16, 0xffff0000, v22 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: v_perm_b32 v1, v14, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX11-FAKE16-NEXT: v_perm_b32 v14, v31, v27, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v13, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: v_perm_b32 v13, v32, v26, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v2, v15, v2, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_perm_b32 v15, v39, v29, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100 -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX12-TRUE16-LABEL: v_maximumnum_v32bf16: -; GFX12-TRUE16: ; %bb.0: -; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0 -; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 -; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 -; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-TRUE16-NEXT: scratch_load_b32 v51, off, s32 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v69, v69 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v70, v70 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v14 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v18.h, v52.l, s25 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v52.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v80, v80 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v82.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v29 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v32, v32 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v38, v38 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v112, v134 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v33, v33 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v13.h, v29.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v10.h, v26.h, s8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v82.l, v52.l, s44 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v55, v55 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v66, v66 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v67, v67 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v29.h, v15.l, s3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v68, v68 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v39, v39 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v4.h, v20.h, s20 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v71, v71 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v5.h, v21.h, s18 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v15.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v26.h, v33.l, s9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v20.h, v39.l, s21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v33.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v55.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v66.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v80.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v48, v48 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v83, v83 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v3.h, v19.h, s22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v21.h, v38.l, s19 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v102, v132 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v19.h, v48.l, s23 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v71.l +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-TRUE16-LABEL: v_maximumnum_v32bf16: +; GFX12-TRUE16: ; %bb.0: +; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0 +; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 +; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v30 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v13 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v80.l, v39.l, s42 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v85, v115 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v9 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v55.l, v15.l, s23 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v101, v131 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v102, v102, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v53, v53 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s26 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v96, v118 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v50 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v101.l, v71.l, v38.l, s41 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v28 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.l, v66.l, v33.l, s26 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v85, v85, v85 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v30.h, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v30 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v34, v34 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v54, v54 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v96, v96, v96 :: v_dual_lshlrev_b32 v101, 16, v101 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v31, v31 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v35, v35 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v30.h, v14.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v84, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v12.h, v28.h, s4 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v14.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v101, v101, v101 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v36, v36 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v54.l ; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v37, v37 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v64, v64 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v16 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v30.h, v32.l, s2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v28 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v11.h, v27.h, s6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v28.h, v31.l, s5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v65, v65 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v31.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v27.h, v32.l, s7 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v64.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v84, v114 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.h, v25.h, s10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v0.h, v16.h, s29 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v32.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v55.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v5.h, v21.h, s19 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v4.h, v20.h, s21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v3.h, v19.h, s23 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v16.h, v54.l, s40 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v65.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v15 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v14 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v29.h, v33.l, s4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v28.h, v34.l, s6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v27.h, v35.l, s8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v26.h, v36.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v25.h, v37.l, s12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v24.h, v38.l, s14 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v23.h, v39.l, s16 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v22.h, v48.l, s18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v21.h, v49.l, s20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v20.h, v50.l, s22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v19.h, v51.l, s24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v54.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v86, v118 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v85.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v30 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v87, v87 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v96, v96 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v39.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v50.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v51.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v18.h, v52.l, s26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v17.h, v53.l, s28 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v64.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v97, v97 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v54.l, v14.l, s22 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v8.h, v24.h, s12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v25.h, v34.l, s11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v32.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v37.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v53.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v86, v116 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.h, v23.h, s14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v34.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v24.h, v35.l, s13 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v67.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v87, v117 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v64.l, v31.l, s24 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v84, v84, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v6.h, v22.h, s16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v35.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v23.h, v36.l, s15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v68.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v65.l, v32.l, s25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX12-TRUE16-NEXT: v_bfe_u32 v114, v84, 16, 1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v36.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v22.h, v37.l, s17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v17.h, v53.l, s27 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v69.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v97, v119 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v87, 16, v87 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v115, 0x400000, v84 -; GFX12-TRUE16-NEXT: v_bfe_u32 v116, v85, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v114, v114, v84, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v84, v84 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v147.l, v84.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v119 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v128 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v129 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v130 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v131 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v132 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v133 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v134 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v135 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v144 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v145 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s63, v116, v86 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v55.l, v32.l, s40 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v55.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v70.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v98, v128 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v146 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v147 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v87, v118 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v96, v119 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s45, v98, v129 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s56, v101, v132 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s59, v112, v135 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s60, v113, v144 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v97.l, v67.l, v34.l, s27 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v87, v87, v87 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v117, 0x400000, v85 -; GFX12-TRUE16-NEXT: v_bfe_u32 v118, v86, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v116, v116, v85, 0x7fff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v114, v114, v115, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v85, v85 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v99, v129 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v68.l, v35.l, s28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v86.l, v32.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v86.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v34.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v36.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v39.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v50.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v51.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s46, v99, v130 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s61, v114, v145 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s62, v115, v146 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.l, v65.l, v34.l, s43 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v67.l, v36.l, s45 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v101.l, v70.l, v39.l, s56 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v81.l, v50.l, s59 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v113.l, v82.l, v51.l, s60 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v55.l, s16 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v118 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v33.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v37.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v48.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v52.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v53.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v119, 0x400000, v86 -; GFX12-TRUE16-NEXT: v_bfe_u32 v128, v87, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v118, v118, v86, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v116, v116, v117, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v86, v86 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v48.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v81.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v100, v130 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v99.l, v69.l, v36.l, s29 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v97, v97, v97 :: v_dual_lshlrev_b32 v98, 16, v98 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v129, 0x400000, v87 -; GFX12-TRUE16-NEXT: v_bfe_u32 v130, v96, 16, 1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v70.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v81.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v64.l, v33.l, s42 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v118, v118, v119, s22 -; GFX12-TRUE16-NEXT: v_add3_u32 v128, v128, v87, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v87, v87 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v99.l, v68.l, v37.l, s46 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v114.l, v83.l, v52.l, s61 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v115.l, v84.l, v53.l, s62 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v96.l, v34.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v98.l, v36.l, s5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v101.l, v39.l, s8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v39.l, v101.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v112.l, v50.l, s11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v112.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v113.l, v51.l, s12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v113.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v55 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v38.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v49.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v54.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v97, v128 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v116.l, v85.l, v54.l, s63 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v87.l, v33.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v99.l, v37.l, s6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v114.l, v52.l, s13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v114.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v115.l, v53.l, s14 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v115.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v39 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v35.h, v81.l, s26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v35.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v70.l, v37.l, s40 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v98, v98, v98 :: v_dual_lshlrev_b32 v99, 16, v99 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v131, 0x400000, v96 -; GFX12-TRUE16-NEXT: v_bfe_u32 v132, v97, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v130, v130, v96, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v128, v128, v129, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v96, v96 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v103, v133 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v99, v99, v99 :: v_dual_lshlrev_b32 v100, 16, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v133, 0x400000, v97 -; GFX12-TRUE16-NEXT: v_bfe_u32 v134, v98, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v132, v132, v97, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v96, v130, v131, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v97, v97 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v100, v100, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v98 -; GFX12-TRUE16-NEXT: v_bfe_u32 v145, v99, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v134, v134, v98, 0x7fff +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s57, v102, v133 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v97, v132, v133, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v98, v98 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v99 -; GFX12-TRUE16-NEXT: v_bfe_u32 v147, v100, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v145, v145, v99, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v100 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v98, v134, v144, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v99, v99 -; GFX12-TRUE16-NEXT: v_bfe_u32 v115, v101, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v147, v147, v100, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v31.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v99, v145, v146, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v100, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v101 -; GFX12-TRUE16-NEXT: v_add3_u32 v115, v115, v101, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v32.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v116.h, v15.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v97.l, v66.l, v35.l, s44 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v116.l, v54.l, s15 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v116.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v51 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v48.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v65.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v66.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s47, v100, v131 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s58, v103, v134 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v71.l, v48.l, s57 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v96.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v97.l, v35.l, s4 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v97.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v52 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v38.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v49.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v64.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v71.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v84, v147, v84, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v101, v101 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v118.h, v31.l, s5 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v34.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v128.h, v32.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v33.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v35.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v36.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v69.l, v38.l, s47 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v103.l, v80.l, v49.l, s58 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v87.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v102.l, v48.l, s9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v48.l, v102.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v30.h, v65.l, s18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v128 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v66.l, s19 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v129 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v80.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0, v85.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v38.l, s7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v103.l, v49.l, s10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v103.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v14.h, v64.l, s17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v119 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v34.h, v71.l, s24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v48 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v65 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v66 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v86.l, v13.h, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v97.h, v34.l, s7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v37.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v96.h, v33.l, s6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v98.h, v35.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v99.h, v36.l, s8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v38.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v85, v115, v85, s22 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v54.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v55.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s25 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v49 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v37.h, v85.l, s41 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v64 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v71 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v96.l, v30.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v97.l, v32.l, s4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v67.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v68.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v98.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v99.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v114.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v117, v102, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v64.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v102, v102 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v54.l, s11 -; GFX12-TRUE16-NEXT: v_add3_u32 v117, v117, v102, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v39.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v114 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v87.l, v38.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v102.l, v38.h, s9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.h, v67.l, s20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v130 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v131 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0, v84.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v70 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0, v82.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v68 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v64.l, s13 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v65.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v86, v117, v86, s22 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v115, 0xffff0000, v128 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v53.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v66.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v83.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v103.l, v81.l, v48.l, s43 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v116 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v84.l, s29 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v101.l, v34.l, s8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v83.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v80 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v82.l, s27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v115.l, v37.l, s14 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v69.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v65.l, s14 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v115 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v71.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v102 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v67.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v68.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v98 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v103, v103, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v70.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v84 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v36.h, v83.l, s28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v103.l, v35.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v113.l, v36.l, s12 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v100.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.h, v69.l, s22 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v81 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v114.l, v48.l, s13 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v132 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v69 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s17 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v131 -; GFX12-TRUE16-NEXT: v_bfe_u32 v119, v103, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v132 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v96 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v80.l -; GFX12-TRUE16-NEXT: v_add3_u32 v119, v119, v103, 0x7fff -; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v97 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v69.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v117 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v85 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v133 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v33.h, s7 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v51 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v50.h, v51.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v31.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v118 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.h, v31.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v84.h, v37.l, s4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v85.h, v38.l, s9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v101 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v32.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v129 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s19 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v130 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v99 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v35, v36 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v14.h, v55.l, s12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v86.h, v39.l, s10 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v86 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v31.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v32.l, v31.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v100 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v118.h, v15.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v39 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v114.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v31.h, v66.l, s15 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v128.h, v15.h, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v32.h, v67.l, s16 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v86.h, v35.l, s9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v96.h, v36.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v33.h, v69.l, s18 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v54, v38, v38 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v34.h, v71.l, s20 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v116.h, v35.h, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v98.h, v33.l, s5 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v84.h, v34.l, s7 -; GFX12-TRUE16-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v97.h, v37.l, s4 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v130 -; GFX12-TRUE16-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v99.h, v37.h, s6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v54, v55, v64, s11 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v64, v112, v112 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v54.h, v31.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v15.h, v31.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v54 -; GFX12-TRUE16-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v32.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX12-TRUE16-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v85.h, v38.l, s8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v54.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v135 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v103, v103 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v113, v54 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v55, v119, v87 :: v_dual_and_b32 v54, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v83.l, v53.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v50.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v15.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v55.h, v48.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v81.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v15.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v0.h, v16.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v31.h, v50.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v31 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v98.l, v32.h, s5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v51.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v99.l, v33.l, s6 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v54, v65, v66, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v67 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v55 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v16.h, v15.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v81.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v54.h, v52.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v64, v64, v64 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v50.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v53 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v31.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v65 -; GFX12-TRUE16-NEXT: v_bfe_u32 v67, v64, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v66 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v82.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX12-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v65 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v50 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v54 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.h, v55.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v64, v66, v67, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v53.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v68 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.l, v50.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v52 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v51.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v50.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v38, v53 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v112.l, v39.l, s11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v64.h, v53.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v51.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v30.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v33.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v50.l, v51.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v83.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.h, v54.h, v32.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v49 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v51.l, v33.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v65.l, v33.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v34.l, v83.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v52, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v14.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v64 -; GFX12-TRUE16-NEXT: v_bfe_u32 v66, v52, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v49.l, v30.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX12-TRUE16-NEXT: v_add3_u32 v49, v66, v52, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v52 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v65, v55 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v15.h, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v117, v117 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v31.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v34.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v116.l, v49.l, vcc_lo +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v64.h, v32.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.l, v33.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v30.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v49, v49, v53, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v34.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v30.l, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v29.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v15.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v52 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v31.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v31.l, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v52, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v52, v55, v55 :: v_dual_and_b32 v53, 0xffff0000, v49 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v34.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v13.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v29.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v31.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v15.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-TRUE16-NEXT: v_bfe_u32 v54, v52, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v13.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v12 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX12-TRUE16-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v53, v53, v53 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v30.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v29.l, v13.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v29.l, v13.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v31.l, v12.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v52, v54, v65, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v33.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v30.l, v13.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; GFX12-TRUE16-NEXT: v_add3_u32 v54, v54, v53, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v15.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v52.h, v33.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v49, v54, v55, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v34.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v52 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v12.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v29.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v53, v53, v53 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v34.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v64 -; GFX12-TRUE16-NEXT: v_bfe_u32 v65, v53, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v49 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v64, v65, v53, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v53 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v66 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v28.l, v12.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v28.l, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v53, v64, v65, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v15.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v14.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v31.l, v12.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v28.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v31.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v53.h, v13.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v29.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v55 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v27.l, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v11.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v30.l, v11.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.h, v28.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v53 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v49, v49, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v52.h, v12.h, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v55, v49, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v29 -; GFX12-TRUE16-NEXT: v_add3_u32 v27, v55, v49, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v49 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v54, v52 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v27.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v12.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v26.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v53.h, v11.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v26.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v29, v27, v29, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v13.l, v11.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v29.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v26.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v52 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v51, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v49 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v27, v12, v12 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v31.l, v10.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v28.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v25.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v9.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; GFX12-TRUE16-NEXT: v_add3_u32 v28, v28, v27, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v27.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v12.l, v10.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v9.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v29.h, v9.h, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v52, v49 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v27, v28, v53, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v29, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v26.l, v9.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v27.h, v11.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX12-TRUE16-NEXT: v_add3_u32 v29, v29, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v13.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v25.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v25.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v29, v49, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v10.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v24.l, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v12.h, v10.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v28, v28 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v11.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v13.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v26.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v10, 16, 1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v26 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v52, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v12.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v49 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v24.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v24.h, v9.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v25.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v27.h, v8.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v10.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v8.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v12.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v25.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.h, v9.h, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v27, v10, v10 :: v_dual_and_b32 v26, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v27, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v27 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v23, v25, v27, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v25.l, v8.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v22.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v24.h, v7.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v11.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v11.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v12.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v22.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v25, v8, v8 :: v_dual_lshlrev_b32 v24, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v11.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v22 -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v25, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v11.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v25, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v6.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v22.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v10.l, v7.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.h, v12.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v24, v25, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v25 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v22.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v21, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v11.l, v6.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v11.h, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v10.l, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v11 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v21 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v8, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v9.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v22, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v8, v9, v21 :: v_dual_lshlrev_b32 v9, 16, v22 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v8.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v11.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v6, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v19 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v7.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v12, v20, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_and_b32 v11, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v9.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v10.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v10.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v8.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v18 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v8.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v19, v20, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v20 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v12, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.h, v4.l, s3 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v9.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v6.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v17.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v7.l, v4.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v16.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v12 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v19, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v18.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v8.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v3.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v17 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v12, v16, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v12.h, v3.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v16, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v12, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v8, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v10, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v17, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v10, v17, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v18, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v2.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v7.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v12.h, v1.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v11.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v11, v30 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v5.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v5.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v7.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v3, v50 :: v_dual_mov_b32 v4, v48 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v13 :: v_dual_mov_b32 v1, v30 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v51 :: v_dual_mov_b32 v5, v39 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v37 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v35 :: v_dual_mov_b32 v9, v33 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v32 :: v_dual_mov_b32 v11, v31 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v12, v36 :: v_dual_mov_b32 v13, v34 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v8.l, v1.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v6.l, v0.h, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v9.l, v2.h, s3 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v10, v31 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v32bf16: @@ -17920,1108 +13716,793 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v29 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: scratch_load_b32 v50, off, s32 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v52, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s0 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v39, v64, v55 :: v_dual_and_b32 v70, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v68, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v80, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v84, v83, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v96, v87, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v100, v99, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v112, v103 :: v_dual_and_b32 v81, 0xffff0000, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v116, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v66, v66 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v128, v119, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v0 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v82, v132, v131 :: v_dual_and_b32 v113, 0xffff0000, v21 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v84, v144, v135 :: v_dual_and_b32 v117, 0xffff0000, v20 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v102, v144, v135, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v34, v34 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v147, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v33 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v36, v36, v35, s3 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 +; GFX12-FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v14, v30, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v37, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v51, v51, v52 :: v_dual_lshlrev_b32 v118, 16, v102 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v51 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v51 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v54, v54 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v39, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v49, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v38 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v52 :: v_dual_lshlrev_b32 v118, 16, v67 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v54, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v64 :: v_dual_lshlrev_b32 v128, 16, v83 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v97, v99, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v103, v68, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v39 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v101, v115, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo +; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v113 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v34 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v38 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v49 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v103, v119, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v115, v119, v98, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v71 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v103 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v131, v82, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v86, v114 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v52 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v99 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v113 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v33, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v115 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v48, v116 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v85, 16, v64 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_bfe_u32 v114, v86, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v86 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v55 -; GFX12-FAKE16-NEXT: v_add3_u32 v114, v114, v86, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v48, v48, v48 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v117 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v118 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v66 -; GFX12-FAKE16-NEXT: v_bfe_u32 v118, v48, 16, 1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v49, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v119 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v70 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v102, 16, v80 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v48 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v71, v52, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v128 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v68 -; GFX12-FAKE16-NEXT: v_add3_u32 v118, v118, v48, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v128, v53, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v129 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v82 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v53 -; GFX12-FAKE16-NEXT: v_add3_u32 v128, v128, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v64, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v81, v81, v81 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v81 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v97 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v85, v85, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v96, v130 -; GFX12-FAKE16-NEXT: v_bfe_u32 v146, v85, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v147, 0x400000, v85 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v97, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v98, v131 -; GFX12-FAKE16-NEXT: v_add3_u32 v146, v146, v85, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v101 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v99, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v100, v132 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v96, v96, v96 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v101, v70, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v102, v133 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v98, v98, v98 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v102, v103, v80, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v134 -; GFX12-FAKE16-NEXT: v_bfe_u32 v134, v81, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v100, v100, v100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v82, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 -; GFX12-FAKE16-NEXT: v_bfe_u32 v86, v96, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v134, v134, v81, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v114, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v96 -; GFX12-FAKE16-NEXT: v_add3_u32 v86, v86, v96, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v69, v69, v69 -; GFX12-FAKE16-NEXT: v_bfe_u32 v132, v69, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v133, 0x400000, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v132, v132, v69, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v36, v36, v36 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v116, v36, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v36 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX12-FAKE16-NEXT: v_add3_u32 v116, v116, v36, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v36, v98, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v50, v147, v38 :: v_dual_lshlrev_b32 v49, 16, v52 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v39 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v129, v30, v66 :: v_dual_lshlrev_b32 v30, 16, v35 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v130 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v116, v117, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v98 -; GFX12-FAKE16-NEXT: v_bfe_u32 v48, v100, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v36, v36, v98, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v118, v118, v119 :: v_dual_max_num_f32 v65, v65, v65 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v100 -; GFX12-FAKE16-NEXT: v_add3_u32 v48, v48, v100, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_bfe_u32 v130, v65, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v131, 0x400000, v65 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v30 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v50 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v35, v36, s0 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v37, v34 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v51, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v34, v39, v48, s0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v131 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v54, 16, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v132 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v133 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v128, v129, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_add3_u32 v130, v130, v65, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v134 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v130, v131, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v135 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v132, v133, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v85, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v81 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v97, v144 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v134, v144, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v81 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v101, v145 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v146, v147, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96 -; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v85 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v118 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v114 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v86 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v146 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v117, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v100, v100 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v116 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v128 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v36 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v112, v113, v96 :: v_dual_lshlrev_b32 v49, 16, v117 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v114, v147 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v48, v119, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v114 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v36 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v116 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v116, 0xffff0000, v118 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v119 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v116, v49 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v48, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v128 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v96 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v118, v130 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v37 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v100, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v128, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v115, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v50, v38, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v117, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v36, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v119, v49, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v34, v48, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v128, v52, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v130, v54 :: v_dual_and_b32 v65, 0xffff0000, v65 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v37, v52, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v131, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v147, v32, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v70 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v132, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v80 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v32, v133, v68 :: v_dual_and_b32 v81, 0xffff0000, v81 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v54, v147 :: v_dual_and_b32 v85, 0xffff0000, v85 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v70 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v54 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v144, v70, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v0 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v86 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v96 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v98 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v49, 16, v34 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v133, 16, v69 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v102 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v147 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v102, v102, v102 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v38, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v38, v128, v38 :: v_dual_lshlrev_b32 v135, 16, v85 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v102, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v102 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v34, v68 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v102, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v54, v147, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v48, v52, v51 :: v_dual_lshlrev_b32 v145, 16, v101 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v37, v37, v55 :: v_dual_lshlrev_b32 v34, 16, v34 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v64, v55 :: v_dual_lshlrev_b32 v147, 16, v114 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v34, v34, v34 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v39, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v55, v34, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v51, 16, v128 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83 -; GFX12-FAKE16-NEXT: v_add3_u32 v55, v55, v34, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v52, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v87, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v97 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v31, v97, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v99 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v32, v99, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v98 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v103 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v48, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v71, v86, v103, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v113 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v30 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v100, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v116 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v33, v115, v36 :: v_dual_and_b32 v86, 0xffff0000, v86 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v117 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v48, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v118 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v119 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v117, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v96 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v119, v38, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v16 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v38, v50, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 +; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v128, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v130, v49, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0, v147 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v39, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v130 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v147, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v85 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v48, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v131, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v86 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v132, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v133, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v112 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v67, v51, v51 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v135, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v53, v129 :: v_dual_lshlrev_b32 v55, 16, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v84 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v101 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v101, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v55 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v52 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v52 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v54, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v80 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v66, v80, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v67 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v80, 16, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v15, v31, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v144, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v67, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v103 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v67, 0x7fff +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v50 :: v_dual_lshlrev_b32 v64, 16, v53 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v103, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v68, v53, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v50, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v70, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v31, v53 :: v_dual_lshlrev_b32 v55, 16, v52 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v66, v55, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX12-FAKE16-NEXT: v_add3_u32 v66, v68, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v69, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v67 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v55 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v65, v82 :: v_dual_lshlrev_b32 v70, 16, v55 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v52, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v65 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v70 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v54, v53 :: v_dual_lshlrev_b32 v65, 16, v55 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v55, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v15, v50 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v113 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v113 :: v_dual_lshlrev_b32 v80, 16, v68 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v64 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v70, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v64, v53, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v65, v69, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v14 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v50 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v80, v71 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v65, v50, v68 :: v_dual_lshlrev_b32 v80, 16, v30 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v14, v30, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v65, v65, v65 :: v_dual_max_num_f32 v66, v66, v66 -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v66, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v66 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v66, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v64, v71 :: v_dual_lshlrev_b32 v71, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v65 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v70, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v69 -; GFX12-FAKE16-NEXT: v_bfe_u32 v54, v65, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v67, v53, v67 :: v_dual_lshlrev_b32 v66, 16, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v54, v54, v65, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v70, v66 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v30, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v71, v13, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v29 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v80, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v29, v71, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v67, v55, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v66 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v54 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v66, v13, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v53, v29 :: v_dual_lshlrev_b32 v70, 16, v71 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v68, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v70, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v12 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v71, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v50 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v66, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v50, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v54 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v53, v66, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v50, v50, v53 :: v_dual_max_num_f32 v53, v55, v55 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v53, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v54, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v27 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v66 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v64, v67 :: v_dual_lshlrev_b32 v68, 16, v28 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v28, v12 :: v_dual_lshlrev_b32 v67, 16, v11 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v53, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v129 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v27, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v54, 16, v12 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v53 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v55, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v129, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v30, v71 :: v_dual_lshlrev_b32 v55, 16, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v66 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v67, v64 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v28 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v54, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v53, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v68, v65 :: v_dual_max_num_f32 v55, v55, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v50, v55, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v55 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v50, v55, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0, v129 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v55, v129, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v64 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v65, v26, v10 :: v_dual_lshlrev_b32 v64, 16, v64 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v64, v64, v64 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v30, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v65 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v65 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v30, v12 :: v_dual_lshlrev_b32 v67, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v9 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v67, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v65, v10 :: v_dual_lshlrev_b32 v55, 16, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v53 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v53 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v25 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX12-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v54, v54, v54 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v30, v54, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-FAKE16-NEXT: v_add3_u32 v30, v30, v54, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v54, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX12-FAKE16-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v24, v8 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v50, 16, v50 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v50, v50, v50 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v50, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v50 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v50, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v53, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v26, 16, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_and_b32 v50, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v65 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v53, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v54, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v23, v7 :: v_dual_lshlrev_b32 v55, 16, v6 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v8 :: v_dual_lshlrev_b32 v29, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX12-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX12-FAKE16-NEXT: v_add3_u32 v25, v28, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v53 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v28, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v25 -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v26 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v54, v9 :: v_dual_lshlrev_b32 v64, 16, v6 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; GFX12-FAKE16-NEXT: v_perm_b32 v9, v36, v9, 0x5040100 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v23, v7 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v50, v8 :: v_dual_lshlrev_b32 v55, 16, v22 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v55 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v22, v6 :: v_dual_lshlrev_b32 v54, 16, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v53 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v26, v8 :: v_dual_lshlrev_b32 v25, 16, v22 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v24 :: v_dual_lshlrev_b32 v53, 16, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v50, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v25, v7 :: v_dual_lshlrev_b32 v50, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v21, v5 :: v_dual_lshlrev_b32 v53, 16, v20 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX12-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v30, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v50 :: v_dual_lshlrev_b32 v50, 16, v20 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v50 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX12-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v20, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v19 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v28, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v22 :: v_dual_lshlrev_b32 v53, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v22, v28, v28 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v3 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v30, v22, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v28, v5 :: v_dual_lshlrev_b32 v50, 16, v19 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX12-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21 -; GFX12-FAKE16-NEXT: v_add3_u32 v30, v30, v22, 0x7fff -; GFX12-FAKE16-NEXT: v_perm_b32 v8, v37, v8, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v50 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v19, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v30, v54 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_lshlrev_b32 v30, 16, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v28, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v21, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v24, v3 :: v_dual_lshlrev_b32 v20, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v24, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v21 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v28, 16, v18 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v20, 16, v16 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v18, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v24, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v30, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v17, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v22 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v24, v28, v28 :: v_dual_lshlrev_b32 v25, 16, v25 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v16, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v24, 16, 1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v25, v25, v25 :: v_dual_lshlrev_b32 v22, 16, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19 -; GFX12-FAKE16-NEXT: v_bfe_u32 v50, v25, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v17, v1 :: v_dual_lshlrev_b32 v25, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v19, v22, v22 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v28, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v50, v25, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v19, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v53, v19, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v22 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v50, v53, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 -; GFX12-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v21, v1 :: v_dual_and_b32 v16, 0xffff0000, v22 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX12-FAKE16-NEXT: v_perm_b32 v1, v14, v1, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX12-FAKE16-NEXT: v_perm_b32 v14, v31, v27, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v13, v0, 0x5040100 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-FAKE16-NEXT: v_perm_b32 v13, v32, v26, 0x5040100 -; GFX12-FAKE16-NEXT: v_perm_b32 v2, v15, v2, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX12-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_perm_b32 v15, v39, v29, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <32 x bfloat> @llvm.maximumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) ret <32 x bfloat> %result @@ -19052,23 +14533,13 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; GFX8-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_maximumnum_bf16_no_ieee: @@ -19084,22 +14555,13 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX900-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX900-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v3, v3, v2, s4 -; GFX900-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-LABEL: v_maximumnum_bf16_no_ieee: @@ -19118,9 +14580,6 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX950-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc @@ -19146,21 +14605,13 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_bf16_no_ieee: @@ -19169,39 +14620,31 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_bf16_no_ieee: @@ -19220,26 +14663,14 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_maximumnum_bf16_no_ieee: @@ -19252,45 +14683,37 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_bf16_no_ieee: @@ -19316,29 +14739,17 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y) ret bfloat %result @@ -19376,24 +14787,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -19403,23 +14804,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -19437,23 +14829,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -19463,21 +14846,13 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v2, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -19492,15 +14867,12 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc @@ -19524,12 +14896,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 @@ -19564,37 +14932,21 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v5, v5, v3, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v4, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v4, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -19608,66 +14960,52 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16_no_ieee: @@ -19680,60 +15018,39 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -19751,71 +15068,56 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16_no_ieee: @@ -19833,69 +15135,48 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -19941,24 +15222,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -19968,23 +15239,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -19994,22 +15256,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -20028,23 +15281,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20054,22 +15298,14 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20079,21 +15315,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v4, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -20108,15 +15336,12 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -20140,9 +15365,6 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -20166,12 +15388,8 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 @@ -20186,180 +15404,125 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX10-LABEL: v_maximumnum_v3bf16_no_ieee: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v5, v5 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v0, vcc_lo -; GFX10-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_or_b32_e32 v11, 0x400000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX10-NEXT: v_bfe_u32 v10, v7, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v10, v10, v7, 0x7fff -; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16_no_ieee: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v9, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v10 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16_no_ieee: @@ -20368,88 +15531,59 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_maximumnum_v3bf16_no_ieee: @@ -20460,104 +15594,77 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v9, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v10 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16_no_ieee: @@ -20570,98 +15677,67 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX12-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 @@ -20669,7 +15745,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) ret <3 x bfloat> %result @@ -20719,24 +15795,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -20748,23 +15814,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, s4, v8 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20774,23 +15831,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20800,22 +15848,13 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v3 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -20836,23 +15875,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -20864,22 +15894,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v8, v8, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v7 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20889,22 +15911,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20914,21 +15928,13 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v5, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v4, v1, s4 @@ -20949,11 +15955,8 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v0 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -20977,9 +15980,6 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc @@ -21003,9 +16003,6 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -21019,7 +16016,7 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_perm_b32 v1, v4, v1, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v0 @@ -21029,12 +16026,8 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 -; GFX950-NEXT: v_perm_b32 v1, v4, v1, s0 +; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 ; GFX950-NEXT: s_nop 1 @@ -21076,78 +16069,46 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX10-NEXT: v_bfe_u32 v14, v8, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v7, v4, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v12 -; GFX10-NEXT: v_add3_u32 v12, v14, v8, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v13, vcc_lo -; GFX10-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_bfe_u32 v15, v9, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX10-NEXT: v_add3_u32 v12, v12, v11, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_or_b32_e32 v16, 0x400000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_bfe_u32 v12, v6, 16, 1 -; GFX10-NEXT: v_add3_u32 v14, v15, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_add3_u32 v12, v12, v6, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 @@ -21166,225 +16127,155 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v10, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v9, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo @@ -21409,123 +16300,94 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v10, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v9, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l -; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v11, v11, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee: @@ -21535,126 +16397,80 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6 -; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 @@ -21663,21 +16479,22 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll index 1d3f163c36698..9ea91cd1dea0e 100644 --- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll @@ -33,25 +33,15 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v3, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; GFX8-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_minimumnum_bf16: @@ -66,24 +56,15 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX900-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX900-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v3, v3, v2, s4 -; GFX900-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc ; GFX900-NEXT: s_movk_i32 s4, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-LABEL: v_minimumnum_bf16: @@ -92,7 +73,7 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 ; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v0 @@ -102,10 +83,6 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX950-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc @@ -131,21 +108,13 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_bf16: @@ -154,39 +123,31 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_bf16: @@ -205,26 +166,14 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_minimumnum_bf16: @@ -237,45 +186,37 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_bf16: @@ -301,29 +242,17 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y) ret bfloat %result @@ -539,26 +468,16 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -568,23 +487,14 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -601,25 +511,16 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 +; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -629,21 +530,13 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v2, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -658,16 +551,12 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc @@ -691,9 +580,6 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -731,37 +617,21 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v5, v5, v3, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v4, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v4, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -775,66 +645,52 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16: @@ -847,60 +703,39 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -918,71 +753,56 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16: @@ -1000,69 +820,48 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -1415,26 +1214,16 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -1444,23 +1233,14 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -1470,22 +1250,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -1503,25 +1274,16 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -1531,22 +1293,14 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -1556,21 +1310,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v4, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -1585,16 +1331,12 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -1618,9 +1360,6 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -1644,9 +1383,6 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -1664,180 +1400,125 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX10-LABEL: v_minimumnum_v3bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v5, v5 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v0, vcc_lo -; GFX10-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_or_b32_e32 v11, 0x400000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX10-NEXT: v_bfe_u32 v10, v7, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v10, v10, v7, 0x7fff -; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v9, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v10 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16: @@ -1846,88 +1527,59 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v9 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_minimumnum_v3bf16: @@ -1938,104 +1590,77 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v9, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v10 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16: @@ -2048,98 +1673,67 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v9 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX12-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 @@ -2147,7 +1741,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) ret <3 x bfloat> %result @@ -2603,26 +2197,16 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -2634,23 +2218,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, s4, v8 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -2660,23 +2235,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2686,22 +2252,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v3 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -2721,25 +2278,16 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -2751,22 +2299,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v8, v8, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -2776,22 +2316,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -2801,21 +2333,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v5, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v4, v1, s4 @@ -2831,17 +2355,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v2 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v0 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v2 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -2865,9 +2385,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc @@ -2891,9 +2408,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -2917,9 +2431,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -2964,78 +2475,46 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX10-NEXT: v_bfe_u32 v14, v8, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v7, v4, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v12 -; GFX10-NEXT: v_add3_u32 v12, v14, v8, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v13, vcc_lo -; GFX10-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX10-NEXT: v_bfe_u32 v15, v9, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX10-NEXT: v_add3_u32 v12, v12, v11, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_or_b32_e32 v16, 0x400000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX10-NEXT: v_bfe_u32 v12, v6, 16, 1 -; GFX10-NEXT: v_add3_u32 v14, v15, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_add3_u32 v12, v12, v6, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 @@ -3054,225 +2533,155 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v10, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v9, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo @@ -3297,123 +2706,94 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v10, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v9, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v11, v11, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16: @@ -3423,126 +2803,80 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 @@ -3551,21 +2885,22 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) @@ -4156,26 +3491,16 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v8, v9 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_mul_f32_e32 v8, 1.0, v8 -; GFX8-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v8 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9 -; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v8 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v7 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v8 +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v8 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 @@ -4187,23 +3512,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v9, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s4, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v8 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 ; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 @@ -4215,23 +3531,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s4, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v9 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc @@ -4241,23 +3548,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s4, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc @@ -4267,23 +3565,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v9, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v9, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9 -; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v5 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -4293,22 +3582,13 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v8 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v7 @@ -4331,25 +3611,16 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v8, v9 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX900-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX900-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v9, v9, v8, s4 -; GFX900-NEXT: v_or_b32_e32 v10, 0x400000, v8 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v8 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v7 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 +; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v8 +; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v8 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 @@ -4361,22 +3632,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v9, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s4 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v8 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 +; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc -; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 ; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v3 ; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 @@ -4388,22 +3651,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v9 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc @@ -4413,22 +3668,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s4 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 +; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc @@ -4438,22 +3685,14 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v9, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v9, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v9, v9, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v10, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v5 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -4463,21 +3702,13 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v8, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v7, v1, s4 @@ -4492,21 +3723,17 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX950-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 -; GFX950-NEXT: v_and_b32_e32 v10, 0xffff0000, v4 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v6 -; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 +; GFX950-NEXT: v_and_b32_e32 v10, 0xffff0000, v4 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v7 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v8, v9 ; GFX950-NEXT: v_lshrrev_b32_e32 v9, 16, v1 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v8, v8, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc @@ -4531,9 +3758,6 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc @@ -4557,9 +3781,6 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc @@ -4583,9 +3804,6 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc @@ -4609,9 +3827,6 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v9, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -4635,9 +3850,6 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc @@ -4663,156 +3875,108 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v1 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 ; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v3 ; GFX10-NEXT: v_cndmask_b32_sdwa v12, v2, v7, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v15, v14, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v6, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v14, v8, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v17 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v9, v6, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_bfe_u32 v16, v10, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v16, v16, v10, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8 -; GFX10-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v13 -; GFX10-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v14, v8, v11, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_bfe_u32 v18, v14, 16, 1 -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v14, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v8, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_add3_u32 v9, v18, v14, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v0 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v10 -; GFX10-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v3, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX10-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX10-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v11, v14, v13, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_bfe_u32 v17, v10, 16, 1 -; GFX10-NEXT: v_add3_u32 v13, v16, v12, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_add3_u32 v16, v17, v10, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v17, 0x400000, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v16, v17, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v15, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v10 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo ; GFX10-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -4820,165 +3984,126 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v1.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.h, v6.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v9.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v14, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s3 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v8.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v7.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14 -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v14, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v14, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s5, v13, v18 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s4 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v16, v20, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v19, v22, s6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v6.l, s0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v7.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v10.l, s5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v9.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v8 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v2.l, s0 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s2 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v7.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v3.h, v10.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v9.l, v8.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v13.l, v8.l, s3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v7 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v14 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v14, v6, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v16, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v4.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v12 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v1.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v8, v12, v14, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s1 -; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v12, v15, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v10, v14, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v4.l, v1.l, s1 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v0.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v3.h, s2 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v6bf16: @@ -4987,176 +4112,116 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_and_b32 v8, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v7 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v10, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v11 :: v_dual_max_f32 v9, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v14, v11 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v16, v18, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v15, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v14 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v15, v8 :: v_dual_lshlrev_b32 v17, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v18, v6 :: v_dual_lshlrev_b32 v9, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v13, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v8, v10, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v16, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v5, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v8 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v3, v0 :: v_dual_lshlrev_b32 v10, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v16, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add3_u32 v16, v17, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v16, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v15, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v13, v0 :: v_dual_and_b32 v5, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v4, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v1, v7, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -5168,191 +4233,143 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v1.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.h, v6.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v9.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v14, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s3 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v8.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v7.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.h, v10.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v14, v14, v14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14 -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v14, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v14, v14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s5, v13, v18 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s4 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v16, v20, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v19, v22, s6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v6.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v7.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v10.l, s5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v9.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v3.h, s2 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v8 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v7.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v3.h, v10.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v2.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v9.l, v8.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v6.l, s2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v14 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v14, v6, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v16, v7, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v13.l, v8.l, s3 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v4.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v16 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v12 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v1.h, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v8, v12, v14, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v12, v15, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v7 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v12.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v10, v14, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v4.l, v1.l, s1 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v8.h, v2.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v3.h, s2 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v6bf16: @@ -5365,211 +4382,147 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_and_b32 v8, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v7 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v10, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v11 :: v_dual_max_num_f32 v9, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v14, v11 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v16, v18, v12, 0x7fff -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v15, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v15, v8 :: v_dual_lshlrev_b32 v17, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v18, v6 :: v_dual_lshlrev_b32 v9, 16, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v13, v13, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v14 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v8, v10, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v16, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v5, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v8 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v3, v0 :: v_dual_lshlrev_b32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX12-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v9, v9, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v16, v10, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v16, v17, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v16, v17, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v15, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v11 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v13, v0 :: v_dual_and_b32 v5, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_and_b32 v4, 0xffff0000, v10 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: v_perm_b32 v1, v7, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <6 x bfloat> @llvm.minimumnum.v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) @@ -5644,26 +4597,16 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: s_movk_i32 s5, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s5, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 +; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v6 ; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 @@ -5675,23 +4618,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v10 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v11, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_mul_f32_e32 v11, 1.0, v11 -; GFX8-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s5, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 @@ -5703,23 +4637,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v12, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s5, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 @@ -5731,23 +4656,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v13, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; GFX8-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, s5, v14 -; GFX8-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc @@ -5757,23 +4673,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s5, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc @@ -5783,23 +4690,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v12, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v7 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s5, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v7 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc @@ -5809,23 +4707,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s5, v7 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -5835,22 +4724,13 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s5, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v10 @@ -5875,25 +4755,16 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v9 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v6 ; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 @@ -5905,22 +4776,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v10 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v11, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX900-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX900-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v11, s4 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v10 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 +; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc -; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v5 ; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 @@ -5932,22 +4795,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v12, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s4 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v11 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 +; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 @@ -5959,22 +4814,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v12 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v13, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX900-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX900-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX900-NEXT: v_add3_u32 v14, v14, v13, s4 -; GFX900-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v14, 16, v13 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v12 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 +; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc -; GFX900-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc @@ -5984,22 +4831,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s4 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v7 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v7 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc @@ -6009,22 +4848,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v12, v7 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v12, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v7 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 +; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc @@ -6034,22 +4865,14 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -6059,21 +4882,13 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v11, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v10, v1, s4 @@ -6089,23 +4904,20 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v3 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 ; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX950-NEXT: v_and_b32_e32 v12, 0xffff0000, v6 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; GFX950-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 +; GFX950-NEXT: v_and_b32_e32 v12, 0xffff0000, v6 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v9 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v10, v11 ; GFX950-NEXT: v_lshrrev_b32_e32 v11, 16, v2 -; GFX950-NEXT: v_and_b32_e32 v14, 0xffff0000, v4 +; GFX950-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v8 -; GFX950-NEXT: s_nop 1 +; GFX950-NEXT: v_and_b32_e32 v14, 0xffff0000, v4 +; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v9 ; GFX950-NEXT: s_nop 1 @@ -6128,9 +4940,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX950-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v11, v11, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc @@ -6155,9 +4964,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc @@ -6181,9 +4987,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v13, v14 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX950-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v13, v13, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc @@ -6207,9 +5010,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc @@ -6233,9 +5033,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v12, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc @@ -6259,9 +5056,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -6285,9 +5079,6 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc @@ -6310,213 +5101,149 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v3 ; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v6 +; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v8 +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v5 -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX10-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX10-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v22, v19, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_max_f32_e32 v15, v16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX10-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v15 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX10-NEXT: v_add3_u32 v19, v19, v15, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v20 -; GFX10-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 +; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v11, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX10-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_add3_u32 v13, v13, v17, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v11, v14, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v9, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v16, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v12, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v12, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v1 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 -; GFX10-NEXT: v_max_f32_e32 v11, v15, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; GFX10-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX10-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v6, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX10-NEXT: v_bfe_u32 v17, v14, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_add3_u32 v17, v17, v14, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v18, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX10-NEXT: v_max_f32_e32 v16, v16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX10-NEXT: v_or_b32_e32 v20, 0x400000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX10-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX10-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX10-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX10-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX10-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -6524,458 +5251,321 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.h, v6.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v7.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v9.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v1.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v9.l, v8.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v15, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v5.h, v12.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v13, v18 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v14.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v11.l, v10.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v4.h, v13.l, s2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v16, v16 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v17, v18 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v10.l, v8.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v9.l, s3 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v15.l, v12.l, s2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, v19, v22, s2 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v20 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v16, v16, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v19.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v13.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v18, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.l, v13.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v19.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v11.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v15.l, v9.l, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v10.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.h, v11.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v13.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v15.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.h, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v12.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v15.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v9, v18, s2 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v16, v12 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v17.h, v8.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v10.h, v13.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v13, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v12.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v14.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v8.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v16, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v8.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v13 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v13, 0x7fff +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v15, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v12, v12, v12 :: v_dual_max_f32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v14, v16, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v2.l, s3 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v0.h, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v14, v15, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v16, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.h, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v6.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v14 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v15 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v1.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v3.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v4.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v1.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v9 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v8 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v8bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v10 :: v_dual_lshlrev_b32 v11, 16, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_and_b32 v16, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v12 :: v_dual_and_b32 v15, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v22, v19 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v15, v16, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v15 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v17, v8 :: v_dual_and_b32 v15, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v17, 16, v17 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v17, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v14 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v18 :: v_dual_lshlrev_b32 v15, 16, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v11, v15, v15 :: v_dual_lshlrev_b32 v18, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v14, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v14, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v18 :: v_dual_lshlrev_b32 v16, 16, v16 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v16, v16, v16 :: v_dual_and_b32 v13, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v14 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -6988,260 +5578,200 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.h, v6.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v7.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v9.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v1.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v9.l, v8.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v12.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v15, v17 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v5.h, v12.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v13, v18 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v14.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v10.l, v8.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v11.l, v10.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v9.l, s3 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v4.h, v13.l, s2 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v16, v16 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v17, v18 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v15.l, v12.l, s2 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v17, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v19, v19, v22, s2 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v20 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v16, v16, v16 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v19.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v13.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v15.l, v9.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.h, v11.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v18, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX12-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.h, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v13.l, v8.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.l, v13.l, s2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v19.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v11.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v15.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.h, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v12.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v10, v10, v10 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v10.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v15.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v12.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v8.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v14 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v9, v18, s2 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v16, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v17.h, v8.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v10.h, v13.l, s3 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v13, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v8.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v9, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v16, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v14 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v13, v13, v13 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v14, v14 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v0.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v15, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v14, v14, v13, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v12, v12, v12 :: v_dual_max_num_f32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v14, v16, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v2.l, s3 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v0.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v14, v15, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v16, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v6.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v14 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v3.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v1.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v4.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v1.h, s3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v13.h, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v7.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v9 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v8 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -7252,256 +5782,170 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v14, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v10 :: v_dual_lshlrev_b32 v11, 16, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v11, v11, v11 :: v_dual_and_b32 v16, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v22, v11, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v11 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v12 :: v_dual_and_b32 v15, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v22, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v22, v19 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v15, v16, v16 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v21, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX12-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v15 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v17, v8 :: v_dual_and_b32 v15, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v20 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v16, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v17, 16, v17 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v17, v17, v17 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v19, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_bfe_u32 v13, v17, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_add3_u32 v13, v13, v17, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v14 :: v_dual_lshlrev_b32 v15, 16, v7 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v18 :: v_dual_lshlrev_b32 v15, 16, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v11, v15, v15 :: v_dual_lshlrev_b32 v18, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v14, v14, v14 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v17, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v15, v16, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v14, 16, 1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v5, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v17, v14, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v18 :: v_dual_lshlrev_b32 v16, 16, v16 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v16, v16, v16 :: v_dual_and_b32 v13, 0xffff0000, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v4, v0, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v13, v13, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v19, v16, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v14 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo @@ -7510,25 +5954,26 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v15, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <8 x bfloat> @llvm.minimumnum.v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) @@ -7653,26 +6098,16 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v16 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v18, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX8-NEXT: v_mul_f32_e32 v18, 1.0, v18 -; GFX8-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v18 -; GFX8-NEXT: s_movk_i32 s5, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v19, vcc, s5, v19 -; GFX8-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18 +; GFX8-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v6 @@ -7684,23 +6119,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v19, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_mul_f32_e32 v19, 1.0, v19 -; GFX8-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, s5, v20 -; GFX8-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v5 @@ -7712,23 +6138,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v18 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v20, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX8-NEXT: v_mul_f32_e32 v20, 1.0, v20 -; GFX8-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v20 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, s5, v21 -; GFX8-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v21, v18, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v12 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v4 @@ -7740,23 +6157,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v21, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX8-NEXT: v_mul_f32_e32 v21, 1.0, v21 -; GFX8-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, s5, v22 -; GFX8-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v22, v19, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v11 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v3 @@ -7768,23 +6176,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v20 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v22, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX8-NEXT: v_mul_f32_e32 v22, 1.0, v22 -; GFX8-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v22 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, s5, v23 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v23, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v10 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v2 @@ -7796,23 +6195,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v23, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX8-NEXT: v_mul_f32_e32 v23, 1.0, v23 -; GFX8-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s5, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v24, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v9 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v1 @@ -7824,23 +6214,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v24, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s5, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v25, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v8 ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v0 @@ -7852,23 +6233,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v23 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v25, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX8-NEXT: v_mul_f32_e32 v25, 1.0, v25 -; GFX8-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, s5, v26 -; GFX8-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc @@ -7878,23 +6250,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s5, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v15 ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc @@ -7904,23 +6267,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v24, v15 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_mul_f32_e32 v15, 1.0, v15 -; GFX8-NEXT: v_bfe_u32 v24, v15, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v15 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s5, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v15 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v15 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v14 ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc @@ -7930,23 +6284,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v5 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v15, v14 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_mul_f32_e32 v14, 1.0, v14 -; GFX8-NEXT: v_bfe_u32 v15, v14, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v15, vcc, v15, v14 -; GFX8-NEXT: v_add_u32_e32 v15, vcc, s5, v15 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v14 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v13 ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc @@ -7956,23 +6301,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v14, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; GFX8-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, s5, v14 -; GFX8-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc @@ -7982,23 +6318,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, 1.0, v12 -; GFX8-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, s5, v13 -; GFX8-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc @@ -8008,23 +6335,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v12, v11 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_mul_f32_e32 v11, 1.0, v11 -; GFX8-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s5, v12 -; GFX8-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc @@ -8034,23 +6352,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v11, v10 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, 1.0, v10 -; GFX8-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, s5, v11 -; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc @@ -8060,22 +6369,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, 1.0, v9 -; GFX8-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s5, v10 -; GFX8-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v23 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v22 @@ -8108,25 +6408,16 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v16 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v18, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX900-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX900-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX900-NEXT: s_movk_i32 s5, 0x7fff -; GFX900-NEXT: v_add3_u32 v19, v19, v18, s5 -; GFX900-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc ; GFX900-NEXT: s_movk_i32 s4, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v18 +; GFX900-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc -; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX900-NEXT: v_lshrrev_b32_e32 v17, 16, v14 ; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v6 @@ -8138,22 +6429,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v19, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX900-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX900-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX900-NEXT: v_add3_u32 v20, v20, v19, s5 -; GFX900-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc -; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v5 @@ -8165,22 +6448,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v18 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v20, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX900-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX900-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX900-NEXT: v_add3_u32 v21, v21, v20, s5 -; GFX900-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v21, v18, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v12 ; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v4 @@ -8192,22 +6467,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v21, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX900-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX900-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX900-NEXT: v_add3_u32 v22, v22, v21, s5 -; GFX900-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v22, v19, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v11 ; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v3 @@ -8219,22 +6486,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v20 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v22, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX900-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX900-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX900-NEXT: v_add3_u32 v23, v23, v22, s5 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v23, v20, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v10 ; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v2 @@ -8246,22 +6505,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v23, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX900-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX900-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v23, s5 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v24, v21, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v9 ; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v1 @@ -8273,22 +6524,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v24, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s5 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v25, v22, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v8 ; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v0 @@ -8300,22 +6543,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v23 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v25, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX900-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX900-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX900-NEXT: v_add3_u32 v26, v26, v25, s5 -; GFX900-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX900-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX900-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc @@ -8325,22 +6560,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s5 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX900-NEXT: v_and_b32_e32 v15, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v15 ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc @@ -8350,22 +6577,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v24, v15 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX900-NEXT: v_max_f32_e32 v15, v15, v15 -; GFX900-NEXT: v_bfe_u32 v24, v15, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v15, s5 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v15 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v15 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX900-NEXT: v_and_b32_e32 v14, 0xffff0000, v15 +; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v14 ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc @@ -8375,22 +6594,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v5 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v15, v14 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX900-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX900-NEXT: v_bfe_u32 v15, v14, 16, 1 -; GFX900-NEXT: v_add3_u32 v15, v15, v14, s5 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v14 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v15, v24, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v15, 16, v14 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX900-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v13 ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc @@ -8400,22 +6611,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v14, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX900-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX900-NEXT: v_bfe_u32 v14, v13, 16, 1 -; GFX900-NEXT: v_add3_u32 v14, v14, v13, s5 -; GFX900-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v14, 16, v13 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX900-NEXT: v_and_b32_e32 v12, 0xffff0000, v13 +; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v13 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc @@ -8425,22 +6628,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX900-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX900-NEXT: v_bfe_u32 v13, v12, 16, 1 -; GFX900-NEXT: v_add3_u32 v13, v13, v12, s5 -; GFX900-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v12 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v12 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v11 ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc @@ -8450,22 +6645,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v12, v11 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX900-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX900-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX900-NEXT: v_add3_u32 v12, v12, v11, s5 -; GFX900-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v11 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v10 ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc @@ -8475,22 +6662,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v11, v10 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX900-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX900-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX900-NEXT: v_add3_u32 v11, v11, v10, s5 -; GFX900-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v10 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v10 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 ; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc @@ -8500,21 +6679,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX900-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX900-NEXT: v_bfe_u32 v10, v9, 16, 1 -; GFX900-NEXT: v_add3_u32 v10, v10, v9, s5 -; GFX900-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v9 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v9 +; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v9 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v23, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v22, v1, s4 @@ -8534,33 +6705,29 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v18, 16, v7 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 ; GFX950-NEXT: v_and_b32_e32 v19, 0xffff0000, v15 -; GFX950-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; GFX950-NEXT: v_and_b32_e32 v21, 0xffff0000, v13 +; GFX950-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 ; GFX950-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v17 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v18, v19 ; GFX950-NEXT: v_lshrrev_b32_e32 v19, 16, v6 -; GFX950-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 +; GFX950-NEXT: v_and_b32_e32 v21, 0xffff0000, v13 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX950-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v18, v18, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v16 +; GFX950-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 ; GFX950-NEXT: v_and_b32_e32 v23, 0xffff0000, v11 -; GFX950-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 ; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v17 +; GFX950-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 ; GFX950-NEXT: v_and_b32_e32 v25, 0xffff0000, v9 -; GFX950-NEXT: v_and_b32_e32 v26, 0xffff0000, v8 ; GFX950-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX950-NEXT: v_and_b32_e32 v17, 0xffff0000, v6 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_and_b32_e32 v26, 0xffff0000, v8 ; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v18, 16, v14 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 @@ -8575,9 +6742,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v20, 16, v5 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v17, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX950-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v19, v19, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v17 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc @@ -8602,9 +6766,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v21, 16, v4 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v18, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX950-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v20, v20, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v18 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc @@ -8629,9 +6790,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v22, 16, v3 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v19, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX950-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v21, v21, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v19 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc @@ -8656,9 +6814,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v23, 16, v2 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v20, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX950-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v22, v22, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v20 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc @@ -8683,9 +6838,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v24, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v21, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX950-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v23, v23, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v21 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc @@ -8710,9 +6862,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v25, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v22, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v22 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc @@ -8736,9 +6885,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v25, v26 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v23, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX950-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v25, v25, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v23 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc @@ -8762,9 +6908,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc @@ -8788,9 +6931,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v24, v15 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX950-NEXT: v_max_f32_e32 v15, v15, v15 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v15, v15, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc @@ -8814,9 +6954,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v15, v14 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX950-NEXT: v_max_f32_e32 v14, v14, v14 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v14, v14, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc @@ -8840,9 +6977,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v14, v13 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX950-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v13, v13, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc @@ -8866,9 +7000,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v13, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX950-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v12, v12, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc @@ -8892,9 +7023,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v12, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX950-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v11, v11, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc @@ -8918,9 +7046,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v11, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX950-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v10, v10, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc @@ -8944,9 +7069,6 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v10, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX950-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v9, v9, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc @@ -8977,881 +7099,634 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v14 ; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 +; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v17 ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 ; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_max_f32_e32 v18, v18, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_bfe_u32 v23, v18, 16, 1 ; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v19 -; GFX10-NEXT: v_add3_u32 v23, v23, v18, 0x7fff +; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v18 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v18 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v24, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v27 -; GFX10-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v29, v28, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v24, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v21 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v28 -; GFX10-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v24, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v30, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX10-NEXT: v_max_f32_e32 v19, v21, v21 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX10-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v26 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v29 -; GFX10-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v27, 0x400000, v19 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_max_f32_e32 v22, v23, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX10-NEXT: v_bfe_u32 v28, v22, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v30 -; GFX10-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v23, v27, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v11 +; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v25, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v29 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v24, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX10-NEXT: v_max_f32_e32 v24, v25, v25 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 -; GFX10-NEXT: v_bfe_u32 v29, v24, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v33, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v20, v26, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v31 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX10-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_max_f32_e32 v26, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX10-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 -; GFX10-NEXT: v_add3_u32 v22, v22, v26, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v21, v27, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v31, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v29, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v7, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v31 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v33, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v26, v23, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v27, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX10-NEXT: v_max_f32_e32 v27, v7, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v21, v23, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 -; GFX10-NEXT: v_bfe_u32 v23, v27, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v28, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31 -; GFX10-NEXT: v_add3_u32 v23, v23, v27, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v15, v33, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v22, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v25, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v14 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v6, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v26, v21, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v5 -; GFX10-NEXT: v_add3_u32 v22, v22, v24, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v21, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v5, v13, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v7 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v31, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v14, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v26, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX10-NEXT: v_max_f32_e32 v23, v24, v24 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v33, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v13, v27, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v15, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_bfe_u32 v21, v23, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_add3_u32 v21, v21, v23, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v6 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v28, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v12 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v26, v15, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v25, v24, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v12, v4, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v22, v25, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 +; GFX10-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX10-NEXT: v_or_b32_e32 v30, 0x400000, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v25, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX10-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v5, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 -; GFX10-NEXT: v_add3_u32 v26, v26, v24, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v25, v27, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v27, v13, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v11, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v30, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v22, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v25, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_bfe_u32 v23, v21, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX10-NEXT: v_add3_u32 v23, v23, v21, 0x7fff -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v24 +; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v24 -; GFX10-NEXT: v_or_b32_e32 v24, 0x400000, v21 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v10 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v23, v24, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v25 -; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v21 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v23 -; GFX10-NEXT: v_max_f32_e32 v24, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v8, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX10-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v11, v23, v23 -; GFX10-NEXT: v_add3_u32 v23, v26, v24, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX10-NEXT: v_bfe_u32 v29, v11, 16, 1 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v29, 0x400000, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX10-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_perm_b32 v6, v17, v14, 0x5040100 -; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_perm_b32 v5, v18, v13, 0x5040100 -; GFX10-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_perm_b32 v7, v16, v15, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX10-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_v16bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v20, v5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v18, v5 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v14 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.h, v15.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v15.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, s0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v21 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v7.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.h, v13.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v16.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v19.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v4.h, v12.h, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v18.h, v13.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v23, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v23, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v25, v26 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v26, v27, v28, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v22.l, v19.l, s2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v26.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v6.l, v5.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v25, v27, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.h, v21.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v7.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v20.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v26.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.h, v16.l, s0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX11-TRUE16-NEXT: v_add3_u32 v16, v27, v23, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v26 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v24.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v23, v16, v27, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v21.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v3.h, v11.h, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v23.h, v19.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v11.h, v16.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v23 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v28, v19, v19 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v2.h, v10.h, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v10.h, v19.l, s0 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v28 -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v7.l, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v22.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v24, v25 :: v_dual_lshlrev_b32 v27, 16, v27 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v28, v28 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v21.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v26, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v19.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v26, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v9.h, v23.l, s0 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l -; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v26, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v21.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v24.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.h, v5.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v26, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v25, v25, v27, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v28 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v25.h, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v21.l, v23.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v8.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v28, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v19.l, v7.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v19.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v24.h, v19.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v19, v26, v26 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v7.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v19, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v19 -; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v19, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v19, v19 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v15 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v22, v22, v30, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v29 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v22.h, v23.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v21.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v18.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v25.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v18.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.h, v21.l, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v24.h, v16.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v14 -; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v17.l, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_add3_u32 v17, v27, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v22.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.l, v18.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v25 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v4.h, v12.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v11 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v22.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v3.h, v11.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v23.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v26, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v19.l, v22.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v11.h, v20.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v5.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v5.l, s0 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v13.l, vcc_lo +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v10.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v14.l, v16.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-TRUE16-NEXT: v_add3_u32 v20, v22, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v13.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, v20, v22, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v18.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v17.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v21, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v20.h, v18.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v21.l, v20.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v20.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v13.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v15, v22, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v22 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v12.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v17, v17, v17 :: v_dual_lshlrev_b32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.h, v5.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v15.h, v16.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v12.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v21, v23, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v12.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, v21, v22, s0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v21.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v19.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v9.h, v23.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.l, v21.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v22.l, v19.l, vcc_lo +; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v0.h, v8.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v5.l, v23.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v19.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v21.l, v23.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v15 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v20.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.l, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v7.l, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v19.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s0 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v13, v21, v21 :: v_dual_lshlrev_b32 v22, 16, v10 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v14.l, s1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v13, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v20, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, v23, v24, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v20.h, v4.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v19.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v17.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v16.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v5.l, vcc_lo ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v9.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v15 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v13, v13, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.l, v16.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v13.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v13.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v16.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v16.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v14.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v6.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.l, v15.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v12.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.l, v4.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v10.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v12.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v15 -; GFX11-TRUE16-NEXT: v_add3_u32 v15, v23, v13, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v21, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v8.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, v17, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v15.h, v3.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v17, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v8.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v12.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v17 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, v12, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v13, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v13, v21, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v22, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v11.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v9.h, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v15.h, v1.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v20.h, v0.h, s3 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.l, v1.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v10.l, v0.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v13.l, v2.h, s3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v18 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v14 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v16 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v19 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v16bf16: @@ -9861,449 +7736,304 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v15 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v13 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v19, v20 :: v_dual_lshlrev_b32 v18, 16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v18, v18, v18 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v18 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v25, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v27, 16, v22 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v27 -; GFX11-FAKE16-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v29, v28 :: v_dual_and_b32 v18, 0xffff0000, v18 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v27, 16, v25 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v19 :: v_dual_lshlrev_b32 v28, 16, v24 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v28 -; GFX11-FAKE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v24, v25 :: v_dual_and_b32 v28, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v26 :: v_dual_lshlrev_b32 v21, 16, v27 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v30, v29 :: v_dual_and_b32 v27, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v18, v19 :: v_dual_lshlrev_b32 v28, 16, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v19, v21, v21 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v29, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v29 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v22, v23, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v22, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX11-FAKE16-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v30 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v29, v23, v27 :: v_dual_and_b32 v30, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v28 :: v_dual_lshlrev_b32 v25, 16, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v28 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v24 :: v_dual_max_f32 v24, v25, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v20, v26 :: v_dual_lshlrev_b32 v31, 16, v25 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v31 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v32, v31 :: v_dual_lshlrev_b32 v29, 16, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v26, v29, v29 :: v_dual_lshlrev_b32 v33, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v28 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v29 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v21, v27 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v31, v32 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v29, v30 :: v_dual_lshlrev_b32 v32, 16, v15 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v23 :: v_dual_and_b32 v22, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v31 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v28 :: v_dual_lshlrev_b32 v32, 16, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v15, v7 :: v_dual_lshlrev_b32 v31, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v25 :: v_dual_lshlrev_b32 v28, 16, v28 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v25, v28, v28 :: v_dual_lshlrev_b32 v32, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v27, v23, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v27, v27, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v27, v30, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v14, v6 :: v_dual_lshlrev_b32 v28, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v25 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v28, v7 :: v_dual_lshlrev_b32 v30, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v29 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v13, v5 :: v_dual_lshlrev_b32 v29, 16, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v27, v27 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v24, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v15, v15, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v26, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v28, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v27 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v12, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_lshlrev_b32 v29, 16, v3 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v14, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v24 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v14, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX11-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v27, v27, v14, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v26, v5 :: v_dual_lshlrev_b32 v28, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v11, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v27, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX11-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v26, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v2 :: v_dual_lshlrev_b32 v25, 16, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v13, v13, v13 :: v_dual_lshlrev_b32 v26, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-FAKE16-NEXT: v_add3_u32 v14, v24, v13, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v27, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v14, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v14 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v26, v26 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v8, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v27, v3 :: v_dual_lshlrev_b32 v14, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_max_f32_e32 v11, v14, v14 -; GFX11-FAKE16-NEXT: v_add3_u32 v14, v26, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v26, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v15 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 ; GFX11-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -10315,534 +8045,406 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6 -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v20, v5 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v18, v5 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v15 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v14 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.h, v15.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v15.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.h, v14.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v18 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v21 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v7.l, vcc_lo +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.h, v13.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v18.h, v13.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v16.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v6.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v19.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v13.h, v20.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v4.h, v12.h, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v23, v23, v23 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v24, v24, v24 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v23, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v27, v27, v23, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v25, v26 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v26, v27, v28, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v22.l, v19.l, s2 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX12-TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v26.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v26 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v19.l, v7.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v19.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.l, v7.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v24, v25, v27, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v12.h, v21.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v23, v23, v23 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v7.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v26.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v4.h, v12.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.h, v16.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX12-TRUE16-NEXT: v_add3_u32 v16, v27, v23, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v26 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v19.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v24.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v23, v16, v27, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v21.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v3.h, v11.h, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.h, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v23.h, v19.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v11.h, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v6.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v23 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v28, v19, v19 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v22.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v2.h, v10.h, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v3.h, v11.h, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v23.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v26, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v19.l, v22.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v10.h, v19.l, s0 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v28 -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v7.l, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v22.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v24, v24, v25 :: v_dual_lshlrev_b32 v27, 16, v27 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v28, v28 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v11.h, v20.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v5.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.h, v21.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v5.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v26, v21, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v19.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v5.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v19.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v26, 16, 1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v10.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v9.h, v23.l, s0 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l -; GFX12-TRUE16-NEXT: v_add3_u32 v25, v25, v26, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v21.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v21.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v24.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v23.h, v5.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v26, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v25, v25, v27, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v28 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v20.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v22.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v25.h, v16.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v1.h, v9.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v21.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v21.l, v23.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v19.l, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v8.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v28, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v19.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v9.h, v23.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v20.l, v21.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v25 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v23.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v22.l, v19.l, vcc_lo +; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v24.h, v19.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v19, v26, v26 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v7.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v7.l, v6.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v20.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v19, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v18 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v19 -; GFX12-TRUE16-NEXT: v_add3_u32 v22, v22, v19, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v19, v19 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v15 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v24 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v0.h, v8.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v22, v22, v30, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v5.l, v23.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v15.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v29 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.h, v19.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v22.h, v23.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v21.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v21.l, v23.l, s0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v19.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v15 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v20.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v18.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v25.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v18.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.h, v21.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v24.h, v16.l, s1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.l, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v7.l, v19.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v19.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v14 -; GFX12-TRUE16-NEXT: v_bfe_u32 v27, v21, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v23 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v17.l, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_add3_u32 v17, v27, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v22.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v15.l, v18.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v14.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v19.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v25 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v17.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v6.l, v16.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v5.l, vcc_lo ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v21, v21 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v13.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v21, 16, 1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v13 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v14.l, v16.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.l, v16.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-TRUE16-NEXT: v_add3_u32 v20, v22, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v13.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v13.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v20, v20, v22, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v18.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v14.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v17.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v21, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v13.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v16.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v20.h, v18.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v15.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v13.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v16.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v15.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v15, v22, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v22 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v12.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v17, v17, v17 :: v_dual_lshlrev_b32 v22, 16, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v14.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v15.h, v16.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v12.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v21, v23, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v12.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v6.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v17, v21, v22, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v15 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v6.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v13, v21, v21 :: v_dual_lshlrev_b32 v22, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v17.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX12-TRUE16-NEXT: v_add3_u32 v23, v23, v13, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v13 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v15.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v20, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.l, v15.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v20, v23, v24, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v12.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.l, v4.h, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v20.h, v4.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v10.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v9.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v15 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v13, v13, v13 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v12.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_bfe_u32 v23, v13, 16, 1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v15 -; GFX12-TRUE16-NEXT: v_add3_u32 v15, v23, v13, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v21, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v4.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v8.l, v0.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, v17, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v15.h, v3.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v17, v21, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v8.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v12.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v17 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, v12, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v13, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v3 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v13, v21, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v22, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v11.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v11.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v9.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v15.h, v1.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v20.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.l, v1.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v10.l, v0.h, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v13.l, v2.h, s3 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v14 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v18 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v14 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v16 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v19 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v16bf16: @@ -10856,557 +8458,399 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) { ; GFX12-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v15 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v13 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v19, v20 :: v_dual_lshlrev_b32 v18, 16, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v18, v18, v18 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX12-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v21, v21, v21 -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v18 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v25, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v25, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v27, 16, v22 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v27 -; GFX12-FAKE16-NEXT: v_add3_u32 v17, v26, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v22, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v25, v29, v28 :: v_dual_and_b32 v18, 0xffff0000, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v24, v16 :: v_dual_lshlrev_b32 v27, 16, v25 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_and_b32 v26, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v19 :: v_dual_lshlrev_b32 v28, 16, v24 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v28 -; GFX12-FAKE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v24, v25 :: v_dual_and_b32 v28, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v26 :: v_dual_lshlrev_b32 v21, 16, v27 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v30, v29 :: v_dual_and_b32 v27, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v18, v19 :: v_dual_lshlrev_b32 v28, 16, v26 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v19, v21, v21 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v29, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v18, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v29, 16, v21 -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v19, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v29 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v27, v19, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v21, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v23, v27, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v31, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v22, v23, v23 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v30, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v22, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v20, v25, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v23 -; GFX12-FAKE16-NEXT: v_add3_u32 v25, v28, v22, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v22 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v27 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v26 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v29, v23, v27 :: v_dual_and_b32 v30, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v28 :: v_dual_lshlrev_b32 v25, 16, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v32, v31, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v28 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v20, v24 :: v_dual_max_num_f32 v24, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v22 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v31, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 -; GFX12-FAKE16-NEXT: v_bfe_u32 v29, v24, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v20, v26 :: v_dual_lshlrev_b32 v31, 16, v25 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v26, v21, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v31 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: v_add3_u32 v26, v29, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v25, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v32, v31 :: v_dual_lshlrev_b32 v29, 16, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v26, v29, v29 :: v_dual_lshlrev_b32 v33, 16, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v31, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX12-FAKE16-NEXT: v_bfe_u32 v22, v26, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v26 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v29 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v21, v27 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v31, v32 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v31, v29, v30 :: v_dual_lshlrev_b32 v32, 16, v15 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v27, v23, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v23 :: v_dual_and_b32 v22, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v31 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v28 :: v_dual_lshlrev_b32 v32, 16, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v26, v26, v26 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v28, v15, v7 :: v_dual_lshlrev_b32 v31, 16, v6 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v25 :: v_dual_lshlrev_b32 v28, 16, v28 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v26 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v25, v28, v28 :: v_dual_lshlrev_b32 v32, 16, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v27, v23, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v25, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v27, v27, v25, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v27, v30, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v14, v6 :: v_dual_lshlrev_b32 v28, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v25 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v13 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v26, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v28, v7 :: v_dual_lshlrev_b32 v30, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v29 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v13, v5 :: v_dual_lshlrev_b32 v29, 16, v12 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v27, v27 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_bfe_u32 v15, v24, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v15, v15, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v26, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v4 +; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v26, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v12 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v28, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v27 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v12, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_lshlrev_b32 v29, 16, v3 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v14, v26, v26 :: v_dual_lshlrev_b32 v27, 16, v11 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v24 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_bfe_u32 v27, v14, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v27, v27, v14, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v26, v5 :: v_dual_lshlrev_b32 v28, 16, v11 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v11, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v27, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v0 -; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v14 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v26, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v2 :: v_dual_lshlrev_b32 v25, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v13, v13, v13 :: v_dual_lshlrev_b32 v26, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v13, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-FAKE16-NEXT: v_add3_u32 v14, v24, v13, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v27, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v10, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v14, v24, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v9, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v14 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v26, v26 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 +; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v8, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v26, v24, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v27, v3 :: v_dual_lshlrev_b32 v14, 16, v14 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v11, v14, v14 -; GFX12-FAKE16-NEXT: v_add3_u32 v14, v26, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v25, v25, v25 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v25, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v28, v25, 0x7fff -; GFX12-FAKE16-NEXT: v_add3_u32 v28, v29, v11, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v11 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v27, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v15 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v30, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 -; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <16 x bfloat> @llvm.minimumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) @@ -11684,95 +9128,77 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 +; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v29 +; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v13 ; GFX8-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 ; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v31 -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v34 -; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v35, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v34, v31, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v35 -; GFX8-NEXT: v_mul_f32_e32 v35, 1.0, v35 -; GFX8-NEXT: v_bfe_u32 v36, v35, 16, 1 -; GFX8-NEXT: s_movk_i32 s5, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v36, vcc, v36, v35 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, s5, v36 -; GFX8-NEXT: v_or_b32_e32 v38, 0x400000, v35 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v31 +; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v34 +; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v35 +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v37, v39 ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v38, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v35 +; GFX8-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v36, v48 +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v31 -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v31, v36, v31, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX8-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 +; GFX8-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX8-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v31, v36, v31, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX8-NEXT: s_waitcnt vmcnt(4) -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v55 -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v55 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 +; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55 +; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc +; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v33, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX8-NEXT: v_mul_f32_e32 v33, 1.0, v33 -; GFX8-NEXT: v_bfe_u32 v35, v33, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v35, vcc, v35, v33 -; GFX8-NEXT: v_add_u32_e32 v35, vcc, s5, v35 -; GFX8-NEXT: v_or_b32_e32 v36, 0x400000, v33 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v33 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v35 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v33, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v32 -; GFX8-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v29 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v13 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v33, vcc -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v33 -; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v35, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v33, v34, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v35 -; GFX8-NEXT: v_mul_f32_e32 v35, 1.0, v35 -; GFX8-NEXT: v_bfe_u32 v36, v35, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, v36, v35 -; GFX8-NEXT: v_add_u32_e32 v36, vcc, s5, v36 -; GFX8-NEXT: v_or_b32_e32 v37, 0x400000, v35 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v35 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v33 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc -; GFX8-NEXT: v_and_b32_e32 v34, 0xffff0000, v35 -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v34 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v33 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX8-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 @@ -11784,27 +9210,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v36, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX8-NEXT: v_mul_f32_e32 v36, 1.0, v36 -; GFX8-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v37, vcc, v37, v36 -; GFX8-NEXT: v_add_u32_e32 v37, vcc, s5, v37 -; GFX8-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v36 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 ; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc -; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 +; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v36 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 ; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v27 ; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc @@ -11812,27 +9228,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v36 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v37, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX8-NEXT: v_mul_f32_e32 v37, 1.0, v37 -; GFX8-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v38, vcc, v38, v37 -; GFX8-NEXT: v_add_u32_e32 v38, vcc, s5, v38 -; GFX8-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v37 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v36 ; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc -; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 +; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v37 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v36 ; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v26 ; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc @@ -11840,23 +9246,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v38, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX8-NEXT: v_mul_f32_e32 v38, 1.0, v38 -; GFX8-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v39, vcc, v39, v38 -; GFX8-NEXT: v_add_u32_e32 v39, vcc, s5, v39 -; GFX8-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v38 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v36 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v37 ; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc -; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 +; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v38 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 ; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v25 ; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 @@ -11868,27 +9265,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v39, v48 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX8-NEXT: v_mul_f32_e32 v39, 1.0, v39 -; GFX8-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v48, vcc, v48, v39 -; GFX8-NEXT: v_add_u32_e32 v48, vcc, s5, v48 -; GFX8-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v39 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v37 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 ; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc -; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 +; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v39 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v38 ; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v24 ; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc @@ -11896,27 +9283,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v48, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX8-NEXT: v_mul_f32_e32 v48, 1.0, v48 -; GFX8-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v49, vcc, v49, v48 -; GFX8-NEXT: v_add_u32_e32 v49, vcc, s5, v49 -; GFX8-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v48 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v39 ; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc -; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 +; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v48 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v23 ; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc @@ -11924,27 +9301,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v48 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v49, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX8-NEXT: v_mul_f32_e32 v49, 1.0, v49 -; GFX8-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v50, vcc, v50, v49 -; GFX8-NEXT: v_add_u32_e32 v50, vcc, s5, v50 -; GFX8-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v49 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v39 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v48 ; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc -; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 +; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v49 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 ; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v6 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc @@ -11952,27 +9319,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v49 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v50, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX8-NEXT: v_mul_f32_e32 v50, 1.0, v50 -; GFX8-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v51, vcc, v51, v50 -; GFX8-NEXT: v_add_u32_e32 v51, vcc, s5, v51 -; GFX8-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v50 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v48 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v49 ; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 +; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v50 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v21 ; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v5 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc @@ -11980,27 +9337,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v50 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v51, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX8-NEXT: v_mul_f32_e32 v51, 1.0, v51 -; GFX8-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v52, vcc, v52, v51 -; GFX8-NEXT: v_add_u32_e32 v52, vcc, s5, v52 -; GFX8-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v51 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v49 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v50 ; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 +; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v51 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 ; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v20 ; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v4 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc @@ -12008,27 +9355,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v52, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX8-NEXT: v_mul_f32_e32 v52, 1.0, v52 -; GFX8-NEXT: v_bfe_u32 v53, v52, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v53, vcc, v53, v52 -; GFX8-NEXT: v_add_u32_e32 v53, vcc, s5, v53 -; GFX8-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v52 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v50 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v51 ; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc -; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 +; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v52 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 ; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v19 ; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v3 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc @@ -12036,27 +9373,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v53, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX8-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; GFX8-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v54, vcc, v54, v53 -; GFX8-NEXT: v_add_u32_e32 v54, vcc, s5, v54 -; GFX8-NEXT: v_or_b32_e32 v40, 0x400000, v53 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v54, v40, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v53 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v51 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v52 ; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc -; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v53 +; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc @@ -12064,27 +9391,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v53 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v54, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX8-NEXT: v_mul_f32_e32 v54, 1.0, v54 -; GFX8-NEXT: v_bfe_u32 v40, v54, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, v40, v54 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, s5, v40 -; GFX8-NEXT: v_or_b32_e32 v41, 0x400000, v54 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v40, v41, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v54 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v52 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v53 ; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc -; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v54 +; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v54 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53 ; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc @@ -12092,27 +9409,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v54 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v40, v41 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX8-NEXT: v_mul_f32_e32 v40, 1.0, v40 -; GFX8-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, v41, v40 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, s5, v41 -; GFX8-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX8-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v53 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v54 ; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc -; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v40 +; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v40 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54 ; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc @@ -12120,23 +9427,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v42, 16, v40 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v41, v42 ; GFX8-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX8-NEXT: v_mul_f32_e32 v41, 1.0, v41 -; GFX8-NEXT: v_bfe_u32 v42, v41, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v42, vcc, v42, v41 -; GFX8-NEXT: v_add_u32_e32 v42, vcc, s5, v42 -; GFX8-NEXT: v_or_b32_e32 v43, 0x400000, v41 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 -; GFX8-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v42, 16, v41 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v54 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc -; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v41 +; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v41 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v40 ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc @@ -12146,23 +9444,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v41, v40 ; GFX8-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX8-NEXT: v_mul_f32_e32 v40, 1.0, v40 -; GFX8-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, v41, v40 -; GFX8-NEXT: v_add_u32_e32 v41, vcc, s5, v41 -; GFX8-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX8-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc -; GFX8-NEXT: v_and_b32_e32 v55, 0xffff0000, v40 +; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v40 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v55 ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc @@ -12172,23 +9461,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v40, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX8-NEXT: v_mul_f32_e32 v55, 1.0, v55 -; GFX8-NEXT: v_bfe_u32 v40, v55, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, v40, v55 -; GFX8-NEXT: v_add_u32_e32 v40, vcc, s5, v40 -; GFX8-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX8-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v55 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v55 +; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc @@ -12198,23 +9478,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v13 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v55, v30 ; GFX8-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX8-NEXT: v_mul_f32_e32 v30, 1.0, v30 -; GFX8-NEXT: v_bfe_u32 v55, v30, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v55, vcc, v55, v30 -; GFX8-NEXT: v_add_u32_e32 v55, vcc, s5, v55 -; GFX8-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX8-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v55, 16, v30 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v30 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v29 ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc @@ -12224,23 +9495,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v12 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v30, v29 ; GFX8-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX8-NEXT: v_mul_f32_e32 v29, 1.0, v29 -; GFX8-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v30, vcc, v30, v29 -; GFX8-NEXT: v_add_u32_e32 v30, vcc, s5, v30 -; GFX8-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX8-NEXT: v_cndmask_b32_e32 v29, v30, v55, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v28 ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc @@ -12250,23 +9512,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v29, v28 ; GFX8-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX8-NEXT: v_mul_f32_e32 v28, 1.0, v28 -; GFX8-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v29, vcc, v29, v28 -; GFX8-NEXT: v_add_u32_e32 v29, vcc, s5, v29 -; GFX8-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX8-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v27 ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc @@ -12276,23 +9529,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v10 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v28, v27 ; GFX8-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX8-NEXT: v_mul_f32_e32 v27, 1.0, v27 -; GFX8-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v28, vcc, v28, v27 -; GFX8-NEXT: v_add_u32_e32 v28, vcc, s5, v28 -; GFX8-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX8-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v27 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v27 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v26 ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc @@ -12302,23 +9546,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v9 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v27, v26 ; GFX8-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX8-NEXT: v_mul_f32_e32 v26, 1.0, v26 -; GFX8-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v27, vcc, v27, v26 -; GFX8-NEXT: v_add_u32_e32 v27, vcc, s5, v27 -; GFX8-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX8-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v26 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v25 ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc @@ -12328,23 +9563,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v26, v25 ; GFX8-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX8-NEXT: v_mul_f32_e32 v25, 1.0, v25 -; GFX8-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; GFX8-NEXT: v_add_u32_e32 v26, vcc, s5, v26 -; GFX8-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc @@ -12354,23 +9580,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX8-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX8-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; GFX8-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; GFX8-NEXT: v_add_u32_e32 v25, vcc, s5, v25 -; GFX8-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX8-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX8-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc @@ -12380,23 +9600,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v24, v23 ; GFX8-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX8-NEXT: v_mul_f32_e32 v23, 1.0, v23 -; GFX8-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; GFX8-NEXT: v_add_u32_e32 v24, vcc, s5, v24 -; GFX8-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc @@ -12406,23 +9617,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v5 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v23, v22 ; GFX8-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX8-NEXT: v_mul_f32_e32 v22, 1.0, v22 -; GFX8-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v22 -; GFX8-NEXT: v_add_u32_e32 v23, vcc, s5, v23 -; GFX8-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc @@ -12432,23 +9634,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v22, v21 ; GFX8-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX8-NEXT: v_mul_f32_e32 v21, 1.0, v21 -; GFX8-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; GFX8-NEXT: v_add_u32_e32 v22, vcc, s5, v22 -; GFX8-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc @@ -12456,29 +9649,16 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX8-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX8-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v21, v20 ; GFX8-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX8-NEXT: v_mul_f32_e32 v20, 1.0, v20 -; GFX8-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v20 -; GFX8-NEXT: v_add_u32_e32 v21, vcc, s5, v21 -; GFX8-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc @@ -12488,23 +9668,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v20, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_mul_f32_e32 v19, 1.0, v19 -; GFX8-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; GFX8-NEXT: v_add_u32_e32 v20, vcc, s5, v20 -; GFX8-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc @@ -12514,23 +9685,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v19, v18 ; GFX8-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX8-NEXT: v_mul_f32_e32 v18, 1.0, v18 -; GFX8-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v18 -; GFX8-NEXT: v_add_u32_e32 v19, vcc, s5, v19 -; GFX8-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc @@ -12540,22 +9702,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v18, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX8-NEXT: v_mul_f32_e32 v17, 1.0, v17 -; GFX8-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v17 -; GFX8-NEXT: v_add_u32_e32 v18, vcc, s5, v18 -; GFX8-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v17 ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v54 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v53 @@ -12605,85 +9758,70 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v13 ; GFX900-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 +; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 ; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc +; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 ; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v31 +; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc ; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v34 +; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v37, v39 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX900-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX900-NEXT: s_movk_i32 s5, 0x7fff -; GFX900-NEXT: v_bfe_u32 v39, v37, 16, 1 -; GFX900-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX900-NEXT: v_add3_u32 v39, v39, v37, s5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 ; GFX900-NEXT: s_movk_i32 s4, 0x8000 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v48, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v37 +; GFX900-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc +; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v36, v48 +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v31 -; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v31, v39, v31, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 +; GFX900-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX900-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 +; GFX900-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX900-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX900-NEXT: v_lshrrev_b32_e32 v33, 16, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v31, v39, v31, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX900-NEXT: s_waitcnt vmcnt(4) -; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v55 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 +; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 +; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 +; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 +; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX900-NEXT: s_waitcnt vmcnt(3) +; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc ; GFX900-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v34 +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v33, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX900-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX900-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX900-NEXT: v_or_b32_e32 v39, 0x400000, v33 -; GFX900-NEXT: v_add3_u32 v37, v37, v33, s5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v37, v39, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v33 +; GFX900-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v32 -; GFX900-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v37, v32, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33 -; GFX900-NEXT: v_and_b32_e32 v33, 0xffff0000, v29 -; GFX900-NEXT: v_cndmask_b32_e32 v32, v37, v32, vcc -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v38, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v34, 16, v33 -; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v36, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v33, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; GFX900-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX900-NEXT: v_bfe_u32 v36, v34, 16, 1 -; GFX900-NEXT: v_add3_u32 v36, v36, v34, s5 -; GFX900-NEXT: v_or_b32_e32 v37, 0x400000, v34 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v37, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v34 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v33 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v33 -; GFX900-NEXT: v_and_b32_e32 v34, 0xffff0000, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v35, v33, vcc -; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v34 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc +; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX900-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX900-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 @@ -12695,26 +9833,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v36, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX900-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX900-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX900-NEXT: v_add3_u32 v37, v37, v36, s5 -; GFX900-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v36 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v34 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 ; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc -; GFX900-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 +; GFX900-NEXT: v_lshlrev_b32_e32 v35, 16, v36 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 ; GFX900-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v27 ; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc @@ -12722,26 +9851,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v36 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v37, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX900-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX900-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX900-NEXT: v_add3_u32 v38, v38, v37, s5 -; GFX900-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v37 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v35 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v36 ; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc -; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 +; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v37 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v36 ; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v26 ; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc @@ -12749,22 +9869,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v37 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v38, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX900-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX900-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX900-NEXT: v_add3_u32 v39, v39, v38, s5 -; GFX900-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v38 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v36 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v37 ; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc -; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 +; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v38 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v25 ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 @@ -12776,26 +9888,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v38 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v39, v48 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX900-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX900-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX900-NEXT: v_add3_u32 v48, v48, v39, s5 -; GFX900-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v39 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v37 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 ; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc -; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 +; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v39 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v38 ; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v24 ; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc @@ -12803,26 +9906,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v48, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX900-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX900-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX900-NEXT: v_add3_u32 v49, v49, v48, s5 -; GFX900-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v48 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v38 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v39 ; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc -; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 +; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v48 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v23 ; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc @@ -12830,26 +9924,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v48 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v49, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX900-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX900-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX900-NEXT: v_add3_u32 v50, v50, v49, s5 -; GFX900-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v49 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v39 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v48 ; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc -; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 +; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v49 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 ; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v6 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc @@ -12857,26 +9942,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v49 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v50, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX900-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX900-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX900-NEXT: v_add3_u32 v51, v51, v50, s5 -; GFX900-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v50 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v48 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v49 ; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 +; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v50 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v21 ; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v5 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc @@ -12884,26 +9960,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v50 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v51, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX900-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX900-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX900-NEXT: v_add3_u32 v52, v52, v51, s5 -; GFX900-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v51 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v49 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v50 ; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 +; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v51 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 ; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v20 ; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v4 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc @@ -12911,26 +9978,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v52, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX900-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX900-NEXT: v_bfe_u32 v53, v52, 16, 1 -; GFX900-NEXT: v_add3_u32 v53, v53, v52, s5 -; GFX900-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v52 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v50 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v51 ; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc -; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 +; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v52 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 ; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v19 ; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v3 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc @@ -12938,26 +9996,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v53, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX900-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX900-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX900-NEXT: v_add3_u32 v54, v54, v53, s5 -; GFX900-NEXT: v_or_b32_e32 v40, 0x400000, v53 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v54, v40, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v53 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v51 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v52 ; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc -; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v53 +; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v18 ; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc @@ -12965,26 +10014,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v53 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v54, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX900-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX900-NEXT: v_bfe_u32 v40, v54, 16, 1 -; GFX900-NEXT: v_add3_u32 v40, v40, v54, s5 -; GFX900-NEXT: v_or_b32_e32 v41, 0x400000, v54 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v40, v41, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v54 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v52 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v53 ; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc -; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v54 +; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v54 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53 ; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v52, v40, v52, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v17 ; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc @@ -12992,26 +10032,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v54 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v40, v41 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX900-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX900-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX900-NEXT: v_add3_u32 v41, v41, v40, s5 -; GFX900-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX900-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v53 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v54 ; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc -; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v40 +; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v40 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54 ; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v53, v41, v53, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v16 ; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc @@ -13019,22 +10050,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v42, 16, v40 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v41, v42 ; GFX900-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX900-NEXT: v_max_f32_e32 v41, v41, v41 -; GFX900-NEXT: v_bfe_u32 v42, v41, 16, 1 -; GFX900-NEXT: v_add3_u32 v42, v42, v41, s5 -; GFX900-NEXT: v_or_b32_e32 v43, 0x400000, v41 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 -; GFX900-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v42, 16, v41 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v54 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc -; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v41 +; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v41 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v40 ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v54, v42, v54, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc @@ -13044,22 +10067,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v41, v40 ; GFX900-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX900-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX900-NEXT: v_bfe_u32 v41, v40, 16, 1 -; GFX900-NEXT: v_add3_u32 v41, v41, v40, s5 -; GFX900-NEXT: v_or_b32_e32 v42, 0x400000, v40 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX900-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v40 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v15 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc -; GFX900-NEXT: v_and_b32_e32 v55, 0xffff0000, v40 +; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v40 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v55 ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v15, v41, v15, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc @@ -13069,22 +10084,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v40, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX900-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX900-NEXT: v_bfe_u32 v40, v55, 16, 1 -; GFX900-NEXT: v_add3_u32 v40, v40, v55, s5 -; GFX900-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX900-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v55 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v14 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX900-NEXT: v_and_b32_e32 v30, 0xffff0000, v55 +; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v14, v40, v14, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc @@ -13094,22 +10101,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v13 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v55, v30 ; GFX900-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX900-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX900-NEXT: v_bfe_u32 v55, v30, 16, 1 -; GFX900-NEXT: v_add3_u32 v55, v55, v30, s5 -; GFX900-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX900-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v55, 16, v30 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v13 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc -; GFX900-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v30 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v29 ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc @@ -13119,22 +10118,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v12 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v30, v29 ; GFX900-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX900-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX900-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX900-NEXT: v_add3_u32 v30, v30, v29, s5 -; GFX900-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX900-NEXT: v_cndmask_b32_e32 v29, v30, v55, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v30, 16, v29 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v12 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc -; GFX900-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 +; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v28 ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc @@ -13144,22 +10135,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v29, v28 ; GFX900-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX900-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX900-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX900-NEXT: v_add3_u32 v29, v29, v28, s5 -; GFX900-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX900-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v11 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc -; GFX900-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v27 ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc @@ -13169,22 +10152,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v10 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v28, v27 ; GFX900-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX900-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX900-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX900-NEXT: v_add3_u32 v28, v28, v27, s5 -; GFX900-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX900-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v28, 16, v27 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v10 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc -; GFX900-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 +; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v27 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v26 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc @@ -13194,47 +10169,34 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v9 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v27, v26 ; GFX900-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX900-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX900-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX900-NEXT: v_add3_u32 v27, v27, v26, s5 -; GFX900-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX900-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v27, 16, v26 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v9 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc -; GFX900-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 +; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v26 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v25 ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc +; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v26, v25 ; GFX900-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX900-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX900-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX900-NEXT: v_add3_u32 v26, v26, v25, s5 -; GFX900-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX900-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v26, 16, v25 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v8 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc -; GFX900-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 +; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v25 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc @@ -13244,22 +10206,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v7 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX900-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX900-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX900-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX900-NEXT: v_add3_u32 v25, v25, v24, s5 -; GFX900-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v25, 16, v24 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc -; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v24 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23 ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc @@ -13269,22 +10223,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v6 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v24, v23 ; GFX900-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX900-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX900-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX900-NEXT: v_add3_u32 v24, v24, v23, s5 -; GFX900-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v23 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc -; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 +; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22 ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc @@ -13294,26 +10240,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v5 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v23, v22 ; GFX900-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX900-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX900-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX900-NEXT: v_add3_u32 v23, v23, v22, s5 -; GFX900-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; GFX900-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload -; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc -; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21 ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc @@ -13323,22 +10257,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v22, v21 ; GFX900-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX900-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX900-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX900-NEXT: v_add3_u32 v22, v22, v21, s5 -; GFX900-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v21 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc -; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v21 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v20 ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc @@ -13348,22 +10274,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v3 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v21, v20 ; GFX900-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX900-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX900-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX900-NEXT: v_add3_u32 v21, v21, v20, s5 -; GFX900-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v20 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc -; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v20 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v19 ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc @@ -13373,22 +10291,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v20, v19 ; GFX900-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX900-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX900-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX900-NEXT: v_add3_u32 v20, v20, v19, s5 -; GFX900-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v19 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc -; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v19 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v18 ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc @@ -13398,22 +10308,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v19, v18 ; GFX900-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX900-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX900-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX900-NEXT: v_add3_u32 v19, v19, v18, s5 -; GFX900-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc -; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v18 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 ; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 ; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc @@ -13423,21 +10325,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v18, v17 ; GFX900-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX900-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX900-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX900-NEXT: v_add3_u32 v18, v18, v17, s5 -; GFX900-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v17 ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v16 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc -; GFX900-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX900-NEXT: v_lshlrev_b32_e32 v16, 16, v17 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v54, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v53, v1, s4 @@ -13461,7 +10355,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-LABEL: v_minimumnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: scratch_load_dword v51, off, s32 +; GFX950-NEXT: scratch_load_dword v50, off, s32 ; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30 ; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v14 @@ -13483,79 +10377,68 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v34 ; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc -; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v37, v39 ; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v37, v39 ; GFX950-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v37 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v36, v48 -; GFX950-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v37, v37, s0 +; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v37 +; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v23 ; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v31 -; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v37 -; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34 -; GFX950-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 -; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 -; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX950-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 +; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v36 ; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v22 +; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v35 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v21 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v20 +; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 ; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v38 ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 +; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 +; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 ; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX950-NEXT: s_waitcnt vmcnt(0) -; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v51 -; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v51 -; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc +; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50 +; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 ; GFX950-NEXT: v_lshlrev_b32_e32 v33, 16, v32 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v34, v34, v32, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v34 +; GFX950-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v35 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v33, v37 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v34, v32, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX950-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v33, v33, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v32 ; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v33 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v35 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v34, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v37 +; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v28 ; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v28 -; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc -; GFX950-NEXT: v_cvt_pk_bf16_f32 v33, v36, s0 -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v35 -; GFX950-NEXT: v_lshrrev_b32_e32 v36, 16, v12 -; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v34, v33, v35, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v38 -; GFX950-NEXT: v_lshlrev_b32_e32 v35, 16, v33 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v48 +; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v34, v34, v38, vcc -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v35 -; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v28 -; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 -; GFX950-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc ; GFX950-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 +; GFX950-NEXT: v_lshrrev_b32_e32 v36, 16, v12 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v35, vcc @@ -13568,9 +10451,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v37, 16, v11 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX950-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v36, v36, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc @@ -13595,9 +10475,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v38, 16, v10 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX950-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v37, v37, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v35 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc @@ -13622,9 +10499,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v39, 16, v9 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX950-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v38, v38, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v36 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc @@ -13649,9 +10523,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v48, 16, v8 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX950-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v39, v39, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v37 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc @@ -13676,9 +10547,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v7 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX950-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v48, v48, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v38 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc @@ -13694,18 +10562,15 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v39 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v48 -; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v49, v50 -; GFX950-NEXT: v_lshrrev_b32_e32 v50, 16, v6 +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v48 +; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v49, v51 +; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v6 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX950-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v49, v49, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v39 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc @@ -13720,84 +10585,75 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v22 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v49, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v48 +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v48 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v49 -; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v50, v52 +; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v51, v52 ; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v5 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX950-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v50, v50, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v51, v49, v48, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v48 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v49 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v51 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v49 ; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc -; GFX950-NEXT: v_lshrrev_b32_e32 v50, 16, v21 +; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc +; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v21 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v51, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v49 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v49, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v52, v53 ; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v4 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v52, v50, v49, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX950-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v52, v52, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v52, v51, v49, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v49 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v50 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v52 -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 -; GFX950-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 +; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v51, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v52 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 +; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v4 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v20 -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v52, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v51 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v52 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v53, v54 ; GFX950-NEXT: v_lshrrev_b32_e32 v54, 16, v3 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v53, v52, v50, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX950-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v53, v53, s0 -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v50 +; GFX950-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v51 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v52 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v52, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v53 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52 ; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v3 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v50, v53, v50, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc ; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v19 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 ; GFX950-NEXT: s_nop 1 @@ -13811,9 +10667,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v55, 16, v2 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX950-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v54, v54, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v52 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc @@ -13838,9 +10691,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v40, 16, v1 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v54, v53, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX950-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v55, v55, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v53 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc @@ -13865,9 +10715,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_lshrrev_b32_e32 v41, 16, v0 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v40, v55, v54, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX950-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v40, v40, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v54 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v54, v40, v54, vcc @@ -13892,9 +10739,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v41, v40, v55, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v41 -; GFX950-NEXT: v_max_f32_e32 v41, v41, v41 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v41, v41, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v55 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc @@ -13907,74 +10751,65 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v50 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v51, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 ; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v15 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v15, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v51 +; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v15, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v50 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v41, v40 ; GFX950-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v40, v51, v15, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v40 -; GFX950-NEXT: v_max_f32_e32 v40, v40, v40 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v40, v40, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v40, v50, v15, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v15 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc -; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v51 +; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v50 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v51, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v40 -; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v14 +; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v40 +; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v14 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v30 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v30 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 +; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 ; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v14 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v30 -; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v40, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v30 +; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v40, v50 ; GFX950-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v51, v30, v14, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX950-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v51, v51, s0 +; GFX950-NEXT: v_cndmask_b32_e32 v50, v30, v14, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v14 ; GFX950-NEXT: s_nop 1 -; GFX950-NEXT: v_cndmask_b32_e32 v14, v51, v14, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v30 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v51 +; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v50 ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v30 ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v13 ; GFX950-NEXT: s_nop 0 -; GFX950-NEXT: v_cndmask_b32_e32 v14, v51, v14, vcc +; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v29 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v13 +; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v13 ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v51, v30 +; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v50, v30 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX950-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v30, v30, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v13 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc @@ -13998,9 +10833,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v30, v29 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX950-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v29, v29, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v12 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc @@ -14024,9 +10856,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v29, v28 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX950-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v28, v28, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v11 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc @@ -14050,9 +10879,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v28, v27 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX950-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v27, v27, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v10 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc @@ -14076,9 +10902,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v27, v26 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX950-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v26, v26, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v9 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc @@ -14102,9 +10925,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v26, v25 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX950-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v25, v25, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc @@ -14128,9 +10948,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v25, v24 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX950-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v24, v24, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc @@ -14154,9 +10971,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v24, v23 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX950-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v23, v23, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc @@ -14180,9 +10994,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v23, v22 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX950-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v22, v22, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc @@ -14206,9 +11017,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v22, v21 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX950-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v21, v21, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v4 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc @@ -14232,9 +11040,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v21, v20 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX950-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v20, v20, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc @@ -14258,9 +11063,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v20, v19 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX950-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v19, v19, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v2 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc @@ -14284,9 +11086,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v19, v18 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX950-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v18, v18, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc @@ -14310,9 +11109,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v18, v17 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX950-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v17, v17, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc @@ -14326,7 +11122,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_perm_b32 v3, v52, v3, s0 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc ; GFX950-NEXT: v_perm_b32 v0, v55, v0, s0 -; GFX950-NEXT: v_perm_b32 v4, v50, v4, s0 +; GFX950-NEXT: v_perm_b32 v4, v51, v4, s0 ; GFX950-NEXT: v_perm_b32 v5, v49, v5, s0 ; GFX950-NEXT: v_perm_b32 v6, v48, v6, s0 ; GFX950-NEXT: v_perm_b32 v7, v39, v7, s0 @@ -14343,2616 +11139,1874 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX10-LABEL: v_minimumnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 -; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v12 +; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v28 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v53 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v32 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v31, v32, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v31 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v33, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v31, v32, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX10-NEXT: v_max_f32_e32 v33, v33, v33 -; GFX10-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_add3_u32 v34, v34, v33, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32 -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v30 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v34, v32, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v31 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v32, 0xffff0000, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v14 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v32 -; GFX10-NEXT: v_and_b32_e32 v32, 0xffff0000, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v31, v34, v31, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v33, v32, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v32 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v34, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v32, v33, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; GFX10-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX10-NEXT: v_bfe_u32 v35, v34, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_add3_u32 v35, v35, v34, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 +; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v11 ; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v35, v33, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v34 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v13 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v33 -; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v32, v35, v32, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v33, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v32 +; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v26 +; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v10 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v51, v51 +; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v34, v48, v39, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v33 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v35, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v33, v34, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v35 -; GFX10-NEXT: v_max_f32_e32 v35, v35, v35 -; GFX10-NEXT: v_bfe_u32 v36, v35, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v37, 0x400000, v35 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_add3_u32 v36, v36, v35, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v23 +; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v7 +; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v22 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v32, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v34 +; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v6 +; GFX10-NEXT: v_lshrrev_b32_e32 v70, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v38, v33, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v37 +; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v3 +; GFX10-NEXT: v_lshrrev_b32_e32 v85, 16, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v36 +; GFX10-NEXT: v_cndmask_b32_e32 v35, v39, v34, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v33 +; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v31, v38 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v26 +; GFX10-NEXT: v_cndmask_b32_e64 v38, v53, v52, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v35 +; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v39, v48 +; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v9 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v25 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v49, v50 +; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v25 +; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e64 v48, v52, v38, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v39, v39 +; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v38 +; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v39, v50, v49, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v39 +; GFX10-NEXT: v_cndmask_b32_e64 v50, v49, v39, s6 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v52, v52 +; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v24 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v54, v53, s6 +; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v51, v55 +; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v49 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v53, v49, s7 +; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v23 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v55, v55 +; GFX10-NEXT: v_cmp_lt_f32_e64 s9, v31, v51 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v65, v64, s7 +; GFX10-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e64 v53, v64, v55, s7 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v65, v65 +; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v53 +; GFX10-NEXT: v_cndmask_b32_e64 v65, v67, v66, s7 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v52 +; GFX10-NEXT: v_cmp_u_f32_e64 s7, v64, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v65 +; GFX10-NEXT: v_cmp_lt_f32_e64 s8, v54, v67 +; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v64, v66, v65, s7 +; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v68, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v21 +; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v4 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54 +; GFX10-NEXT: v_lshrrev_b32_e32 v69, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v64 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v67, v66, s10 +; GFX10-NEXT: v_and_b32_e32 v67, 0xffff0000, v21 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v68, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v70, v69, s10 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v67, v67 +; GFX10-NEXT: v_lshlrev_b32_e32 v70, 16, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v66, v54, s10 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v71, v71 +; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v66 +; GFX10-NEXT: v_cndmask_b32_e64 v67, v69, v68, s10 +; GFX10-NEXT: v_and_b32_e32 v69, 0xffff0000, v3 +; GFX10-NEXT: v_cmp_lt_f32_e64 s11, v70, v81 +; GFX10-NEXT: v_and_b32_e32 v70, 0xffff0000, v2 +; GFX10-NEXT: v_cmp_u_f32_e64 s10, v69, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v71, s10 +; GFX10-NEXT: v_cmp_lt_f32_e64 s10, v31, v51 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v19 +; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v18 +; GFX10-NEXT: v_cmp_lt_f32_e64 s12, v82, v83 +; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v17 +; GFX10-NEXT: v_lshrrev_b32_e32 v83, 16, v1 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v69 +; GFX10-NEXT: v_cndmask_b32_e64 v71, v71, v69, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v70, v70 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v81, v80, s13 +; GFX10-NEXT: v_and_b32_e32 v81, 0xffff0000, v1 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v71 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v70, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s13, v81, v81 +; GFX10-NEXT: v_and_b32_e32 v81, 0xffff0000, v17 +; GFX10-NEXT: v_cndmask_b32_e64 v83, v83, v82, s13 +; GFX10-NEXT: v_cmp_u_f32_e64 s14, v81, v81 +; GFX10-NEXT: v_cmp_lt_f32_e64 s13, v51, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v70 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v80 +; GFX10-NEXT: v_cndmask_b32_e64 v81, v82, v83, s14 +; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v0 +; GFX10-NEXT: v_cmp_lt_f32_e64 s14, v31, v51 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v83 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v81 +; GFX10-NEXT: v_cmp_lt_f32_e64 s15, v31, v51 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v16 +; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v16 +; GFX10-NEXT: v_cndmask_b32_e64 v82, v82, v51, s16 +; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v31 +; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v82 +; GFX10-NEXT: v_cndmask_b32_e64 v51, v51, v82, s16 +; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v51 +; GFX10-NEXT: v_cmp_lt_f32_e64 s16, v31, v84 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 +; GFX10-NEXT: v_lshrrev_b32_e32 v84, 16, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s17, v31, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v84, s17 +; GFX10-NEXT: v_and_b32_e32 v85, 0xffff0000, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s17, v85, v85 +; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v84, v84, v31, s17 +; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84 +; GFX10-NEXT: v_cmp_lt_f32_e64 s17, v85, v86 +; GFX10-NEXT: v_cndmask_b32_e64 v85, v84, v31, s17 +; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v31 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s17 +; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v84 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v31, v84, s17 +; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v85 +; GFX10-NEXT: v_cmp_eq_f32_e64 s17, 0, v84 +; GFX10-NEXT: v_cndmask_b32_e64 v84, v37, v32, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v32 +; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s17 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v84, v32, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v32, v37, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v84 +; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v37, v36, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v33 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v84, v32, s5 +; GFX10-NEXT: buffer_load_dword v84, off, s[0:3], s32 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v37, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v36 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v55 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v33, v36, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v37 +; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v36 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34 -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v28 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v35 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v37, v33, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v49 ; GFX10-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v35 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v12 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v34 -; GFX10-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v35, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v34 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v34, v35, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX10-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX10-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_add3_u32 v37, v37, v36, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v35, v34, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v36 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v11 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v35 -; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v34, v37, v34, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v35 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v37, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v36, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX10-NEXT: v_max_f32_e32 v37, v37, v37 -; GFX10-NEXT: v_bfe_u32 v38, v37, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v39, 0x400000, v37 +; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v35, v48, v38, s6 +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v69 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v38, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v38, v50, v39, s9 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v48, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v38 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v38, v39, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v50, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v48, v52, v49, s8 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v48, v49, s4 +; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v52 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v48 +; GFX10-NEXT: v_cndmask_b32_e64 v49, v49, v52, s4 +; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v50 +; GFX10-NEXT: v_cndmask_b32_e64 v50, v53, v55, s7 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v50, v55, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v53 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v52, v53, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v53, v64, v65, s10 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v65 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v53, v65, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v64 +; GFX10-NEXT: v_cndmask_b32_e64 v65, v67, v68, s12 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v55, v64, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v64, v66, v54, s11 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v54 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v64, v54, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v66 +; GFX10-NEXT: v_cndmask_b32_e64 v54, v54, v66, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v68 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v65, v68, s5 +; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v66, v66, v67, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65 +; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v67, v71, v69, s13 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v67, v69, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v71 +; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v70, s14 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v68, v71, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v70 +; GFX10-NEXT: v_cndmask_b32_e64 v71, v81, v83, s15 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v69, v70, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v80 +; GFX10-NEXT: v_cndmask_b32_e64 v70, v70, v80, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v83 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v71, v83, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v81 +; GFX10-NEXT: v_lshrrev_b32_e32 v83, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v81, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v81, v51, v82, s16 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v82 +; GFX10-NEXT: v_cndmask_b32_e64 v82, v81, v82, s6 +; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v51 +; GFX10-NEXT: v_cndmask_b32_e64 v51, v82, v51, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v36 +; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v82 +; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v35 +; GFX10-NEXT: v_cndmask_b32_e64 v34, v36, v34, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v14 +; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v82 +; GFX10-NEXT: v_and_b32_e32 v82, 0xffff0000, v15 +; GFX10-NEXT: v_cndmask_b32_e64 v35, v35, v37, s6 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v30 +; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v50 +; GFX10-NEXT: v_cndmask_b32_e64 v85, v14, v30, s6 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v38, v39, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_add3_u32 v38, v38, v37, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36 -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v37 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v86, v30, v85, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 -; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v35, v38, v35, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v36 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v38, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v36, v37, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; GFX10-NEXT: v_max_f32_e32 v38, v38, v38 -; GFX10-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_add3_u32 v39, v39, v38, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37 -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v25 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v37, v36, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e64 v30, v48, v49, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v67 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v69 +; GFX10-NEXT: v_cndmask_b32_e32 v36, v50, v52, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37 -; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v36, v39, v36, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v37, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v37 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v39, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v37, v38, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v39 -; GFX10-NEXT: v_max_f32_e32 v39, v39, v39 -; GFX10-NEXT: v_bfe_u32 v48, v39, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_add3_u32 v48, v48, v39, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38 -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v38, v37, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v39 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v71 +; GFX10-NEXT: v_cndmask_b32_e32 v37, v53, v55, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v38 -; GFX10-NEXT: v_and_b32_e32 v38, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v37, v48, v37, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v38 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v48, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v38, v39, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX10-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX10-NEXT: v_bfe_u32 v49, v48, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_add3_u32 v49, v49, v48, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v23 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v39, v38, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v48 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v7 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v81 +; GFX10-NEXT: v_cndmask_b32_e32 v38, v64, v54, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v84 +; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v84 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v83, v52, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v39 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v49, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v39, v48, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX10-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX10-NEXT: v_bfe_u32 v50, v49, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_add3_u32 v50, v50, v49, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48 -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v22 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v84 +; GFX10-NEXT: v_cndmask_b32_e32 v64, v15, v84, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX10-NEXT: v_cndmask_b32_e64 v15, v65, v66, s5 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v55, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v52 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v84, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48 -; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v39, v50, v39, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v48 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v48, v49, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v50 -; GFX10-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX10-NEXT: v_bfe_u32 v51, v50, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_add3_u32 v51, v51, v50, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49 -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v49, v48, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v50 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v39, v67, v68, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v49, v50, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; GFX10-NEXT: v_max_f32_e32 v51, v51, v51 -; GFX10-NEXT: v_bfe_u32 v52, v51, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v54, 0x400000, v51 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_add3_u32 v52, v52, v51, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v51, v52, v54, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v50, v49, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v51 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v54 +; GFX10-NEXT: v_cndmask_b32_e32 v48, v69, v70, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v66 +; GFX10-NEXT: v_cndmask_b32_e32 v49, v52, v55, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v67, v68 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v49 +; GFX10-NEXT: v_cndmask_b32_e32 v65, v54, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX10-NEXT: v_and_b32_e32 v50, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v50 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v50, v51, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX10-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX10-NEXT: v_bfe_u32 v54, v52, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v55, 0x400000, v52 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v52, v54, v55, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51 -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v54, v51, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v51, v50, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v50, v54, v50, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51 -; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v51 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v51, v52, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX10-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX10-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v54, v55, v64, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v50, v71, v80, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v49, v55, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64 +; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v64, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 -; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v18 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v54 ; GFX10-NEXT: v_cndmask_b32_e32 v52, v55, v52, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v52, v51, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v54 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v2 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 -; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v51, v55, v51, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v54, v52, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v52, v54, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v52 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v52, v54, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX10-NEXT: v_max_f32_e32 v55, v55, v55 -; GFX10-NEXT: v_bfe_u32 v64, v55, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v65, 0x400000, v55 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_add3_u32 v64, v64, v55, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v55, v64, v65, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX10-NEXT: v_and_b32_e32 v65, 0xffff0000, v17 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v65 ; GFX10-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v55 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v1 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v52, v64, v52, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v55, v54, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v54 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v65 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v54, v55, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX10-NEXT: v_max_f32_e32 v64, v64, v64 -; GFX10-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v66, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 -; GFX10-NEXT: v_and_b32_e32 v66, 0xffff0000, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v55, v54, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v0 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 -; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v54, v65, v54, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v64, v55, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v55 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v66 -; GFX10-NEXT: v_cndmask_b32_e32 v65, v55, v64, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX10-NEXT: v_max_f32_e32 v65, v65, v65 -; GFX10-NEXT: v_bfe_u32 v66, v65, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v67, 0x400000, v65 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX10-NEXT: v_add3_u32 v66, v66, v65, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v65, v66, v67, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64 -; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v65 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v66, v64, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v64, v55, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v65 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v55, v66, v55, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v53, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v53, v53, v15, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v64, v53, v15, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX10-NEXT: v_max_f32_e32 v64, v64, v64 -; GFX10-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX10-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v66, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v65, v15, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v53, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v64 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v66 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v52, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v65, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_perm_b32 v15, v31, v15, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v53, v30, v14, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX10-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX10-NEXT: v_bfe_u32 v64, v53, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v65, 0x400000, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v52, v81, v51, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v85 +; GFX10-NEXT: v_cndmask_b32_e32 v51, v65, v54, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v86 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX10-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v53, v64, v65, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v53 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v64, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v53 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v64, v14, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_perm_b32 v14, v32, v14, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v13 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v86, v85, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 ; GFX10-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v30 -; GFX10-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX10-NEXT: v_bfe_u32 v53, v30, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v64, 0x400000, v30 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX10-NEXT: v_add3_u32 v53, v53, v30, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v30, v53, v64, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v85 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v54, v85, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v53, v28, v12, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v86 +; GFX10-NEXT: v_cndmask_b32_e32 v28, v55, v86, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 -; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v30 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v55 +; GFX10-NEXT: v_cndmask_b32_e32 v28, v54, v28, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v66, v65 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v54, v53, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 ; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX10-NEXT: v_perm_b32 v13, v33, v13, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX10-NEXT: v_max_f32_e32 v29, v29, v29 -; GFX10-NEXT: v_bfe_u32 v30, v29, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v53, 0x400000, v29 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 -; GFX10-NEXT: v_add3_u32 v30, v30, v29, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v29, v30, v53, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v11 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v29 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v29 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v54 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 -; GFX10-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX10-NEXT: v_max_f32_e32 v28, v28, v28 -; GFX10-NEXT: v_bfe_u32 v29, v28, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX10-NEXT: v_add3_u32 v29, v29, v28, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v53, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX10-NEXT: v_perm_b32 v13, v32, v13, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9 +; GFX10-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v29 +; GFX10-NEXT: v_cndmask_b32_e32 v29, v27, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v28 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v29 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v53, v26, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX10-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX10-NEXT: v_max_f32_e32 v27, v27, v27 -; GFX10-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX10-NEXT: v_add3_u32 v28, v28, v27, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v53 +; GFX10-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 ; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v27 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX10-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; GFX10-NEXT: v_max_f32_e32 v26, v26, v26 -; GFX10-NEXT: v_bfe_u32 v27, v26, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX10-NEXT: v_add3_u32 v27, v27, v26, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 +; GFX10-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v25 -; GFX10-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; GFX10-NEXT: v_max_f32_e32 v25, v25, v25 -; GFX10-NEXT: v_bfe_u32 v26, v25, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v27, 0x400000, v25 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX10-NEXT: v_perm_b32 v9, v14, v9, 0x5040100 +; GFX10-NEXT: v_perm_b32 v14, v31, v28, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v26 +; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX10-NEXT: v_add3_u32 v26, v26, v25, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: v_max_f32_e32 v24, v24, v24 -; GFX10-NEXT: v_bfe_u32 v25, v24, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX10-NEXT: v_add3_u32 v25, v25, v24, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v24 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v26 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX10-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v23 +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX10-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX10-NEXT: v_max_f32_e32 v23, v23, v23 -; GFX10-NEXT: v_bfe_u32 v24, v23, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX10-NEXT: v_add3_u32 v24, v24, v23, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc_lo +; GFX10-NEXT: v_perm_b32 v8, v30, v8, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 +; GFX10-NEXT: v_perm_b32 v7, v36, v7, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v23 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v24, v6, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX10-NEXT: v_perm_b32 v6, v37, v6, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v22 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX10-NEXT: v_max_f32_e32 v22, v22, v22 -; GFX10-NEXT: v_bfe_u32 v23, v22, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v24, 0x400000, v22 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX10-NEXT: v_add3_u32 v23, v23, v22, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v22 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v22, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX10-NEXT: v_max_f32_e32 v21, v21, v21 -; GFX10-NEXT: v_bfe_u32 v22, v21, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX10-NEXT: v_add3_u32 v22, v22, v21, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v23 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX10-NEXT: v_perm_b32 v5, v38, v5, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_perm_b32 v4, v50, v4, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX10-NEXT: v_max_f32_e32 v20, v20, v20 -; GFX10-NEXT: v_bfe_u32 v21, v20, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX10-NEXT: v_add3_u32 v21, v21, v20, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v21, v3, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_perm_b32 v3, v51, v3, 0x5040100 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX10-NEXT: v_perm_b32 v3, v39, v3, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v16 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 ; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX10-NEXT: v_max_f32_e32 v19, v19, v19 -; GFX10-NEXT: v_bfe_u32 v20, v19, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX10-NEXT: v_add3_u32 v20, v20, v19, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v20, v2, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_perm_b32 v2, v52, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX10-NEXT: v_max_f32_e32 v18, v18, v18 -; GFX10-NEXT: v_bfe_u32 v19, v18, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX10-NEXT: v_add3_u32 v19, v19, v18, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v18 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v23 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX10-NEXT: v_perm_b32 v1, v54, v1, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX10-NEXT: v_max_f32_e32 v17, v17, v17 -; GFX10-NEXT: v_bfe_u32 v18, v17, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX10-NEXT: v_add3_u32 v18, v18, v17, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v17 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 +; GFX10-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v55, v0, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX10-NEXT: v_perm_b32 v2, v48, v2, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX10-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX10-NEXT: v_perm_b32 v15, v49, v51, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_v32bf16: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: scratch_load_b32 v51, off, s32 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v69, v69 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v70, v70 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v18.h, v52.l, s25 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v52.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v80, v80 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v82.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v29 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v32, v32 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v38, v38 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134 +; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v30 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v13 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v11 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v10 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v112, v134 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v33, v33 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v13.h, v29.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v10.h, v26.h, s8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v82.l, v52.l, s44 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v55, v55 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v66, v66 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v67, v67 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v29.h, v15.l, s3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v9 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v30.h, v32.l, s2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v68, v68 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v39, v39 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v4.h, v20.h, s20 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v71, v71 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v5.h, v21.h, s18 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v26.h, v33.l, s9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v20.h, v39.l, s21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v33.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v55.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v66.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v80.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v48, v48 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v83, v83 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v3.h, v19.h, s22 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v21.h, v38.l, s19 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v102, v132 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v19.h, v48.l, s23 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v71.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v80.l, v39.l, s42 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v85, v115 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v55.l, v15.l, s23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v101, v131 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v102, v102, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s26 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v96, v118 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v50 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v101.l, v71.l, v38.l, s41 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v96.l, v66.l, v33.l, s26 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v85, v85, v85 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v30.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v0.h, v16.h, s29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v32.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v55.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v30 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v34, v34 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v54, v54 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v96, v96, v96 :: v_dual_lshlrev_b32 v101, 16, v101 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v31, v31 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v27 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v35, v35 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v30.h, v14.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v84, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v12.h, v28.h, s4 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v14.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v101, v101, v101 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v36, v36 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v54.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v37, v37 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v64, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v11.h, v27.h, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v28.h, v31.l, s5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v65, v65 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v27.h, v32.l, s7 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v64.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v84, v114 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.h, v25.h, s10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v32.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v5.h, v21.h, s19 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v4.h, v20.h, s21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v3.h, v19.h, s23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v16.h, v54.l, s40 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v65.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v15 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v14 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v29.h, v33.l, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v28.h, v34.l, s6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v27.h, v35.l, s8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v26.h, v36.l, s10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v25.h, v37.l, s12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v24.h, v38.l, s14 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v23.h, v39.l, s16 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v22.h, v48.l, s18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v21.h, v49.l, s20 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v20.h, v50.l, s22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v19.h, v51.l, s24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v54.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v86, v118 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v85.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v87, v87 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v96, v96 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v39.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v50.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v51.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v18.h, v52.l, s26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v17.h, v53.l, s28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v64.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v54.l, v14.l, s22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v8.h, v24.h, s12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v25.h, v34.l, s11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v86, v116 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.h, v23.h, s14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v34.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v24.h, v35.l, s13 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v67.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v87, v117 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v64.l, v31.l, s24 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v84, v84, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v6.h, v22.h, s16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v35.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v23.h, v36.l, s15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v68.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v65.l, v32.l, s25 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-TRUE16-NEXT: v_bfe_u32 v114, v84, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v22.h, v37.l, s17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v17.h, v53.l, s27 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v97, v97 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v32.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v37.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v53.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v69.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v97, v119 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v87, 16, v87 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, 0x400000, v84 -; GFX11-TRUE16-NEXT: v_bfe_u32 v116, v85, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v114, v114, v84, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v84, v84 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v84.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v119 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v128 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v129 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v130 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v131 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v132 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v133 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v134 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v135 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v144 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v145 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s63, v116, v86 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v55.l, v32.l, s40 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v13 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v55.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v70.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v98, v128 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v97.l, v67.l, v34.l, s27 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v87, v87, v87 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, 0x400000, v85 -; GFX11-TRUE16-NEXT: v_bfe_u32 v118, v86, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v116, v116, v85, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v114, v114, v115, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v85, v85 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v99, v129 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v68.l, v35.l, s28 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v146 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v147 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v87, v118 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v96, v119 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s45, v98, v129 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s56, v101, v132 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s59, v112, v135 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s60, v113, v144 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v86.l, v32.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v86.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v34.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v36.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v39.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v50.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v51.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s46, v99, v130 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s61, v114, v145 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s62, v115, v146 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v96.l, v65.l, v34.l, s43 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v67.l, v36.l, s45 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v101.l, v70.l, v39.l, s56 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v81.l, v50.l, s59 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v113.l, v82.l, v51.l, s60 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v55.l, s16 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v118 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v33.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v37.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v48.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v52.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v53.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v119, 0x400000, v86 -; GFX11-TRUE16-NEXT: v_bfe_u32 v128, v87, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v118, v118, v86, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v116, v116, v117, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v86, v86 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v48.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v81.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v100, v130 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v99.l, v69.l, v36.l, s29 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v97, v97, v97 :: v_dual_lshlrev_b32 v98, 16, v98 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v129, 0x400000, v87 -; GFX11-TRUE16-NEXT: v_bfe_u32 v130, v96, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v118, v118, v119, s22 -; GFX11-TRUE16-NEXT: v_add3_u32 v128, v128, v87, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v87, v87 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v70.l, v37.l, s40 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v98, v98, v98 :: v_dual_lshlrev_b32 v99, 16, v99 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v131, 0x400000, v96 -; GFX11-TRUE16-NEXT: v_bfe_u32 v132, v97, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v130, v130, v96, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v128, v128, v129, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v96, v96 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v103, v133 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v99, v99, v99 :: v_dual_lshlrev_b32 v100, 16, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v133, 0x400000, v97 -; GFX11-TRUE16-NEXT: v_bfe_u32 v134, v98, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v132, v132, v97, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v96, v130, v131, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v97, v97 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v100, v100, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v98 -; GFX11-TRUE16-NEXT: v_bfe_u32 v145, v99, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v134, v134, v98, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v97, v132, v133, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v98, v98 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v99 -; GFX11-TRUE16-NEXT: v_bfe_u32 v147, v100, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v145, v145, v99, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v100 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v98, v134, v144, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v99, v99 -; GFX11-TRUE16-NEXT: v_bfe_u32 v115, v101, 16, 1 -; GFX11-TRUE16-NEXT: v_add3_u32 v147, v147, v100, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v99, v145, v146, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v100, v100 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v101 -; GFX11-TRUE16-NEXT: v_add3_u32 v115, v115, v101, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v32.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v116.h, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v84, v147, v84, s22 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v101, v101 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v118.h, v31.l, s5 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v34.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v128.h, v32.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v33.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v35.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v97.h, v34.l, s7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v37.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v96.h, v33.l, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v98.h, v35.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v99.h, v36.l, s8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v38.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v85, v115, v85, s22 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v54.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v55.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v114.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v117, v102, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v64.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v102 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v102, v102 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v54.l, s11 -; GFX11-TRUE16-NEXT: v_add3_u32 v117, v117, v102, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v39.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v114 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v64.l, s13 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v65.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v86, v117, v86, s22 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v115, 0xffff0000, v128 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v53.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v66.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v83.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v103.l, v81.l, v48.l, s43 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v116 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v65.l, s14 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v115 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v71.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v70.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0x8000, v81.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v64.l, v33.l, s42 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v99.l, v68.l, v37.l, s46 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v114.l, v83.l, v52.l, s61 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v115.l, v84.l, v53.l, s62 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v96.l, v34.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v98.l, v36.l, s5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v101.l, v39.l, s8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v101.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v112.l, v50.l, s11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v112.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v113.l, v51.l, s12 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v113.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v55 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v38.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v49.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v54.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v97, v128 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v116.l, v85.l, v54.l, s63 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v87.l, v33.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v99.l, v37.l, s6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v114.l, v52.l, s13 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v114.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v115.l, v53.l, s14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v115.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v39 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v35.h, v81.l, s26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v35.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v102 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v67.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v68.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v98 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v103, v103, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v70.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v84 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s17 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v131 -; GFX11-TRUE16-NEXT: v_bfe_u32 v119, v103, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v103 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v132 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v96 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v80.l -; GFX11-TRUE16-NEXT: v_add3_u32 v119, v119, v103, 0x7fff -; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v97 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0x8000, v69.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v117 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v85 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v133 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s57, v102, v133 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v97.l, v66.l, v35.l, s44 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v116.l, v54.l, s15 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v116.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v51 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v48.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0x8000, v65.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v66.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s47, v100, v131 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s58, v103, v134 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v71.l, v48.l, s57 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v96.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v97.l, v35.l, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v97.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v52 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v38.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v49.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v64.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0x8000, v71.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v69.l, v38.l, s47 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v103.l, v80.l, v49.l, s58 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v87.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v102.l, v48.l, s9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v102.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v30.h, v65.l, s18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v128 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v66.l, s19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v129 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0x8000, v80.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0x8000, v85.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v38.l, s7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v103.l, v49.l, s10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v103.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v14.h, v64.l, s17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v119 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v34.h, v71.l, s24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v48 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v65 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v66 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v86.l, v13.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s25 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v49 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v37.h, v85.l, s41 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v64 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v71 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v96.l, v30.h, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v97.l, v32.l, s4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v67.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v68.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v98.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v99.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v87.l, v38.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v102.l, v38.h, s9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.h, v67.l, s20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v130 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s21 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v131 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0x8000, v84.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v70 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0x8000, v82.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v68 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v84.l, s29 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v101.l, v34.l, s8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0x8000, v83.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v80 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v82.l, s27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v115.l, v37.l, s14 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v69.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v36.h, v83.l, s28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v103.l, v35.l, s10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v113.l, v36.l, s12 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v100.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.h, v69.l, s22 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v81 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v114.l, v48.l, s13 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v132 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v69 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v33.h, s7 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v51 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v50.h, v51.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v31.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v118 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.h, v31.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v84.h, v37.l, s4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v85.h, v38.l, s9 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v101 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v32.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v129 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s19 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v130 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v99 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v35, v36 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v14.h, v55.l, s12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v86.h, v39.l, s10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v86 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v32.l, v31.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v100 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v118.h, v15.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v39 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s21 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v114.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v31.h, v66.l, s15 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v128.h, v15.h, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v32.h, v67.l, s16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v86.h, v35.l, s9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v96.h, v36.l, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v33.h, v69.l, s18 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v54, v38, v38 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v34.h, v71.l, s20 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v116.h, v35.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v98.h, v33.l, s5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v84.h, v34.l, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v97.h, v37.l, s4 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v130 -; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v99.h, v37.h, s6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v54, v55, v64, s11 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v64, v112, v112 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v54.h, v31.l, s10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v54 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v32.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v85.h, v38.l, s8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v54.h, v14.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v135 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v103, v103 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v113, v54 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v119, v87 :: v_dual_and_b32 v54, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v15.h, v31.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v83.l, v53.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v16 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v55.h, v48.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v81.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v15.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v0.h, v16.h, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v50.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v15.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v31.h, v50.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v31 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v98.l, v32.h, s5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v51.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v99.l, v33.l, s6 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v54, v65, v66, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v67 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v16.h, v15.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v81.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v54.h, v52.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v64, v64, v64 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v50.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v53 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v31.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v65 -; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v64, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v66 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v82.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX11-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v65 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v50 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.h, v55.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v64, v66, v67, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v53.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v68 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v64.h, v53.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.l, v50.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v52 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v51.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v50.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v38, v53 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v112.l, v39.l, s11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v51.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v14.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v30.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v50.l, v51.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v83.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.h, v54.h, v32.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v15.h, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v117, v117 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v31.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v116.l, v49.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v52, v52 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v51.l, v33.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v34.l, v83.l, s1 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v52, v52, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v14.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v64 -; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v52, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v49.l, v30.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX11-TRUE16-NEXT: v_add3_u32 v49, v66, v52, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v52 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v65, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v34.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v64.h, v32.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.l, v33.l, s1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v30.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v49, v53, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v34.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v32.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v30.l, v14.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v29.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v15.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v52 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v31.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v52, v55, v55 :: v_dual_and_b32 v53, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v34.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v13.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v29.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v31.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v15.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v52, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v13.h, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v12 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v29.l, v13.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v52, v54, v65, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v33.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v53, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v15.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v52.h, v33.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v49, v54, v55, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v34.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v52 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v12.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v14.l, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v53, v53, v53 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v34.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v31.l, v14.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v64 -; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v53, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v49 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v64, v65, v53, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v53 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v66 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v28.l, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v53, v64, v65, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v52, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v30.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v29.l, v13.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v31.l, v12.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v30.l, v13.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v14.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v53.h, v13.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v29.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v55 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v27.l, v11.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v11.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v28.l, v12.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v53 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v49, v49, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v52.h, v12.h, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v49, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v29 -; GFX11-TRUE16-NEXT: v_add3_u32 v27, v55, v49, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v49 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v54, v52 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v53.h, v11.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v26.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v27, v29, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v13.l, v11.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v29.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v49 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v28.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v27, v12, v12 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v28.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v25.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v9.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; GFX11-TRUE16-NEXT: v_add3_u32 v28, v28, v27, 0x7fff +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v31.l, v12.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v28.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v31.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v29.h, v9.h, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v27, v28, v53, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8 -; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v12, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v27.h, v11.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX11-TRUE16-NEXT: v_add3_u32 v29, v29, v12, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v30.l, v11.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.h, v28.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v27.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v12.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v26.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v26.l, v11.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v52 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v51, v50 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v31.l, v10.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v27.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v12.l, v10.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v9.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v26.l, v9.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v25.l, v10.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v25.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v26 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v29, v49, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v24.l, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v12.h, v10.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v28, v28 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v11.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v13.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v26.l, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v10, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v26 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v52, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v12.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v24.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v10.l, v9.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v8.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v12.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v24.h, v9.l, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v25.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v27.h, v8.h, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v25.l, s2 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.h, v9.h, s1 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v27, v10, v10 :: v_dual_and_b32 v26, 0xffff0000, v24 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v27, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v27, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v22.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v24.h, v7.h, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v27 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v25.l, v8.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v11.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v12.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v22.h, v8.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v25, v8, v8 :: v_dual_lshlrev_b32 v24, 16, v21 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v11.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v22 -; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v25, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v6.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v11.l, v8.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v26 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v25, v24 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v22.l, v6.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v10.l, v7.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.h, v12.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v24, v25, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v25 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v22.h, v5.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v21, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v11.h, v7.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v11.l, v6.h, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v10.l, v7.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v10.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v11 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v21 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v9.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v22, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v9, v21 :: v_dual_lshlrev_b32 v9, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v21.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v7.l, v6.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v8.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v11.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.h, v12.l, vcc_lo -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v6, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v4.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v19 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v12, v20, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_and_b32 v11, 0xffff0000, v8 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v9.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v10.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v10.l, v5.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v8.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v18 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v8.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.h, v4.h, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v19, v20, s3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v3.h, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.h, v4.l, s3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v17 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v20 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v9.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v6.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v17.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v16.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v4.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v7.l, v4.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v18.l, v2.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v8.l, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v17 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v3.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.l, v0.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v12, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v1.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v2.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v12 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v19, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v17, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v12, v16, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v17, 16, 1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v12.h, v3.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v16, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v17 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo -; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v8, s0 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v10, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.h, v2.l, s0 -; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v12 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v10, v17, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v18, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v17 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v12.h, v1.h, s2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v11.h, v0.h, s3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v5.h, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v3.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v7.h, v2.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v7.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v30 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v5.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v2.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v8.l, v1.h, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v6.l, v0.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v9.l, v2.h, s3 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v50 :: v_dual_mov_b32 v4, v48 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v13 :: v_dual_mov_b32 v1, v30 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v51 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v39 :: v_dual_mov_b32 v6, v38 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v37 :: v_dual_mov_b32 v8, v35 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v33 :: v_dual_mov_b32 v10, v32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v31 :: v_dual_mov_b32 v12, v36 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v34 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v37 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v32bf16: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v29 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: scratch_load_b32 v50, off, s32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v52, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v39, v64, v55 :: v_dual_and_b32 v70, 0xffff0000, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v68, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v80, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v84, v83, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v96, v87, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v100, v99, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v112, v103 :: v_dual_and_b32 v81, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v116, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v128, v119, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v66, v66 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v82, v132, v131 :: v_dual_and_b32 v113, 0xffff0000, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v84, v144, v135 :: v_dual_and_b32 v117, 0xffff0000, v20 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v102, v144, v135, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v34, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v147, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v36, v36, v35, s3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v14, v30, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v51, v51, v52 :: v_dual_lshlrev_b32 v118, 16, v102 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v51 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v51 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v54, v54 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v52 :: v_dual_lshlrev_b32 v118, 16, v67 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v38 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v54, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v64 :: v_dual_lshlrev_b32 v128, 16, v83 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v97, v99, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v103, v68, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v39 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v101, v115, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v113 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v34 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v49 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v87 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v103, v119, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v115, v119, v98, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v71 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v103 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v113, v131, v82, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v86, v114 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v52 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v99 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v113 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v115 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v48, v116 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v85, 16, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v114, v86, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v86 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v55 -; GFX11-FAKE16-NEXT: v_add3_u32 v114, v114, v86, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v48, v48, v48 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v117 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v118 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v66 -; GFX11-FAKE16-NEXT: v_bfe_u32 v118, v48, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v119 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v70 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v102, 16, v80 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v71, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v81, v128 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v68 -; GFX11-FAKE16-NEXT: v_add3_u32 v118, v118, v48, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v128, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v85, v129 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v82 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_add3_u32 v128, v128, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v64, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v81, v81, v81 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v81 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v97 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v85, v85, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v96, v130 -; GFX11-FAKE16-NEXT: v_bfe_u32 v146, v85, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v147, 0x400000, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v97, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v98, v131 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v50, v147, v38 :: v_dual_lshlrev_b32 v49, 16, v52 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v39 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v129, v30, v66 :: v_dual_lshlrev_b32 v30, 16, v35 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v49, v130 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v35, v36, s0 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v37, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v51, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add3_u32 v146, v146, v85, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v101 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v99, v68, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v100, v132 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v96, v96, v96 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v100, v101, v70, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v102, v133 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v98, v98, v98 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v102, v103, v80, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v112, v134 -; GFX11-FAKE16-NEXT: v_bfe_u32 v134, v81, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v100, v100, v100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v82, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 -; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v96, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v134, v134, v81, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v114, v114, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v96 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v86, v86, v96, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v69, v69, v69 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v132, v69, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v133, 0x400000, v69 -; GFX11-FAKE16-NEXT: v_add3_u32 v132, v132, v69, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v36, v36, v36 -; GFX11-FAKE16-NEXT: v_bfe_u32 v116, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v116, v116, v36, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v98, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v116, v116, v117, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v98 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v100, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v98, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v118, v118, v119 :: v_dual_max_f32 v65, v65, v65 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v100 -; GFX11-FAKE16-NEXT: v_add3_u32 v48, v48, v100, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v130, v65, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v131, 0x400000, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v128, v129, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v130, v130, v65, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v130, v131, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v132, v133, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v134, v144, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v146, v147, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v115, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v118 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v114 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v117, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v100, v100 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v116 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v128 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v48, v119, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v114 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v116 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v116, 0xffff0000, v118 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v48, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v128 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v100, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v115, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v117, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v119, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v34, v39, v48, s0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v131 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v54, 16, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v132 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v133 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v81, v134 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v85, v135 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v85, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v81 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v97, v144 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v101, v145 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v112, v146 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v112, v113, v96 :: v_dual_lshlrev_b32 v49, 16, v117 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v114, v147 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v119 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v116, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v118, v130 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v37 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v128, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v50, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v34, v48, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v128, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v130, v54 :: v_dual_and_b32 v65, 0xffff0000, v65 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v37, v52, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v131, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v147, v32, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v132, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v133, v68 :: v_dual_and_b32 v81, 0xffff0000, v81 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v54, v147 :: v_dual_and_b32 v85, 0xffff0000, v85 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v70 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v144, v70, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v80 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v86 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v96 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v98 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v49, 16, v34 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v133, 16, v69 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v102 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v147 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v102, v102, v102 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v128, v38 :: v_dual_lshlrev_b32 v135, 16, v85 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v102, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v102 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v34, v68 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v102, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v54, v147, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v48, v52, v51 :: v_dual_lshlrev_b32 v145, 16, v101 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v37, v37, v55 :: v_dual_lshlrev_b32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v64, v55 :: v_dual_lshlrev_b32 v147, 16, v114 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v34, v34, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v39, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v51, 16, v128 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83 -; GFX11-FAKE16-NEXT: v_add3_u32 v55, v55, v34, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v52, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v87 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v87, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v97 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v31, v97, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v99 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v32, v99, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v98 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v48, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v100, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v116 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v115, v36 :: v_dual_and_b32 v86, 0xffff0000, v86 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v118 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v117, v37, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v96 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v119, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v69 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v128, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v130, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0x8000, v147 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v147, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v85 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v131, v51, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v86 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v132, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v133, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v112 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v67, v51, v51 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v135, v84, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v52, v53, v129 :: v_dual_lshlrev_b32 v55, 16, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v84 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v101 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v101, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v52 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v54, v84, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v80 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v66, v80, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v80, 16, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v144, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v67, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v103 -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v67, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v103, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v70, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v66, v55, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v69, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v67 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v65, v82 :: v_dual_lshlrev_b32 v70, 16, v55 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v68, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v70 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v55, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v15, v50 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v86, v103, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v113 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v113 :: v_dual_lshlrev_b32 v80, 16, v68 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v68, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v70, v84, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v65, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v80, v71 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v65, v50, v68 :: v_dual_lshlrev_b32 v80, 16, v30 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v14, v30, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v65, v65, v65 :: v_dual_max_f32 v66, v66, v66 -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v66, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v66 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v66, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v64, v71 :: v_dual_lshlrev_b32 v71, 16, v13 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v70, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v69 -; GFX11-FAKE16-NEXT: v_bfe_u32 v54, v65, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v67, v53, v67 :: v_dual_lshlrev_b32 v66, 16, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v54, v54, v65, 0x7fff -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v70, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v30, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v13, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v29 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v80, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v29, v71, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v67, v55, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v65 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v66 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v54 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v66, v13, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v53, v29 :: v_dual_lshlrev_b32 v70, 16, v71 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v68, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v70, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v117 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v119 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v66, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v50, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v54 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v53, v66, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v50, v50, v53 :: v_dual_max_f32 v53, v55, v55 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v53 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v38, v50, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v130 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v15, v31, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v50 :: v_dual_lshlrev_b32 v64, 16, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v50, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v31, v53 :: v_dual_lshlrev_b32 v55, 16, v52 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v54 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v55 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v52, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v65 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v54, v53 :: v_dual_lshlrev_b32 v65, 16, v55 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v64, v53, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v66 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v53, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v129 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v54, 16, v12 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v129, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v53, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v53, v66, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v12 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v69 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0x8000, v129 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v55, v129, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v64 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v66, v65 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v54, v69, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v12 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v64, v67 :: v_dual_lshlrev_b32 v68, 16, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v28, v12 :: v_dual_lshlrev_b32 v67, 16, v11 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v27, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v55, v30, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v68, v30, v71 :: v_dual_lshlrev_b32 v55, 16, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v66 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v67, v64 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v54, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v68, v65 :: v_dual_max_f32 v55, v55, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v55, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v55 -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v50, v55, 0x7fff -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v67, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v65, v26, v10 :: v_dual_lshlrev_b32 v64, 16, v64 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v64, v64, v64 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v30, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v50 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v65 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v30, v12 :: v_dual_lshlrev_b32 v67, 16, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v67, v55 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v65, v10 :: v_dual_lshlrev_b32 v55, 16, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX11-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v53 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v54, 16, v26 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v25 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v54, v54, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v25, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v54, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v54, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v64, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 +; GFX11-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v24, v8 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v50, 16, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v50, v50, v50 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v50, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v53, v66, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v53, v53, v53 :: v_dual_and_b32 v50, 0xffff0000, v50 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v65 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v53, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v54, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v23, v7 :: v_dual_lshlrev_b32 v55, 16, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v26, 16, v8 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_add3_u32 v25, v28, v53, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v53 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v28, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v8 :: v_dual_lshlrev_b32 v29, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v54, v9 :: v_dual_lshlrev_b32 v64, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v5 -; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_perm_b32 v9, v36, v9, 0x5040100 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v23, v7 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v50, v8 :: v_dual_lshlrev_b32 v55, 16, v22 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v22, v6 :: v_dual_lshlrev_b32 v54, 16, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 -; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v24 :: v_dual_lshlrev_b32 v53, 16, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v28 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v24, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v50, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v26, v8 :: v_dual_lshlrev_b32 v25, 16, v22 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v25, v7 :: v_dual_lshlrev_b32 v50, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v21, v5 :: v_dual_lshlrev_b32 v53, 16, v20 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v30, v30, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v50 :: v_dual_lshlrev_b32 v50, 16, v20 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v20, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v28, 16, v50 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v22 :: v_dual_lshlrev_b32 v53, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v22, v28, v28 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v3 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v22, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v28, v5 :: v_dual_lshlrev_b32 v50, 16, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX11-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v22, 0x7fff -; GFX11-FAKE16-NEXT: v_perm_b32 v8, v37, v8, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v17 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v19, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v30, v54 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v21, v21, v21 :: v_dual_lshlrev_b32 v30, 16, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v28, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v21, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v22 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v24, v21, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v28, 16, v18 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v18, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v24, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v17, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v22 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v24, v28, v28 :: v_dual_lshlrev_b32 v25, 16, v25 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v16, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v24, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v25, v25, v25 :: v_dual_lshlrev_b32 v22, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v24, v3 :: v_dual_lshlrev_b32 v20, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v25, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_max_f32_e32 v19, v22, v22 -; GFX11-FAKE16-NEXT: v_add3_u32 v22, v28, v24, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_add3_u32 v24, v50, v25, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v19, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add3_u32 v50, v53, v19, 0x7fff -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v22 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v50, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v20, 16, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v20 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v17, v1 :: v_dual_lshlrev_b32 v25, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v21, v1 :: v_dual_and_b32 v16, 0xffff0000, v22 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX11-FAKE16-NEXT: v_perm_b32 v1, v14, v1, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX11-FAKE16-NEXT: v_perm_b32 v14, v31, v27, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v0, v13, v0, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX11-FAKE16-NEXT: v_perm_b32 v13, v32, v26, 0x5040100 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_perm_b32 v2, v15, v2, 0x5040100 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_perm_b32 v15, v39, v29, 0x5040100 -; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_minimumnum_v32bf16: @@ -16962,2105 +13016,1548 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-TRUE16-NEXT: scratch_load_b32 v51, off, s32 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v69, v69 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v70, v70 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v14 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v13 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v18.h, v52.l, s25 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v52.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v80, v80 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v82.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v29 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v32, v32 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v38, v38 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134 +; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v30 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v112, v134 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v33, v33 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v13.h, v29.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v10.h, v26.h, s8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v82.l, v52.l, s44 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v55, v55 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v66, v66 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v67, v67 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v29.h, v15.l, s3 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v68, v68 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v39, v39 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v4.h, v20.h, s20 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v71, v71 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v5.h, v21.h, s18 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v15.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v26.h, v33.l, s9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v20.h, v39.l, s21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v33.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v55.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v66.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v80.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v48, v48 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v83, v83 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v3.h, v19.h, s22 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v21.h, v38.l, s19 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v102, v132 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v19.h, v48.l, s23 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v71.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v13 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v80.l, v39.l, s42 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v85, v115 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s1 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v11 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v10 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v9 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v55.l, v15.l, s23 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v101, v131 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v102, v102, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v53, v53 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s26 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v96, v118 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v50 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v101.l, v71.l, v38.l, s41 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v28 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.l, v66.l, v33.l, s26 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v85, v85, v85 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v30.h, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v30 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v34, v34 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v54, v54 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v96, v96, v96 :: v_dual_lshlrev_b32 v101, 16, v101 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v31, v31 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v27 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v35, v35 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v30.h, v14.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v84, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v12.h, v28.h, s4 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v14.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v101, v101, v101 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v36, v36 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v54.l ; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v37, v37 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v64, v64 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v4 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v16 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v30.h, v32.l, s2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v29 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v28 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v27 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v25 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v23 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v22 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v21 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v20 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v19 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v11.h, v27.h, s6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v28.h, v31.l, s5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v65, v65 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v31.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v27.h, v32.l, s7 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v64.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v84, v114 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.h, v25.h, s10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v0.h, v16.h, s29 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v32.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v55.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v18 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v17 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s15 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v5.h, v21.h, s19 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v4.h, v20.h, s21 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v3.h, v19.h, s23 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v16.h, v54.l, s40 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v65.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v15 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v14 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v2.h, v18.h, s25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v1.h, v17.h, s27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v29.h, v33.l, s4 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v28.h, v34.l, s6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v27.h, v35.l, s8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v26.h, v36.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v25.h, v37.l, s12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v24.h, v38.l, s14 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v23.h, v39.l, s16 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v22.h, v48.l, s18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v21.h, v49.l, s20 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v20.h, v50.l, s22 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v19.h, v51.l, s24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v54.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v86, v118 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v85.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v30 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v87, v87 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v96, v96 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v39.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v50.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v51.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v18.h, v52.l, s26 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v17.h, v53.l, s28 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v64.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v97, v97 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v54.l, v14.l, s22 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v8.h, v24.h, s12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v25.h, v34.l, s11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v32.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v37.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v53.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v86, v116 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.h, v23.h, s14 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v34.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v24.h, v35.l, s13 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v67.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v87, v117 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v64.l, v31.l, s24 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v84, v84, v84 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v6.h, v22.h, s16 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v35.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v23.h, v36.l, s15 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v68.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v65.l, v32.l, s25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 -; GFX12-TRUE16-NEXT: v_bfe_u32 v114, v84, 16, 1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v36.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v22.h, v37.l, s17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v17.h, v53.l, s27 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v69.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v97, v119 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v87, 16, v87 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v115, 0x400000, v84 -; GFX12-TRUE16-NEXT: v_bfe_u32 v116, v85, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v114, v114, v84, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v84, v84 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v147.l, v84.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v119 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v128 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v129 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v130 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v131 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v132 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v133 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v134 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v135 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v144 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v145 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s63, v116, v86 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v55.l, v32.l, s40 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v55.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v70.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v98, v128 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v97.l, v67.l, v34.l, s27 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v87, v87, v87 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v117, 0x400000, v85 -; GFX12-TRUE16-NEXT: v_bfe_u32 v118, v86, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v116, v116, v85, 0x7fff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v114, v114, v115, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v85, v85 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v99, v129 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v68.l, v35.l, s28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v119, 0x400000, v86 -; GFX12-TRUE16-NEXT: v_bfe_u32 v128, v87, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v118, v118, v86, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v116, v116, v117, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v86, v86 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v48.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v81.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v100, v130 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v99.l, v69.l, v36.l, s29 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v97, v97, v97 :: v_dual_lshlrev_b32 v98, 16, v98 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v129, 0x400000, v87 -; GFX12-TRUE16-NEXT: v_bfe_u32 v130, v96, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v118, v118, v119, s22 -; GFX12-TRUE16-NEXT: v_add3_u32 v128, v128, v87, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v87, v87 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v70.l, v37.l, s40 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v98, v98, v98 :: v_dual_lshlrev_b32 v99, 16, v99 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v131, 0x400000, v96 -; GFX12-TRUE16-NEXT: v_bfe_u32 v132, v97, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v130, v130, v96, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v128, v128, v129, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v96, v96 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v103, v133 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v99, v99, v99 :: v_dual_lshlrev_b32 v100, 16, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v133, 0x400000, v97 -; GFX12-TRUE16-NEXT: v_bfe_u32 v134, v98, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v132, v132, v97, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v96, v130, v131, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v97, v97 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v100, v100, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v98 -; GFX12-TRUE16-NEXT: v_bfe_u32 v145, v99, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v134, v134, v98, 0x7fff +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v146 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v147 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v87, v118 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v96, v119 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s45, v98, v129 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s56, v101, v132 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s59, v112, v135 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s60, v113, v144 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v97, v132, v133, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v98, v98 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v99 -; GFX12-TRUE16-NEXT: v_bfe_u32 v147, v100, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v145, v145, v99, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v100 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v86.l, v32.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v86.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v34.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v36.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v39.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v50.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v51.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s46, v99, v130 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s61, v114, v145 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s62, v115, v146 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.l, v65.l, v34.l, s43 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v67.l, v36.l, s45 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v101.l, v70.l, v39.l, s56 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v81.l, v50.l, s59 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v113.l, v82.l, v51.l, s60 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v55.l, s16 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v118 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v33.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v37.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v48.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v52.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v53.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v70.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0x8000, v81.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v64.l, v33.l, s42 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v98, v134, v144, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v99, v99 -; GFX12-TRUE16-NEXT: v_bfe_u32 v115, v101, 16, 1 -; GFX12-TRUE16-NEXT: v_add3_u32 v147, v147, v100, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v31.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v99.l, v68.l, v37.l, s46 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v114.l, v83.l, v52.l, s61 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v115.l, v84.l, v53.l, s62 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v96.l, v34.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v98.l, v36.l, s5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v101.l, v39.l, s8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v39.l, v101.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v112.l, v50.l, s11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v112.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v113.l, v51.l, s12 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v113.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v55 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v38.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v49.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v54.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v97, v128 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v116.l, v85.l, v54.l, s63 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v87.l, v33.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v99.l, v37.l, s6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v114.l, v52.l, s13 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v114.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v115.l, v53.l, s14 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v115.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v39 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v35.h, v81.l, s26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v35.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s57, v102, v133 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v99, v145, v146, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v100, v100 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v101 -; GFX12-TRUE16-NEXT: v_add3_u32 v115, v115, v101, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v32.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v116.h, v15.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v97.l, v66.l, v35.l, s44 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v116.l, v54.l, s15 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v116.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v51 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v48.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0x8000, v65.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v66.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s47, v100, v131 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s58, v103, v134 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v71.l, v48.l, s57 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v96.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v97.l, v35.l, s4 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v97.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v52 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v38.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v49.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v64.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0x8000, v71.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v84, v147, v84, s22 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v101, v101 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v118.h, v31.l, s5 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v34.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v128.h, v32.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v33.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v35.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v36.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v69.l, v38.l, s47 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v103.l, v80.l, v49.l, s58 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v87.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v102.l, v48.l, s9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v48.l, v102.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v30.h, v65.l, s18 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v128 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v66.l, s19 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v129 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0x8000, v80.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0x8000, v85.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v38.l, s7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v103.l, v49.l, s10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v103.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v14.h, v64.l, s17 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v119 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v34.h, v71.l, s24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v48 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v65 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v66 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v86.l, v13.h, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v97.h, v34.l, s7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v37.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v96.h, v33.l, s6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v98.h, v35.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v99.h, v36.l, s8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v38.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v85, v115, v85, s22 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v54.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v55.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s25 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v49 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v37.h, v85.l, s41 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v64 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v71 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v96.l, v30.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v97.l, v32.l, s4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v67.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v68.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v98.l +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v99.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v114.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v117, v102, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v64.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v102 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v102, v102 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v54.l, s11 -; GFX12-TRUE16-NEXT: v_add3_u32 v117, v117, v102, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v39.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v114 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v87.l, v38.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v102.l, v38.h, s9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.h, v67.l, s20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v130 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s21 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v131 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0x8000, v84.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v70 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v67 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0x8000, v82.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v68 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v64.l, s13 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v65.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v86, v117, v86, s22 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v115, 0xffff0000, v128 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v53.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v66.l -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v83.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v103.l, v81.l, v48.l, s43 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v116 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v84.l, s29 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v101.l, v34.l, s8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0x8000, v83.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v80 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v82.l, s27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v115.l, v37.l, s14 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v69.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v65.l, s14 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v115 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v71.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v102 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v67.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v68.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v98 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v103, v103, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v70.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v84 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v36.h, v83.l, s28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v103.l, v35.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v113.l, v36.l, s12 +; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v100.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.h, v69.l, s22 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v81 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v114.l, v48.l, s13 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v132 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v69 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v68.l, s17 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v131 -; GFX12-TRUE16-NEXT: v_bfe_u32 v119, v103, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v103 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v132 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v96 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v80.l -; GFX12-TRUE16-NEXT: v_add3_u32 v119, v119, v103, 0x7fff -; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v97 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0x8000, v69.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v117 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v85 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v133 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v100.l, v33.h, s7 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v51 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v50.h, v51.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v31.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v118 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.h, v31.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v34 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v84.h, v37.l, s4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v85.h, v38.l, s9 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v101 -; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v32.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v129 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v70.l, s19 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v130 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v99 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v35, v36 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v14.h, v55.l, s12 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v86.h, v39.l, s10 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v86 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v31.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v32.l, v31.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v100 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v118.h, v15.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v39 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v80.l, s21 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l +; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v114.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v31.h, v66.l, s15 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v128.h, v15.h, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v37 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v32.h, v67.l, s16 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v86.h, v35.l, s9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v96.h, v36.l, s3 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v33.h, v69.l, s18 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v54, v38, v38 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v34.h, v71.l, s20 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v116.h, v35.h, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v98.h, v33.l, s5 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v84.h, v34.l, s7 -; GFX12-TRUE16-NEXT: v_bfe_u32 v55, v54, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v97.h, v37.l, s4 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v130 -; GFX12-TRUE16-NEXT: v_add3_u32 v55, v55, v54, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v99.h, v37.h, s6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v54, v55, v64, s11 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v64, v112, v112 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v54.h, v31.l, s10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v15.h, v31.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v54 -; GFX12-TRUE16-NEXT: v_bfe_u32 v65, v64, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v64 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v32.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v39 -; GFX12-TRUE16-NEXT: v_add3_u32 v65, v65, v64, 0x7fff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v85.h, v38.l, s8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v54.h, v14.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v135 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v103, v103 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v113, v54 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v55, v119, v87 :: v_dual_and_b32 v54, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v83.l, v53.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v50.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v15.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v55.h, v48.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v81.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v15.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v0.h, v16.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v31.h, v50.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v31 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v98.l, v32.h, s5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v51.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v99.l, v33.l, s6 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v54, v65, v66, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v67 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v55 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v16.h, v15.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v81.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v54.h, v52.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v64, v64, v64 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v50.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v53 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v31.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v65 -; GFX12-TRUE16-NEXT: v_bfe_u32 v67, v64, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v66 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v82.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v64, v64 -; GFX12-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v65 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v50 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v54 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.h, v55.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v64, v66, v67, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v53.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v51 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v68 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v51.l, v50.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v52 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v51.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v50.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v38, v53 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v112.l, v39.l, s11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v64.h, v53.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v15.h, v51.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v31.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v14.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v30.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v33.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v50.l, v51.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v83.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.h, v54.h, v32.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v49 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v51.l, v33.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v65.l, v33.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v34.l, v83.l, s1 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v52, v52, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v14.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v64 -; GFX12-TRUE16-NEXT: v_bfe_u32 v66, v52, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v32.l, v15.h, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v117, v117 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v31.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v49.l, v30.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX12-TRUE16-NEXT: v_add3_u32 v49, v66, v52, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v52 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v65, v55 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v34.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v116.l, v49.l, vcc_lo +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v64.h, v32.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.l, v33.l, s1 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v30.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v49, v49, v53, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v34.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v32.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v30.l, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v29.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v31.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v54, v54 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v15.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v52 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v31.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v31.l, v14.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v52, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s0 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v52, v55, v55 :: v_dual_and_b32 v53, 0xffff0000, v49 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v34.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v13.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v29.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.h, v31.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v15.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v64 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-TRUE16-NEXT: v_bfe_u32 v54, v52, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v49.h, v13.h, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v12 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX12-TRUE16-NEXT: v_add3_u32 v54, v54, v52, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v53, v53, v53 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v30.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v29.l, v13.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v15.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v29.l, v13.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v31.l, v12.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v52, v54, v65, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v54, v53, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v33.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; GFX12-TRUE16-NEXT: v_add3_u32 v54, v54, v53, 0x7fff -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v15.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v30.l, v13.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v52.h, v33.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v49, v54, v55, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v34.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v52 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v12.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v53 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v29.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.h, v14.l, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v53, v53, v53 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v34.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v64 -; GFX12-TRUE16-NEXT: v_bfe_u32 v65, v53, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v28.l, v12.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v49 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v64, v65, v53, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v53 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v66 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v28.l, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v53, v64, v65, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v15.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v49.h, v14.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v31.l, v12.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v28.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v31.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v53.h, v13.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v29.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v55 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v52 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v27.l, v11.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v11.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v30.l, v11.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.h, v28.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.h, v29.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v53 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v49, v49, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v13.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v52.h, v12.h, s0 -; GFX12-TRUE16-NEXT: v_bfe_u32 v55, v49, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v29 -; GFX12-TRUE16-NEXT: v_add3_u32 v27, v55, v49, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v49 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v54, v52 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v27.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v12.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v26.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v53.h, v11.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v26.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v29, v27, v29, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v13.l, v11.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v29.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v53, v53 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v49 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v28.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v27, v12, v12 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v26.l, v11.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v52 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v51, v50 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v31.l, v10.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v26.l, v10.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v28.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v28, v27, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v25.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v9.l -; GFX12-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; GFX12-TRUE16-NEXT: v_add3_u32 v28, v28, v27, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v27.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v12.l, v10.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v9.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v29.h, v9.h, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v52, v49 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v27, v28, v53, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v29, v12, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v26.l, v9.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v27.h, v11.l, s0 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v25.l, v9.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24 -; GFX12-TRUE16-NEXT: v_add3_u32 v29, v29, v12, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v13.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v25.l, v10.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v24 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v25.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v26 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v29, v49, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v10.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v24.l, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v12.h, v10.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v28, v28 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v11.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v13.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.h, v26.l, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v10, 16, 1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_add3_u32 v24, v24, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v26 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v24, v24, v52, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.h, v12.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v49 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v24.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v24.h, v9.l, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v25.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v27.h, v8.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v10.l, v9.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v8.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v12.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v25.l, s2 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.h, v9.h, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v27, v10, v10 :: v_dual_and_b32 v26, 0xffff0000, v24 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX12-TRUE16-NEXT: v_bfe_u32 v25, v27, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v27 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v23, v25, v27, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v27 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v25.l, v8.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v22.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v24.h, v7.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v11.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, v11.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v12.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v22.h, v8.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v25, v8, v8 :: v_dual_lshlrev_b32 v24, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v11.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v22 -; GFX12-TRUE16-NEXT: v_bfe_u32 v24, v25, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v11.l, v8.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v26 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v25, v24 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v6.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v22.l, v6.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v10.l, v7.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.h, v12.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v24, v25, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v25 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v5.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v22.h, v5.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, v21, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v7.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v11.l, v6.h, vcc_lo +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v11.h, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v10.l, v7.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v10.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v11 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v21 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX12-TRUE16-NEXT: v_bfe_u32 v22, v8, 16, 1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v9.l, s1 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v22, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_dual_cndmask_b32 v8, v9, v21 :: v_dual_lshlrev_b32 v9, 16, v22 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v20 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v8.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v11.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v20 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v8.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, v9.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v5.h, v12.l, vcc_lo -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v6, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v21.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v4.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v19 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v7.l, v6.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v7.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v21 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v10.l, v5.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v12, v20, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_and_b32 v11, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v20.l, v4.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v8.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v8.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v9.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v20 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v12, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, v10.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v19.l, v3.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v9.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v18 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v6.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.h, v4.h, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v7.l, v4.h, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v19, v20, s3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v18.l, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v3.h, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v8.l, v2.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, v6.l, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.h, v4.l, s3 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v17 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v3.l, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v17 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v16 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v17.l, v1.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v3.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.l, v0.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v12, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v3.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v6.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v16.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v2.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v19, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v12 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v19, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v17, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v4.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v9.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v12, v16, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v16, v17, 16, 1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v12.h, v3.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v16, v17, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v17 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v2.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v17, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v3 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, v8, s0 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v10, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16 -; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.h, v2.l, s0 -; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v4.l, s1 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v2.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v10, v17, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v18, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v7.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v17 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v12.h, v1.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v11.h, v0.h, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v11, v30 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v5.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v5.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v3.h, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v7.h, v2.l, s1 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v3, v50 :: v_dual_mov_b32 v4, v48 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v13 :: v_dual_mov_b32 v1, v30 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v51 :: v_dual_mov_b32 v5, v39 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v37 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v35 :: v_dual_mov_b32 v9, v33 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v32 :: v_dual_mov_b32 v11, v31 -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v12, v36 :: v_dual_mov_b32 v13, v34 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v2.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v8.l, v1.h, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v6.l, v0.h, s2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v9.l, v2.h, s3 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34 +; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v10, v31 +; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v32bf16: ; GFX12-FAKE16: ; %bb.0: -; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0 -; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 -; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 -; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v29 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: scratch_load_b32 v50, off, s32 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v52, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0 +; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 +; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s0 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v39, v64, v55 :: v_dual_and_b32 v70, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v68, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v80, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v84, v83, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v96, v87, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v100, v99, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v112, v103 :: v_dual_and_b32 v81, 0xffff0000, v25 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v116, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v66, v66 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v128, v119, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v0 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v82, v132, v131 :: v_dual_and_b32 v113, 0xffff0000, v21 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v84, v144, v135 :: v_dual_and_b32 v117, 0xffff0000, v20 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v102, v144, v135, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v34, v34 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v147, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v33 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v36, v36, v35, s3 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 +; GFX12-FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v14, v30, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v37, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v51, v51, v52 :: v_dual_lshlrev_b32 v118, 16, v102 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v51 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v51 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v54, v54 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v39, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v49, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v38 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v52 :: v_dual_lshlrev_b32 v118, 16, v67 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v54, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v64 :: v_dual_lshlrev_b32 v128, 16, v83 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v97, v99, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v103, v68, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v39 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v101, v115, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo +; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v113 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v34 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v38 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v49 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v103, v119, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v115, v119, v98, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v35 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v71 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v103 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v131, v82, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v86, v114 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v52 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v99 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v113 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v33, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v115 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v48, v116 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v86, v86, v86 :: v_dual_lshlrev_b32 v85, 16, v64 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_bfe_u32 v114, v86, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v86 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v55 -; GFX12-FAKE16-NEXT: v_add3_u32 v114, v114, v86, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v48, v48, v48 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v117 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v118 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v66 -; GFX12-FAKE16-NEXT: v_bfe_u32 v118, v48, 16, 1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v49, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v119 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v70 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v102, 16, v80 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v48 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v71, v52, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v81, v128 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v68 -; GFX12-FAKE16-NEXT: v_add3_u32 v118, v118, v48, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v128, v53, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v85, v129 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v82 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v53 -; GFX12-FAKE16-NEXT: v_add3_u32 v128, v128, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v64, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v81, v81, v81 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v81 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v97 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v85, v85, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v96, v130 -; GFX12-FAKE16-NEXT: v_bfe_u32 v146, v85, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v147, 0x400000, v85 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v97, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v98, v131 -; GFX12-FAKE16-NEXT: v_add3_u32 v146, v146, v85, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v101 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v99, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v100, v132 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v96, v96, v96 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v101, v70, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v102, v133 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v98, v98, v98 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v102, v103, v80, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v112, v134 -; GFX12-FAKE16-NEXT: v_bfe_u32 v134, v81, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v100, v100, v100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v82, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86 -; GFX12-FAKE16-NEXT: v_bfe_u32 v86, v96, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v134, v134, v81, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v114, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v115, 0x400000, v96 -; GFX12-FAKE16-NEXT: v_add3_u32 v86, v86, v96, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v69, v69, v69 -; GFX12-FAKE16-NEXT: v_bfe_u32 v132, v69, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v133, 0x400000, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v132, v132, v69, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v36, v36, v36 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v116, v36, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v36 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX12-FAKE16-NEXT: v_add3_u32 v116, v116, v36, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v36, v98, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v50, v147, v38 :: v_dual_lshlrev_b32 v49, 16, v52 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v39 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v129, v30, v66 :: v_dual_lshlrev_b32 v30, 16, v35 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v49, v130 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v116, v117, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v117, 0x400000, v98 -; GFX12-FAKE16-NEXT: v_bfe_u32 v48, v100, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v36, v36, v98, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v118, v118, v119 :: v_dual_max_num_f32 v65, v65, v65 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v119, 0x400000, v100 -; GFX12-FAKE16-NEXT: v_add3_u32 v48, v48, v100, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_bfe_u32 v130, v65, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v131, 0x400000, v65 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v30 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v50 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v35, v36, s0 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v37, v34 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v51, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82 +; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v34, v39, v48, s0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v131 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v54, 16, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v132 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v133 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v128, v129, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_add3_u32 v130, v130, v65, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v81, v134 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v130, v131, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v85, v135 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v132, v133, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v85, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v81 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v97, v144 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v134, v144, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v81 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v101, v145 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v146, v147, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96 -; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v85 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v112, v146 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v115, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v118 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v114 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v86 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v117, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v100, v100 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v116 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v128 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v36 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v112, v113, v96 :: v_dual_lshlrev_b32 v49, 16, v117 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v114, v147 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v48, v119, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v114 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v36 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v116 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v116, 0xffff0000, v118 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v119 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v116, v49 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v48, v34, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v128 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v96 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v118, v130 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v37 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v100, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v128, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v115, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v50, v38, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v117, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v36, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v119, v49, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v34, v48, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v128, v52, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v130, v54 :: v_dual_and_b32 v65, 0xffff0000, v65 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v37, v52, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v131, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v147, v32, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v70 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v132, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v80 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v32, v133, v68 :: v_dual_and_b32 v81, 0xffff0000, v81 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v54, v147 :: v_dual_and_b32 v85, 0xffff0000, v85 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v70 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v54 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v144, v70, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v0 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v86 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v96 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v98 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v49, 16, v34 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v133, 16, v69 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v102 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v147 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v102, v102, v102 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v38, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v38, v128, v38 :: v_dual_lshlrev_b32 v135, 16, v85 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v102, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v102 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v34, v68 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v102, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v54, v147, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v48, v52, v51 :: v_dual_lshlrev_b32 v145, 16, v101 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v37, v37, v55 :: v_dual_lshlrev_b32 v34, 16, v34 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v64, v55 :: v_dual_lshlrev_b32 v147, 16, v114 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v34, v34, v34 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v39, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v55, v34, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v51, 16, v128 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83 -; GFX12-FAKE16-NEXT: v_add3_u32 v55, v55, v34, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v52, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v87 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v87, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v97 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v31, v97, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v99 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v32, v99, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v98 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v103 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v48, v33, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v71, v86, v103, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v113 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v30 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v100, v35, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v116 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v33, v115, v36 :: v_dual_and_b32 v86, 0xffff0000, v86 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v117 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v48, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v118 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v119 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v117, v37, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v96 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v119, v38, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v69 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v16 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v38, v50, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36 +; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v128, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v130, v49, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0x8000, v147 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v39, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v130 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v147, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v85 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v48, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v131, v51, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v48 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v86 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v132, v52, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v133, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v112 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v55, v39, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v67, v51, v51 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v135, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v53, v129 :: v_dual_lshlrev_b32 v55, 16, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v84 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v101 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v101, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v55 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v52 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v52 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v54, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v80 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v66, v80, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v67 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_lshlrev_b32 v80, 16, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v15, v31, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v144, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v67, 16, 1 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v103 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v67, 0x7fff +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v50 :: v_dual_lshlrev_b32 v64, 16, v53 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v103, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v16 -; GFX12-FAKE16-NEXT: v_bfe_u32 v68, v53, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v50, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v70, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v31, v53 :: v_dual_lshlrev_b32 v55, 16, v52 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v66, v55, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v64 -; GFX12-FAKE16-NEXT: v_add3_u32 v66, v68, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v69, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v67 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v55 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v65, v82 :: v_dual_lshlrev_b32 v70, 16, v55 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v52, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v65 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v70 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v54, v53 :: v_dual_lshlrev_b32 v65, 16, v55 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v55, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v15, v50 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v113 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v113 :: v_dual_lshlrev_b32 v80, 16, v68 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v64 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v68, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v70, v84, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v64, v53, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v65, v69, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v14 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v50 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v64, v54, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v80, v71 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v65, v50, v68 :: v_dual_lshlrev_b32 v80, 16, v30 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v65 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v69, v14, v30, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v65, v65, v65 :: v_dual_max_num_f32 v66, v66, v66 -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v66, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v66 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v66, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v64, v71 :: v_dual_lshlrev_b32 v71, 16, v13 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v65 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v64 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v70, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v69 -; GFX12-FAKE16-NEXT: v_bfe_u32 v54, v65, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v65 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v67, v53, v67 :: v_dual_lshlrev_b32 v66, 16, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_add3_u32 v54, v54, v65, 0x7fff -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v70, v66 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v55, v33, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v66 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v30, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v71, v13, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v29 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v64, v53, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v129 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v80, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v54, 16, v12 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v53 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v29, v71, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v129, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v67, v55, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v65 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v66 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v54 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v28 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v66, v13, v13 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v53, v29 :: v_dual_lshlrev_b32 v70, 16, v71 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v68, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v70, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v12 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v71, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v50 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v66, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v50, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v54 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v53, v66, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v50, v50, v53 :: v_dual_max_num_f32 v53, v55, v55 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v53 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v64, v29, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v64, v53, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v53, v66, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v69 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_add3_u32 v64, v64, v53, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v54, v69, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v27 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v12 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v64, v67 :: v_dual_lshlrev_b32 v68, 16, v28 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v68 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v28, v12 :: v_dual_lshlrev_b32 v67, 16, v11 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v66, v27, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 vcc_lo, 0x8000, v129 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v55, v30, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v68, v30, v71 :: v_dual_lshlrev_b32 v55, 16, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v66 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v67, v64 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v66, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v54, v27, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v68, v65 :: v_dual_max_num_f32 v55, v55, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v50, v55, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v55 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v50, v55, 0x7fff -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v55, v129, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v64 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v67, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v65, v26, v10 :: v_dual_lshlrev_b32 v64, 16, v64 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v64, v64, v64 :: v_dual_and_b32 v53, 0xffff0000, v53 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v30, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v65 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v66, v65 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v30, v12 :: v_dual_lshlrev_b32 v67, 16, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v9 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v67, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v65, v10 :: v_dual_lshlrev_b32 v55, 16, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v53 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v53 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v25 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26 +; GFX12-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v9 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_perm_b32 v12, v33, v12, 0x5040100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v54, v54, v54 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_bfe_u32 v30, v54, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54 -; GFX12-FAKE16-NEXT: v_add3_u32 v30, v30, v54, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v54, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v64, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v24 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v8 -; GFX12-FAKE16-NEXT: v_perm_b32 v11, v34, v11, 0x5040100 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v24, v8 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v50, 16, v50 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v50, v50, v50 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v50, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v50 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v50, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v53, v66, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v54 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v50 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v26, 16, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v53, v53, v53 :: v_dual_and_b32 v50, 0xffff0000, v50 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v65 :: v_dual_lshlrev_b32 v55, 16, v23 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v28, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v53, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v54, v9, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v23, v7 :: v_dual_lshlrev_b32 v55, 16, v6 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v8 :: v_dual_lshlrev_b32 v29, 16, v7 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX12-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX12-FAKE16-NEXT: v_add3_u32 v25, v28, v53, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v53 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v28, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v25 -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v26 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v54, v9 :: v_dual_lshlrev_b32 v64, 16, v6 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v5 -; GFX12-FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; GFX12-FAKE16-NEXT: v_perm_b32 v9, v36, v9, 0x5040100 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v23, v7 :: v_dual_lshlrev_b32 v28, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v50, v8 :: v_dual_lshlrev_b32 v55, 16, v22 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v55 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v22, v6 :: v_dual_lshlrev_b32 v54, 16, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v53 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v26, v8 :: v_dual_lshlrev_b32 v25, 16, v22 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24 -; GFX12-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v24 :: v_dual_lshlrev_b32 v53, 16, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v28 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v24, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v50, v8, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v25, v7 :: v_dual_lshlrev_b32 v50, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v53 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v30, v21, v5 :: v_dual_lshlrev_b32 v53, 16, v20 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v30, 16, v30 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX12-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v30, v30, v30 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 -; GFX12-FAKE16-NEXT: v_add3_u32 v23, v23, v24, 0x7fff -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v50 :: v_dual_lshlrev_b32 v50, 16, v20 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v50 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX12-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v20, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v19 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v28, 16, v50 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v22 :: v_dual_lshlrev_b32 v53, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v22, v28, v28 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v3 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v30, v22, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v22 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v28, v5 :: v_dual_lshlrev_b32 v50, 16, v19 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3 +; GFX12-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21 -; GFX12-FAKE16-NEXT: v_add3_u32 v30, v30, v22, 0x7fff -; GFX12-FAKE16-NEXT: v_perm_b32 v8, v37, v8, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v50 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v17 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v19, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 +; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v30, v54 :: v_dual_lshlrev_b32 v21, 16, v21 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v21, v21, v21 :: v_dual_lshlrev_b32 v30, 16, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v25, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v28, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_bfe_u32 v24, v21, 16, 1 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v24, v3 :: v_dual_lshlrev_b32 v20, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v22 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v24, v21, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v21 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v28, 16, v18 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_lshlrev_b32 v20, 16, v16 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v28 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v18, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v24, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v30, v25 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v17, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v22 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v24, v28, v28 :: v_dual_lshlrev_b32 v25, 16, v25 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v16, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX12-FAKE16-NEXT: v_bfe_u32 v28, v24, 16, 1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v25, v25, v25 :: v_dual_lshlrev_b32 v22, 16, v22 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v20 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19 -; GFX12-FAKE16-NEXT: v_bfe_u32 v50, v25, 16, 1 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v17, v1 :: v_dual_lshlrev_b32 v25, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v19, v22, v22 -; GFX12-FAKE16-NEXT: v_add3_u32 v22, v28, v24, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v24 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX12-FAKE16-NEXT: v_add3_u32 v24, v50, v25, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v53, v19, 16, 1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX12-FAKE16-NEXT: v_add3_u32 v50, v53, v19, 0x7fff -; GFX12-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v19 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v22 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v50, v53, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v24 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v30, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100 -; GFX12-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v21, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v19 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v21, v1 :: v_dual_and_b32 v16, 0xffff0000, v22 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18 -; GFX12-FAKE16-NEXT: v_perm_b32 v1, v14, v1, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v25, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16 -; GFX12-FAKE16-NEXT: v_perm_b32 v14, v31, v27, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_perm_b32 v0, v13, v0, 0x5040100 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v54, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20 -; GFX12-FAKE16-NEXT: v_perm_b32 v13, v32, v26, 0x5040100 -; GFX12-FAKE16-NEXT: v_perm_b32 v2, v15, v2, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21 +; GFX12-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v23, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_perm_b32 v15, v39, v29, 0x5040100 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100 +; GFX12-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <32 x bfloat> @llvm.minimumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) ret <32 x bfloat> %result @@ -19090,25 +14587,15 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v3, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; GFX8-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3 -; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc ; GFX8-NEXT: s_movk_i32 s4, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_minimumnum_bf16_no_ieee: @@ -19123,24 +14610,15 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX900-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX900-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v3, v3, v2, s4 -; GFX900-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc ; GFX900-NEXT: s_movk_i32 s4, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX900-NEXT: s_setpc_b64 s[30:31] ; ; GFX950-LABEL: v_minimumnum_bf16_no_ieee: @@ -19149,7 +14627,7 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 ; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v1 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v0 @@ -19159,10 +14637,6 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX950-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc @@ -19188,21 +14662,13 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX10-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX10-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_bf16_no_ieee: @@ -19211,39 +14677,31 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_bf16_no_ieee: @@ -19262,26 +14720,14 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v2, v2, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_minimumnum_bf16_no_ieee: @@ -19294,45 +14740,37 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, v4, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_bf16_no_ieee: @@ -19358,29 +14796,17 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 { ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v2 -; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y) ret bfloat %result @@ -19417,26 +14843,16 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, 1.0, v4 -; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -19446,23 +14862,14 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4 -; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -19479,25 +14886,16 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX900-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX900-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v5, v5, v4, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 +; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc @@ -19507,21 +14905,13 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v4, v4, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX900-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v2, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -19536,16 +14926,12 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v2 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX950-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc @@ -19569,9 +14955,6 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v4, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -19609,37 +14992,21 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo -; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v4, v4, v4 -; GFX10-NEXT: v_or_b32_e32 v8, 0x400000, v3 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX10-NEXT: v_add3_u32 v5, v5, v3, 0x7fff -; GFX10-NEXT: v_bfe_u32 v7, v4, 16, 1 -; GFX10-NEXT: v_or_b32_e32 v9, 0x400000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo -; GFX10-NEXT: v_add3_u32 v7, v7, v4, 0x7fff -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -19653,66 +15020,52 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v7 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-TRUE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16_no_ieee: @@ -19725,60 +15078,39 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; @@ -19796,71 +15128,56 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l ; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v7 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v1.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v7, v9, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v0.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16_no_ieee: @@ -19878,69 +15195,48 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> % ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v8 :: v_dual_lshlrev_b32 v5, 16, v5 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v5, v5, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v7, v0 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] @@ -19985,26 +15281,16 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20014,23 +15300,14 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v5 -; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20040,22 +15317,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5 -; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -20073,25 +15341,16 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20101,22 +15360,14 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX900-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX900-NEXT: v_bfe_u32 v6, v5, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v5, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20126,21 +15377,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v5, v5, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v4, v0, s4 ; GFX900-NEXT: s_setpc_b64 s[30:31] @@ -20155,16 +15398,12 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -20188,9 +15427,6 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX950-NEXT: v_max_f32_e32 v5, v5, v5 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc @@ -20214,9 +15450,6 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v5, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -20234,180 +15467,125 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX10-LABEL: v_minimumnum_v3bf16_no_ieee: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v5, v5 -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cmp_u_f32_e64 s4, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v5, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v0, vcc_lo -; GFX10-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_or_b32_e32 v11, 0x400000, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX10-NEXT: v_bfe_u32 v10, v7, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo -; GFX10-NEXT: v_add3_u32 v10, v10, v7, 0x7fff -; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo +; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v13, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 -; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 +; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16_no_ieee: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v9, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v10 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16_no_ieee: @@ -20416,88 +15594,59 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v9 -; GFX11-FAKE16-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-TRUE16-LABEL: v_minimumnum_v3bf16_no_ieee: @@ -20508,104 +15657,77 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v9, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v10 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v6, v6 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v2.l, v0.l, s3 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s2 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v7, v7, v7 :: v_dual_and_b32 v4, 0xffff0000, v6 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s2 -; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s1 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v8, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v12, v14, s5 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s3 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s1 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v0.h, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v1.l, s0 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16_no_ieee: @@ -20618,98 +15740,67 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v7, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v5 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v8, 16, v0 -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v7 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3 ; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v5, v4 :: v_dual_lshlrev_b32 v9, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v6 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v9 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_lshlrev_b32 v7, 16, v7 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v7, v7, v7 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc_lo -; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX12-FAKE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v6 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v9 :: v_dual_and_b32 v6, 0xffff0000, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX12-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v12, v12, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v5, 0xffff0000, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v10, v1 :: v_dual_and_b32 v2, 0xffff0000, v8 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 @@ -20717,7 +15808,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> % ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) ret <3 x bfloat> %result @@ -20766,26 +15857,16 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: s_movk_i32 s4, 0x7fff -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: s_movk_i32 s5, 0x8000 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -20797,23 +15878,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, 1.0, v7 -; GFX8-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, s4, v8 -; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20823,23 +15895,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, 1.0, v6 -; GFX8-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7 -; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20849,22 +15912,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v3 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6 -; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -20884,25 +15938,16 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v5 ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 +; GFX900-NEXT: s_movk_i32 s4, 0x8000 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: s_movk_i32 s4, 0x7fff -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: s_movk_i32 s5, 0x8000 -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v4 ; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5 ; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 @@ -20914,22 +15959,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v6 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX900-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX900-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX900-NEXT: v_add3_u32 v8, v8, v7, s4 -; GFX900-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; GFX900-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v5 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v6 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v5 +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v7 +; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc @@ -20939,22 +15976,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v1 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX900-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX900-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX900-NEXT: v_add3_u32 v7, v7, v6, s4 -; GFX900-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; GFX900-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v1 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v3 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v1 +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc @@ -20964,21 +15993,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX900-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX900-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX900-NEXT: v_add3_u32 v6, v6, v3, s4 -; GFX900-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc -; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v0 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s5, v2 +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0 +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v2 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 +; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 ; GFX900-NEXT: v_perm_b32 v0, v5, v0, s4 ; GFX900-NEXT: v_perm_b32 v1, v4, v1, s4 @@ -20994,17 +16015,13 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 ; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v5 -; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v2 +; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v4 ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v7 ; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v0 -; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v2 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 -; GFX950-NEXT: s_movk_i32 s0, 0x8000 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc @@ -21028,9 +16045,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v7, v8 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX950-NEXT: v_max_f32_e32 v7, v7, v7 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v7, v7, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v5 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc @@ -21054,9 +16068,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX950-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v6, v6, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v1 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc @@ -21080,9 +16091,6 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX950-NEXT: v_cmp_lt_f32_e32 vcc, v6, v3 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc -; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX950-NEXT: v_max_f32_e32 v3, v3, v3 -; GFX950-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v0 ; GFX950-NEXT: s_nop 1 ; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc @@ -21127,78 +16135,46 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v14 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0 -; GFX10-NEXT: v_bfe_u32 v14, v8, 16, 1 -; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v7, v4, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 -; GFX10-NEXT: v_or_b32_e32 v13, 0x400000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v12 -; GFX10-NEXT: v_add3_u32 v12, v14, v8, 0x7fff -; GFX10-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v13, vcc_lo -; GFX10-NEXT: v_bfe_u32 v12, v11, 16, 1 -; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10 -; GFX10-NEXT: v_bfe_u32 v15, v9, 16, 1 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX10-NEXT: v_add3_u32 v12, v12, v11, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_or_b32_e32 v16, 0x400000, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX10-NEXT: v_bfe_u32 v12, v6, 16, 1 -; GFX10-NEXT: v_add3_u32 v14, v15, v9, 0x7fff -; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX10-NEXT: v_add3_u32 v12, v12, v6, 0x7fff -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v15, vcc_lo -; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 @@ -21217,225 +16193,155 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v10, v8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v13 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_max_f32_e32 v11, v11, v11 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v9, v10 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX11-TRUE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX11-TRUE16-NEXT: v_max_f32_e32 v9, v9, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v12 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 ; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX11-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 -; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v8, v8, v8 -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v12, v12, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_max_f32_e32 v10, v10, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo @@ -21460,123 +16366,94 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo ; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s1 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9 +; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd ; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s2 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l ; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v10, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff +; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v5.l, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v2.l -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v9, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, s1 ; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v7.l, v6.l, vcc_lo -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12 -; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l -; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v13 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v10, v10, v10 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.l, v1.l, s0 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l -; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v0.l, s1 -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10 -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v11, v11, v11 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10 -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff -; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, s2 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.l -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v12, v13, s1 -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11 -; GFX12-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff -; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v9, v9, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8 +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v12 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v4.l, vcc_lo -; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v10 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v13 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14 +; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff ; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo -; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4 -; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v11.h, v6.l, s2 -; GFX12-TRUE16-NEXT: v_add3_u32 v5, v12, v8, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v9, 0x7fff -; GFX12-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9 -; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s0 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, v6, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10 ; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v11 -; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.l -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l +; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v7.l, s2 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l +; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.l -; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s2 -; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v5 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v7 ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1 +; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 +; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.l, v0.h, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v2.h, s2 ; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.h, v0.h, vcc_lo -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.h, v2.h, s2 -; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v0.l, vcc_lo ; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff -; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s1 +; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1 ; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee: @@ -21586,126 +16463,80 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v10 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v6 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v8, v8, v8 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v13 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0 +; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v14, 16, v2 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0 ; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v8 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v14 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v9 -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4 -; GFX12-FAKE16-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_lshlrev_b32 v12, 16, v12 +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6 +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v12, v12, v12 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX12-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v10, v10, v10 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v10, 16, 1 -; GFX12-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10 -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5 -; GFX12-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6 -; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1 -; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff -; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v12, 0x7fff ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8 +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10 +; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1 -; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0 @@ -21714,21 +16545,22 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7 ; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v5 -; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10 +; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo +; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd -; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v6 :: v_dual_and_b32 v2, 0xffff0000, v9 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8 ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd ; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) diff --git a/llvm/test/CodeGen/Mips/fp-maximumnum-minimumnum.ll b/llvm/test/CodeGen/Mips/fp-maximumnum-minimumnum.ll index bc81966ca0f5c..7aaf00f871136 100644 --- a/llvm/test/CodeGen/Mips/fp-maximumnum-minimumnum.ll +++ b/llvm/test/CodeGen/Mips/fp-maximumnum-minimumnum.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc --mtriple=mipsisa32r6 < %s | FileCheck %s --check-prefix=MIPS32R6 +; RUN: llc --mtriple=mips64 < %s | FileCheck %s --check-prefix=MIPS64R2 declare float @llvm.maximumnum.f32(float, float) declare double @llvm.maximumnum.f64(double, double) @@ -13,6 +14,25 @@ define float @maximumnum_float(float %x, float %y) { ; MIPS32R6-NEXT: min.s $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.s $f0, $f1, $f0 +; +; MIPS64R2-LABEL: maximumnum_float: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.un.s $f12, $f12 +; MIPS64R2-NEXT: movt.s $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.s $f13, $f13 +; MIPS64R2-NEXT: movt.s $f13, $f12, $fcc0 +; MIPS64R2-NEXT: c.ule.s $f12, $f13 +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: movf.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: mfc1 $1, $f12 +; MIPS64R2-NEXT: mov.s $f1, $f0 +; MIPS64R2-NEXT: movz.s $f1, $f12, $1 +; MIPS64R2-NEXT: mfc1 $1, $f13 +; MIPS64R2-NEXT: movz.s $f1, $f13, $1 +; MIPS64R2-NEXT: mtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.s $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.s $f0, $f1, $fcc0 %z = call float @llvm.maximumnum.f32(float %x, float %y) ret float %z } @@ -24,6 +44,17 @@ define float @maximumnum_float_nsz(float %x, float %y) { ; MIPS32R6-NEXT: min.s $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.s $f0, $f1, $f0 +; +; MIPS64R2-LABEL: maximumnum_float_nsz: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: c.un.s $f12, $f12 +; MIPS64R2-NEXT: movt.s $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.s $f13, $f13 +; MIPS64R2-NEXT: movt.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: c.ule.s $f12, $f0 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movf.s $f0, $f12, $fcc0 %z = call nsz float @llvm.maximumnum.f32(float %x, float %y) ret float %z } @@ -33,6 +64,21 @@ define float @maximumnum_float_nnan(float %x, float %y) { ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.s $f0, $f12, $f14 +; +; MIPS64R2-LABEL: maximumnum_float_nnan: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.ule.s $f12, $f13 +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: movf.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: mfc1 $1, $f12 +; MIPS64R2-NEXT: mov.s $f1, $f0 +; MIPS64R2-NEXT: movz.s $f1, $f12, $1 +; MIPS64R2-NEXT: mfc1 $1, $f13 +; MIPS64R2-NEXT: movz.s $f1, $f13, $1 +; MIPS64R2-NEXT: mtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.s $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.s $f0, $f1, $fcc0 %z = call nnan float @llvm.maximumnum.f32(float %x, float %y) ret float %z } @@ -45,6 +91,25 @@ define double @maximumnum_double(double %x, double %y) { ; MIPS32R6-NEXT: min.d $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.d $f0, $f1, $f0 +; +; MIPS64R2-LABEL: maximumnum_double: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.un.d $f12, $f12 +; MIPS64R2-NEXT: movt.d $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.d $f13, $f13 +; MIPS64R2-NEXT: movt.d $f13, $f12, $fcc0 +; MIPS64R2-NEXT: c.ule.d $f12, $f13 +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: movf.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: dmfc1 $1, $f12 +; MIPS64R2-NEXT: mov.d $f1, $f0 +; MIPS64R2-NEXT: movz.d $f1, $f12, $1 +; MIPS64R2-NEXT: dmfc1 $1, $f13 +; MIPS64R2-NEXT: movz.d $f1, $f13, $1 +; MIPS64R2-NEXT: dmtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.d $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.d $f0, $f1, $fcc0 %z = call double @llvm.maximumnum.f64(double %x, double %y) ret double %z } @@ -56,6 +121,17 @@ define double @maximumnum_double_nsz(double %x, double %y) { ; MIPS32R6-NEXT: min.d $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.d $f0, $f1, $f0 +; +; MIPS64R2-LABEL: maximumnum_double_nsz: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: c.un.d $f12, $f12 +; MIPS64R2-NEXT: movt.d $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.d $f13, $f13 +; MIPS64R2-NEXT: movt.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: c.ule.d $f12, $f0 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movf.d $f0, $f12, $fcc0 %z = call nsz double @llvm.maximumnum.f64(double %x, double %y) ret double %z } @@ -65,6 +141,21 @@ define double @maximumnum_double_nnan(double %x, double %y) { ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: max.d $f0, $f12, $f14 +; +; MIPS64R2-LABEL: maximumnum_double_nnan: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.ule.d $f12, $f13 +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: movf.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: dmfc1 $1, $f12 +; MIPS64R2-NEXT: mov.d $f1, $f0 +; MIPS64R2-NEXT: movz.d $f1, $f12, $1 +; MIPS64R2-NEXT: dmfc1 $1, $f13 +; MIPS64R2-NEXT: movz.d $f1, $f13, $1 +; MIPS64R2-NEXT: dmtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.d $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.d $f0, $f1, $fcc0 %z = call nnan double @llvm.maximumnum.f64(double %x, double %y) ret double %z } @@ -76,6 +167,28 @@ define float @minimumnum_float(float %x, float %y) { ; MIPS32R6-NEXT: min.s $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.s $f0, $f1, $f0 +; +; MIPS64R2-LABEL: minimumnum_float: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.un.s $f12, $f12 +; MIPS64R2-NEXT: movt.s $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.s $f13, $f13 +; MIPS64R2-NEXT: movt.s $f13, $f12, $fcc0 +; MIPS64R2-NEXT: c.olt.s $f12, $f13 +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: movt.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: mfc1 $1, $f12 +; MIPS64R2-NEXT: lui $2, 32768 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: mov.s $f1, $f0 +; MIPS64R2-NEXT: movz.s $f1, $f12, $1 +; MIPS64R2-NEXT: mfc1 $1, $f13 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: movz.s $f1, $f13, $1 +; MIPS64R2-NEXT: mtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.s $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.s $f0, $f1, $fcc0 %z = call float @llvm.minimumnum.f32(float %x, float %y) ret float %z } @@ -87,6 +200,17 @@ define float @minimumnum_float_nsz(float %x, float %y) { ; MIPS32R6-NEXT: min.s $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.s $f0, $f1, $f0 +; +; MIPS64R2-LABEL: minimumnum_float_nsz: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: c.un.s $f12, $f12 +; MIPS64R2-NEXT: movt.s $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.s $f13, $f13 +; MIPS64R2-NEXT: movt.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: c.olt.s $f12, $f0 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.s $f0, $f12, $fcc0 %z = call nsz float @llvm.minimumnum.f32(float %x, float %y) ret float %z } @@ -96,6 +220,24 @@ define float @minimumnum_float_nnan(float %x, float %y) { ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.s $f0, $f12, $f14 +; +; MIPS64R2-LABEL: minimumnum_float_nnan: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.olt.s $f12, $f13 +; MIPS64R2-NEXT: mov.s $f0, $f13 +; MIPS64R2-NEXT: movt.s $f0, $f12, $fcc0 +; MIPS64R2-NEXT: mfc1 $1, $f12 +; MIPS64R2-NEXT: lui $2, 32768 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: mov.s $f1, $f0 +; MIPS64R2-NEXT: movz.s $f1, $f12, $1 +; MIPS64R2-NEXT: mfc1 $1, $f13 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: movz.s $f1, $f13, $1 +; MIPS64R2-NEXT: mtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.s $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.s $f0, $f1, $fcc0 %z = call nnan float @llvm.minimumnum.f32(float %x, float %y) ret float %z } @@ -107,6 +249,29 @@ define double @minimumnum_double(double %x, double %y) { ; MIPS32R6-NEXT: min.d $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.d $f0, $f1, $f0 +; +; MIPS64R2-LABEL: minimumnum_double: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.un.d $f12, $f12 +; MIPS64R2-NEXT: movt.d $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.d $f13, $f13 +; MIPS64R2-NEXT: movt.d $f13, $f12, $fcc0 +; MIPS64R2-NEXT: c.olt.d $f12, $f13 +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: movt.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: dmfc1 $1, $f12 +; MIPS64R2-NEXT: daddiu $2, $zero, 1 +; MIPS64R2-NEXT: dsll $2, $2, 63 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: mov.d $f1, $f0 +; MIPS64R2-NEXT: movz.d $f1, $f12, $1 +; MIPS64R2-NEXT: dmfc1 $1, $f13 +; MIPS64R2-NEXT: xor $1, $1, $2 +; MIPS64R2-NEXT: movz.d $f1, $f13, $1 +; MIPS64R2-NEXT: dmtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.d $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.d $f0, $f1, $fcc0 %z = call double @llvm.minimumnum.f64(double %x, double %y) ret double %z } @@ -118,6 +283,17 @@ define double @minimumnum_double_nsz(double %x, double %y) { ; MIPS32R6-NEXT: min.d $f1, $f12, $f12 ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.d $f0, $f1, $f0 +; +; MIPS64R2-LABEL: minimumnum_double_nsz: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: c.un.d $f12, $f12 +; MIPS64R2-NEXT: movt.d $f12, $f13, $fcc0 +; MIPS64R2-NEXT: c.un.d $f13, $f13 +; MIPS64R2-NEXT: movt.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: c.olt.d $f12, $f0 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.d $f0, $f12, $fcc0 %z = call nsz double @llvm.minimumnum.f64(double %x, double %y) ret double %z } @@ -127,6 +303,25 @@ define double @minimumnum_double_nnan(double %x, double %y) { ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: min.d $f0, $f12, $f14 +; +; MIPS64R2-LABEL: minimumnum_double_nnan: +; MIPS64R2: # %bb.0: +; MIPS64R2-NEXT: c.olt.d $f12, $f13 +; MIPS64R2-NEXT: mov.d $f0, $f13 +; MIPS64R2-NEXT: movt.d $f0, $f12, $fcc0 +; MIPS64R2-NEXT: daddiu $1, $zero, 1 +; MIPS64R2-NEXT: dsll $1, $1, 63 +; MIPS64R2-NEXT: dmfc1 $2, $f12 +; MIPS64R2-NEXT: xor $2, $2, $1 +; MIPS64R2-NEXT: mov.d $f1, $f0 +; MIPS64R2-NEXT: movz.d $f1, $f12, $2 +; MIPS64R2-NEXT: dmfc1 $2, $f13 +; MIPS64R2-NEXT: xor $1, $2, $1 +; MIPS64R2-NEXT: movz.d $f1, $f13, $1 +; MIPS64R2-NEXT: dmtc1 $zero, $f2 +; MIPS64R2-NEXT: c.eq.d $f0, $f2 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movt.d $f0, $f1, $fcc0 %z = call nnan double @llvm.minimumnum.f64(double %x, double %y) ret double %z } diff --git a/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll index 5945bae94f452..33bc93d0fe4db 100644 --- a/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll +++ b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll @@ -1812,15 +1812,15 @@ define <4 x half> @test_fmaximumnum_v4f16(<4 x half> %x, <4 x half> %y) nounwind ; ; AVX512-LABEL: test_fmaximumnum_v4f16: ; AVX512: # %bb.0: -; AVX512-NEXT: subq $72, %rsp -; AVX512-NEXT: vmovdqa %xmm1, %xmm4 -; AVX512-NEXT: vmovdqa %xmm0, %xmm8 +; AVX512-NEXT: subq $56, %rsp +; AVX512-NEXT: vmovdqa %xmm1, %xmm5 +; AVX512-NEXT: vmovdqa %xmm0, %xmm6 ; AVX512-NEXT: vpsrldq {{.*#+}} xmm0 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX512-NEXT: vucomiss %xmm0, %xmm0 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vpsrldq {{.*#+}} xmm1 = xmm8[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vpsrldq {{.*#+}} xmm1 = xmm6[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al @@ -1837,41 +1837,39 @@ define <4 x half> @test_fmaximumnum_v4f16(<4 x half> %x, <4 x half> %y) nounwind ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 ; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm2 +; AVX512-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm5[3,3,3,3] ; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 -; AVX512-NEXT: movzwl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax -; AVX512-NEXT: vmovd %eax, %xmm1 -; AVX512-NEXT: vcvtph2ps %xmm1, %xmm9 -; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm4[3,3,3,3] -; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 -; AVX512-NEXT: vucomiss %xmm1, %xmm1 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm8[3,3,3,3] -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm6[3,3,3,3] +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 +; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 -; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 -; AVX512-NEXT: vmovaps %xmm2, (%rsp) # 16-byte Spill -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k2} ; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; AVX512-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vcvtph2ps %xmm1, %xmm3 -; AVX512-NEXT: vucomiss %xmm3, %xmm2 +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm1 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} -; AVX512-NEXT: vpsrldq {{.*#+}} xmm1 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; AVX512-NEXT: vpsrldq {{.*#+}} xmm1 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vpsrldq {{.*#+}} xmm2 = xmm8[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vpsrldq {{.*#+}} xmm2 = xmm6[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX512-NEXT: vucomiss %xmm2, %xmm2 ; AVX512-NEXT: setp %al @@ -1888,222 +1886,178 @@ define <4 x half> @test_fmaximumnum_v4f16(<4 x half> %x, <4 x half> %y) nounwind ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 ; AVX512-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1} -; AVX512-NEXT: vshufpd {{.*#+}} xmm2 = xmm4[1,0] -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm3 +; AVX512-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm5[1,0] +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 +; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vshufpd {{.*#+}} xmm7 = xmm8[1,0] -; AVX512-NEXT: vcvtph2ps %xmm7, %xmm7 -; AVX512-NEXT: vucomiss %xmm7, %xmm7 +; AVX512-NEXT: vshufpd {{.*#+}} xmm2 = xmm6[1,0] +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm2 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 -; AVX512-NEXT: vmovss %xmm2, %xmm7, %xmm7 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm7, %xmm14 -; AVX512-NEXT: vcvtph2ps %xmm14, %xmm7 -; AVX512-NEXT: vmovss %xmm7, %xmm2, %xmm2 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 -; AVX512-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vucomiss %xmm2, %xmm7 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm13 +; AVX512-NEXT: vcvtph2ps %xmm13, %xmm2 +; AVX512-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm12 +; AVX512-NEXT: vcvtph2ps %xmm12, %xmm1 +; AVX512-NEXT: vucomiss %xmm1, %xmm2 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovss %xmm7, %xmm2, %xmm2 {%k1} -; AVX512-NEXT: vxorps %xmm15, %xmm15, %xmm15 -; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm15[1,2,3] -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm5 -; AVX512-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm0 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 -; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 -; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm15[1,2,3] -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm3 -; AVX512-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm0 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 -; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 -; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm15[1,2,3] -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm1 +; AVX512-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; AVX512-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm0 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 -; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 -; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm15[1,2,3] -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm2 -; AVX512-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; AVX512-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512-NEXT: vpsrlq $48, %xmm4, %xmm0 +; AVX512-NEXT: vpsrlq $48, %xmm5, %xmm0 ; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX512-NEXT: vucomiss %xmm0, %xmm0 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vpsrlq $48, %xmm8, %xmm1 +; AVX512-NEXT: vpsrlq $48, %xmm6, %xmm1 ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 ; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm12 -; AVX512-NEXT: vcvtph2ps %xmm12, %xmm1 +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm11 +; AVX512-NEXT: vcvtph2ps %xmm11, %xmm1 ; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm13 -; AVX512-NEXT: vcvtph2ps %xmm13, %xmm6 -; AVX512-NEXT: vucomiss %xmm6, %xmm1 +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm15 +; AVX512-NEXT: vcvtph2ps %xmm15, %xmm7 +; AVX512-NEXT: vucomiss %xmm7, %xmm1 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovss %xmm1, %xmm6, %xmm6 {%k1} -; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm4[1,1,3,3] +; AVX512-NEXT: vmovss %xmm1, %xmm7, %xmm7 {%k1} +; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm5[1,1,3,3] ; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX512-NEXT: vucomiss %xmm0, %xmm0 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm8[1,1,3,3] +; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm6[1,1,3,3] ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 ; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm10 +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm9 +; AVX512-NEXT: vcvtph2ps %xmm9, %xmm4 +; AVX512-NEXT: vmovss %xmm4, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm10 ; AVX512-NEXT: vcvtph2ps %xmm10, %xmm3 -; AVX512-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm11 -; AVX512-NEXT: vcvtph2ps %xmm11, %xmm5 -; AVX512-NEXT: vucomiss %xmm5, %xmm3 +; AVX512-NEXT: vucomiss %xmm3, %xmm4 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovss %xmm3, %xmm5, %xmm5 {%k1} -; AVX512-NEXT: vcvtph2ps %xmm4, %xmm0 +; AVX512-NEXT: vmovss %xmm4, %xmm3, %xmm3 {%k1} +; AVX512-NEXT: vcvtph2ps %xmm5, %xmm0 ; AVX512-NEXT: vucomiss %xmm0, %xmm0 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vcvtph2ps %xmm8, %xmm3 -; AVX512-NEXT: vucomiss %xmm3, %xmm3 +; AVX512-NEXT: vcvtph2ps %xmm6, %xmm4 +; AVX512-NEXT: vucomiss %xmm4, %xmm4 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 -; AVX512-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm3 -; AVX512-NEXT: vcvtph2ps %xmm3, %xmm1 +; AVX512-NEXT: vmovss %xmm0, %xmm4, %xmm4 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm4, %xmm4 +; AVX512-NEXT: vcvtph2ps %xmm4, %xmm1 ; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm7 -; AVX512-NEXT: vcvtph2ps %xmm7, %xmm2 +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm8 +; AVX512-NEXT: vcvtph2ps %xmm8, %xmm2 ; AVX512-NEXT: vucomiss %xmm2, %xmm1 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 ; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} -; AVX512-NEXT: vpsrld $16, %xmm4, %xmm1 +; AVX512-NEXT: vpsrld $16, %xmm5, %xmm1 ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512-NEXT: vucomiss %xmm1, %xmm1 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vpsrld $16, %xmm8, %xmm4 -; AVX512-NEXT: vcvtph2ps %xmm4, %xmm4 -; AVX512-NEXT: vucomiss %xmm4, %xmm4 +; AVX512-NEXT: vpsrld $16, %xmm6, %xmm5 +; AVX512-NEXT: vcvtph2ps %xmm5, %xmm5 +; AVX512-NEXT: vucomiss %xmm5, %xmm5 ; AVX512-NEXT: setp %al ; AVX512-NEXT: kmovw %eax, %k2 -; AVX512-NEXT: vmovss %xmm1, %xmm4, %xmm4 {%k2} -; AVX512-NEXT: vcvtps2ph $4, %xmm4, %xmm8 -; AVX512-NEXT: vcvtph2ps %xmm8, %xmm4 -; AVX512-NEXT: vmovss %xmm4, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovss %xmm1, %xmm5, %xmm5 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm5, %xmm6 +; AVX512-NEXT: vcvtph2ps %xmm6, %xmm5 +; AVX512-NEXT: vmovss %xmm5, %xmm1, %xmm1 {%k1} ; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; AVX512-NEXT: vcvtph2ps %xmm1, %xmm0 -; AVX512-NEXT: vucomiss %xmm0, %xmm4 +; AVX512-NEXT: vucomiss %xmm0, %xmm5 ; AVX512-NEXT: seta %al ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovss %xmm4, %xmm0, %xmm0 {%k1} -; AVX512-NEXT: vcvtps2ph $4, %xmm6, %xmm4 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm4, %xmm4 -; AVX512-NEXT: vmulss %xmm4, %xmm9, %xmm4 -; AVX512-NEXT: vcvtps2ph $4, %xmm5, %xmm5 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm5, %xmm5 -; AVX512-NEXT: vmulss %xmm5, %xmm9, %xmm5 -; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vmulss %xmm2, %xmm9, %xmm2 -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 -; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 -; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 -; AVX512-NEXT: vblendps {{.*#+}} xmm4 = xmm4[0],xmm15[1,2,3] -; AVX512-NEXT: vblendps {{.*#+}} xmm5 = xmm5[0],xmm15[1,2,3] -; AVX512-NEXT: vblendps {{.*#+}} xmm9 = xmm2[0],xmm15[1,2,3] -; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm15[1,2,3] -; AVX512-NEXT: vcvtps2ph $4, %xmm4, %xmm2 -; AVX512-NEXT: vcvtps2ph $4, %xmm5, %xmm6 -; AVX512-NEXT: vcvtps2ph $4, %xmm9, %xmm4 -; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm5 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3] -; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm9[0],xmm0[0],xmm9[1],xmm0[1] +; AVX512-NEXT: vmovss %xmm5, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm7, %xmm7 +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm3 +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm5 +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm7[0],xmm3[1],xmm7[1],xmm3[2],xmm7[2],xmm3[3],xmm7[3] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm14 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm14[0],xmm0[0],xmm14[1],xmm0[1] ; AVX512-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload ; AVX512-NEXT: # xmm0 = xmm0[0],mem[0] -; AVX512-NEXT: vmovdqa (%rsp), %xmm9 # 16-byte Reload -; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm9, %xmm9 # 16-byte Folded Reload -; AVX512-NEXT: # xmm9 = xmm9[0],mem[0],xmm9[1],mem[1],xmm9[2],mem[2],xmm9[3],mem[3] +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm14 # 16-byte Reload ; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm14, %xmm14 # 16-byte Folded Reload ; AVX512-NEXT: # xmm14 = xmm14[0],mem[0],xmm14[1],mem[1],xmm14[2],mem[2],xmm14[3],mem[3] -; AVX512-NEXT: vpunpckldq {{.*#+}} xmm9 = xmm14[0],xmm9[0],xmm14[1],xmm9[1] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm10[0],xmm12[0],xmm10[1],xmm12[1],xmm10[2],xmm12[2],xmm10[3],xmm12[3] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm8[0],xmm3[1],xmm8[1],xmm3[2],xmm8[2],xmm3[3],xmm8[3] -; AVX512-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm10[0],xmm3[1],xmm10[1] -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm9[0] -; AVX512-NEXT: vpxor %xmm8, %xmm8, %xmm8 -; AVX512-NEXT: vpcmpeqw %xmm3, %xmm8, %xmm9 -; AVX512-NEXT: vpblendvb %xmm9, %xmm3, %xmm0, %xmm3 +; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm13, %xmm13 # 16-byte Folded Reload +; AVX512-NEXT: # xmm13 = xmm13[0],mem[0],xmm13[1],mem[1],xmm13[2],mem[2],xmm13[3],mem[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm13 = xmm13[0],xmm14[0],xmm13[1],xmm14[1] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm9[0],xmm11[0],xmm9[1],xmm11[1],xmm9[2],xmm11[2],xmm9[3],xmm11[3] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1],xmm4[2],xmm6[2],xmm4[3],xmm6[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm9[0],xmm4[1],xmm9[1] +; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm13[0] +; AVX512-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512-NEXT: vpcmpeqw %xmm6, %xmm4, %xmm9 +; AVX512-NEXT: vpblendvb %xmm9, %xmm4, %xmm0, %xmm4 ; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload ; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm9, %xmm9 # 16-byte Folded Reload ; AVX512-NEXT: # xmm9 = xmm9[0],mem[0],xmm9[1],mem[1],xmm9[2],mem[2],xmm9[3],mem[3] -; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload -; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm10, %xmm10 # 16-byte Folded Reload -; AVX512-NEXT: # xmm10 = xmm10[0],mem[0],xmm10[1],mem[1],xmm10[2],mem[2],xmm10[3],mem[3] -; AVX512-NEXT: vpunpckldq {{.*#+}} xmm9 = xmm10[0],xmm9[0],xmm10[1],xmm9[1] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm11[0],xmm13[0],xmm11[1],xmm13[1],xmm11[2],xmm13[2],xmm11[3],xmm13[3] -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[1],xmm1[1],xmm7[2],xmm1[2],xmm7[3],xmm1[3] +; AVX512-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm12, %xmm11 # 16-byte Folded Reload +; AVX512-NEXT: # xmm11 = xmm12[0],mem[0],xmm12[1],mem[1],xmm12[2],mem[2],xmm12[3],mem[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm9 = xmm11[0],xmm9[0],xmm11[1],xmm9[1] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm10[0],xmm15[0],xmm10[1],xmm15[1],xmm10[2],xmm15[2],xmm10[3],xmm15[3] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm8[0],xmm1[0],xmm8[1],xmm1[1],xmm8[2],xmm1[2],xmm8[3],xmm1[3] ; AVX512-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm10[0],xmm1[1],xmm10[1] ; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm9[0] -; AVX512-NEXT: vpcmpeqw %xmm1, %xmm8, %xmm7 -; AVX512-NEXT: vpblendvb %xmm7, %xmm1, %xmm3, %xmm1 -; AVX512-NEXT: vcvtph2ps %xmm5, %xmm3 +; AVX512-NEXT: vpcmpeqw %xmm6, %xmm1, %xmm6 +; AVX512-NEXT: vpblendvb %xmm6, %xmm1, %xmm4, %xmm1 +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; AVX512-NEXT: vucomiss %xmm5, %xmm3 +; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $65535, %ecx # imm = 0xFFFF ; AVX512-NEXT: movl $0, %edx ; AVX512-NEXT: cmovel %ecx, %edx -; AVX512-NEXT: vcvtph2ps %xmm4, %xmm3 -; AVX512-NEXT: vucomiss %xmm5, %xmm3 +; AVX512-NEXT: vcvtph2ps %xmm5, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %esi ; AVX512-NEXT: cmovel %ecx, %esi -; AVX512-NEXT: vcvtph2ps %xmm6, %xmm3 -; AVX512-NEXT: vucomiss %xmm5, %xmm3 +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %edi ; AVX512-NEXT: cmovel %ecx, %edi -; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 -; AVX512-NEXT: vucomiss %xmm5, %xmm2 +; AVX512-NEXT: vcvtph2ps %xmm7, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %r8d ; AVX512-NEXT: cmovel %ecx, %r8d ; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload -; AVX512-NEXT: vucomiss %xmm5, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %r9d ; AVX512-NEXT: cmovel %ecx, %r9d ; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload -; AVX512-NEXT: vucomiss %xmm5, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %r10d ; AVX512-NEXT: cmovel %ecx, %r10d -; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload -; AVX512-NEXT: vucomiss %xmm5, %xmm2 +; AVX512-NEXT: vcvtph2ps (%rsp), %xmm2 # 16-byte Folded Reload +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: movl $0, %r11d ; AVX512-NEXT: cmovel %ecx, %r11d ; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload -; AVX512-NEXT: vucomiss %xmm5, %xmm2 +; AVX512-NEXT: vucomiss %xmm4, %xmm2 ; AVX512-NEXT: vmovd %esi, %xmm2 ; AVX512-NEXT: vpinsrw $1, %edx, %xmm2, %xmm2 ; AVX512-NEXT: vpinsrw $2, %edi, %xmm2, %xmm2 @@ -2114,7 +2068,7 @@ define <4 x half> @test_fmaximumnum_v4f16(<4 x half> %x, <4 x half> %y) nounwind ; AVX512-NEXT: cmovel %ecx, %eax ; AVX512-NEXT: vpinsrw $7, %eax, %xmm2, %xmm2 ; AVX512-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: addq $72, %rsp +; AVX512-NEXT: addq $56, %rsp ; AVX512-NEXT: retq ; ; AVX10_2-LABEL: test_fmaximumnum_v4f16: