From 2303a1da43d8926280b5778f35bb72b81c06b59e Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 22 Sep 2017 18:31:56 -0300 Subject: [PATCH 1/6] lpc: Introduce LPCOpen for LPC18xx/43xx LPCOpen library for LPC18xx/43xx v3.01. Signed-off-by: Ezequiel Garcia --- ports/lpc/chips/lpc_chip_43xx/README | 2 + .../chips/lpc_chip_43xx/inc/adc_18xx_43xx.h | 274 + .../chips/lpc_chip_43xx/inc/aes_18xx_43xx.h | 167 + .../lpc_chip_43xx/inc/arm_common_tables.h | 99 + ports/lpc/chips/lpc_chip_43xx/inc/arm_math.h | 7312 +++++++++++++++++ .../lpc_chip_43xx/inc/atimer_18xx_43xx.h | 149 + .../chips/lpc_chip_43xx/inc/ccan_18xx_43xx.h | 511 ++ .../lpc_chip_43xx/inc/cguccu_18xx_43xx.h | 120 + ports/lpc/chips/lpc_chip_43xx/inc/chip.h | 169 + .../lpc/chips/lpc_chip_43xx/inc/chip_clocks.h | 258 + .../chips/lpc_chip_43xx/inc/chip_lpc18xx.h | 218 + .../chips/lpc_chip_43xx/inc/chip_lpc43xx.h | 229 + .../chips/lpc_chip_43xx/inc/clock_18xx_43xx.h | 400 + ports/lpc/chips/lpc_chip_43xx/inc/cmsis.h | 69 + .../lpc/chips/lpc_chip_43xx/inc/cmsis_18xx.h | 172 + .../lpc/chips/lpc_chip_43xx/inc/cmsis_43xx.h | 173 + .../lpc_chip_43xx/inc/cmsis_43xx_m0app.h | 156 + .../lpc_chip_43xx/inc/cmsis_43xx_m0sub.h | 151 + .../inc/config_43xx/cmsis_43xx.h | 173 + .../inc/config_43xx/sys_config.h | 36 + ports/lpc/chips/lpc_chip_43xx/inc/core_cm0.h | 688 ++ .../chips/lpc_chip_43xx/inc/core_cm0plus.h | 799 ++ ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h | 1633 ++++ ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h | 1778 ++++ .../chips/lpc_chip_43xx/inc/core_cm4_simd.h | 679 ++ .../lpc/chips/lpc_chip_43xx/inc/core_cmFunc.h | 642 ++ .../chips/lpc_chip_43xx/inc/core_cmInstr.h | 694 ++ .../lpc/chips/lpc_chip_43xx/inc/core_sc000.h | 819 ++ .../lpc/chips/lpc_chip_43xx/inc/core_sc300.h | 1604 ++++ .../chips/lpc_chip_43xx/inc/creg_18xx_43xx.h | 244 + .../chips/lpc_chip_43xx/inc/dac_18xx_43xx.h | 172 + ports/lpc/chips/lpc_chip_43xx/inc/eeprom.h | 76 + .../lpc_chip_43xx/inc/eeprom_18xx_43xx.h | 281 + .../chips/lpc_chip_43xx/inc/emc_18xx_43xx.h | 360 + .../chips/lpc_chip_43xx/inc/enet_18xx_43xx.h | 686 ++ ports/lpc/chips/lpc_chip_43xx/inc/error.h | 278 + .../chips/lpc_chip_43xx/inc/evrt_18xx_43xx.h | 179 + .../chips/lpc_chip_43xx/inc/fmc_18xx_43xx.h | 160 + ports/lpc/chips/lpc_chip_43xx/inc/fpu_init.h | 58 + .../chips/lpc_chip_43xx/inc/gima_18xx_43xx.h | 72 + .../chips/lpc_chip_43xx/inc/gpdma_18xx_43xx.h | 424 + .../chips/lpc_chip_43xx/inc/gpio_18xx_43xx.h | 509 ++ .../lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h | 211 + .../chips/lpc_chip_43xx/inc/hsadc_18xx_43xx.h | 581 ++ .../chips/lpc_chip_43xx/inc/i2c_18xx_43xx.h | 406 + .../lpc_chip_43xx/inc/i2c_common_18xx_43xx.h | 206 + .../chips/lpc_chip_43xx/inc/i2cm_18xx_43xx.h | 425 + .../chips/lpc_chip_43xx/inc/i2s_18xx_43xx.h | 566 ++ ports/lpc/chips/lpc_chip_43xx/inc/iap.h | 190 + .../chips/lpc_chip_43xx/inc/iap_18xx_43xx.h | 217 + .../chips/lpc_chip_43xx/inc/lcd_18xx_43xx.h | 389 + ports/lpc/chips/lpc_chip_43xx/inc/lpc_types.h | 228 + .../chips/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h | 86 + .../chips/lpc_chip_43xx/inc/otp_18xx_43xx.h | 150 + ports/lpc/chips/lpc_chip_43xx/inc/packing.h | 45 + .../lpc_chip_43xx/inc/pinint_18xx_43xx.h | 258 + .../chips/lpc_chip_43xx/inc/pmc_18xx_43xx.h | 105 + .../chips/lpc_chip_43xx/inc/qei_18xx_43xx.h | 92 + .../chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h | 164 + .../lpc/chips/lpc_chip_43xx/inc/ring_buffer.h | 194 + .../lpc_chip_43xx/inc/ritimer_18xx_43xx.h | 195 + .../lpc_chip_43xx/inc/romapi_18xx_43xx.h | 134 + .../chips/lpc_chip_43xx/inc/rtc_18xx_43xx.h | 644 ++ ports/lpc/chips/lpc_chip_43xx/inc/rtc_ut.h | 90 + .../chips/lpc_chip_43xx/inc/sct_18xx_43xx.h | 429 + .../lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h | 184 + .../chips/lpc_chip_43xx/inc/scu_18xx_43xx.h | 253 + .../chips/lpc_chip_43xx/inc/sdif_18xx_43xx.h | 485 ++ .../chips/lpc_chip_43xx/inc/sdio_18xx_43xx.h | 284 + ports/lpc/chips/lpc_chip_43xx/inc/sdmmc.h | 456 + .../chips/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h | 157 + .../chips/lpc_chip_43xx/inc/sgpio_18xx_43xx.h | 114 + .../chips/lpc_chip_43xx/inc/spi_18xx_43xx.h | 422 + .../chips/lpc_chip_43xx/inc/spifi_18xx_43xx.h | 355 + .../chips/lpc_chip_43xx/inc/ssp_18xx_43xx.h | 604 ++ ports/lpc/chips/lpc_chip_43xx/inc/stopwatch.h | 143 + .../chips/lpc_chip_43xx/inc/timer_18xx_43xx.h | 451 + .../chips/lpc_chip_43xx/inc/uart_18xx_43xx.h | 832 ++ .../chips/lpc_chip_43xx/inc/usbd_rom/usbd.h | 711 ++ .../lpc_chip_43xx/inc/usbd_rom/usbd_adc.h | 383 + .../lpc_chip_43xx/inc/usbd_rom/usbd_cdc.h | 255 + .../lpc_chip_43xx/inc/usbd_rom/usbd_cdcuser.h | 535 ++ .../lpc_chip_43xx/inc/usbd_rom/usbd_core.h | 591 ++ .../lpc_chip_43xx/inc/usbd_rom/usbd_desc.h | 54 + .../lpc_chip_43xx/inc/usbd_rom/usbd_dfu.h | 126 + .../lpc_chip_43xx/inc/usbd_rom/usbd_dfuuser.h | 276 + .../lpc_chip_43xx/inc/usbd_rom/usbd_hid.h | 437 + .../lpc_chip_43xx/inc/usbd_rom/usbd_hiduser.h | 427 + .../lpc_chip_43xx/inc/usbd_rom/usbd_hw.h | 463 ++ .../lpc_chip_43xx/inc/usbd_rom/usbd_msc.h | 125 + .../lpc_chip_43xx/inc/usbd_rom/usbd_mscuser.h | 276 + .../lpc_chip_43xx/inc/usbd_rom/usbd_rom_api.h | 98 + .../chips/lpc_chip_43xx/inc/usbhs_18xx_43xx.h | 129 + .../chips/lpc_chip_43xx/inc/wwdt_18xx_43xx.h | 233 + .../chips/lpc_chip_43xx/src/adc_18xx_43xx.c | 263 + .../chips/lpc_chip_43xx/src/aes_18xx_43xx.c | 180 + .../lpc_chip_43xx/src/atimer_18xx_43xx.c | 69 + .../chips/lpc_chip_43xx/src/ccan_18xx_43xx.c | 317 + .../chips/lpc_chip_43xx/src/chip_18xx_43xx.c | 123 + .../chips/lpc_chip_43xx/src/clock_18xx_43xx.c | 832 ++ .../chips/lpc_chip_43xx/src/dac_18xx_43xx.c | 91 + .../lpc_chip_43xx/src/eeprom_18xx_43xx.c | 106 + .../chips/lpc_chip_43xx/src/emc_18xx_43xx.c | 295 + .../chips/lpc_chip_43xx/src/enet_18xx_43xx.c | 188 + .../chips/lpc_chip_43xx/src/evrt_18xx_43xx.c | 117 + ports/lpc/chips/lpc_chip_43xx/src/fpu_init.c | 103 + .../chips/lpc_chip_43xx/src/gpdma_18xx_43xx.c | 752 ++ .../chips/lpc_chip_43xx/src/gpio_18xx_43xx.c | 66 + .../lpc_chip_43xx/src/gpiogroup_18xx_43xx.c | 54 + .../chips/lpc_chip_43xx/src/i2c_18xx_43xx.c | 560 ++ .../chips/lpc_chip_43xx/src/i2cm_18xx_43xx.c | 274 + .../chips/lpc_chip_43xx/src/i2s_18xx_43xx.c | 264 + .../chips/lpc_chip_43xx/src/iap_18xx_43xx.c | 211 + .../chips/lpc_chip_43xx/src/lcd_18xx_43xx.c | 212 + .../chips/lpc_chip_43xx/src/otp_18xx_43xx.c | 151 + .../lpc_chip_43xx/src/pinint_18xx_43xx.c | 54 + .../chips/lpc_chip_43xx/src/pmc_18xx_43xx.c | 75 + .../lpc/chips/lpc_chip_43xx/src/ring_buffer.c | 173 + .../lpc_chip_43xx/src/ritimer_18xx_43xx.c | 103 + .../chips/lpc_chip_43xx/src/rtc_18xx_43xx.c | 226 + .../chips/lpc_chip_43xx/src/sct_18xx_43xx.c | 93 + .../lpc_chip_43xx/src/sct_pwm_18xx_43xx.c | 93 + .../chips/lpc_chip_43xx/src/sdif_18xx_43xx.c | 229 + .../chips/lpc_chip_43xx/src/sdmmc_18xx_43xx.c | 598 ++ .../chips/lpc_chip_43xx/src/spi_18xx_43xx.c | 233 + .../chips/lpc_chip_43xx/src/ssp_18xx_43xx.c | 475 ++ .../lpc_chip_43xx/src/stopwatch_18xx_43xx.c | 112 + .../lpc_chip_43xx/src/sysinit_18xx_43xx.c | 166 + .../chips/lpc_chip_43xx/src/timer_18xx_43xx.c | 123 + .../chips/lpc_chip_43xx/src/uart_18xx_43xx.c | 430 + .../chips/lpc_chip_43xx/src/wwdt_18xx_43xx.c | 84 + 131 files changed, 48032 insertions(+) create mode 100644 ports/lpc/chips/lpc_chip_43xx/README create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/adc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/aes_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/arm_common_tables.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/arm_math.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/atimer_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/ccan_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cguccu_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/chip.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/chip_clocks.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc18xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/clock_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cmsis.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cmsis_18xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0app.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/sys_config.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cm0.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cm0plus.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cm4_simd.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cmFunc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_cmInstr.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_sc000.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/core_sc300.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/creg_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/dac_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/eeprom.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/eeprom_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/emc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/enet_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/error.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/evrt_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/fmc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/fpu_init.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/gima_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/gpdma_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/gpio_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/hsadc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/i2c_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/i2cm_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/i2s_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/iap.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/lcd_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/lpc_types.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/otp_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/packing.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/pinint_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/pmc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/qei_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/ring_buffer.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/ritimer_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/rtc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/rtc_ut.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sct_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/scu_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sdif_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sdio_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sdmmc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/sgpio_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/spi_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/spifi_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/ssp_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/stopwatch.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/timer_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/uart_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_adc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdcuser.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_core.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_desc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfu.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfuuser.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hid.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hiduser.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hw.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_msc.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_mscuser.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_rom_api.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/usbhs_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/inc/wwdt_18xx_43xx.h create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/aes_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/atimer_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/ccan_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/chip_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/clock_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/dac_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/eeprom_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/emc_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/enet_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/evrt_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/fpu_init.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/gpdma_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/gpio_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/gpiogroup_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/i2c_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/i2cm_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/i2s_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/iap_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/otp_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/pinint_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/pmc_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/ring_buffer.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/ritimer_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/rtc_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/sct_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/sct_pwm_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/sdif_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/sdmmc_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/ssp_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/stopwatch_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/sysinit_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/timer_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/wwdt_18xx_43xx.c diff --git a/ports/lpc/chips/lpc_chip_43xx/README b/ports/lpc/chips/lpc_chip_43xx/README new file mode 100644 index 0000000000000..f3a0855b909aa --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/README @@ -0,0 +1,2 @@ +All files from LPCOpen v3.01 (Release Date: 03/24/2017), except: +- startup.c diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/adc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/adc_18xx_43xx.h new file mode 100644 index 0000000000000..9062853fc66be --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/adc_18xx_43xx.h @@ -0,0 +1,274 @@ +/* + * @brief LPC18xx/43xx A/D conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ADC_18XX_43XX_H_ +#define __ADC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define ADC_ACC_10BITS + +#define ADC_MAX_SAMPLE_RATE 400000 + +/** + * @brief 10 or 12-bit ADC register block structure + */ +typedef struct { /*!< ADCn Structure */ + __IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ + __I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */ + __I uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ + __I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ + __I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ +} LPC_ADC_T; + +/** + * @brief ADC register support bitfields and mask + */ + +#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */ +#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */ +#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */ +#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */ +#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */ +#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */ +#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */ +#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */ +#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */ +#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */ +#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */ +#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */ +#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */ +#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */ +#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */ +#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */ +#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */ +#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07)) + +/** + * @brief ADC status register used for IP drivers + */ +typedef enum IP_ADC_STATUS { + ADC_DR_DONE_STAT, /*!< ADC data register staus */ + ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */ + ADC_DR_ADINT_STAT /*!< ADC interrupt status */ +} ADC_STATUS_T; + +/** The channels on one ADC peripheral*/ +typedef enum CHIP_ADC_CHANNEL { + ADC_CH0 = 0, /**< ADC channel 0 */ + ADC_CH1, /**< ADC channel 1 */ + ADC_CH2, /**< ADC channel 2 */ + ADC_CH3, /**< ADC channel 3 */ + ADC_CH4, /**< ADC channel 4 */ + ADC_CH5, /**< ADC channel 5 */ + ADC_CH6, /**< ADC channel 6 */ + ADC_CH7, /**< ADC channel 7 */ +} ADC_CHANNEL_T; + +/** The number of bits of accuracy of the result in the LS bits of ADDR*/ +typedef enum CHIP_ADC_RESOLUTION { + ADC_10BITS = 0, /**< ADC 10 bits */ + ADC_9BITS, /**< ADC 9 bits */ + ADC_8BITS, /**< ADC 8 bits */ + ADC_7BITS, /**< ADC 7 bits */ + ADC_6BITS, /**< ADC 6 bits */ + ADC_5BITS, /**< ADC 5 bits */ + ADC_4BITS, /**< ADC 4 bits */ + ADC_3BITS, /**< ADC 3 bits */ +} ADC_RESOLUTION_T; + +/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */ +typedef enum CHIP_ADC_EDGE_CFG { + ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */ + ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */ +} ADC_EDGE_CFG_T; + +/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */ +typedef enum CHIP_ADC_START_MODE { + ADC_NO_START = 0, + ADC_START_NOW, /*!< Start conversion now */ + ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */ + ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */ + ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */ + ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */ + ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */ +} ADC_START_MODE_T; + +/** Clock setup structure for ADC controller passed to the initialize function */ +typedef struct { + uint32_t adcRate; /*!< ADC rate */ + uint8_t bitsAccuracy; /*!< ADC bit accuracy */ + bool burstMode; /*!< ADC Burt Mode */ +} ADC_CLOCK_SETUP_T; + +/** + * @brief Initialize the ADC peripheral and the ADC setup structure to default value + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be set + * @return Nothing + * @note Default setting for ADC is 400kHz - 10bits + */ +void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup); + +/** + * @brief Shutdown ADC + * @param pADC : The base of ADC peripheral on the chip + * @return Nothing + */ +void Chip_ADC_DeInit(LPC_ADC_T *pADC); + +/** + * @brief Read the ADC value from a channel + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param data : Pointer to where to put data + * @return SUCCESS or ERROR if no conversion is ready + */ +Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data); + +/** + * @brief Read the ADC value and convert it to 8bits value + * @param pADC : The base of ADC peripheral on the chip + * @param channel: selected channel + * @param data : Storage for data + * @return Status : ERROR or SUCCESS + */ +Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data); + +/** + * @brief Read the ADC channel status + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param StatusType : Status type of ADC_DR_* + * @return SET or RESET + */ +FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType); + +/** + * @brief Enable/Disable interrupt for ADC channel + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param NewState : New state, ENABLE or DISABLE + * @return SET or RESET + */ +void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState); + +/** + * @brief Enable/Disable global interrupt for ADC channel + * @param pADC : The base of ADC peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState) +{ + Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState); +} + +/** + * @brief Select the mode starting the AD conversion + * @param pADC : The base of ADC peripheral on the chip + * @param mode : Stating mode, should be : + * - ADC_NO_START : Must be set for Burst mode + * - ADC_START_NOW : Start conversion now + * - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15 + * - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8 + * - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 + * - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 + * - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 + * @param EdgeOption : Stating Edge Condition, should be : + * - ADC_TRIGGERMODE_RISING : Trigger event on rising edge + * - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge + * @return Nothing + */ +void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption); + +/** + * @brief Set the ADC Sample rate + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be modified + * @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz. + * @return Nothing + */ +void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate); + +/** + * @brief Set the ADC accuracy bits + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be modified + * @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS + * @return Nothing + */ +void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution); + +/** + * @brief Enable or disable the ADC channel on ADC peripheral + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel to be enable or disable + * @param NewState : New state, should be: + * - ENABLE + * - DISABLE + * @return Nothing + */ +void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState); + +/** + * @brief Enable burst mode + * @param pADC : The base of ADC peripheral on the chip + * @param NewState : New state, should be: + * - ENABLE + * - DISABLE + * @return Nothing + */ +void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/aes_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/aes_18xx_43xx.h new file mode 100644 index 0000000000000..027c93abefa05 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/aes_18xx_43xx.h @@ -0,0 +1,167 @@ +/* + * @brief LPC18xx/43xx AES Engine driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __AES_18XX_43XX_H_ +#define __AES_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup AES_18XX_43XX CHIP: LPC18xx/43xx AES Engine driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief AES Engine operation mode + */ +typedef enum CHIP_AES_OP_MODE { + CHIP_AES_API_CMD_ENCODE_ECB, /*!< ECB Encode mode */ + CHIP_AES_API_CMD_DECODE_ECB, /*!< ECB Decode mode */ + CHIP_AES_API_CMD_ENCODE_CBC, /*!< CBC Encode mode */ + CHIP_AES_API_CMD_DECODE_CBC, /*!< CBC Decode mode */ +} CHIP_AES_OP_MODE_T; + +/** + * @brief Initialize the AES Engine function + * @return None + * This function will initialize all the AES Engine driver function pointers + * and call the AES Engine Initialization function. + */ +void Chip_AES_Init(void); + +/** + * @brief Set operation mode in AES Engine + * @param AesMode : AES Operation Mode + * @return Status + */ +uint32_t Chip_AES_SetMode(CHIP_AES_OP_MODE_T AesMode); + +/** + * @brief Load 128-bit AES user key in AES Engine + * @param keyNum: 0 - Load AES 128-bit user key 1, else load user key2 + * @return None + */ +void Chip_AES_LoadKey(uint32_t keyNum); + +/** + * @brief Load randomly generated key in AES engine + * @return None + * To update the RNG and load a new random number, + * the API call Chip_OTP_GenRand should be used + */ +void Chip_AES_LoadKeyRNG(void); + +/** + * @brief Load 128-bit AES software defined user key in AES Engine + * @param pKey : Pointer to 16 byte user key + * @return None + */ +void Chip_AES_LoadKeySW(uint8_t *pKey); + +/** + * @brief Load 128-bit AES initialization vector in AES Engine + * @param pVector : Pointer to 16 byte Initialisation vector + * @return None + */ +void Chip_AES_LoadIV_SW(uint8_t *pVector); + +/** + * @brief Load IC specific 128-bit AES initialization vector in AES Engine + * @return None + * This loads 128-bit AES IC specific initialization vector, + * which is used to decrypt a boot image + */ +void Chip_AES_LoadIV_IC(void); + +/** + * @brief Operate AES Engine + * @param pDatOut : Pointer to output data stream + * @param pDatIn : Pointer to input data stream + * @param Size : Size of the data stream (128-bit) + * @return Status + * This function performs the AES operation after the AES mode + * has been set using Chip_AES_SetMode and the appropriate keys + * and init vectors have been loaded + */ +uint32_t Chip_AES_Operate(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t Size); + +/** + * @brief Program 128-bit AES Key in OTP + * @param KeyNum : Key Number (Select 0 or 1) + * @param pKey : Pointer to AES Key (16 bytes required) + * @return Status + * When calling the aes_ProgramKey2 function, ensure that VPP = 2.7 V to 3.6 V. + */ +uint32_t Chip_AES_ProgramKey(uint32_t KeyNum, uint8_t *pKey); + +/** + * @brief Checks for valid AES configuration of the chip and setup + * DMA channel to process an AES data block. + * @param channel_id : channel id + * @return Status + */ +uint32_t Chip_AES_Config_DMA(uint32_t channel_id); + +/** + * @brief Checks for valid AES configuration of the chip and + * enables DMA channel to process an AES data block. + * @param channel_id : channel_id + * @param dataOutAddr : destination address(16 x size of consecutive bytes) + * @param dataInAddr : source address(16 x size of consecutive bytes) + * @param size : number of 128 bit AES blocks + * @return Status + */ +uint32_t Chip_AES_OperateDMA(uint32_t channel_id, uint8_t *dataOutAddr, uint8_t *dataInAddr, uint32_t size); + +/** + * @brief Read status of DMA channels that process an AES data block. + * @param channel_id : channel id + * @return Status + */ + uint32_t Chip_AES_GetStatusDMA(uint32_t channel_id); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __AES_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/arm_common_tables.h b/ports/lpc/chips/lpc_chip_43xx/inc/arm_common_tables.h new file mode 100644 index 0000000000000..d1bb64aa9b4b5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/arm_common_tables.h @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/arm_math.h b/ports/lpc/chips/lpc_chip_43xx/inc/arm_math.h new file mode 100644 index 0000000000000..34f38d7ead0d5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/arm_math.h @@ -0,0 +1,7312 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/atimer_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/atimer_18xx_43xx.h new file mode 100644 index 0000000000000..72538ff296dcf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/atimer_18xx_43xx.h @@ -0,0 +1,149 @@ +/* + * @brief LPC18xx/43xx Alarm Timer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ATIMER_18XX_43XX_H_ +#define __ATIMER_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx Alarm Timer driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Alarm Timer register block structure + */ +typedef struct { /*!< ATIMER Structure */ + __IO uint32_t DOWNCOUNTER; /*!< Downcounter register */ + __IO uint32_t PRESET; /*!< Preset value register */ + __I uint32_t RESERVED0[1012]; + __O uint32_t CLR_EN; /*!< Interrupt clear enable register */ + __O uint32_t SET_EN; /*!< Interrupt set enable register */ + __I uint32_t STATUS; /*!< Status register */ + __I uint32_t ENABLE; /*!< Enable register */ + __O uint32_t CLR_STAT; /*!< Clear register */ + __O uint32_t SET_STAT; /*!< Set register */ +} LPC_ATIMER_T; + +/** + * @brief Initialize Alarm Timer + * @param pATIMER : The base of ATIMER peripheral on the chip + * @param PresetValue : Count of 1 to 1024s for Alarm + * @return None + */ +void Chip_ATIMER_Init(LPC_ATIMER_T *pATIMER, uint32_t PresetValue); + +/** + * @brief Close ATIMER device + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return None + */ +void Chip_ATIMER_DeInit(LPC_ATIMER_T *pATIMER); + +/** + * @brief Enable ATIMER Interrupt + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_ATIMER_IntEnable(LPC_ATIMER_T *pATIMER) +{ + pATIMER->SET_EN = 1; +} + +/** + * @brief Disable ATIMER Interrupt + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_ATIMER_IntDisable(LPC_ATIMER_T *pATIMER) +{ + pATIMER->CLR_EN = 1; +} + +/** + * @brief Clear ATIMER Interrupt Status + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_ATIMER_ClearIntStatus(LPC_ATIMER_T *pATIMER) +{ + pATIMER->CLR_STAT = 1; +} + +/** + * @brief Set ATIMER Interrupt Status + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_ATIMER_SetIntStatus(LPC_ATIMER_T *pATIMER) +{ + pATIMER->SET_STAT = 1; +} + +/** + * @brief Update Preset value + * @param pATIMER : The base of ATIMER peripheral on the chip + * @param PresetValue : updated preset value + * @return Nothing + */ +STATIC INLINE void Chip_ATIMER_UpdatePresetValue(LPC_ATIMER_T *pATIMER, uint32_t PresetValue) +{ + pATIMER->PRESET = PresetValue; +} + +/** + * @brief Read value of preset register + * @param pATIMER : The base of ATIMER peripheral on the chip + * @return Value of capture register + */ +STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(LPC_ATIMER_T *pATIMER) +{ + return pATIMER->PRESET; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ATIMER_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/ccan_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/ccan_18xx_43xx.h new file mode 100644 index 0000000000000..7966d1a707182 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/ccan_18xx_43xx.h @@ -0,0 +1,511 @@ +/* + * @brief LPC18xx/43xx CCAN driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CCAN_18XX_43XX_H_ +#define __CCAN_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CCAN_18XX_43XX CHIP: LPC18xx/43xx CCAN driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief CCAN message interface register block structure + */ +typedef struct { /*!< C_CAN message interface Structure */ + __IO uint32_t CMDREQ; /*!< Message interface command request */ + __IO uint32_t CMDMSK; /*!< Message interface command mask*/ + __IO uint32_t MSK1; /*!< Message interface mask 1 */ + __IO uint32_t MSK2; /*!< Message interface mask 2 */ + __IO uint32_t ARB1; /*!< Message interface arbitration 1 */ + __IO uint32_t ARB2; /*!< Message interface arbitration 2 */ + __IO uint32_t MCTRL; /*!< Message interface message control */ + __IO uint32_t DA1; /*!< Message interface data A1 */ + __IO uint32_t DA2; /*!< Message interface data A2 */ + __IO uint32_t DB1; /*!< Message interface data B1 */ + __IO uint32_t DB2; /*!< Message interface data B2 */ + __I uint32_t RESERVED[13]; +} CCAN_IF_T; + +/** + * @brief CCAN Controller Area Network register block structure + */ +typedef struct { /*!< C_CAN Structure */ + __IO uint32_t CNTL; /*!< CAN control */ + __IO uint32_t STAT; /*!< Status register */ + __I uint32_t EC; /*!< Error counter */ + __IO uint32_t BT; /*!< Bit timing register */ + __I uint32_t INT; /*!< Interrupt register */ + __IO uint32_t TEST; /*!< Test register */ + __IO uint32_t BRPE; /*!< Baud rate prescaler extension register */ + __I uint32_t RESERVED0; + CCAN_IF_T IF[2]; + __I uint32_t RESERVED2[8]; + __I uint32_t TXREQ1; /*!< Transmission request 1 */ + __I uint32_t TXREQ2; /*!< Transmission request 2 */ + __I uint32_t RESERVED3[6]; + __I uint32_t ND1; /*!< New data 1 */ + __I uint32_t ND2; /*!< New data 2 */ + __I uint32_t RESERVED4[6]; + __I uint32_t IR1; /*!< Interrupt pending 1 */ + __I uint32_t IR2; /*!< Interrupt pending 2 */ + __I uint32_t RESERVED5[6]; + __I uint32_t MSGV1; /*!< Message valid 1 */ + __I uint32_t MSGV2; /*!< Message valid 2 */ + __I uint32_t RESERVED6[6]; + __IO uint32_t CLKDIV; /*!< CAN clock divider register */ +} LPC_CCAN_T; + +/* CCAN Control register bit definitions */ +#define CCAN_CTRL_INIT (1 << 0) /*!< Initialization is started. */ +#define CCAN_CTRL_IE (1 << 1) /*!< Module Interupt Enable. */ +#define CCAN_CTRL_SIE (1 << 2) /*!< Status Change Interupt Enable. */ +#define CCAN_CTRL_EIE (1 << 3) /*!< Error Interupt Enable. */ +#define CCAN_CTRL_DAR (1 << 5) /*!< Automatic retransmission disabled. */ +#define CCAN_CTRL_CCE (1 << 6) /*!< The CPU has write access to the CANBT register while the INIT bit is one.*/ +#define CCAN_CTRL_TEST (1 << 7) /*!< Test mode. */ + +/* CCAN STAT register bit definitions */ +#define CCAN_STAT_LEC_MASK (0x07) /* Mask for Last Error Code */ +#define CCAN_STAT_TXOK (1 << 3) /* Transmitted a message successfully */ +#define CCAN_STAT_RXOK (1 << 4) /* Received a message successfully */ +#define CCAN_STAT_EPASS (1 << 5) /* The CAN controller is in the error passive state*/ +#define CCAN_STAT_EWARN (1 << 6) /*At least one of the error counters in the EC has reached the error warning limit of 96.*/ +#define CCAN_STAT_BOFF (1 << 7) /*The CAN controller is in busoff state.*/ + +/** + * @brief Last Error Code definition + */ +typedef enum { + CCAN_LEC_NO_ERROR, /*!< No error */ + CCAN_LEC_STUFF_ERROR, /*!< More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ + CCAN_LEC_FORM_ERROR, /*!< A fixed format part of a received frame has the wrong format */ + CCAN_LEC_ACK_ERROR, /*!< The message this CAN core transmitted was not acknowledged. */ + CCAN_LEC_BIT1_ERROR, /*!< During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level + (bit of logical value "1"), but the monitored bus value was LOW/dominant. */ + CCAN_LEC_BIT0_ERROR, /*!< During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a + LOW/dominant level (data or identifier bit logical value "0"), but the monitored Bus value was HIGH/recessive. During busoff recovery this + status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables + the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed). */ + CCAN_LEC_CRC_ERROR, /*!< The CRC checksum was incorrect in the message received. */ +} CCAN_LEC_T; + +/* CCAN INT register bit definitions */ +#define CCAN_INT_NO_PENDING 0 /*!< No interrupt pending */ +#define CCAN_INT_STATUS 0x8000 /*!< Status interrupt*/ +#define CCAN_INT_MSG_NUM(n) (n) /*! + * - CCAN_CTRL_SIE
+ * - CCAN_CTRL_EIE
+ * @return Nothing + */ +STATIC INLINE void Chip_CCAN_EnableInt(LPC_CCAN_T *pCCAN, uint32_t mask) +{ + pCCAN->CNTL |= mask; +} + +/** + * @brief Disable CCAN Interrupts + * @param pCCAN : The base of CCAN peripheral on the chip + * @param mask : Interrupt mask, or-ed bit value of + * - CCAN_CTRL_IE
+ * - CCAN_CTRL_SIE
+ * - CCAN_CTRL_EIE
+ * @return Nothing + */ +STATIC INLINE void Chip_CCAN_DisableInt(LPC_CCAN_T *pCCAN, uint32_t mask) +{ + pCCAN->CNTL &= ~mask; +} + +/** + * @brief Get the source ID of an interrupt + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Interrupt source ID + */ +STATIC INLINE uint32_t Chip_CCAN_GetIntID(LPC_CCAN_T *pCCAN) +{ + return pCCAN->INT; +} + +/** + * @brief Get the CCAN status register + * @param pCCAN : The base of CCAN peripheral on the chip + * @return CCAN status register (or-ed bit value of CCAN_STAT_*) + */ +STATIC INLINE uint32_t Chip_CCAN_GetStatus(LPC_CCAN_T *pCCAN) +{ + return pCCAN->STAT; +} + +/** + * @brief Set the CCAN status + * @param pCCAN : The base of CCAN peripheral on the chip + * @param val : Value to be set for status register (or-ed bit value of CCAN_STAT_*) + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_SetStatus(LPC_CCAN_T *pCCAN, uint32_t val) +{ + pCCAN->STAT = val & 0x1F; +} + +/** + * @brief Clear the status of CCAN bus + * @param pCCAN : The base of CCAN peripheral on the chip + * @param val : Status to be cleared (or-ed bit value of CCAN_STAT_*) + * @return Nothing + */ +void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, uint32_t val); + +/** + * @brief Get the current value of the transmit/receive error counter + * @param pCCAN : The base of CCAN peripheral on the chip + * @param dir : direction + * @return Current value of the transmit/receive error counter + * @note When @a dir is #CCAN_RX_DIR, then MSB (bit-7) indicates the + * receiver error passive level, if the bit is High(1) then the reciever + * counter has reached error passive level as specified in CAN2.0 + * specification; else if the bit is Low(0) it indicates that the + * error counter is below the passive level. Bits from (bit6-0) has + * the actual error count. When @a dir is #CCAN_TX_DIR, the complete + * 8-bits indicates the number of tx errors. + */ +STATIC INLINE uint8_t Chip_CCAN_GetErrCounter(LPC_CCAN_T *pCCAN, CCAN_TRANSFER_DIR_T dir) +{ + return (dir == CCAN_TX_DIR) ? (pCCAN->EC & 0x0FF) : ((pCCAN->EC >> 8) & 0x0FF); +} + +/** + * @brief Enable test mode in CCAN + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_EnableTestMode(LPC_CCAN_T *pCCAN) +{ + pCCAN->CNTL |= CCAN_CTRL_TEST; +} + +/** + * @brief Enable test mode in CCAN + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_DisableTestMode(LPC_CCAN_T *pCCAN) +{ + pCCAN->CNTL &= ~CCAN_CTRL_TEST; +} + +/** + * @brief Enable/Disable test mode in CCAN + * @param pCCAN : The base of CCAN peripheral on the chip + * @param cfg : Test function, or-ed bit values of CCAN_TEST_* + * @return Nothing + * @note Test Mode must be enabled before using Chip_CCAN_EnableTestMode function. + */ +STATIC INLINE void Chip_CCAN_ConfigTestMode(LPC_CCAN_T *pCCAN, uint32_t cfg) +{ + pCCAN->TEST = cfg; +} + +/** + * @brief Enable automatic retransmission + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_EnableAutoRetransmit(LPC_CCAN_T *pCCAN) +{ + pCCAN->CNTL &= ~CCAN_CTRL_DAR; +} + +/** + * @brief Disable automatic retransmission + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_DisableAutoRetransmit(LPC_CCAN_T *pCCAN) +{ + pCCAN->CNTL |= CCAN_CTRL_DAR; +} + +/** + * @brief Get the transmit repuest bit in all message objects + * @param pCCAN : The base of CCAN peripheral on the chip + * @return A 32 bits value, each bit corresponds to transmit request bit in message objects + */ +STATIC INLINE uint32_t Chip_CCAN_GetTxRQST(LPC_CCAN_T *pCCAN) +{ + return pCCAN->TXREQ1 | (pCCAN->TXREQ2 << 16); +} + +/** + * @brief Initialize the CCAN peripheral, free all message object in RAM + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +void Chip_CCAN_Init(LPC_CCAN_T *pCCAN); + +/** + * @brief De-initialize the CCAN peripheral + * @param pCCAN : The base of CCAN peripheral on the chip + * @return Nothing + */ +void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN); + +/** + * @brief Select bit rate for CCAN bus + * @param pCCAN : The base of CCAN peripheral on the chip + * @param bitRate : Bit rate to be set + * @return SUCCESS/ERROR + */ +Status Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate); + +/** Number of message objects in Message RAM */ +#define CCAN_MSG_MAX_NUM 32 + +/** + * @brief CAN message object structure + */ +typedef struct { + uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */ + uint32_t dlc; /**< Message data length */ + uint8_t data[8]; /**< Message data */ +} CCAN_MSG_OBJ_T; + +typedef enum { + CCAN_MSG_IF1 = 0, + CCAN_MSG_IF2 = 1, +} CCAN_MSG_IF_T; + +/* bit field of IF command request n register */ +#define CCAN_IF_CMDREQ_MSG_NUM(n) (n) /* Message number (1->20) */ +#define CCAN_IF_CMDREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when RD/WR done */ + +/* bit field of IF command mask register */ +#define CCAN_IF_CMDMSK_DATAB (1 << 0) /** 1 is transfer data byte 4-7 to message object, 0 is not */ +#define CCAN_IF_CMDMSK_DATAA (1 << 1) /** 1 is transfer data byte 0-3 to message object, 0 is not */ +#define CCAN_IF_CMDMSK_W_TXRQST (1 << 2) /** Request a transmission. Set the TXRQST bit IF1/2_MCTRL. */ +#define CCAN_IF_CMDMSK_R_NEWDAT (1 << 2) /** Clear NEWDAT bit in the message object */ +#define CCAN_IF_CMDMSK_R_CLRINTPND (1 << 3) /** Clear INTPND bit in the message object. */ +#define CCAN_IF_CMDMSK_CTRL (1 << 4) /** 1 is transfer the CTRL bit to the message object, 0 is not */ +#define CCAN_IF_CMDMSK_ARB (1 << 5) /** 1 is transfer the ARB bits to the message object, 0 is not */ +#define CCAN_IF_CMDMSK_MASK (1 << 6) /** 1 is transfer the MASK bit to the message object, 0 is not */ +#define CCAN_IF_CMDMSK_WR (1 << 7) /* Tranfer direction: Write */ +#define CCAN_IF_CMDMSK_RD (0) /* Tranfer direction: Read */ +#define CCAN_IF_CMDMSK_TRANSFER_ALL (CCAN_IF_CMDMSK_CTRL | CCAN_IF_CMDMSK_MASK | CCAN_IF_CMDMSK_ARB | \ + CCAN_IF_CMDMSK_DATAB | CCAN_IF_CMDMSK_DATAA) + +/* bit field of IF mask 2 register */ +#define CCAN_IF_MASK2_MXTD (1 << 15) /* 1 is extended identifier bit is used in the RX filter unit, 0 is not */ +#define CCAN_IF_MASK2_MDIR(n) (((n) & 0x01) << 14) /* 1 is direction bit is used in the RX filter unit, 0 is not */ + +/* bit field of IF arbitration 2 register */ +#define CCAN_IF_ARB2_DIR(n) (((n) & 0x01) << 13) /* 1: Dir = transmit, 0: Dir = receive */ +#define CCAN_IF_ARB2_XTD (1 << 14) /* Extended identifier bit is used*/ +#define CCAN_IF_ARB2_MSGVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */ + +/* bit field of IF message control register */ +#define CCAN_IF_MCTRL_DLC_MSK 0x000F /* bit mask for DLC */ +#define CCAN_IF_MCTRL_EOB (1 << 7) /* End of buffer, always write to 1 */ +#define CCAN_IF_MCTRL_TXRQ (1 << 8) /* 1 is TxRqst enabled */ +#define CCAN_IF_MCTRL_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */ +#define CCAN_IF_MCTRL_RXIE (1 << 10) /* 1 is RX interrupt enabled */ +#define CCAN_IF_MCTRL_TXIE (1 << 11) /* 1 is TX interrupt enabled */ +#define CCAN_IF_MCTRL_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */ +#define CCAN_IF_MCTRL_INTP (1 << 13) /* 1 indicates message object is an interrupt source */ +#define CCAN_IF_MCTRL_MLST (1 << 14) /* 1 indicates a message loss. */ +#define CCAN_IF_MCTRL_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */ + +#define CCAN_MSG_ID_STD_MASK 0x07FF +#define CCAN_MSG_ID_EXT_MASK 0x1FFFFFFF + +/** + * @brief Tranfer message object between IF registers and Message RAM + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param mask : command mask (or-ed bit value of CCAN_IF_CMDMSK_*) + * @param msgNum : The number of message object in message RAM to be get + * @return Nothing + */ +void Chip_CCAN_TransferMsgObject(LPC_CCAN_T *pCCAN, + CCAN_MSG_IF_T IFSel, + uint32_t mask, + uint32_t msgNum); + +/** + * @brief Set a message into the message object in message RAM + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param dir : transmit/receive + * @param remoteFrame: Enable/Disable passives transmit by using remote frame + * @param msgNum : Message number + * @param pMsgObj : Pointer of message to be set + * @return Nothing + */ +void Chip_CCAN_SetMsgObject (LPC_CCAN_T *pCCAN, + CCAN_MSG_IF_T IFSel, + CCAN_TRANSFER_DIR_T dir, + bool remoteFrame, + uint8_t msgNum, + const CCAN_MSG_OBJ_T *pMsgObj); + +/** + * @brief Get a message object in message RAM into the message buffer + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param msgNum : The number of message object in message RAM to be get + * @param pMsgObj : Pointer of the message buffer + * @return Nothing + */ +void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, CCAN_MSG_OBJ_T *pMsgObj); + +/** + * @brief Enable/Disable the message object to valid + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param msgNum : Message number + * @param valid : true: valid, false: invalide + * @return Nothing + */ +void Chip_CCAN_SetValidMsg(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, bool valid); + +/** + * @brief Check the message objects is valid or not + * @param pCCAN : The base of CCAN peripheral on the chip + * @return A 32 bits value, each bit corresponds to a message objects form 0 to 31 (1 is valid, 0 is invalid) + */ +STATIC INLINE uint32_t Chip_CCAN_GetValidMsg(LPC_CCAN_T *pCCAN) +{ + return pCCAN->MSGV1 | (pCCAN->MSGV2 << 16); +} + +/** + * @brief Clear the pending message interrupt + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param msgNum : Message number + * @param dir : Select transmit or receive interrupt to be cleared + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN, + CCAN_MSG_IF_T IFSel, + uint8_t msgNum, + CCAN_TRANSFER_DIR_T dir) +{ + Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum); +} + +/** + * @brief Clear new data flag bit in the message object + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param msgNum : Message number + * @return Nothing + */ +STATIC INLINE void Chip_CCAN_ClearNewDataFlag(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum) +{ + Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_NEWDAT, msgNum); +} + +/** + * @brief Send a message + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param remoteFrame: Enable/Disable passives transmit by using remote frame + * @param pMsgObj : Message to be transmitted + * @return Nothing + */ +void Chip_CCAN_Send (LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, bool remoteFrame, CCAN_MSG_OBJ_T *pMsgObj); + +/** + * @brief Register a message ID for receiving + * @param pCCAN : The base of CCAN peripheral on the chip + * @param IFSel : The Message interface to be used + * @param id : Received message ID + * @return Nothing + */ +void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id); + +/** + * @brief Remove a registered message ID from receiving + * @param IFSel : The Message interface to be used + * @param pCCAN : The base of CCAN peripheral on the chip + * @param id : Received message ID to be removed + * @return Nothing + */ +void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CCAN_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cguccu_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/cguccu_18xx_43xx.h new file mode 100644 index 0000000000000..cd077e0e84b3a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cguccu_18xx_43xx.h @@ -0,0 +1,120 @@ +/* + * @brief CGU/CCU registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CGUCCU_18XX_43XX_H_ +#define __CGUCCU_18XX_43XX_H_ + +#include "chip_clocks.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup CLOCK_18XX_43XX + * @{ + */ + +/** + * Audio or USB PLL selection + */ +typedef enum CHIP_CGU_USB_AUDIO_PLL { + CGU_USB_PLL, + CGU_AUDIO_PLL +} CHIP_CGU_USB_AUDIO_PLL_T; + +/** + * PLL register block + */ +typedef struct { + __I uint32_t PLL_STAT; /*!< PLL status register */ + __IO uint32_t PLL_CTRL; /*!< PLL control register */ + __IO uint32_t PLL_MDIV; /*!< PLL M-divider register */ + __IO uint32_t PLL_NP_DIV; /*!< PLL N/P-divider register */ +} CGU_PLL_REG_T; + +/** + * @brief LPC18XX/43XX CGU register block structure + */ +typedef struct { /*!< (@ 0x40050000) CGU Structure */ + __I uint32_t RESERVED0[5]; + __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ + __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ + CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /*!< (@ 0x4005001C) USB and audio PLL blocks */ + __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */ + __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ + __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ + __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */ + __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */ +} LPC_CGU_T; + +/** + * @brief CCU clock config/status register pair + */ +typedef struct { + __IO uint32_t CFG; /*!< CCU clock configuration register */ + __I uint32_t STAT; /*!< CCU clock status register */ +} CCU_CFGSTAT_T; + +/** + * @brief CCU1 register block structure + */ +typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ + __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ + __I uint32_t RESERVED0[62]; + CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */ +} LPC_CCU1_T; + +/** + * @brief CCU2 register block structure + */ +typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ + __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ + __I uint32_t RESERVED0[62]; + CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */ +} LPC_CCU2_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CGUCCU_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/chip.h b/ports/lpc/chips/lpc_chip_43xx/inc/chip.h new file mode 100644 index 0000000000000..273b4d931496e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/chip.h @@ -0,0 +1,169 @@ +/* + * @brief Chip inclusion selector file + * + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_H_ +#define __CHIP_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#if defined(CHIP_LPC18XX) +#include "chip_lpc18xx.h" + +#elif defined(CHIP_LPC43XX) +#include "chip_lpc43xx.h" + +#else +#error CHIP_LPC18XX or CHIP_LPC43XX must be defined +#endif + +/* Aliasing for Chip_USB_Init */ +#define Chip_USB_Init Chip_USB0_Init + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @ingroup CHIP_18XX_43XX_DRIVER_OPTIONS + * @{ + */ + +/** + * @brief System oscillator rate + * This value is defined externally to the chip layer and contains + * the value in Hz for the external oscillator for the board. If using the + * internal oscillator, this rate can be 0. + */ +extern const uint32_t OscRateIn; + +/** + * @brief Clock rate on the CLKIN pin + * This value is defined externally to the chip layer and contains + * the value in Hz for the CLKIN pin for the board. If this pin isn't used, + * this rate can be 0. + */ +extern const uint32_t ExtRateIn; + +/** + * @} + */ + +/** @defgroup SUPPORT_18XX_43XX_FUNC CHIP: LPC18xx/43xx support functions + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Current system clock rate, mainly used for sysTick + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Update system core clock rate, should be called if the + * system has a clock rate change + * @return None + */ +void SystemCoreClockUpdate(void); + +/** + * @brief USB0 Pin and clock initialization + * Calling this function will initialize the USB0 pins and the clock + * @note This function will assume that the chip is clocked by an + * external crystal oscillator of frequency 12MHz + */ +void Chip_USB0_Init(void); + +/** + * @brief USB1 Pin and clock initialization + * Calling this function will initialize the USB0 pins and the clock + * @note This function will assume that the chip is clocked by an + * external crystal oscillator of frequency 12MHz + */ +void Chip_USB1_Init(void); + +/** + * @brief Set up and initialize hardware prior to call to main() + * @return None + * @note Chip_SystemInit() is called prior to the application and sets up + * system clocking prior to the application starting. + */ +void Chip_SystemInit(void); + +/** + * @brief Clock and PLL initialization based input given in @a clkin + * @param clkin : Input reference clock to PLL1 (MAINPLL) see #CHIP_CGU_CLKIN_T + * @param core_freq : Desired output frequency of the PLL1 (Base clock to CPU Core) + * @param setbase : Setup default base clock of peripherals (see notes) + * @return None + * @note This API will initialize the MAINPLL (PLL1) to the frequency given by + * @a core_freq, and will use this PLL's output as the base clock for CPU + * Core. If @a clkin is #CLKIN_CRYSTAL then External Crystal Oscillator + * of frequency 12MHz will be used as the input reference clock to PLL1.
+ * Parameter @a setbase if true will set APB[1,3], SSP[0,1], UART[0,1,2,3], + * SPI base clocks to MAINPLL's output clock. If @a setbase is false then + * the base clock settings for the peripherals will not be modified, only + * CPU Core's base clock will be updated to use clock generated by PLL1. + */ +void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase); + +/** + * @brief Clock and PLL initialization based on the external oscillator + * @return None + * @note This API will initialize the MAINPLL (PLL1) to the maximum + * frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this + * PLL's output as the base clock for CPU Core. External Crystal Oscillator + * of frequency 12MHz will be used as the input reference clock to PLL1. + */ +void Chip_SetupXtalClocking(void); + +/** + * @brief Clock and PLL initialization based on the internal oscillator + * @return None + * @note This API will initialize the MAINPLL (PLL1) to the maximum + * frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this + * PLL's output as the base clock for CPU Core. Internal RC Oscillator + * will be used as the input reference clock to PLL1. + */ +void Chip_SetupIrcClocking(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/chip_clocks.h b/ports/lpc/chips/lpc_chip_43xx/inc/chip_clocks.h new file mode 100644 index 0000000000000..cacf8dc9efdbd --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/chip_clocks.h @@ -0,0 +1,258 @@ +/* + * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_CLOCKS_H_ +#define __CHIP_CLOCKS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup CLOCK_18XX_43XX + * @{ + */ + +/** + * @brief CGU clock input list + * These are possible input clocks for the CGU and can come + * from both external (crystal) and internal (PLL) sources. These + * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T). + */ +typedef enum CHIP_CGU_CLKIN { + CLKIN_32K, /*!< External 32KHz input */ + CLKIN_IRC, /*!< Internal IRC (12MHz) input */ + CLKIN_ENET_RX, /*!< External ENET_RX pin input */ + CLKIN_ENET_TX, /*!< External ENET_TX pin input */ + CLKIN_CLKIN, /*!< External GPCLKIN pin input */ + CLKIN_RESERVED1, + CLKIN_CRYSTAL, /*!< External (main) crystal pin input */ + CLKIN_USBPLL, /*!< Internal USB PLL input */ + CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */ + CLKIN_MAINPLL, /*!< Internal Main PLL input */ + CLKIN_RESERVED2, + CLKIN_RESERVED3, + CLKIN_IDIVA, /*!< Internal divider A input */ + CLKIN_IDIVB, /*!< Internal divider B input */ + CLKIN_IDIVC, /*!< Internal divider C input */ + CLKIN_IDIVD, /*!< Internal divider D input */ + CLKIN_IDIVE, /*!< Internal divider E input */ + CLKINPUT_PD /*!< External 32KHz input */ +} CHIP_CGU_CLKIN_T; + +/** + * @brief CGU base clocks + * CGU base clocks are clocks that are associated with a single input clock + * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH + * clock can be configured to use the CLKIN_MAINPLL input clock, which will in + * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and + * CLK_PERIPH_SGPIO periphral clocks. + */ +typedef enum CHIP_CGU_BASE_CLK { + CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */ + CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */ +#if defined(CHIP_LPC43XX) + CLK_BASE_PERIPH, /*!< Base clock for SGPIO */ +#else + CLK_BASE_RESERVED1, +#endif + CLK_BASE_USB1, /*!< Base USB clock for USB1 */ + CLK_BASE_MX, /*!< Base clock for CPU core */ + CLK_BASE_SPIFI, /*!< Base clock for SPIFI */ +#if defined(CHIP_LPC43XX) + CLK_BASE_SPI, /*!< Base clock for SPI */ +#else + CLK_BASE_RESERVED2, +#endif + CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */ + CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */ + CLK_BASE_APB1, /*!< Base clock for APB1 group */ + CLK_BASE_APB3, /*!< Base clock for APB3 group */ + CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */ +#if defined(CHIP_LPC43XX) + CLK_BASE_ADCHS, /*!< Base clock for ADCHS */ +#else + CLK_BASE_RESERVED3, +#endif + CLK_BASE_SDIO, /*!< Base clock for SDIO */ + CLK_BASE_SSP0, /*!< Base clock for SSP0 */ + CLK_BASE_SSP1, /*!< Base clock for SSP1 */ + CLK_BASE_UART0, /*!< Base clock for UART0 */ + CLK_BASE_UART1, /*!< Base clock for UART1 */ + CLK_BASE_UART2, /*!< Base clock for UART2 */ + CLK_BASE_UART3, /*!< Base clock for UART3 */ + CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */ + CLK_BASE_RESERVED4, + CLK_BASE_RESERVED5, + CLK_BASE_RESERVED6, + CLK_BASE_RESERVED7, + CLK_BASE_APLL, /*!< Base clock for audio PLL */ + CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */ + CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */ + CLK_BASE_LAST, + CLK_BASE_NONE = CLK_BASE_LAST +} CHIP_CGU_BASE_CLK_T; + +/** + * @brief CGU dividers + * CGU dividers provide an extra clock state where a specific clock can be + * divided before being routed to a peripheral group. A divider accepts an + * input clock and then divides it. To use the divided clock for a base clock + * group, use the divider as the input clock for the base clock (for example, + * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider). + */ +typedef enum CHIP_CGU_IDIV { + CLK_IDIV_A, /*!< CGU clock divider A */ + CLK_IDIV_B, /*!< CGU clock divider B */ + CLK_IDIV_C, /*!< CGU clock divider A */ + CLK_IDIV_D, /*!< CGU clock divider D */ + CLK_IDIV_E, /*!< CGU clock divider E */ + CLK_IDIV_LAST +} CHIP_CGU_IDIV_T; + +#define CHIP_CGU_IDIV_MASK(x) ("\x03\x0F\x0F\x0F\xFF"[x]) + +/** + * @brief Peripheral clocks + * Peripheral clocks are individual clocks routed to peripherals. Although + * multiple peripherals may share a same base clock, each peripheral's clock + * can be enabled or disabled individually. Some peripheral clocks also have + * additional dividers associated with them. + */ +typedef enum CHIP_CCU_CLK { + /* CCU1 clocks */ + CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */ + CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */ + CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */ + CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */ + CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */ + CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */ + CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */ + CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */ + CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */ + CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */ + CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */ + CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */ + CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */ + RESERVED_ALIGN = CLK_MX_MXCORE + 3, + CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */ + CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */ + CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */ + CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */ + CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */ +#if defined(CHIP_LPC43XX) + CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */ + CLK_MX_ADCHS, /*!< ADCHS clock from base clock CLK_BASE_ADCHS */ +#else + CLK_RESERVED1, + CLK_RESERVED2, +#endif + CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */ + CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */ + CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */ + CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */ + CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */ + CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */ + CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */ + CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */ +#if defined(CHIP_LPC43XX) + CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */ + CLK_RESERVED3, + CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */ + CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */ +#else + CLK_RESERVED3 = 192, + CLK_RESERVED3A, + CLK_RESERVED4, + CLK_RESERVED5, +#endif + CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */ + CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */ +#if defined(CHIP_LPC43XX) + CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */ + CLK_ADCHS = 320, /*!< ADCHS clock from base clock CLK_BASE_ADCHS */ +#else + CLK_RESERVED7 = 320, + CLK_RESERVED8, +#endif + CLK_CCU1_LAST, + + /* CCU2 clocks */ + CLK_CCU2_START, + CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */ + RESERVED_ALIGNB = CLK_CCU2_START + 31, + CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */ + RESERVED_ALIGNC = CLK_CCU2_START + 63, + CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */ + RESERVED_ALIGND = CLK_CCU2_START + 95, + CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */ + RESERVED_ALIGNE = CLK_CCU2_START + 127, + CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */ + RESERVED_ALIGNF = CLK_CCU2_START + 159, + CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */ + RESERVED_ALIGNG = CLK_CCU2_START + 191, + CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */ + RESERVED_ALIGNH = CLK_CCU2_START + 223, + CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */ + CLK_CCU2_LAST +} CHIP_CCU_CLK_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_CLOCKS_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc18xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc18xx.h new file mode 100644 index 0000000000000..525188e906e4c --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc18xx.h @@ -0,0 +1,218 @@ +/* + * @brief LPC18xx basic chip inclusion file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_LPC18XX_H_ +#define __CHIP_LPC18XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lpc_types.h" +#include "sys_config.h" + +#ifndef CORE_M3 +#error CORE_M3 is not defined for the LPC18xx architecture +#error CORE_M3 should be defined as part of your compiler define list +#endif + +#ifndef CHIP_LPC18XX +#error The LPC18XX Chip include path is used for this build, but +#error CHIP_LPC18XX is not defined! +#endif + +/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define LPC_SCT_BASE 0x40000000 +#define LPC_GPDMA_BASE 0x40002000 +#define LPC_SPIFI_BASE 0x40003000 +#define LPC_SDMMC_BASE 0x40004000 +#define LPC_EMC_BASE 0x40005000 +#define LPC_USB0_BASE 0x40006000 +#define LPC_USB1_BASE 0x40007000 +#define LPC_LCD_BASE 0x40008000 +#define LPC_FMCA_BASE 0x4000C000 +#define LPC_FMCB_BASE 0x4000D000 +#define LPC_ETHERNET_BASE 0x40010000 +#define LPC_ATIMER_BASE 0x40040000 +#define LPC_REGFILE_BASE 0x40041000 +#define LPC_PMC_BASE 0x40042000 +#define LPC_CREG_BASE 0x40043000 +#define LPC_EVRT_BASE 0x40044000 +#define LPC_OTP_BASE 0x40045000 +#define LPC_RTC_BASE 0x40046000 +#define LPC_CGU_BASE 0x40050000 +#define LPC_CCU1_BASE 0x40051000 +#define LPC_CCU2_BASE 0x40052000 +#define LPC_RGU_BASE 0x40053000 +#define LPC_WWDT_BASE 0x40080000 +#define LPC_USART0_BASE 0x40081000 +#define LPC_USART2_BASE 0x400C1000 +#define LPC_USART3_BASE 0x400C2000 +#define LPC_UART1_BASE 0x40082000 +#define LPC_SSP0_BASE 0x40083000 +#define LPC_SSP1_BASE 0x400C5000 +#define LPC_TIMER0_BASE 0x40084000 +#define LPC_TIMER1_BASE 0x40085000 +#define LPC_TIMER2_BASE 0x400C3000 +#define LPC_TIMER3_BASE 0x400C4000 +#define LPC_SCU_BASE 0x40086000 +#define LPC_PIN_INT_BASE 0x40087000 +#define LPC_GPIO_GROUP_INT0_BASE 0x40088000 +#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 +#define LPC_MCPWM_BASE 0x400A0000 +#define LPC_I2C0_BASE 0x400A1000 +#define LPC_I2C1_BASE 0x400E0000 +#define LPC_I2S0_BASE 0x400A2000 +#define LPC_I2S1_BASE 0x400A3000 +#define LPC_C_CAN1_BASE 0x400A4000 +#define LPC_RITIMER_BASE 0x400C0000 +#define LPC_QEI_BASE 0x400C6000 +#define LPC_GIMA_BASE 0x400C7000 +#define LPC_DAC_BASE 0x400E1000 +#define LPC_C_CAN0_BASE 0x400E2000 +#define LPC_ADC0_BASE 0x400E3000 +#define LPC_ADC1_BASE 0x400E4000 +#define LPC_GPIO_PORT_BASE 0x400F4000 +#define LPC_SPI_BASE 0x40100000 +#define LPC_SGPIO_BASE 0x40101000 +#define LPC_EEPROM_BASE 0x4000E000 +#define LPC_ROM_API_BASE 0x10400100 + +#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE) +#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE) +#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE) +#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE) +#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE) +#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE) +#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE) +#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE) +#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE) +#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE) +#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE) +#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE) +#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE) +#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE) +#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE) +#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE) +#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE) +#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE) +#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE) +#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE) +#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE) +#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE) +#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE) +#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE) +#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE) +#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE) +#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE) +#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE) +#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE) +#define LPC_GPIO_PIN_INT ((LPC_PIN_INT_T *) LPC_PIN_INT_BASE) +#define LPC_GPIOGROUP ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE) +#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE) +#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE) +#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE) +#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE) +#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE) +#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE) +#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE) +#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE) +#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE) +#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE) +#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE) +#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE) +#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE) +#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE) +#define LPC_FMCA ((LPC_FMC_T *) LPC_FMCA_BASE) +#define LPC_FMCB ((LPC_FMC_T *) LPC_FMCB_BASE) +#define LPC_ROM_API ((LPC_ROM_API_T *) LPC_ROM_API_BASE) + +/** + * @} + */ + +#include "scu_18xx_43xx.h" +#include "clock_18xx_43xx.h" +#include "rgu_18xx_43xx.h" +#include "creg_18xx_43xx.h" +#include "evrt_18xx_43xx.h" +#include "otp_18xx_43xx.h" +#include "sdif_18xx_43xx.h" +#include "adc_18xx_43xx.h" +#include "atimer_18xx_43xx.h" +#include "aes_18xx_43xx.h" +#include "ccan_18xx_43xx.h" +#include "dac_18xx_43xx.h" +#include "eeprom_18xx_43xx.h" +#include "emc_18xx_43xx.h" +#include "enet_18xx_43xx.h" +#include "fmc_18xx_43xx.h" +#include "i2c_18xx_43xx.h" +#include "i2s_18xx_43xx.h" +#include "gima_18xx_43xx.h" +#include "gpdma_18xx_43xx.h" +#include "gpio_18xx_43xx.h" +#include "pinint_18xx_43xx.h" +#include "gpiogroup_18xx_43xx.h" +#include "lcd_18xx_43xx.h" +#include "mcpwm_18xx_43xx.h" +#include "pmc_18xx_43xx.h" +#include "qei_18xx_43xx.h" +#include "ritimer_18xx_43xx.h" +#include "rtc_18xx_43xx.h" +#include "sct_18xx_43xx.h" +#include "sct_pwm_18xx_43xx.h" +#include "sdmmc_18xx_43xx.h" +#include "sdio_18xx_43xx.h" +#include "spifi_18xx_43xx.h" +#include "ssp_18xx_43xx.h" +#include "timer_18xx_43xx.h" +#include "uart_18xx_43xx.h" +#include "usbhs_18xx_43xx.h" +#include "wwdt_18xx_43xx.h" +#include "romapi_18xx_43xx.h" +#include "i2cm_18xx_43xx.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_LPC18XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc43xx.h new file mode 100644 index 0000000000000..eb79f6fe8729b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/chip_lpc43xx.h @@ -0,0 +1,229 @@ +/* + * @brief LPC43xx basic chip inclusion file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_LPC43XX_H_ +#define __CHIP_LPC43XX_H_ + +#include "lpc_types.h" +#include "sys_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(CORE_M4) && !defined(CORE_M0) +#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture +#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list +#endif + +#ifndef CHIP_LPC43XX +#error The LPC43XX Chip include path is used for this build, but +#error CHIP_LPC43XX is not defined! +#endif + +/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define LPC_SCT_BASE 0x40000000 +#define LPC_GPDMA_BASE 0x40002000 +#define LPC_SPIFI_BASE 0x40003000 +#define LPC_SDMMC_BASE 0x40004000 +#define LPC_EMC_BASE 0x40005000 +#define LPC_USB0_BASE 0x40006000 +#define LPC_USB1_BASE 0x40007000 +#define LPC_LCD_BASE 0x40008000 +#define LPC_FMCA_BASE 0x4000C000 +#define LPC_FMCB_BASE 0x4000D000 +#define LPC_ETHERNET_BASE 0x40010000 +#define LPC_ATIMER_BASE 0x40040000 +#define LPC_REGFILE_BASE 0x40041000 +#define LPC_PMC_BASE 0x40042000 +#define LPC_CREG_BASE 0x40043000 +#define LPC_EVRT_BASE 0x40044000 +#define LPC_OTP_BASE 0x40045000 +#define LPC_RTC_BASE 0x40046000 +#define LPC_CGU_BASE 0x40050000 +#define LPC_CCU1_BASE 0x40051000 +#define LPC_CCU2_BASE 0x40052000 +#define LPC_RGU_BASE 0x40053000 +#define LPC_WWDT_BASE 0x40080000 +#define LPC_USART0_BASE 0x40081000 +#define LPC_USART2_BASE 0x400C1000 +#define LPC_USART3_BASE 0x400C2000 +#define LPC_UART1_BASE 0x40082000 +#define LPC_SSP0_BASE 0x40083000 +#define LPC_SSP1_BASE 0x400C5000 +#define LPC_TIMER0_BASE 0x40084000 +#define LPC_TIMER1_BASE 0x40085000 +#define LPC_TIMER2_BASE 0x400C3000 +#define LPC_TIMER3_BASE 0x400C4000 +#define LPC_SCU_BASE 0x40086000 +#define LPC_PIN_INT_BASE 0x40087000 +#define LPC_GPIO_GROUP_INT0_BASE 0x40088000 +#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 +#define LPC_MCPWM_BASE 0x400A0000 +#define LPC_I2C0_BASE 0x400A1000 +#define LPC_I2C1_BASE 0x400E0000 +#define LPC_I2S0_BASE 0x400A2000 +#define LPC_I2S1_BASE 0x400A3000 +#define LPC_C_CAN1_BASE 0x400A4000 +#define LPC_RITIMER_BASE 0x400C0000 +#define LPC_QEI_BASE 0x400C6000 +#define LPC_GIMA_BASE 0x400C7000 +#define LPC_DAC_BASE 0x400E1000 +#define LPC_C_CAN0_BASE 0x400E2000 +#define LPC_ADC0_BASE 0x400E3000 +#define LPC_ADC1_BASE 0x400E4000 +#define LPC_ADCHS_BASE 0x400F0000 +#define LPC_GPIO_PORT_BASE 0x400F4000 +#define LPC_SPI_BASE 0x40100000 +#define LPC_SGPIO_BASE 0x40101000 +#define LPC_EEPROM_BASE 0x4000E000 +#define LPC_ROM_API_BASE 0x10400100 + +#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE) +#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE) +#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE) +#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE) +#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE) +#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE) +#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE) +#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE) +#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE) +#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE) +#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE) +#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE) +#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE) +#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE) +#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE) +#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE) +#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE) +#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE) +#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE) +#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE) +#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE) +#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE) +#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE) +#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE) +#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE) +#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE) +#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE) +#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE) +#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE) +#define LPC_GPIO_PIN_INT ((LPC_PIN_INT_T *) LPC_PIN_INT_BASE) +#define LPC_GPIOGROUP ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE) +#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE) +#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE) +#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE) +#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE) +#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE) +#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE) +#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE) +#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE) +#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE) +#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE) +#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE) +#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE) +#define LPC_ADCHS ((LPC_HSADC_T *) LPC_ADCHS_BASE) +#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE) +#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE) +#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE) +#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE) +#define LPC_FMCA ((LPC_FMC_T *) LPC_FMCA_BASE) +#define LPC_FMCB ((LPC_FMC_T *) LPC_FMCB_BASE) +#define LPC_ROM_API ((LPC_ROM_API_T *) LPC_ROM_API_BASE) + +/** + * @} + */ + +#include "scu_18xx_43xx.h" +#include "clock_18xx_43xx.h" +#include "rgu_18xx_43xx.h" +#include "creg_18xx_43xx.h" +#include "evrt_18xx_43xx.h" +#include "otp_18xx_43xx.h" +#include "sdif_18xx_43xx.h" +#include "adc_18xx_43xx.h" +#include "hsadc_18xx_43xx.h" +#include "atimer_18xx_43xx.h" +#include "aes_18xx_43xx.h" +#include "ccan_18xx_43xx.h" +#include "dac_18xx_43xx.h" +#include "eeprom_18xx_43xx.h" +#include "emc_18xx_43xx.h" +#include "enet_18xx_43xx.h" +#include "fmc_18xx_43xx.h" +#include "i2c_18xx_43xx.h" +#include "i2s_18xx_43xx.h" +#include "gima_18xx_43xx.h" +#include "gpdma_18xx_43xx.h" +#include "gpio_18xx_43xx.h" +#include "pinint_18xx_43xx.h" +#include "gpiogroup_18xx_43xx.h" +#include "lcd_18xx_43xx.h" +#include "mcpwm_18xx_43xx.h" +#include "pmc_18xx_43xx.h" +#include "qei_18xx_43xx.h" +#include "ritimer_18xx_43xx.h" +#include "rtc_18xx_43xx.h" +#include "sct_18xx_43xx.h" +#include "sct_pwm_18xx_43xx.h" +#include "sdmmc_18xx_43xx.h" +#include "sdio_18xx_43xx.h" +#include "sgpio_18xx_43xx.h" +#include "spifi_18xx_43xx.h" +#include "spi_18xx_43xx.h" +#include "ssp_18xx_43xx.h" +#include "timer_18xx_43xx.h" +#include "uart_18xx_43xx.h" +#include "usbhs_18xx_43xx.h" +#include "wwdt_18xx_43xx.h" +#include "romapi_18xx_43xx.h" +#include "i2cm_18xx_43xx.h" + +#if defined(CORE_M4) +#include "fpu_init.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_LPC43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/clock_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/clock_18xx_43xx.h new file mode 100644 index 0000000000000..6f0c5a7cc33ce --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/clock_18xx_43xx.h @@ -0,0 +1,400 @@ +/* + * @brief LPC18xx/43xx clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CLOCK_18XX_43XX_H_ +#define __CLOCK_18XX_43XX_H_ + +#include "cguccu_18xx_43xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options + * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS + * The clock driver has options that configure it's operation at build-time.
+ * + * MAX_CLOCK_FREQ
+ * This macro defines the maximum frequency supported by the Chip [204MHz for LPC43xx + * 180MHz for LPC18xx]. API Chip_SetupXtalClocking() and Chip_SetupIrcClocking() will + * use this macro to set the CPU Core frequency to the maximum supported.
+ * To set a Core frequency other than the maximum frequency Chip_SetupCoreClock() API + * must be used. Using this macro to set the Core freqency is not recommended. + * @{ + */ + +/** + * @} + */ + +/* Internal oscillator frequency */ +#define CGU_IRC_FREQ (12000000) + +#ifndef MAX_CLOCK_FREQ +#if defined(CHIP_LPC43XX) +#define MAX_CLOCK_FREQ (204000000) +#else +#define MAX_CLOCK_FREQ (180000000) +#endif +#endif + +#define PLL_MIN_CCO_FREQ 156000000 /**< Min CCO frequency of main PLL */ +#define PLL_MAX_CCO_FREQ 320000000 /**< Max CCO frequency of main PLL */ + +/** + * @brief PLL Parameter strucutre + */ +typedef struct { + int ctrl; /**< Control register value */ + CHIP_CGU_CLKIN_T srcin; /**< Input clock Source see #CHIP_CGU_CLKIN_T */ + int nsel; /**< Pre-Div value */ + int psel; /**< Post-Div Value */ + int msel; /**< M-Div value */ + uint32_t fin; /**< Input frequency */ + uint32_t fout; /**< Output frequency */ + uint32_t fcco; /**< CCO frequency */ +} PLL_PARAM_T; + +/** + * @brief Enables the crystal oscillator + * @return Nothing + */ +void Chip_Clock_EnableCrystal(void); + +/** + * @brief Disables the crystal oscillator + * @return Nothing + */ +void Chip_Clock_DisableCrystal(void); + +/** + * @brief Configures the main PLL + * @param Input : Which clock input to use as the PLL input + * @param MinHz : Minimum allowable PLL output frequency + * @param DesiredHz : Desired PLL output frequency + * @param MaxHz : Maximum allowable PLL output frequency + * @return Frequency of the PLL in Hz + * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz + * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if + * the PLL is locked. + */ +uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz); + +/** + * @brief Directly set the PLL multipler + * @param Input : Which clock input to use as the PLL input + * @param mult : How many times to multiply the input clock + * @return Frequency of the PLL in Hz + */ +uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult); + +/** + * @brief Returns the frequency of the main PLL + * @return Frequency of the PLL in Hz + * Returns zero if the main PLL is not running. + */ +uint32_t Chip_Clock_GetMainPLLHz(void); + +/** + * @brief Disables the main PLL + * @return none + * Make sure the main PLL is not needed to clock the part before disabling it. + * Saves power if the main PLL is not needed. + */ +__STATIC_INLINE void Chip_Clock_DisableMainPLL(void) +{ + /* power down main PLL */ + LPC_CGU->PLL1_CTRL |= 1; +} + +/** + * @brief Enbles the main PLL + * @return none + * Make sure the main PLL is enabled. + */ +__STATIC_INLINE void Chip_Clock_EnableMainPLL(void) +{ + /* power up main PLL */ + LPC_CGU->PLL1_CTRL &= ~1; +} +/** + * @brief Sets-up the main PLL + * @param ppll : Pointer to pll param structure #PLL_PARAM_T + * @return none + * Make sure the main PLL is enabled. + */ +__STATIC_INLINE void Chip_Clock_SetupMainPLL(const PLL_PARAM_T *ppll) +{ + /* power up main PLL */ + LPC_CGU->PLL1_CTRL = ppll->ctrl | ((uint32_t) ppll->srcin << 24) | (ppll->msel << 16) | (ppll->nsel << 12) | (ppll->psel << 8) | ( 1 << 11); +} + +/** + * @brief Sets up a CGU clock divider and it's input clock + * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to configure + * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider + * @param Divisor : value to divide Input clock by + * @return Nothing + * Maximum divider on A = 4, B/C/D = 16, E = 256. + * See the user manual for allowable combinations for input clock. + */ +void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor); + +/** + * @brief Gets a CGU clock divider source + * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of + * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD + */ +CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider); + +/** + * @brief Gets a CGU clock divider divisor + * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of + * @return the divider value for the divider + */ +uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider); + +/** + * @brief Returns the frequency of the specified input clock source + * @param input : Which clock input to return the frequency of + * @return Frequency of input source in Hz + * This function returns an ideal frequency and not the actual frequency. Returns + * zero if the clock source is disabled. + */ +uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input); + +/** + * @brief Returns the frequency of the specified base clock source + * @param clock : which base clock to return the frequency of. + * @return Frequency of base source in Hz + * This function returns an ideal frequency and not the actual frequency. Returns + * zero if the clock source is disabled. + */ +uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock); + +/** + * @brief Sets a CGU Base Clock clock source + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to set + * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock + * @param autoblocken : Enables autoblocking during frequency change if true + * @param powerdn : The clock base is setup, but powered down if true + * @return Nothing + */ +void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn); + +/** + * @brief Get CGU Base Clock clock source information + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get + * @param Input : Pointer to CHIP_CGU_CLKIN_T value of the base clock + * @param autoblocken : Pointer to autoblocking value of the base clock + * @param powerdn : Pointer to power down flag + * @return Nothing + */ +void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken, + bool *powerdn); + +/** + * @brief Gets a CGU Base Clock clock source + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for + * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD + */ +CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock); + +/** + * @brief Enables a base clock source + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to enable + * @return Nothing + */ +void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock); + +/** + * @brief Disables a base clock source + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to disable + * @return Nothing + */ +void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock); + +/** + * @brief Returns base clock enable state + * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to check + * @return true if the base clock is enabled, false if disabled + */ +bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock); + +/** + * @brief Enables a peripheral clock and sets clock states + * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable + * @param autoen : true to enable autoblocking on a clock rate change, false to disable + * @param wakeupen : true to enable wakeup mechanism, false to disable + * @param div : Divider for the clock, must be 1 for most clocks, 2 supported on others + * @return Nothing + */ +void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div); + +/** + * @brief Enables a peripheral clock + * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable + * @return Nothing + */ +void Chip_Clock_Enable(CHIP_CCU_CLK_T clk); + +/** + * @brief Enables RTCclock + * @return Nothing + */ +void Chip_Clock_RTCEnable(void); + +/** + * @brief Disables a peripheral clock + * @param clk : CHIP_CCU_CLK_T value indicating which clock to disable + * @return Nothing + */ +void Chip_Clock_Disable(CHIP_CCU_CLK_T clk); + +/** + * @brief Returns a peripheral clock rate + * @param clk : CHIP_CCU_CLK_T value indicating which clock to get rate for + * @return 0 if the clock is disabled, or the rate of the clock + */ +uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk); + +/** + * @brief Returns EMC clock rate + * @return 0 if the clock is disabled, or the rate of the clock + */ +uint32_t Chip_Clock_GetEMCRate(void); + +/** + * @brief Start the power down sequence by disabling the branch output + * clocks with wake up mechanism (Only the clocks which + * wake up mechanism bit enabled will be disabled) + * @return Nothing + */ +void Chip_Clock_StartPowerDown(void); + +/** + * @brief Clear the power down mode bit & proceed normal operation of branch output + * clocks (Only the clocks which wake up mechanism bit enabled will be + * enabled after the wake up event) + * @return Nothing + */ +void Chip_Clock_ClearPowerDown(void); + +/** + * Structure for setting up the USB or audio PLL + */ +typedef struct { + uint32_t ctrl; /* Default control word for PLL */ + uint32_t mdiv; /* Default M-divider value for PLL */ + uint32_t ndiv; /* Default NP-divider value for PLL */ + uint32_t fract; /* Default fractional value for audio PLL only */ + uint32_t freq; /* Output frequency of the pll */ +} CGU_USBAUDIO_PLL_SETUP_T; + +/** + * @brief Sets up the audio or USB PLL + * @param Input : Input clock + * @param pllnum : PLL identifier + * @param pPLLSetup : Pointer to PLL setup structure + * @return Nothing + * Sets up the PLL with the passed structure values. + */ +void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum, + const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup); + +/** + * @brief Enables the audio or USB PLL + * @param pllnum : PLL identifier + * @return Nothing + */ +void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum); + +/** + * @brief Disables the audio or USB PLL + * @param pllnum : PLL identifier + * @return Nothing + */ +void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum); + +#define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */ +#define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */ + +/** + * @brief Returns the PLL status + * @param pllnum : PLL identifier + * @return An OR'ed value of CGU_PLL_LOCKED or CGU_PLL_FR + */ +uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum); + +/** + * @brief Calculate main PLL Pre, Post and M div values + * @param freq : Expected output frequency + * @param ppll : Pointer to #PLL_PARAM_T structure + * @return 0 on success; < 0 on failure + * @note + * ppll->srcin[IN] should have the appropriate Input clock source selected
+ * ppll->fout[OUT] will have the actual output frequency
+ * ppll->fcco[OUT] will have the frequency of CCO + */ +int Chip_Clock_CalcMainPLLValue(uint32_t freq, PLL_PARAM_T *ppll); + + +/** + * @brief Wait for Main PLL to be locked + * @return 1 - PLL is LOCKED; 0 - PLL is not locked + * @note The main PLL should be locked prior to using it as a clock input for a base clock. + */ +__STATIC_INLINE int Chip_Clock_MainPLLLocked(void) +{ + /* Return true if locked */ + return (LPC_CGU->PLL1_STAT & 1) != 0; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLOCK_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cmsis.h b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis.h new file mode 100644 index 0000000000000..5fb24b3be257b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis.h @@ -0,0 +1,69 @@ +/* + * @brief LPC11xx selective CMSIS inclusion file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_H_ +#define __CMSIS_H_ + +#include "lpc_types.h" +#include "sys_config.h" + +/* Select correct CMSIS include file based on CHIP_* definition */ +#if defined(CHIP_LPC43XX) + +#ifdef CORE_M4 +#include "cmsis_43xx.h" + +#elif defined(CORE_M0) +#if defined(LPC43XX_CORE_M0APP) +#include "cmsis_43xx_m0app.h" + +#elif (defined(LPC43XX_CORE_M0SUB)) +#include "cmsis_43xx_m0sub.h" + +#else +#error "LPC43XX_CORE_M0APP or LPC43XX_CORE_M0SUB must be defined" +#endif + +#else +#error "CORE_M0 or CORE_M4 must be defined for CHIP_LPC43XX" +#endif + +#elif defined(CHIP_LPC18XX) +#include "cmsis_18xx.h" + +#else +#error "No CHIP_* definition is defined" +#endif + +#endif /* __CMSIS_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_18xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_18xx.h new file mode 100644 index 0000000000000..616edf0699fd5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_18xx.h @@ -0,0 +1,172 @@ +/* + * @brief Basic CMSIS include file for LPC18XX + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_18XX_H_ +#define __CMSIS_18XX_H_ + +#ifndef __CMSIS_H_ +#error "cmsis_18xx.h should not be included directly use cmsis.h instead" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_18XX CHIP: LPC18xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif +/** @defgroup CMSIS_18XX_COMMON CHIP: LPC18xx Cortex CMSIS definitions + * @{ + */ + +#define __CM3_REV 0x0201 +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + RESERVED0_IRQn = 1, + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + RESERVED3_IRQn = 20, + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + RESERVED5_IRQn = 31, + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + RESERVED7_IRQn = 45,/*!< */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + RESERVED9_IRQn = 50, + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} LPC18XX_IRQn_Type; + +/** + * @} + */ + +typedef LPC18XX_IRQn_Type IRQn_Type; + +/* Cortex-M3 processor and core peripherals */ +#include "core_cm3.h" + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CMSIS_18XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx.h new file mode 100644 index 0000000000000..e2d6550f60adf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx.h @@ -0,0 +1,173 @@ +/* + * @brief Basic CMSIS include file for LPC43XX + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_43XX_M0_H_ +#define __CMSIS_43XX_M0_H_ + +#ifndef __CMSIS_H_ +#error "cmsis_43xx.h should not be included directly use cmsis.h instead" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_43XX CHIP: LPC43xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/** @defgroup CMSIS_43XX_COMMON CHIP: LPC43xx Cortex CMSIS definitions + * @{ + */ + +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */ + PendSV_IRQn = -2,/*!< 14 Pendable request for system service */ + SysTick_IRQn = -1,/*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + M0APP_IRQn = 1,/*!< 1 M0APP Core interrupt */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + SPI_INT_IRQn = 20,/*!< 20 SPI_INT */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */ + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + ADCHS_IRQn = 45,/*!< 45 ADCHS interrupt */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + M0SUB_IRQn = 50,/*!< 50 M0SUB core interrupt */ + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} LPC43XX_IRQn_Type; + +/** + * @} + */ + +typedef LPC43XX_IRQn_Type IRQn_Type; + +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CMSIS_43XX_M0_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0app.h b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0app.h new file mode 100644 index 0000000000000..42c1d034365f4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0app.h @@ -0,0 +1,156 @@ +/* + * @brief Basic CMSIS include file for LPC43XX + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_43XX_H_ +#define __CMSIS_43XX_H_ + +#ifndef __CMSIS_H_ +#error "cmsis_43xx.h should not be included directly use cmsis.h instead" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/** @defgroup CMSIS_43XX_M0_COMMON CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions + * @{ + */ + +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + RTC_IRQn = 0,/*!< 0 RTC */ + M4_IRQn = 1,/*!< 1 M4 Core interrupt */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 */ + FLASHEEPROM_IRQn = 4,/*!< 4 ORed Flash Bank A, B, EEPROM */ + ATIMER_IRQn = 4,/*!< 4 ATIMER ORed with Flash/EEPROM */ + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 ORed RITIMER, WWDT */ + WWDT_IRQn = 11,/*!< 11 ORed RITIMER, WWDT */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + GINT1_IRQn = 13,/*!< 13 GINT1 */ + PIN_INT4_IRQn = 14,/*!< 14 GPIO 4 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 ORed I2C0, I2C1 */ + I2C1_IRQn = 18,/*!< 18 ORed I2C0, I2C1 */ + SGPIO_INT_IRQn = 19,/*!< 19 SGPIO */ + SPI_INT_IRQn = 20,/*!< 20 ORed SPI/DAC */ + DAC_IRQn = 20,/*!< 20 ORed SPI/DAC */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */ + SSP1_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */ + EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 ORed USART2/C_CAN1 */ + C_CAN1_IRQn = 26,/*!< 29 ORed USART2/C_CAN1 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 ORed I2S0/I2S1/QEI */ + I2S1_IRQn = 28,/*!< 29 ORed I2S0/I2S1/QEI */ + QEI_IRQn = 28,/*!< 29 ORed I2S0/I2S1/QEI */ + C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */ + ADCHS_IRQn = 30,/*!< 30 ADCHS interrupt */ + M0SUB_IRQn = 31,/*!< 31 M0SUB */ +} LPC43XX_M0_IRQn_Type; + +/** + * @} + */ + +typedef LPC43XX_M0_IRQn_Type IRQn_Type; + +/* Cortex-M4 processor and core peripherals */ +#include "core_cm0.h" + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CMSIS_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h new file mode 100644 index 0000000000000..80d0986a3aa5e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h @@ -0,0 +1,151 @@ +/* + * @brief Basic CMSIS include file for LPC43XX + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_43XX_H_ +#define __CMSIS_43XX_H_ + +#ifndef __CMSIS_H_ +#error "cmsis_43xx.h should not be included directly use cmsis.h instead" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/** @defgroup CMSIS_43XX_M0_COMMON CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions + * @{ + */ + +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + M4_IRQn = 1,/*!< 1 M0a */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 */ + SGPIO_INPUT_IRQn = 4,/*!< 4 SGPIO Input bit match */ + SGPIO_MATCH_IRQn = 5,/*!< 5 SGPIO Pattern Match */ + SGPIO_SHIFT_IRQn = 6,/*!< 6 SGPIO Shift Clock */ + SGPIO_POS_IRQn = 7,/*!< 7 SGPIO Capture Clock */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + GINT1_IRQn = 12,/*!< 12 GINT1 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + PIN_INT5_IRQn = 15,/*!< 15 GPIO Pin interrupt 5 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + SPI_INT_IRQn = 20,/*!< 20 SPI_INT */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */ + SSP1_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */ + EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 ORed USART2/C_CAN1 */ + C_CAN1_IRQn = 26,/*!< 26 ORed USART2/C_CAN1 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */ + I2S1_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */ + C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */ + ADCHS_IRQn = 30,/*!< 30 ADCHS interrupt */ + M0APP_IRQn = 31,/*!< 31 M0SUB */ +} LPC43XX_M0_IRQn_Type; + +/** + * @} + */ + +typedef LPC43XX_M0_IRQn_Type IRQn_Type; + +/* Cortex-M4 processor and core peripherals */ +#include "core_cm0.h" + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CMSIS_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h new file mode 100644 index 0000000000000..e2d6550f60adf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h @@ -0,0 +1,173 @@ +/* + * @brief Basic CMSIS include file for LPC43XX + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_43XX_M0_H_ +#define __CMSIS_43XX_M0_H_ + +#ifndef __CMSIS_H_ +#error "cmsis_43xx.h should not be included directly use cmsis.h instead" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_43XX CHIP: LPC43xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/** @defgroup CMSIS_43XX_COMMON CHIP: LPC43xx Cortex CMSIS definitions + * @{ + */ + +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */ + PendSV_IRQn = -2,/*!< 14 Pendable request for system service */ + SysTick_IRQn = -1,/*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + M0APP_IRQn = 1,/*!< 1 M0APP Core interrupt */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + SPI_INT_IRQn = 20,/*!< 20 SPI_INT */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */ + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + ADCHS_IRQn = 45,/*!< 45 ADCHS interrupt */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + M0SUB_IRQn = 50,/*!< 50 M0SUB core interrupt */ + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} LPC43XX_IRQn_Type; + +/** + * @} + */ + +typedef LPC43XX_IRQn_Type IRQn_Type; + +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CMSIS_43XX_M0_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/sys_config.h b/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/sys_config.h new file mode 100644 index 0000000000000..6e048760b1445 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/config_43xx/sys_config.h @@ -0,0 +1,36 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +/* LPC43xx chip family */ +#define CHIP_LPC43XX + +#endif /* __SYS_CONFIG_H_ */ diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0.h new file mode 100644 index 0000000000000..efb9eba2ddcd6 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0plus.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0plus.h new file mode 100644 index 0000000000000..7d8858857fa30 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm0plus.h @@ -0,0 +1,799 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h new file mode 100644 index 0000000000000..195e3c75ccbbd --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h @@ -0,0 +1,1633 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h new file mode 100644 index 0000000000000..2a6e37807bc17 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h @@ -0,0 +1,1778 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4_simd.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4_simd.h new file mode 100644 index 0000000000000..d5a0e0c142687 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4_simd.h @@ -0,0 +1,679 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cmFunc.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cmFunc.h new file mode 100644 index 0000000000000..a824f793dba63 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cmFunc.h @@ -0,0 +1,642 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cmInstr.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cmInstr.h new file mode 100644 index 0000000000000..2705838d23aed --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cmInstr.h @@ -0,0 +1,694 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_sc000.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_sc000.h new file mode 100644 index 0000000000000..badeccd606747 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_sc000.h @@ -0,0 +1,819 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_sc300.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_sc300.h new file mode 100644 index 0000000000000..50720256680d2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_sc300.h @@ -0,0 +1,1604 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/creg_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/creg_18xx_43xx.h new file mode 100644 index 0000000000000..4bef32ec88db2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/creg_18xx_43xx.h @@ -0,0 +1,244 @@ +/* + * @brief LPC18XX/43XX CREG control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CREG_18XX_43XX_H_ +#define __CREG_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief CREG Register Block + */ +typedef struct { /*!< CREG Structure */ + __I uint32_t RESERVED0; + __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */ + __I uint32_t RESERVED1[62]; + __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED2[5]; +#else + __I uint32_t RESERVED2; + __I uint32_t CREG1; /*!< Configuration Register 1 */ + __I uint32_t CREG2; /*!< Configuration Register 2 */ + __I uint32_t CREG3; /*!< Configuration Register 3 */ + __I uint32_t CREG4; /*!< Configuration Register 4 */ +#endif + __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */ + __IO uint32_t DMAMUX; /*!< DMA muxing control */ + __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */ + __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */ + __IO uint32_t ETBCFG; /*!< ETB RAM configuration */ + __IO uint32_t CREG6; /*!< Chip configuration register 6. */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED4[52]; +#else + __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */ + __I uint32_t RESERVED4[51]; +#endif + __I uint32_t CHIPID; /*!< Part ID */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED5[191]; +#else + __I uint32_t RESERVED5[65]; + __IO uint32_t M0SUBMEMMAP; /*!< M0SUB IPC Event memory mapping */ + __I uint32_t RESERVED6[2]; + __IO uint32_t M0SUBTXEVENT; /*!< M0SUB IPC Event register */ + __I uint32_t RESERVED7[58]; + __IO uint32_t M0APPTXEVENT; /*!< M0APP IPC Event register */ + __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0APP memory mapping */ + __I uint32_t RESERVED8[62]; +#endif + __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */ + __I uint32_t RESERVED9[63]; + __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */ +} LPC_CREG_T; + +/** + * @brief Identifies whether on-chip flash is present + * @return true if on chip flash is available, otherwise false + */ +STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void) +{ + return LPC_CREG->CHIPID != 0x3284E02B; +} + +/** + * @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts. + * @param Hz : Current frequency in Hz of the CPU + * @return Nothing + * This function should be called with the higher frequency before the clock frequency is + * increased and it should be called with the new lower value after the clock frequency is + * decreased. + */ +STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz) +{ + uint32_t FAValue = Hz / 21510000; + + LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12); + LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12); +} + +/** + * @brief FLASH Access time definitions + */ +typedef enum { + FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock */ + FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock */ + FLASHTIM_60MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock */ + FLASHTIM_80MHZ_CPU = 3, /*!< Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock */ + FLASHTIM_100MHZ_CPU = 4, /*!< Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock */ + FLASHTIM_120MHZ_CPU = 5, /*!< Flash accesses use 6 CPU clocks. Use for up to 120 MHz CPU clock */ + FLASHTIM_150MHZ_CPU = 6, /*!< Flash accesses use 7 CPU clocks. Use for up to 150 Mhz CPU clock */ + FLASHTIM_170MHZ_CPU = 7, /*!< Flash accesses use 8 CPU clocks. Use for up to 170 MHz CPU clock */ + FLASHTIM_190MHZ_CPU = 8, /*!< Flash accesses use 9 CPU clocks. Use for up to 190 MHz CPU clock */ + FLASHTIM_SAFE_SETTING = 9, /*!< Flash accesses use 10 CPU clocks. Safe setting for any allowed conditions */ +} CREG_FLASHTIM_T; + +/** + * @brief Set FLASH memory access time in clocks + * @param clks : FLASH access speed rating + * @return Nothing + */ +STATIC INLINE void Chip_CREG_SetFLASHAccess(CREG_FLASHTIM_T clks) +{ + uint32_t tmpA, tmpB; + + /* Don't alter lower bits */ + tmpA = LPC_CREG->FLASHCFGA & ~(0xF << 12); + LPC_CREG->FLASHCFGA = tmpA | ((uint32_t) clks << 12); + tmpB = LPC_CREG->FLASHCFGB & ~(0xF << 12); + LPC_CREG->FLASHCFGB = tmpB | ((uint32_t) clks << 12); +} + +/** + * @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts + * @return Nothing + * @note The USB0 PLL & clock should be configured before calling this function. This function + * should be called before the USB0 registers are accessed. + */ +STATIC INLINE void Chip_CREG_EnableUSB0Phy(void) +{ + LPC_CREG->CREG0 &= ~(1 << 5); +} + +/** + * @brief Disable the USB0 high-speed PHY on LPC18xx/LPC43xx parts + * @return Nothing + * @note The USB0 PLL & clock should be configured before calling this function. This function + * should be called before the USB0 registers are accessed. + */ +STATIC INLINE void Chip_CREG_DisableUSB0Phy(void) +{ + LPC_CREG->CREG0 |= (1 << 5); +} + +/** + * @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts. + * @param BODVL : Brown-Out Detect voltage level (0-3) + * @param BORVL : Brown-Out Reset voltage level (0-3) + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL) +{ + LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10); +} + +#if (defined(CHIP_LPC43XX) && defined(LPC_CREG)) +/** + * @brief Configures base address of image to be run in the Cortex M0APP Core. + * @param memaddr : Address of the image (must be aligned to 4K) + * @return Nothing + */ +STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr) +{ + LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF; +} + +/** + * @brief Configures base address of image to be run in the Cortex M0SUB Core. + * @param memaddr : Address of the image (must be aligned to 4K) + * @return Nothing + */ +STATIC INLINE void Chip_CREG_SetM0SubMemMap(uint32_t memaddr) +{ + LPC_CREG->M0SUBMEMMAP = memaddr & ~0xFFF; +} + +/** + * @brief Clear M4 IPC Event + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ClearM4Event(void) +{ + LPC_CREG->M4TXEVENT = 0; +} + +/** + * @brief Clear M0APP IPC Event + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ClearM0AppEvent(void) +{ + LPC_CREG->M0APPTXEVENT = 0; +} + +/** + * @brief Clear M0APP IPC Event + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ClearM0SubEvent(void) +{ + LPC_CREG->M0SUBTXEVENT = 0; +} +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CREG_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/dac_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/dac_18xx_43xx.h new file mode 100644 index 0000000000000..55b9d26286d16 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/dac_18xx_43xx.h @@ -0,0 +1,172 @@ +/* + * @brief LPC18xx/43xx D/A conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __DAC_18XX_43XX_H_ +#define __DAC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup DAC_18XX_43XX CHIP: LPC18xx/43xx D/A conversion driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief DAC register block structure + */ +typedef struct { /*!< DAC Structure */ + __IO uint32_t CR; /*!< DAC register. Holds the conversion data. */ + __IO uint32_t CTRL; /*!< DAC control register. */ + __IO uint32_t CNTVAL; /*!< DAC counter value register. */ +} LPC_DAC_T; + +/** After the selected settling time after this field is written with a + new VALUE, the voltage on the AOUT pin (with respect to VSSA) + is VALUE/1024 ? VREF */ +#define DAC_VALUE(n) ((uint32_t) ((n & 0x3FF) << 6)) +/** If this bit = 0: The settling time of the DAC is 1 microsecond max, + * and the maximum current is 700 microAmpere + * If this bit = 1: The settling time of the DAC is 2.5 microsecond + * and the maximum current is 350 microAmpere + */ +#define DAC_BIAS_EN ((uint32_t) (1 << 16)) +/** Value to reload interrupt DMA counter */ +#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff)) + +/** DCAR double buffering */ +#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1)) +/** DCAR Time out count enable */ +#define DAC_CNT_ENA ((uint32_t) (1 << 2)) +/** DCAR DMA access */ +#define DAC_DMA_ENA ((uint32_t) (1 << 3)) +/** DCAR DACCTRL mask bit */ +#define DAC_DACCTRL_MASK ((uint32_t) (0x0F)) + +/** + * @brief Current option in DAC configuration option + */ +typedef enum IP_DAC_CURRENT_OPT { + DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption; + allows for a maximum update rate of 1 MHz */ + DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption; + allows for a maximum update rate of 400 kHz */ +} DAC_CURRENT_OPT_T; + +/** + * @brief Initial DAC configuration + * - Maximum current is 700 uA + * - Value to AOUT is 0 + * @param pDAC : pointer to LPC_DAC_T + * @return Nothing + */ +void Chip_DAC_Init(LPC_DAC_T *pDAC); + +/** + * @brief Shutdown DAC + * @param pDAC : pointer to LPC_DAC_T + * @return Nothing + */ +void Chip_DAC_DeInit(LPC_DAC_T *pDAC); + +/** + * @brief Update value to DAC buffer + * @param pDAC : pointer to LPC_DAC_T + * @param dac_value : value 10 bit to be converted to output + * @return Nothing + */ +void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value); + +/** + * @brief Set maximum update rate for DAC + * @param pDAC : pointer to LPC_DAC_T + * @param bias : Using Bias value, should be: + * - 0 is 1MHz + * - 1 is 400kHz + * @return Nothing + */ +void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias); + +/** + * @brief Enables the DMA operation and controls DMA timer + * @param pDAC : pointer to LPC_DAC_T + * @param dacFlags : An Or'ed value of the following DAC values: + * - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature + * - DAC_CNT_ENA :enable/disable timer out counter + * - DAC_DMA_ENA :enable/disable DMA access + * @return Nothing + * @note Pass an Or'ed value of the DAC flags to enable those options. + */ +STATIC INLINE void Chip_DAC_ConfigDAConverterControl(LPC_DAC_T *pDAC, uint32_t dacFlags) +{ + uint32_t temp; + + temp = pDAC->CTRL & ~DAC_DACCTRL_MASK; + pDAC->CTRL = temp | dacFlags; +} + +/** + * @brief Set reload value for interrupt/DMA counter + * @param pDAC : pointer to LPC_DAC_T + * @param time_out : time out to reload for interrupt/DMA counter + * @return Nothing + */ +STATIC INLINE void Chip_DAC_SetDMATimeOut(LPC_DAC_T *pDAC, uint32_t time_out) +{ + pDAC->CNTVAL = DAC_CCNT_VALUE(time_out); +} + +/** + * @brief Get status for interrupt/DMA time out + * @param pDAC : pointer to LPC_DAC_T + * @return interrupt/DMA time out status, should be SET or RESET + */ +STATIC INLINE IntStatus Chip_DAC_GetIntStatus(LPC_DAC_T *pDAC) +{ + return (pDAC->CTRL & 0x01) ? SET : RESET; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/eeprom.h b/ports/lpc/chips/lpc_chip_43xx/inc/eeprom.h new file mode 100644 index 0000000000000..6bcf8e349522a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/eeprom.h @@ -0,0 +1,76 @@ +/* + * @brief Common EEPROM support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EEPROM_H_ +#define __EEPROM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup COMMON_EEPROM CHIP: Common Chip EEPROM commands + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Write data to EEPROM + * @param dstAdd : EEPROM address to be written to + * @param ptr : Pointer to buffer to write from + * @param byteswrt : Number of bytes to write to EEPROM + * @return An IAP response definition from iap.h + */ +uint8_t Chip_EEPROM_Write(uint32_t dstAdd, uint8_t *ptr, uint32_t byteswrt); + +/** + * @brief Read data from EEPROM + * @param srcAdd : EEPROM address to be read from + * @param ptr : Pointer to buffer to read to + * @param bytesrd : Number of bytes to read from EEPROM + * @return An IAP response definition from iap.h + */ +uint8_t Chip_EEPROM_Read(uint32_t srcAdd, uint8_t *ptr, uint32_t bytesrd); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EEPROM_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/eeprom_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/eeprom_18xx_43xx.h new file mode 100644 index 0000000000000..c1903ed4a03ab --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/eeprom_18xx_43xx.h @@ -0,0 +1,281 @@ +/* + * @brief LPC18xx/43xx EEPROM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef _EEPROM_18XX_43XX_H_ +#define _EEPROM_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EEPROM_18XX_43XX CHIP: LPC18xx/43xx EEPROM driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/* FIX ME: Move to chip.h */ +/** EEPROM start address */ +#define EEPROM_START (0x20040000) +/** EEPROM byes per page */ +#define EEPROM_PAGE_SIZE (128) +/**The number of EEPROM pages. The last page is not writable.*/ +#define EEPROM_PAGE_NUM (128) +/** Get the eeprom address */ +#define EEPROM_ADDRESS(page, offset) (EEPROM_START + (EEPROM_PAGE_SIZE * (page)) + offset) +#define EEPROM_CLOCK_DIV 1500000 +#define EEPROM_READ_WAIT_STATE_VAL 0x58 +#define EEPROM_WAIT_STATE_VAL 0x232 + +/** + * @brief EEPROM register block structure + */ +typedef struct { /* EEPROM Structure */ + __IO uint32_t CMD; /*!< EEPROM command register */ + uint32_t RESERVED0; + __IO uint32_t RWSTATE; /*!< EEPROM read wait state register */ + __IO uint32_t AUTOPROG; /*!< EEPROM auto programming register */ + __IO uint32_t WSTATE; /*!< EEPROM wait state register */ + __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */ + __IO uint32_t PWRDWN; /*!< EEPROM power-down register */ + uint32_t RESERVED2[1007]; + __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */ + __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */ + __I uint32_t INTSTAT; /*!< EEPROM interrupt status */ + __I uint32_t INTEN; /*!< EEPROM interrupt enable */ + __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */ + __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */ +} LPC_EEPROM_T; + +/* + * @brief Macro defines for EEPROM command register + */ +#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */ + +/* + * @brief Macro defines for EEPROM Auto Programming register + */ +#define EEPROM_AUTOPROG_OFF (0) /*!PWRDWN = EEPROM_PWRDWN; +} + +/** + * @brief Bring EEPROM device out of power down mode + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_DisablePowerDown(LPC_EEPROM_T *pEEPROM) +{ + pEEPROM->PWRDWN = 0; +} + +/** + * @brief Initializes EEPROM + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return Nothing + */ +void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM); + +/** + * @brief De-initializes EEPROM + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_DeInit(LPC_EEPROM_T *pEEPROM) +{ + /* Enable EEPROM power down mode */ + Chip_EEPROM_EnablePowerDown(pEEPROM); +} + +/** + * @brief Set Auto program mode + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mode : Auto Program Mode (One of EEPROM_AUTOPROG_* value) + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_SetAutoProg(LPC_EEPROM_T *pEEPROM, uint32_t mode) +{ + pEEPROM->AUTOPROG = mode; +} + +/** + * @brief Set EEPROM Read Wait State + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param ws : Wait State value + * @return Nothing + * @note Bits 7:0 represents wait state for Read Phase 2 and + * Bits 15:8 represents wait state for Read Phase1 + */ +STATIC INLINE void Chip_EEPROM_SetReadWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws) +{ + pEEPROM->RWSTATE = ws; +} + +/** + * @brief Set EEPROM wait state + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param ws : Wait State value + * @return Nothing + * @note Bits 7:0 represents wait state for Phase 3, + * Bits 15:8 represents wait state for Phase2, and + * Bits 23:16 represents wait state for Phase1 + */ +STATIC INLINE void Chip_EEPROM_SetWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws) +{ + pEEPROM->WSTATE = ws; +} + +/** + * @brief Select an EEPROM command + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param cmd : EEPROM command + * @return Nothing + * @note The cmd is OR-ed bits value of EEPROM_CMD_* + */ +STATIC INLINE void Chip_EEPROM_SetCmd(LPC_EEPROM_T *pEEPROM, uint32_t cmd) +{ + pEEPROM->CMD = cmd; +} + +/** + * @brief Erase/Program an EEPROM page + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return Nothing + */ +void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM); + +/** + * @brief Wait for interrupt occurs + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mask : Expected interrupt + * @return Nothing + */ +void Chip_EEPROM_WaitForIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask); + +/** + * @brief Enable EEPROM interrupt + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*) + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_EnableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask) +{ + pEEPROM->INTENSET = mask; +} + +/** + * @brief Disable EEPROM interrupt + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*) + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_DisableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask) +{ + pEEPROM->INTENCLR = mask; +} + +/** + * @brief Get the value of the EEPROM interrupt enable register + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return OR-ed bits value of EEPROM_INT_* + */ +STATIC INLINE uint32_t Chip_EEPROM_GetIntEnable(LPC_EEPROM_T *pEEPROM) +{ + return pEEPROM->INTEN; +} + +/** + * @brief Get EEPROM interrupt status + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @return OR-ed bits value of EEPROM_INT_* + */ +STATIC INLINE uint32_t Chip_EEPROM_GetIntStatus(LPC_EEPROM_T *pEEPROM) +{ + return pEEPROM->INTSTAT; +} + +/** + * @brief Set EEPROM interrupt status + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*) + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_SetIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask) +{ + pEEPROM->INTSTATSET = mask; +} + +/** + * @brief Clear EEPROM interrupt status + * @param pEEPROM : Pointer to EEPROM peripheral block structure + * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*) + * @return Nothing + */ +STATIC INLINE void Chip_EEPROM_ClearIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask) +{ + pEEPROM->INTSTATCLR = mask; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _EEPROM_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/emc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/emc_18xx_43xx.h new file mode 100644 index 0000000000000..1e34b547db869 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/emc_18xx_43xx.h @@ -0,0 +1,360 @@ +/* + * @brief LPC18xx/43xx EMC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EMC_18XX_43XX_H_ +#define __EMC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx External Memory Controller driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + * The EMC interface clocks must be enabled outside this driver prior to + * calling any function of this driver. + */ + +/** + * @brief External Memory Controller (EMC) register block structure + */ +typedef struct { /*!< EMC Structure */ + __IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */ + __I uint32_t STATUS; /*!< Provides EMC status information. */ + __IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */ + __I uint32_t RESERVED0[5]; + __IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */ + __IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */ + __IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */ + __I uint32_t RESERVED1; + __IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */ + __IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */ + __IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */ + __IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */ + __IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */ + __IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */ + __IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */ + __IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */ + __IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */ + __IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */ + __IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */ + __I uint32_t RESERVED2[9]; + __IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */ + __I uint32_t RESERVED3[31]; + __IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED4[6]; + __IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED5[6]; + __IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED6[6]; + __IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED7[38]; + __IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED8; + __IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED9; + __IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED10; + __IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */ +} LPC_EMC_T; + +/** + * Dynamic Chip Select Address + */ +#define EMC_ADDRESS_DYCS0 (0x28000000) +#define EMC_ADDRESS_DYCS1 (0x30000000) +#define EMC_ADDRESS_DYCS2 (0x60000000) +#define EMC_ADDRESS_DYCS3 (0x70000000) + +/** + * Static Chip Select Address + */ +#define EMC_ADDRESS_CS0 (0x1C000000) +#define EMC_ADDRESS_CS1 (0x1D000000) +#define EMC_ADDRESS_CS2 (0x1E000000) +#define EMC_ADDRESS_CS3 (0x1F000000) + +/** + * @brief EMC register support bitfields and mask + */ +/* Reserve for extending support to ARM9 or nextgen LPC */ +#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */ + +#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */ +#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */ + +#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */ +#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */ + +/* Dynamic Memory Configuration Register Bit Definitions */ +#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */ + +/*!< Memory configuration values in EMC Dynamic Configuration Register */ +#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */ +#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */ +#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */ +#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */ +#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */ +#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */ +#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */ +#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */ +#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */ +#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */ +#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */ +#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */ +#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */ + +/*!< Dynamic Memory Mode Register Bit Definition */ +#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */ + +#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */ + +/*!< CAS Latency in Dynamic Mode Register */ +#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */ +#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */ +#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */ +#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */ + +/*!< Operation Mode in Dynamic Mode register */ +#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */ +#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */ + +/*!< Write Burst Mode in Dynamic Mode register */ +#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */ +#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */ +#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */ + +/*!< Dynamic Memory Control Register Bit Definitions */ +#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */ + +/*!< Static Memory Configuration Register Bit Definitions */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */ + +#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */ +#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */ + +#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */ +#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */ +#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */ + +#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */ +#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */ +#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */ + +#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */ +#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */ +#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */ + +/*!< Q24.8 Fixed Point Helper */ +#define Q24_8_FP(x) ((x) * 256) +#define EMC_NANOSECOND(x) Q24_8_FP(x) +#define EMC_CLOCK(x) Q24_8_FP(-(x)) + +/** + * @brief EMC Dynamic Device Configuration structure used for IP drivers + */ +typedef struct { + uint32_t BaseAddr; /*!< Base Address */ + uint8_t RAS; /*!< RAS value */ + uint32_t ModeRegister; /*!< Mode Register value */ + uint32_t DynConfig; /*!< Dynamic Configuration value */ +} IP_EMC_DYN_DEVICE_CONFIG_T; + +/** + * @brief EMC Dynamic Configure Struct + */ +typedef struct { + int32_t RefreshPeriod; /*!< Refresh period */ + uint32_t ReadConfig; /*!< Clock*/ + int32_t tRP; /*!< Precharge Command Period */ + int32_t tRAS; /*!< Active to Precharge Command Period */ + int32_t tSREX; /*!< Self Refresh Exit Time */ + int32_t tAPR; /*!< Last Data Out to Active Time */ + int32_t tDAL; /*!< Data In to Active Command Time */ + int32_t tWR; /*!< Write Recovery Time */ + int32_t tRC; /*!< Active to Active Command Period */ + int32_t tRFC; /*!< Auto-refresh Period */ + int32_t tXSR; /*!< Exit Selt Refresh */ + int32_t tRRD; /*!< Active Bank A to Active Bank B Time */ + int32_t tMRD; /*!< Load Mode register command to Active Command */ + IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4]; /*!< Device Configuration array */ +} IP_EMC_DYN_CONFIG_T; + +/** + * @brief EMC Static Configure Structure + */ +typedef struct { + uint8_t ChipSelect; /*!< Chip select */ + uint32_t Config; /*!< Configuration value */ + int32_t WaitWen; /*!< Write Enable Wait */ + int32_t WaitOen; /*!< Output Enable Wait */ + int32_t WaitRd; /*!< Read Wait */ + int32_t WaitPage; /*!< Page Access Wait */ + int32_t WaitWr; /*!< Write Wait */ + int32_t WaitTurn; /*!< Turn around wait */ +} IP_EMC_STATIC_CONFIG_T; + +/** + * @brief Dyanmic memory setup + * @param Dynamic_Config : Pointer to dynamic memory setup data + * @return None + */ +void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config); + +/** + * @brief Static memory setup + * @param Static_Config : Pointer to static memory setup data + * @return None + */ +void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config); + +/** + * @brief Enable Dynamic Memory Controller + * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable + * @return None + */ +void Chip_EMC_Dynamic_Enable(uint8_t Enable); + +/** + * @brief Mirror CS1 to CS0 and DYCS0 + * @param Enable : 1 = Mirror, 0 = Normal Memory Map + * @return None + */ +void Chip_EMC_Mirror(uint8_t Enable); + +/** + * @brief Enable EMC + * @param Enable : 1 = Enable, 0 = Disable + * @return None + */ +void Chip_EMC_Enable(uint8_t Enable); + +/** + * @brief Set EMC LowPower Mode + * @param Enable : 1 = Enable, 0 = Disable + * @return None + * @note This function should only be called when the memory + * controller is not busy (bit 0 of the status register is not set). + */ +void Chip_EMC_LowPowerMode(uint8_t Enable); + +/** + * @brief Initialize EMC + * @param Enable : 1 = Enable, 0 = Disable + * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2 + * @param EndianMode : Endian Mode, 0 = Little, 1 = Big + * @return None + */ +void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode); + +/** + * @brief Set Static Memory Extended Wait in Clock + * @param Wait16Clks : Number of '16 clock' delay cycles + * @return None + */ +STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks) +{ + LPC_EMC->STATICEXTENDEDWAIT = Wait16Clks; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EMC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/enet_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/enet_18xx_43xx.h new file mode 100644 index 0000000000000..62ac2a191c3a1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/enet_18xx_43xx.h @@ -0,0 +1,686 @@ +/* + * @brief LPC18xx/43xx Ethernet driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ENET_18XX_43XX_H_ +#define __ENET_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief 10/100 MII & RMII Ethernet with timestamping register block structure + */ +typedef struct { /*!< ETHERNET Structure */ + __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */ + __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */ + __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */ + __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */ + __IO uint32_t MAC_MII_ADDR; /*!< MII address register */ + __IO uint32_t MAC_MII_DATA; /*!< MII data register */ + __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */ + __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */ + __I uint32_t RESERVED0; + __I uint32_t MAC_DEBUG; /*!< Debug register */ + __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */ + __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */ + __I uint32_t RESERVED1[2]; + __I uint32_t MAC_INTR; /*!< Interrupt status register */ + __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */ + __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */ + __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */ + __I uint32_t RESERVED2[430]; + __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */ + __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */ + __I uint32_t SECONDS; /*!< System time seconds register */ + __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */ + __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */ + __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */ + __IO uint32_t ADDEND; /*!< Time stamp addend register */ + __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */ + __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */ + __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */ + __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */ + __IO uint32_t PPSCTRL; /*!< PPS control register */ + __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */ + __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */ + __I uint32_t RESERVED3[562]; + __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */ + __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */ + __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */ + __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */ + __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */ + __IO uint32_t DMA_STAT; /*!< Status register */ + __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */ + __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */ + __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */ + __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */ + __I uint32_t RESERVED4[8]; + __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */ + __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */ + __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */ + __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */ +} LPC_ENET_T; + +/* + * @brief MAC_CONFIG register bit defines + */ +#define MAC_CFG_RE (1 << 2) /*!< Receiver enable */ +#define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */ +#define MAC_CFG_DF (1 << 4) /*!< Deferral Check */ +#define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */ +#define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */ +#define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */ +#define MAC_CFG_DR (1 << 9) /*!< Disable Retry */ +#define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */ +#define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */ +#define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */ +#define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */ +#define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */ +#define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */ +#define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */ +#define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */ +#define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */ +#define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */ +#define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */ + +/* + * @brief MAC_FRAME_FILTER register bit defines + */ +#define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */ +#define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */ +#define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */ +#define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */ +#define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */ +#define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */ +#define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */ +#define MAC_FF_RA (1UL << 31) /*!< Receive all */ + +/* + * @brief MAC_MII_ADDR register bit defines + */ +#define MAC_MIIA_GB (1 << 0) /*!< MII busy */ +#define MAC_MIIA_W (1 << 1) /*!< MII write */ +#define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */ +#define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */ +#define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */ + +/* + * @brief MAC_MII_DATA register bit defines + */ +#define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */ + +/** + * @brief MAC_FLOW_CONTROL register bit defines + */ +#define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */ +#define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */ +#define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */ +#define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */ +#define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */ +#define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */ +#define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */ + +/* + * @brief MAC_VLAN_TAG register bit defines + */ +#define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */ +#define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */ + +/* + * @brief MAC_PMT_CTRL_STAT register bit defines + */ +#define MAC_PMT_PD (1 << 0) /*!< Power-down */ +#define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */ +#define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */ +#define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */ +#define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */ +#define MAC_PMT_GU (1 << 9) /*!< Global Unicast */ +#define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */ + +/* + * @brief MAC_INTR_MASK register bit defines + */ +#define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */ + +/* + * @brief MAC_ADDR0_HIGH register bit defines + */ +#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */ + +/* + * @brief MAC_ADDR0_HIGH register bit defines + */ +#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */ + +/* + * @brief MAC_TIMESTAMP register bit defines + */ +#define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */ +#define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */ +#define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */ +#define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */ +#define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */ +#define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */ +#define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */ +#define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */ +#define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */ +#define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */ +#define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */ +#define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */ +#define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */ +#define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */ +#define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */ +#define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */ + +/* + * @brief DMA_BUS_MODE register bit defines + */ +#define DMA_BM_SWR (1 << 0) /*!< Software reset */ +#define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */ +#define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */ +#define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */ +#define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */ +#define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */ +#define DMA_BM_FB (1 << 16) /*!< Fixed burst */ +#define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */ +#define DMA_BM_USP (1 << 23) /*!< Use separate PBL */ +#define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */ +#define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */ +#define DMA_BM_MB (1 << 26) /*!< Mixed burst */ +#define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */ + +/* + * @brief DMA_STAT register bit defines + */ +#define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */ +#define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */ +#define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */ +#define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */ +#define DMA_ST_OVF (1 << 4) /*!< Receive overflow */ +#define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */ +#define DMA_ST_RI (1 << 6) /*!< Receive interrupt */ +#define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */ +#define DMA_ST_RPS (1 << 8) /*!< Received process stopped */ +#define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */ +#define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */ +#define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */ +#define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */ +#define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */ +#define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */ +#define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */ + +/* + * @brief DMA_OP_MODE register bit defines + */ +#define DMA_OM_SR (1 << 1) /*!< Start/stop receive */ +#define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */ +#define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */ +#define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */ +#define DMA_OM_FEF (1 << 7) /*!< Forward error frames */ +#define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */ +#define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */ +#define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */ +#define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */ +#define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */ +#define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */ +#define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */ + +/* + * @brief DMA_INT_EN register bit defines + */ +#define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */ +#define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */ +#define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */ +#define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */ +#define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */ +#define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */ +#define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */ +#define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */ +#define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */ +#define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */ +#define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */ +#define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */ +#define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */ +#define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */ +#define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */ + +/* + * @brief DMA_MFRM_BUFOF register bit defines + */ +#define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */ +#define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */ +#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */ +#define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */ + +/* + * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines + */ +#define TDES_DB (1 << 0) /*!< Deferred Bit */ +#define TDES_UF (1 << 1) /*!< Underflow Error */ +#define TDES_ED (1 << 2) /*!< Excessive Deferral */ +#define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */ +#define TDES_VF (1 << 7) /*!< VLAN Frame */ +#define TDES_EC (1 << 8) /*!< Excessive Collision */ +#define TDES_LC (1 << 9) /*!< Late Collision */ +#define TDES_NC (1 << 10) /*!< No Carrier */ +#define TDES_LCAR (1 << 11) /*!< Loss of Carrier */ +#define TDES_IPE (1 << 12) /*!< IP Payload Error */ +#define TDES_FF (1 << 13) /*!< Frame Flushed */ +#define TDES_JT (1 << 14) /*!< Jabber Timeout */ +#define TDES_ES (1 << 15) /*!< Error Summary */ +#define TDES_IHE (1 << 16) /*!< IP Header Error */ +#define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */ +#define TDES_OWN (1UL << 31) /*!< Own Bit */ + +/* + * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines + */ +#define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */ +#define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */ +#define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */ +#define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */ +#define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */ +#define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */ +#define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */ +#define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */ +#define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */ + +/* + * @brief TRAN_DESC_T only BSIZE field bit defines + */ +#define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */ +#define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */ +#define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */ +#define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */ +#define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */ +#define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */ +#define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */ +#define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */ +#define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */ +#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */ +#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */ + +/* + * @brief TRAN_DESC_ENH_T only BSIZE field bit defines + */ +#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */ +#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */ + +/* + * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines + */ +#define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */ +#define RDES_CE (1 << 1) /*!< CRC Error */ +#define RDES_DRE (1 << 2) /*!< Dribble Bit Error */ +#define RDES_RE (1 << 3) /*!< Receive Error */ +#define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */ +#define RDES_FT (1 << 5) /*!< Frame Type */ +#define RDES_LC (1 << 6) /*!< Late Collision */ +#define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */ +#define RDES_LS (1 << 8) /*!< Last Descriptor */ +#define RDES_FS (1 << 9) /*!< First Descriptor */ +#define RDES_VLAN (1 << 10) /*!< VLAN Tag */ +#define RDES_OE (1 << 11) /*!< Overflow Error */ +#define RDES_LE (1 << 12) /*!< Length Error */ +#define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */ +#define RDES_DE (1 << 14) /*!< Descriptor Error */ +#define RDES_ES (1 << 15) /*!< ES: Error Summary */ +#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */ +#define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */ +#define RDES_OWN (1UL << 31) /*!< Own Bit */ + +/* + * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines + */ +#define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */ + +/* + * @brief REC_DESC_T pnly CTRL field bit defines + */ +#define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */ +#define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */ +#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */ +#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */ + +/** + * @brief REC_DESC_ENH_T only CTRL field bit defines + */ +#define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */ +#define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */ +#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */ +#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */ + +/* + * @brief REC_DESC_ENH_T only EXTSTAT field bit defines + */ +#define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */ +#define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */ +#define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */ +#define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */ +#define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */ +#define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */ +#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */ + +/* + * @brief Maximum size of an ethernet buffer + */ +#define EMAC_ETH_MAX_FLEN (1536) + +/** + * @brief Structure of a transmit descriptor (without timestamp) + */ +typedef struct { + __IO uint32_t CTRLSTAT; /*!< TDES control and status word */ + __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ +} ENET_TXDESC_T; + +/** + * @brief Structure of a enhanced transmit descriptor (with timestamp) + */ +typedef struct { + __IO uint32_t CTRLSTAT; /*!< TDES control and status word */ + __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ + __IO uint32_t TDES4; /*!< Reserved */ + __IO uint32_t TDES5; /*!< Reserved */ + __IO uint32_t TTSL; /*!< Timestamp value low */ + __IO uint32_t TTSH; /*!< Timestamp value high */ +} ENET_ENHTXDESC_T; + +/** + * @brief Structure of a receive descriptor (without timestamp) + */ +typedef struct { + __IO uint32_t STATUS; /*!< RDES status word */ + __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ +} ENET_RXDESC_T; + +/** + * @brief Structure of a enhanced receive descriptor (with timestamp) + */ +typedef struct { + __IO uint32_t STATUS; /*!< RDES status word */ + __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ + __IO uint32_t EXTSTAT; /*!< Extended Status */ + __IO uint32_t RDES5; /*!< Reserved */ + __IO uint32_t RTSL; /*!< Timestamp value low */ + __IO uint32_t RTSH; /*!< Timestamp value high */ +} ENET_ENHRXDESC_T; + +/** + * @brief Resets the ethernet interface + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + * @note Resets the ethernet interface. This should be called prior to + * Chip_ENET_Init with a small delay after this call. + */ +STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET) +{ + /* This should be called prior to IP_ENET_Init. The MAC controller may + not be ready for a call to init right away so a small delay should + occur after this call. */ + pENET->DMA_BUS_MODE |= DMA_BM_SWR; +} + +/** + * @brief Sets the address of the interface + * @param pENET : The base of ENET peripheral on the chip + * @param macAddr : Pointer to the 6 bytes used for the MAC address + * @return Nothing + */ +STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr) +{ + /* Save MAC address */ + pENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) | + ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) | + ((uint32_t) macAddr[0]); + pENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) | + ((uint32_t) macAddr[4]); +} + +/** + * @brief Sets up the PHY link clock divider and PHY address + * @param pENET : The base of ENET peripheral on the chip + * @param div : Divider index, not a divider value, see user manual + * @param addr : PHY address, used with MII read and write + * @return Nothing + */ +void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr); + +/** + * @brief Starts a PHY write via the MII + * @param pENET : The base of ENET peripheral on the chip + * @param reg : PHY register to write + * @param data : Data to write to PHY register + * @return Nothing + * @note Start a PHY write operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when write is complete. + */ +void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data); + +/** + * @brief Starts a PHY read via the MII + * @param pENET : The base of ENET peripheral on the chip + * @param reg : PHY register to read + * @return Nothing + * @note Start a PHY read operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when read is complete and calling + * IP_ENET_ReadMIIData to get the data. + */ +void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg); + +/** + * @brief Returns MII link (PHY) busy status + * @param pENET : The base of ENET peripheral on the chip + * @return Returns true if busy, otherwise false + */ +STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET) +{ + return (pENET->MAC_MII_ADDR & MAC_MIIA_GB) ? true : false; +} + +/** + * @brief Returns the value read from the PHY + * @param pENET : The base of ENET peripheral on the chip + * @return Read value from PHY + */ +STATIC INLINE uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET) +{ + return pENET->MAC_MII_DATA; +} + +/** + * @brief Enables ethernet transmit + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET) +{ + pENET->MAC_CONFIG |= MAC_CFG_TE; + pENET->DMA_OP_MODE |= DMA_OM_ST; +} + +/** + * @brief Disables ethernet transmit + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET) +{ + pENET->MAC_CONFIG &= ~MAC_CFG_TE; +} + +/** + * @brief Enables ethernet packet reception + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET) +{ + pENET->MAC_CONFIG |= MAC_CFG_RE; + pENET->DMA_OP_MODE |= DMA_OM_SR; +} + +/** + * @brief Disables ethernet packet reception + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET) +{ + pENET->MAC_CONFIG &= ~MAC_CFG_RE; +} + +/** + * @brief Enable RMII ethernet operation + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + * @note This function must be called to enable the internal + * RMII PHY, and must be called before calling any Ethernet + * functions. + */ +STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET) +{ + LPC_CREG->CREG6 |= 0x4; +} + +/** + * @brief Enable MII ethernet operation + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + * @note This function must be called to enable the + * MII PHY, and must be called before calling any Ethernet + * functions. + */ +STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET) +{ + LPC_CREG->CREG6 &= ~0x7; +} + +/** + * @brief Sets full or half duplex for the interface + * @param pENET : The base of ENET peripheral on the chip + * @param full : true to selected full duplex, false for half + * @return Nothing + */ +void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full); + +/** + * @brief Sets speed for the interface + * @param pENET : The base of ENET peripheral on the chip + * @param speed100 : true to select 100Mbps mode, false for 10Mbps + * @return Nothing + */ +void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100); + +/** + * @brief Configures the initial ethernet descriptors + * @param pENET : The base of ENET peripheral on the chip + * @param pTXDescs : Pointer to TX descriptor list + * @param pRXDescs : Pointer to RX descriptor list + * @return Nothing + */ +STATIC INLINE void Chip_ENET_InitDescriptors(LPC_ENET_T *pENET, + ENET_ENHTXDESC_T *pTXDescs, ENET_ENHRXDESC_T *pRXDescs) +{ + /* Setup descriptor list base addresses */ + pENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs; + pENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs; +} + +/** + * @brief Starts receive polling of RX descriptors + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_RXStart(LPC_ENET_T *pENET) +{ + /* Start receive polling */ + pENET->DMA_REC_POLL_DEMAND = 1; +} + +/** + * @brief Starts transmit polling of TX descriptors + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ENET_TXStart(LPC_ENET_T *pENET) +{ + /* Start transmit polling */ + pENET->DMA_TRANS_POLL_DEMAND = 1; +} + +/** + * @brief Initialize ethernet interface + * @param pENET : The base of ENET peripheral on the chip + * @param phyAddr : Address of the Phy [valid range 0 to 31] + * @return Nothing + * @note Performs basic initialization of the ethernet interface in a default + * state. This is enough to place the interface in a usable state, but + * may require more setup outside this function. + */ +void Chip_ENET_Init(LPC_ENET_T *pENET, uint32_t phyAddr); + +/** + * @brief De-initialize the ethernet interface + * @param pENET : The base of ENET peripheral on the chip + * @return Nothing + */ +void Chip_ENET_DeInit(LPC_ENET_T *pENET); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ENET_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/error.h b/ports/lpc/chips/lpc_chip_43xx/inc/error.h new file mode 100644 index 0000000000000..83d62ad9ed193 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/error.h @@ -0,0 +1,278 @@ +/* + * @brief Error code returned by Boot ROM drivers/library functions + * + * This file contains unified error codes to be used across driver, + * middleware, applications, hal and demo software. + * + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_ERROR_H__ +#define __LPC_ERROR_H__ + +/** Error code returned by Boot ROM drivers/library functions + * + * Error codes are a 32-bit value with : + * - The 16 MSB contains the peripheral code number + * - The 16 LSB contains an error code number associated to that peripheral + * + */ +typedef enum +{ + /**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */ + /**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */ + /**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */ + /**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */ + + /* ISP related errors */ + ERR_ISP_BASE = 0x00000000, + /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1, + /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */ + /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */ + /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED, + /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED, + /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */ + /*0x00000007*/ ERR_ISP_INVALID_SECTOR, + /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, + /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, + /*0x0000000A*/ ERR_ISP_COMPARE_ERROR, + /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */ + /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */ + /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */ + /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED, + /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */ + /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */ + /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE, + /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT, + /*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED, + /*0x00000014*/ ERR_ISP_INVALID_FLASH_UNIT, + /*0x00000015*/ ERR_ISP_USER_CODE_CHECKSUM, + /*0x00000016*/ ERR_ISP_SETTING_ACTIVE_PARTITION, + /*0x00000017*/ ERR_ISP_IRC_NO_POWER, + /*0x00000018*/ ERR_ISP_FLASH_NO_POWER, + /*0x00000019*/ ERR_ISP_EEPROM_NO_POWER, + /*0x0000001A*/ ERR_ISP_EEPROM_NO_CLOCK, + /*0x0000001B*/ ERR_ISP_FLASH_NO_CLOCK, + /*0x0000001C*/ ERR_ISP_REINVOKE_ISP_CONFIG, + + /* ROM API related errors */ + ERR_API_BASE = 0x00010000, + /**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/ + /**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */ + /**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */ + /**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */ + /**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */ + + /* SPIFI API related errors */ + ERR_SPIFI_BASE = 0x00020000, + /*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1, + /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR, + /*0x00020003*/ ERR_SPIFI_TIMEOUT, + /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR, + /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM, + /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT, + /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID, + /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE, + /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG, + /*0x0002000A*/ ERR_SPIFI_NO_DEVICE, + /*0x0002000B*/ ERR_SPIFI_ERASE_NEEDED, + + SEC_AES_NO_ERROR=0, + /* Security API related errors */ + ERR_SEC_AES_BASE = 0x00030000, + /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_AES_BASE+1, + /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED, + /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED, + /*0x00030004*/ ERR_SEC_AES_DMA_CHANNEL_CFG, + /*0x00030005*/ ERR_SEC_AES_DMA_MUX_CFG, + /*0x00030006*/ SEC_AES_DMA_BUSY, + + /* USB device stack related errors */ + ERR_USBD_BASE = 0x00040000, + /**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */ + /**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */ + /**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */ + /**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */ + /**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */ + /**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/ + /**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/ + /**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/ + /**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/ + /**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */ + /**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */ + + /* CGU related errors */ + ERR_CGU_BASE = 0x00050000, + /*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1, + /*0x00050002*/ ERR_CGU_INVALID_PARAM, + /*0x00050003*/ ERR_CGU_INVALID_SLICE, + /*0x00050004*/ ERR_CGU_OUTPUT_GEN, + /*0x00050005*/ ERR_CGU_DIV_SRC, + /*0x00050006*/ ERR_CGU_DIV_VAL, + /*0x00050007*/ ERR_CGU_SRC, + + /* I2C related errors */ + ERR_I2C_BASE = 0x00060000, + /*0x00060000*/ ERR_I2C_BUSY = ERR_I2C_BASE, + /*0x00060001*/ ERR_I2C_NAK, + /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, + /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, + /*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, + /*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, + /*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, + /*0x00060007*/ ERR_I2C_GENERAL_FAILURE, + /*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT, + /*0x00060009*/ ERR_I2C_TIMEOUT, + /*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW, + /*0x0006000B*/ ERR_I2C_PARAM, + + /* OTP related errors */ + ERR_OTP_BASE = 0x00070000, + /*0x00070001*/ ERR_OTP_WR_ENABLE_INVALID = ERR_OTP_BASE+1, + /*0x00070002*/ ERR_OTP_SOME_BITS_ALREADY_PROGRAMMED, + /*0x00070003*/ ERR_OTP_ALL_DATA_OR_MASK_ZERO, + /*0x00070004*/ ERR_OTP_WRITE_ACCESS_LOCKED, + /*0x00070005*/ ERR_OTP_READ_DATA_MISMATCH, + /*0x00070006*/ ERR_OTP_USB_ID_ENABLED, + /*0x00070007*/ ERR_OTP_ETH_MAC_ENABLED, + /*0x00070008*/ ERR_OTP_AES_KEYS_ENABLED, + /*0x00070009*/ ERR_OTP_ILLEGAL_BANK, + + /* UART related errors */ + ERR_UART_BASE = 0x00080000, + /*0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE+1, //UART rxd is busy + /*0x00080002*/ ERR_UART_TXD_BUSY, //UART txd is busy + /*0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, //overrun err, frame err, parity err, RxNoise err + /*0x00080004*/ ERR_UART_UNDERRUN, //underrun err + /*0x00080005*/ ERR_UART_PARAM, //parameter is error + /*0x00080006*/ ERR_UART_BAUDRATE, //baudrate setting is error + + /* CAN related errors */ + ERR_CAN_BASE = 0x00090000, + /*0x00090001*/ ERR_CAN_BAD_MEM_BUF = ERR_CAN_BASE+1, + /*0x00090002*/ ERR_CAN_INIT_FAIL, + /*0x00090003*/ ERR_CANOPEN_INIT_FAIL, + + /* SPIFI Lite API related errors */ + ERR_SPIFI_LITE_BASE = 0x000A0000, + /*0x000A0001*/ ERR_SPIFI_LITE_INVALID_ARGUMENTS = ERR_SPIFI_LITE_BASE+1, + /*0x000A0002*/ ERR_SPIFI_LITE_BUSY, + /*0x000A0003*/ ERR_SPIFI_LITE_MEMORY_MODE_ON, + /*0x000A0004*/ ERR_SPIFI_LITE_MEMORY_MODE_OFF, + /*0x000A0005*/ ERR_SPIFI_LITE_IN_DMA, + /*0x000A0006*/ ERR_SPIFI_LITE_NOT_IN_DMA, + /*0x000A0100*/ PENDING_SPIFI_LITE, + + /* CLK related errors */ + ERR_CLK_BASE = 0x000B0000, + /*0x000B0001*/ ERR_CLK_NOT_IMPL=ERR_CLK_BASE+1, + /*0x000B0002*/ ERR_CLK_INVALID_PARAM, + /*0x000B0003*/ ERR_CLK_INVALID_SLICE, + /*0x000B0004*/ ERR_CLK_OUTPUT_GEN, + /*0x000B0005*/ ERR_CLK_DIV_SRC, + /*0x000B0006*/ ERR_CLK_DIV_VAL, + /*0x000B0007*/ ERR_CLK_SRC, + /*0x000B0008*/ ERR_CLK_PLL_FIN_TOO_SMALL, + /*0x000B0009*/ ERR_CLK_PLL_FIN_TOO_LARGE, + /*0x000B000A*/ ERR_CLK_PLL_FOUT_TOO_SMALL, + /*0x000B000B*/ ERR_CLK_PLL_FOUT_TOO_LARGE, + /*0x000B000C*/ ERR_CLK_PLL_NO_SOLUTION, + /*0x000B000D*/ ERR_CLK_PLL_MIN_PCT, + /*0x000B000E*/ ERR_CLK_PLL_MAX_PCT, + /*0x000B000F*/ ERR_CLK_OSC_FREQ, + /*0x000B0010*/ ERR_CLK_CFG, + /*0x000B0011*/ ERR_CLK_TIMEOUT, + /*0x000B0012*/ ERR_CLK_BASE_OFF, + /*0x000B0013*/ ERR_CLK_OFF_DEADLOCK, + + /*Power API*/ + ERR_PWR_BASE = 0x000C0000, + /*0x000C0001*/ PWR_ERROR_ILLEGAL_MODE=ERR_PWR_BASE+1, + /*0x000C0002*/ PWR_ERROR_CLOCK_FREQ_TOO_HIGH, + /*0x000C0003*/ PWR_ERROR_INVALID_STATE, + /*0x000C0004*/ PWR_ERROR_INVALID_CFG, + /*0x000C0005*/ PWR_ERROR_PVT_DETECT, + + /* DMA related errors */ + ERR_DMA_BASE = 0x000D0000, + /*0x000D0001*/ ERR_DMA_ERROR_INT=ERR_DMA_BASE+1, + /*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER, + /*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED, + /*0x000D0004*/ ERR_DMA_BUSY, + /*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT, + /*0x000D0006*/ ERR_DMA_PING_PONG_EN, + /*0x000D0007*/ ERR_DMA_CHANNEL_VALID_PENDING, + /*0x000D0008*/ ERR_DMA_PARAM, + /*0x000D0009*/ ERR_DMA_QUEUE_EMPTY, + /*0x000D000A*/ ERR_DMA_GENERAL, + + /* SPI related errors */ + ERR_SPI_BASE = 0x000E0000, + /*0x000E0000*/ ERR_SPI_BUSY=ERR_SPI_BASE, + /*0x000E0001*/ ERR_SPI_RXOVERRUN, + /*0x000E0002*/ ERR_SPI_TXUNDERRUN, + /*0x000E0003*/ ERR_SPI_SELNASSERT, + /*0x000E0004*/ ERR_SPI_SELNDEASSERT, + /*0x000E0005*/ ERR_SPI_CLKSTALL, + /*0x000E0006*/ ERR_SPI_PARAM, + /*0x000E0007*/ ERR_SPI_INVALID_LENGTH, + + /* ADC related errors */ + ERR_ADC_BASE = 0x000F0000, + /*0x000F0001*/ ERR_ADC_OVERRUN=ERR_ADC_BASE+1, + /*0x000F0002*/ ERR_ADC_INVALID_CHANNEL, + /*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE, + /*0x000F0004*/ ERR_ADC_INVALID_SETUP, + /*0x000F0005*/ ERR_ADC_PARAM, + /*0x000F0006*/ ERR_ADC_INVALID_LENGTH, + /*0x000F0007*/ ERR_ADC_NO_POWER, + + /* Debugger Mailbox related errors */ + ERR_DM_BASE = 0x00100000, + /*0x00100001*/ ERR_DM_NOT_ENTERED=ERR_DM_BASE+1, + /*0x00100002*/ ERR_DM_UNKNOWN_CMD, + /*0x00100003*/ ERR_DM_COMM_FAIL + +} ErrorCode_t; + +#ifndef offsetof +#define offsetof(s, m) (int) &(((s *) 0)->m) +#endif + +#define COMPILE_TIME_ASSERT(pred) switch (0) { \ + case 0: \ + case pred:; } + +#endif /* __LPC_ERROR_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/evrt_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/evrt_18xx_43xx.h new file mode 100644 index 0000000000000..186485163ede9 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/evrt_18xx_43xx.h @@ -0,0 +1,179 @@ +/* + * @brief LPC18xx/43xx event router driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EVRT_18XX_43XX_H_ +#define __EVRT_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Event Router register structure + */ +typedef struct { /*!< EVENTROUTER Structure */ + __IO uint32_t HILO; /*!< Level configuration register */ + __IO uint32_t EDGE; /*!< Edge configuration */ + __I uint32_t RESERVED0[1012]; + __O uint32_t CLR_EN; /*!< Event clear enable register */ + __O uint32_t SET_EN; /*!< Event set enable register */ + __I uint32_t STATUS; /*!< Status register */ + __I uint32_t ENABLE; /*!< Enable register */ + __O uint32_t CLR_STAT; /*!< Clear register */ + __O uint32_t SET_STAT; /*!< Set register */ +} LPC_EVRT_T; + +/** + * @brief EVRT input sources + */ +typedef enum CHIP_EVRT_SRC { + EVRT_SRC_WAKEUP0, /*!< WAKEUP0 event router source */ + EVRT_SRC_WAKEUP1, /*!< WAKEUP1 event router source */ + EVRT_SRC_WAKEUP2, /*!< WAKEUP2 event router source */ + EVRT_SRC_WAKEUP3, /*!< WAKEUP3 event router source */ + EVRT_SRC_ATIMER, /*!< Alarm timer event router source */ + EVRT_SRC_RTC, /*!< RTC event router source */ + EVRT_SRC_BOD1, /*!< BOD event router source */ + EVRT_SRC_WWDT, /*!< WWDT event router source */ + EVRT_SRC_ETHERNET, /*!< Ethernet event router source */ + EVRT_SRC_USB0, /*!< USB0 event router source */ + EVRT_SRC_USB1, /*!< USB1 event router source */ + EVRT_SRC_SDIO, /*!< Reserved */ + EVRT_SRC_CCAN, /*!< C_CAN event router source */ + EVRT_SRC_COMBINE_TIMER2, /*!< Combined timer 2 event router source */ + EVRT_SRC_COMBINE_TIMER6, /*!< Combined timer 6 event router source */ + EVRT_SRC_QEI, /*!< QEI event router source */ + EVRT_SRC_COMBINE_TIMER14, /*!< Combined timer 14 event router source */ + EVRT_SRC_RESERVED1, /*!< Reserved */ + EVRT_SRC_RESERVED2, /*!< Reserved */ + EVRT_SRC_RESET, /*!< Reset event router source */ + EVRT_SRC_BOD_RESET, /*!< Reset event router source */ + EVRT_SRC_DEEP_POWER_DOWN /*!< Reset event router source */ +} CHIP_EVRT_SRC_T; + +/** + * @brief Macro for checking for a valid EVRT source + */ +#define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \ + || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \ + || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \ + || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \ + || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \ + || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \ + || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \ + || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \ + || (n == EVRT_SRC_RESET) || (n == EVRT_SRC_BOD_RESET) || (n == EVRT_SRC_DEEP_POWER_DOWN)) \ + +/** + * @brief EVRT input state detecting type + */ +typedef enum CHIP_EVRT_SRC_ACTIVE { + EVRT_SRC_ACTIVE_LOW_LEVEL, /*!< Active low level */ + EVRT_SRC_ACTIVE_HIGH_LEVEL, /*!< Active high level */ + EVRT_SRC_ACTIVE_FALLING_EDGE, /*!< Active falling edge */ + EVRT_SRC_ACTIVE_RISING_EDGE /*!< Active rising edge */ +} CHIP_EVRT_SRC_ACTIVE_T; + +/** + * @brief Macro for checking for a valid EVRT state type + */ +#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \ + || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE)) + +/** + * @brief Initialize the EVRT + * @return Nothing + */ +void Chip_EVRT_Init (void); + +/** + * @brief Set up the type of interrupt type for a source to EVRT + * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type + * @param type : EVRT type, should be one of CHIP_EVRT_SRC_ACTIVE_T type + * @return Nothing + */ +void Chip_EVRT_ConfigIntSrcActiveType(CHIP_EVRT_SRC_T EVRT_Src, CHIP_EVRT_SRC_ACTIVE_T type); + +/** + * @brief Check if a source is sending interrupt to EVRT + * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type + * @return true if the interrupt from the source is pending, otherwise false + */ +IntStatus Chip_EVRT_IsSourceInterrupting(CHIP_EVRT_SRC_T EVRT_Src); + +/** + * @brief Enable or disable interrupt sources to EVRT + * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type + * @param state : ENABLE or DISABLE to enable or disable event router source + * @return Nothing + */ +void Chip_EVRT_SetUpIntSrc(CHIP_EVRT_SRC_T EVRT_Src, FunctionalState state); + +/** + * @brief De-initializes the EVRT peripheral + * @return Nothing + */ +STATIC INLINE void Chip_EVRT_DeInit(void) +{ + LPC_EVRT->CLR_EN = 0xFFFF; + LPC_EVRT->CLR_STAT = 0xFFFF; +} + +/** + * @brief Clear pending interrupt EVRT source + * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type + * @return Nothing + */ +STATIC INLINE void Chip_EVRT_ClrPendIntSrc(CHIP_EVRT_SRC_T EVRT_Src) +{ + LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EVRT_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/fmc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/fmc_18xx_43xx.h new file mode 100644 index 0000000000000..2697dce401e7b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/fmc_18xx_43xx.h @@ -0,0 +1,160 @@ +/* + * @brief LPC18xx/43xx FLASH Memory Controller (FMC) driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __FMC_18XX_43XX_H_ +#define __FMC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup FMC_18XX_43XX CHIP: LPC18xx/43xx FLASH Memory Controller driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief FLASH Memory Controller Unit register block structure + */ +typedef struct { /*!< FMC Structure */ + __I uint32_t RESERVED1[8]; + __IO uint32_t FMSSTART; + __IO uint32_t FMSSTOP; + __I uint32_t RESERVED2; + __I uint32_t FMSW[4]; + __I uint32_t RESERVED3[1001]; + __I uint32_t FMSTAT; + __I uint32_t RESERVED5; + __O uint32_t FMSTATCLR; + __I uint32_t RESERVED4[5]; +} LPC_FMC_T; + +/* Flash signature start and busy status bit */ +#define FMC_FLASHSIG_BUSY (1UL << 17) + +/* Flash signature clear status bit */ +#define FMC_FLASHSIG_STAT (1 << 2) + +/** + * @brief Gets the base address of given bank + * @param 0 - Bank 0; 1 - Bank 1 + * @return Base address corresponding to given bank + */ +__STATIC_INLINE LPC_FMC_T * Chip_FMC_BaseAddr(uint8_t bank) +{ + if (!bank) { + return LPC_FMCA; + } else { + return LPC_FMCB; + } +} + +/** + * @brief Start computation of a signature for a FLASH memory range + * @param bank : FLASH bank, A = 0, B = 1 + * @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary + * @param stop : Ending FLASH address for computation, must be aligned on 16 byte boundary + * @return Nothing + * @note Only bits 20..4 are used for the FLASH signature computation. + * Use the Chip_FMC_IsSignatureBusy() function to determine when the + * signature computation operation is complete and use the + * Chip_FMC_GetSignature() function to get the computed signature. + */ +STATIC INLINE void Chip_FMC_ComputeSignature(uint8_t bank, uint32_t start, uint32_t stop) +{ + LPC_FMC_T *LPC_FMC = Chip_FMC_BaseAddr(bank); + LPC_FMC->FMSSTART = (start >> 4); + LPC_FMC->FMSTATCLR = FMC_FLASHSIG_STAT; + LPC_FMC->FMSSTOP = (stop >> 4) | FMC_FLASHSIG_BUSY; +} + +/** + * @brief Start computation of a signature for a FLASH memory address and block count + * @param bank : FLASH bank, A = 0, B = 1 + * @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary + * @param blocks : Number of 16 byte blocks used for computation + * @return Nothing + * @note Only bits 20..4 are used for the FLASH signature computation. + * Use the Chip_FMC_IsSignatureBusy() function to determine when the + * signature computation operation is complete and the + * Chip_FMC_GetSignature() function to get the computed signature. + */ +STATIC INLINE void Chip_FMC_ComputeSignatureBlocks(uint8_t bank, uint32_t start, uint32_t blocks) +{ + Chip_FMC_ComputeSignature(bank, start, (start + (blocks * 16))); +} + +/** + * @brief Clear signature generation completion flag + * @param bank : FLASH bank, A = 0, B = 1 + * @return Nothing + */ +STATIC INLINE void Chip_FMC_ClearSignatureBusy(uint8_t bank) +{ + Chip_FMC_BaseAddr(bank)->FMSTATCLR = FMC_FLASHSIG_STAT; +} + +/** + * @brief Check for signature generation completion + * @param bank : FLASH bank, A = 0, B = 1 + * @return true if the signature computation is running, false if finished + */ +STATIC INLINE bool Chip_FMC_IsSignatureBusy(uint8_t bank) +{ + return (bool) ((Chip_FMC_BaseAddr(bank)->FMSTAT & FMC_FLASHSIG_STAT) == 0); +} + +/** + * @brief Returns the generated FLASH signature value + * @param bank : FLASH bank, A = 0, B = 1 + * @param index : Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc. + * @return the generated FLASH signature value + */ +STATIC INLINE uint32_t Chip_FMC_GetSignature(uint8_t bank, int index) +{ + return Chip_FMC_BaseAddr(bank)->FMSW[index]; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/fpu_init.h b/ports/lpc/chips/lpc_chip_43xx/inc/fpu_init.h new file mode 100644 index 0000000000000..b6f631c15792a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/fpu_init.h @@ -0,0 +1,58 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __FPU_INIT_H_ +#define __FPU_INIT_H_ + +/** + * @defgroup CHIP_FPU_CMX CHIP: FPU initialization + * @ingroup CHIP_Common + * Cortex FPU initialization + * @{ + */ + +/** + * @brief Early initialization of the FPU + * @return Nothing + */ +void fpuInit(void); + +/** + * @} + */ + +#endif /* __FPU_INIT_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/gima_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/gima_18xx_43xx.h new file mode 100644 index 0000000000000..ed63d9f7f8cfc --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/gima_18xx_43xx.h @@ -0,0 +1,72 @@ +/* + * @brief LPC18xx/43xx GIMA driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GIMA_18XX_43XX_H_ +#define __GIMA_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GIMA_18XX_43XX CHIP: LPC18xx/43xx GIMA driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Global Input Multiplexer Array (GIMA) register block structure + */ +typedef struct { /*!< GIMA Structure */ + __IO uint32_t CAP0_IN[4][4]; /*!< Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */ + __IO uint32_t CTIN_IN[8]; /*!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */ + __IO uint32_t ADCHS_TRIGGER_IN; /*!< ADCHS trigger input multiplexer (GIMA output 24) */ + __IO uint32_t EVENTROUTER_13_IN; /*!< Event router input 13 multiplexer (GIMA output 25) */ + __IO uint32_t EVENTROUTER_14_IN; /*!< Event router input 14 multiplexer (GIMA output 26) */ + __IO uint32_t EVENTROUTER_16_IN; /*!< Event router input 16 multiplexer (GIMA output 27) */ + __IO uint32_t ADCSTART0_IN; /*!< ADC start0 input multiplexer (GIMA output 28) */ + __IO uint32_t ADCSTART1_IN; /*!< ADC start1 input multiplexer (GIMA output 29) */ +} LPC_GIMA_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GIMA_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/gpdma_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/gpdma_18xx_43xx.h new file mode 100644 index 0000000000000..2763847a3bd64 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/gpdma_18xx_43xx.h @@ -0,0 +1,424 @@ +/* + * @brief LPC18xx/43xx General Purpose DMA driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPDMA_18XX_43XX_H_ +#define __GPDMA_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Number of channels on GPDMA + */ +#define GPDMA_NUMBER_CHANNELS 8 + +/** + * @brief GPDMA Channel register block structure + */ +typedef struct { + __IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */ + __IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */ + __IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */ + __IO uint32_t CONTROL; /*!< DMA Channel Control Register */ + __IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */ + __I uint32_t RESERVED1[3]; +} GPDMA_CH_T; + +/** + * @brief GPDMA register block + */ +typedef struct { /*!< GPDMA Structure */ + __I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */ + __I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */ + __O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */ + __I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */ + __O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */ + __I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */ + __I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */ + __IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */ + __IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */ + __IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */ + __IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */ + __IO uint32_t CONFIG; /*!< DMA Configuration Register */ + __IO uint32_t SYNC; /*!< DMA Synchronization Register */ + __I uint32_t RESERVED0[50]; + GPDMA_CH_T CH[GPDMA_NUMBER_CHANNELS]; +} LPC_GPDMA_T; + +/** + * @brief Macro defines for DMA channel control registers + */ +#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /*!< Transfer size*/ +#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /*!< Source burst size*/ +#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /*!< Destination burst size*/ +#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /*!< Source transfer width*/ +#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /*!< Destination transfer width*/ +#define GPDMA_DMACCxControl_SI ((1UL << 26)) /*!< Source increment*/ +#define GPDMA_DMACCxControl_DI ((1UL << 27)) /*!< Destination increment*/ +#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) /*!< Source AHB master select in 18xx43xx*/ +#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) /*!< Destination AHB master select in 18xx43xx*/ +#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /*!< Indicates that the access is in user mode or privileged mode*/ +#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /*!< Indicates that the access is bufferable or not bufferable*/ +#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /*!< Indicates that the access is cacheable or not cacheable*/ +#define GPDMA_DMACCxControl_I ((1UL << 31)) /*!< Terminal count interrupt enable bit */ + +/** + * @brief Macro defines for DMA Configuration register + */ +#define GPDMA_DMACConfig_E ((0x01)) /*!< DMA Controller enable*/ +#define GPDMA_DMACConfig_M ((0x02)) /*!< AHB Master endianness configuration*/ +#define GPDMA_DMACConfig_BITMASK ((0x03)) + +/** + * @brief Macro defines for DMA Channel Configuration registers + */ +#define GPDMA_DMACCxConfig_E ((1UL << 0)) /*!< DMA control enable*/ +#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /*!< Source peripheral*/ +#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /*!< Destination peripheral*/ +#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /*!< This value indicates the type of transfer*/ +#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /*!< Interrupt error mask*/ +#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /*!< Terminal count interrupt mask*/ +#define GPDMA_DMACCxConfig_L ((1UL << 16)) /*!< Lock*/ +#define GPDMA_DMACCxConfig_A ((1UL << 17)) /*!< Active*/ +#define GPDMA_DMACCxConfig_H ((1UL << 18)) /*!< Halt*/ + +/** + * @brief GPDMA Interrupt Clear Status + */ +typedef enum { + GPDMA_STATCLR_INTTC, /*!< GPDMA Interrupt Terminal Count Request Clear */ + GPDMA_STATCLR_INTERR /*!< GPDMA Interrupt Error Clear */ +} GPDMA_STATECLEAR_T; + +/** + * @brief GPDMA Type of Interrupt Status + */ +typedef enum { + GPDMA_STAT_INT, /*!< GPDMA Interrupt Status */ + GPDMA_STAT_INTTC, /*!< GPDMA Interrupt Terminal Count Request Status */ + GPDMA_STAT_INTERR, /*!< GPDMA Interrupt Error Status */ + GPDMA_STAT_RAWINTTC, /*!< GPDMA Raw Interrupt Terminal Count Status */ + GPDMA_STAT_RAWINTERR, /*!< GPDMA Raw Error Interrupt Status */ + GPDMA_STAT_ENABLED_CH /*!< GPDMA Enabled Channel Status */ +} GPDMA_STATUS_T; + +/** + * @brief GPDMA Type of DMA controller + */ +typedef enum { + GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /*!< Memory to memory - DMA control */ + GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /*!< Memory to peripheral - DMA control */ + GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /*!< Peripheral to memory - DMA control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /*!< Source peripheral to destination peripheral - DMA control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /*!< Source peripheral to destination peripheral - destination peripheral control */ + GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /*!< Memory to peripheral - peripheral control */ + GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /*!< Peripheral to memory - peripheral control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /*!< Source peripheral to destination peripheral - source peripheral control */ +} GPDMA_FLOW_CONTROL_T; + +/** + * @brief GPDMA structure using for DMA configuration + */ +typedef struct { + uint32_t ChannelNum; /*!< DMA channel number, should be in + * range from 0 to 7. + * Note: DMA channel 0 has the highest priority + * and DMA channel 7 the lowest priority. + */ + uint32_t TransferSize; /*!< Length/Size of transfer */ + uint32_t TransferWidth; /*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ + uint32_t SrcAddr; /*!< Physical Source Address, used in case TransferType is chosen as + * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ + uint32_t DstAddr; /*!< Physical Destination Address, used in case TransferType is chosen as + * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ + uint32_t TransferType; /*!< Transfer Type, should be one of the following: + * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control + * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control + * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control + * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control + */ +} GPDMA_CH_CFG_T; + +/** + * @brief GPDMA request connections + */ +#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */ +#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */ +#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */ +#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */ +#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */ +#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */ +#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */ +#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */ +#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */ +#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */ +#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */ +#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */ +#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */ +#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */ +#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */ +#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/ +#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */ +#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */ +#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/ +#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */ +#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S0 Tx on channel 0 */ +#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */ +#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S0 Rx on channel 0 */ +#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */ +#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */ +#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */ +#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */ +#define GPDMA_CONN_DAC ((27UL)) /**< DAC */ +#define GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL)) /**< I2S1 Tx on channel 0 */ +#define GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL)) /**< I2S1 Rx on channel 0 */ + +/** + * @brief GPDMA Burst size in Source and Destination definitions + */ +#define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */ +#define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */ +#define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */ +#define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */ +#define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */ +#define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */ +#define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */ +#define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */ + +/** + * @brief Width in Source transfer width and Destination transfer width definitions + */ +#define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */ +#define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */ +#define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */ + +/** + * @brief Flow control definitions + */ +#define DMA_CONTROLLER 0 /*!< Flow control is DMA controller*/ +#define SRC_PER_CONTROLLER 1 /*!< Flow control is Source peripheral controller*/ +#define DST_PER_CONTROLLER 2 /*!< Flow control is Destination peripheral controller*/ + +/** + * @brief DMA channel handle structure + */ +typedef struct { + FunctionalState ChannelStatus; /*!< DMA channel status */ +} DMA_ChannelHandle_t; + +/** + * @brief Transfer Descriptor structure typedef + */ +typedef struct DMA_TransferDescriptor { + uint32_t src; /*!< Source address */ + uint32_t dst; /*!< Destination address */ + uint32_t lli; /*!< Pointer to next descriptor structure */ + uint32_t ctrl; /*!< Control word that has transfer size, type etc. */ +} DMA_TransferDescriptor_t; + +/** + * @brief Initialize the GPDMA + * @param pGPDMA : The base of GPDMA on the chip + * @return Nothing + */ +void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA); + +/** + * @brief Shutdown the GPDMA + * @param pGPDMA : The base of GPDMA on the chip + * @return Nothing + */ +void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA); + +/** + * @brief Initialize channel configuration strucutre + * @param pGPDMA : The base of GPDMA on the chip + * @param GPDMACfg : Pointer to configuration structure to be initialized + * @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()* + * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY + * PeripheralConnection_ID @endlink, which is the source + * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY + * PeripheralConnection_ID @endlink, which is the destination + * @param Size : The number of DMA transfers + * @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T) + * @return ERROR on error, SUCCESS on success + */ +int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA, + GPDMA_CH_CFG_T *GPDMACfg, + uint8_t ChannelNum, + uint32_t src, + uint32_t dst, + uint32_t Size, + GPDMA_FLOW_CONTROL_T TransferType); + +/** + * @brief Enable or Disable the GPDMA Channel + * @param pGPDMA : The base of GPDMA on the chip + * @param channelNum : The GPDMA channel : 0 - 7 + * @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA + * @return Nothing + */ +void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState); + +/** + * @brief Stop a stream DMA transfer + * @param pGPDMA : The base of GPDMA on the chip + * @param ChannelNum : Channel Number to be closed + * @return Nothing + */ +void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum); + +/** + * @brief The GPDMA stream interrupt status checking + * @param pGPDMA : The base of GPDMA on the chip + * @param ChannelNum : Channel Number to be checked on interruption + * @return Status: + * - SUCCESS : DMA transfer success + * - ERROR : DMA transfer failed + */ +Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum); + +/** + * @brief Read the status from different registers according to the type + * @param pGPDMA : The base of GPDMA on the chip + * @param type : Status mode, should be: + * - GPDMA_STAT_INT : GPDMA Interrupt Status + * - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status + * - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status + * - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status + * - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status + * - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status + * @param channel : The GPDMA channel : 0 - 7 + * @return SET is interrupt is pending or RESET if not pending + */ +IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel); + +/** + * @brief Clear the Interrupt Flag from different registers according to the type + * @param pGPDMA : The base of GPDMA on the chip + * @param type : Flag mode, should be: + * - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request + * - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error + * @param channel : The GPDMA channel : 0 - 7 + * @return Nothing + */ +void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel); + +/** + * @brief Get a free GPDMA channel for one DMA connection + * @param pGPDMA : The base of GPDMA on the chip + * @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx ) + * @return The channel number which is selected + */ +uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA, + uint32_t PeripheralConnection_ID); + +/** + * @brief Do a DMA transfer M2M, M2P,P2M or P2P + * @param pGPDMA : The base of GPDMA on the chip + * @param ChannelNum : Channel used for transfer + * @param src : Address of Memory or PeripheralConnection_ID which is the source + * @param dst : Address of Memory or PeripheralConnection_ID which is the destination + * @param TransferType: Select the transfer controller and the type of transfer. Should be: + * - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL + * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL + * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL + * @param Size : The number of DMA transfers + * @return ERROR on error, SUCCESS on success + */ +Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum, + uint32_t src, + uint32_t dst, + GPDMA_FLOW_CONTROL_T TransferType, + uint32_t Size); + +/** + * @brief Do a DMA transfer using linked list of descriptors + * @param pGPDMA : The base of GPDMA on the chip + * @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()* + * @param DMADescriptor : First node in the linked list of descriptors + * @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T) + * @return ERROR on error, SUCCESS on success + */ +Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum, + const DMA_TransferDescriptor_t *DMADescriptor, + GPDMA_FLOW_CONTROL_T TransferType); + +/** + * @brief Prepare a single DMA descriptor + * @param pGPDMA : The base of GPDMA on the chip + * @param DMADescriptor : DMA Descriptor to be initialized + * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY + * PeripheralConnection_ID @endlink, which is the source + * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY + * PeripheralConnection_ID @endlink, which is the destination + * @param Size : The number of DMA transfers + * @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T) + * @param NextDescriptor : Pointer to next descriptor (0 if no more descriptors available) + * @return ERROR on error, SUCCESS on success + */ +Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA, + DMA_TransferDescriptor_t *DMADescriptor, + uint32_t src, + uint32_t dst, + uint32_t Size, + GPDMA_FLOW_CONTROL_T TransferType, + const DMA_TransferDescriptor_t *NextDescriptor); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPDMA_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/gpio_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/gpio_18xx_43xx.h new file mode 100644 index 0000000000000..09fbd460b2762 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/gpio_18xx_43xx.h @@ -0,0 +1,509 @@ +/* + * @brief LPC18xx/43xx GPIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIO_18XX_43XX_H_ +#define __GPIO_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief GPIO port register block structure + */ +typedef struct { /*!< GPIO_PORT Structure */ + __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */ + __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */ + __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */ + __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */ + __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */ + __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */ + __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */ + __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */ + __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */ +} LPC_GPIO_T; + +/** + * @brief Initialize GPIO block + * @param pGPIO : The base of GPIO peripheral on the chip + * @return Nothing + */ +void Chip_GPIO_Init(LPC_GPIO_T *pGPIO); + +/** + * @brief De-Initialize GPIO block + * @param pGPIO : The base of GPIO peripheral on the chip + * @return Nothing + */ +void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO); + +/** + * @brief Set a GPIO port/bit state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set + * @param setting : true for high, false for low + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting) +{ + pGPIO->B[port][pin] = setting; +} + +/** + * @brief Set a GPIO pin state via the GPIO byte register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to set + * @param setting : true for high, false for low + * @return Nothing + * @note This function replaces Chip_GPIO_WritePortBit() + */ +STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting) +{ + pGPIO->B[port][pin] = setting; +} + +/** + * @brief Read a GPIO state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read + * @param pin : GPIO pin to read + * @return true of the GPIO is high, false if low + * @note It is recommended to use the Chip_GPIO_GetPinState() function instead. + */ +STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin) +{ + return (bool) pGPIO->B[port][pin]; +} + +/** + * @brief Get a GPIO pin state via the GPIO byte register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to get state for + * @return true if the GPIO is high, false if low + * @note This function replaces Chip_GPIO_ReadPortBit() + */ +STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + return (bool) pGPIO->B[port][pin]; +} + +/** + * @brief Set a GPIO direction + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param bit : GPIO bit to set + * @param setting : true for output, false for input + * @return Nothing + * @note It is recommended to use the Chip_GPIO_SetPinDIROutput(), + * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead + * of this function. + */ +STATIC INLINE void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting) +{ + if (setting) { + pGPIO->DIR[port] |= 1UL << bit; + } + else { + pGPIO->DIR[port] &= ~(1UL << bit); + } +} + +/** + * @brief Set GPIO direction for a single GPIO pin to an output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to set direction on as output + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->DIR[port] |= 1UL << pin; +} + +/** + * @brief Set GPIO direction for a single GPIO pin to an input + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to set direction on as input + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->DIR[port] &= ~(1UL << pin); +} + +/** + * @brief Set GPIO direction for a single GPIO pin + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to set direction for + * @param output : true for output, false for input + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output) +{ + if (output) { + Chip_GPIO_SetPinDIROutput(pGPIO, port, pin); + } + else { + Chip_GPIO_SetPinDIRInput(pGPIO, port, pin); + } +} + +/** + * @brief Read a GPIO direction (out or in) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read + * @param bit : GPIO bit to read + * @return true of the GPIO is an output, false if input + * @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead. + */ +STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit) +{ + return (bool) (((pGPIO->DIR[port]) >> bit) & 1); +} + +/** + * @brief Get GPIO direction for a single GPIO pin + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : GPIO pin to get direction for + * @return true if the GPIO is an output, false if input + */ +STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + return (bool) (((pGPIO->DIR[port]) >> pin) & 1); +} + +/** + * @brief Set Direction for a GPIO port + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port Number + * @param bitValue : GPIO bit to set + * @param out : Direction value, 0 = input, !0 = output + * @return None + * @note Bits set to '0' are not altered. It is recommended to use the + * Chip_GPIO_SetPortDIR() function instead. + */ +STATIC INLINE void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out) +{ + if (out) { + pGPIO->DIR[portNum] |= bitValue; + } + else { + pGPIO->DIR[portNum] &= ~bitValue; + } +} + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n) + * @return Nothing + * @note Sets multiple GPIO pins to the output direction, each bit's position that is + * high sets the corresponding pin number for that bit to an output. + */ +STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) +{ + pGPIO->DIR[port] |= pinMask; +} + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an input + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n) + * @return Nothing + * @note Sets multiple GPIO pins to the input direction, each bit's position that is + * high sets the corresponding pin number for that bit to an input. + */ +STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) +{ + pGPIO->DIR[port] &= ~pinMask; +} + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an input or output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n) + * @param outSet : Direction value, false = set as inputs, true = set as outputs + * @return Nothing + * @note Sets multiple GPIO pins to the input direction, each bit's position that is + * high sets the corresponding pin number for that bit to an input. + */ +STATIC INLINE void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet) +{ + if (outSet) { + Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask); + } + else { + Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask); + } +} + +/** + * @brief Get GPIO direction for a all GPIO pins + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @return a bitfield containing the input and output states for each pin + * @note For pins 0..n, a high state in a bit corresponds to an output state for the + * same pin, while a low state corresponds to an input state. + */ +STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->DIR[port]; +} + +/** + * @brief Set GPIO port mask value for GPIO masked read and write + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @param mask : Mask value for read and write (only low bits are enabled) + * @return Nothing + * @note Controls which bits are set or unset when using the masked + * GPIO read and write functions. A low state indicates the pin is settable + * and readable via the masked write and read functions. + */ +STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask) +{ + pGPIO->MASK[port] = mask; +} + +/** + * @brief Get GPIO port mask value used for GPIO masked read and write + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @return Returns value set with the Chip_GPIO_SetPortMask() function. + * @note A high bit in the return value indicates that that GPIO pin for the + * port cannot be set using the masked write function. + */ +STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->MASK[port]; +} + +/** + * @brief Set all GPIO raw pin states (regardless of masking) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param value : Value to set all GPIO pin states (0..n) to + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) +{ + pGPIO->PIN[port] = value; +} + +/** + * @brief Get all GPIO raw pin states (regardless of masking) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @return Current (raw) state of all GPIO pins + */ +STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->PIN[port]; +} + +/** + * @brief Set all GPIO pin states, but mask via the MASKP0 register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param value : Value to set all GPIO pin states (0..n) to + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) +{ + pGPIO->MPIN[port] = value; +} + +/** + * @brief Get all GPIO pin statesm but mask via the MASKP0 register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @return Current (masked) state of all GPIO pins + */ +STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->MPIN[port]; +} + +/** + * @brief Set a GPIO port/bit to the high state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number + * @param bitValue : bit(s) in the port to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. It is recommended to use the + * Chip_GPIO_SetPortOutHigh() function instead. + */ +STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) +{ + pGPIO->SET[portNum] = bitValue; +} + +/** + * @brief Set selected GPIO output pins to the high state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pins : pins (0..n) to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->SET[port] = pins; +} + +/** + * @brief Set an individual GPIO output pin to the high state + * @param pGPIO : The base of GPIO peripheral on the chip' + * @param port : GPIO Port number where @a pin is located + * @param pin : pin number (0..n) to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->SET[port] = (1 << pin); +} + +/** + * @brief Set a GPIO port/bit to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number + * @param bitValue : bit(s) in the port to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) +{ + pGPIO->CLR[portNum] = bitValue; +} + +/** + * @brief Set selected GPIO output pins to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pins : pins (0..n) to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->CLR[port] = pins; +} + +/** + * @brief Set an individual GPIO output pin to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : pin number (0..n) to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->CLR[port] = (1 << pin); +} + +/** + * @brief Toggle selected GPIO output pins to the opposite state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pins : pins (0..n) to toggle + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->NOT[port] = pins; +} + +/** + * @brief Toggle an individual GPIO output pin to the opposite state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO Port number where @a pin is located + * @param pin : pin number (0..n) to toggle + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->NOT[port] = (1 << pin); +} + +/** + * @brief Read current bit states for the selected port + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number to read + * @return Current value of GPIO port + * @note The current states of the bits for the port are read, regardless of + * whether the GPIO port bits are input or output. + */ +STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum) +{ + return pGPIO->PIN[portNum]; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h new file mode 100644 index 0000000000000..8a8e450ff052d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h @@ -0,0 +1,211 @@ +/* + * @brief LPC18xx/43xx GPIO group driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIOGROUP_18XX_43XX_H_ +#define __GPIOGROUP_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIOGP_18XX_43XX CHIP: LPC18xx/43xx GPIO group driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief GPIO grouped interrupt register block structure + */ +typedef struct { /*!< GPIO_GROUP_INTn Structure */ + __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */ + uint32_t RESERVED1[1000]; +} LPC_GPIOGROUPINT_T; + +/** + * LPC18xx/43xx GPIO group bit definitions + */ +#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */ +#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */ +#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */ + +/** + * @brief Clear interrupt pending status for the selected group + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + uint32_t temp; + + temp = pGPIOGPINT[group].CTRL; + pGPIOGPINT[group].CTRL = temp | GPIOGR_INT; +} + +/** + * @brief Returns current GPIO group inetrrupt pending status + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return true if the group interrupt is pending, otherwise false. + */ +STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0); +} + +/** + * @brief Selected GPIO group functionality for trigger on any pin in group (OR mode) + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB; +} + +/** + * @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode) + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL |= GPIOGR_COMB; +} + +/** + * @brief Selected GPIO group functionality edge trigger mode + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG; +} + +/** + * @brief Selected GPIO group functionality level trigger mode + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL |= GPIOGR_TRIG; +} + +/** + * @brief Set selected pins for the group and port to low level trigger + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_POL[port] &= ~pinMask; +} + +/** + * @brief Set selected pins for the group and port to high level trigger + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + */ +STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_POL[port] |= pinMask; +} + +/** + * @brief Disabled selected pins for the group interrupt + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + * @note Disabled pins do not contrinute to the group interrupt. + */ +STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask; +} + +/** + * @brief Enable selected pins for the group interrupt + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + * @note Enabled pins contribute to the group interrupt. + */ +STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_ENA[port] |= pinMask; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIOGROUP_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/hsadc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/hsadc_18xx_43xx.h new file mode 100644 index 0000000000000..a0f54512e7dae --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/hsadc_18xx_43xx.h @@ -0,0 +1,581 @@ +/* + * @brief LPC18xx/43xx High speed ADC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __HSADC_18XX_43XX_H_ +#define __HSADC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup HSADC_18XX_43XX CHIP: LPC18xx/43xx High speed ADC driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief High speed ADC interrupt control structure + */ +typedef struct { + __O uint32_t CLR_EN; /*!< Interrupt clear mask */ + __O uint32_t SET_EN; /*!< Interrupt set mask */ + __I uint32_t MASK; /*!< Interrupt mask */ + __I uint32_t STATUS; /*!< Interrupt status */ + __O uint32_t CLR_STAT; /*!< Interrupt clear status */ + __O uint32_t SET_STAT; /*!< Interrupt set status */ + uint32_t RESERVED[2]; +} HSADCINTCTRL_T; + +/** + * @brief HSADC register block structure + */ +typedef struct { /*!< HSADC Structure */ + __O uint32_t FLUSH; /*!< Flushes FIFO */ + __IO uint32_t DMA_REQ; /*!< Set or clear DMA write request */ + __I uint32_t FIFO_STS; /*!< Indicates FIFO fill level status */ + __IO uint32_t FIFO_CFG; /*!< Configures FIFO fill level */ + __O uint32_t TRIGGER; /*!< Enable software trigger to start descriptor processing */ + __IO uint32_t DSCR_STS; /*!< Indicates active descriptor table and descriptor entry */ + __IO uint32_t POWER_DOWN; /*!< Set or clear power down mode */ + __IO uint32_t CONFIG; /*!< Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down */ + __IO uint32_t THR[2]; /*!< Configures window comparator A or B levels */ + __I uint32_t LAST_SAMPLE[6]; /*!< Contains last converted sample of input M [M=0..5) and result of window comparator */ + uint32_t RESERVED0[49]; + __IO uint32_t ADC_SPEED; /*!< ADC speed control */ + __IO uint32_t POWER_CONTROL; /*!< Configures ADC power vs. speed, DC-in biasing, output format and power gating */ + uint32_t RESERVED1[61]; + __I uint32_t FIFO_OUTPUT[16]; /*!< FIFO output mapped to 16 consecutive address locations */ + uint32_t RESERVED2[48]; + __IO uint32_t DESCRIPTOR[2][8]; /*!< Table 0 and 1 descriptors */ + uint32_t RESERVED3[752]; + HSADCINTCTRL_T INTS[2]; /*!< Interrupt 0 and 1 control and status registers */ +} LPC_HSADC_T; + +#define HSADC_MAX_SAMPLEVAL 0xFFF + +/** + * @brief Initialize the High speed ADC + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + */ +void Chip_HSADC_Init(LPC_HSADC_T *pHSADC); + +/** + * @brief Shutdown HSADC + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + */ +void Chip_HSADC_DeInit(LPC_HSADC_T *pHSADC); + +/** + * @brief Flush High speed ADC FIFO + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_FlushFIFO(LPC_HSADC_T *pHSADC) +{ + pHSADC->FLUSH = 1; +} + +/** + * @brief Load a descriptor table from memory by requesting a DMA write + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + * @note WHat is this used for? + */ +STATIC INLINE void Chip_HSADC_LoadDMADesc(LPC_HSADC_T *pHSADC) +{ + pHSADC->DMA_REQ = 1; +} + +/** + * @brief Returns current HSADC FIFO fill level + * @param pHSADC : The base of HSADC peripheral on the chip + * @return FIFO level, 0 for empty, 1 to 15, or 16 for full + * @note WHat is this used for? + */ +STATIC INLINE uint32_t Chip_HSADC_GetFIFOLevel(LPC_HSADC_T *pHSADC) +{ + return pHSADC->FIFO_STS; +} + +/** + * @brief Sets up HSADC FIFO trip level and packing + * @param pHSADC : The base of HSADC peripheral on the chip + * @param trip : HSADC FIFO trip point (1 to 15 samples) + * @param packed : true to pack samples, false for no packing + * @return Nothing + * @note The FIFO trip point is used for the DMA or interrupt level. + * Sample packging allows packing 2 samples into a single 32-bit + * word. + */ +void Chip_HSADC_SetupFIFO(LPC_HSADC_T *pHSADC, uint8_t trip, bool packed); + +/** + * @brief Starts a manual (software) trigger of HSADC descriptors + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_SWTrigger(LPC_HSADC_T *pHSADC) +{ + pHSADC->TRIGGER = 1; +} + +/** + * @brief Set active table descriptor index and number + * @param pHSADC : The base of HSADC peripheral on the chip + * @param table : Table index, 0 or 1 + * @param desc : Descriptor index, 0 to 7 + * @return Nothing + * @note This function can be used to set active descriptor table and + * active descriptor entry values. The new values will be updated + * immediately. This should only be updated when descriptors are + * not running (halted). + */ +STATIC INLINE void Chip_HSADC_SetActiveDescriptor(LPC_HSADC_T *pHSADC, uint8_t table, uint8_t desc) +{ + pHSADC->DSCR_STS = (uint32_t) ((desc << 1) | table); +} + +/** + * @brief Returns currently active descriptor index being processed + * @param pHSADC : The base of HSADC peripheral on the chip + * @return the current active descriptor index, 0 to 7 + */ +STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorIndex(LPC_HSADC_T *pHSADC) +{ + return (uint8_t) ((pHSADC->DSCR_STS >> 1) & 0x7); +} + +/** + * @brief Returns currently active descriptor table being processed + * @param pHSADC : The base of HSADC peripheral on the chip + * @return the current active descriptor table, 0 or 1 + */ +STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorTable(LPC_HSADC_T *pHSADC) +{ + return (uint8_t) (pHSADC->DSCR_STS & 1); +} + +/** + * @brief Enables ADC power down mode + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + * @note In most cases, this function doesn't need to be used as + * the descriptors control power as needed. + */ +STATIC INLINE void Chip_HSADC_EnablePowerDownMode(LPC_HSADC_T *pHSADC) +{ + pHSADC->POWER_DOWN = 1; +} + +/** + * @brief Disables ADC power down mode + * @param pHSADC : The base of HSADC peripheral on the chip + * @return Nothing + * @note In most cases, this function doesn't need to be used as + * the descriptors control power as needed. + */ +STATIC INLINE void Chip_HSADC_DisablePowerDownMode(LPC_HSADC_T *pHSADC) +{ + pHSADC->POWER_DOWN = 0; +} + +/* HSADC trigger configuration mask types */ +typedef enum { + HSADC_CONFIG_TRIGGER_OFF = 0, /*!< ADCHS triggers off */ + HSADC_CONFIG_TRIGGER_SW = 1, /*!< ADCHS software trigger only */ + HSADC_CONFIG_TRIGGER_EXT = 2, /*!< ADCHS external trigger only */ + HSADC_CONFIG_TRIGGER_BOTH = 3 /*!< ADCHS both software and external triggers allowed */ +} HSADC_TRIGGER_MASK_T; + +/* HSADC trigger configuration mode types */ +typedef enum { + HSADC_CONFIG_TRIGGER_RISEEXT = (0 << 2), /*!< ADCHS rising external trigger */ + HSADC_CONFIG_TRIGGER_FALLEXT = (1 << 2), /*!< ADCHS falling external trigger */ + HSADC_CONFIG_TRIGGER_LOWEXT = (2 << 2), /*!< ADCHS low external trigger */ + HSADC_CONFIG_TRIGGER_HIGHEXT = (3 << 2) /*!< ADCHS high external trigger */ +} HSADC_TRIGGER_MODE_T; + +/* HSADC trigger configuration sync types */ +typedef enum { + HSADC_CONFIG_TRIGGER_NOEXTSYNC = (0 << 4), /*!< do not synchronize external trigger input */ + HSADC_CONFIG_TRIGGER_EXTSYNC = (1 << 4), /*!< synchronize external trigger input */ +} HSADC_TRIGGER_SYNC_T; + +/* HSADC trigger configuration channel ID */ +typedef enum { + HSADC_CHANNEL_ID_EN_NONE = (0 << 5), /*!< do not add channel ID to FIFO output data */ + HSADC_CHANNEL_ID_EN_ADD = (1 << 5), /*!< add channel ID to FIFO output data */ +} HSADC_CHANNEL_ID_EN_T; + +/** + * @brief Configure HSADC trigger source and recovery time + * @param pHSADC : The base of HSADC peripheral on the chip + * @param mask : HSADC trigger configuration mask type + * @param mode : HSADC trigger configuration mode type + * @param sync : HSADC trigger configuration sync type + * @param chID : HSADC trigger configuration channel ID enable + * @param recoveryTime : ADC recovery time (in HSADC clocks) from powerdown (255 max) + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_ConfigureTrigger(LPC_HSADC_T *pHSADC, + HSADC_TRIGGER_MASK_T mask, + HSADC_TRIGGER_MODE_T mode, + HSADC_TRIGGER_SYNC_T sync, + HSADC_CHANNEL_ID_EN_T chID, uint16_t recoveryTime) +{ + pHSADC->CONFIG = (uint32_t) mask | (uint32_t) mode | (uint32_t) sync | + (uint32_t) chID | (uint32_t) (recoveryTime << 6); +} + +/** + * @brief Set HSADC Threshold low value + * @param pHSADC : The base of HSADC peripheral on the chip + * @param thrnum : Threshold register value (0 for threshold register A, 1 for threshold register B) + * @param value : Threshold low data value (should be 12-bit value) + * @return None + */ +void Chip_HSADC_SetThrLowValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value); + +/** + * @brief Set HSADC Threshold high value + * @param pHSADC : The base of HSADC peripheral on the chip + * @param thrnum : Threshold register value (0 for threshold register A, 1 for threshold register B) + * @param value : Threshold high data value (should be 12-bit value) + * @return None + */ +void Chip_HSADC_SetThrHighValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value); + +/** HSADC last sample registers bit fields */ +#define HSADC_LS_DONE (1 << 0) /*!< Sample conversion complete bit */ +#define HSADC_LS_OVERRUN (1 << 1) /*!< Sample overrun bit */ +#define HSADC_LS_RANGE_IN (0 << 2) /*!< Threshold range comparison is in range */ +#define HSADC_LS_RANGE_BELOW (1 << 2) /*!< Threshold range comparison is below range */ +#define HSADC_LS_RANGE_ABOVE (2 << 2) /*!< Threshold range comparison is above range */ +#define HSADC_LS_RANGE(val) ((val) & 0xC) /*!< Mask for threshold crossing comparison result */ +#define HSADC_LS_CROSSING_NONE (0 << 4) /*!< No threshold crossing detected */ +#define HSADC_LS_CROSSING_DOWN (1 << 4) /*!< Downward threshold crossing detected */ +#define HSADC_LS_CROSSING_UP (2 << 4) /*!< Upward threshold crossing detected */ +#define HSADC_LS_CROSSING(val) ((val) & 0x30) /*!< Mask for threshold crossing comparison result */ +#define HSADC_LS_DATA(val) ((val) >> 6) /*!< Mask data value out of sample */ + +/** + * @brief Read a ADC last sample register + * @param pHSADC : The base of ADC peripheral on the chip + * @param channel : Last sample register to read, 0-5 + * @return Current raw value of the indexed last sample register + * @note This function returns the raw value of the indexed last sample register + * and clears the sample's DONE and OVERRUN statuses if set. You can determine + * the overrun and datavalid status for the sample by masking the return value + * with HSADC_LS_DONE or HSADC_LS_OVERRUN. To get the data value for the sample, + * use the HSADC_LS_DATA(sample) macro. The threshold range and crossing results + * can be determined by using the HSADC_LS_RANGE(sample) and + * HSADC_LS_CROSSING(sample) macros and comparing the result against the + * HSADC_LS_RANGE_* or HSADC_LS_CROSSING_* definitions.
+ */ +STATIC INLINE uint32_t Chip_HSADC_GetLastSample(LPC_HSADC_T *pHSADC, uint8_t channel) +{ + return pHSADC->LAST_SAMPLE[channel]; +} + +/** + * @brief Setup speed for a input channel + * @param pHSADC : The base of ADC peripheral on the chip + * @param channel : Input to set, 0-5 + * @param speed : Speed value to set (0xF, 0xE, or 0x0), see user manual + * @return Nothing + * @note It is recommended not to use this function, as the values needed + * for this register will be setup with the Chip_HSADC_SetPowerSpeed() function. + */ +void Chip_HSADC_SetSpeed(LPC_HSADC_T *pHSADC, uint8_t channel, uint8_t speed); + +/** + * @brief Setup (common) HSADC power and speed settings + * @param pHSADC : The base of ADC peripheral on the chip + * @param comp2 : True sets up for 2's complement, false sets up for offset binary data format + * @return Nothing + * @note This function sets up the HSADC current/power/speed settings that + * apply to all HSADC channels (inputs). Based on the HSADC clock rate, it will + * automatically setup the best current setting (CRS) and speed settings (DGEC) + * for all channels. (See user manual).
+ * This function is also used to set the data format of the sampled data. It is + * recommended to call this function if the HSADC sample rate changes. + */ +void Chip_HSADC_SetPowerSpeed(LPC_HSADC_T *pHSADC, bool comp2); + +/* AC-DC coupling selection for vin_neg and vin_pos sides */ +typedef enum { + HSADC_CHANNEL_NODCBIAS = 0, /*!< No DC bias */ + HSADC_CHANNEL_DCBIAS = 1, /*!< DC bias on vin_neg side */ +} HSADC_DCBIAS_T; + +/** + * @brief Setup AC-DC coupling selection for a channel + * @param pHSADC : The base of ADC peripheral on the chip + * @param channel : Input to set, 0-5 + * @param dcInNeg : AC-DC coupling selection on vin_neg side + * @param dcInPos : AC-DC coupling selection on vin_pos side + * @return Nothing + * @note This function sets up the HSADC current/power/speed settings that + * apply to all HSADC channels (inputs). Based on the HSADC clock rate, it will + * automatically setup the best current setting (CRS) and speed settings (DGEC) + * for all channels. (See user manual).
+ * This function is also used to set the data format of the sampled data. It is + * recommended to call this function if the HSADC sample rate changes. + */ +void Chip_HSADC_SetACDCBias(LPC_HSADC_T *pHSADC, uint8_t channel, + HSADC_DCBIAS_T dcInNeg, HSADC_DCBIAS_T dcInPos); + +/** + * @brief Enable HSADC power control and band gap reference + * @param pHSADC : The base of ADC peripheral on the chip + * @return Nothing + * @note This function enables both the HSADC power and band gap + * reference. + */ +STATIC INLINE void Chip_HSADC_EnablePower(LPC_HSADC_T *pHSADC) +{ + pHSADC->POWER_CONTROL |= (1 << 17) | (1 << 18); +} + +/** + * @brief Disable HSADC power control and band gap reference + * @param pHSADC : The base of ADC peripheral on the chip + * @return Nothing + * @note This function disables both the HSADC power and band gap + * reference. + */ +STATIC INLINE void Chip_HSADC_DisablePower(LPC_HSADC_T *pHSADC) +{ + pHSADC->POWER_CONTROL &= ~((1 << 17) | (1 << 18)); +} + +/** HSADC FIFO registers bit fields for unpacked sample in lower 16 bits */ +#define HSADC_FIFO_SAMPLE_MASK (0xFFF) /*!< 12-bit sample mask (unpacked) */ +#define HSADC_FIFO_SAMPLE(val) ((val) & 0xFFF) /*!< Macro for stripping out unpacked sample data */ +#define HSADC_FIFO_CHAN_ID_MASK (0x7000) /*!< Channel ID mask */ +#define HSADC_FIFO_CHAN_ID(val) (((val) >> 12) & 0x7) /*!< Macro for stripping out sample data */ +#define HSADC_FIFO_EMPTY (0x1 << 15) /*!< FIFO empty (invalid sample) */ +#define HSADC_FIFO_SHIFTPACKED(val) ((val) >> 16) /*!< Shifts the packed FIFO sample into the lower 16-bits of a word */ +#define HSADC_FIFO_PACKEDMASK (1UL << 31) /*!< Packed sample check mask */ + +/** + * @brief Reads the HSADC FIFO + * @param pHSADC : The base of ADC peripheral on the chip + * @return HSADC FIFO value + * @note This function reads and pops the HSADC FIFO. The FIFO + * contents can be determined by using the HSADC_FIFO_* macros. If + * FIFO packing is enabled, this may contain 2 samples. Use the + * HSADC_FIFO_SHIFTPACKED macro to shift packed sample data into a + * variable that can be used with the HSADC_FIFO_* macros. Note that + * even if packing is enabled, the packed sample may not be valid. + */ +STATIC INLINE uint32_t Chip_HSADC_GetFIFO(LPC_HSADC_T *pHSADC) +{ + return pHSADC->FIFO_OUTPUT[0]; +} + +/** HSADC descriptor registers bit fields and support macros */ +#define HSADC_DESC_CH(ch) (ch) /*!< Converter input channel */ +#define HSADC_DESC_HALT (1 << 3) /*!< Descriptor halt after conversion bit */ +#define HSADC_DESC_INT (1 << 4) /*!< Raise interrupt when ADC result is available bit */ +#define HSADC_DESC_POWERDOWN (1 << 5) /*!< Power down after this conversion bit */ +#define HSADC_DESC_BRANCH_NEXT (0 << 6) /*!< Continue with next descriptor */ +#define HSADC_DESC_BRANCH_FIRST (1 << 6) /*!< Branch to the first descriptor */ +#define HSADC_DESC_BRANCH_SWAP (2 << 6) /*!< Swap tables and branch to the first descriptor of the new table */ +#define HSADC_DESC_MATCH(val) ((val) << 8) /*!< Match value used to trigger a descriptor */ +#define HSADC_DESC_THRESH_NONE (0 << 22) /*!< No threshold detection performed */ +#define HSADC_DESC_THRESH_A (1 << 22) /*!< Use A threshold detection */ +#define HSADC_DESC_THRESH_B (2 << 22) /*!< Use B threshold detection */ +#define HSADC_DESC_RESET_TIMER (1 << 24) /*!< Reset descriptor timer */ +#define HSADC_DESC_UPDATE_TABLE (1UL << 31) /*!< Update table with all 8 descriptors of this table */ + +/** + * @brief Sets up a raw HSADC descriptor entry + * @param pHSADC : The base of ADC peripheral on the chip + * @param table : Descriptor table number, 0 or 1 + * @param descNo : Descriptor number to setup, 0 to 7 + * @param desc : Raw descriptor value (see notes) + * @return Nothing + * @note This function sets up a descriptor table entry. To setup + * a descriptor entry, select a OR'ed combination of the HSADC_DESC_CH, + * HSADC_DESC_HALT, HSADC_DESC_INT, HSADC_DESC_POWERDOWN, one of + * HSADC_DESC_BRANCH_*, HSADC_DESC_MATCH, one of HSADC_DESC_THRESH_*, and + * HSADC_DESC_RESET_TIMER definitions.
+ * Example for setting up a table 0, descriptor number 4 entry for input 0:
+ * Chip_HSADC_SetupDescEntry(LPC_HSADC, 0, 4, (HSADC_DESC_CH(0) | HSADC_DESC_HALT | + * HSADC_DESC_INT)); + */ +STATIC INLINE void Chip_HSADC_SetupDescEntry(LPC_HSADC_T *pHSADC, uint8_t table, + uint8_t descNo, uint32_t desc) +{ + pHSADC->DESCRIPTOR[table][descNo] = desc; +} + +/** + * @brief Update all descriptors of a table + * @param pHSADC : The base of ADC peripheral on the chip + * @param table : Descriptor table number, 0 or 1 + * @return Nothing + * @note Updates descriptor table with all 8 descriptors. This + * function should be used after all descriptors are setup with + * the Chip_HSADC_SetupDescEntry() function. + */ +STATIC INLINE void Chip_HSADC_UpdateDescTable(LPC_HSADC_T *pHSADC, uint8_t table) +{ + pHSADC->DESCRIPTOR[table][0] |= HSADC_DESC_UPDATE_TABLE; +} + +/* Interrupt selection for interrupt 0 set - these interrupts and statuses + should only be used with the interrupt 0 register set */ +#define HSADC_INT0_FIFO_FULL (1 << 0) /*!< number of samples in FIFO is more than FIFO_LEVEL */ +#define HSADC_INT0_FIFO_EMPTY (1 << 1) /*!< FIFO is empty */ +#define HSADC_INT0_FIFO_OVERFLOW (1 << 2) /*!< FIFO was full; conversion sample is not stored and lost */ +#define HSADC_INT0_DSCR_DONE (1 << 3) /*!< The descriptor INTERRUPT field was enabled and its sample is converted */ +#define HSADC_INT0_DSCR_ERROR (1 << 4) /*!< The ADC was not fully woken up when a sample was converted and the conversion results is unreliable */ +#define HSADC_INT0_ADC_OVF (1 << 5) /*!< Converted sample value was over range of the 12 bit output code */ +#define HSADC_INT0_ADC_UNF (1 << 6) /*!< Converted sample value was under range of the 12 bit output code */ + +/* Interrupt selection for interrupt 1 set - these interrupts and statuses + should only be used with the interrupt 1 register set */ +#define HSADC_INT1_THCMP_BRANGE(ch) (1 << ((ch * 5) + 0)) /*!< Input channel result below range */ +#define HSADC_INT1_THCMP_ARANGE(ch) (1 << ((ch * 5) + 1)) /*!< Input channel result above range */ +#define HSADC_INT1_THCMP_DCROSS(ch) (1 << ((ch * 5) + 2)) /*!< Input channel result downward threshold crossing detected */ +#define HSADC_INT1_THCMP_UCROSS(ch) (1 << ((ch * 5) + 3)) /*!< Input channel result upward threshold crossing detected */ +#define HSADC_INT1_OVERRUN(ch) (1 << ((ch * 5) + 4)) /*!< New conversion on channel completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read */ + +/** + * @brief Enable an interrupt for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @param intMask : Interrupts to enable, use HSADC_INT0_* for group 0 + * and HSADC_INT1_* values for group 1 + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_EnableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask) +{ + pHSADC->INTS[intGrp].SET_EN = intMask; +} + +/** + * @brief Disables an interrupt for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @param intMask : Interrupts to disable, use HSADC_INT0_* for group 0 + * and HSADC_INT1_* values for group 1 + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_DisableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask) +{ + pHSADC->INTS[intGrp].CLR_EN = intMask; +} + +/** + * @brief Returns enabled interrupt for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @return enabled interrupts for the selected group + * @note Mask the return value with a HSADC_INT0_* macro for group 0 + * or HSADC_INT1_* values for group 1 to determine which interrupts are enabled. + */ +STATIC INLINE uint32_t Chip_HSADC_GetEnabledInts(LPC_HSADC_T *pHSADC, uint8_t intGrp) +{ + return pHSADC->INTS[intGrp].MASK; +} + +/** + * @brief Returns status for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @return interrupt (pending) status for the selected group + * @note Mask the return value with a HSADC_INT0_* macro for group 0 + * or HSADC_INT1_* values for group 1 to determine which statuses are active. + */ +STATIC INLINE uint32_t Chip_HSADC_GetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp) +{ + return pHSADC->INTS[intGrp].STATUS; +} + +/** + * @brief Clear a status for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @param stsMask : Statuses to clear, use HSADC_INT0_* for group 0 + * and HSADC_INT1_* values for group 1 + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_ClearIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask) +{ + pHSADC->INTS[intGrp].CLR_STAT = stsMask; +} + +/** + * @brief Sets a status for HSADC interrupt group 0 or 1 + * @param pHSADC : The base of ADC peripheral on the chip + * @param intGrp : Interrupt group 0 or 1 + * @param stsMask : Statuses to set, use HSADC_INT0_* for group 0 + * and HSADC_INT1_* values for group 1 + * @return Nothing + */ +STATIC INLINE void Chip_HSADC_SetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask) +{ + pHSADC->INTS[intGrp].SET_STAT = stsMask; +} + +/** + * @brief Returns the clock rate in Hz for the HSADC + * @param pHSADC : The base of HSADC peripheral on the chip + * @return clock rate in Hz for the HSADC + */ +STATIC INLINE uint32_t Chip_HSADC_GetBaseClockRate(LPC_HSADC_T *pHSADC) +{ + (void) pHSADC; + + /* Return computed sample rate for the high speed ADC peripheral */ + return Chip_Clock_GetRate(CLK_ADCHS); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HSADC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/i2c_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/i2c_18xx_43xx.h new file mode 100644 index 0000000000000..74916ff2b9e3b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/i2c_18xx_43xx.h @@ -0,0 +1,406 @@ +/* + * @brief LPC18xx/43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2C_18XX_43XX_H_ +#define __I2C_18XX_43XX_H_ +#include "i2c_common_18xx_43xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup I2C_18XX_43XX + * @{ + */ + +/** + * @brief Return values for SLAVE handler + * @note + * Chip drivers will usally be designed to match their events with this value + */ +#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */ +#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */ +#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */ +#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */ + +/** + * @brief I2C state handle return values + */ +#define I2C_STA_STO_RECV 0x20 + +/* + * @brief I2C return status code definitions + */ +#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */ +#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */ + +/* + * @brief I2C status values + */ +#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */ +#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */ +#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */ + +/* + * @brief I2C state handle return values + */ +#define I2C_OK 0x00 +#define I2C_BYTE_SENT 0x01 +#define I2C_BYTE_RECV 0x02 +#define I2C_LAST_BYTE_RECV 0x04 +#define I2C_SEND_END 0x08 +#define I2C_RECV_END 0x10 +#define I2C_STA_STO_RECV 0x20 + +#define I2C_ERR (0x10000000) +#define I2C_NAK_RECV (0x10000000 | 0x01) + +#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000) + +/* + * @brief I2C monitor control configuration defines + */ +#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */ +#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */ + +/** + * @brief I2C Slave Identifiers + */ +typedef enum { + I2C_SLAVE_GENERAL, /**< Slave ID for general calls */ + I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */ + I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */ + I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */ + I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */ + I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */ +} I2C_SLAVE_ID; + +/** + * @brief I2C transfer status + */ +typedef enum { + I2C_STATUS_DONE, /**< Transfer done successfully */ + I2C_STATUS_NAK, /**< NAK received during transfer */ + I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */ + I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */ + I2C_STATUS_BUSY, /**< I2C is busy doing transfer */ + I2C_STATUS_SLAVENAK,/**< NAK received after SLA+W or SLA+R */ +} I2C_STATUS_T; + +/** + * @brief Master transfer data structure definitions + */ +typedef struct { + uint8_t slaveAddr; /**< 7-bit I2C Slave address */ + const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */ + int txSz; /**< Number of bytes in transmit array, + if 0 only receive transfer will be carried on */ + uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */ + int rxSz; /**< Number of bytes to received, + if 0 only transmission we be carried on */ + I2C_STATUS_T status; /**< Status of the current I2C transfer */ +} I2C_XFER_T; + +/** + * @brief I2C interface IDs + * @note + * All Chip functions will take this as the first parameter, + * I2C_NUM_INTERFACE must never be used for calling any Chip + * functions, it is only used to find the number of interfaces + * available in the Chip. + */ +typedef enum I2C_ID { + I2C0, /**< ID I2C0 */ + I2C1, /**< ID I2C1 */ + I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */ +} I2C_ID_T; + +/** + * @brief I2C master events + */ +typedef enum { + I2C_EVENT_WAIT = 1, /**< I2C Wait event */ + I2C_EVENT_DONE, /**< Done event that wakes up Wait event */ + I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */ + I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */ + I2C_EVENT_SLAVE_RX, /**< Slave receive event */ + I2C_EVENT_SLAVE_TX, /**< Slave transmit event */ +} I2C_EVENT_T; + +/** + * @brief Event handler function type + */ +typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T); + +/** + * @brief Initializes the LPC_I2C peripheral with specified parameter. + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Nothing + */ +void Chip_I2C_Init(I2C_ID_T id); + +/** + * @brief De-initializes the I2C peripheral registers to their default reset values + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Nothing + */ +void Chip_I2C_DeInit(I2C_ID_T id); + +/** + * @brief Set up clock rate for LPC_I2C peripheral. + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param clockrate : Target clock rate value to initialized I2C peripheral (Hz) + * @return Nothing + * @note + * Parameter @a clockrate for I2C0 should be from 1000 up to 1000000 + * (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate + * is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus() + * must be called prior to calling this function. + */ +void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate); + +/** + * @brief Get current clock rate for LPC_I2C peripheral. + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return The current I2C peripheral clock rate + */ +uint32_t Chip_I2C_GetClockRate(I2C_ID_T id); + +/** + * @brief Transmit and Receive data in master mode + * @param id : I2C peripheral selected (I2C0, I2C1 etc) + * @param xfer : Pointer to a I2C_XFER_T structure see notes below + * @return + * Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes + * not sent due to error, xfer->rxSz will have the number of bytes yet + * to be received. + * @note + * The parameter @a xfer should have its member @a slaveAddr initialized + * to the 7-Bit slave address to which the master will do the xfer, Bit0 + * to bit6 should have the address and Bit8 is ignored. During the transfer + * no code (like event handler) must change the content of the memory + * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be + * initialized to the memory from which the I2C must pick the data to be + * transfered to slave and the number of bytes to send respectively, similarly + * @a rxBuff and @a rxSz must have pointer to memroy where data received + * from slave be stored and the number of data to get from slave respectilvely. + */ +int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer); + +/** + * @brief Transmit data to I2C slave using I2C Master mode + * @param id : I2C peripheral ID (I2C0, I2C1 .. etc) + * @param slaveAddr : Slave address to which the data be written + * @param buff : Pointer to buffer having the array of data + * @param len : Number of bytes to be transfered from @a buff + * @return Number of bytes successfully transfered + */ +int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len); + +/** + * @brief Transfer a command to slave and receive data from slave after a repeated start + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param slaveAddr : Slave address of the I2C device + * @param cmd : Command (Address/Register) to be written + * @param buff : Pointer to memory that will hold the data received + * @param len : Number of bytes to receive + * @return Number of bytes successfully received + */ +int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len); + +/** + * @brief Get pointer to current function handling the events + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Pointer to function handing events of I2C + */ +I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id); + +/** + * @brief Set function that must handle I2C events + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param event : Pointer to function that will handle the event (Should not be NULL) + * @return 1 when successful, 0 when a transfer is on going with its own event handler + */ +int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event); + +/** + * @brief Set function that must handle I2C events + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param slaveAddr : Slave address from which data be read + * @param buff : Pointer to memory where data read be stored + * @param len : Number of bytes to read from slave + * @return Number of bytes read successfully + */ +int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len); + +/** + * @brief Default event handler for polling operation + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param event : Event ID of the event that called the function + * @return Nothing + */ +void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event); + +/** + * @brief Default event handler for interrupt base operation + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param event : Event ID of the event that called the function + * @return Nothing + */ +void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event); + +/** + * @brief I2C Master transfer state change handler + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Nothing + * @note Usually called from the appropriate Interrupt handler + */ +void Chip_I2C_MasterStateHandler(I2C_ID_T id); + +/** + * @brief Disable I2C peripheral's operation + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Nothing + */ +void Chip_I2C_Disable(I2C_ID_T id); + +/** + * @brief Checks if master xfer in progress + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return 1 if master xfer in progress 0 otherwise + * @note + * This API is generally used in interrupt handler + * of the application to decide whether to call + * master state handler or to call slave state handler + */ +int Chip_I2C_IsMasterActive(I2C_ID_T id); + +/** + * @brief Setup a slave I2C device + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc) + * @param xfer : Pointer to transfer structure (see note below for more info) + * @param event : Event handler for slave transfers + * @param addrMask : Address mask to use along with slave address (see notes below for more info) + * @return Nothing + * @note + * Parameter @a xfer should point to a valid I2C_XFER_T structure object + * and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7), + * Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will + * be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers + * where slave can receive or send the data from, size of which will be provided by + * @a rxSz and @a txSz respectively. Function pointed to by @a event will be called + * for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully + * from the master and stored inside memory pointed by xfer->rxBuff, incremented + * the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of + * data from xfer->txBuff was sent to master successfully, incremented the pointer + * and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers + * with the slave).
+ *
Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1 + * to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as + * don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then + * 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered + * slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual + * address which was received from master.
+ *
General Call Handling
+ * Slave can receive data from master using general call address (0x00). General call + * handling must be setup as given below + * - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL + * - xfer->slaveAddr ignored, argument @a addrMask ignored + * - function provided by @a event will registered to be called when slave received data using addr 0x00 + * - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer + * - To handle General Call only (No other slaves are configured) + * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3) + * - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL + * - provide @a addrMask (typically 0, if not you better be knowing what you are doing) + * - To handler General Call when other slave is active + * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3) + * - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7] + * - Set Bit0 of @a xfer->slaveAddr as 1 + * - Provide appropriate @a addrMask + * - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC + * @warning + * If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler + * will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer + * then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be + * called to notify this. For more info see section below
+ *
Last data handling in slave
+ * If the user wants to implement a slave which will read a byte from a specific location over and over + * again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read + * the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from + * xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another + * byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will + * occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte + * event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer + * and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte + * in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and + * the process repeats. + */ +void Chip_I2C_SlaveSetup(I2C_ID_T id, + I2C_SLAVE_ID sid, + I2C_XFER_T *xfer, + I2C_EVENTHANDLER_T event, + uint8_t addrMask); + +/** + * @brief I2C Slave event handler + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return Nothing + */ +void Chip_I2C_SlaveStateHandler(I2C_ID_T id); + +/** + * @brief I2C peripheral state change checking + * @param id : I2C peripheral ID (I2C0, I2C1 ... etc) + * @return 1 if I2C peripheral @a id has changed its state, + * 0 if there is no state change + * @note + * This function must be used by the application when + * the polling has to be done based on state change. + */ +int Chip_I2C_IsStateChanged(I2C_ID_T id); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h new file mode 100644 index 0000000000000..8311dfd0ee127 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h @@ -0,0 +1,206 @@ +/* + * @brief LPC18xx_43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2C_COMMON_18XX_43XX_H_ +#define __I2C_COMMON_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2C_18XX_43XX CHIP: LPC18xx_43xx I2C driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief I2C register block structure + */ +typedef struct { /* I2C0 Structure */ + __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ + __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ + __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ + __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ + __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __IO uint32_t MMCTRL; /*!< Monitor mode control register. */ + __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ + __IO uint32_t MASK[4]; /*!< I2C Slave address mask register */ +} LPC_I2C_T; + +/* + * @brief I2C Control Set register description + */ +#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */ +#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */ +#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */ +#define I2C_I2CONSET_STA ((0x20))/*!< START flag */ +#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */ + +/* + * @brief I2C Control Clear register description + */ +#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */ +#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */ +#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */ +#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */ +#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */ + +/* + * @brief I2C Common Control register description + */ +#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */ +#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */ +#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */ +#define I2C_CON_STA (1UL << 5) /*!< START flag bit */ +#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */ + +/* + * @brief I2C Status Code definition (I2C Status register) + */ +#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */ +#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */ + +/* + * @brief I2C Master transmit mode + */ +#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */ +#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */ +#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */ + +/* + * @brief I2C Master receive mode + */ +#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */ +#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */ +#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */ +#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */ +#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */ + +/* + * @brief I2C Slave receive mode + */ +#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */ +// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */ +#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */ +// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */ +#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or + SLV/TRX (Slave Transmit) */ + +/* + * @brief I2C Slave transmit mode + */ +#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */ +#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */ +// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */ +#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */ +#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */ +#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */ +#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */ + +/* + * @brief I2C Data register definition + */ +#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */ +#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than + its sending data length that can be supported */ + +/* + * @brief I2C Monitor mode control register description + */ +#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */ +#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */ +#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */ +#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */ + +/* + * @brief I2C Data buffer register description + */ +#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */ + +/* + * @brief I2C Slave Address registers definition + */ +#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */ +#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */ + +/* + * @brief I2C Mask Register definition + */ +#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */ + +/* + * @brief I2C SCL HIGH duty cycle Register definition + */ +#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */ + +/* + * @brief I2C SCL LOW duty cycle Register definition + */ +#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */ + +/* + * @brief I2C monitor control configuration defines + */ +#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */ +#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */ + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __I2C_COMMON_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/i2cm_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/i2cm_18xx_43xx.h new file mode 100644 index 0000000000000..439ab60d81666 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/i2cm_18xx_43xx.h @@ -0,0 +1,425 @@ +/* + * @brief LPC18xx/43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2CM_18XX_43XX_H_ +#define __I2CM_18XX_43XX_H_ + +#include "i2c_common_18xx_43xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2CM_18XX_43XX CHIP: LPC18xx/43xx I2C master-only driver + * @ingroup I2C_18XX_43XX + * This driver only works in master mode. To describe the I2C transactions + * following symbols are used in driver documentation. + * + * Key to symbols + * ============== + * S (1 bit) : Start bit + * P (1 bit) : Stop bit + * Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0. + * A, NA (1 bit) : Acknowledge and Not-Acknowledge bit. + * Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to + * get a 10 bit I2C address. + * Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh + * for 16 bit data. + * [..]: Data sent by I2C device, as opposed to data sent by the host adapter. + * @{ + */ + +/** I2CM_18XX_43XX_OPTIONS_TYPES I2C master transfer options + * @{ + */ + +/** Ignore NACK during data transfer. By default transfer is aborted. */ +#define I2CM_XFER_OPTION_IGNORE_NACK 0x01 +/** ACK last byte received. By default we NACK last byte we receive per I2C spec. */ +#define I2CM_XFER_OPTION_LAST_RX_ACK 0x02 + +/** + * @} + */ + +/** I2CM_18XX_43XX_STATUS_TYPES I2C master transfer status types + * @{ + */ + +#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */ +#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */ +#define I2CM_STATUS_NAK 0x02 /*!< No acknowledgement received from slave. */ +#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */ +#define I2CM_STATUS_SLAVE_NAK 0x04 /*!< No device responded for given slave address during SLA+W or SLA+R */ +#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */ +#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmitter is busy. */ + +/** + * @} + */ + +/** + * @brief Master transfer data structure definitions + */ +typedef struct { + uint8_t slaveAddr; /*!< 7-bit I2C Slave address */ + uint8_t options; /*!< Options for transfer*/ + uint16_t status; /*!< Status of the current I2C transfer */ + uint16_t txSz; /*!< Number of bytes in transmit array, + if 0 only receive transfer will be carried on */ + uint16_t rxSz; /*!< Number of bytes to received, + if 0 only transmission we be carried on */ + const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */ + uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */ +} I2CM_XFER_T; + +/** + * @brief Initialize I2C Interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function enables the I2C clock. + */ +void Chip_I2CM_Init(LPC_I2C_T *pI2C); + +/** + * @brief Shutdown I2C Interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function disables the I2C clock. + */ +void Chip_I2CM_DeInit(LPC_I2C_T *pI2C); + +/** + * @brief Sets HIGH and LOW duty cycle registers + * @param pI2C : Pointer to selected I2C peripheral + * @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time. + * @param sclL : Number of I2C_PCLK cycles for the SCL LOW time. + * @return Nothing + * @note The frequency is determined by the following formula (I2C_PCLK + * is the frequency of the peripheral I2C clock):
+ * I2C_bitFrequency = (I2C_PCLK)/(sclH + sclL); + */ +static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL) +{ + pI2C->SCLH = (uint32_t) sclH; + pI2C->SCLL = (uint32_t) sclL; +} + +/** + * @brief Set up bus speed for LPC_I2C controller + * @param pI2C : Pointer to selected I2C peripheral + * @param busSpeed : I2C bus clock rate + * @return Nothing + * @note Per I2C specification the busSpeed should be + * @li 100000 for Standard mode + * @li 400000 for Fast mode + * @li 1000000 for Fast mode plus + * IOCON registers corresponding to I2C pads should be updated + * according to the bus mode. + */ +void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed); + +/** + * @brief Transmit START or Repeat-START signal on I2C bus + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to transmit START condition when + * the bus becomes free. + */ +static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C) +{ + pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA; +} + +/** + * @brief Reset I2C controller state + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function clears all control/status flags. + */ +static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C) +{ + /* Reset STA, AA and SI. Stop flag should not be cleared as it is a reserved bit */ + pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA | I2C_CON_AA; + +} + +/** + * @brief Transmit a single data byte through the I2C peripheral + * @param pI2C : Pointer to selected I2C peripheral + * @param data : Byte to transmit + * @return Nothing + * @note This function attempts to place a byte into the UART transmit + * FIFO or transmit hold register regard regardless of UART state + * + */ +static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data) +{ + pI2C->DAT = (uint32_t) data; +} + +/** + * @brief Read a single byte data from the I2C peripheral + * @param pI2C : Pointer to selected I2C peripheral + * @return A single byte of data read + * @note This function reads a byte from the I2C receive hold register + * regardless of I2C state. The I2C status should be read first prior + * to using this function. + */ +static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C) +{ + return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK); +} + +/** + * @brief Generate NACK after receiving next byte + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to NACK after receiving next + * byte from slave transmitter. Used before receiving last byte. + */ +static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C) +{ + pI2C->CONCLR = I2C_CON_AA; +} + +/** + * @brief Transmit STOP signal on I2C bus + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to transmit STOP condition. + */ +static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C) +{ + pI2C->CONSET = I2C_CON_STO; +} + +/** + * @brief Force start I2C transmit + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function forces I2C state machine to start transmitting. + * If an uncontrolled source generates a superfluous START or masks + * a STOP condition, then the I2C-bus stays busy indefinitely. If + * the STA flag is set and bus access is not obtained within a + * reasonable amount of time, then a forced access to the I2C-bus is + * possible. This is achieved by setting the STO flag while the STA + * flag is still set. No STOP condition is transmitted. + */ +static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C) +{ + /* check if we are pending on start */ + if (pI2C->CONSET & I2C_CON_STA) { + pI2C->CONSET = I2C_CON_STO; + } + else { + Chip_I2CM_SendStart(pI2C); + } +} + +/** + * @brief Transmit STOP+START signal on I2C bus + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to transmit STOP condition + * followed by a START condition. + */ +static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C) +{ + pI2C->CONSET = I2C_CON_STO | I2C_CON_STA; +} + +/** + * @brief Check if I2C controller state changed + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns 0 if state didn't change + * @note + */ +static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C) +{ + return pI2C->CONSET & I2C_CON_SI; +} + +/** + * @brief Clear state change interrupt flag + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note + */ +static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C) +{ + /* Stop flag should not be cleared as it is a reserved bit */ + pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA; +} + +/** + * @brief Check if I2C bus is free per our controller + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns 0 if busy else a non-zero value. + * @note I2C controller clears STO bit when it sees STOP + * condition after a START condition on the bus. + */ +static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C) +{ + return !(pI2C->CONSET & I2C_CON_STO); +} + +/** + * @brief Get current state of the I2C controller + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns 0 if busy else a non-zero value. + * @note I2C controller clears STO bit when it sees STOP + * condition after a START condition on the bus. + */ +static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C) +{ + return pI2C->STAT & I2C_STAT_CODE_BITMASK; +} + +/** + * @brief Disable I2C interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note + */ +static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C) +{ + pI2C->CONCLR = I2C_CON_I2EN; +} + +/** + * @brief Transfer state change handler handler + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Returns non-zero value on completion of transfer. The @a status + * member of @a xfer structure contains the current status of the + * transfer at the end of the call. + * @note + * The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer() + * routine. + */ +uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @brief Transmit and Receive data in master mode + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Nothing. + * @note + * The parameter @a xfer should have its member @a slaveAddr initialized + * to the 7-Bit slave address to which the master will do the xfer, Bit0 + * to bit6 should have the address and Bit8 is ignored. During the transfer + * no code (like event handler) must change the content of the memory + * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be + * initialized to the memory from which the I2C must pick the data to be + * transferred to slave and the number of bytes to send respectively, similarly + * @a rxBuff and @a rxSz must have pointer to memory where data received + * from slave be stored and the number of data to get from slave respectively. + * Following types of transfers are possible: + * - Write-only transfer: When @a rxSz member of @a xfer is set to 0. + * + * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P + * + * - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options member + * + * S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P + * + * - Read-only transfer: When @a txSz member of @a xfer is set to 0. + * + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P + * + * - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options member + * + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P + * + * - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero. + * + * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P + * + */ +void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @brief Transmit and Receive data in master mode + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Returns non-zero value on successful completion of transfer. + * @note + * This function operates same as Chip_I2CM_Xfer(), but is a blocking call. + */ +uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @brief Write given buffer of data to I2C interface + * @param pI2C : Pointer to selected I2C peripheral + * @param buff : Pointer to buffer to be transmitted + * @param len : Length of the buffer + * @return Returns number of bytes written. + * @note This function is a blocking call. The function generates + * START/repeat-START condition on bus and starts transmitting + * data until transfer finishes or a NACK is received. No + * STOP condition is transmitted on the bus. + * + * S Data0 [A] Data1 [A] ... DataN [A] + */ +uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len); + +/** + * @brief Read data from I2C slave to given buffer + * @param pI2C : Pointer to selected I2C peripheral + * @param buff : Pointer to buffer for data received from I2C slave + * @param len : Length of the buffer + * @return Returns number of bytes read. + * @note This function is a blocking call. The function generates + * START/repeat-START condition on bus and starts reading + * data until requested number of bytes are read. No + * STOP condition is transmitted on the bus. + * + * S [Data0] A [Data1] A ... [DataN] A + */ +uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len); + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __I2C_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/i2s_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/i2s_18xx_43xx.h new file mode 100644 index 0000000000000..89978f5c3df14 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/i2s_18xx_43xx.h @@ -0,0 +1,566 @@ +/* + * @brief LPC18xx/43xx I2S driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2S_18XX_43XX_H_ +#define __I2S_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief I2S DMA request channel define + */ +typedef enum { + I2S_DMA_REQUEST_CHANNEL_1, /*!< DMA request channel 1 */ + I2S_DMA_REQUEST_CHANNEL_2, /*!< DMA request channel 2 */ + I2S_DMA_REQUEST_CHANNEL_NUM,/*!< The number of DMA request channels */ +} I2S_DMA_CHANNEL_T; + +/** + * @brief I2S register block structure + */ +typedef struct { /*!< I2S Structure */ + __IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */ + __IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */ + __O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */ + __I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */ + __I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */ + __IO uint32_t DMA[I2S_DMA_REQUEST_CHANNEL_NUM]; /*!< I2S DMA Configuration Registers. Contains control information for DMA request channels */ + __IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */ + __IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */ + __IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */ + __IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */ + __IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */ + __IO uint32_t TXMODE; /*!< I2S Transmit mode control */ + __IO uint32_t RXMODE; /*!< I2S Receive mode control */ +} LPC_I2S_T; + +/* + * @brief I2S configuration parameter defines + */ +/* I2S Wordwidth bit */ +#define I2S_WORDWIDTH_8 (0UL << 0) /*!< 8 bit Word */ +#define I2S_WORDWIDTH_16 (1UL << 0) /*!< 16 bit word */ +#define I2S_WORDWIDTH_32 (3UL << 0) /*!< 32 bit word */ + +/* I2S Channel bit */ +#define I2S_STEREO (0UL << 2) /*!< Stereo audio */ +#define I2S_MONO (1UL << 2) /*!< Mono audio */ + +/* I2S Master/Slave mode bit */ +#define I2S_MASTER_MODE (0UL << 5) /*!< I2S in master mode */ +#define I2S_SLAVE_MODE (1UL << 5) /*!< I2S in slave mode */ + +/* I2S Stop bit */ +#define I2S_STOP_ENABLE (0UL << 3) /*!< I2S stop enable mask */ +#define I2S_STOP_DISABLE (1UL << 3) /*!< I2S stop disable mask */ + +/* I2S Reset bit */ +#define I2S_RESET_ENABLE (1UL << 4) /*!< I2S reset enable mask */ +#define I2S_RESET_DISABLE (0UL << 4) /*!< I2S reset disable mask */ + +/* I2S Mute bit */ +#define I2S_MUTE_ENABLE (1UL << 15) /*!< I2S mute enable mask */ +#define I2S_MUTE_DISABLE (0UL << 15) /*!< I2S mute disbale mask */ + +/* + * @brief Macro defines for DAO-Digital Audio Output register + */ +/* I2S wordwide - the number of bytes in data*/ +#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAO 8 bit */ +#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAO 16 bit */ +#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAO 32 bit */ +#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3)) + +/* I2S control mono or stereo format */ +#define I2S_DAO_MONO ((uint32_t) (1 << 2)) /*!< DAO mono audio mask */ + +/* I2S control stop mode */ +#define I2S_DAO_STOP ((uint32_t) (1 << 3)) /*!< DAO stop mask */ + +/* I2S control reset mode */ +#define I2S_DAO_RESET ((uint32_t) (1 << 4)) /*!< DAO reset mask */ + +/* I2S control master/slave mode */ +#define I2S_DAO_SLAVE ((uint32_t) (1 << 5)) /*!< DAO slave mode mask */ + +/* I2S word select half period minus one */ +#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6)) /*!< DAO Word select set macro */ +#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAO Word select mask */ + +/* I2S control mute mode */ +#define I2S_DAO_MUTE ((uint32_t) (1 << 15)) /*!< DAO mute mask */ + +/* + * @brief Macro defines for DAI-Digital Audio Input register + */ +/* I2S wordwide - the number of bytes in data*/ +#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAI 8 bit */ +#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAI 16 bit */ +#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAI 32 bit */ +#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3)) /*!< DAI word wide mask */ + +/* I2S control mono or stereo format */ +#define I2S_DAI_MONO ((uint32_t) (1 << 2)) /*!< DAI mono mode mask */ + +/* I2S control stop mode */ +#define I2S_DAI_STOP ((uint32_t) (1 << 3)) /*!< DAI stop bit mask */ + +/* I2S control reset mode */ +#define I2S_DAI_RESET ((uint32_t) (1 << 4)) /*!< DAI reset bit mask */ + +/* I2S control master/slave mode */ +#define I2S_DAI_SLAVE ((uint32_t) (1 << 5)) /*!< DAI slave mode mask */ + +/* I2S word select half period minus one (9 bits)*/ +#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6)) /*!< DAI Word select set macro */ +#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAI Word select mask */ + +/* + * @brief Macro defines for STAT register (Status Feedback register) + */ +#define I2S_STATE_IRQ ((uint32_t) (1))/*!< I2S Status Receive or Transmit Interrupt */ +#define I2S_STATE_DMA1 ((uint32_t) (1 << 1)) /*!< I2S Status Receive or Transmit DMA1 */ +#define I2S_STATE_DMA2 ((uint32_t) (1 << 2)) /*!< I2S Status Receive or Transmit DMA2 */ +#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))/*!< I2S Status Current level of the Receive FIFO (5 bits)*/ +#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16)) /*!< I2S Status Current level of the Transmit FIFO (5 bits)*/ + +/* + * @brief Macro defines for DMA1 register (DMA1 Configuration register) + */ +#define I2S_DMA1_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA1 for I2S receive */ +#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */ +#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */ +#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */ + +/* + * @brief Macro defines for DMA2 register (DMA2 Configuration register) + */ +#define I2S_DMA2_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA2 for I2S receive */ +#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */ +#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */ +#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */ + +/* + * @brief Macro defines for IRQ register (Interrupt Request Control register) + */ + +#define I2S_IRQ_RX_ENABLE ((uint32_t) (1))/*!< I2S control I2S receive interrupt */ +#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control I2S transmit interrupt */ +#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8)) /*!< I2S set the FIFO level on which to create an irq request */ +#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8)) +#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16)) /*!< I2S set the FIFO level on which to create an irq request */ +#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16)) + +/* + * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) + */ +#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Transmit MCLK rate denominator */ +#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Transmit MCLK rate denominator */ +#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Receive MCLK rate denominator */ +#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Receive MCLK rate denominator */ + +/* + * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) + */ +#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F)) +#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F)) + +/* + * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) + */ +#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Transmit select clock source (2 bits)*/ +#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Transmit control 4-pin mode */ +#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Transmit control the TX_MCLK output */ +#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Receive select clock source */ +#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Receive control 4-pin mode */ +#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Receive control the TX_MCLK output */ + +/** + * @brief I2S Audio Format Structure + */ +typedef struct { + uint32_t SampleRate; /*!< Sample Rate */ + uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */ + uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */ +} I2S_AUDIO_FORMAT_T; + +/** + * @brief Initialize for I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +void Chip_I2S_Init(LPC_I2S_T *pI2S); + +/** + * @brief Shutdown I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value + */ +void Chip_I2S_DeInit(LPC_I2S_T *pI2S); + +/** + * @brief Send a 32-bit data to TXFIFO for transmition + * @param pI2S : The base of I2S peripheral on the chip + * @param data : Data to be transmited + * @return Nothing + * @note The function writes to TXFIFO without checking any condition. + */ +STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data) +{ + pI2S->TXFIFO = data; +} + +/** + * @brief Get received data from RXFIFO + * @param pI2S : The base of I2S peripheral on the chip + * @return Data received in RXFIFO + * @note The function reads from RXFIFO without checking any condition. + */ +STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_T *pI2S) +{ + return pI2S->RXFIFO; +} + +/** + * @brief Start transmit data + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_TxStart(LPC_I2S_T *pI2S) +{ + pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE); +} + +/** + * @brief Start receive data + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_RxStart(LPC_I2S_T *pI2S) +{ + pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP); +} + +/** + * @brief Disables accesses on FIFOs, places the transmit channel in mute mode + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_TxPause(LPC_I2S_T *pI2S) +{ + pI2S->DAO |= I2S_DAO_STOP; +} + +/** + * @brief Disables accesses on FIFOs, places the transmit channel in mute mode + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_RxPause(LPC_I2S_T *pI2S) +{ + pI2S->DAI |= I2S_DAI_STOP; +} + +/** + * @brief Mute the Transmit channel + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note The data output from I2S transmit channel is always zeroes + */ +STATIC INLINE void Chip_I2S_EnableMute(LPC_I2S_T *pI2S) +{ + pI2S->DAO |= I2S_DAO_MUTE; +} + +/** + * @brief Un-Mute the I2S channel + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_DisableMute(LPC_I2S_T *pI2S) +{ + pI2S->DAO &= ~I2S_DAO_MUTE; +} + +/** + * @brief Stop I2S asynchronously + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note Pause, resets the transmit channel and FIFO asynchronously + */ +STATIC INLINE void Chip_I2S_TxStop(LPC_I2S_T *pI2S) +{ + pI2S->DAO &= ~I2S_DAO_MUTE; + pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET; +} + +/** + * @brief Stop I2S asynchronously + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note Pause, resets the transmit channel and FIFO asynchronously + */ +STATIC INLINE void Chip_I2S_RxStop(LPC_I2S_T *pI2S) +{ + pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET; +} + +/** + * @brief Sets the I2S receive channel in slave mode + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note 4 pin mode must be enabled on appropriate channel. + * Must be called after each Chip_I2S_TxModeConfig call if + * slave mode is needed. + */ +STATIC INLINE void Chip_I2S_RxSlave(LPC_I2S_T *pI2S) +{ + pI2S->DAI |= I2S_SLAVE_MODE; +} + +/** + * @brief Sets the I2S transmit channel in slave mode + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * @note 4 pin mode must be enabled on appropriate channel. + * Must be called after each Chip_I2S_TxModeConfig call if + * slave mode is needed. + */ +STATIC INLINE void Chip_I2S_TxSlave(LPC_I2S_T *pI2S) +{ + pI2S->DAO |= I2S_SLAVE_MODE; +} + +/** + * @brief Set the I2S transmit mode + * @param pI2S : The base of I2S peripheral on the chip + * @param clksel : Clock source selection for the receive bit clock divider + * @param fpin : Receive 4-pin mode selection + * @param mcena : Enable for the RX_MCLK output + * @return Nothing + * @note In addition to master and slave modes, which are independently configurable for + * the transmitter and the receiver, several different clock sources are possible, + * including variations that share the clock and/or WS between the transmitter and + * receiver. It also allows using I2S with fewer pins, typically four. + */ +STATIC INLINE void Chip_I2S_TxModeConfig(LPC_I2S_T *pI2S, + uint32_t clksel, + uint32_t fpin, + uint32_t mcena) +{ + pI2S->TXMODE = clksel | fpin | mcena; +} + +/** + * @brief Set the I2S receive mode + * @param pI2S : The base of I2S peripheral on the chip + * @param clksel : Clock source selection for the receive bit clock divider + * @param fpin : Receive 4-pin mode selection + * @param mcena : Enable for the RX_MCLK output + * @return Nothing + * @note In addition to master and slave modes, which are independently configurable for + * the transmitter and the receiver, several different clock sources are possible, + * including variations that share the clock and/or WS between the transmitter and + * receiver. It also allows using I2S with fewer pins, typically four. + */ +STATIC INLINE void Chip_I2S_RxModeConfig(LPC_I2S_T *pI2S, + uint32_t clksel, + uint32_t fpin, + uint32_t mcena) +{ + pI2S->RXMODE = clksel | fpin | mcena; +} + +/** + * @brief Get the current level of the Transmit FIFO + * @param pI2S : The base of I2S peripheral on the chip + * @return Current level of the Transmit FIFO + */ +STATIC INLINE uint8_t Chip_I2S_GetTxLevel(LPC_I2S_T *pI2S) +{ + return (pI2S->STATE >> 16) & 0xF; +} + +/** + * @brief Get the current level of the Receive FIFO + * @param pI2S : The base of I2S peripheral on the chip + * @return Current level of the Receive FIFO + */ +STATIC INLINE uint8_t Chip_I2S_GetRxLevel(LPC_I2S_T *pI2S) +{ + return (pI2S->STATE >> 8) & 0xF; +} + +/** + * @brief Set the clock frequency for I2S interface + * @param pI2S : The base of I2S peripheral on the chip + * @param div : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface + * @return Nothing + * @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used. + * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz + */ +STATIC INLINE void Chip_I2S_SetTxBitRate(LPC_I2S_T *pI2S, uint32_t div) +{ + pI2S->TXBITRATE = div; +} + +/** + * @brief Set the clock frequency for I2S interface + * @param pI2S : The base of I2S peripheral on the chip + * @param div : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface + * @return Nothing + * @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used. + * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz + */ +STATIC INLINE void Chip_I2S_SetRxBitRate(LPC_I2S_T *pI2S, uint32_t div) +{ + pI2S->RXBITRATE = div; +} + +/** + * @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK + * @param pI2S : The base of I2S peripheral on the chip + * @param xDiv : I2S transmit MCLK rate numerator + * @param yDiv : I2S transmit MCLK rate denominator + * @return Nothing + * @note Values of the numerator (X) and the denominator (Y) must be chosen to + * produce a frequency twice that desired for the transmitter MCLK, which + * must be an integer multiple of the transmitter bit clock rate. + * The equation for the fractional rate generator is: + * MCLK = PCLK * (X/Y) /2 + * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be + * greater than or equal to X. + */ +STATIC INLINE void Chip_I2S_SetTxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv) +{ + pI2S->TXRATE = yDiv | (xDiv << 8); +} + +/** + * @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK + * @param pI2S : The base of I2S peripheral on the chip + * @param xDiv : I2S transmit MCLK rate numerator + * @param yDiv : I2S transmit MCLK rate denominator + * @return Nothing + * @note Values of the numerator (X) and the denominator (Y) must be chosen to + * produce a frequency twice that desired for the transmitter MCLK, which + * must be an integer multiple of the transmitter bit clock rate. + * The equation for the fractional rate generator is: + * MCLK = PCLK * (X/Y) /2 + * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be + * greater than or equal to X. + */ +STATIC INLINE void Chip_I2S_SetRxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv) +{ + pI2S->RXRATE = yDiv | (xDiv << 8); +} + +/** + * @brief Configure I2S for Audio Format input + * @param pI2S : The base I2S peripheral on the chip + * @param format : Audio Format + * @return SUCCESS or ERROR + */ +Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format); + +/** + * @brief Configure I2S for Audio Format input + * @param pI2S : The base I2S peripheral on the chip + * @param format : Audio Format + * @return SUCCESS or ERROR + */ +Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format); + +/** + * @brief Enable/Disable Interrupt with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param newState : ENABLE or DISABLE interrupt + * @param depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth); + +/** + * @brief Enable/Disable Interrupt with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param newState : ENABLE or DISABLE interrupt + * @param depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth); + +/** + * @brief Enable/Disable DMA with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param dmaNum : Should be + * - I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1 + * - I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2 + * @param newState : ENABLE or DISABLE interrupt + * @param depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth); + +/** + * @brief Enable/Disable DMA with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param dmaNum : Should be + * - I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1 + * - I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2 + * @param newState : ENABLE or DISABLE interrupt + * @param depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/iap.h b/ports/lpc/chips/lpc_chip_43xx/inc/iap.h new file mode 100644 index 0000000000000..556648a2744c8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/iap.h @@ -0,0 +1,190 @@ +/* + * @brief Common IAP support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __IAP_H_ +#define __IAP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes + * @ingroup CHIP_Common + * @{ + */ + +/* IAP command definitions */ +#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */ +#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */ +#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */ +#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */ +#define IAP_REPID_CMD 54 /*!< Read PartID command */ +#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */ +#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */ +#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */ +#define IAP_READ_UID_CMD 58 /*!< Read UID */ +#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */ +#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */ +#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */ + +/* IAP response definitions */ +#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */ +#define IAP_INVALID_COMMAND 1 /*!< Invalid command */ +#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */ +#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */ +#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */ +#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */ +#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */ +#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */ +#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */ +#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */ +#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */ +#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */ +#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */ +#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */ +#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */ +#define IAP_CMD_LOCKED 15 /*!< Command is locked */ +#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */ +#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */ +#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */ +#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ + +/* IAP_ENTRY API function type */ +typedef void (*IAP_ENTRY_T)(unsigned int[], unsigned int[]); + +/** + * @brief Prepare sector for write operation + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Status code to indicate the command is executed successfully or not + * @note This command must be executed before executing "Copy RAM to flash" + * or "Erase Sector" command. + * The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector); + +/** + * @brief Copy RAM to flash + * @param dstAdd : Destination FLASH address where data bytes are to be written + * @param srcAdd : Source RAM address where data bytes are to be read + * @param byteswrt : Number of bytes to be written + * @return Status code to indicate the command is executed successfully or not + * @note The addresses should be a 256 byte boundary and the number of bytes + * should be 256 | 512 | 1024 | 4096 + */ +uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt); + +/** + * @brief Erase sector + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Status code to indicate the command is executed successfully or not + * @note The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector); + +/** + * @brief Blank check a sector or multiples sector of on-chip flash memory + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK + * @note The end sector must be greater than or equal to start sector number + */ +// FIXME - There are two return value (result[0] & result[1] +// Result0:Offset of the first non blank word location if the Status Code is +// SECTOR_NOT_BLANK. +// Result1:Contents of non blank word location. +uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector); + +/** + * @brief Read part identification number + * @return Part identification number + */ +uint32_t Chip_IAP_ReadPID(void); + +/** + * @brief Read boot code version number + * @return Boot code version number + */ +uint32_t Chip_IAP_ReadBootCode(void); + +/** + * @brief Compare the memory contents at two locations + * @param dstAdd : Destination of the RAM address of data bytes to be compared + * @param srcAdd : Source of the RAM address of data bytes to be compared + * @param bytescmp : Number of bytes to be compared + * @return Offset of the first mismatch of the status code is COMPARE_ERROR + * @note The addresses should be a word boundary and number of bytes should be + * a multiply of 4 + */ +uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp); + +/** + * @brief IAP reinvoke ISP to invoke the bootloader in ISP mode + * @return none + */ +uint8_t Chip_IAP_ReinvokeISP(void); + +/** + * @brief Read the unique ID + * @return Status code to indicate the command is executed successfully or not + */ +uint32_t Chip_IAP_ReadUID(uint32_t* uid); + +/** + * @brief Erase a page or multiple papers of on-chip flash memory + * @param strPage : Start page number + * @param endPage : End page number + * @return Status code to indicate the command is executed successfully or not + * @note The page number must be greater than or equal to start page number + */ +// FIXME - There are four return value +// Result0:The first 32-bit word (at the lowest address) +// Result1:The second 32-bit word. +// Result2:The third 32-bit word. +// Result3:The fourth 32-bit word. +uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IAP_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h new file mode 100644 index 0000000000000..93f2eeef153f5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h @@ -0,0 +1,217 @@ +/* + * @brief Common IAP support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __IAP_H_ +#define __IAP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IAP_18XX_43XX CHIP: LPC18xx/43xx Flash IAP driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/* IAP command definitions */ +#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */ +#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */ +#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */ +#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */ +#define IAP_REPID_CMD 54 /*!< Read PartID command */ +#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */ +#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */ +#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */ +#define IAP_READ_UID_CMD 58 /*!< Read UID */ +#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */ +#define IAP_SET_BOOT_FLASH 60 /*!< Set active boot flash bank */ +#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */ +#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */ + +/* IAP response definitions */ +#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */ +#define IAP_INVALID_COMMAND 1 /*!< Invalid command */ +#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */ +#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */ +#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */ +#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */ +#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */ +#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */ +#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */ +#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */ +#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */ +#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */ +#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */ +#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */ +#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */ +#define IAP_CMD_LOCKED 15 /*!< Command is locked */ +#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */ +#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */ +#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */ +#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ + +/* IAP_ENTRY API function type */ +typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]); + +/** + * @brief Initialize IAP + * @return Status code to indicate the command is executed successfully or not + */ +uint8_t Chip_IAP_Init(void); + +/** + * @brief Prepare sector for write operation + * @param strSector : Start sector number + * @param endSector : End sector number + * @param bankNum : Flash Bank number + * @return Status code to indicate the command is executed successfully or not + * @note This command must be executed before executing "Copy RAM to flash" + * or "Erase Sector" command. + * The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector, uint8_t bankNum); + +/** + * @brief Copy RAM to flash + * @param dstAdd : Destination flash address where data bytes are to be written + * @param srcAdd : Source flash address where data bytes are to be read + * @param byteswrt : Number of bytes to be written + * @return Status code to indicate the command is executed successfully or not + * @note The addresses should be a 256 byte boundary and the number of bytes + * should be 256 | 512 | 1024 | 4096 + */ +uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt); + +/** + * @brief Erase sector + * @param strSector : Start sector number + * @param endSector : End sector number + * @param bankNum : Flash Bank number + * @return Status code to indicate the command is executed successfully or not + * @note The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector, uint8_t bankNum); + +/** + * @brief Blank check a sector or multiples sector of on-chip flash memory + * @param strSector : Start sector number + * @param endSector : End sector number + * @param bankNum : Flash Bank number + * @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK + * @note The end sector must be greater than or equal to start sector number + */ +// FIXME - There are two return value (result[0] & result[1] +// Result0:Offset of the first non blank word location if the Status Code is +// SECTOR_NOT_BLANK. +// Result1:Contents of non blank word location. +uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector, uint8_t bankNum); + +/** + * @brief Read part identification number + * @return Part identification number + */ +uint32_t Chip_IAP_ReadPID(void); + +/** + * @brief Read boot code version number + * @return Boot code version number + */ +uint8_t Chip_IAP_ReadBootCode(void); + +/** + * @brief Compare the memory contents at two locations + * @param dstAdd : Destination of the RAM address of data bytes to be compared + * @param srcAdd : Source of the RAM address of data bytes to be compared + * @param bytescmp : Number of bytes to be compared + * @return Offset of the first mismatch of the status code is COMPARE_ERROR + * @note The addresses should be a word boundary and number of bytes should be + * a multiply of 4 + */ +uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp); + +/** + * @brief IAP reinvoke ISP to invoke the bootloader in ISP mode + * @return none + */ +uint8_t Chip_IAP_ReinvokeISP(void); + +/** + * @brief Read the unique ID + * @param uid[] : Array of uint32_t with 4 elements to return the UID + * @return Status code to indicate the command is executed successfully or not + */ +uint32_t Chip_IAP_ReadUID(uint32_t uid[]); + +/** + * @brief Erase a page or multiple papers of on-chip flash memory + * @param strPage : Start page number + * @param endPage : End page number + * @return Status code to indicate the command is executed successfully or not + * @note The page number must be greater than or equal to start page number + */ +// FIXME - There are four return value +// Result0:The first 32-bit word (at the lowest address) +// Result1:The second 32-bit word. +// Result2:The third 32-bit word. +// Result3:The fourth 32-bit word. +uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage); + +/** + * @brief Set active boot flash bank + * @param bankNum : Flash bank number + * @return Status code to indicate the command is executed successfully or not + * @note Enable booting from the indicated flash unit by inserting a valid + * signature and invalidating the other flash unit + */ +uint8_t Chip_IAP_SetBootFlashBank(uint8_t bankNum); + +/** + * @brief Initialize the IAP command interface + * @return IAP_CMD_SUCCESS on success + * @note On parts with flash this API must be called before using IAP interface + */ +uint8_t Chip_IAP_init(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IAP_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/lcd_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/lcd_18xx_43xx.h new file mode 100644 index 0000000000000..0647fc9eedaaa --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/lcd_18xx_43xx.h @@ -0,0 +1,389 @@ +/* + * @brief LPC18xx/43xx LCD chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LCD_18XX_43XX_H_ +#define __LCD_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief LCD Controller register block structure + */ +typedef struct { /*!< LCD Structure */ + __IO uint32_t TIMH; /*!< Horizontal Timing Control register */ + __IO uint32_t TIMV; /*!< Vertical Timing Control register */ + __IO uint32_t POL; /*!< Clock and Signal Polarity Control register */ + __IO uint32_t LE; /*!< Line End Control register */ + __IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */ + __IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */ + __IO uint32_t CTRL; /*!< LCD Control register */ + __IO uint32_t INTMSK; /*!< Interrupt Mask register */ + __I uint32_t INTRAW; /*!< Raw Interrupt Status register */ + __I uint32_t INTSTAT; /*!< Masked Interrupt Status register */ + __O uint32_t INTCLR; /*!< Interrupt Clear register */ + __I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */ + __I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */ + __I uint32_t RESERVED0[115]; + __IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */ + __I uint32_t RESERVED1[256]; + __IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */ + __IO uint32_t CRSR_CTRL; /*!< Cursor Control register */ + __IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */ + __IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */ + __IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */ + __IO uint32_t CRSR_XY; /*!< Cursor XY Position register */ + __IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */ + __I uint32_t RESERVED2[2]; + __IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */ + __O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */ + __I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */ + __I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */ +} LPC_LCD_T; + +/** + * @brief LCD Palette entry format + */ +typedef struct { + uint32_t Rl : 5; + uint32_t Gl : 5; + uint32_t Bl : 5; + uint32_t Il : 1; + uint32_t Ru : 5; + uint32_t Gu : 5; + uint32_t Bu : 5; + uint32_t Iu : 1; +} LCD_PALETTE_ENTRY_T; + +/** + * @brief LCD Panel type + */ +typedef enum { + LCD_TFT = 0x02, /*!< standard TFT */ + LCD_MONO_4 = 0x01, /*!< 4-bit STN mono */ + LCD_MONO_8 = 0x05, /*!< 8-bit STN mono */ + LCD_CSTN = 0x00 /*!< color STN */ +} LCD_PANEL_OPT_T; + +/** + * @brief LCD Color Format + */ +typedef enum { + LCD_COLOR_FORMAT_RGB = 0, + LCD_COLOR_FORMAT_BGR +} LCD_COLOR_FORMAT_OPT_T; + +/** LCD Interrupt control mask register bits */ +#define LCD_INTMSK_FUFIM 0x2 /*!< FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM 0x4 /*!< LCD next base address update interrupt enable */ +#define LCD_INTMSK_VCOMPIM 0x8 /*!< Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM 0x10 /*!< AHB master error interrupt enable */ + +#define CLCDC_LCDCTRL_ENABLE _BIT(0) /*!< LCD control enable bit */ +#define CLCDC_LCDCTRL_PWR _BIT(11) /*!< LCD control power enable bit */ + +/** + * @brief A structure for LCD Configuration + */ +typedef struct { + uint8_t HBP; /*!< Horizontal back porch in clocks */ + uint8_t HFP; /*!< Horizontal front porch in clocks */ + uint8_t HSW; /*!< HSYNC pulse width in clocks */ + uint16_t PPL; /*!< Pixels per line */ + uint8_t VBP; /*!< Vertical back porch in clocks */ + uint8_t VFP; /*!< Vertical front porch in clocks */ + uint8_t VSW; /*!< VSYNC pulse width in clocks */ + uint16_t LPP; /*!< Lines per panel */ + uint8_t IOE; /*!< Invert output enable, 1 = invert */ + uint8_t IPC; /*!< Invert panel clock, 1 = invert */ + uint8_t IHS; /*!< Invert HSYNC, 1 = invert */ + uint8_t IVS; /*!< Invert VSYNC, 1 = invert */ + uint8_t ACB; /*!< AC bias frequency in clocks (not used) */ + uint8_t BPP; /*!< Maximum bits per pixel the display supports */ + LCD_PANEL_OPT_T LCD; /*!< LCD panel type */ + LCD_COLOR_FORMAT_OPT_T color_format; /*!CTRL |= CLCDC_LCDCTRL_PWR; + for (i = 0; i < 1000000; i++) {} + pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE; +} + +/** + * @brief Power-off the LCD Panel (power pin) + * @param pLCD : The base of LCD peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_LCD_PowerOff(LPC_LCD_T *pLCD) +{ + volatile int i; + pLCD->CTRL &= ~CLCDC_LCDCTRL_PWR; + for (i = 0; i < 1000000; i++) {} + pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE; +} + +/** + * @brief Enable/Disable the LCD Controller + * @param pLCD : The base of LCD peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_LCD_Enable(LPC_LCD_T *pLCD) +{ + pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE; +} + +/** + * @brief Enable/Disable the LCD Controller + * @param pLCD : The base of LCD peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_LCD_Disable(LPC_LCD_T *pLCD) +{ + pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE; +} + +/** + * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame + * Buffer for Dual Panel + * @param pLCD : The base of LCD peripheral on the chip + * @param buffer : address of buffer + * @return None + */ +STATIC INLINE void Chip_LCD_SetUPFrameBuffer(LPC_LCD_T *pLCD, void *buffer) +{ + pLCD->UPBASE = (uint32_t) buffer; +} + +/** + * @brief Set LCD Lower Panel Frame Buffer for Dual Panel + * @param pLCD : The base of LCD peripheral on the chip + * @param buffer : address of buffer + * @return None + */ +STATIC INLINE void Chip_LCD_SetLPFrameBuffer(LPC_LCD_T *pLCD, void *buffer) +{ + pLCD->LPBASE = (uint32_t) buffer; +} + +/** + * @brief Configure Cursor + * @param pLCD : The base of LCD peripheral on the chip + * @param cursor_size : specify size of cursor + * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels + * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels + * @param sync : cursor sync mode + * - TRUE :cursor sync to the frame sync pulse + * - FALSE :cursor async mode + * @return None + */ +void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync); + +/** + * @brief Enable Cursor + * @param pLCD : The base of LCD peripheral on the chip + * @param cursor_num : specify number of cursor is going to be written + * this param must < 4 + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_Enable(LPC_LCD_T *pLCD, uint8_t cursor_num) +{ + pLCD->CRSR_CTRL = (cursor_num << 4) | 1; +} + +/** + * @brief Disable Cursor + * @param pLCD : The base of LCD peripheral on the chip + * @param cursor_num : specify number of cursor is going to be written + * this param must < 4 + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_Disable(LPC_LCD_T *pLCD, uint8_t cursor_num) +{ + pLCD->CRSR_CTRL = (cursor_num << 4); +} + +/** + * @brief Load Cursor Palette + * @param pLCD : The base of LCD peripheral on the chip + * @param palette_color : cursor palette 0 value + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(LPC_LCD_T *pLCD, uint32_t palette_color) +{ + /* 7:0 - Red + 15:8 - Green + 23:16 - Blue + 31:24 - Not used*/ + pLCD->CRSR_PAL0 = (uint32_t) palette_color; +} + +/** + * @brief Load Cursor Palette + * @param pLCD : The base of LCD peripheral on the chip + * @param palette_color : cursor palette 1 value + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(LPC_LCD_T *pLCD, uint32_t palette_color) +{ + /* 7:0 - Red + 15:8 - Green + 23:16 - Blue + 31:24 - Not used*/ + pLCD->CRSR_PAL1 = (uint32_t) palette_color; +} + +/** + * @brief Set Cursor Position + * @param pLCD : The base of LCD peripheral on the chip + * @param x : horizontal position + * @param y : vertical position + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_SetPos(LPC_LCD_T *pLCD, uint16_t x, uint16_t y) +{ + pLCD->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16); +} + +/** + * @brief Set Cursor Clipping Position + * @param pLCD : The base of LCD peripheral on the chip + * @param x : horizontal position, should be in range: 0..63 + * @param y : vertical position, should be in range: 0..63 + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_SetClip(LPC_LCD_T *pLCD, uint16_t x, uint16_t y) +{ + pLCD->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8); +} + +/** + * @brief Enable Controller Interrupt + * @param pLCD : The base of LCD peripheral on the chip + * @param ints : OR'ed interrupt bits to enable + * @return None + */ +STATIC INLINE void Chip_LCD_EnableInts(LPC_LCD_T *pLCD, uint32_t ints) +{ + pLCD->INTMSK = ints; +} + +/** + * @brief Disable Controller Interrupt + * @param pLCD : The base of LCD peripheral on the chip + * @param ints : OR'ed interrupt bits to disable + * @return None + */ +STATIC INLINE void Chip_LCD_DisableInts(LPC_LCD_T *pLCD, uint32_t ints) +{ + pLCD->INTMSK = pLCD->INTMSK & ~(ints); +} + +/** + * @brief Clear Controller Interrupt + * @param pLCD : The base of LCD peripheral on the chip + * @param ints : OR'ed interrupt bits to clear + * @return None + */ +STATIC INLINE void Chip_LCD_ClearInts(LPC_LCD_T *pLCD, uint32_t ints) +{ + pLCD->INTCLR = pLCD->INTMSK & (ints); +} + +/** + * @brief Write Cursor Image into Internal Cursor Image Buffer + * @param pLCD : The base of LCD peripheral on the chip + * @param cursor_num : Cursor index + * @param Image : Pointer to image data + * @return None + */ +void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image); + +/** + * @brief Load LCD Palette + * @param pLCD : The base of LCD peripheral on the chip + * @param palette : Address of palette table to load + * @return None + */ +void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __LCD_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/lpc_types.h b/ports/lpc/chips/lpc_chip_43xx/inc/lpc_types.h new file mode 100644 index 0000000000000..79380696db99d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/lpc_types.h @@ -0,0 +1,228 @@ +/* + * @brief Common types used in LPC functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_TYPES_H_ +#define __LPC_TYPES_H_ + +#include +#include + +/** @defgroup LPC_Types CHIP: LPC Common Types + * @ingroup CHIP_Common + * @{ + */ + +/** @defgroup LPC_Types_Public_Types LPC Public Types + * @{ + */ + +/** + * @brief Boolean Type definition + */ +//typedef enum {FALSE = 0, TRUE = !FALSE} Bool; // in earlier versions +#ifndef TRUE +#define TRUE (1) +#endif +#ifndef FALSE +#define FALSE (0) +#endif + +/** + * @brief Boolean Type definition + */ +#if !defined(__cplusplus) +// typedef enum {false = 0, true = !false} bool; +#endif + +/** + * @brief Flag Status and Interrupt Flag Status type definition + */ +typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; +#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET)) + +/** + * @brief Functional State Definition + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE)) + +/** + * @ Status type definition + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; + +/** + * Read/Write transfer type mode (Block or non-block) + */ +typedef enum { + NONE_BLOCKING = 0, /**< None Blocking type */ + BLOCKING, /**< Blocking type */ +} TRANSFER_BLOCK_T; + +/** Pointer to Function returning Void (any number of parameters) */ +typedef void (*PFV)(); + +/** Pointer to Function returning int32_t (any number of parameters) */ +typedef int32_t (*PFI)(); + +/** + * @} + */ + +/** @defgroup LPC_Types_Public_Macros LPC Public Macros + * @{ + */ + +/* _BIT(n) sets the bit at position "n" + * _BIT(n) is intended to be used in "OR" and "AND" expressions: + * e.g., "(_BIT(3) | _BIT(7))". + */ +#undef _BIT +/* Set bit macro */ +#define _BIT(n) (1 << (n)) + +/* _SBF(f,v) sets the bit field starting at position "f" to value "v". + * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: + * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" + */ +#undef _SBF +/* Set bit field macro */ +#define _SBF(f, v) ((v) << (f)) + +/* _BITMASK constructs a symbol with 'field_width' least significant + * bits set. + * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF + * The symbol is intended to be used to limit the bit field width + * thusly: + * = (any_expression) & _BITMASK(x), where 0 < x <= 32. + * If "any_expression" results in a value that is larger than can be + * contained in 'x' bits, the bits above 'x - 1' are masked off. When + * used with the _SBF example above, the example would be written: + * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) + * This ensures that the value written to a_reg is no wider than + * 16 bits, and makes the code easier to read and understand. + */ +#undef _BITMASK +/* Bitmask creation macro */ +#define _BITMASK(field_width) ( _BIT(field_width) - 1) + +/* NULL pointer */ +#ifndef NULL +#define NULL ((void *) 0) +#endif + +/* Number of elements in an array */ +#define NELEMENTS(array) (sizeof(array) / sizeof(array[0])) + +/* Static data/function define */ +#define STATIC static +/* External data/function define */ +#define EXTERN extern + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/** + * @} + */ + +/* Old Type Definition compatibility */ +/** @addtogroup LPC_Types_Public_Types + * @{ + */ + +/** LPC type for character type */ +typedef char CHAR; + +/** LPC type for 8 bit unsigned value */ +typedef uint8_t UNS_8; + +/** LPC type for 8 bit signed value */ +typedef int8_t INT_8; + +/** LPC type for 16 bit unsigned value */ +typedef uint16_t UNS_16; + +/** LPC type for 16 bit signed value */ +typedef int16_t INT_16; + +/** LPC type for 32 bit unsigned value */ +typedef uint32_t UNS_32; + +/** LPC type for 32 bit signed value */ +typedef int32_t INT_32; + +/** LPC type for 64 bit signed value */ +typedef int64_t INT_64; + +/** LPC type for 64 bit unsigned value */ +typedef uint64_t UNS_64; + +#ifdef __CODE_RED +#define BOOL_32 bool +#define BOOL_16 bool +#define BOOL_8 bool +#else +/** 32 bit boolean type */ +typedef bool BOOL_32; + +/** 16 bit boolean type */ +typedef bool BOOL_16; + +/** 8 bit boolean type */ +typedef bool BOOL_8; +#endif + +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __LPC_TYPES_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h new file mode 100644 index 0000000000000..cc20b6663f4d2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h @@ -0,0 +1,86 @@ +/* + * @brief LPC18xx/43xx Motor Control PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __MCPWM_18XX_43XX_H_ +#define __MCPWM_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup MCPWM_18XX_43XX CHIP: LPC18xx/43xx Motor Control PWM driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Motor Control PWM register block structure + */ +typedef struct { /*!< MCPWM Structure */ + __I uint32_t CON; /*!< PWM Control read address */ + __O uint32_t CON_SET; /*!< PWM Control set address */ + __O uint32_t CON_CLR; /*!< PWM Control clear address */ + __I uint32_t CAPCON; /*!< Capture Control read address */ + __O uint32_t CAPCON_SET; /*!< Capture Control set address */ + __O uint32_t CAPCON_CLR; /*!< Event Control clear address */ + __IO uint32_t TC[3]; /*!< Timer Counter register */ + __IO uint32_t LIM[3]; /*!< Limit register */ + __IO uint32_t MAT[3]; /*!< Match register */ + __IO uint32_t DT; /*!< Dead time register */ + __IO uint32_t CCP; /*!< Communication Pattern register */ + __I uint32_t CAP[3]; /*!< Capture register */ + __I uint32_t INTEN; /*!< Interrupt Enable read address */ + __O uint32_t INTEN_SET; /*!< Interrupt Enable set address */ + __O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */ + __I uint32_t CNTCON; /*!< Count Control read address */ + __O uint32_t CNTCON_SET; /*!< Count Control set address */ + __O uint32_t CNTCON_CLR; /*!< Count Control clear address */ + __I uint32_t INTF; /*!< Interrupt flags read address */ + __O uint32_t INTF_SET; /*!< Interrupt flags set address */ + __O uint32_t INTF_CLR; /*!< Interrupt flags clear address */ + __O uint32_t CAP_CLR; /*!< Capture clear address */ +} LPC_MCPWM_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MCPWM_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/otp_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/otp_18xx_43xx.h new file mode 100644 index 0000000000000..c0b800137adf3 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/otp_18xx_43xx.h @@ -0,0 +1,150 @@ +/* + * @brief LPC18xx/43xx OTP Controller driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __OTP_18XX_43XX_H_ +#define __OTP_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup OTP_18XX_43XX CHIP: LPC18xx/43xx OTP Controller driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief OTP Register block + */ +typedef struct { + __IO uint32_t OTP0_0; /*!< (@ 0x40045000) OTP content */ + __IO uint32_t OTP0_1; /*!< (@ 0x40045004) OTP content */ + __IO uint32_t OTP0_2; /*!< (@ 0x40045008) OTP content */ + __IO uint32_t OTP0_3; /*!< (@ 0x4004500C) OTP content */ + __IO uint32_t OTP1_0; /*!< (@ 0x40045010) OTP content */ + __IO uint32_t OTP1_1; /*!< (@ 0x40045014) OTP content */ + __IO uint32_t OTP1_2; /*!< (@ 0x40045018) OTP content */ + __IO uint32_t OTP1_3; /*!< (@ 0x4004501C) OTP content */ + __IO uint32_t OTP2_0; /*!< (@ 0x40045020) OTP content */ + __IO uint32_t OTP2_1; /*!< (@ 0x40045024) OTP content */ + __IO uint32_t OTP2_2; /*!< (@ 0x40045028) OTP content */ + __IO uint32_t OTP2_3; /*!< (@ 0x4004502C) OTP content */ + __IO uint32_t OTP3_0; /*!< (@ 0x40045030) OTP content */ + __IO uint32_t OTP3_1; /*!< (@ 0x40045034) OTP content */ + __IO uint32_t OTP3_2; /*!< (@ 0x40045038) OTP content */ + __IO uint32_t OTP3_3; /*!< (@ 0x4004503C) OTP content */ +} LPC_OTP_T; + +/** + * @brief OTP Boot Source selection used in Chip driver + */ +typedef enum CHIP_OTP_BOOT_SRC { + CHIP_OTP_BOOTSRC_PINS, /*!< Boot source - External pins */ + CHIP_OTP_BOOTSRC_UART0, /*!< Boot source - UART0 */ + CHIP_OTP_BOOTSRC_SPIFI, /*!< Boot source - EMC 8-bit memory */ + CHIP_OTP_BOOTSRC_EMC8, /*!< Boot source - EMC 16-bit memory */ + CHIP_OTP_BOOTSRC_EMC16, /*!< Boot source - EMC 32-bit memory */ + CHIP_OTP_BOOTSRC_EMC32, /*!< Boot source - EMC 32-bit memory */ + CHIP_OTP_BOOTSRC_USB0, /*!< Boot source - DFU USB0 boot */ + CHIP_OTP_BOOTSRC_USB1, /*!< Boot source - DFU USB1 boot */ + CHIP_OTP_BOOTSRC_SPI, /*!< Boot source - SPI boot */ + CHIP_OTP_BOOTSRC_UART3 /*!< Boot source - UART3 */ +} CHIP_OTP_BOOT_SRC_T; + +/** + * @brief Initialize for OTP Controller functions + * @return Status of Otp_Init function + * This function will initialise all the OTP driver function pointers + * and call the ROM OTP Initialisation function. + */ +uint32_t Chip_OTP_Init(void); + +/** + * @brief Program boot source in OTP Controller + * @param BootSrc : Boot Source enum value + * @return Status + */ +uint32_t Chip_OTP_ProgBootSrc(CHIP_OTP_BOOT_SRC_T BootSrc); + +/** + * @brief Program the JTAG bit in OTP Controller + * @return Status + */ +uint32_t Chip_OTP_ProgJTAGDis(void); + +/** + * @brief Program USB ID in OTP Controller + * @param ProductID : USB Product ID + * @param VendorID : USB Vendor ID + * @return Status + */ +uint32_t Chip_OTP_ProgUSBID(uint32_t ProductID, uint32_t VendorID); + +/** + * @brief Program OTP GP Word memory + * @param WordNum : Word Number (Select word 0 or word 1 or word 2) + * @param Data : Data value + * @param Mask : Mask value + * @return Status + * This function available in devices which are not AES capable + */ +uint32_t Chip_OTP_ProgGPWord(uint32_t WordNum, uint32_t Data, uint32_t Mask); + +/** + * @brief Program AES Key + * @param KeyNum : Key Number (Select 0 or 1) + * @param key : Pointer to AES Key (16 bytes required) + * @return Status + * This function available in devices which are AES capable + */ +uint32_t Chip_OTP_ProgKey(uint32_t KeyNum, uint8_t *key); + +/** + * @brief Generate Random Number using HW Random Number Generator + * @return Error code of the random number generation. To load the random number into AES, call Chip_AES_LoadKeyRNG + */ +uint32_t Chip_OTP_GenRand(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OTP_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/packing.h b/ports/lpc/chips/lpc_chip_43xx/inc/packing.h new file mode 100644 index 0000000000000..ce1f5167570d6 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/packing.h @@ -0,0 +1,45 @@ +/* + * @brief Packing macros + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PACKING_H_ +#define __PACKING_H_ + +#define PRE_PACK /* Nothing */ +#define POST_PACK /* Nothing */ +#define ALIGNED(n) /* Nothing */ + +#endif /* __PACKING_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/pinint_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/pinint_18xx_43xx.h new file mode 100644 index 0000000000000..3d93b5a809add --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/pinint_18xx_43xx.h @@ -0,0 +1,258 @@ +/* + * @brief LPC18xx/43xx Pin Interrupt and Pattern Match Registers and driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PININT_18XX_43XX_H_ +#define __PININT_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PININT_18XX_43XX CHIP: LPC18xx/43xx Pin Interrupt and Pattern Match driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief LPC18xx/43xx Pin Interrupt and Pattern Match register block structure + */ +typedef struct { /*!< PIN_INT Structure */ + __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< Pin Interrupt Status register */ +} LPC_PIN_INT_T; + + +/** + * LPC18xx/43xx Pin Interrupt channel values + */ +#define PININTCH0 (1 << 0) +#define PININTCH1 (1 << 1) +#define PININTCH2 (1 << 2) +#define PININTCH3 (1 << 3) +#define PININTCH4 (1 << 4) +#define PININTCH5 (1 << 5) +#define PININTCH6 (1 << 6) +#define PININTCH7 (1 << 7) +#define PININTCH(ch) (1 << (ch)) + +/** + * @brief Initialize Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + * @note This function should be used after the Chip_GPIO_Init() function. + */ +STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {} + +/** + * @brief De-Initialize Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {} + +/** + * @brief Configure the pins as edge sensitive in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->ISEL &= ~pins; +} + +/** + * @brief Configure the pins as level sensitive in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->ISEL |= pins; +} + +/** + * @brief Return current PININT rising edge or high level interrupt enable state + * @param pPININT : The base address of Pin interrupt block + * @return A bifield containing the high edge/level interrupt enables for each + * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. + * For each bit, a 0 means the high edge/level interrupt is disabled, while a 1 + * means it's enabled. + */ +STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IENR; +} + +/** + * @brief Enable high edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to enable (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->SIENR = pins; +} + +/** + * @brief Disable high edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to disable (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->CIENR = pins; +} + +/** + * @brief Return current PININT falling edge or low level interrupt enable state + * @param pPININT : The base address of Pin interrupt block + * @return A bifield containing the low edge/level interrupt enables for each + * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. + * For each bit, a 0 means the low edge/level interrupt is disabled, while a 1 + * means it's enabled. + */ +STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IENF; +} + +/** + * @brief Enable low edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to enable (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->SIENF = pins; +} + +/** + * @brief Disable low edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to disable (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->CIENF = pins; +} + +/** + * @brief Return pin states that have a detected latched high edge (RISE) state + * @param pPININT : The base address of Pin interrupt block + * @return PININT states (bit n = high) with a latched rise state detected + */ +STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT) +{ + return pPININT->RISE; +} + +/** + * @brief Clears pin states that had a latched high edge (RISE) state + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins with latched states to clear + * @return Nothing + */ +STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->RISE = pins; +} + +/** + * @brief Return pin states that have a detected latched falling edge (FALL) state + * @param pPININT : The base address of Pin interrupt block + * @return PININT states (bit n = high) with a latched rise state detected + */ +STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT) +{ + return pPININT->FALL; +} + +/** + * @brief Clears pin states that had a latched falling edge (FALL) state + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins with latched states to clear + * @return Nothing + */ +STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->FALL = pins; +} + +/** + * @brief Get interrupt status from Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Interrupt status (bit n for PININTn = high means interrupt ie pending) + */ +STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IST; +} + +/** + * @brief Clear interrupt status in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pin interrupts to clear (ORed value of PININTCH*) + * @return Nothing + */ +STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->IST = pins; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PININT_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/pmc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/pmc_18xx_43xx.h new file mode 100644 index 0000000000000..a8d6d826e779e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/pmc_18xx_43xx.h @@ -0,0 +1,105 @@ +/* + * @brief LPC18xx/43xx Power Management Controller driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PMC_18XX_43XX_H_ +#define __PMC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PMC_18XX_43XX CHIP: LPC18xx/43xx Power Management Controller driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Power Management Controller register block structure + */ +typedef struct { /*!< PMC Structure */ + __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< Hardware sleep event enable register */ + __I uint32_t RESERVED0[6]; + __IO uint32_t PD0_SLEEP0_MODE; /*!< Sleep power mode register */ +} LPC_PMC_T; + +/** + * @brief Power Management Controller power modes + * Setting this mode will not make IO loose the state + */ +#define PMC_PWR_DEEP_SLEEP_MODE 0x3000AA +#define PMC_PWR_POWER_DOWN_MODE 0x30FCBA +#define PMC_PWR_DEEP_POWER_DOWN_MODE 0x30FF7F + +/** + * @brief Power Management Controller power modes (IO powerdown) + * Setting this mode will make the IO loose the state + */ +#define PMC_PWR_DEEP_SLEEP_MODE_NO_IO 0x3F00AA +#define PMC_PWR_POWER_DOWN_MODE_NO_IO 0x3FFCBA +#define PMC_PWR_DEEP_POWER_DOWN_MODE_NO_IO 0x3FFF7F + +/* + * @brief PMC power states + */ +typedef enum { + PMC_DeepSleep = PMC_PWR_DEEP_SLEEP_MODE, /*!< Deep sleep state */ + PMC_PowerDown = PMC_PWR_POWER_DOWN_MODE, /*!< Power Down state */ + PMC_DeepPowerDown = PMC_PWR_DEEP_POWER_DOWN_MODE, /*!< Power Down state */ +} CHIP_PMC_PWR_STATE_T; + +/** + * @brief Set to sleep power state + * @return Nothing + */ +void Chip_PMC_Sleep(void); + +/** + * @brief Set to sleep power mode + * @param PwrState : Power State as specified in /a CHIP_PMC_PWR_STATE_T enum + * @return Nothing + */ +void Chip_PMC_Set_PwrState(CHIP_PMC_PWR_STATE_T PwrState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PMC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/qei_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/qei_18xx_43xx.h new file mode 100644 index 0000000000000..a97e19c76bb57 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/qei_18xx_43xx.h @@ -0,0 +1,92 @@ +/* + * @brief LPC18xx/43xx Quadrature Encoder Interface driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __QEI_18XX_43XX_H_ +#define __QEI_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup QEI_18XX_43XX CHIP: LPC18xx/43xx Quadrature Encoder Interface driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Quadrature Encoder Interface register block structure + */ +typedef struct { /*!< QEI Structure */ + __O uint32_t CON; /*!< Control register */ + __I uint32_t STAT; /*!< Encoder status register */ + __IO uint32_t CONF; /*!< Configuration register */ + __I uint32_t POS; /*!< Position register */ + __IO uint32_t MAXPOS; /*!< Maximum position register */ + __IO uint32_t CMPOS0; /*!< position compare register 0 */ + __IO uint32_t CMPOS1; /*!< position compare register 1 */ + __IO uint32_t CMPOS2; /*!< position compare register 2 */ + __I uint32_t INXCNT; /*!< Index count register */ + __IO uint32_t INXCMP0; /*!< Index compare register 0 */ + __IO uint32_t LOAD; /*!< Velocity timer reload register */ + __I uint32_t TIME; /*!< Velocity timer register */ + __I uint32_t VEL; /*!< Velocity counter register */ + __I uint32_t CAP; /*!< Velocity capture register */ + __IO uint32_t VELCOMP; /*!< Velocity compare register */ + __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */ + __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */ + __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */ + __IO uint32_t WINDOW; /*!< Index acceptance window register */ + __IO uint32_t INXCMP1; /*!< Index compare register 1 */ + __IO uint32_t INXCMP2; /*!< Index compare register 2 */ + __I uint32_t RESERVED0[993]; + __O uint32_t IEC; /*!< Interrupt enable clear register */ + __O uint32_t IES; /*!< Interrupt enable set register */ + __I uint32_t INTSTAT; /*!< Interrupt status register */ + __I uint32_t IE; /*!< Interrupt enable register */ + __O uint32_t CLR; /*!< Interrupt status clear register */ + __O uint32_t SET; /*!< Interrupt status set register */ +} LPC_QEI_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QEI_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h new file mode 100644 index 0000000000000..68569edaf4373 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h @@ -0,0 +1,164 @@ +/* + * @brief LPC18xx/43xx Reset Generator Unit driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RGU_18XX_43XX_H_ +#define __RGU_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief RGU reset enumerations + */ +typedef enum CHIP_RGU_RST { + RGU_CORE_RST, + RGU_PERIPH_RST, + RGU_MASTER_RST, + RGU_WWDT_RST = 4, + RGU_CREG_RST, + RGU_BUS_RST = 8, + RGU_SCU_RST, + RGU_M0SUB_RST = 12, + RGU_M3_RST, + RGU_LCD_RST = 16, + RGU_USB0_RST, + RGU_USB1_RST, + RGU_DMA_RST, + RGU_SDIO_RST, + RGU_EMC_RST, + RGU_ETHERNET_RST, + RGU_FLASHA_RST = 25, + RGU_EEPROM_RST = 27, + RGU_GPIO_RST, + RGU_FLASHB_RST, + RGU_TIMER0_RST = 32, + RGU_TIMER1_RST, + RGU_TIMER2_RST, + RGU_TIMER3_RST, + RGU_RITIMER_RST, + RGU_SCT_RST, + RGU_MOTOCONPWM_RST, + RGU_QEI_RST, + RGU_ADC0_RST, + RGU_ADC1_RST, + RGU_DAC_RST, + RGU_UART0_RST = 44, + RGU_UART1_RST, + RGU_UART2_RST, + RGU_UART3_RST, + RGU_I2C0_RST, + RGU_I2C1_RST, + RGU_SSP0_RST, + RGU_SSP1_RST, + RGU_I2S_RST, + RGU_SPIFI_RST, + RGU_CAN1_RST, + RGU_CAN0_RST, +#ifdef CHIP_LPC43XX + RGU_M0APP_RST, + RGU_SGPIO_RST, + RGU_SPI_RST, + RGU_ADCHS_RST = 60, +#endif + RGU_LAST_RST = 63, +} CHIP_RGU_RST_T; + +/** + * @brief RGU register structure + */ +typedef struct { /*!< RGU Structure */ + __I uint32_t RESERVED0[64]; + __O uint32_t RESET_CTRL[2]; /*!< Reset control register 0,1 */ + __I uint32_t RESERVED1[2]; + __IO uint32_t RESET_STATUS[4]; /*!< Reset status register 0 to 3 */ + __I uint32_t RESERVED2[12]; + __I uint32_t RESET_ACTIVE_STATUS[2]; /*!< Reset active status register 0, 1 */ + __I uint32_t RESERVED3[170]; + __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */ +} LPC_RGU_T; + +/** + * @brief Trigger a peripheral reset for the selected peripheral + * @param ResetNumber : Peripheral reset number to trigger + * @return Nothing + */ +STATIC INLINE void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber) +{ + LPC_RGU->RESET_CTRL[ResetNumber >> 5] = 1 << (ResetNumber & 31); + /* Reset will auto clear after 1 clock cycle */ +} + +/** + * @brief Checks the reset status of a peripheral + * @param ResetNumber : Peripheral reset number to trigger + * @return true if the periperal is still being reset + */ +STATIC INLINE bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber) +{ + return !(LPC_RGU->RESET_ACTIVE_STATUS[ResetNumber >> 5] & (1 << (ResetNumber & 31))); +} + +/** + * @brief Clears reset for the selected peripheral + * @param ResetNumber : Peripheral reset number to trigger (RGU_M0SUB_RST or RGU_M0APP_RST) + * @return Nothing + * @note + * Almost all peripherals will auto clear the reset bit. Only a few peripherals + * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require + * this function to clear the reset bit. This function clears all reset bits in + * a reset register. + */ +STATIC INLINE void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber) +{ + LPC_RGU->RESET_CTRL[ResetNumber >> 5] = 0; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RGU_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/ring_buffer.h b/ports/lpc/chips/lpc_chip_43xx/inc/ring_buffer.h new file mode 100644 index 0000000000000..2711cab8a54ff --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/ring_buffer.h @@ -0,0 +1,194 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RING_BUFFER_H_ +#define __RING_BUFFER_H_ + +#include "lpc_types.h" + +/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Ring buffer structure + */ +typedef struct { + void *data; + int count; + int itemSz; + uint32_t head; + uint32_t tail; +} RINGBUFF_T; + +/** + * @def RB_VHEAD(rb) + * volatile typecasted head index + */ +#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head) + +/** + * @def RB_VTAIL(rb) + * volatile typecasted tail index + */ +#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail) + +/** + * @brief Initialize ring buffer + * @param RingBuff : Pointer to ring buffer to initialize + * @param buffer : Pointer to buffer to associate with RingBuff + * @param itemSize : Size of each buffer item size + * @param count : Size of ring buffer + * @note Memory pointed by @a buffer must have correct alignment of + * @a itemSize, and @a count must be a power of 2 and must at + * least be 2 or greater. + * @return Nothing + */ +int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count); + +/** + * @brief Resets the ring buffer to empty + * @param RingBuff : Pointer to ring buffer + * @return Nothing + */ +STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff) +{ + RingBuff->head = RingBuff->tail = 0; +} + +/** + * @brief Return size the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Size of the ring buffer in bytes + */ +STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff) +{ + return RingBuff->count; +} + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Number of items in the ring buffer + */ +STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff) +{ + return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff); +} + +/** + * @brief Return number of free items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Number of free items in the ring buffer + */ +STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff) +{ + return RingBuff->count - RingBuffer_GetCount(RingBuff); +} + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return 1 if the ring buffer is full, otherwise 0 + */ +STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff) +{ + return (RingBuffer_GetCount(RingBuff) >= RingBuff->count); +} + +/** + * @brief Return empty status of ring buffer + * @param RingBuff : Pointer to ring buffer + * @return 1 if the ring buffer is empty, otherwise 0 + */ +STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff) +{ + return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff); +} + +/** + * @brief Insert a single item into ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : pointer to item + * @return 1 when successfully inserted, + * 0 on error (Buffer not initialized using + * RingBuffer_Init() or attempted to insert + * when buffer is full) + */ +int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data); + +/** + * @brief Insert an array of items into ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to first element of the item array + * @param num : Number of items in the array + * @return number of items successfully inserted, + * 0 on error (Buffer not initialized using + * RingBuffer_Init() or attempted to insert + * when buffer is full) + */ +int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num); + +/** + * @brief Pop an item from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to memory where popped item be stored + * @return 1 when item popped successfuly onto @a data, + * 0 When error (Buffer not initialized using + * RingBuffer_Init() or attempted to pop item when + * the buffer is empty) + */ +int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data); + +/** + * @brief Pop an array of items from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to memory where popped items be stored + * @param num : Max number of items array @a data can hold + * @return Number of items popped onto @a data, + * 0 on error (Buffer not initialized using RingBuffer_Init() + * or attempted to pop when the buffer is empty) + */ +int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num); + + +/** + * @} + */ + +#endif /* __RING_BUFFER_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/ritimer_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/ritimer_18xx_43xx.h new file mode 100644 index 0000000000000..1d59f4682f337 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/ritimer_18xx_43xx.h @@ -0,0 +1,195 @@ +/* + * @brief LPC18xx/43xx RITimer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RITIMER_18XX_43XX_H_ +#define __RITIMER_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RITIMER_18XX_43XX CHIP: LPC18xx/43xx Repetitive Interrupt Timer driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Repetitive Interrupt Timer register block structure + */ +typedef struct { /*!< RITIMER Structure */ + __IO uint32_t COMPVAL; /*!< Compare register */ + __IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */ + __IO uint32_t CTRL; /*!< Control register. */ + __IO uint32_t COUNTER; /*!< 32-bit counter */ +} LPC_RITIMER_T; + +/* + * @brief RITIMER register support bitfields and mask + */ + +/* + * RIT control register + */ +/** Set by H/W when the counter value equals the masked compare value */ +#define RIT_CTRL_INT ((uint32_t) (1)) +/** Set timer enable clear to 0 when the counter value equals the masked compare value */ +#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1)) +/** Set timer enable on debug */ +#define RIT_CTRL_ENBR ((uint32_t) _BIT(2)) +/** Set timer enable */ +#define RIT_CTRL_TEN ((uint32_t) _BIT(3)) + +/** + * @brief Initialize the RIT + * @param pRITimer : RITimer peripheral selected + * @return None + */ +void Chip_RIT_Init(LPC_RITIMER_T *pRITimer); + +/** + * @brief Shutdown the RIT + * @param pRITimer : RITimer peripheral selected + * @return None + */ +void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer); + +/** + * @brief Enable Timer + * @param pRITimer : RITimer peripheral selected + * @return None + */ +STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_TEN; +} + +/** + * @brief Disable Timer + * @param pRITimer : RITimer peripheral selected + * @return None + */ +STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL &= ~RIT_CTRL_TEN; +} + +/** + * @brief Enable timer debug + * @param pRITimer : RITimer peripheral selected + * @return None + */ +STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_ENBR; +} + +/** + * @brief Disable timer debug + * @param pRITimer : RITimer peripheral selected + * @return None + */ +STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL &= ~RIT_CTRL_ENBR; +} + +/** + * @brief Check whether interrupt flag is set or not + * @param pRITimer : RITimer peripheral selected + * @return Current interrupt status, either ET or UNSET + */ +IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer); + +/** + * @brief Set a tick value for the interrupt to time out + * @param pRITimer : RITimer peripheral selected + * @param val : value (in ticks) of the interrupt to be set + * @return None + */ +STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val) +{ + pRITimer->COMPVAL = val; +} + +/** + * @brief Enables or clears the RIT or interrupt + * @param pRITimer : RITimer peripheral selected + * @param val : RIT to be set, one or more RIT_CTRL_* values + * @return None + */ +STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val) +{ + pRITimer->CTRL |= val; +} + +/** + * @brief Clears the RIT interrupt + * @param pRITimer : RITimer peripheral selected + * @return None + */ +STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_INT; +} + +/** + * @brief Returns the current RIT Counter value + * @param pRITimer : RITimer peripheral selected + * @return the current timer counter value + */ +STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer) +{ + return pRITimer->COUNTER; +} + +/** + * @brief Set timer interval value + * @param pRITimer : RITimer peripheral selected + * @param time_interval : timer interval value (ms) + * @return None + */ +void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RITIMER_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h new file mode 100644 index 0000000000000..50cec255dd935 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h @@ -0,0 +1,134 @@ +/* + * @brief LPC18xx_43xx ROM API declarations and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ROMAPI_18XX_43XX_H_ +#define __ROMAPI_18XX_43XX_H_ + +#include "iap_18xx_43xx.h" +#include "error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ROMAPI_18XX_43XX CHIP: LPC18xx_43xx ROM API declarations and functions + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief LPC18XX_43XX OTP API structure + */ +typedef struct { + uint32_t (*Init)(void); /*!< Initializes OTP controller. */ + uint32_t (*ProgBootSrc)(CHIP_OTP_BOOT_SRC_T BootSrc); + uint32_t (*ProgJTAGDis)(void); + uint32_t (*ProgUSBID)(uint32_t ProductID, uint32_t VendorID); + uint32_t reserved01; + uint32_t reserved02; + uint32_t reserved03; + uint32_t reserved04; + uint32_t (*ProgGP0)(uint32_t data, uint32_t mask); + uint32_t (*ProgGP1)(uint32_t data, uint32_t mask); + uint32_t (*ProgGP2)(uint32_t data, uint32_t mask); + uint32_t (*ProgKey1)(uint8_t *key); + uint32_t (*ProgKey2)(uint8_t *key); + uint32_t (*GenRand)(void); +} OTP_API_T; + +/** + * @brief LPC18XX_43XX AES API structure + */ +typedef struct { + uint32_t (*Init)(void); + uint32_t (*SetMode)(uint32_t mode); + uint32_t (*LoadKey1)(void); + uint32_t (*LoadKey2)(void); + uint32_t (*LoadKeyRNG)(void); + uint32_t (*LoadKeySW)(uint8_t *pKey); + uint32_t (*LoadIV_SW)(uint8_t *pVector); + uint32_t (*LoadIV_IC)(void); + uint32_t (*Operate)(uint8_t *pOutput, uint8_t *pInput, uint32_t size); + uint32_t (*ProgramKey1)(uint8_t *pKey); + uint32_t (*ProgramKey2)(uint8_t *pKey); +} AES_API_T; + +/** + * @brief LPC18XX High level ROM API structure + */ +typedef struct { + void(*const iap_entry) (uint32_t *, uint32_t *); /*!< IAP API entry function available on Flash parts only*/ + const OTP_API_T *pOtp; + const AES_API_T *pAes; + uint32_t reserved[3]; + const uint32_t spifiApiBase; /*!< SPIFI API function table base address*/ + const uint32_t usbdApiBase; /*!< USBD API function table base address*/ + const uint32_t endMarker; /*!< API table end marker = 0x87654321 */ + +} LPC_ROM_API_T; + +/* Pointer to ROM API function address */ +#define LPC_ROM_API_BASE_LOC 0x10400100 +#define LPC_ROM_API ((LPC_ROM_API_T *) LPC_ROM_API_BASE) + +/* Pointer to ROM IAP entry functions */ +#define IAP_ENTRY_LOCATION (*((uint32_t *) 0x10400100)) + +/** + * @brief IAP flash bank definitions + */ +#define IAP_FLASH_BANK_A 0 +#define IAP_FLASH_BANK_B 1 + +/** + * @} + */ + +static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[]) +{ + ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ROMAPI_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/rtc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/rtc_18xx_43xx.h new file mode 100644 index 0000000000000..ff2caa2f19f06 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/rtc_18xx_43xx.h @@ -0,0 +1,644 @@ +/* + * @brief LPC18xx/43xx RTC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_18XX_43XX_H_ +#define __RTC_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx Real Time Clock driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */ + +/** + * @brief RTC time type option + */ +typedef enum { + RTC_TIMETYPE_SECOND, /*!< Second */ + RTC_TIMETYPE_MINUTE, /*!< Month */ + RTC_TIMETYPE_HOUR, /*!< Hour */ + RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */ + RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */ + RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */ + RTC_TIMETYPE_MONTH, /*!< Month */ + RTC_TIMETYPE_YEAR, /*!< Year */ + RTC_TIMETYPE_LAST +} RTC_TIMEINDEX_T; + +#if RTC_EV_SUPPORT +/** + * @brief Event Channel Identifier definitions + */ +typedef enum { + RTC_EV_CHANNEL_1 = 0, + RTC_EV_CHANNEL_2, + RTC_EV_CHANNEL_3, + RTC_EV_CHANNEL_NUM, +} RTC_EV_CHANNEL_T; +#endif /*RTC_EV_SUPPORT*/ + +/** + * @brief Real Time Clock register block structure + */ +typedef struct { /*!< RTC Structure */ + __IO uint32_t ILR; /*!< Interrupt Location Register */ + __I uint32_t RESERVED0; + __IO uint32_t CCR; /*!< Clock Control Register */ + __IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */ + __IO uint32_t AMR; /*!< Alarm Mask Register */ + __I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */ + __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */ + __IO uint32_t CALIBRATION; /*!< Calibration Value Register */ + __I uint32_t RESERVED1[7]; + __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */ +#if RTC_EV_SUPPORT + __IO uint32_t ERSTATUS; /*!< Event Monitor/Recorder Status register*/ + __IO uint32_t ERCONTROL; /*!< Event Monitor/Recorder Control register*/ + __I uint32_t ERCOUNTERS; /*!< Event Monitor/Recorder Counters register*/ + __I uint32_t RESERVED2; + __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /*!> (8 * ch)) & 0x07)) + +/* + * @brief Event Monitor/Recorder TimeStamp register + */ +#define RTC_ER_TIMESTAMP_SEC(n) ((uint32_t) (n & 0x3F)) +#define RTC_ER_TIMESTAMP_MIN(n) ((uint32_t) ((n >> 6) & 0x3F)) +#define RTC_ER_TIMESTAMP_HOUR(n) ((uint32_t) ((n >> 12) & 0x1F)) +#define RTC_ER_TIMESTAMP_DOY(n) ((uint32_t) ((n >> 17) & 0x1FF)) + +/** + * @brief Event Monitor/Recorder Mode definition + */ +typedef enum IP_RTC_EV_MODE { + RTC_EV_MODE_DISABLE = 0, /*!< Event Monitor/Recoder is disabled */ + RTC_EV_MODE_ENABLE_16HZ = 1, /*!< Event Monitor/Recoder is enabled and use 16Hz sample clock for event input */ + RTC_EV_MODE_ENABLE_64HZ = 2, /*!< Event Monitor/Recoder is enabled and use 64Hz sample clock for event input */ + RTC_EV_MODE_ENABLE_1KHZ = 3, /*!< Event Monitor/Recoder is enabled and use 1kHz sample clock for event input */ + RTC_EV_MODE_LAST, +} RTC_EV_MODE_T; + +/** + * @brief Event Monitor/Recorder Timestamp structure + */ +typedef struct { + uint8_t sec; /*!< Second */ + uint8_t min; /*!< Minute */ + uint8_t hour; /*!< Hour */ + uint16_t dayofyear; /*!< Day of year */ +} RTC_EV_TIMESTAMP_T; + +#endif /*RTC_EV_SUPPORT*/ + +/** + * @brief RTC enumeration + */ + +/** @brief RTC interrupt source */ +typedef enum { + RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */ + RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */ +} RTC_INT_OPT_T; + +typedef struct { + uint32_t time[RTC_TIMETYPE_LAST]; +} RTC_TIME_T; + +/** + * @brief Reset clock tick counter in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @return None + */ +void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC); + +/** + * @brief Start/Stop RTC peripheral + * @param pRTC : RTC peripheral selected + * @param NewState : New State of this function, should be: + * - ENABLE :The time counters are enabled + * - DISABLE :The time counters are disabled + * @return None + */ +void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState); + +/** + * @brief Enable/Disable Counter increment interrupt for a time type in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState); + +/** + * @brief Enable/Disable Alarm interrupt for a time type in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState); + +/** + * @brief Set current time value for a time type in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param Timetype : time field index type to set + * @param TimeValue : Value to palce in time field + * @return None + */ +STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t TimeValue) +{ + pRTC->TIME[Timetype] = TimeValue; +} + +/** + * @brief Get current time value for a type time type + * @param pRTC : RTC peripheral selected + * @param Timetype : Time field index type to get + * @return Value of time field according to specified time type + */ +STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype) +{ + return pRTC->TIME[Timetype]; +} + +/** + * @brief Set full time in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param pFullTime : Pointer to full time data + * @return None + */ +void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime); + +/** + * @brief Get full time from the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime); + +/** + * @brief Set alarm time value for a time type + * @param pRTC : RTC peripheral selected + * @param Timetype : Time index field to set + * @param ALValue : Alarm time value to set + * @return None + */ +STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t ALValue) +{ + pRTC->ALRM[Timetype] = ALValue; +} + +/** + * @brief Get alarm time value for a time type + * @param pRTC : RTC peripheral selected + * @param Timetype : Time index field to get + * @return Value of Alarm time according to specified time type + */ +STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype) +{ + return pRTC->ALRM[Timetype]; +} + +/** + * @brief Set full alarm time in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param pFullTime : Pointer to full time record to set alarm + * @return None + */ +void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime); + +/** + * @brief Get full alarm time in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime); + +/** + * @brief Write value to General purpose registers + * @param pRegFile : RegFile peripheral selected + * @param index : General purpose register index + * @param value : Value to write + * @return None + * @note These General purpose registers can be used to store important + * information when the main power supply is off. The value in these + * registers is not affected by chip reset. These registers are + * powered in the RTC power domain. + */ +STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t value) +{ + pRegFile->REGFILE[index] = value; +} + +/** + * @brief Read value from General purpose registers + * @param pRegFile : RegFile peripheral selected + * @param index : General purpose register index + * @return Read Value + * @note These General purpose registers can be used to store important + * information when the main power supply is off. The value in these + * registers is not affected by chip reset. These registers are + * powered in the RTC power domain. + */ +STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index) +{ + return pRegFile->REGFILE[index]; +} + +/** + * @brief Enable/Disable calibration counter in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param NewState : New State of this function, should be: + * - ENABLE :The calibration counter is enabled and counting + * - DISABLE :The calibration counter is disabled and reset to zero + * @return None + */ +void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState); + +/** + * @brief Configures Calibration in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param CalibValue : Calibration value, should be in range from 0 to 131,072 + * @param CalibDir : Calibration Direction, should be: + * - RTC_CALIB_DIR_FORWARD :Forward calibration + * - RTC_CALIB_DIR_BACKWARD :Backward calibration + * @return None + */ +STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir) +{ + pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK) + | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0); +} + +/** + * @brief Clear specified Location interrupt pending in the RTC peripheral + * @param pRTC : RTC peripheral selected + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending. + * - RTC_INT_ALARM :Clear alarm interrupt pending + * @return None + */ +STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType) +{ + pRTC->ILR = IntType; +} + +/** + * @brief Check whether if specified location interrupt in the RTC peripheral is set or not + * @param pRTC : RTC peripheral selected + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt. + * - RTC_INT_ALARM: Alarm generated an interrupt. + * @return New state of specified Location interrupt in RTC peripheral, SET OR RESET + */ +STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType) +{ + return (pRTC->ILR & IntType) ? SET : RESET; +} + +#if RTC_EV_SUPPORT + +/** + * @brief Configure a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @param flag : Configuration flag + * @return None + * @note flag is or-ed bit value of RTC_ERCTRL_INTWAKE_EN,RTC_ERCTRL_GPCLEAR_EN, + * RTC_ERCTRL_POL_POSITIVE and RTC_ERCTRL_INPUT_EN. + */ +STATIC INLINE void Chip_RTC_EV_Config(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, uint32_t flag) +{ + uint32_t temp; + + temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK; + pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK); +} + +/** + * @brief Enable/Disable and select clock frequency for Event Monitor/Recorder + * @param pRTC : RTC peripheral selected + * @param mode : selected mode + * @return None + */ +STATIC INLINE void Chip_RTC_EV_SetMode(LPC_RTC_T *pRTC, RTC_EV_MODE_T mode) +{ + uint32_t temp; + + temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK; + pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode); +} + +/** + * @brief Get Event Monitor/Recorder Status + * @param pRTC : RTC peripheral selected + * @return Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP + */ +STATIC INLINE uint8_t Chip_RTC_EV_GetStatus(LPC_RTC_T *pRTC) +{ + return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP); +} + +/** + * @brief Clear Event Monitor/Recorder Status + * @param pRTC : RTC peripheral selected + * @param flag : Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP + * @return Nothing + */ +STATIC INLINE void Chip_RTC_EV_ClearStatus(LPC_RTC_T *pRTC, uint32_t flag) +{ + pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP); +} + +/** + * @brief Get status of a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @return SET (At least 1 event occurred on the channel), RESET: no event occured. + */ +STATIC INLINE FlagStatus Chip_RTC_EV_GetChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch) +{ + return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET; +} + +/** + * @brief Clear status of a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @return Nothing. + */ +STATIC INLINE void Chip_RTC_EV_ClearChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch) +{ + pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch); +} + +/** + * @brief Get counter value of a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @return counter value + */ +STATIC INLINE uint8_t Chip_RTC_EV_GetCounter(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch) +{ + return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS); +} + +/** + * @brief Get first time stamp of a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @param pTimeStamp : pointer to Timestamp buffer + * @return Nothing. + */ +void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp); + +/** + * @brief Get last time stamp of a specific event channel + * @param pRTC : RTC peripheral selected + * @param ch : Channel number + * @param pTimeStamp : pointer to Timestamp buffer + * @return Nothing. + */ +void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp); + +#endif /*RTC_EV_SUPPORT*/ + +/** + * @brief Initialize the RTC peripheral + * @param pRTC : RTC peripheral selected + * @return None + */ +void Chip_RTC_Init(LPC_RTC_T *pRTC); + +/** + * @brief De-initialize the RTC peripheral + * @param pRTC : RTC peripheral selected + * @return None + */ +void Chip_RTC_DeInit(LPC_RTC_T *pRTC); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/rtc_ut.h b/ports/lpc/chips/lpc_chip_43xx/inc/rtc_ut.h new file mode 100644 index 0000000000000..7ec9c898b14e4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/rtc_ut.h @@ -0,0 +1,90 @@ +/* + * @brief RTC tick to (a more) Universal Time + * Adds conversion functions to use an RTC that only provides a + * seconds capability to provide "struct tm" support. + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_UT_H_ +#define __RTC_UT_H_ + +#include "chip.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RTC_UT CHIP: RTC tick to (a more) Universal Time conversion functions + * @ingroup CHIP_Common + * This driver converts between a RTC 1-second tick value and + * a Universal time format in a structure of type 'struct tm'. + * @{ + */ + +/* Starting year and starting day of week for the driver */ +#define TM_YEAR_BASE (1900) +#define TM_DAYOFWEEK (1) + +/** + * @brief Converts a RTC tick time to Universal time + * @param rtcTick : Current RTC time value + * @param pTime : Pointer to time structure to fill + * @return Nothing + * @note When setting time, the 'tm_wday', 'tm_yday', and 'tm_isdst' + * fields are not used. + */ +void ConvertRtcTime(uint32_t rtcTick, struct tm *pTime); + +/** + * @brief Converts a Universal time to RTC tick time + * @param pTime : Pointer to time structure to use + * @param rtcTick : Pointer to RTC time value to fill + * @return Nothing + * @note When converting time, the 'tm_isdst' field is not + * populated by the conversion function. + */ +void ConvertTimeRtc(struct tm *pTime, uint32_t *rtcTick); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_UT_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sct_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sct_18xx_43xx.h new file mode 100644 index 0000000000000..aa4ff2ad2ce7b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sct_18xx_43xx.h @@ -0,0 +1,429 @@ +/* + * @brief LPC18xx/43xx State Configurable Timer (SCT) driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCT_18XX_43XX_H_ +#define __SCT_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCT_18XX_43XX CHIP: LPC18xx/43xx State Configurable Timer driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/* + * @brief SCT Module configuration + */ +#define CONFIG_SCT_nEV (16) /*!< Number of events */ +#define CONFIG_SCT_nRG (16) /*!< Number of match/compare registers */ +#define CONFIG_SCT_nOU (16) /*!< Number of outputs */ + +/** + * @brief State Configurable Timer register block structure + */ +typedef struct { + __IO uint32_t CONFIG; /*!< Configuration Register */ + union { + __IO uint32_t CTRL_U; /*!< Control Register */ + struct { + __IO uint16_t CTRL_L; /*!< Low control register */ + __IO uint16_t CTRL_H; /*!< High control register */ + }; + + }; + + __IO uint16_t LIMIT_L; /*!< limit register for counter L */ + __IO uint16_t LIMIT_H; /*!< limit register for counter H */ + __IO uint16_t HALT_L; /*!< halt register for counter L */ + __IO uint16_t HALT_H; /*!< halt register for counter H */ + __IO uint16_t STOP_L; /*!< stop register for counter L */ + __IO uint16_t STOP_H; /*!< stop register for counter H */ + __IO uint16_t START_L; /*!< start register for counter L */ + __IO uint16_t START_H; /*!< start register for counter H */ + uint32_t RESERVED1[10]; /*!< 0x03C reserved */ + union { + __IO uint32_t COUNT_U; /*!< counter register */ + struct { + __IO uint16_t COUNT_L; /*!< counter register for counter L */ + __IO uint16_t COUNT_H; /*!< counter register for counter H */ + }; + + }; + + __IO uint16_t STATE_L; /*!< state register for counter L */ + __IO uint16_t STATE_H; /*!< state register for counter H */ + __I uint32_t INPUT; /*!< input register */ + __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */ + __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */ + __IO uint32_t OUTPUT; /*!< output register */ + __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */ + __IO uint32_t RES; /*!< conflict resolution register */ + __IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */ + __IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */ + uint32_t RESERVED2[35]; + __IO uint32_t EVEN; /*!< event enable register */ + __IO uint32_t EVFLAG; /*!< event flag register */ + __IO uint32_t CONEN; /*!< conflict enable register */ + __IO uint32_t CONFLAG; /*!< conflict flag register */ + union { + __IO union { /*!< ... Match / Capture value */ + uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */ + struct { + uint16_t L; /*!< SCTMATCH[i].L Access to L value */ + uint16_t H; /*!< SCTMATCH[i].H Access to H value */ + }; + + } MATCH[CONFIG_SCT_nRG]; + + __I union { + uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */ + struct { + uint16_t L; /*!< SCTCAP[i].L Access to L value */ + uint16_t H; /*!< SCTCAP[i].H Access to H value */ + }; + + } CAP[CONFIG_SCT_nRG]; + + }; + + uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /*!< ...-0x17C reserved */ + union { + __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /*!< 0x180-... Match Value L counter */ + __I uint16_t CAP_L[CONFIG_SCT_nRG]; /*!< 0x180-... Capture Value L counter */ + }; + + uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /*!< ...-0x1BE reserved */ + union { + __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Match Value H counter */ + __I uint16_t CAP_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Capture Value H counter */ + }; + + uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /*!< ...-0x1FE reserved */ + union { + __IO union { /*!< 0x200-... Match Reload / Capture Control value */ + uint32_t U; /*!< SCTMATCHREL[i].U Unified 32-bit register */ + struct { + uint16_t L; /*!< SCTMATCHREL[i].L Access to L value */ + uint16_t H; /*!< SCTMATCHREL[i].H Access to H value */ + }; + + } MATCHREL[CONFIG_SCT_nRG]; + + __IO union { + uint32_t U; /*!< SCTCAPCTRL[i].U Unified 32-bit register */ + struct { + uint16_t L; /*!< SCTCAPCTRL[i].L Access to L value */ + uint16_t H; /*!< SCTCAPCTRL[i].H Access to H value */ + }; + + } CAPCTRL[CONFIG_SCT_nRG]; + + }; + + uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /*!< ...-0x27C reserved */ + union { + __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Match Reload value L counter */ + __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Capture Control value L counter */ + }; + + uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /*!< ...-0x2BE reserved */ + union { + __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Match Reload value H counter */ + __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Capture Control value H counter */ + }; + + uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /*!< ...-0x2FE reserved */ + __IO struct { /*!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ + uint32_t STATE; /*!< Event State Register */ + uint32_t CTRL; /*!< Event Control Register */ + } EVENT[CONFIG_SCT_nEV]; + + uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */ + __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ + uint32_t SET; /*!< Output n Set Register */ + uint32_t CLR; /*!< Output n Clear Register */ + } OUT[CONFIG_SCT_nOU]; + + uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */ + __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */ +} LPC_SCT_T; + +/* + * @brief Macro defines for SCT configuration register + */ +#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */ +#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */ + +#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */ +#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */ +#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */ +#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */ + +#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */ +#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */ +#define SCT_CONFIG_AUTOLIMIT_L (0x1 << 17) /*!< Limits counter(L) based on MATCH0 */ +#define SCT_CONFIG_AUTOLIMIT_H (0x1 << 18) /*!< Limits counter(L) based on MATCH0 */ + +/* + * @brief Macro defines for SCT control register + */ +#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */ +#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 + +#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */ +#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */ +#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */ +#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */ +#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */ + +#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */ +#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 +#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */ +#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */ +#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */ +#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20) +#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */ + +/* + * @brief Macro defines for SCT Conflict resolution register + */ +#define SCT_RES_NOCHANGE (0) +#define SCT_RES_SET_OUTPUT (1) +#define SCT_RES_CLEAR_OUTPUT (2) +#define SCT_RES_TOGGLE_OUTPUT (3) + +/** + * SCT Match register values enum + */ +typedef enum CHIP_SCT_MATCH_REG { + SCT_MATCH_0 = 0, /*!< SCT Match register 0 */ + SCT_MATCH_1 = 1, /*!< SCT Match register 1 */ + SCT_MATCH_2 = 2, /*!< SCT Match register 2 */ + SCT_MATCH_3 = 3, /*!< SCT Match register 3 */ + SCT_MATCH_4 = 4 /*!< SCT Match register 4 */ +} CHIP_SCT_MATCH_REG_T; + +/** + * SCT Event values enum + */ +typedef enum CHIP_SCT_EVENT { + SCT_EVT_0 = (1 << 0), /*!< Event 0 */ + SCT_EVT_1 = (1 << 1), /*!< Event 1 */ + SCT_EVT_2 = (1 << 2), /*!< Event 2 */ + SCT_EVT_3 = (1 << 3), /*!< Event 3 */ + SCT_EVT_4 = (1 << 4) /*!< Event 4 */ +} CHIP_SCT_EVENT_T; + +/** + * @brief Configures the State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param value : The 32-bit CONFIG register value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value) +{ + pSCT->CONFIG = value; +} + +/** + * @brief Set or Clear the Control register + * @param pSCT : Pointer to SCT register block + * @param value : SCT Control register value + * @param ena : ENABLE - To set the fields specified by value + * : DISABLE - To clear the field specified by value + * @return Nothing + * Set or clear the control register bits as specified by the \a value + * parameter. If \a ena is set to ENABLE, the mentioned register fields + * will be set. If \a ena is set to DISABLE, the mentioned register + * fields will be cleared + */ +void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena); + +/** + * @brief Set the conflict resolution + * @param pSCT : Pointer to SCT register block + * @param outnum : Output number + * @param value : Output value + * - SCT_RES_NOCHANGE :No change + * - SCT_RES_SET_OUTPUT :Set output + * - SCT_RES_CLEAR_OUTPUT :Clear output + * - SCT_RES_TOGGLE_OUTPUT :Toggle output + * : SCT_RES_NOCHANGE + * : DISABLE - To clear the field specified by value + * @return Nothing + * Set conflict resolution for the output \a outnum + */ +void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value); + +/** + * @brief Set unified count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 32-bit count value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count) +{ + pSCT->COUNT_U = count; +} + +/** + * @brief Set lower count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 16-bit count value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count) +{ + pSCT->COUNT_L = count; +} + +/** + * @brief Set higher count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 16-bit count value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count) +{ + pSCT->COUNT_H = count; +} + +/** + * @brief Set unified match count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param n : Match register value + * @param value : The 32-bit match count value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetMatchCount(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) +{ + pSCT->MATCH[n].U = value; +} + +/** + * @brief Set control register in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param value : Value (ORed value of SCT_CTRL_* bits) + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value) +{ + pSCT->CTRL_U |= value; +} + +/** + * @brief Clear control register in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param value : Value (ORed value of SCT_CTRL_* bits) + * @return Nothing + */ +STATIC INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value) +{ + pSCT->CTRL_U &= ~(value); +} + +/** + * @brief Set unified match reload count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param n : Match register value + * @param value : The 32-bit match count reload value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_SetMatchReload(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) +{ + pSCT->MATCHREL[n].U = value; +} + +/** + * @brief Enable the interrupt for the specified event in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_EnableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) +{ + pSCT->EVEN |= evt; +} + +/** + * @brief Disable the interrupt for the specified event in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_DisableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) +{ + pSCT->EVEN &= ~(evt); +} + +/** + * @brief Clear the specified event flag in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +STATIC INLINE void Chip_SCT_ClearEventFlag(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) +{ + pSCT->EVFLAG |= evt; +} + +/** + * @brief Initializes the State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @return Nothing + */ +void Chip_SCT_Init(LPC_SCT_T *pSCT); + +/** + * @brief Deinitializes the State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @return Nothing + */ +void Chip_SCT_DeInit(LPC_SCT_T *pSCT); + +/** + * @} + */ + +#ifdef __cplusplus +} + +#endif + +#endif /* __SCT_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h new file mode 100644 index 0000000000000..91e65c7e41289 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h @@ -0,0 +1,184 @@ +/* + * @brief LPC18xx_43xx State Configurable Timer (SCT/PWM) Chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCT_PWM_18XX_43XX_H_ +#define __SCT_PWM_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCT_PWM_18XX_43XX CHIP: LPC18XX_43XX State Configurable Timer PWM driver + * + * For more information on how to use the driver please visit the FAQ page at + * + * www.lpcware.com + * + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Get number of ticks per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @return Number ot ticks that will be counted per cycle + * @note Return value of this function will be vaild only + * after calling Chip_SCTPWM_SetRate() + */ +STATIC INLINE uint32_t Chip_SCTPWM_GetTicksPerCycle(LPC_SCT_T *pSCT) +{ + return pSCT->MATCHREL[0].U; +} + +/** + * @brief Converts a percentage to ticks + * @param pSCT : The base of SCT peripheral on the chip + * @param percent : Percentage to convert (0 - 100) + * @return Number ot ticks corresponding to given percentage + * @note Do not use this function when using very low + * pwm rate (like 100Hz or less), on a chip that has + * very high frequency as the calculation might + * cause integer overflow + */ +STATIC INLINE uint32_t Chip_SCTPWM_PercentageToTicks(LPC_SCT_T *pSCT, uint8_t percent) +{ + return (Chip_SCTPWM_GetTicksPerCycle(pSCT) * percent) / 100; +} + +/** + * @brief Get number of ticks on per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @param index : Index of the PWM 1 to N (see notes) + * @return Number ot ticks for which the output will be ON per cycle + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. + */ +STATIC INLINE uint32_t Chip_SCTPWM_GetDutyCycle(LPC_SCT_T *pSCT, uint8_t index) +{ + return pSCT->MATCHREL[index].U; +} + +/** + * @brief Get number of ticks on per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @param index : Index of the PWM 1 to N (see notes) + * @param ticks : Number of ticks the output should say ON + * @return None + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. The new duty cycle will be effective only + * after completion of current PWM cycle. + */ +STATIC INLINE void Chip_SCTPWM_SetDutyCycle(LPC_SCT_T *pSCT, uint8_t index, uint32_t ticks) +{ + Chip_SCT_SetMatchReload(pSCT, (CHIP_SCT_MATCH_REG_T)index, ticks); +} + +/** + * @brief Initialize the SCT/PWM clock and reset + * @param pSCT : The base of SCT peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_SCTPWM_Init(LPC_SCT_T *pSCT) +{ + Chip_SCT_Init(pSCT); +} + +/** + * @brief Start the SCT PWM + * @param pSCT : The base of SCT peripheral on the chip + * @return None + * @note This function must be called after all the + * configuration is completed. Do not call Chip_SCTPWM_SetRate() + * or Chip_SCTPWM_SetOutPin() after the SCT/PWM is started. Use + * Chip_SCTPWM_Stop() to stop the SCT/PWM before reconfiguring, + * Chip_SCTPWM_SetDutyCycle() can be called when the SCT/PWM is + * running to change the DutyCycle. + */ +STATIC INLINE void Chip_SCTPWM_Start(LPC_SCT_T *pSCT) +{ + Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); +} + +/** + * @brief Stop the SCT PWM + * @param pSCT : The base of SCT peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_SCTPWM_Stop(LPC_SCT_T *pSCT) +{ + /* Stop SCT */ + Chip_SCT_SetControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); + + /* Clear the counter */ + Chip_SCT_SetControl(pSCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_CLRCTR_H); +} + +/** + * @brief Sets the frequency of the generated PWM wave + * @param pSCT : The base of SCT peripheral on the chip + * @param freq : Frequency in Hz + * @return None + */ +void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq); + +/** + * @brief Setup the OUTPUT pin and associate it with an index + * @param pSCT : The base of the SCT peripheral on the chip + * @param index : Index of PWM 1 to N (see notes) + * @param pin : COUT pin to be associated with the index + * @return None + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. + */ +void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin); + +/** + * @} + */ + +#ifdef __cplusplus +} + +#endif + +#endif /* __SCT_PWM_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/scu_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/scu_18xx_43xx.h new file mode 100644 index 0000000000000..889640e58bdf3 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/scu_18xx_43xx.h @@ -0,0 +1,253 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCU_18XX_43XX_H_ +#define __SCU_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions) + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + + +/** + * @brief Array of pin definitions passed to Chip_SCU_SetPinMuxing() must be in this format + */ +typedef struct { + uint8_t pingrp; /* Pin group */ + uint8_t pinnum; /* Pin number */ + uint16_t modefunc; /* Pin mode and function for SCU */ +} PINMUX_GRP_T; + +/** + * @brief System Control Unit register block + */ +typedef struct { + __IO uint32_t SFSP[16][32]; + __I uint32_t RESERVED0[256]; + __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */ + __I uint32_t RESERVED16[28]; + __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */ + __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */ + __IO uint32_t ENAIO[3]; /*!< Analog function select registerS */ + __I uint32_t RESERVED17[27]; + __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */ + __I uint32_t RESERVED18[63]; + __IO uint32_t PINTSEL[2]; /*!< Pin interrupt select register for pin int 0 to 3 index 0, 4 to 7 index 1. */ +} LPC_SCU_T; + +/** + * SCU function and mode selection definitions + * See the User Manual for specific modes and functions supoprted by the + * various LPC18xx/43xx devices. Functionality can vary per device. + */ +#define SCU_MODE_PULLUP (0x0 << 3) /*!< Enable pull-up resistor at pad */ +#define SCU_MODE_REPEATER (0x1 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */ +#define SCU_MODE_INACT (0x2 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */ +#define SCU_MODE_PULLDOWN (0x3 << 3) /*!< Enable pull-down resistor at pad */ +#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /*!< Enable high-speed slew */ +#define SCU_MODE_INBUFF_EN (0x1 << 6) /*!< Enable Input buffer */ +#define SCU_MODE_ZIF_DIS (0x1 << 7) /*!< Disable input glitch filter */ +#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /*!< Normal drive: 4mA drive strength */ +#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /*!< Medium drive: 8mA drive strength */ +#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /*!< High drive: 14mA drive strength */ +#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /*!< Ultra high- drive: 20mA drive strength */ +#define SCU_MODE_FUNC0 0x0 /*!< Selects pin function 0 */ +#define SCU_MODE_FUNC1 0x1 /*!< Selects pin function 1 */ +#define SCU_MODE_FUNC2 0x2 /*!< Selects pin function 2 */ +#define SCU_MODE_FUNC3 0x3 /*!< Selects pin function 3 */ +#define SCU_MODE_FUNC4 0x4 /*!< Selects pin function 4 */ +#define SCU_MODE_FUNC5 0x5 /*!< Selects pin function 5 */ +#define SCU_MODE_FUNC6 0x6 /*!< Selects pin function 6 */ +#define SCU_MODE_FUNC7 0x7 /*!< Selects pin function 7 */ +#define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS) + +/** + * SCU function and mode selection definitions (old) + * For backwards compatibility. + */ +#define MD_PUP (0x0 << 3) /** Enable pull-up resistor at pad */ +#define MD_BUK (0x1 << 3) /** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */ +#define MD_PLN (0x2 << 3) /** Disable pull-down and pull-up resistor at resistor at pad */ +#define MD_PDN (0x3 << 3) /** Enable pull-down resistor at pad */ +#define MD_EHS (0x1 << 5) /** Enable fast slew rate */ +#define MD_EZI (0x1 << 6) /** Input buffer enable */ +#define MD_ZI (0x1 << 7) /** Disable input glitch filter */ +#define MD_EHD0 (0x1 << 8) /** EHD driver strength low bit */ +#define MD_EHD1 (0x1 << 8) /** EHD driver strength high bit */ +#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS) +#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /** Pin configuration for STANDARD/FAST mode I2C */ +#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /** Pin configuration for Fast-mode Plus I2C */ +#define FUNC0 0x0 /** Pin function 0 */ +#define FUNC1 0x1 /** Pin function 1 */ +#define FUNC2 0x2 /** Pin function 2 */ +#define FUNC3 0x3 /** Pin function 3 */ +#define FUNC4 0x4 /** Pin function 4 */ +#define FUNC5 0x5 /** Pin function 5 */ +#define FUNC6 0x6 /** Pin function 6 */ +#define FUNC7 0x7 /** Pin function 7 */ + +#define PORT_OFFSET 0x80 /** Port offset definition */ +#define PIN_OFFSET 0x04 /** Pin offset definition */ + +/** Returns the SFSP register address in the SCU for a pin and port, recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */ +#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4)) + +/** Returns the address in the SCU for a SFSCLK clock register, recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */ +#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4))) + +/** + * @brief Sets I/O Control pin mux + * @param port : Port number, should be: 0..15 + * @param pin : Pin number, should be: 0..31 + * @param modefunc : OR'ed values or type SCU_MODE_* + * @return Nothing + * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use + * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins. + */ +STATIC INLINE void Chip_SCU_PinMuxSet(uint8_t port, uint8_t pin, uint16_t modefunc) +{ + LPC_SCU->SFSP[port][pin] = modefunc; +} + +/** + * @brief Configure pin function + * @param port : Port number, should be: 0..15 + * @param pin : Pin number, should be: 0..31 + * @param mode : OR'ed values or type SCU_MODE_* + * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7 + * @return Nothing + * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use + * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins. + */ +STATIC INLINE void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func) +{ + Chip_SCU_PinMuxSet(port, pin, (mode | (uint16_t) func)); +} + +/** + * @brief Configure clock pin function (pins SFSCLKx) + * @param clknum : Clock pin number, should be: 0..3 + * @param modefunc : OR'ed values or type SCU_MODE_* + * @return Nothing + */ +STATIC INLINE void Chip_SCU_ClockPinMuxSet(uint8_t clknum, uint16_t modefunc) +{ + LPC_SCU->SFSCLK[clknum] = (uint32_t) modefunc; +} + +/** + * @brief Configure clock pin function (pins SFSCLKx) + * @param clknum : Clock pin number, should be: 0..3 + * @param mode : OR'ed values or type SCU_MODE_* + * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7 + * @return Nothing + */ +STATIC INLINE void Chip_SCU_ClockPinMux(uint8_t clknum, uint16_t mode, uint8_t func) +{ + LPC_SCU->SFSCLK[clknum] = ((uint32_t) mode | (uint32_t) func); +} + +/** + * @brief GPIO Interrupt Pin Select + * @param PortSel : GPIO PINTSEL interrupt, should be: 0 to 7 + * @param PortNum : GPIO port number interrupt, should be: 0 to 7 + * @param PinNum : GPIO pin number Interrupt , should be: 0 to 31 + * @return Nothing + */ +STATIC INLINE void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum) +{ + int32_t of = (PortSel & 3) << 3; + uint32_t val = (((PortNum & 0x7) << 5) | (PinNum & 0x1F)) << of; + LPC_SCU->PINTSEL[PortSel >> 2] = (LPC_SCU->PINTSEL[PortSel >> 2] & ~(0xFF << of)) | val; +} + +/** + * @brief I2C Pin Configuration + * @param I2C0Mode : I2C0 mode, should be: + * - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit + * - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit + * @return Nothing + */ +STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode) +{ + LPC_SCU->SFSI2C0 = I2C0Mode; +} + +/** + * @brief ADC Pin Configuration + * @param ADC_ID : ADC number + * @param channel : ADC channel + * @return Nothing + */ +STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel) +{ + LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel; +} + +/** + * @brief DAC Pin Configuration + * @return Nothing + */ +STATIC INLINE void Chip_SCU_DAC_Analog_Config(void) +{ + /*Enable analog function DAC on pin P4_4*/ + LPC_SCU->ENAIO[2] |= 1; +} + +/** + * @brief Set all I/O Control pin muxing + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +STATIC INLINE void Chip_SCU_SetPinMuxing(const PINMUX_GRP_T *pinArray, uint32_t arrayLength) +{ + uint32_t ix; + for (ix = 0; ix < arrayLength; ix++ ) { + Chip_SCU_PinMuxSet(pinArray[ix].pingrp, pinArray[ix].pinnum, pinArray[ix].modefunc); + } +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCU_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sdif_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sdif_18xx_43xx.h new file mode 100644 index 0000000000000..498c369904dbf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sdif_18xx_43xx.h @@ -0,0 +1,485 @@ +/* + * @brief LPC18xx/43xx SD/SDIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDIF_18XX_43XX_H_ +#define __SDIF_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SDIF_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief SD/MMC & SDIO register block structure + */ +typedef struct { /*!< SDMMC Structure */ + __IO uint32_t CTRL; /*!< Control Register */ + __IO uint32_t PWREN; /*!< Power Enable Register */ + __IO uint32_t CLKDIV; /*!< Clock Divider Register */ + __IO uint32_t CLKSRC; /*!< SD Clock Source Register */ + __IO uint32_t CLKENA; /*!< Clock Enable Register */ + __IO uint32_t TMOUT; /*!< Timeout Register */ + __IO uint32_t CTYPE; /*!< Card Type Register */ + __IO uint32_t BLKSIZ; /*!< Block Size Register */ + __IO uint32_t BYTCNT; /*!< Byte Count Register */ + __IO uint32_t INTMASK; /*!< Interrupt Mask Register */ + __IO uint32_t CMDARG; /*!< Command Argument Register */ + __IO uint32_t CMD; /*!< Command Register */ + __I uint32_t RESP0; /*!< Response Register 0 */ + __I uint32_t RESP1; /*!< Response Register 1 */ + __I uint32_t RESP2; /*!< Response Register 2 */ + __I uint32_t RESP3; /*!< Response Register 3 */ + __I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */ + __IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */ + __I uint32_t STATUS; /*!< Status Register */ + __IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */ + __I uint32_t CDETECT; /*!< Card Detect Register */ + __I uint32_t WRTPRT; /*!< Write Protect Register */ + __IO uint32_t GPIO; /*!< General Purpose Input/Output Register */ + __I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */ + __I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */ + __IO uint32_t DEBNCE; /*!< Debounce Count Register */ + __IO uint32_t USRID; /*!< User ID Register */ + __I uint32_t VERID; /*!< Version ID Register */ + __I uint32_t RESERVED0; + __IO uint32_t UHS_REG; /*!< UHS-1 Register */ + __IO uint32_t RST_N; /*!< Hardware Reset */ + __I uint32_t RESERVED1; + __IO uint32_t BMOD; /*!< Bus Mode Register */ + __O uint32_t PLDMND; /*!< Poll Demand Register */ + __IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */ + __IO uint32_t IDSTS; /*!< Internal DMAC Status Register */ + __IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */ + __I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */ + __I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */ +} LPC_SDMMC_T; + +/** @brief SDIO DMA descriptor control (des0) register defines + */ +#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */ +#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */ +#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */ +#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */ +#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */ +#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */ +#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */ + +/** @brief SDIO DMA descriptor size (des1) register defines + */ +#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */ +#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */ +#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */ + +/** @brief SDIO control register defines + */ +#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */ +#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */ +#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */ +#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */ +#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */ +#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */ +#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */ +#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */ +#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */ +#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */ +#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */ +#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */ + +/** @brief SDIO Power Enable register defines + */ +#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */ + +/** @brief SDIO Clock divider register defines + */ +#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */ + +/** @brief SDIO Clock source register defines + */ +#define MCI_CLKSRC_CLKDIV0 0 +#define MCI_CLKSRC_CLKDIV1 1 +#define MCI_CLKSRC_CLKDIV2 2 +#define MCI_CLKSRC_CLKDIV3 3 +#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */ + +/** @brief SDIO Clock Enable register defines + */ +#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */ +#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */ + +/** @brief SDIO time-out register defines + */ +#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */ +#define MCI_TMOUT_DATA_MSK 0xFFFFFF00 +#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */ +#define MCI_TMOUT_RESP_MSK 0xFF + +/** @brief SDIO card-type register defines + */ +#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */ +#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */ + +/** @brief SDIO Interrupt status & mask register defines + */ +#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */ +#define MCI_INT_EBE (1 << 15) /*!< End-bit error */ +#define MCI_INT_ACD (1 << 14) /*!< Auto command done */ +#define MCI_INT_SBE (1 << 13) /*!< Start bit error */ +#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */ +#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */ +#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */ +#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */ +#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */ +#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */ +#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */ +#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */ +#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */ +#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */ +#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */ +#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */ +#define MCI_INT_CD (1 << 0) /*!< Card detect */ + +/** @brief SDIO Command register defines + */ +#define MCI_CMD_START (1UL << 31) /*!< Start command */ +#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */ +#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */ +#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */ +#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */ +#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */ +#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */ +#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */ +#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */ +#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */ +#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */ +#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */ +#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */ +#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */ +#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */ +#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */ +#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */ +#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */ +#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */ +#define MCI_CMD_INDX(n) ((n) & 0x1F) + +/** @brief SDIO status register definess + */ +#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF) + +/** @brief SDIO FIFO threshold defines + */ +#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF) +#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16) +#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28) +#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28) +#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28) +#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28) +#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28) +#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28) +#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28) +#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28) + +/** @brief Bus mode register defines + */ +#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */ +#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */ +#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */ +#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */ +#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */ +#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */ +#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */ +#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */ +#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */ +#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */ +#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */ +#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */ + +/** @brief Commonly used definitions + */ +#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */ + +/** Function prototype for SD interface IRQ callback */ +typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t); + +/** Function prototype for SD detect and write protect status check */ +typedef int32_t (*PSCHECK_FUNC_T)(void); + +/** Function prototype for SD slot power enable or slot reset */ +typedef void (*PS_POWER_FUNC_T)(int32_t enable); + +/** @brief SDIO chained DMA descriptor + */ +typedef struct { + volatile uint32_t des0; /*!< Control and status */ + volatile uint32_t des1; /*!< Buffer size(s) */ + volatile uint32_t des2; /*!< Buffer address pointer 1 */ + volatile uint32_t des3; /*!< Buffer address pointer 2 */ +} pSDMMC_DMA_T; + +/** @brief SDIO device type + */ +typedef struct _sdif_device { + /* MCI_IRQ_CB_FUNC_T irq_cb; */ + pSDMMC_DMA_T mci_dma_dd[1 + (0x10000 / MCI_DMADES1_MAXTR)]; + /* uint32_t sdio_clk_rate; */ + /* uint32_t sdif_slot_clk_rate; */ + /* int32_t clock_enabled; */ +} sdif_device; + +/** @brief Setup options for the SDIO driver + */ +#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */ +#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/ +#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */ +#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */ +#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */ +#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */ +#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */ +#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */ +#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */ +#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */ + +/** + * @brief Set block size for the transfer + * @param pSDMMC : SDMMC peripheral selected + * @param bytes : block size in bytes + * @return None + */ +STATIC INLINE void Chip_SDIF_SetBlkSize(LPC_SDMMC_T *pSDMMC, uint32_t bytes) +{ + pSDMMC->BLKSIZ = bytes; +} + +/** + * @brief Reset card in slot + * @param pSDMMC : SDMMC peripheral selected + * @param reset : Sets SD_RST to passed state + * @return None + * @note Reset card in slot, must manually de-assert reset after assertion + * (Uses SD_RST pin, set per reset parameter state) + */ +STATIC INLINE void Chip_SDIF_Reset(LPC_SDMMC_T *pSDMMC, int32_t reset) +{ + if (reset) { + pSDMMC->RST_N = 1; + } + else { + pSDMMC->RST_N = 0; + } +} + +/** + * @brief Detect if an SD card is inserted + * @param pSDMMC : SDMMC peripheral selected + * @return Returns 0 if a card is detected, otherwise 1 + * @note Detect if an SD card is inserted + * (uses SD_CD pin, returns 0 on card detect) + */ +STATIC INLINE int32_t Chip_SDIF_CardNDetect(LPC_SDMMC_T *pSDMMC) +{ + return (pSDMMC->CDETECT & 1); +} + +/** + * @brief Detect if write protect is enabled + * @param pSDMMC : SDMMC peripheral selected + * @return Returns 1 if card is write protected, otherwise 0 + * @note Detect if write protect is enabled + * (uses SD_WP pin, returns 1 if card is write protected) + */ +STATIC INLINE int32_t Chip_SDIF_CardWpOn(LPC_SDMMC_T *pSDMMC) +{ + return (pSDMMC->WRTPRT & 1); +} + +/** + * @brief Disable slot power + * @param pSDMMC : SDMMC peripheral selected + * @return None + * @note Uses SD_POW pin, set to low. + */ +STATIC INLINE void Chip_SDIF_PowerOff(LPC_SDMMC_T *pSDMMC) +{ + pSDMMC->PWREN = 0; +} + +/** + * @brief Enable slot power + * @param pSDMMC : SDMMC peripheral selected + * @return None + * @note Uses SD_POW pin, set to high. + */ +STATIC INLINE void Chip_SDIF_PowerOn(LPC_SDMMC_T *pSDMMC) +{ + pSDMMC->PWREN = 1; +} + +/** + * @brief Function to set card type + * @param pSDMMC : SDMMC peripheral selected + * @param ctype : card type + * @return None + */ +STATIC INLINE void Chip_SDIF_SetCardType(LPC_SDMMC_T *pSDMMC, uint32_t ctype) +{ + pSDMMC->CTYPE = ctype; +} + +/** + * @brief Returns the raw SD interface interrupt status + * @param pSDMMC : SDMMC peripheral selected + * @return Current pending interrupt status of Or'ed values MCI_INT_* + */ +STATIC INLINE uint32_t Chip_SDIF_GetIntStatus(LPC_SDMMC_T *pSDMMC) +{ + return pSDMMC->RINTSTS; +} + +/** + * @brief Clears the raw SD interface interrupt status + * @param pSDMMC : SDMMC peripheral selected + * @param iVal : Interrupts to be cleared, Or'ed values MCI_INT_* + * @return None + */ +STATIC INLINE void Chip_SDIF_ClrIntStatus(LPC_SDMMC_T *pSDMMC, uint32_t iVal) +{ + pSDMMC->RINTSTS = iVal; +} + +/** + * @brief Sets the SD interface interrupt mask + * @param pSDMMC : SDMMC peripheral selected + * @param iVal : Interrupts to enable, Or'ed values MCI_INT_* + * @return None + */ +STATIC INLINE void Chip_SDIF_SetIntMask(LPC_SDMMC_T *pSDMMC, uint32_t iVal) +{ + pSDMMC->INTMASK = iVal; +} + +/** + * @brief Set block size and byte count for transfer + * @param pSDMMC : SDMMC peripheral selected + * @param blk_size: block size and byte count in bytes + * @return None + */ +STATIC INLINE void Chip_SDIF_SetBlkSizeByteCnt(LPC_SDMMC_T *pSDMMC, uint32_t blk_size) +{ + pSDMMC->BLKSIZ = blk_size; + pSDMMC->BYTCNT = blk_size; +} + +/** + * @brief Set byte count for transfer + * @param pSDMMC : SDMMC peripheral selected + * @param bytes : block size and byte count in bytes + * @return None + */ +STATIC INLINE void Chip_SDIF_SetByteCnt(LPC_SDMMC_T *pSDMMC, uint32_t bytes) +{ + pSDMMC->BYTCNT = bytes; +} + +/** + * @brief Initializes the SD/MMC card controller + * @param pSDMMC : SDMMC peripheral selected + * @return None + */ +void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Shutdown the SD/MMC card controller + * @param pSDMMC : SDMMC peripheral selected + * @return None + */ +void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Function to send command to Card interface unit (CIU) + * @param pSDMMC : SDMMC peripheral selected + * @param cmd : Command with all flags set + * @param arg : Argument for the command + * @return TRUE on times-out, otherwise FALSE + */ +int32_t Chip_SDIF_SendCmd(LPC_SDMMC_T *pSDMMC, uint32_t cmd, uint32_t arg); + +/** + * @brief Read the response from the last command + * @param pSDMMC : SDMMC peripheral selected + * @param resp : Pointer to response array to fill + * @return None + */ +void Chip_SDIF_GetResponse(LPC_SDMMC_T *pSDMMC, uint32_t *resp); + +/** + * @brief Sets the SD bus clock speed + * @param pSDMMC : SDMMC peripheral selected + * @param clk_rate : Input clock rate into the IP block + * @param speed : Desired clock speed to the card + * @return None + */ +void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed); + +/** + * @brief Function to clear interrupt & FIFOs + * @param pSDMMC : SDMMC peripheral selected + * @return None + */ +void Chip_SDIF_SetClearIntFifo(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Setup DMA descriptors + * @param pSDMMC : SDMMC peripheral selected + * @param psdif_dev : SD interface device + * @param addr : Address of buffer (source or destination) + * @param size : size of buffer in bytes (64K max) + * @return None + */ +void Chip_SDIF_DmaSetup(LPC_SDMMC_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDIF_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sdio_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sdio_18xx_43xx.h new file mode 100644 index 0000000000000..a131c3761feb3 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sdio_18xx_43xx.h @@ -0,0 +1,284 @@ +/* + * @brief LPC18xx/43xx SD/MMC card driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDIO_18XX_43XX_H_ +#define __SDIO_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SDIO_18XX_43XX CHIP: LPC18xx/43xx SDIO Card driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** @brief SDIO Driver events */ +enum SDIO_EVENT +{ + SDIO_START_COMMAND, /**! SDIO driver is about to start a command transfer */ + SDIO_START_DATA, /**! SDIO driver is about to start a data transfer */ + SDIO_WAIT_DELAY, /**! SDIO driver needs to wait for given milli seconds */ + SDIO_WAIT_COMMAND, /**! SDIO driver is waiting for a command to complete */ + SDIO_WAIT_DATA, /**! SDIO driver is waiting for data transfer to complete */ + + SDIO_CARD_DETECT, /**! SDIO driver has detected a card */ + SDIO_CMD_ERR, /**! Error in command transfer */ + SDIO_CMD_DONE, /**! Command transfer successful */ + SDIO_DATA_ERR, /**! Data transfer error */ + SDIO_DATA_DONE, /**! Data transfer successful */ + SDIO_CARD_INT, /**! SDIO Card interrupt (from a function) */ +}; + +/** @brief SDIO Command Responses */ +#define SDIO_CMD_RESP_R1 (1UL << 6) +#define SDIO_CMD_RESP_R2 (3UL << 6) +#define SDIO_CMD_RESP_R3 (1UL << 6) +#define SDIO_CMD_RESP_R4 (1UL << 6) +#define SDIO_CMD_RESP_R5 (1UL << 6) +#define SDIO_CMD_RESP_R6 (1UL << 6) + +/** @brief SDIO Command misc options */ +#define SDIO_CMD_CRC (1UL << 8) /**! Response must have a valid CRC */ +#define SDIO_CMD_DATA (1UL << 9) /**! Command is a data transfer command */ + +/** @brief List of commands */ +#define CMD0 (0 | (1 << 15)) +#define CMD5 (5 | SDIO_CMD_RESP_R4) +#define CMD3 (3 | SDIO_CMD_RESP_R6) +#define CMD7 (7 | SDIO_CMD_RESP_R1) +#define CMD52 (52 | SDIO_CMD_RESP_R5 | SDIO_CMD_CRC) +#define CMD53 (53 | SDIO_CMD_RESP_R5 | SDIO_CMD_DATA | SDIO_CMD_CRC) + +/** @brief SDIO Error numbers */ +#define SDIO_ERROR -1 /**! General SDIO Error */ +#define SDIO_ERR_FNUM -2 /**! Error getting Number of functions supported */ +#define SDIO_ERR_READWRITE -3 /**! Error when performing Read/write of data */ +#define SDIO_ERR_VOLT -4 /**! Error Reading or setting up the voltage to 3v3 */ +#define SDIO_ERR_RCA -5 /**! Error during RCA phase */ +#define SDIO_ERR_INVFUNC -6 /**! Invalid function argument */ +#define SDIO_ERR_INVARG -7 /**! Invalid argument supplied to function */ + +#define SDIO_VOLT_3_3 0x00100000UL /* for CMD5 */ + +/* SDIO Data transfer modes */ +/** @brief Block mode transfer flag + * + * When this flag is specified in a transfer the data will be transfered in blocks if not + * it will be transfered in bytes. See SDIO_Card_DataRead(), SDIO_Card_DataWrite() + * for more information. + */ +#define SDIO_MODE_BLOCK (1UL << 27) + +/** @brief Buffer mode transfer flag + * + * Default mode for SDIO_Card_ReadData() and SDIO_Card_WriteData() is FIFO mode + * in FIFO mode all the given data will be written to or read from the same + * register address in the function. This flag will set the transfers to BUFFER + * mode; in BUFFER mode read first byte will be read from the given source address + * and the next byte will be read from the next source address (i.e src_addr + 1), + * and so on, in BUFFER mode write first byte will be written to dest_addr, next + * byte will be written to dest_addr + 1 and so on. + */ +#define SDIO_MODE_BUFFER (1UL << 26) + +/* ---- SDIO Internal map ---- */ +#define SDIO_AREA_CIA 0 /* function 0 */ + +/* ---- Card Capability(0x08) register ---- */ +#define SDIO_CCCR_LSC 0x40u /* card is low-speed cards */ +#define SDIO_CCCR_4BLS 0x80u /* 4-bit support for low-speed cards */ + +#define SDIO_POWER_INIT 1 + +#define SDIO_CLK_HISPEED 33000000UL /* High-Speed Clock */ +#define SDIO_CLK_FULLSPEED 16000000UL /* Full-Speed Clock */ +#define SDIO_CLK_LOWSPEED 400000 /* Low-Speed Clock */ + +/** + * @brief Initialize the SDIO card + * @param pSDMMC : SDMMC peripheral selected + * @param freq : Initial frequency to use during the enumeration + * @return 0 on Success; > 0 on response error [like CRC error] < 0 on BUS error + */ +int SDIO_Card_Init(LPC_SDMMC_T *pSDMMC, uint32_t freq); + +/** + * @brief Write 8-Bit register from SDIO register space + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param addr : Address of the register to read + * @param data : 8-bit data be written + * @return 0 on Success; > 0 on response error [like CRC error] < 0 on BUS error + * @note SDIO_Setup_Callback() function must be called to setup the call backs before + * calling this API. + */ +int SDIO_Write_Direct(LPC_SDMMC_T *pSDMMC, uint32_t func, uint32_t addr, uint32_t data); + +/** + * @brief Write 8-Bit register from SDIO register space and read the register back + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param addr : Address of the register to read + * @param data : Pointer to memory where the 8-bit data be stored + * @return 0 on Success; > 0 on response error [like CRC error] < 0 on BUS error + * @note @a data must have the value to be written stored in it when the function is called + */ +int SDIO_WriteRead_Direct(LPC_SDMMC_T *pSDMMC, uint32_t func, uint32_t addr, uint32_t *data); + +/** + * @brief Read an 8-Bit register from SDIO register space + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param addr : Address of the register to read + * @param data : Pointer to memory where the 8-bit data be stored + * @return 0 on Success; > 0 on response error [like CRC error] < 0 on BUS error + */ +int SDIO_Read_Direct(LPC_SDMMC_T *pSDMMC, uint32_t func, uint32_t addr, uint32_t *data); + +/** + * @brief Setup SDIO wait and wakeup callbacks + * @param pSDMMC : SDMMC peripheral selected + * @param wake_evt : Wakeup event call-back handler + * @param wait_evt : Wait event call-back handler + * @return Nothing + * @note @a wake_evt and @a wait_evt should always be non-null function pointers + * This function must be called before calling SDIO_Card_Init() function + */ +void SDIO_Setup_Callback(LPC_SDMMC_T *pSDMMC, + void (*wake_evt)(LPC_SDMMC_T *pSDMMC, uint32_t event, void *arg), + uint32_t (*wait_evt)(LPC_SDMMC_T *pSDMMC, uint32_t event, void *arg)); + +/** + * @brief SDIO Event handler [Should be called from SDIO interrupt handler] + * @param pSDMMC : SDMMC peripheral selected + * @return Nothing + */ +void SDIO_Handler(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Sends a command to the SDIO Card [Example CMD52] + * @param pSDMMC : SDMMC peripheral selected + * @param cmd : Command to be sent along with any flags + * @param arg : Argument for the command + * @return 0 on Success; Non-Zero on failure + */ +uint32_t SDIO_Send_Command(LPC_SDMMC_T *pSDMMC, uint32_t cmd, uint32_t arg); + +/** + * @brief Gets the block size of a given function + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @return Block size of the given function + * @sa SDIO_Card_SetBlockSize() + * @note If the return value is 0 then bock size is not set using + * SDIO_Card_SetBlockSize(), or given @a func is not valid or the + * card does not support block data transfers. + */ +uint32_t SDIO_Card_GetBlockSize(LPC_SDMMC_T *pSDMMC, uint32_t func); + +/** + * @brief Sets the block size of a given function + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param blkSize : Block size to set + * @return 0 on success; Non-Zero on failure + * @sa SDIO_Card_GetBlockSize() + * @note After setting block size using this API, if + * SDIO_Card_GetBlockSize() returns 0 for a valid function then the card + * does not support block transfers. + */ +int SDIO_Card_SetBlockSize(LPC_SDMMC_T *pSDMMC, uint32_t func, uint32_t blkSize); + +/** + * @brief Writes stream or block of data to the SDIO card [Using CMD53] + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param dest_addr : Address where the data to be written (inside @a func register space) + * @param src_addr : Buffer from which data to be taken + * @param size : Number of Bytes/Blocks to be transfered [Must be in the range 1 to 512] + * @param flags : Or-ed value of #SDIO_MODE_BLOCK, #SDIO_MODE_BUFFER + * @return 0 on success; Non-Zero on failure + * @note When #SDIO_MODE_BLOCK is set in @a flags the size is number of blocks, so + * the number of bytes transferd will be @a size * "block size" [See SDIO_Card_GetBlockSize() and + * SDIO_Card_SetBlockSize() for more information] + */ +int SDIO_Card_WriteData(LPC_SDMMC_T *pSDMMC, uint32_t func, + uint32_t dest_addr, const uint8_t *src_addr, + uint32_t size, uint32_t flags); + +/** + * @brief Reads stream or block of data from the SDIO card [Using CMD53] + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @param dest_addr : memory where the data to be read into + * @param src_addr : Register address from which data to be read (inside @a func register space) + * @param size : Number of Bytes/Blocks to be transfered [Must be in the range 1 to 512] + * @param flags : Or-ed value of #SDIO_MODE_BLOCK, #SDIO_MODE_BUFFER + * @return 0 on success; Non-Zero on failure + * @note When #SDIO_MODE_BLOCK is set in @a flags the size is number of blocks, so + * the number of bytes transferd will be @a size * "block size" [See SDIO_Card_GetBlockSize() and + * SDIO_Card_SetBlockSize() for more information] + */ +int SDIO_Card_ReadData(LPC_SDMMC_T *pSDMMC, uint32_t func, + uint8_t *dest_addr, uint32_t src_addr, + uint32_t size, uint32_t flags); + +/** + * @brief Disable SDIO interrupt for a given function + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @return 0 - on success; Non zero on failure + */ +int SDIO_Card_DisableInt(LPC_SDMMC_T *pSDMMC, uint32_t func); + +/** + * @brief Enable SDIO interrupt for a given function + * @param pSDMMC : SDMMC peripheral selected + * @param func : function number [0 to 7] [0 = CIA function] + * @return 0 - on success; Non zero on failure + */ +int SDIO_Card_EnableInt(LPC_SDMMC_T *pSDMMC, uint32_t func); + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __SDIO_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc.h b/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc.h new file mode 100644 index 0000000000000..6bcdc32669ae1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc.h @@ -0,0 +1,456 @@ +/* + * @brief Common definitions used in SD/MMC cards + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDMMC_H +#define __SDMMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CHIP_SDMMC_Definitions CHIP: Common SD/MMC definitions + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief OCR Register definitions + */ +/** Support voltage range 2.0-2.1 (this bit is reserved in SDC)*/ +#define SDC_OCR_20_21 (((uint32_t) 1) << 8) +/** Support voltage range 2.1-2.2 (this bit is reserved in SDC)*/ +#define SDC_OCR_21_22 (((uint32_t) 1) << 9) +/** Support voltage range 2.2-2.3 (this bit is reserved in SDC)*/ +#define SDC_OCR_22_23 (((uint32_t) 1) << 10) +/** Support voltage range 2.3-2.4 (this bit is reserved in SDC)*/ +#define SDC_OCR_23_24 (((uint32_t) 1) << 11) +/** Support voltage range 2.4-2.5 (this bit is reserved in SDC)*/ +#define SDC_OCR_24_25 (((uint32_t) 1) << 12) +/** Support voltage range 2.5-2.6 (this bit is reserved in SDC)*/ +#define SDC_OCR_25_26 (((uint32_t) 1) << 13) +/** Support voltage range 2.6-2.7 (this bit is reserved in SDC)*/ +#define SDC_OCR_26_27 (((uint32_t) 1) << 14) +/** Support voltage range 2.7-2.8 */ +#define SDC_OCR_27_28 (((uint32_t) 1) << 15) +/** Support voltage range 2.8-2.9*/ +#define SDC_OCR_28_29 (((uint32_t) 1) << 16) +/** Support voltage range 2.9-3.0 */ +#define SDC_OCR_29_30 (((uint32_t) 1) << 17) +/** Support voltage range 3.0-3.1 */ +#define SDC_OCR_30_31 (((uint32_t) 1) << 18) +/** Support voltage range 3.1-3.2 */ +#define SDC_OCR_31_32 (((uint32_t) 1) << 19) +/** Support voltage range 3.2-3.3 */ +#define SDC_OCR_32_33 (((uint32_t) 1) << 20) +/** Support voltage range 3.3-3.4 */ +#define SDC_OCR_33_34 (((uint32_t) 1) << 21) +/** Support voltage range 3.4-3.5 */ +#define SDC_OCR_34_35 (((uint32_t) 1) << 22) +/** Support voltage range 3.5-3.6 */ +#define SDC_OCR_35_36 (((uint32_t) 1) << 23) +/** Support voltage range 2.7-3.6 */ +#define SDC_OCR_27_36 ((uint32_t) 0x00FF8000) +/** Card Capacity Status (CCS). (this bit is reserved in MMC) */ +#define SDC_OCR_HC_CCS (((uint32_t) 1) << 30) +/** Card power up status bit */ +#define SDC_OCR_IDLE (((uint32_t) 1) << 31) +#define SDC_OCR_BUSY (((uint32_t) 0) << 31) + +/* SD/MMC commands - this matrix shows the command, response types, and + supported card type for that command. + Command Number Resp SD MMC + ----------------------- ------ ----- --- --- + Reset (go idle) CMD0 NA x x + Send op condition CMD1 R3 x + All send CID CMD2 R2 x x + Send relative address CMD3 R1 x + Send relative address CMD3 R6 x + Program DSR CMD4 NA x + Select/deselect card CMD7 R1b x + Select/deselect card CMD7 R1 x + Send CSD CMD9 R2 x x + Send CID CMD10 R2 x x + Read data until stop CMD11 R1 x x + Stop transmission CMD12 R1/b x x + Send status CMD13 R1 x x + Go inactive state CMD15 NA x x + Set block length CMD16 R1 x x + Read single block CMD17 R1 x x + Read multiple blocks CMD18 R1 x x + Write data until stop CMD20 R1 x + Setblock count CMD23 R1 x + Write single block CMD24 R1 x x + Write multiple blocks CMD25 R1 x x + Program CID CMD26 R1 x + Program CSD CMD27 R1 x x + Set write protection CMD28 R1b x x + Clear write protection CMD29 R1b x x + Send write protection CMD30 R1 x x + Erase block start CMD32 R1 x + Erase block end CMD33 R1 x + Erase block start CMD35 R1 x + Erase block end CMD36 R1 x + Erase blocks CMD38 R1b x + Fast IO CMD39 R4 x + Go IRQ state CMD40 R5 x + Lock/unlock CMD42 R1b x + Application command CMD55 R1 x + General command CMD56 R1b x + + *** SD card application commands - these must be preceded with *** + *** MMC CMD55 application specific command first *** + Set bus width ACMD6 R1 x + Send SD status ACMD13 R1 x + Send number WR blocks ACMD22 R1 x + Set WR block erase cnt ACMD23 R1 x + Send op condition ACMD41 R3 x + Set clear card detect ACMD42 R1 x + Send CSR ACMD51 R1 x */ + +/** + * @brief SD/MMC application specific commands for SD cards only - these + * must be preceded by the SDMMC CMD55 to work correctly + */ +typedef enum { + SD_SET_BUS_WIDTH, /*!< Set the SD bus width */ + SD_SEND_STATUS, /*!< Send the SD card status */ + SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */ + SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */ + SD_SENDOP_COND, /*!< Send the OCR register (init) */ + SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */ + SD_SEND_SCR, /*!< Send the SD configuration register */ + SD_INVALID_APP_CMD /*!< Invalid SD application command */ +} SD_APP_CMD_T; + +/** + * @brief Possible SDMMC response types + */ +typedef enum { + SDMMC_RESPONSE_R1, /*!< Typical status */ + SDMMC_RESPONSE_R1B, /*!< Typical status with busy */ + SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */ + SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */ + SDMMC_RESPONSE_R4, /*!< Fast IO response word */ + SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */ + SDMMC_RESPONSE_R6, /*!< Published RCA response */ + SDMMC_RESPONSE_NONE /*!< No response expected */ +} SDMMC_RESPONSE_T; + +/** + * @brief Possible SDMMC card state types + */ +typedef enum { + SDMMC_IDLE_ST = 0, /*!< Idle state */ + SDMMC_READY_ST, /*!< Ready state */ + SDMMC_IDENT_ST, /*!< Identification State */ + SDMMC_STBY_ST, /*!< standby state */ + SDMMC_TRAN_ST, /*!< transfer state */ + SDMMC_DATA_ST, /*!< Sending-data State */ + SDMMC_RCV_ST, /*!< Receive-data State */ + SDMMC_PRG_ST, /*!< Programming State */ + SDMMC_DIS_ST /*!< Disconnect State */ +} SDMMC_STATE_T; + +/* Function prototype for event setup function */ +typedef void (*SDMMC_EVSETUP_FUNC_T)(void *); + +/* Function prototype for wait for event function */ +typedef uint32_t (*SDMMC_EVWAIT_FUNC_T)(void); + +/* Function prototype for milliSecond delay function */ +typedef void (*SDMMC_MSDELAY_FUNC_T)(uint32_t); + +/** + * @brief SD/MMC Card specific setup data structure + */ +typedef struct { + uint32_t response[4]; /*!< Most recent response */ + uint32_t cid[4]; /*!< CID of acquired card */ + uint32_t csd[4]; /*!< CSD of acquired card */ + uint32_t ext_csd[512 / 4]; /*!< Ext CSD */ + uint32_t card_type; /*!< Card Type */ + uint16_t rca; /*!< Relative address assigned to card */ + uint32_t speed; /*!< Speed */ + uint32_t block_len; /*!< Card sector size */ + uint64_t device_size; /*!< Device Size */ + uint32_t blocknr; /*!< Block Number */ + uint32_t clk_rate; /*! Clock rate */ + SDMMC_EVSETUP_FUNC_T evsetup_cb; /*!< Function to setup event information */ + SDMMC_EVWAIT_FUNC_T waitfunc_cb; /*!< Function to wait for event */ + SDMMC_MSDELAY_FUNC_T msdelay_func; /*!< Function to sleep in ms */ +} SDMMC_CARD_T; + +/** + * @brief SD/MMC commands, arguments and responses + * Standard SD/MMC commands (3.1) type argument response + */ +/* class 1 */ +#define MMC_GO_IDLE_STATE 0 /* bc */ +#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ +#define MMC_ALL_SEND_CID 2 /* bcr R2 */ +#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ +#define MMC_SET_DSR 4 /* bc [31:16] RCA */ +#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ +#define MMC_SEND_EXT_CSD 8 /* bc R1 */ +#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ +#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ +#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ +#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ +#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ + +/* class 2 */ +#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ +#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ +#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ + +/* class 3 */ +#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ + +/* class 4 */ +#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ +#define MMC_PROGRAM_CID 26 /* adtc R1 */ +#define MMC_PROGRAM_CSD 27 /* adtc R1 */ + +/* class 6 */ +#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ +#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ +#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ + +/* class 5 */ +#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ +#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ +#define MMC_ERASE 37 /* ac R1b */ +#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */ +#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */ +#define SD_ERASE 38 /* ac R1b */ + +/* class 9 */ +#define MMC_FAST_IO 39 /* ac R4 */ +#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ + +/* class 7 */ +#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ + +/* class 8 */ +#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ +#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */ + +/* SD commands type argument response */ +/* class 8 */ +/* This is basically the same command as for MMC with some quirks. */ +#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */ +#define SD_CMD8 8 /* bcr [31:0] OCR R3 */ + +/* Application commands */ +#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ +#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */ +#define SD_APP_SEND_SCR 51 /* adtc R1 */ + +/** + * @brief MMC status in R1
+ * Type
+ * e : error bit
+ * s : status bit
+ * r : detected and set for the actual command response
+ * x : detected and set during command execution. the host must poll + * the card by sending status command in order to read these bits. + * Clear condition
+ * a : according to the card state
+ * b : always related to the previous command. Reception of + * a valid command will clear it (with a delay of one command)
+ * c : clear by read
+ */ + +#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */ +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ +#define R1_CC_ERROR (1 << 20) /* erx, c */ +#define R1_ERROR (1 << 19) /* erx, c */ +#define R1_UNDERRUN (1 << 18) /* ex, c */ +#define R1_OVERRUN (1 << 17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ +#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_STATUS(x) (x & 0xFFFFE000) +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ +#define R1_APP_CMD (1 << 5) /* sr, c */ + +/** + * @brief SD/MMC card OCR register bits + */ +#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */ +#define OCR_HC_CCS (1 << 30) /* High capacity card */ +#define OCR_VOLTAGE_RANGE_MSK (0x00FF8000) + +#define SD_SEND_IF_ARG 0x000001AA +#define SD_SEND_IF_ECHO_MSK 0x000000FF +#define SD_SEND_IF_RESP 0x000000AA + +/** + * @brief R3 response definitions + */ +#define CMDRESP_R3_OCR_VAL(n) (((uint32_t) n) & 0xFFFFFF) +#define CMDRESP_R3_S18A (((uint32_t) 1 ) << 24) +#define CMDRESP_R3_HC_CCS (((uint32_t) 1 ) << 30) +#define CMDRESP_R3_INIT_COMPLETE (((uint32_t) 1 ) << 31) + +/** + * @brief R6 response definitions + */ +#define CMDRESP_R6_RCA_VAL(n) (((uint32_t) (n >> 16)) & 0xFFFF) +#define CMDRESP_R6_CARD_STATUS(n) (((uint32_t) (n & 0x1FFF)) | \ + ((n & (1 << 13)) ? (1 << 19) : 0) | \ + ((n & (1 << 14)) ? (1 << 22) : 0) | \ + ((n & (1 << 15)) ? (1 << 23) : 0)) + +/** + * @brief R7 response definitions + */ +/** Echo-back of check-pattern */ +#define CMDRESP_R7_CHECK_PATTERN(n) (((uint32_t) n ) & 0xFF) +/** Voltage accepted */ +#define CMDRESP_R7_VOLTAGE_ACCEPTED (((uint32_t) 1 ) << 8) + +/** + * @brief CMD3 command definitions + */ +/** Card Address */ +#define CMD3_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16) + +/** + * @brief CMD7 command definitions + */ +/** Card Address */ +#define CMD7_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16) + +/** + * @brief CMD8 command definitions + */ +/** Check pattern */ +#define CMD8_CHECKPATTERN(n) (((uint32_t) (n & 0xFF) ) << 0) +/** Recommended pattern */ +#define CMD8_DEF_PATTERN (0xAA) +/** Voltage supplied.*/ +#define CMD8_VOLTAGESUPPLIED_27_36 (((uint32_t) 1 ) << 8) + +/** + * @brief CMD9 command definitions + */ +#define CMD9_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16) + +/** + * @brief CMD13 command definitions + */ +#define CMD13_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16) + +/** + * @brief APP_CMD command definitions + */ +#define CMD55_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16) + +/** + * @brief ACMD41 command definitions + */ +#define ACMD41_OCR(n) (((uint32_t) n) & 0xFFFFFF) +#define ACMD41_S18R (((uint32_t) 1 ) << 24) +#define ACMD41_XPC (((uint32_t) 1 ) << 28) +#define ACMD41_HCS (((uint32_t) 1 ) << 30) + +/** + * @brief ACMD6 command definitions + */ +#define ACMD6_BUS_WIDTH(n) ((uint32_t) n & 0x03) +#define ACMD6_BUS_WIDTH_1 (0) +#define ACMD6_BUS_WIDTH_4 (2) + +/** @brief Card type defines + */ +#define CARD_TYPE_SD (1 << 0) +#define CARD_TYPE_4BIT (1 << 1) +#define CARD_TYPE_8BIT (1 << 2) +#define CARD_TYPE_HC (OCR_HC_CCS)/*!< high capacity card > 2GB */ + +/** + * @brief SD/MMC sector size in bytes + */ +#define MMC_SECTOR_SIZE 512 + +/** + * @brief Typical enumeration clock rate + */ +#define SD_MMC_ENUM_CLOCK 400000 + +/** + * @brief Max MMC clock rate + */ +#define MMC_MAX_CLOCK 20000000 + +/** + * @brief Type 0 MMC card max clock rate + */ +#define MMC_LOW_BUS_MAX_CLOCK 26000000 + +/** + * @brief Type 1 MMC card max clock rate + */ +#define MMC_HIGH_BUS_MAX_CLOCK 52000000 + +/** + * @brief Max SD clock rate + */ +#define SD_MAX_CLOCK 25000000 + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __SDMMC_H */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h new file mode 100644 index 0000000000000..4e8980912c2f4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h @@ -0,0 +1,157 @@ +/* + * @brief LPC18xx/43xx SD/MMC card driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDMMC_18XX_43XX_H_ +#define __SDMMC_18XX_43XX_H_ + +#include "sdmmc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/MMC driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define CMD_MASK_RESP (0x3UL << 28) +#define CMD_RESP(r) (((r) & 0x3) << 28) +#define CMD_RESP_R0 (0 << 28) +#define CMD_RESP_R1 (1 << 28) +#define CMD_RESP_R2 (2 << 28) +#define CMD_RESP_R3 (3 << 28) +#define CMD_BIT_AUTO_STOP (1 << 24) +#define CMD_BIT_APP (1 << 23) +#define CMD_BIT_INIT (1 << 22) +#define CMD_BIT_BUSY (1 << 21) +#define CMD_BIT_LS (1 << 20) /* Low speed, used during acquire */ +#define CMD_BIT_DATA (1 << 19) +#define CMD_BIT_WRITE (1 << 18) +#define CMD_BIT_STREAM (1 << 17) +#define CMD_MASK_CMD (0xff) +#define CMD_SHIFT_CMD (0) + +#define CMD(c, r) ( ((c) & CMD_MASK_CMD) | CMD_RESP((r)) ) + +#define CMD_IDLE CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS | CMD_BIT_INIT +#define CMD_SD_OP_COND CMD(SD_APP_OP_COND, 1) | CMD_BIT_LS | CMD_BIT_APP +#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1) | CMD_BIT_LS +#define CMD_MMC_OP_COND CMD(MMC_SEND_OP_COND, 3) | CMD_BIT_LS | CMD_BIT_INIT +#define CMD_ALL_SEND_CID CMD(MMC_ALL_SEND_CID, 2) | CMD_BIT_LS +#define CMD_MMC_SET_RCA CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS +#define CMD_SD_SEND_RCA CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS +#define CMD_SEND_CSD CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS +#define CMD_SEND_EXT_CSD CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA +#define CMD_DESELECT_CARD CMD(MMC_SELECT_CARD, 0) +#define CMD_SELECT_CARD CMD(MMC_SELECT_CARD, 1) +#define CMD_SET_BLOCKLEN CMD(MMC_SET_BLOCKLEN, 1) +#define CMD_SEND_STATUS CMD(MMC_SEND_STATUS, 1) +#define CMD_READ_SINGLE CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA +#define CMD_READ_MULTIPLE CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP +#define CMD_SD_SET_WIDTH CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP +#define CMD_STOP CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY +#define CMD_WRITE_SINGLE CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE +#define CMD_WRITE_MULTIPLE CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP + +/* Card specific setup data */ +typedef struct _mci_card_struct { + sdif_device sdif_dev; + SDMMC_CARD_T card_info; +} mci_card_struct; + +/** + * @brief Get card's current state (idle, transfer, program, etc.) + * @param pSDMMC : SDMMC peripheral selected + * @return Current SD card transfer state + */ +int32_t Chip_SDMMC_GetState(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Function to enumerate the SD/MMC/SDHC/MMC+ cards + * @param pSDMMC : SDMMC peripheral selected + * @param pcardinfo : Pointer to pre-allocated card info structure + * @return 1 if a card is acquired, otherwise 0 + */ +uint32_t Chip_SDMMC_Acquire(LPC_SDMMC_T *pSDMMC, mci_card_struct *pcardinfo); + +/** + * @brief Get the device size of SD/MMC card (after enumeration) + * @param pSDMMC : SDMMC peripheral selected + * @return Card size in number of bytes (capacity) + */ +uint64_t Chip_SDMMC_GetDeviceSize(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Get the number of device blocks of SD/MMC card (after enumeration) + * Since Chip_SDMMC_GetDeviceSize is limited to 32 bits cards with greater than + * 2 GBytes of data will not be correct, in such cases users can use this function + * to get the size of the card in blocks. + * @param pSDMMC : SDMMC peripheral selected + * @return Number of 512 bytes blocks in the card + */ +int32_t Chip_SDMMC_GetDeviceBlocks(LPC_SDMMC_T *pSDMMC); + +/** + * @brief Performs the read of data from the SD/MMC card + * @param pSDMMC : SDMMC peripheral selected + * @param buffer : Pointer to data buffer to copy to + * @param start_block : Start block number + * @param num_blocks : Number of block to read + * @return Bytes read, or 0 on error + */ +int32_t Chip_SDMMC_ReadBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks); + +/** + * @brief Performs write of data to the SD/MMC card + * @param pSDMMC : SDMMC peripheral selected + * @param buffer : Pointer to data buffer to copy to + * @param start_block : Start block number + * @param num_blocks : Number of block to write + * @return Number of bytes actually written, or 0 on error + */ +int32_t Chip_SDMMC_WriteBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/sgpio_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/sgpio_18xx_43xx.h new file mode 100644 index 0000000000000..fb4111a2ae844 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/sgpio_18xx_43xx.h @@ -0,0 +1,114 @@ +/* + * @brief LPC43xx Serial GPIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SGPIO_43XX_H_ +#define __SGPIO_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SGPIO_43XX CHIP: LPC43xx Serial GPIO driver + * @ingroup LPC_CHIP_18XX_43XX_Drivers + * This module is present in LPC43xx MCUs only. + * @{ + */ + +#if defined(CHIP_LPC43XX) + +/** + * @brief Serial GPIO register block structure + */ +typedef struct { /*!< SGPIO Structure */ + __IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */ + __IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */ + __IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */ + __IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */ + __IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */ + __IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */ + __IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */ + __IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */ + __IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */ + __IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */ + __IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */ + __IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */ + __I uint32_t GPIO_INREG; /*!< GPIO input status register */ + __IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */ + __IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */ + __IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */ + __IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */ + __I uint32_t RESERVED0[823]; + __O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */ + __O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */ + __I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */ + __I uint32_t STATUS_0; /*!< Shift clock interrupt status */ + __O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */ + __O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */ + __I uint32_t RESERVED1[2]; + __O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */ + __O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */ + __I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */ + __I uint32_t STATUS_1; /*!< Capture clock interrupt status */ + __O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */ + __O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */ + __I uint32_t RESERVED2[2]; + __O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */ + __O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */ + __I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */ + __I uint32_t STATUS_2; /*!< Pattern match interrupt status */ + __O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */ + __O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */ + __I uint32_t RESERVED3[2]; + __O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */ + __O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */ + __I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */ + __I uint32_t STATUS_3; /*!< Input bit match interrupt status */ + __O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */ + __O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */ +} LPC_SGPIO_T; + +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SGPIO_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/spi_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/spi_18xx_43xx.h new file mode 100644 index 0000000000000..97f484775ff7e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/spi_18xx_43xx.h @@ -0,0 +1,422 @@ +/* + * @brief LPC43xx SPI driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPI_43XX_H_ +#define __SPI_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SPI_43XX CHIP: LPC43xx SPI driver + * @ingroup CHIP_18XX_43XX_Drivers + * This module is present in LPC43xx MCUs only. + * @{ + */ +#if defined(CHIP_LPC43XX) + +/** + * @brief SPI register block structure + */ +typedef struct { /*!< SPI Structure */ + __IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */ + __I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */ + __IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */ + __IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */ + __I uint32_t RESERVED0[3]; + __IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */ +} LPC_SPI_T; + +/* + * Macro defines for SPI Control register + */ +/* SPI CFG Register BitMask */ +#define SPI_CR_BITMASK ((uint32_t) 0xFFC) +/** Enable of controlling the number of bits per transfer */ +#define SPI_CR_BIT_EN ((uint32_t) (1 << 2)) +/** Mask of field of bit controlling */ +#define SPI_CR_BITS_MASK ((uint32_t) 0xF00) +/** Set the number of bits per a transfer */ +#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */ +/** SPI Clock Phase Select*/ +#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/ +#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/ +/** SPI Clock Polarity Select*/ +#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/ +#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/ +/** SPI Slave Mode Select */ +#define SPI_CR_SLAVE_EN ((uint32_t) 0) +/** SPI Master Mode Select */ +#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5)) +/** SPI MSB First mode enable */ +#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/ +/** SPI LSB First mode enable */ +#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/ +/** SPI interrupt enable */ +#define SPI_CR_INT_EN ((uint32_t) (1 << 7)) + +/* + * Macro defines for SPI Status register + */ +/** SPI STAT Register BitMask */ +#define SPI_SR_BITMASK ((uint32_t) 0xF8) +/** Slave abort Flag */ +#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */ +/* Mode fault Flag */ +#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */ +/** Read overrun flag*/ +#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */ +/** Write collision flag. */ +#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */ +/** SPI transfer complete flag. */ +#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */ +/** SPI error flag */ +#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL) +/* + * Macro defines for SPI Test Control Register register + */ +/*Enable SPI Test Mode */ +#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1)) + +/* + * Macro defines for SPI Interrupt register + */ +/** SPI interrupt flag */ +#define SPI_INT_SPIF ((uint32_t) (1 << 0)) + +/** + * Macro defines for SPI Data register + */ +/** Receiver Data */ +#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF)) + +/** @brief SPI Mode*/ +typedef enum { + SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */ + SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */ +} SPI_MODE_T; + +/** @brief SPI Clock Mode*/ +typedef enum { + SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */ + SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */ + SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */ + SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */ + SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */ + SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */ + SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */ + SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */ +} SPI_CLOCK_MODE_T; + +/** @brief SPI Data Order Mode*/ +typedef enum { + SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */ + SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */ +} SPI_DATA_ORDER_T; + +/* + * @brief Number of bits per frame + */ +typedef enum { + SPI_BITS_8 = SPI_CR_BITS(8), /**< 8 bits/frame */ + SPI_BITS_9 = SPI_CR_BITS(9), /**< 9 bits/frame */ + SPI_BITS_10 = SPI_CR_BITS(10), /**< 10 bits/frame */ + SPI_BITS_11 = SPI_CR_BITS(11), /**< 11 bits/frame */ + SPI_BITS_12 = SPI_CR_BITS(12), /**< 12 bits/frame */ + SPI_BITS_13 = SPI_CR_BITS(13), /**< 13 bits/frame */ + SPI_BITS_14 = SPI_CR_BITS(14), /**< 14 bits/frame */ + SPI_BITS_15 = SPI_CR_BITS(15), /**< 15 bits/frame */ + SPI_BITS_16 = SPI_CR_BITS(16), /**< 16 bits/frame */ +} SPI_BITS_T; + +/** SPI callback function type*/ +typedef void (*SPI_CALLBACK_T)(void); +/* + * @brief SPI config format + */ +typedef struct { + SPI_BITS_T bits; /*!< bits/frame */ + SPI_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */ + SPI_DATA_ORDER_T dataOrder; /*!< Data order (MSB first/LSB first) */ +} SPI_CONFIG_FORMAT_T; + +/* + * @brief SPI data setup structure + */ +typedef struct { + uint8_t *pTxData; /*!< Pointer to transmit data */ + uint8_t *pRxData; /*!< Pointer to receive data */ + uint32_t cnt; /*!< Transfer counter */ + uint32_t length; /*!< Length of transfer data */ + SPI_CALLBACK_T fnBefFrame; /*!< Function to call before sending frame */ + SPI_CALLBACK_T fnAftFrame; /*!< Function to call after sending frame */ + SPI_CALLBACK_T fnBefTransfer; /*!< Function to call before starting a transfer */ + SPI_CALLBACK_T fnAftTransfer; /*!< Function to call after a transfer complete */ +} SPI_DATA_SETUP_T; + +/** + * @brief Get the current status of SPI controller + * @return SPI controller status (Or-ed value of SPI_SR_*) + */ +STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI) +{ + return pSPI->SR; +} + +/** + * @brief Send SPI 16-bit data + * @param pSPI : The base of SPI peripheral on the chip + * @param data : Transmit Data + * @return Nothing + */ +STATIC INLINE void Chip_SPI_SendFrame(LPC_SPI_T *pSPI, uint16_t data) +{ + pSPI->DR = SPI_DR_DATA(data); +} + +/** + * @brief Get received SPI data + * @param pSPI : The base of SPI peripheral on the chip + * @return receive data + */ +STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI) +{ + return SPI_DR_DATA(pSPI->DR); +} + +/** + * @brief Set up output clocks per bit for SPI bus + * @param pSPI : The base of SPI peripheral on the chip + * @param counter : the number of SPI peripheral clock cycles that make up an SPI clock + * @return Nothing + * @note The counter must be an even number greater than or equal to 8.
+ * The SPI SCK rate = PCLK_SPI / counter. + */ +STATIC INLINE void Chip_SPI_SetClockCounter(LPC_SPI_T *pSPI, uint32_t counter) +{ + pSPI->CCR = counter; +} + +/** + * @brief Set up the SPI frame format + * @param pSPI : The base SPI peripheral on the chip + * @param format : Pointer to Frame format structure + * @return Nothing + */ +STATIC INLINE void Chip_SPI_SetFormat(LPC_SPI_T *pSPI, SPI_CONFIG_FORMAT_T *format) +{ + pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | format->bits | format->clockMode | format->dataOrder; +} + +/** + * @brief Get the number of bits transferred in each frame + * @param pSPI : The base of SPI peripheral on the chip + * @return the number of bits transferred in each frame + */ +STATIC INLINE SPI_BITS_T Chip_SPI_GetDataSize(LPC_SPI_T *pSPI) +{ + return (pSPI->CR & SPI_CR_BIT_EN) ? ((SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8; +} + +/** + * @brief Get the current CPHA & CPOL setting + * @param pSPI : The base of SPI peripheral on the chip + * @return CPHA & CPOL setting + */ +STATIC INLINE SPI_CLOCK_MODE_T Chip_SPI_GetClockMode(LPC_SPI_T *pSPI) +{ + return (SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3)); +} + +/** + * @brief Set the SPI working as master or slave mode + * @param pSPI : The base of SPI peripheral on the chip + * @return Operating mode + */ +STATIC INLINE SPI_MODE_T Chip_SPI_GetMode(LPC_SPI_T *pSPI) +{ + return (SPI_MODE_T) (pSPI->CR & (1 << 5)); +} + +/** + * @brief Set the SPI operating modes, master or slave + * @param pSPI : The base SPI peripheral on the chip + * @param mode : master mode/slave mode + * @return Nothing + */ +STATIC INLINE void Chip_SPI_SetMode(LPC_SPI_T *pSPI, SPI_MODE_T mode) +{ + pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode; +} + +/** + * @brief Set the clock frequency for SPI interface + * @param pSPI : The base SPI peripheral on the chip + * @param bitRate : The SPI bit rate + * @return Nothing + */ +void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate); + +/** + * @brief Enable SPI interrupt + * @param pSPI : The base SPI peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SPI_Int_Enable(LPC_SPI_T *pSPI) +{ + pSPI->CR |= SPI_CR_INT_EN; +} + +/** + * @brief Disable SPI interrupt + * @param pSPI : The base SPI peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SPI_Int_Disable(LPC_SPI_T *pSPI) +{ + pSPI->CR &= ~SPI_CR_INT_EN; +} + +/** + * @brief Get the interrupt status + * @param pSPI : The base of SPI peripheral on the chip + * @return SPI interrupt Status (Or-ed bit value of SPI_INT_*) + */ +STATIC INLINE uint32_t Chip_SPI_Int_GetStatus(LPC_SPI_T *pSPI) +{ + return pSPI->INT; +} + +/** + * @brief Clear the interrupt status + * @param pSPI : The base of SPI peripheral on the chip + * @param mask : SPI interrupt mask (Or-ed bit value of SPI_INT_*) + * @return Nothing + */ +STATIC INLINE void Chip_SPI_Int_ClearStatus(LPC_SPI_T *pSPI, uint32_t mask) +{ + pSPI->INT = mask; +} + +/** + * @brief Initialize the SPI + * @param pSPI : The base SPI peripheral on the chip + * @return Nothing + */ +void Chip_SPI_Init(LPC_SPI_T *pSPI); + +/** + * @brief Deinitialise the SPI + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note The SPI controller is disabled + */ +void Chip_SPI_DeInit(LPC_SPI_T *pSPI); + +/** + * @brief Clean all data in RX FIFO of SPI + * @param pSPI : The base SPI peripheral on the chip + * @return Nothing + */ +void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI); + +/** + * @brief SPI Interrupt Read/Write with 8-bit frame width + * @param pSPI : The base SPI peripheral on the chip + * @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup); + +/** + * @brief SPI Interrupt Read/Write with 16-bit frame width + * @param pSPI : The base SPI peripheral on the chip + * @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup); + +/** + * @brief SPI Polling Read/Write in blocking mode + * @param pSPI : The base SPI peripheral on the chip + * @param pXfSetup : Pointer to a SPI_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. It starts with writing phase and after that, + * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared + * through xf_setup param. + */ +uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup); + +/** + * @brief SPI Polling Write in blocking mode + * @param pSPI : The base SPI peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : Buffer length + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. First, a writing operation will send + * the needed data. After that, a dummy reading operation is generated to clear data buffer + */ +uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len); + +/** + * @brief SPI Polling Read in blocking mode + * @param pSPI : The base SPI peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : The length of buffer + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. First, a dummy writing operation is generated + * to clear data buffer. After that, a reading operation will receive the needed data + */ +uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len); + +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/spifi_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/spifi_18xx_43xx.h new file mode 100644 index 0000000000000..20055871427fd --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/spifi_18xx_43xx.h @@ -0,0 +1,355 @@ +/* + * @brief LPCSPIFILIB hardware definitions and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPIFILIB_CHIPHW_H_ +#define __SPIFILIB_CHIPHW_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define for inline */ +#ifndef INLINE +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif /* __CC_ARM */ +#endif /* !INLINE */ + +#ifdef __CC_ARM +#pragma anon_unions +#endif +/** @defgroup LPCSPIFILIB_HW_API LPCSPIFILIB hardware definitions and API functions + * @ingroup LPCSPIFILIB + * @{ + */ + +/** + * @brief SPIFI controller hardware register structure + */ + +typedef struct LPC_SPIFI_CHIPHW { + volatile uint32_t CTRL; /**< SPIFI control register */ + volatile uint32_t CMD; /**< SPIFI command register */ + volatile uint32_t ADDR; /**< SPIFI address register */ + volatile uint32_t DATINTM; /**< SPIFI intermediate data register */ + volatile uint32_t CACHELIMIT; /**< SPIFI cache limit register */ + union { + volatile uint8_t DAT8; /**< SPIFI 8 bit data */ + volatile uint16_t DAT16; /**< SPIFI 16 bit data */ + volatile uint32_t DAT32; /**< SPIFI 32 bit data */ + }; + + volatile uint32_t MEMCMD; /**< SPIFI memory command register */ + volatile uint32_t STAT; /**< SPIFI status register */ +} LPC_SPIFI_T; + +/** @defgroup LPCSPIFILIB_HW_PRIM LPCSPIFILIB primative API functions + * @{ + */ + +/** + * @brief SPIFI controller control register bit definitions + */ +#define SPIFI_CTRL_TO(t) ((t) << 0) /**< SPIFI timeout */ +#define SPIFI_CTRL_CSHI(c) ((c) << 16) /**< SPIFI chip select minimum high time */ +#define SPIFI_CTRL_DATA_PREFETCH_DISABLE(d) ((d) << 21) /**< SPIFI memMode prefetch enable*/ +#define SPIFI_CTRL_INTEN(i) ((i) << 22) /**< SPIFI cmdComplete irq enable */ +#define SPIFI_CTRL_MODE3(m) ((m) << 23) /**< SPIFI mode3 config */ +#define SPIFI_CTRL_PREFETCH_DISABLE(d) ((d) << 27) /**< SPIFI cache prefetch enable */ +#define SPIFI_CTRL_DUAL(d) ((d) << 28) /**< SPIFI enable dual */ +#define SPIFI_CTRL_RFCLK(m) ((m) << 29) /**< SPIFI clock edge config */ +#define SPIFI_CTRL_FBCLK(m) ((m) << 30) /**< SPIFI feedback clock select */ +#define SPIFI_CTRL_DMAEN(m) ((m) << 31) /**< SPIFI dma enable */ + +/** + * @brief Write SPIFI controller control register + * @param pSpifi : Base address of SPIFI controller + * @param ctrl : Control value to write + * @return Nothing + */ +static INLINE void spifi_HW_SetCtrl(LPC_SPIFI_T *pSpifi, uint32_t ctrl) +{ + pSpifi->CTRL = ctrl; +} + +/** + * @brief Read SPIFI controller control register + * @param pSpifi : Base address of SPIFI controller + * @return Current CTRL register values + */ +static INLINE uint32_t spifi_HW_GetCtrl(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->CTRL; +} + +/** + * @brief SPIFI controller status register bit definitions + */ +#define SPIFI_STAT_RESET (1 << 4) /**< SPIFI reset */ +#define SPIFI_STAT_INTRQ (1 << 5) /**< SPIFI interrupt request */ +#define SPIFI_STAT_CMD (1 << 1) /**< SPIFI command in progress */ +#define SPIFI_STAT_MCINIT (1) /**< SPIFI MCINIT */ + +/** + * @brief Write SPIFI controller status register + * @param pSpifi : Base address of SPIFI controller + * @param stat : Status bits to write + * @return Nothing + */ +static INLINE void spifi_HW_SetStat(LPC_SPIFI_T *pSpifi, uint32_t stat) +{ + pSpifi->STAT = stat; +} + +/** + * @brief Read SPIFI controller status register + * @param pSpifi : Base address of SPIFI controller + * @return Current STAT register values + */ +static INLINE uint32_t spifi_HW_GetStat(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->STAT; +} + +/** + * @brief SPIFI controller command register bit definitions + */ +#define SPIFI_CMD_DATALEN(l) ((l) << 0) /**< SPIFI bytes to send or receive */ +#define SPIFI_CMD_POLLRS(p) ((p) << 14) /**< SPIFI enable poll */ +#define SPIFI_CMD_DOUT(d) ((d) << 15) /**< SPIFI data direction is out */ +#define SPIFI_CMD_INTER(i) ((i) << 16) /**< SPIFI intermediate bit length */ +#define SPIFI_CMD_FIELDFORM(p) ((p) << 19) /**< SPIFI 2 bit data/cmd mode control */ +#define SPIFI_CMD_FRAMEFORM(f) ((f) << 21) /**< SPIFI op and adr field config */ +#define SPIFI_CMD_OPCODE(o) ((uint32_t) (o) << 24) /**< SPIFI 8-bit command code */ + +/** + * @brief frame form definitions + */ +typedef enum { + SPIFI_FRAMEFORM_OP = 1, + SPIFI_FRAMEFORM_OP_1ADDRESS = 2, + SPIFI_FRAMEFORM_OP_2ADDRESS = 3, + SPIFI_FRAMEFORM_OP_3ADDRESS = 4, + SPIFI_FRAMEFORM_OP_4ADDRESS = 5, + SPIFI_FRAMEFORM_NOOP_3ADDRESS = 6, + SPIFI_FRAMEFORM_NOOP_4ADDRESS = 7 +} SPIFI_FRAMEFORM_T; + +/** + * @brief serial type definitions + */ +typedef enum { + SPIFI_FIELDFORM_ALL_SERIAL = 0, + SPIFI_FIELDFORM_SERIAL_OPCODE_ADDRESS = 1, + SPIFI_FIELDFORM_SERIAL_OPCODE = 2, + SPIFI_FIELDFORM_NO_SERIAL = 3 +} SPIFI_FIELDFORM_T; + +/** + * @brief Read SPIFI controller command register + * @param pSpifi : Base address of SPIFI controller + * @return 32-bit value read from the command register + */ +static INLINE uint32_t spifi_HW_GetCmd(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->CMD; +} + +/** + * @brief Write SPIFI controller command register + * @param pSpifi : Base address of SPIFI controller + * @param cmd : Command to write + * @return Nothing + */ +static INLINE void spifi_HW_SetCmd(LPC_SPIFI_T *pSpifi, uint32_t cmd) +{ + pSpifi->CMD = cmd; +} + +/** + * @brief Write SPIFI controller address register + * @param pSpifi : Base address of SPIFI controller + * @param addr : address (offset) to write + * @return Nothing + */ +static INLINE void spifi_HW_SetAddr(LPC_SPIFI_T *pSpifi, uint32_t addr) +{ + pSpifi->ADDR = addr; +} + +/** + * @brief Read an 8-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @return 8-bit value read from the data register + */ +static INLINE uint8_t spifi_HW_GetData8(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->DAT8; +} + +/** + * @brief Read an 16-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @return 16-bit value read from the data register + */ +static INLINE uint16_t spifi_HW_GetData16(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->DAT16; +} + +/** + * @brief Read an 32-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @return 32-bit value read from the data register + */ +static INLINE uint32_t spifi_HW_GetData32(LPC_SPIFI_T *pSpifi) +{ + return pSpifi->DAT32; +} + +/** + * @brief Write an 8-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @param data : 8-bit data value to write + * @return Nothing + */ +static INLINE void spifi_HW_SetData8(LPC_SPIFI_T *pSpifi, uint8_t data) +{ + pSpifi->DAT8 = data; +} + +/** + * @brief Write an 16-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @param data : 16-bit data value to write + * @return Nothing + */ +static INLINE void spifi_HW_SetData16(LPC_SPIFI_T *pSpifi, uint16_t data) +{ + pSpifi->DAT16 = data; +} + +/** + * @brief Write an 32-bit value from the controller data register + * @param pSpifi : Base address of SPIFI controller + * @param data : 32-bit data value to write + * @return Nothing + */ +static INLINE void spifi_HW_SetData32(LPC_SPIFI_T *pSpifi, uint32_t data) +{ + pSpifi->DAT32 = data; +} + +/** + * @brief Write IDATA register + * @param pSpifi : Base address of SPIFI controller + * @param mode : value to write. Used to specify value used for intermediate + data value when enabled. + * @return Nothing + */ +static INLINE void spifi_HW_SetIDATA(LPC_SPIFI_T *pSpifi, uint32_t mode) +{ + pSpifi->DATINTM = mode; +} + +/** + * @brief Write MEMCMD register + * @param pSpifi : Base address of SPIFI controller + * @param cmd : Command value to write + * @return Nothing + */ +static INLINE void spifi_HW_SetMEMCMD(LPC_SPIFI_T *pSpifi, uint32_t cmd) +{ + pSpifi->MEMCMD = cmd; +} + +/** + * @} + */ + +/** @defgroup LPCSPIFILIB_HW_L2 LPCSPIFILIB hardware support API functions + * @{ + */ + +/** + * @brief Reset SPIFI controller + * @param pSpifi : Base address of SPIFI controller + * @return Nothing + */ +static INLINE void spifi_HW_ResetController(LPC_SPIFI_T *pSpifi) +{ + pSpifi->STAT = SPIFI_STAT_RESET; + while ((pSpifi->STAT & SPIFI_STAT_RESET) != 0) {} +} + +/** + * @brief Wait for a command to complete + * @param pSpifi : Base address of SPIFI controller + * @return Nothing + */ +static INLINE void spifi_HW_WaitCMD(LPC_SPIFI_T *pSpifi) +{ + while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_CMD) != 0) {} +} + +/** + * @brief Wait for a RESET bit to clear + * @param pSpifi : Base address of SPIFI controller + * @return Nothing + */ +static INLINE void spifi_HW_WaitRESET(LPC_SPIFI_T *pSpifi) +{ + while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_RESET) != 0) {} +} + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIFILIB_CHIPHW_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/ssp_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/ssp_18xx_43xx.h new file mode 100644 index 0000000000000..edef017a9140a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/ssp_18xx_43xx.h @@ -0,0 +1,604 @@ +/* + * @brief LPC18xx/43xx SSP driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SSP_18XX_43XX_H_ +#define __SSP_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief SSP register block structure + */ +typedef struct { /*!< SSPn Structure */ + __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */ + __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< Status Register */ + __IO uint32_t CPSR; /*!< Clock Prescale Register */ + __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< SSPn DMA control register */ +} LPC_SSP_T; + +/** + * Macro defines for CR0 register + */ + +/** SSP data size select, must be 4 bits to 16 bits */ +#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF)) +/** SSP control 0 Motorola SPI mode */ +#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) +/** SSP control 0 TI synchronous serial mode */ +#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) +/** SSP control 0 National Micro-wire mode */ +#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) +/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the + bus clock high between frames, (0) = low */ +#define SSP_CR0_CPOL_LO ((uint32_t) (0)) +#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6)) +/** SPI clock out phase bit (used in SPI mode only), (1) = captures data + on the second clock transition of the frame, (0) = first */ +#define SSP_CR0_CPHA_FIRST ((uint32_t) (0)) +#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7)) +/** SSP serial clock rate value load macro, divider rate is + PERIPH_CLK / (cpsr * (SCR + 1)) */ +#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) +/** SSP CR0 bit mask */ +#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) +/** SSP CR0 bit mask */ +#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) +/** SSP serial clock rate value load macro, divider rate is + PERIPH_CLK / (cpsr * (SCR + 1)) */ +#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) + +/** + * Macro defines for CR1 register + */ + +/** SSP control 1 loopback mode enable bit */ +#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) +/** SSP control 1 enable bit */ +#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) +/** SSP control 1 slave enable */ +#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) +#define SSP_CR1_MASTER_EN ((uint32_t) (0)) +/** SSP control 1 slave out disable bit, disables transmit line in slave + mode */ +#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) +/** SSP CR1 bit mask */ +#define SSP_CR1_BITMASK ((uint32_t) (0x0F)) + +/** SSP CPSR bit mask */ +#define SSP_CPSR_BITMASK ((uint32_t) (0xFF)) +/** + * Macro defines for DR register + */ + +/** SSP data bit mask */ +#define SSP_DR_BITMASK(n) ((n) & 0xFFFF) + +/** + * Macro defines for SR register + */ + +/** SSP SR bit mask */ +#define SSP_SR_BITMASK ((uint32_t) (0x1F)) + +/** ICR bit mask */ +#define SSP_ICR_BITMASK ((uint32_t) (0x03)) + +/** + * @brief SSP Type of Status + */ +typedef enum _SSP_STATUS { + SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */ + SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */ + SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */ + SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */ + SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */ +} SSP_STATUS_T; + +/** + * @brief SSP Type of Interrupt Mask + */ +typedef enum _SSP_INTMASK { + SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */ + SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */ + SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */ + SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)), +} SSP_INTMASK_T; + +/** + * @brief SSP Type of Mask Interrupt Status + */ +typedef enum _SSP_MASKINTSTATUS { + SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */ + SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */ + SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */ + SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)), +} SSP_MASKINTSTATUS_T; + +/** + * @brief SSP Type of Raw Interrupt Status + */ +typedef enum _SSP_RAWINTSTATUS { + SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */ + SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */ + SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */ + SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)), +} SSP_RAWINTSTATUS_T; + +typedef enum _SSP_INTCLEAR { + SSP_RORIC = 0x0, + SSP_RTIC = 0x1, + SSP_INT_CLEAR_BITMASK = 0x3, +} SSP_INTCLEAR_T; + +typedef enum _SSP_DMA { + SSP_DMA_RX = (1u), /**< DMA RX Enable */ + SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */ + SSP_DMA_BITMASK = ((uint32_t)(0x3)), +} SSP_DMA_T; + +/* + * @brief SSP clock format + */ +typedef enum CHIP_SSP_CLOCK_FORMAT { + SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */ + SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */ + SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */ + SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */ + SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */ + SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */ + SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */ + SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */ +} CHIP_SSP_CLOCK_MODE_T; + +/* + * @brief SSP frame format + */ +typedef enum CHIP_SSP_FRAME_FORMAT { + SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */ + CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */ + SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */ +} CHIP_SSP_FRAME_FORMAT_T; + +/* + * @brief Number of bits per frame + */ +typedef enum CHIP_SSP_BITS { + SSP_BITS_4 = (3u << 0), /*!< 4 bits/frame */ + SSP_BITS_5 = (4u << 0), /*!< 5 bits/frame */ + SSP_BITS_6 = (5u << 0), /*!< 6 bits/frame */ + SSP_BITS_7 = (6u << 0), /*!< 7 bits/frame */ + SSP_BITS_8 = (7u << 0), /*!< 8 bits/frame */ + SSP_BITS_9 = (8u << 0), /*!< 9 bits/frame */ + SSP_BITS_10 = (9u << 0), /*!< 10 bits/frame */ + SSP_BITS_11 = (10u << 0), /*!< 11 bits/frame */ + SSP_BITS_12 = (11u << 0), /*!< 12 bits/frame */ + SSP_BITS_13 = (12u << 0), /*!< 13 bits/frame */ + SSP_BITS_14 = (13u << 0), /*!< 14 bits/frame */ + SSP_BITS_15 = (14u << 0), /*!< 15 bits/frame */ + SSP_BITS_16 = (15u << 0), /*!< 16 bits/frame */ +} CHIP_SSP_BITS_T; + +/* + * @brief SSP config format + */ +typedef struct SSP_ConfigFormat { + CHIP_SSP_BITS_T bits; /*!< Format config: bits/frame */ + CHIP_SSP_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */ + CHIP_SSP_FRAME_FORMAT_T frameFormat; /*!< Format config: SPI/TI/Microwire */ +} SSP_ConfigFormat; + +/** + * @brief Enable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP) +{ + pSSP->CR1 |= SSP_CR1_SSP_EN; +} + +/** + * @brief Disable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP) +{ + pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; +} + +/** + * @brief Enable loopback mode + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + * @note Serial input is taken from the serial output (MOSI or MISO) rather + * than the serial input pin + */ +STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP) +{ + pSSP->CR1 |= SSP_CR1_LBM_EN; +} + +/** + * @brief Disable loopback mode + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + * @note Serial input is taken from the serial output (MOSI or MISO) rather + * than the serial input pin + */ +STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP) +{ + pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK; +} + +/** + * @brief Get the current status of SSP controller + * @param pSSP : The base of SSP peripheral on the chip + * @param Stat : Type of status, should be : + * - SSP_STAT_TFE + * - SSP_STAT_TNF + * - SSP_STAT_RNE + * - SSP_STAT_RFF + * - SSP_STAT_BSY + * @return SSP controller status, SET or RESET + */ +STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat) +{ + return (pSSP->SR & Stat) ? SET : RESET; +} + +/** + * @brief Get the masked interrupt status + * @param pSSP : The base of SSP peripheral on the chip + * @return SSP Masked Interrupt Status Register value + * @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked) + */ +STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP) +{ + return pSSP->MIS; +} + +/** + * @brief Get the raw interrupt status + * @param pSSP : The base of SSP peripheral on the chip + * @param RawInt : Interrupt condition to be get status, shoud be : + * - SSP_RORRIS + * - SSP_RTRIS + * - SSP_RXRIS + * - SSP_TXRIS + * @return Raw interrupt status corresponding to interrupt condition , SET or RESET + * @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled + */ +STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt) +{ + return (pSSP->RIS & RawInt) ? SET : RESET; +} + +/** + * @brief Get the number of bits transferred in each frame + * @param pSSP : The base of SSP peripheral on the chip + * @return the number of bits transferred in each frame minus one + * @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer + */ +STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP) +{ + return SSP_CR0_DSS(pSSP->CR0); +} + +/** + * @brief Clear the corresponding interrupt condition(s) in the SSP controller + * @param pSSP : The base of SSP peripheral on the chip + * @param IntClear: Type of cleared interrupt, should be : + * - SSP_RORIC + * - SSP_RTIC + * @return Nothing + * @note Software can clear one or more interrupt condition(s) in the SSP controller + */ +STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear) +{ + pSSP->ICR = IntClear; +} + +/** + * @brief Enable interrupt for the SSP + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP) +{ + pSSP->IMSC |= SSP_TXIM; +} + +/** + * @brief Disable interrupt for the SSP + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP) +{ + pSSP->IMSC &= (~SSP_TXIM); +} + +/** + * @brief Get received SSP data + * @param pSSP : The base of SSP peripheral on the chip + * @return SSP 16-bit data received + */ +STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP) +{ + return (uint16_t) (SSP_DR_BITMASK(pSSP->DR)); +} + +/** + * @brief Send SSP 16-bit data + * @param pSSP : The base of SSP peripheral on the chip + * @param tx_data : SSP 16-bit data to be transmited + * @return Nothing + */ +STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data) +{ + pSSP->DR = SSP_DR_BITMASK(tx_data); +} + +/** + * @brief Set up output clocks per bit for SSP bus + * @param pSSP : The base of SSP peripheral on the chip + * @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one + * @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK + * @return Nothing + * @note The bit frequency is PCLK / (prescale x[clk_rate+1]) + */ +void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale); + +/** + * @brief Set up the SSP frame format + * @param pSSP : The base of SSP peripheral on the chip + * @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16 + * @param frameFormat : Frame format, should be : + * - SSP_FRAMEFORMAT_SPI + * - SSP_FRAME_FORMAT_TI + * - SSP_FRAMEFORMAT_MICROWIRE + * @param clockMode : Select Clock polarity and Clock phase, should be : + * - SSP_CLOCK_CPHA0_CPOL0 + * - SSP_CLOCK_CPHA0_CPOL1 + * - SSP_CLOCK_CPHA1_CPOL0 + * - SSP_CLOCK_CPHA1_CPOL1 + * @return Nothing + * @note Note: The clockFormat is only used in SPI mode + */ +STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode) +{ + pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode; +} + +/** + * @brief Set the SSP working as master or slave mode + * @param pSSP : The base of SSP peripheral on the chip + * @param mode : Operating mode, should be + * - SSP_MODE_MASTER + * - SSP_MODE_SLAVE + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode) +{ + pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode; +} + +/** + * @brief Enable DMA for SSP + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP) +{ + pSSP->DMACR |= SSP_DMA_BITMASK; +} + +/** + * @brief Disable DMA for SSP + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP) +{ + pSSP->DMACR &= ~SSP_DMA_BITMASK; +} + +/* + * @brief SSP mode + */ +typedef enum CHIP_SSP_MODE { + SSP_MODE_MASTER = (0 << 2), /**< Master mode */ + SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */ +} CHIP_SSP_MODE_T; + +/* + * @brief SPI address + */ +typedef struct { + uint8_t port; /*!< Port Number */ + uint8_t pin; /*!< Pin number */ +} SPI_Address_t; + +/* + * @brief SSP data setup structure + */ +typedef struct { + void *tx_data; /*!< Pointer to transmit data */ + uint32_t tx_cnt; /*!< Transmit counter */ + void *rx_data; /*!< Pointer to transmit data */ + uint32_t rx_cnt; /*!< Receive counter */ + uint32_t length; /*!< Length of transfer data */ +} Chip_SSP_DATA_SETUP_T; + +/** SSP configuration parameter defines */ +/** Clock phase control bit */ +#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST +#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND + +/** Clock polarity control bit */ +/* There's no bug here!!! + * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. + * That means the active clock is in HI state. + * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock + * high between frames. That means the active clock is in LO state. + */ +#define SSP_CPOL_HI SSP_CR0_CPOL_LO +#define SSP_CPOL_LO SSP_CR0_CPOL_HI + +/** SSP master mode enable */ +#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN +#define SSP_MASTER_MODE SSP_CR1_MASTER_EN + +/** + * @brief Clean all data in RX FIFO of SSP + * @param pSSP : The base SSP peripheral on the chip + * @return Nothing + */ +void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP); + +/** + * @brief SSP Interrupt Read/Write with 8-bit frame width + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup); + +/** + * @brief SSP Interrupt Read/Write with 16-bit frame width + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup); + +/** + * @brief SSP Polling Read/Write in blocking mode + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified + * information about transmit/receive data configuration + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. It starts with writing phase and after that, + * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared + * through xf_setup param. + */ +uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup); + +/** + * @brief SSP Polling Write in blocking mode + * @param pSSP : The base SSP peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : Buffer length + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. First, a writing operation will send + * the needed data. After that, a dummy reading operation is generated to clear data buffer + */ +uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, const uint8_t *buffer, uint32_t buffer_len); + +/** + * @brief SSP Polling Read in blocking mode + * @param pSSP : The base SSP peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : The length of buffer + * @return Actual data length has been transferred + * @note + * This function can be used in both master and slave mode. First, a dummy writing operation is generated + * to clear data buffer. After that, a reading operation will receive the needed data + */ +uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len); + +/** + * @brief Initialize the SSP + * @param pSSP : The base SSP peripheral on the chip + * @return Nothing + */ +void Chip_SSP_Init(LPC_SSP_T *pSSP); + +/** + * @brief Deinitialise the SSP + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + * @note The SSP controller is disabled + */ +void Chip_SSP_DeInit(LPC_SSP_T *pSSP); + +/** + * @brief Set the SSP operating modes, master or slave + * @param pSSP : The base SSP peripheral on the chip + * @param master : 1 to set master, 0 to set slave + * @return Nothing + */ +void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master); + +/** + * @brief Set the clock frequency for SSP interface + * @param pSSP : The base SSP peripheral on the chip + * @param bitRate : The SSP bit rate + * @return Nothing + */ +void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SSP_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/stopwatch.h b/ports/lpc/chips/lpc_chip_43xx/inc/stopwatch.h new file mode 100644 index 0000000000000..af349ad825d3d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/stopwatch.h @@ -0,0 +1,143 @@ +/* + * @brief Common stopwatch support + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __STOPWATCH_H_ +#define __STOPWATCH_H_ + +#include "cmsis.h" + +/** @defgroup Stop_Watch CHIP: Stopwatch primitives. + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Initialize stopwatch + * @return Nothing + */ +void StopWatch_Init(void); + +/** + * @brief Start a stopwatch + * @return Current cycle count + */ +uint32_t StopWatch_Start(void); + +/** + * @brief Returns number of ticks elapsed since stopwatch was started + * @param startTime : Time returned by StopWatch_Start(). + * @return Number of ticks elapsed since stopwatch was started + */ +STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime) +{ + return StopWatch_Start() - startTime; +} + +/** + * @brief Returns number of ticks per second of the stopwatch timer + * @return Number of ticks per second of the stopwatch timer + */ +uint32_t StopWatch_TicksPerSecond(void); + +/** + * @brief Converts from stopwatch ticks to mS. + * @param ticks : Duration in ticks to convert to mS. + * @return Number of mS in given number of ticks + */ +uint32_t StopWatch_TicksToMs(uint32_t ticks); + +/** + * @brief Converts from stopwatch ticks to uS. + * @param ticks : Duration in ticks to convert to uS. + * @return Number of uS in given number of ticks + */ +uint32_t StopWatch_TicksToUs(uint32_t ticks); + +/** + * @brief Converts from mS to stopwatch ticks. + * @param mS : Duration in mS to convert to ticks. + * @return Number of ticks in given number of mS + */ +uint32_t StopWatch_MsToTicks(uint32_t mS); + +/** + * @brief Converts from uS to stopwatch ticks. + * @param uS : Duration in uS to convert to ticks. + * @return Number of ticks in given number of uS + */ +uint32_t StopWatch_UsToTicks(uint32_t uS); + +/** + * @brief Delays the given number of ticks using stopwatch primitives + * @param ticks : Number of ticks to delay + * @return Nothing + */ +STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks) +{ + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @brief Delays the given number of mS using stopwatch primitives + * @param mS : Number of mS to delay + * @return Nothing + */ +STATIC INLINE void StopWatch_DelayMs(uint32_t mS) +{ + uint32_t ticks = StopWatch_MsToTicks(mS); + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @brief Delays the given number of uS using stopwatch primitives + * @param uS : Number of uS to delay + * @return Nothing + */ +STATIC INLINE void StopWatch_DelayUs(uint32_t uS) +{ + uint32_t ticks = StopWatch_UsToTicks(uS); + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @} + */ + +#endif /* __STOPWATCH_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/timer_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/timer_18xx_43xx.h new file mode 100644 index 0000000000000..e7734f20f946a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/timer_18xx_43xx.h @@ -0,0 +1,451 @@ +/* + * @brief LPC18xx/43xx 16/32-bit Timer/PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __TIMER_18XX_43XX_H_ +#define __TIMER_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx 16/32-bit Timer driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief 32-bit Standard timer register block structure + */ +typedef struct { /*!< TIMERn Structure */ + __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ + __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ + __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ + __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ + __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ + __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ + __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ + __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ + __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ + __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +} LPC_TIMER_T; + +/** Macro to clear interrupt pending */ +#define TIMER_IR_CLR(n) _BIT(n) + +/** Macro for getting a timer match interrupt bit */ +#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F)) +/** Macro for getting a capture event interrupt bit */ +#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4))) + +/** Timer/counter enable bit */ +#define TIMER_ENABLE ((uint32_t) (1 << 0)) +/** Timer/counter reset bit */ +#define TIMER_RESET ((uint32_t) (1 << 1)) + +/** Bit location for interrupt on MRx match, n = 0 to 3 */ +#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3))) +/** Bit location for reset on MRx match, n = 0 to 3 */ +#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1))) +/** Bit location for stop on MRx match, n = 0 to 3 */ +#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2))) + +/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ +#define TIMER_CAP_RISING(n) (_BIT(((n) * 3))) +/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ +#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1))) +/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ +#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2))) + +/** + * @brief Initialize a timer + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_Init(LPC_TIMER_T *pTMR); + +/** + * @brief Shutdown a timer + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR); + +/** + * @brief Determine if a match interrupt is pending + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * @note Determine if the match interrupt for the passed timer and match + * counter is pending. + */ +STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0); +} + +/** + * @brief Determine if a capture interrupt is pending + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * @note Determine if the capture interrupt for the passed capture pin is + * pending. + */ +STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum) +{ + return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0); +} + +/** + * @brief Clears a (pending) match interrupt + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match interrupt number to clear + * @return Nothing + * @note Clears a pending timer match interrupt. + */ +STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->IR = TIMER_IR_CLR(matchnum); +} + +/** + * @brief Clears a (pending) capture interrupt + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture interrupt number to clear + * @return Nothing + * @note Clears a pending timer capture interrupt. + */ +STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->IR = (0x10 << capnum); +} + +/** + * @brief Enables the timer (starts count) + * @param pTMR : Pointer to timer IP register address + * @return Nothing + * @note Enables the timer to start counting. + */ +STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR) +{ + pTMR->TCR |= TIMER_ENABLE; +} + +/** + * @brief Disables the timer (stops count) + * @param pTMR : Pointer to timer IP register address + * @return Nothing + * @note Disables the timer to stop counting. + */ +STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR) +{ + pTMR->TCR &= ~TIMER_ENABLE; +} + +/** + * @brief Returns the current timer count + * @param pTMR : Pointer to timer IP register address + * @return Current timer terminal count value + * @note Returns the current timer terminal count. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR) +{ + return pTMR->TC; +} + +/** + * @brief Returns the current prescale count + * @param pTMR : Pointer to timer IP register address + * @return Current timer prescale count value + * @note Returns the current prescale count. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR) +{ + return pTMR->PC; +} + +/** + * @brief Sets the prescaler value + * @param pTMR : Pointer to timer IP register address + * @param prescale : Prescale value to set the prescale register to + * @return Nothing + * @note Sets the prescale count value. + */ +STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale) +{ + pTMR->PR = prescale; +} + +/** + * @brief Sets a timer match value + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer to set match count for + * @param matchval : Match value for the selected match count + * @return Nothing + * @note Sets one of the timer match values. + */ +STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval) +{ + pTMR->MR[matchnum] = matchval; +} + +/** + * @brief Reads a capture register + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture register to read + * @return The selected capture register value + * @note Returns the selected capture register value. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum) +{ + return pTMR->CR[capnum]; +} + +/** + * @brief Resets the timer terminal and prescale counts to 0 + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_Reset(LPC_TIMER_T *pTMR); + +/** + * @brief Enables a match interrupt that fires when the terminal count + * matches the match counter value. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief Disables a match interrupt for a match counter. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, enables reset of the terminal count register when a match occurs + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, disables reset of the terminal count register when a match occurs + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief Enable a match timer to stop the terminal count when a + * match count equals the terminal count. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Disable stop on match for a match timer. Disables a match timer + * to stop the terminal count when a match count equals the terminal count. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Enables capture on on rising edge of selected CAP signal for the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR |= TIMER_CAP_RISING(capnum); +} + +/** + * @brief Disables capture on on rising edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR &= ~TIMER_CAP_RISING(capnum); +} + +/** + * @brief Enables capture on on falling edge of selected CAP signal. For the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR |= TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Disables capture on on falling edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR &= ~TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Enables interrupt on capture of selected CAP signal. For the + * selected capture register, an interrupt will be generated when the enabled + * rising or falling edge on CAPn.capnum is detected. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR |= TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Disables interrupt on capture of selected CAP signal + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Standard timer initial match pin state and change state + */ +typedef enum IP_TIMER_PIN_MATCH_STATE { + TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */ + TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */ + TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */ + TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */ +} TIMER_PIN_MATCH_STATE_T; + +/** + * @brief Sets external match control (MATn.matchnum) pin control. For the pin + * selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + * @param pTMR : Pointer to timer IP register address + * @param initial_state : Initial state of the pin, high(1) or low(0) + * @param matchState : Selects the match state for the pin + * @param matchnum : MATn.matchnum signal to use + * @return Nothing + * @note For the pin selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + */ +void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, + TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum); + +/** + * @brief Standard timer clock and edge for count source + */ +typedef enum IP_TIMER_CAP_SRC_STATE { + TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */ + TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */ + TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */ + TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */ +} TIMER_CAP_SRC_STATE_T; + +/** + * @brief Sets timer count source and edge with the selected passed from CapSrc. + * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + * @param pTMR : Pointer to timer IP register address + * @param capSrc : timer clock source and edge + * @param capnum : CAPn.capnum pin to use (if used) + * @return Nothing + * @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + */ +STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR, + TIMER_CAP_SRC_STATE_T capSrc, + int8_t capnum) +{ + pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/uart_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/uart_18xx_43xx.h new file mode 100644 index 0000000000000..cad86cd6051a1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/uart_18xx_43xx.h @@ -0,0 +1,832 @@ +/* + * @brief LPC18xx/43xx UART chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __UART_18XX_43XX_H_ +#define __UART_18XX_43XX_H_ + +#include "ring_buffer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup UART_18XX_43XX CHIP: LPC18xx/43xx UART driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief USART register block structure + */ +typedef struct { /*!< USARTn Structure */ + + union { + __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ + __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */ + __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */ + }; + + union { + __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */ + __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ + }; + + union { + __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */ + __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + + __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */ + __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */ + __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */ + __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */ + __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */ + __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ + uint32_t RESERVED0[3]; + __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */ + __I uint32_t RESERVED1[1]; + __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */ + + __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */ + + union { + __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */ + __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ + }; + + __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */ +} LPC_USART_T; + + +/** + * @brief Macro defines for UART Receive Buffer register + */ +#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */ + +/** + * @brief Macro defines for UART Divisor Latch LSB register + */ +#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading LSB of divisor */ +#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB bit mask */ + +/** + * @brief Macro defines for UART Divisor Latch MSB register + */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading MSB of divisors */ +#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB bit mask */ + +/** + * @brief Macro defines for UART Interrupt Enable Register + */ +#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable */ +#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable */ +#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable */ +#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1 only */ +#define UART_IER_CTSINT (1 << 7) /*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */ +#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */ +#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/ +#define UART1_IER_BITMASK (0x30F) /*!< UART1 interrupt enable register bit mask - valid for 11xx only */ +#define UART2_IER_BITMASK (0x38F) /*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */ + +/** + * @brief Macro defines for UART Interrupt Identification Register + */ +#define UART_IIR_INTSTAT_PEND (1 << 0) /*!< Interrupt pending status - Active low */ +#define UART_IIR_FIFO_EN (3 << 6) /*!< These bits are equivalent to FCR[0] */ +#define UART_IIR_ABEO_INT (1 << 8) /*!< End of auto-baud interrupt */ +#define UART_IIR_ABTO_INT (1 << 9) /*!< Auto-baud time-out interrupt */ +#define UART_IIR_BITMASK (0x3CF) /*!< UART interrupt identification register bit mask */ + +/* Interrupt ID bit definitions */ +#define UART_IIR_INTID_MASK (7 << 1) /*!< Interrupt identification: Interrupt ID mask */ +#define UART_IIR_INTID_RLS (3 << 1) /*!< Interrupt identification: Receive line interrupt */ +#define UART_IIR_INTID_RDA (2 << 1) /*!< Interrupt identification: Receive data available interrupt */ +#define UART_IIR_INTID_CTI (6 << 1) /*!< Interrupt identification: Character time-out indicator interrupt */ +#define UART_IIR_INTID_THRE (1 << 1) /*!< Interrupt identification: THRE interrupt */ +#define UART_IIR_INTID_MODEM (0 << 1) /*!< Interrupt identification: Modem interrupt */ + +/** + * @brief Macro defines for UART FIFO Control Register + */ +#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */ +#define UART_FCR_RX_RS (1 << 1) /*!< UART RX FIFO reset */ +#define UART_FCR_TX_RS (1 << 2) /*!< UART TX FIFO reset */ +#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */ +#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */ + +#define UART_TX_FIFO_SIZE (16) + +/* FIFO trigger level bit definitions */ +#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */ +#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */ +#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */ +#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */ + +/** + * @brief Macro defines for UART Line Control Register + */ +/* UART word length select bit definitions */ +#define UART_LCR_WLEN_MASK (3 << 0) /*!< UART word length select bit mask */ +#define UART_LCR_WLEN5 (0 << 0) /*!< UART word length select: 5 bit data mode */ +#define UART_LCR_WLEN6 (1 << 0) /*!< UART word length select: 6 bit data mode */ +#define UART_LCR_WLEN7 (2 << 0) /*!< UART word length select: 7 bit data mode */ +#define UART_LCR_WLEN8 (3 << 0) /*!< UART word length select: 8 bit data mode */ + +/* UART Stop bit select bit definitions */ +#define UART_LCR_SBS_MASK (1 << 2) /*!< UART stop bit select: bit mask */ +#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART stop bit select: 1 stop bit */ +#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */ + +/* UART Parity enable bit definitions */ +#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */ +#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */ +#define UART_LCR_PARITY_ODD (0 << 4) /*!< UART Parity select: Odd parity */ +#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Parity select: Even parity */ +#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART Parity select: Forced 1 stick parity */ +#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART Parity select: Forced 0 stick parity */ +#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Break transmission enable */ +#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */ +#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */ + +/** + * @brief Macro defines for UART Modem Control Register + */ +#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */ +#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */ +#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */ +#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */ +#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */ +#define UART_MCR_BITMASK (0xD3) /*!< UART bit mask value */ + +/** + * @brief Macro defines for UART Line Status Register + */ +#define UART_LSR_RDR (1 << 0) /*!< Line status: Receive data ready */ +#define UART_LSR_OE (1 << 1) /*!< Line status: Overrun error */ +#define UART_LSR_PE (1 << 2) /*!< Line status: Parity error */ +#define UART_LSR_FE (1 << 3) /*!< Line status: Framing error */ +#define UART_LSR_BI (1 << 4) /*!< Line status: Break interrupt */ +#define UART_LSR_THRE (1 << 5) /*!< Line status: Transmit holding register empty */ +#define UART_LSR_TEMT (1 << 6) /*!< Line status: Transmitter empty */ +#define UART_LSR_RXFE (1 << 7) /*!< Line status: Error in RX FIFO */ +#define UART_LSR_TXFE (1 << 8) /*!< Line status: Error in RX FIFO */ +#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */ +#define UART1_LSR_BITMASK (0x1FF) /*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */ + +/** + * @brief Macro defines for UART Modem Status Register + */ +#define UART_MSR_DELTA_CTS (1 << 0) /*!< Modem status: State change of input CTS */ +#define UART_MSR_DELTA_DSR (1 << 1) /*!< Modem status: State change of input DSR */ +#define UART_MSR_LO2HI_RI (1 << 2) /*!< Modem status: Low to high transition of input RI */ +#define UART_MSR_DELTA_DCD (1 << 3) /*!< Modem status: State change of input DCD */ +#define UART_MSR_CTS (1 << 4) /*!< Modem status: Clear To Send State */ +#define UART_MSR_DSR (1 << 5) /*!< Modem status: Data Set Ready State */ +#define UART_MSR_RI (1 << 6) /*!< Modem status: Ring Indicator State */ +#define UART_MSR_DCD (1 << 7) /*!< Modem status: Data Carrier Detect State */ +#define UART_MSR_BITMASK (0xFF) /*!< Modem status: MSR register bit-mask value */ + +/** + * @brief Macro defines for UART Auto baudrate control register + */ +#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */ +#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */ +#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */ +#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */ +#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */ +#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */ + +/** + * Autobaud modes + */ +#define UART_ACR_MODE0 (0) /*!< Auto baudrate Mode 0 */ +#define UART_ACR_MODE1 (1) /*!< Auto baudrate Mode 1 */ + +/** + * @brief Macro defines for UART RS485 Control register + */ +#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */ +#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */ +#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */ +#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is + used for direction control */ +#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */ +#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction + control signal on the RTS (or DTR) pin. The direction control pin + will be driven to logic "1" when the transmitter has data to be sent */ +#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */ + +/** + * @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only + */ +#define UART_ICR_IRDAEN (1 << 0) /*!< IrDA mode enable */ +#define UART_ICR_IRDAINV (1 << 1) /*!< IrDA serial input inverted */ +#define UART_ICR_FIXPULSE_EN (1 << 2) /*!< IrDA fixed pulse width mode */ +#define UART_ICR_PULSEDIV(n) ((n & 0x07) << 3) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_BITMASK (0x3F) /*!< UART IRDA bit mask */ + +/** + * @brief Macro defines for UART half duplex register - ???? + */ +#define UART_HDEN_HDEN ((1 << 0)) /*!< enable half-duplex mode*/ + +/** + * @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only + */ +#define UART_SCICTRL_SCIEN (1 << 0) /*!< enable asynchronous half-duplex smart card interface*/ +#define UART_SCICTRL_NACKDIS (1 << 1) /*!< NACK response is inhibited*/ +#define UART_SCICTRL_PROTSEL_T1 (1 << 2) /*!< ISO7816-3 protocol T1 is selected*/ +#define UART_SCICTRL_TXRETRY(n) ((n & 0x07) << 5) /*!< number of retransmission*/ +#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8) /*!< Extra guard time*/ + +/** + * @brief Macro defines for UART Fractional Divider Register + */ +#define UART_FDR_DIVADDVAL(n) (n & 0x0F) /*!< Baud-rate generation pre-scaler divisor */ +#define UART_FDR_MULVAL(n) ((n << 4) & 0xF0) /*!< Baud-rate pre-scaler multiplier value */ +#define UART_FDR_BITMASK (0xFF) /*!< UART Fractional Divider register bit mask */ + +/** + * @brief Macro defines for UART Tx Enable Register + */ +#define UART_TER1_TXEN (1 << 7) /*!< Transmit enable bit - valid for 11xx, 13xx, 17xx/40xx only */ +#define UART_TER2_TXEN (1 << 0) /*!< Transmit enable bit - valid for 18xx/43xx only */ + +/** + * @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only + */ +#define UART_SYNCCTRL_SYNC (1 << 0) /*!< enable synchronous mode*/ +#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) /*!< synchronous master mode*/ +#define UART_SYNCCTRL_FES (1 << 2) /*!< sample on falling edge*/ +#define UART_SYNCCTRL_TSBYPASS (1 << 3) /*!< to be defined*/ +#define UART_SYNCCTRL_CSCEN (1 << 4) /*!< Continuous running clock enable (master mode only)*/ +#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5) /*!< Do not send start/stop bit*/ +#define UART_SYNCCTRL_CCCLR (1 << 6) /*!< stop continuous clock*/ + +/** + * @brief Enable transmission on UART TxD pin + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART) +{ + pUART->TER2 = UART_TER2_TXEN; +} + +/** + * @brief Disable transmission on UART TxD pin + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART) +{ + pUART->TER2 = 0; +} + +/** + * @brief Transmit a single data byte through the UART peripheral + * @param pUART : Pointer to selected UART peripheral + * @param data : Byte to transmit + * @return Nothing + * @note This function attempts to place a byte into the UART transmit + * FIFO or transmit hold register regard regardless of UART state + */ +STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data) +{ + pUART->THR = (uint32_t) data; +} + +/** + * @brief Read a single byte data from the UART peripheral + * @param pUART : Pointer to selected UART peripheral + * @return A single byte of data read + * @note This function reads a byte from the UART receive FIFO or + * receive hold register regard regardless of UART state. The + * FIFO status should be read first prior to using this function + */ +STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART) +{ + return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT); +} + +/** + * @brief Enable UART interrupts + * @param pUART : Pointer to selected UART peripheral + * @param intMask : OR'ed Interrupts to enable in the Interrupt Enable Register (IER) + * @return Nothing + * @note Use an OR'ed value of UART_IER_* definitions with this function + * to enable specific UART interrupts. The Divisor Latch Access Bit + * (DLAB) in LCR must be cleared in order to access the IER register. + * This function doesn't alter the DLAB state + */ +STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask) +{ + pUART->IER |= intMask; +} + +/** + * @brief Disable UART interrupts + * @param pUART : Pointer to selected UART peripheral + * @param intMask : OR'ed Interrupts to disable in the Interrupt Enable Register (IER) + * @return Nothing + * @note Use an OR'ed value of UART_IER_* definitions with this function + * to disable specific UART interrupts. The Divisor Latch Access Bit + * (DLAB) in LCR must be cleared in order to access the IER register. + * This function doesn't alter the DLAB state + */ +STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask) +{ + pUART->IER &= ~intMask; +} + +/** + * @brief Returns UART interrupts that are enabled + * @param pUART : Pointer to selected UART peripheral + * @return Returns the enabled UART interrupts + * @note Use an OR'ed value of UART_IER_* definitions with this function + * to determine which interrupts are enabled. You can check + * for multiple enabled bits if needed. + */ +STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART) +{ + return pUART->IER; +} + +/** + * @brief Read the Interrupt Identification Register (IIR) + * @param pUART : Pointer to selected UART peripheral + * @return Current pending interrupt status per the IIR register + */ +STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART) +{ + return pUART->IIR; +} + +/** + * @brief Setup the UART FIFOs + * @param pUART : Pointer to selected UART peripheral + * @param fcr : FIFO control register setup OR'ed flags + * @return Nothing + * @note Use OR'ed value of UART_FCR_* definitions with this function + * to select specific options. For example, to enable the FIFOs + * with a RX trip level of 8 characters, use something like + * (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2) + */ +STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr) +{ + pUART->FCR = fcr; +} + +/** + * @brief Configure data width, parity and stop bits + * @param pUART : Pointer to selected pUART peripheral + * @param config : UART configuration, OR'ed values of UART_LCR_* defines + * @return Nothing + * @note Select OR'ed config options for the UART from the UART_LCR_* + * definitions. For example, a configuration of 8 data bits, 1 + * stop bit, and even (enabled) parity would be + * (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN) + */ +STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config) +{ + pUART->LCR = config; +} + +/** + * @brief Enable access to Divisor Latches + * @param pUART : Pointer to selected UART peripheral + * @return Nothing + */ +STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART) +{ + pUART->LCR |= UART_LCR_DLAB_EN; +} + +/** + * @brief Disable access to Divisor Latches + * @param pUART : Pointer to selected UART peripheral + * @return Nothing + */ +STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART) +{ + pUART->LCR &= ~UART_LCR_DLAB_EN; +} + +/** + * @brief Set LSB and MSB divisor latch registers + * @param pUART : Pointer to selected UART peripheral + * @param dll : Divisor Latch LSB value + * @param dlm : Divisor Latch MSB value + * @return Nothing + * @note The Divisor Latch Access Bit (DLAB) in LCR must be set in + * order to access the USART Divisor Latches. This function + * doesn't alter the DLAB state. + */ +STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm) +{ + pUART->DLL = (uint32_t) dll; + pUART->DLM = (uint32_t) dlm; +} + + +/** + * @brief Return modem control register/status + * @param pUART : Pointer to selected UART peripheral + * @return Modem control register (status) + * @note Mask bits of the returned status value with UART_MCR_* + * definitions for specific statuses. + */ +STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART) +{ + return pUART->MCR; +} + +/** + * @brief Set modem control register/status + * @param pUART : Pointer to selected UART peripheral + * @param mcr : Modem control register flags to set + * @return Nothing + * @note Use an Or'ed value of UART_MCR_* definitions with this + * call to set specific options. + */ +STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr) +{ + pUART->MCR |= mcr; +} + +/** + * @brief Clear modem control register/status + * @param pUART : Pointer to selected UART peripheral + * @param mcr : Modem control register flags to clear + * @return Nothing + * @note Use an Or'ed value of UART_MCR_* definitions with this + * call to clear specific options. + */ +STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr) +{ + pUART->MCR &= ~mcr; +} + +/** + * @brief Return Line Status register/status (LSR) + * @param pUART : Pointer to selected UART peripheral + * @return Line Status register (status) + * @note Mask bits of the returned status value with UART_LSR_* + * definitions for specific statuses. + */ +STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART) +{ + return pUART->LSR; +} + +/** + * @brief Return Modem Status register/status (MSR) + * @param pUART : Pointer to selected UART peripheral + * @return Modem Status register (status) + * @note Mask bits of the returned status value with UART_MSR_* + * definitions for specific statuses. + */ +STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART) +{ + return pUART->MSR; +} + +/** + * @brief Write a byte to the scratchpad register + * @param pUART : Pointer to selected UART peripheral + * @param data : Byte value to write + * @return Nothing + */ +STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data) +{ + pUART->SCR = (uint32_t) data; +} + +/** + * @brief Returns current byte value in the scratchpad register + * @param pUART : Pointer to selected UART peripheral + * @return Byte value read from scratchpad register + */ +STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART) +{ + return (uint8_t) (pUART->SCR & 0xFF); +} + +/** + * @brief Set autobaud register options + * @param pUART : Pointer to selected UART peripheral + * @param acr : Or'ed values to set for ACR register + * @return Nothing + * @note Use an Or'ed value of UART_ACR_* definitions with this + * call to set specific options. + */ +STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr) +{ + pUART->ACR |= acr; +} + +/** + * @brief Clear autobaud register options + * @param pUART : Pointer to selected UART peripheral + * @param acr : Or'ed values to clear for ACR register + * @return Nothing + * @note Use an Or'ed value of UART_ACR_* definitions with this + * call to clear specific options. + */ +STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr) +{ + pUART->ACR &= ~acr; +} + +/** + * @brief Set RS485 control register options + * @param pUART : Pointer to selected UART peripheral + * @param ctrl : Or'ed values to set for RS485 control register + * @return Nothing + * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this + * call to set specific options. + */ +STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl) +{ + pUART->RS485CTRL |= ctrl; +} + +/** + * @brief Clear RS485 control register options + * @param pUART : Pointer to selected UART peripheral + * @param ctrl : Or'ed values to clear for RS485 control register + * @return Nothing + * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this + * call to clear specific options. + */ +STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl) +{ + pUART->RS485CTRL &= ~ctrl; +} + +/** + * @brief Set RS485 address match value + * @param pUART : Pointer to selected UART peripheral + * @param addr : Address match value for RS-485/EIA-485 mode + * @return Nothing + */ +STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr) +{ + pUART->RS485ADRMATCH = (uint32_t) addr; +} + +/** + * @brief Read RS485 address match value + * @param pUART : Pointer to selected UART peripheral + * @return Address match value for RS-485/EIA-485 mode + */ +STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART) +{ + return (uint8_t) (pUART->RS485ADRMATCH & 0xFF); +} + +/** + * @brief Set RS485 direction control (RTS or DTR) delay value + * @param pUART : Pointer to selected UART peripheral + * @param dly : direction control (RTS or DTR) delay value + * @return Nothing + * @note This delay time is in periods of the baud clock. Any delay + * time from 0 to 255 bit times may be programmed. + */ +STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly) +{ + pUART->RS485DLY = (uint32_t) dly; +} + +/** + * @brief Read RS485 direction control (RTS or DTR) delay value + * @param pUART : Pointer to selected UART peripheral + * @return direction control (RTS or DTR) delay value + * @note This delay time is in periods of the baud clock. Any delay + * time from 0 to 255 bit times may be programmed. + */ +STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART) +{ + return (uint8_t) (pUART->RS485DLY & 0xFF); +} + +/** + * @brief Initializes the pUART peripheral + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +void Chip_UART_Init(LPC_USART_T *pUART); + +/** + * @brief De-initializes the pUART peripheral. + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +void Chip_UART_DeInit(LPC_USART_T *pUART); + + +/** + * @brief Check whether if UART is busy or not + * @param pUART : Pointer to selected pUART peripheral + * @return RESET if UART is not busy, otherwise return SET + */ +FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART); + +/** + * @brief Transmit a byte array through the UART peripheral (non-blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to bytes to transmit + * @param numBytes : Number of bytes to transmit + * @return The actual number of bytes placed into the FIFO + * @note This function places data into the transmit FIFO until either + * all the data is in the FIFO or the FIFO is full. This function + * will not block in the FIFO is full. The actual number of bytes + * placed into the FIFO is returned. This function ignores errors. + */ +int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes); + +/** + * @brief Read data through the UART peripheral (non-blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to bytes array to fill + * @param numBytes : Size of the passed data array + * @return The actual number of bytes read + * @note This function reads data from the receive FIFO until either + * all the data has been read or the passed buffer is completely full. + * This function will not block. This function ignores errors. + */ +int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes); + +/** + * @brief Sets best dividers to get a target bit rate (without fractional divider) + * @param pUART : Pointer to selected UART peripheral + * @param baudrate : Target baud rate (baud rate = bit rate) + * @return The actual baud rate, or 0 if no rate can be found + */ +uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate); + +/** + * @brief Sets best dividers to get a target bit rate (with fractional divider) + * @param pUART : Pointer to selected UART peripheral + * @param baud : Target baud rate (baud rate = bit rate) + * @return The actual baud rate, or 0 if no rate can be found + * @note The maximum bit rate possible is (clk / 16), the next possible bit + * rate is (clk / 32), the next possible bit rate is (clk / 48), no + * rates in-between any of the above three maximum rates could be set + * using this API. Fractional dividers can only be used for rates + * lower than (clk / 48) where @a clk is the base clock of the UART. + */ +uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baud); + +/** + * @brief Transmit a byte array through the UART peripheral (blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to data to transmit + * @param numBytes : Number of bytes to transmit + * @return The number of bytes transmitted + * @note This function will send or place all bytes into the transmit + * FIFO. This function will block until the last bytes are in the FIFO. + */ +int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes); + +/** + * @brief Read data through the UART peripheral (blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to data array to fill + * @param numBytes : Size of the passed data array + * @return The size of the dat array + * @note This function reads data from the receive FIFO until the passed + * buffer is completely full. The function will block until full. + * This function ignores errors. + */ +int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes); + +/** + * @brief UART receive-only interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @return Nothing + * @note If ring buffer support is desired for the receive side + * of data transfer, the UART interrupt should call this + * function for a receive based interrupt status. + */ +void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); + +/** + * @brief UART transmit-only interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @return Nothing + * @note If ring buffer support is desired for the transmit side + * of data transfer, the UART interrupt should call this + * function for a transmit based interrupt status. + */ +void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); + +/** + * @brief Populate a transmit ring buffer and start UART transmit + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @param data : Pointer to buffer to move to ring buffer + * @param bytes : Number of bytes to move + * @return The number of bytes placed into the ring buffer + * @note Will move the data into the TX ring buffer and start the + * transfer. If the number of bytes returned is less than the + * number of bytes to send, the ring buffer is considered full. + */ +uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes); + +/** + * @brief Copy data from a receive ring buffer + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @param data : Pointer to buffer to fill from ring buffer + * @param bytes : Size of the passed buffer in bytes + * @return The number of bytes placed into the ring buffer + * @note Will move the data from the RX ring buffer up to the + * the maximum passed buffer size. Returns 0 if there is + * no data in the ring buffer. + */ +int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes); + +/** + * @brief UART receive/transmit interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRXRB : Pointer to transmit ring buffer + * @param pTXRB : Pointer to receive ring buffer + * @return Nothing + * @note This provides a basic implementation of the UART IRQ + * handler for support of a ring buffer implementation for + * transmit and receive. + */ +void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB); + +/** + * @brief Returns the Auto Baud status + * @param pUART : Pointer to selected UART peripheral + * @return RESET if autobaud not completed, SET if autobaud completed + */ +FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART); + +/** + * @brief Start/stop autobaud operation + * @param pUART : Pointer to selected UART peripheral + * @param mode : Autobaud mode (UART_ACR_MODE0 or UART_ACR_MODE1) + * @param autorestart : Enable autorestart (true to enable or false to disable) + * @param NewState : ENABLE to start autobaud operation, DISABLE to + * stop autobaud operation + * @return Nothing + */ +void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart, + FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd.h new file mode 100644 index 0000000000000..b9d0adb40a4f1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd.h @@ -0,0 +1,711 @@ +/*********************************************************************** +* $Id:: mw_usbd.h 575 2012-11-20 01:35:56Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ + +#ifndef __USBD_H__ +#define __USBD_H__ + +/** \file + * \brief Common definitions and declarations for the USB stack. + * + * Common definitions and declarations for the USB stack. + * \addtogroup USBD_Core + * @{ + */ + +#include "lpc_types.h" + +#if defined(__GNUC__) +/* As per http://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax, +6.29 Attributes Syntax +"An attribute specifier list may appear as part of a struct, union or +enum specifier. It may go either immediately after the struct, union +or enum keyword, or after the closing brace. The former syntax is +preferred. Where attribute specifiers follow the closing brace, they +are considered to relate to the structure, union or enumerated type +defined, not to any enclosing declaration the type specifier appears +in, and the type defined is not complete until after the attribute +specifiers." +So use POST_PACK immediately after struct keyword +*/ +#define PRE_PACK +#define POST_PACK __attribute__((__packed__)) +#define ALIGNED(n) __attribute__((aligned (n))) + +#elif defined(__arm) +#define PRE_PACK __packed +#define POST_PACK +#define ALIGNED(n) __align(n) + +#elif defined(__ICCARM__) +#define PRE_PACK __packed +#define POST_PACK +#define PRAGMA_ALIGN_4096 _Pragma("data_alignment=4096") +#define PRAGMA_ALIGN_2048 _Pragma("data_alignment=2048") +#define PRAGMA_ALIGN_512 _Pragma("data_alignment=512") +#define PRAGMA_ALIGN_256 _Pragma("data_alignment=256") +#define PRAGMA_ALIGN_128 _Pragma("data_alignment=128") +#define PRAGMA_ALIGN_64 _Pragma("data_alignment=64") +#define PRAGMA_ALIGN_48 _Pragma("data_alignment=48") +#define PRAGMA_ALIGN_32 _Pragma("data_alignment=32") +#define PRAGMA_ALIGN_4 _Pragma("data_alignment=4") +#define ALIGNED(n) PRAGMA_ALIGN_##n + +#pragma diag_suppress=Pe021 +#endif + +/** Structure to pack lower and upper byte to form 16 bit word. */ +PRE_PACK struct POST_PACK _WB_T +{ + uint8_t L; /**< lower byte */ + uint8_t H; /**< upper byte */ +}; +/** Structure to pack lower and upper byte to form 16 bit word.*/ +typedef struct _WB_T WB_T; + +/** Union of \ref _WB_T struct and 16 bit word.*/ +PRE_PACK union POST_PACK __WORD_BYTE +{ + uint16_t W; /**< data member to do 16 bit access */ + WB_T WB; /**< data member to do 8 bit access */ +} ; +/** Union of \ref _WB_T struct and 16 bit word.*/ +typedef union __WORD_BYTE WORD_BYTE; + +/** bmRequestType.Dir defines + * @{ + */ +/** Request from host to device */ +#define REQUEST_HOST_TO_DEVICE 0 +/** Request from device to host */ +#define REQUEST_DEVICE_TO_HOST 1 +/** @} */ + +/** bmRequestType.Type defines + * @{ + */ +/** Standard Request */ +#define REQUEST_STANDARD 0 +/** Class Request */ +#define REQUEST_CLASS 1 +/** Vendor Request */ +#define REQUEST_VENDOR 2 +/** Reserved Request */ +#define REQUEST_RESERVED 3 +/** @} */ + +/** bmRequestType.Recipient defines + * @{ + */ +/** Request to device */ +#define REQUEST_TO_DEVICE 0 +/** Request to interface */ +#define REQUEST_TO_INTERFACE 1 +/** Request to endpoint */ +#define REQUEST_TO_ENDPOINT 2 +/** Request to other */ +#define REQUEST_TO_OTHER 3 +/** @} */ + +/** Structure to define 8 bit USB request.*/ +PRE_PACK struct POST_PACK _BM_T +{ + uint8_t Recipient : 5; /**< Recipient type. */ + uint8_t Type : 2; /**< Request type. */ + uint8_t Dir : 1; /**< Direction type. */ +}; +/** Structure to define 8 bit USB request.*/ +typedef struct _BM_T BM_T; + +/** Union of \ref _BM_T struct and 8 bit byte.*/ +PRE_PACK union POST_PACK _REQUEST_TYPE +{ + uint8_t B; /**< byte wide access memeber */ + BM_T BM; /**< bitfield structure access memeber */ +} ; +/** Union of \ref _BM_T struct and 8 bit byte.*/ +typedef union _REQUEST_TYPE REQUEST_TYPE; + +/** USB Standard Request Codes + * @{ + */ +/** GET_STATUS request */ +#define USB_REQUEST_GET_STATUS 0 +/** CLEAR_FEATURE request */ +#define USB_REQUEST_CLEAR_FEATURE 1 +/** SET_FEATURE request */ +#define USB_REQUEST_SET_FEATURE 3 +/** SET_ADDRESS request */ +#define USB_REQUEST_SET_ADDRESS 5 +/** GET_DESCRIPTOR request */ +#define USB_REQUEST_GET_DESCRIPTOR 6 +/** SET_DESCRIPTOR request */ +#define USB_REQUEST_SET_DESCRIPTOR 7 +/** GET_CONFIGURATION request */ +#define USB_REQUEST_GET_CONFIGURATION 8 +/** SET_CONFIGURATION request */ +#define USB_REQUEST_SET_CONFIGURATION 9 +/** GET_INTERFACE request */ +#define USB_REQUEST_GET_INTERFACE 10 +/** SET_INTERFACE request */ +#define USB_REQUEST_SET_INTERFACE 11 +/** SYNC_FRAME request */ +#define USB_REQUEST_SYNC_FRAME 12 +/** @} */ + +/** USB GET_STATUS Bit Values + * @{ + */ +/** SELF_POWERED status*/ +#define USB_GETSTATUS_SELF_POWERED 0x01 +/** REMOTE_WAKEUP capable status*/ +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 +/** ENDPOINT_STALL status*/ +#define USB_GETSTATUS_ENDPOINT_STALL 0x01 +/** @} */ + +/** USB Standard Feature selectors + * @{ + */ +/** ENDPOINT_STALL feature*/ +#define USB_FEATURE_ENDPOINT_STALL 0 +/** REMOTE_WAKEUP feature*/ +#define USB_FEATURE_REMOTE_WAKEUP 1 +/** TEST_MODE feature*/ +#define USB_FEATURE_TEST_MODE 2 +/** @} */ + +/** USB Default Control Pipe Setup Packet*/ +PRE_PACK struct POST_PACK _USB_SETUP_PACKET +{ + REQUEST_TYPE bmRequestType; /**< This bitmapped field identifies the characteristics + of the specific request. \sa _BM_T. + */ + uint8_t bRequest; /**< This field specifies the particular request. The + Type bits in the bmRequestType field modify the meaning + of this field. \sa USBD_REQUEST. + */ + WORD_BYTE wValue; /**< Used to pass a parameter to the device, specific + to the request. + */ + WORD_BYTE wIndex; /**< Used to pass a parameter to the device, specific + to the request. The wIndex field is often used in + requests to specify an endpoint or an interface. + */ + uint16_t wLength; /**< This field specifies the length of the data + transferred during the second phase of the control + transfer. + */ +} ; +/** USB Default Control Pipe Setup Packet*/ +typedef struct _USB_SETUP_PACKET USB_SETUP_PACKET; + + +/** USB Descriptor Types + * @{ + */ +/** Device descriptor type */ +#define USB_DEVICE_DESCRIPTOR_TYPE 1 +/** Configuration descriptor type */ +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 +/** String descriptor type */ +#define USB_STRING_DESCRIPTOR_TYPE 3 +/** Interface descriptor type */ +#define USB_INTERFACE_DESCRIPTOR_TYPE 4 +/** Endpoint descriptor type */ +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 +/** Device qualifier descriptor type */ +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6 +/** Other speed configuration descriptor type */ +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7 +/** Interface power descriptor type */ +#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8 +/** OTG descriptor type */ +#define USB_OTG_DESCRIPTOR_TYPE 9 +/** Debug descriptor type */ +#define USB_DEBUG_DESCRIPTOR_TYPE 10 +/** Interface association descriptor type */ +#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11 +/** @} */ + +/** USB Device Classes + * @{ + */ +/** Reserved device class */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +/** Audio device class */ +#define USB_DEVICE_CLASS_AUDIO 0x01 +/** Communications device class */ +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 +/** Human interface device class */ +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 +/** monitor device class */ +#define USB_DEVICE_CLASS_MONITOR 0x04 +/** physical interface device class */ +#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 +/** power device class */ +#define USB_DEVICE_CLASS_POWER 0x06 +/** Printer device class */ +#define USB_DEVICE_CLASS_PRINTER 0x07 +/** Storage device class */ +#define USB_DEVICE_CLASS_STORAGE 0x08 +/** Hub device class */ +#define USB_DEVICE_CLASS_HUB 0x09 +/** miscellaneous device class */ +#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF +/** Application device class */ +#define USB_DEVICE_CLASS_APP 0xFE +/** Vendor specific device class */ +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF +/** @} */ + +/** bmAttributes in Configuration Descriptor + * @{ + */ +/** Power field mask */ +#define USB_CONFIG_POWERED_MASK 0x40 +/** Bus powered */ +#define USB_CONFIG_BUS_POWERED 0x80 +/** Self powered */ +#define USB_CONFIG_SELF_POWERED 0xC0 +/** remote wakeup */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +/** @} */ + +/** bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +/** bEndpointAddress in Endpoint Descriptor + * @{ + */ +/** Endopint address mask */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +/** Macro to convert OUT endopint number to endpoint address value. */ +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +/** Macro to convert IN endopint number to endpoint address value. */ +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) +/** @} */ + +/** bmAttributes in Endpoint Descriptor + * @{ + */ +/** Endopint type mask */ +#define USB_ENDPOINT_TYPE_MASK 0x03 +/** Control Endopint type */ +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +/** isochronous Endopint type */ +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +/** bulk Endopint type */ +#define USB_ENDPOINT_TYPE_BULK 0x02 +/** interrupt Endopint type */ +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 +/** Endopint sync type mask */ +#define USB_ENDPOINT_SYNC_MASK 0x0C +/** no synchronization Endopint */ +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 +/** Asynchronous sync Endopint */ +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 +/** Adaptive sync Endopint */ +#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 +/** Synchronous sync Endopint */ +#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C +/** Endopint usage type mask */ +#define USB_ENDPOINT_USAGE_MASK 0x30 +/** Endopint data usage type */ +#define USB_ENDPOINT_USAGE_DATA 0x00 +/** Endopint feedback usage type */ +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +/** Endopint implicit feedback usage type */ +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 +/** Endopint reserved usage type */ +#define USB_ENDPOINT_USAGE_RESERVED 0x30 +/** @} */ + +/** Control endopint EP0's maximum packet size in high-speed mode.*/ +#define USB_ENDPOINT_0_HS_MAXP 64 +/** Control endopint EP0's maximum packet size in low-speed mode.*/ +#define USB_ENDPOINT_0_LS_MAXP 8 +/** Bulk endopint's maximum packet size in high-speed mode.*/ +#define USB_ENDPOINT_BULK_HS_MAXP 512 + +/** USB Standard Device Descriptor */ +PRE_PACK struct POST_PACK _USB_DEVICE_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes. */ + uint8_t bDescriptorType; /**< DEVICE Descriptor Type. */ + uint16_t bcdUSB; /**< BUSB Specification Release Number in + Binary-Coded Decimal (i.e., 2.10 is 210H). + This field identifies the release of the USB + Specification with which the device and its + descriptors are compliant. + */ + uint8_t bDeviceClass; /**< Class code (assigned by the USB-IF). + If this field is reset to zero, each interface + within a configuration specifies its own + class information and the various + interfaces operate independently.\n + If this field is set to a value between 1 and + FEH, the device supports different class + specifications on different interfaces and + the interfaces may not operate + independently. This value identifies the + class definition used for the aggregate + interfaces. \n + If this field is set to FFH, the device class + is vendor-specific. + */ + uint8_t bDeviceSubClass; /**< Subclass code (assigned by the USB-IF). + These codes are qualified by the value of + the bDeviceClass field. \n + If the bDeviceClass field is reset to zero, + this field must also be reset to zero. \n + If the bDeviceClass field is not set to FFH, + all values are reserved for assignment by + the USB-IF. + */ + uint8_t bDeviceProtocol; /**< Protocol code (assigned by the USB-IF). + These codes are qualified by the value of + the bDeviceClass and the + bDeviceSubClass fields. If a device + supports class-specific protocols on a + device basis as opposed to an interface + basis, this code identifies the protocols + that the device uses as defined by the + specification of the device class. \n + If this field is reset to zero, the device + does not use class-specific protocols on a + device basis. However, it may use classspecific + protocols on an interface basis. \n + If this field is set to FFH, the device uses a + vendor-specific protocol on a device basis. + */ + uint8_t bMaxPacketSize0; /**< Maximum packet size for endpoint zero + (only 8, 16, 32, or 64 are valid). For HS devices + is fixed to 64. + */ + + uint16_t idVendor; /**< Vendor ID (assigned by the USB-IF). */ + uint16_t idProduct; /**< Product ID (assigned by the manufacturer). */ + uint16_t bcdDevice; /**< Device release number in binary-coded decimal. */ + uint8_t iManufacturer; /**< Index of string descriptor describing manufacturer. */ + uint8_t iProduct; /**< Index of string descriptor describing product. */ + uint8_t iSerialNumber; /**< Index of string descriptor describing the device’s + serial number. + */ + uint8_t bNumConfigurations; /**< Number of possible configurations. */ +} ; +/** USB Standard Device Descriptor */ +typedef struct _USB_DEVICE_DESCRIPTOR USB_DEVICE_DESCRIPTOR; + +/** USB 2.0 Device Qualifier Descriptor */ +PRE_PACK struct POST_PACK _USB_DEVICE_QUALIFIER_DESCRIPTOR +{ + uint8_t bLength; /**< Size of descriptor */ + uint8_t bDescriptorType; /**< Device Qualifier Type */ + uint16_t bcdUSB; /**< USB specification version number (e.g., 0200H for V2.00) */ + uint8_t bDeviceClass; /**< Class Code */ + uint8_t bDeviceSubClass; /**< SubClass Code */ + uint8_t bDeviceProtocol; /**< Protocol Code */ + uint8_t bMaxPacketSize0; /**< Maximum packet size for other speed */ + uint8_t bNumConfigurations; /**< Number of Other-speed Configurations */ + uint8_t bReserved; /**< Reserved for future use, must be zero */ +} ; +/** USB 2.0 Device Qualifier Descriptor */ +typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR USB_DEVICE_QUALIFIER_DESCRIPTOR; + +/** USB Standard Configuration Descriptor */ +PRE_PACK struct POST_PACK _USB_CONFIGURATION_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes */ + uint8_t bDescriptorType; /**< CONFIGURATION Descriptor Type*/ + uint16_t wTotalLength; /**< Total length of data returned for this + configuration. Includes the combined length + of all descriptors (configuration, interface, + endpoint, and class- or vendor-specific) + returned for this configuration.*/ + uint8_t bNumInterfaces; /**< Number of interfaces supported by this configuration*/ + uint8_t bConfigurationValue; /**< Value to use as an argument to the + SetConfiguration() request to select this + configuration. */ + uint8_t iConfiguration; /**< Index of string descriptor describing this + configuration*/ + uint8_t bmAttributes; /**< Configuration characteristics \n + D7: Reserved (set to one)\n + D6: Self-powered \n + D5: Remote Wakeup \n + D4...0: Reserved (reset to zero) \n + D7 is reserved and must be set to one for + historical reasons. \n + A device configuration that uses power from + the bus and a local source reports a non-zero + value in bMaxPower to indicate the amount of + bus power required and sets D6. The actual + power source at runtime may be determined + using the GetStatus(DEVICE) request (see + USB 2.0 spec Section 9.4.5). \n + If a device configuration supports remote + wakeup, D5 is set to one.*/ + uint8_t bMaxPower; /**< Maximum power consumption of the USB + device from the bus in this specific + configuration when the device is fully + operational. Expressed in 2 mA units + (i.e., 50 = 100 mA). \n + Note: A device configuration reports whether + the configuration is bus-powered or selfpowered. + Device status reports whether the + device is currently self-powered. If a device is + disconnected from its external power source, it + updates device status to indicate that it is no + longer self-powered. \n + A device may not increase its power draw + from the bus, when it loses its external power + source, beyond the amount reported by its + configuration. \n + If a device can continue to operate when + disconnected from its external power source, it + continues to do so. If the device cannot + continue to operate, it fails operations it can + no longer support. The USB System Software + may determine the cause of the failure by + checking the status and noting the loss of the + device’s power source.*/ +} ; +/** USB Standard Configuration Descriptor */ +typedef struct _USB_CONFIGURATION_DESCRIPTOR USB_CONFIGURATION_DESCRIPTOR; + +/** USB Standard Interface Association Descriptor */ +PRE_PACK struct POST_PACK _USB_IAD_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes*/ + uint8_t bDescriptorType; /**< INTERFACE ASSOCIATION Descriptor Type*/ + uint8_t bFirstInterface; /**< Interface number of the first interface that is + associated with this function.*/ + uint8_t bInterfaceCount; /**< Number of contiguous interfaces that are + associated with this function. */ + uint8_t bFunctionClass; /**< Class code (assigned by USB-IF). \n + A value of zero is not allowed in this descriptor. + If this field is FFH, the function class is vendorspecific. + All other values are reserved for assignment by + the USB-IF.*/ + uint8_t bFunctionSubClass; /**< Subclass code (assigned by USB-IF). \n + If the bFunctionClass field is not set to FFH all + values are reserved for assignment by the USBIF.*/ + uint8_t bFunctionProtocol; /**< Protocol code (assigned by the USB). \n + These codes are qualified by the values of the + bFunctionClass and bFunctionSubClass fields.*/ + uint8_t iFunction; /**< Index of string descriptor describing this function.*/ +} ; +/** USB Standard Interface Association Descriptor */ +typedef struct _USB_IAD_DESCRIPTOR USB_IAD_DESCRIPTOR; + +/** USB Standard Interface Descriptor */ +PRE_PACK struct POST_PACK _USB_INTERFACE_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes*/ + uint8_t bDescriptorType; /**< INTERFACE Descriptor Type*/ + uint8_t bInterfaceNumber; /**< Number of this interface. Zero-based + value identifying the index in the array of + concurrent interfaces supported by this + configuration.*/ + uint8_t bAlternateSetting; /**< Value used to select this alternate setting + for the interface identified in the prior field*/ + uint8_t bNumEndpoints; /**< Number of endpoints used by this + interface (excluding endpoint zero). If this + value is zero, this interface only uses the + Default Control Pipe.*/ + uint8_t bInterfaceClass; /**< Class code (assigned by the USB-IF). \n + A value of zero is reserved for future + standardization. \n + If this field is set to FFH, the interface + class is vendor-specific. \n + All other values are reserved for + assignment by the USB-IF.*/ + uint8_t bInterfaceSubClass; /**< Subclass code (assigned by the USB-IF). \n + These codes are qualified by the value of + the bInterfaceClass field. \n + If the bInterfaceClass field is reset to zero, + this field must also be reset to zero. \n + If the bInterfaceClass field is not set to + FFH, all values are reserved for + assignment by the USB-IF.*/ + uint8_t bInterfaceProtocol; /**< Protocol code (assigned by the USB). \n + These codes are qualified by the value of + the bInterfaceClass and the + bInterfaceSubClass fields. If an interface + supports class-specific requests, this code + identifies the protocols that the device + uses as defined by the specification of the + device class. \n + If this field is reset to zero, the device + does not use a class-specific protocol on + this interface. \n + If this field is set to FFH, the device uses + a vendor-specific protocol for this + interface.*/ + uint8_t iInterface; /**< Index of string descriptor describing this interface*/ +} ; +/** USB Standard Interface Descriptor */ +typedef struct _USB_INTERFACE_DESCRIPTOR USB_INTERFACE_DESCRIPTOR; + +/** USB Standard Endpoint Descriptor */ +PRE_PACK struct POST_PACK _USB_ENDPOINT_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes*/ + uint8_t bDescriptorType; /**< ENDPOINT Descriptor Type*/ + uint8_t bEndpointAddress; /**< The address of the endpoint on the USB device + described by this descriptor. The address is + encoded as follows: \n + Bit 3...0: The endpoint number \n + Bit 6...4: Reserved, reset to zero \n + Bit 7: Direction, ignored for control endpoints + 0 = OUT endpoint + 1 = IN endpoint. \n \sa USBD_ENDPOINT_ADR_Type*/ + uint8_t bmAttributes; /**< This field describes the endpoint’s attributes when it is + configured using the bConfigurationValue. \n + Bits 1..0: Transfer Type + \li 00 = Control + \li 01 = Isochronous + \li 10 = Bulk + \li 11 = Interrupt \n + If not an isochronous endpoint, bits 5..2 are reserved + and must be set to zero. If isochronous, they are + defined as follows: \n + Bits 3..2: Synchronization Type + \li 00 = No Synchronization + \li 01 = Asynchronous + \li 10 = Adaptive + \li 11 = Synchronous \n + Bits 5..4: Usage Type + \li 00 = Data endpoint + \li 01 = Feedback endpoint + \li 10 = Implicit feedback Data endpoint + \li 11 = Reserved \n + Refer to Chapter 5 of USB 2.0 specification for more information. \n + All other bits are reserved and must be reset to zero. + Reserved bits must be ignored by the host. + \n \sa USBD_EP_ATTR_Type*/ + uint16_t wMaxPacketSize; /**< Maximum packet size this endpoint is capable of + sending or receiving when this configuration is + selected. \n + For isochronous endpoints, this value is used to + reserve the bus time in the schedule, required for the + per-(micro)frame data payloads. The pipe may, on an + ongoing basis, actually use less bandwidth than that + reserved. The device reports, if necessary, the actual + bandwidth used via its normal, non-USB defined + mechanisms. \n + For all endpoints, bits 10..0 specify the maximum + packet size (in bytes). \n + For high-speed isochronous and interrupt endpoints: \n + Bits 12..11 specify the number of additional transaction + opportunities per microframe: \n + \li 00 = None (1 transaction per microframe) + \li 01 = 1 additional (2 per microframe) + \li 10 = 2 additional (3 per microframe) + \li 11 = Reserved \n + Bits 15..13 are reserved and must be set to zero.*/ + uint8_t bInterval; /**< Interval for polling endpoint for data transfers. + Expressed in frames or microframes depending on the + device operating speed (i.e., either 1 millisecond or + 125 µs units). + \li For full-/high-speed isochronous endpoints, this value + must be in the range from 1 to 16. The bInterval value + is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a + bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). + \li For full-/low-speed interrupt endpoints, the value of + this field may be from 1 to 255. + \li For high-speed interrupt endpoints, the bInterval value + is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a + bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value + must be from 1 to 16. + \li For high-speed bulk/control OUT endpoints, the + bInterval must specify the maximum NAK rate of the + endpoint. A value of 0 indicates the endpoint never + NAKs. Other values indicate at most 1 NAK each + bInterval number of microframes. This value must be + in the range from 0 to 255. \n + Refer to Chapter 5 of USB 2.0 specification for more information. + */ +} ; +/** USB Standard Endpoint Descriptor */ +typedef struct _USB_ENDPOINT_DESCRIPTOR USB_ENDPOINT_DESCRIPTOR; + +/** USB String Descriptor */ +PRE_PACK struct POST_PACK _USB_STRING_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes*/ + uint8_t bDescriptorType; /**< STRING Descriptor Type*/ + uint16_t bString/*[]*/; /**< UNICODE encoded string */ +} ; +/** USB String Descriptor */ +typedef struct _USB_STRING_DESCRIPTOR USB_STRING_DESCRIPTOR; + +/** USB Common Descriptor */ +PRE_PACK struct POST_PACK _USB_COMMON_DESCRIPTOR +{ + uint8_t bLength; /**< Size of this descriptor in bytes*/ + uint8_t bDescriptorType; /**< Descriptor Type*/ +} ; +/** USB Common Descriptor */ +typedef struct _USB_COMMON_DESCRIPTOR USB_COMMON_DESCRIPTOR; + +/** USB Other Speed Configuration */ +PRE_PACK struct POST_PACK _USB_OTHER_SPEED_CONFIGURATION +{ + uint8_t bLength; /**< Size of descriptor*/ + uint8_t bDescriptorType; /**< Other_speed_Configuration Type*/ + uint16_t wTotalLength; /**< Total length of data returned*/ + uint8_t bNumInterfaces; /**< Number of interfaces supported by this speed configuration*/ + uint8_t bConfigurationValue; /**< Value to use to select configuration*/ + uint8_t IConfiguration; /**< Index of string descriptor*/ + uint8_t bmAttributes; /**< Same as Configuration descriptor*/ + uint8_t bMaxPower; /**< Same as Configuration descriptor*/ +} ; +/** USB Other Speed Configuration */ +typedef struct _USB_OTHER_SPEED_CONFIGURATION USB_OTHER_SPEED_CONFIGURATION; + +/** \ingroup USBD_Core + * USB device stack/module handle. + */ +typedef void* USBD_HANDLE_T; + +#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) +#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF) + +#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) +#define USB_CONFIGURATION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) +#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) +#define USB_INTERFACE_ASSOC_DESC_SIZE (sizeof(USB_IAD_DESCRIPTOR)) +#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) +#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR)) +#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION)) + +/** @}*/ + +#endif /* __USBD_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_adc.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_adc.h new file mode 100644 index 0000000000000..dcbdac3a97164 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_adc.h @@ -0,0 +1,383 @@ +/*********************************************************************** +* $Id:: mw_usbd_audio.h 165 2011-04-14 17:41:11Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Audio Device Class Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __AUDIO_H__ +#define __AUDIO_H__ + + +/* Audio Interface Subclass Codes */ +#define AUDIO_SUBCLASS_UNDEFINED 0x00 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_SUBCLASS_MIDISTREAMING 0x03 + +/* Audio Interface Protocol Codes */ +#define AUDIO_PROTOCOL_UNDEFINED 0x00 + + +/* Audio Descriptor Types */ +#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20 +#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21 +#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22 +#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23 +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + + +/* Audio Control Interface Descriptor Subtypes */ +#define AUDIO_CONTROL_UNDEFINED 0x00 +#define AUDIO_CONTROL_HEADER 0x01 +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 +#define AUDIO_CONTROL_MIXER_UNIT 0x04 +#define AUDIO_CONTROL_SELECTOR_UNIT 0x05 +#define AUDIO_CONTROL_FEATURE_UNIT 0x06 +#define AUDIO_CONTROL_PROCESSING_UNIT 0x07 +#define AUDIO_CONTROL_EXTENSION_UNIT 0x08 + +/* Audio Streaming Interface Descriptor Subtypes */ +#define AUDIO_STREAMING_UNDEFINED 0x00 +#define AUDIO_STREAMING_GENERAL 0x01 +#define AUDIO_STREAMING_FORMAT_TYPE 0x02 +#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03 + +/* Audio Endpoint Descriptor Subtypes */ +#define AUDIO_ENDPOINT_UNDEFINED 0x00 +#define AUDIO_ENDPOINT_GENERAL 0x01 + + +/* Audio Descriptor Sizes */ +#define AUDIO_CONTROL_INTERFACE_DESC_SZ(n) 0x08+n +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 +#define AUDIO_MIXER_UNIT_DESC_SZ(p,n) 0x0A+p+n +#define AUDIO_SELECTOR_UNIT_DESC_SZ(p) 0x06+p +#define AUDIO_FEATURE_UNIT_DESC_SZ(ch,n) 0x07+(ch+1)*n +#define AUDIO_PROCESSING_UNIT_DESC_SZ(p,n,x) 0x0D+p+n+x +#define AUDIO_EXTENSION_UNIT_DESC_SZ(p,n) 0x0D+p+n +#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 +#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 + + +/* Audio Processing Unit Process Types */ +#define AUDIO_UNDEFINED_PROCESS 0x00 +#define AUDIO_UP_DOWN_MIX_PROCESS 0x01 +#define AUDIO_DOLBY_PROLOGIC_PROCESS 0x02 +#define AUDIO_3D_STEREO_PROCESS 0x03 +#define AUDIO_REVERBERATION_PROCESS 0x04 +#define AUDIO_CHORUS_PROCESS 0x05 +#define AUDIO_DYN_RANGE_COMP_PROCESS 0x06 + + +/* Audio Request Codes */ +#define AUDIO_REQUEST_UNDEFINED 0x00 +#define AUDIO_REQUEST_SET_CUR 0x01 +#define AUDIO_REQUEST_GET_CUR 0x81 +#define AUDIO_REQUEST_SET_MIN 0x02 +#define AUDIO_REQUEST_GET_MIN 0x82 +#define AUDIO_REQUEST_SET_MAX 0x03 +#define AUDIO_REQUEST_GET_MAX 0x83 +#define AUDIO_REQUEST_SET_RES 0x04 +#define AUDIO_REQUEST_GET_RES 0x84 +#define AUDIO_REQUEST_SET_MEM 0x05 +#define AUDIO_REQUEST_GET_MEM 0x85 +#define AUDIO_REQUEST_GET_STAT 0xFF + + +/* Audio Control Selector Codes */ +#define AUDIO_CONTROL_UNDEFINED 0x00 /* Common Selector */ + +/* Terminal Control Selectors */ +#define AUDIO_COPY_PROTECT_CONTROL 0x01 + +/* Feature Unit Control Selectors */ +#define AUDIO_MUTE_CONTROL 0x01 +#define AUDIO_VOLUME_CONTROL 0x02 +#define AUDIO_BASS_CONTROL 0x03 +#define AUDIO_MID_CONTROL 0x04 +#define AUDIO_TREBLE_CONTROL 0x05 +#define AUDIO_GRAPHIC_EQUALIZER_CONTROL 0x06 +#define AUDIO_AUTOMATIC_GAIN_CONTROL 0x07 +#define AUDIO_DELAY_CONTROL 0x08 +#define AUDIO_BASS_BOOST_CONTROL 0x09 +#define AUDIO_LOUDNESS_CONTROL 0x0A + +/* Processing Unit Control Selectors: */ +#define AUDIO_ENABLE_CONTROL 0x01 /* Common Selector */ +#define AUDIO_MODE_SELECT_CONTROL 0x02 /* Common Selector */ + +/* - Up/Down-mix Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */ + +/* - Dolby Prologic Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */ + +/* - 3D Stereo Extender Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_SPACIOUSNESS_CONTROL 0x02 + +/* - Reverberation Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_REVERB_LEVEL_CONTROL 0x02 +#define AUDIO_REVERB_TIME_CONTROL 0x03 +#define AUDIO_REVERB_FEEDBACK_CONTROL 0x04 + +/* - Chorus Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_CHORUS_LEVEL_CONTROL 0x02 +#define AUDIO_SHORUS_RATE_CONTROL 0x03 +#define AUDIO_CHORUS_DEPTH_CONTROL 0x04 + +/* - Dynamic Range Compressor Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_COMPRESSION_RATE_CONTROL 0x02 +#define AUDIO_MAX_AMPL_CONTROL 0x03 +#define AUDIO_THRESHOLD_CONTROL 0x04 +#define AUDIO_ATTACK_TIME_CONTROL 0x05 +#define AUDIO_RELEASE_TIME_CONTROL 0x06 + +/* Extension Unit Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ + +/* Endpoint Control Selectors */ +#define AUDIO_SAMPLING_FREQ_CONTROL 0x01 +#define AUDIO_PITCH_CONTROL 0x02 + + +/* Audio Format Specific Control Selectors */ + +/* MPEG Control Selectors */ +#define AUDIO_MPEG_CONTROL_UNDEFINED 0x00 +#define AUDIO_MPEG_DUAL_CHANNEL_CONTROL 0x01 +#define AUDIO_MPEG_SECOND_STEREO_CONTROL 0x02 +#define AUDIO_MPEG_MULTILINGUAL_CONTROL 0x03 +#define AUDIO_MPEG_DYN_RANGE_CONTROL 0x04 +#define AUDIO_MPEG_SCALING_CONTROL 0x05 +#define AUDIO_MPEG_HILO_SCALING_CONTROL 0x06 + +/* AC-3 Control Selectors */ +#define AUDIO_AC3_CONTROL_UNDEFINED 0x00 +#define AUDIO_AC3_MODE_CONTROL 0x01 +#define AUDIO_AC3_DYN_RANGE_CONTROL 0x02 +#define AUDIO_AC3_SCALING_CONTROL 0x03 +#define AUDIO_AC3_HILO_SCALING_CONTROL 0x04 + + +/* Audio Format Types */ +#define AUDIO_FORMAT_TYPE_UNDEFINED 0x00 +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_II 0x02 +#define AUDIO_FORMAT_TYPE_III 0x03 + + +/* Audio Format Type Descriptor Sizes */ +#define AUDIO_FORMAT_TYPE_I_DESC_SZ(n) 0x08+(n*3) +#define AUDIO_FORMAT_TYPE_II_DESC_SZ(n) 0x09+(n*3) +#define AUDIO_FORMAT_TYPE_III_DESC_SZ(n) 0x08+(n*3) +#define AUDIO_FORMAT_MPEG_DESC_SIZE 0x09 +#define AUDIO_FORMAT_AC3_DESC_SIZE 0x0A + + +/* Audio Data Format Codes */ + +/* Audio Data Format Type I Codes */ +#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000 +#define AUDIO_FORMAT_PCM 0x0001 +#define AUDIO_FORMAT_PCM8 0x0002 +#define AUDIO_FORMAT_IEEE_FLOAT 0x0003 +#define AUDIO_FORMAT_ALAW 0x0004 +#define AUDIO_FORMAT_MULAW 0x0005 + +/* Audio Data Format Type II Codes */ +#define AUDIO_FORMAT_TYPE_II_UNDEFINED 0x1000 +#define AUDIO_FORMAT_MPEG 0x1001 +#define AUDIO_FORMAT_AC3 0x1002 + +/* Audio Data Format Type III Codes */ +#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x2000 +#define AUDIO_FORMAT_IEC1937_AC3 0x2001 +#define AUDIO_FORMAT_IEC1937_MPEG1_L1 0x2002 +#define AUDIO_FORMAT_IEC1937_MPEG1_L2_3 0x2003 +#define AUDIO_FORMAT_IEC1937_MPEG2_NOEXT 0x2003 +#define AUDIO_FORMAT_IEC1937_MPEG2_EXT 0x2004 +#define AUDIO_FORMAT_IEC1937_MPEG2_L1_LS 0x2005 +#define AUDIO_FORMAT_IEC1937_MPEG2_L2_3 0x2006 + + +/* Predefined Audio Channel Configuration Bits */ +#define AUDIO_CHANNEL_M 0x0000 /* Mono */ +#define AUDIO_CHANNEL_L 0x0001 /* Left Front */ +#define AUDIO_CHANNEL_R 0x0002 /* Right Front */ +#define AUDIO_CHANNEL_C 0x0004 /* Center Front */ +#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */ +#define AUDIO_CHANNEL_LS 0x0010 /* Left Surround */ +#define AUDIO_CHANNEL_RS 0x0020 /* Right Surround */ +#define AUDIO_CHANNEL_LC 0x0040 /* Left of Center */ +#define AUDIO_CHANNEL_RC 0x0080 /* Right of Center */ +#define AUDIO_CHANNEL_S 0x0100 /* Surround */ +#define AUDIO_CHANNEL_SL 0x0200 /* Side Left */ +#define AUDIO_CHANNEL_SR 0x0400 /* Side Right */ +#define AUDIO_CHANNEL_T 0x0800 /* Top */ + + +/* Feature Unit Control Bits */ +#define AUDIO_CONTROL_MUTE 0x0001 +#define AUDIO_CONTROL_VOLUME 0x0002 +#define AUDIO_CONTROL_BASS 0x0004 +#define AUDIO_CONTROL_MID 0x0008 +#define AUDIO_CONTROL_TREBLE 0x0010 +#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 +#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 +#define AUDIO_CONTROL_DEALY 0x0080 +#define AUDIO_CONTROL_BASS_BOOST 0x0100 +#define AUDIO_CONTROL_LOUDNESS 0x0200 + +/* Processing Unit Control Bits: */ +#define AUDIO_CONTROL_ENABLE 0x0001 /* Common Bit */ +#define AUDIO_CONTROL_MODE_SELECT 0x0002 /* Common Bit */ + +/* - Up/Down-mix Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */ + +/* - Dolby Prologic Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */ + +/* - 3D Stereo Extender Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_SPACIOUSNESS 0x0002 + +/* - Reverberation Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_REVERB_TYPE 0x0002 +#define AUDIO_CONTROL_REVERB_LEVEL 0x0004 +#define AUDIO_CONTROL_REVERB_TIME 0x0008 +#define AUDIO_CONTROL_REVERB_FEEDBACK 0x0010 + +/* - Chorus Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_CHORUS_LEVEL 0x0002 +#define AUDIO_CONTROL_SHORUS_RATE 0x0004 +#define AUDIO_CONTROL_CHORUS_DEPTH 0x0008 + +/* - Dynamic Range Compressor Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_COMPRESSION_RATE 0x0002 +#define AUDIO_CONTROL_MAX_AMPL 0x0004 +#define AUDIO_CONTROL_THRESHOLD 0x0008 +#define AUDIO_CONTROL_ATTACK_TIME 0x0010 +#define AUDIO_CONTROL_RELEASE_TIME 0x0020 + +/* Extension Unit Control Bits */ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ + +/* Endpoint Control Bits */ +#define AUDIO_CONTROL_SAMPLING_FREQ 0x01 +#define AUDIO_CONTROL_PITCH 0x02 +#define AUDIO_MAX_PACKETS_ONLY 0x80 + + +/* Audio Terminal Types */ + +/* USB Terminal Types */ +#define AUDIO_TERMINAL_USB_UNDEFINED 0x0100 +#define AUDIO_TERMINAL_USB_STREAMING 0x0101 +#define AUDIO_TERMINAL_USB_VENDOR_SPECIFIC 0x01FF + +/* Input Terminal Types */ +#define AUDIO_TERMINAL_INPUT_UNDEFINED 0x0200 +#define AUDIO_TERMINAL_MICROPHONE 0x0201 +#define AUDIO_TERMINAL_DESKTOP_MICROPHONE 0x0202 +#define AUDIO_TERMINAL_PERSONAL_MICROPHONE 0x0203 +#define AUDIO_TERMINAL_OMNI_DIR_MICROPHONE 0x0204 +#define AUDIO_TERMINAL_MICROPHONE_ARRAY 0x0205 +#define AUDIO_TERMINAL_PROCESSING_MIC_ARRAY 0x0206 + +/* Output Terminal Types */ +#define AUDIO_TERMINAL_OUTPUT_UNDEFINED 0x0300 +#define AUDIO_TERMINAL_SPEAKER 0x0301 +#define AUDIO_TERMINAL_HEADPHONES 0x0302 +#define AUDIO_TERMINAL_HEAD_MOUNTED_AUDIO 0x0303 +#define AUDIO_TERMINAL_DESKTOP_SPEAKER 0x0304 +#define AUDIO_TERMINAL_ROOM_SPEAKER 0x0305 +#define AUDIO_TERMINAL_COMMUNICATION_SPEAKER 0x0306 +#define AUDIO_TERMINAL_LOW_FREQ_SPEAKER 0x0307 + +/* Bi-directional Terminal Types */ +#define AUDIO_TERMINAL_BIDIRECTIONAL_UNDEFINED 0x0400 +#define AUDIO_TERMINAL_HANDSET 0x0401 +#define AUDIO_TERMINAL_HEAD_MOUNTED_HANDSET 0x0402 +#define AUDIO_TERMINAL_SPEAKERPHONE 0x0403 +#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOSUPRESS 0x0404 +#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOCANCEL 0x0405 + +/* Telephony Terminal Types */ +#define AUDIO_TERMINAL_TELEPHONY_UNDEFINED 0x0500 +#define AUDIO_TERMINAL_PHONE_LINE 0x0501 +#define AUDIO_TERMINAL_TELEPHONE 0x0502 +#define AUDIO_TERMINAL_DOWN_LINE_PHONE 0x0503 + +/* External Terminal Types */ +#define AUDIO_TERMINAL_EXTERNAL_UNDEFINED 0x0600 +#define AUDIO_TERMINAL_ANALOG_CONNECTOR 0x0601 +#define AUDIO_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602 +#define AUDIO_TERMINAL_LINE_CONNECTOR 0x0603 +#define AUDIO_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604 +#define AUDIO_TERMINAL_SPDIF_INTERFACE 0x0605 +#define AUDIO_TERMINAL_1394_DA_STREAM 0x0606 +#define AUDIO_TERMINAL_1394_DA_STREAM_TRACK 0x0607 + +/* Embedded Function Terminal Types */ +#define AUDIO_TERMINAL_EMBEDDED_UNDEFINED 0x0700 +#define AUDIO_TERMINAL_CALIBRATION_NOISE 0x0701 +#define AUDIO_TERMINAL_EQUALIZATION_NOISE 0x0702 +#define AUDIO_TERMINAL_CD_PLAYER 0x0703 +#define AUDIO_TERMINAL_DAT 0x0704 +#define AUDIO_TERMINAL_DCC 0x0705 +#define AUDIO_TERMINAL_MINI_DISK 0x0706 +#define AUDIO_TERMINAL_ANALOG_TAPE 0x0707 +#define AUDIO_TERMINAL_PHONOGRAPH 0x0708 +#define AUDIO_TERMINAL_VCR_AUDIO 0x0709 +#define AUDIO_TERMINAL_VIDEO_DISC_AUDIO 0x070A +#define AUDIO_TERMINAL_DVD_AUDIO 0x070B +#define AUDIO_TERMINAL_TV_TUNER_AUDIO 0x070C +#define AUDIO_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D +#define AUDIO_TERMINAL_CABLE_TUNER_AUDIO 0x070E +#define AUDIO_TERMINAL_DSS_AUDIO 0x070F +#define AUDIO_TERMINAL_RADIO_RECEIVER 0x0710 +#define AUDIO_TERMINAL_RADIO_TRANSMITTER 0x0711 +#define AUDIO_TERMINAL_MULTI_TRACK_RECORDER 0x0712 +#define AUDIO_TERMINAL_SYNTHESIZER 0x0713 + + +#endif /* __AUDIO_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdc.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdc.h new file mode 100644 index 0000000000000..6754a5cce259f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdc.h @@ -0,0 +1,255 @@ +/*********************************************************************** +* $Id:: mw_usbd_cdc.h 165 2011-04-14 17:41:11Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Communication Device Class User module Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __CDC_H +#define __CDC_H + +#include "usbd.h" + +/*---------------------------------------------------------------------------- + * Definitions based on usbcdc11.pdf (www.usb.org) + *---------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110 + +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 + +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 +#define CDC_TELEPHONE_CONTROL_MODEL 0x03 +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04 +#define CDC_CAPI_CONTROL_MODEL 0x05 +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06 +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07 + +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01 + +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_PROTOCOL_ISDN_BRI 0x30 +#define CDC_PROTOCOL_HDLC 0x31 +#define CDC_PROTOCOL_TRANSPARENT 0x32 +#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_PROTOCOL_V42 0x90 +#define CDC_PROTOCOL_EURO_ISDN 0x91 +#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_PROTOCOL_CAPI 0x93 +#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_HEADER 0x00 +#define CDC_CALL_MANAGEMENT 0x01 +#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_TELEPHONE_RINGER 0x04 +#define CDC_REPORTING_CAPABILITIES 0x05 +#define CDC_UNION 0x06 +#define CDC_COUNTRY_SELECTION 0x07 +#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_USB_TERMINAL 0x09 +#define CDC_NETWORK_CHANNEL 0x0A +#define CDC_PROTOCOL_UNIT 0x0B +#define CDC_EXTENSION_UNIT 0x0C +#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_ETHERNET_NETWORKING 0x0F +#define CDC_ATM_NETWORKING 0x10 + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_AUX_LINE_STATE 0x10 +#define CDC_SET_HOOK_STATE 0x11 +#define CDC_PULSE_SETUP 0x12 +#define CDC_SEND_PULSE 0x13 +#define CDC_SET_PULSE_TIME 0x14 +#define CDC_RING_AUX_JACK 0x15 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 +#define CDC_SET_RINGER_PARMS 0x30 +#define CDC_GET_RINGER_PARMS 0x31 +#define CDC_SET_OPERATION_PARMS 0x32 +#define CDC_GET_OPERATION_PARMS 0x33 +#define CDC_SET_LINE_PARMS 0x34 +#define CDC_GET_LINE_PARMS 0x35 +#define CDC_DIAL_DIGITS 0x36 +#define CDC_SET_UNIT_PARAMETER 0x37 +#define CDC_GET_UNIT_PARAMETER 0x38 +#define CDC_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_GET_PROFILE 0x3A +#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_GET_ETHERNET_STATISTIC 0x44 +#define CDC_SET_ATM_DATA_FORMAT 0x50 +#define CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_SET_ATM_DEFAULT_VC 0x52 +#define CDC_GET_ATM_VC_STATISTICS 0x53 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ + + +/*---------------------------------------------------------------------------- + * Structures based on usbcdc11.pdf (www.usb.org) + *---------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +PRE_PACK struct POST_PACK _CDC_HEADER_DESCRIPTOR{ + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +}; +typedef struct _CDC_HEADER_DESCRIPTOR CDC_HEADER_DESCRIPTOR; + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +PRE_PACK struct POST_PACK _CDC_CALL_MANAGEMENT_DESCRIPTOR { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +}; +typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR CDC_CALL_MANAGEMENT_DESCRIPTOR; + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +PRE_PACK struct POST_PACK _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +}; +typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR; + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +PRE_PACK struct POST_PACK _CDC_UNION_DESCRIPTOR { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +}; +typedef struct _CDC_UNION_DESCRIPTOR CDC_UNION_DESCRIPTOR; + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +PRE_PACK struct POST_PACK _CDC_UNION_1SLAVE_DESCRIPTOR { + CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */ + uint8_t bSlaveInterfaces[1]; /* Slave interface 0 */ +}; +typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR CDC_UNION_1SLAVE_DESCRIPTOR; + +/* Line coding structure */ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +PRE_PACK struct POST_PACK _CDC_LINE_CODING { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +}; +typedef struct _CDC_LINE_CODING CDC_LINE_CODING; + +/* Notification header */ +/* Data sent on the notification endpoint must follow this header. */ +/* see USB_SETUP_PACKET in file usb.h */ +typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER; + +#endif /* __CDC_H */ + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdcuser.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdcuser.h new file mode 100644 index 0000000000000..75ff2033e188a --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_cdcuser.h @@ -0,0 +1,535 @@ +/*********************************************************************** +* $Id:: mw_usbd_cdcuser.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Communication Device Class User module Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __CDCUSER_H__ +#define __CDCUSER_H__ + +#include "error.h" +#include "usbd.h" +#include "usbd_cdc.h" + +/** \file + * \brief Communication Device Class (CDC) API structures and function prototypes. + * + * Definition of functions exported by ROM based CDC function driver. + * + */ + +/** \ingroup Group_USBD + * @defgroup USBD_CDC Communication Device Class (CDC) Function Driver + * \section Sec_CDCModDescription Module Description + * CDC Class Function Driver module. This module contains an internal implementation of the USB CDC Class. + * + * User applications can use this class driver instead of implementing the CDC-ACM class manually + * via the low-level USBD_HW and USBD_Core APIs. + * + * This module is designed to simplify the user code by exposing only the required interface needed to interface with + * Devices using the USB CDC-ACM Class. + */ + +/*---------------------------------------------------------------------------- + We need a buffer for incoming data on USB port because USB receives + much faster than UART transmits + *---------------------------------------------------------------------------*/ +/* Buffer masks */ +#define CDC_BUF_SIZE (128) /* Output buffer in bytes (power 2) */ + /* large enough for file transfer */ +#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul) + +/** \brief Communication Device Class function driver initialization parameter data structure. + * \ingroup USBD_CDC + * + * \details This data structure is used to pass initialization parameters to the + * Communication Device Class function driver's init function. + * + */ +typedef struct USBD_CDC_INIT_PARAM +{ + /* memory allocation params */ + uint32_t mem_base; /**< Base memory location from where the stack can allocate + data and buffers. \note The memory address set in this field + should be accessible by USB DMA controller. Also this value + should be aligned on 4 byte boundary. + */ + uint32_t mem_size; /**< The size of memory buffer which stack can use. + \note The \em mem_size should be greater than the size + returned by USBD_CDC_API::GetMemSize() routine.*/ + /** Pointer to the control interface descriptor within the descriptor + * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T + * structure. The stack assumes both HS and FS use same BULK endpoints. + */ + uint8_t* cif_intf_desc; + /** Pointer to the data interface descriptor within the descriptor + * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T + * structure. The stack assumes both HS and FS use same BULK endpoints. + */ + uint8_t* dif_intf_desc; + + /* user defined functions */ + + /* required functions */ + /** + * Communication Interface Class specific get request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends CIC management element get requests. + * \note Applications implementing Abstract Control Model subclass can set this + * param to NULL. As the default driver parses ACM requests and calls the + * individual ACM call-back routines defined in this structure. For all other subclasses + * this routine should be provided by the application. + * \n + * The setup packet data (\em pSetup) is passed to the call-back so that application + * can extract the CIC request type and other associated data. By default the stack + * will assign \em pBuffer pointer to \em EP0Buff allocated at init. The application + * code can directly write data into this buffer as long as data is less than 64 byte. + * If more data has to be sent then application code should update \em pBuffer pointer + * and length accordingly. + * + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data. + * Pointer-to-pointer is used to implement zero-copy buffers. + * See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in, out] length Amount of data to be sent back to host. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); + + /** + * Communication Interface Class specific set request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a CIC management element requests. + * \note Applications implementing Abstract Control Model subclass can set this + * param to NULL. As the default driver parses ACM requests and calls the + * individual ACM call-back routines defined in this structure. For all other subclasses + * this routine should be provided by the application. + * \n + * The setup packet data (\em pSetup) is passed to the call-back so that application can + * extract the CIC request type and other associated data. If a set request has data associated, + * then this call-back is called twice. + * -# First when setup request is received, at this time application code could update + * \em pBuffer pointer to point to the intended destination. The length param is set to 0 + * so that application code knows this is first time. By default the stack will + * assign \em pBuffer pointer to \em EP0Buff allocated at init. Note, if data length is + * greater than 64 bytes and application code doesn't update \em pBuffer pointer the + * stack will send STALL condition to host. + * -# Second when the data is received from the host. This time the length param is set + * with number of data bytes received. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data. + * Pointer-to-pointer is used to implement zero-copy buffers. + * See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in] length Amount of data copied to destination buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length); + + /** + * Communication Device Class specific BULK IN endpoint handler. + * + * The application software should provide the BULK IN endpoint handler. + * Applications should transfer data depending on the communication protocol type set in descriptors. + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CDC_BulkIN_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + + /** + * Communication Device Class specific BULK OUT endpoint handler. + * + * The application software should provide the BULK OUT endpoint handler. + * Applications should transfer data depending on the communication protocol type set in descriptors. + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CDC_BulkOUT_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + + /** + * Abstract control model(ACM) subclass specific SEND_ENCAPSULATED_COMMAND request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a SEND_ENCAPSULATED_COMMAND set request. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] buffer Pointer to the command buffer. + * \param[in] len Length of the command buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len); + + /** + * Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a GET_ENCAPSULATED_RESPONSE request. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in, out] buffer Pointer to a pointer of data buffer containing response data. + * Pointer-to-pointer is used to implement zero-copy buffers. + * See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in, out] len Amount of data to be sent back to host. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len); + + /** + * Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a SET_COMM_FEATURE set request. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47. + * \param[in] buffer Pointer to the settings buffer for the specified communication feature. + * \param[in] len Length of the request buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len); + + /** + * Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a GET_ENCAPSULATED_RESPONSE request. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47. + * \param[in, out] buffer Pointer to a pointer of data buffer containing current settings + * for the communication feature. + * Pointer-to-pointer is used to implement zero-copy buffers. + * \param[in, out] len Amount of data to be sent back to host. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len); + + /** + * Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a CLEAR_COMM_FEATURE request. In the call-back the application + * should Clears the settings for a particular communication feature. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature); + + /** + * Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a SET_CONTROL_LINE_STATE request. RS-232 signal used to tell the DCE + * device the DTE device is now present + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] state The state value uses bitmap values defined in usbcdc11.pdf, + * section 6.2.14, Table 51. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state); + + /** + * Abstract control model(ACM) subclass specific SEND_BREAK request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a SEND_BREAK request. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] mstime Duration of Break signal in milliseconds. If mstime is FFFFh, then + * the application should send break until another SendBreak request is received + * with the wValue of 0000h. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t mstime); + + /** + * Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. + * + * This function is provided by the application software. This function gets called + * when host sends a SET_LINE_CODING request. The application should configure the device + * per DTE rate, stop-bits, parity, and number-of-character bits settings provided in + * command buffer. See usbcdc11.pdf, section 6.2.13, table 50 for detail of the command buffer. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] line_coding Pointer to the CDC_LINE_CODING command buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding); + + /** + * Optional Communication Device Class specific INTERRUPT IN endpoint handler. + * + * The application software should provide the INT IN endpoint handler. + * Applications should transfer data depending on the communication protocol type set in descriptors. + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CDC_InterruptEP_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + + /** + * Optional user override-able function to replace the default CDC class handler. + * + * The application software could override the default EP0 class handler with their + * own by providing the handler function address as this data member of the parameter + * structure. Application which like the default handler should set this data member + * to zero before calling the USBD_CDC_API::Init(). + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*CDC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + +} USBD_CDC_INIT_PARAM_T; + +/** \brief CDC class API functions structure. + * \ingroup USBD_CDC + * + * This module exposes functions which interact directly with USB device controller hardware. + * + */ +typedef struct USBD_CDC_API +{ + /** \fn uint32_t GetMemSize(USBD_CDC_INIT_PARAM_T* param) + * Function to determine the memory required by the CDC function driver module. + * + * This function is called by application layer before calling pUsbApi->CDC->Init(), to allocate memory used + * by CDC function driver module. The application should allocate the memory which is accessible by USB + * controller/DMA controller. + * \note Some memory areas are not accessible by all bus masters. + * + * \param[in] param Structure containing CDC function driver module initialization parameters. + * \return Returns the required memory size in bytes. + */ + uint32_t (*GetMemSize)(USBD_CDC_INIT_PARAM_T* param); + + /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param) + * Function to initialize CDC function driver module. + * + * This function is called by application layer to initialize CDC function driver module. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in, out] param Structure containing CDC function driver module initialization parameters. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte + * aligned or smaller than required. + * \retval ERR_API_INVALID_PARAM2 Either CDC_Write() or CDC_Read() or + * CDC_Verify() callbacks are not defined. + * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. + * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. + */ + ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC); + + /** \fn ErrorCode_t SendNotification(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data) + * Function to send CDC class notifications to host. + * + * This function is called by application layer to send CDC class notifications to host. + * See usbcdc11.pdf, section 6.3, Table 67 for various notification types the CDC device can send. + * \note The current version of the driver only supports following notifications allowed by ACM subclass: + * CDC_NOTIFICATION_NETWORK_CONNECTION, CDC_RESPONSE_AVAILABLE, CDC_NOTIFICATION_SERIAL_STATE. + * \n + * For all other notifications application should construct the notification buffer appropriately + * and call hw->USB_WriteEP() for interrupt endpoint associated with the interface. + * + * \param[in] hCdc Handle to CDC function driver. + * \param[in] bNotification Notification type allowed by ACM subclass. Should be CDC_NOTIFICATION_NETWORK_CONNECTION, + * CDC_RESPONSE_AVAILABLE or CDC_NOTIFICATION_SERIAL_STATE. For all other types ERR_API_INVALID_PARAM2 + * is returned. See usbcdc11.pdf, section 3.6.2.1, table 5. + * \param[in] data Data associated with notification. + * \n For CDC_NOTIFICATION_NETWORK_CONNECTION a non-zero data value is interpreted as connected state. + * \n For CDC_RESPONSE_AVAILABLE this parameter is ignored. + * \n For CDC_NOTIFICATION_SERIAL_STATE the data should use bitmap values defined in usbcdc11.pdf, + * section 6.3.5, Table 69. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_API_INVALID_PARAM2 If unsupported notification type is passed. + * + */ + ErrorCode_t (*SendNotification)(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data); + +} USBD_CDC_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes + *-----------------------------------------------------------------------------*/ +/** @cond ADVANCED_API */ + +typedef struct _CDC_CTRL_T +{ + USB_CORE_CTRL_T* pUsbCtrl; + /* notification buffer */ + uint8_t notice_buf[12]; + CDC_LINE_CODING line_coding; + uint8_t pad0; + + uint8_t cif_num; /* control interface number */ + uint8_t dif_num; /* data interface number */ + uint8_t epin_num; /* BULK IN endpoint number */ + uint8_t epout_num; /* BULK OUT endpoint number */ + uint8_t epint_num; /* Interrupt IN endpoint number */ + uint8_t pad[3]; + /* user defined functions */ + ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len); + ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len); + ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len); + ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len); + ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature); + ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state); + ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t state); + ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding); + + /* virtual functions */ + ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); + ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length); + +} USB_CDC_CTRL_T; + +/* structure used by old ROM drivers, needed for workaround */ +typedef struct _CDC0_CTRL_T { + USB_CORE_CTRL_T *pUsbCtrl; + /* notification buffer */ + uint8_t notice_buf[12]; + CDC_LINE_CODING line_coding; + + uint8_t cif_num; /* control interface number */ + uint8_t dif_num; /* data interface number */ + uint8_t epin_num; /* BULK IN endpoint number */ + uint8_t epout_num; /* BULK OUT endpoint number */ + uint8_t epint_num; /* Interrupt IN endpoint number */ + /* user defined functions */ + ErrorCode_t (*SendEncpsCmd)(USBD_HANDLE_T hCDC, uint8_t *buffer, uint16_t len); + ErrorCode_t (*GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t * *buffer, uint16_t *len); + ErrorCode_t (*SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len); + ErrorCode_t (*GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t * *pBuffer, uint16_t *len); + ErrorCode_t (*ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature); + ErrorCode_t (*SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state); + ErrorCode_t (*SendBreak)(USBD_HANDLE_T hCDC, uint16_t state); + ErrorCode_t (*SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding); + + /* virtual functions */ + ErrorCode_t (*CIC_GetRequest)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t *length); + ErrorCode_t (*CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t length); + +} USB_CDC0_CTRL_T; + +typedef ErrorCode_t (*CIC_SetRequest_t)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t length); + +/** @cond DIRECT_API */ +extern uint32_t mwCDC_GetMemSize(USBD_CDC_INIT_PARAM_T* param); +extern ErrorCode_t mwCDC_init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC); +extern ErrorCode_t mwCDC_SendNotification (USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data); +/** @endcond */ + +/** @endcond */ + + + + + +#endif /* __CDCUSER_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_core.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_core.h new file mode 100644 index 0000000000000..34729880af7c2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_core.h @@ -0,0 +1,591 @@ +/*********************************************************************** +* $Id:: mw_usbd_core.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB core controller structure definitions and function prototypes. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __MW_USBD_CORE_H__ +#define __MW_USBD_CORE_H__ + +#include "error.h" +#include "usbd.h" +#include "app_usbd_cfg.h" + +/** \file + * \brief ROM API for USB device stack. + * + * Definition of functions exported by core layer of ROM based USB device stack. + * + */ + +/** \ingroup Group_USBD + * @defgroup USBD_Core USB Core Layer + * \section Sec_CoreModDescription Module Description + * The USB Core Layer implements the device abstraction defined in the Universal Serial Bus Specification, + * for applications to interact with the USB device interface on the device. The software in this layer responds to + * standard requests and returns standard descriptors. In current stack the Init() routine part of + * \ref USBD_HW_API_T structure initializes both hardware layer and core layer. + */ + + +/* function pointer types */ + +/** \ingroup USBD_Core + * \typedef USB_CB_T + * \brief USB device stack's event callback function type. + * + * The USB device stack exposes several event triggers through callback to application layer. The + * application layer can register methods to be called when such USB event happens. + * + * \param[in] hUsb Handle to the USB device stack. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx Other error conditions. + * + */ +typedef ErrorCode_t (*USB_CB_T) (USBD_HANDLE_T hUsb); + +/** \ingroup USBD_Core + * \typedef USB_PARAM_CB_T + * \brief USB device stack's event callback function type. + * + * The USB device stack exposes several event triggers through callback to application layer. The + * application layer can register methods to be called when such USB event happens. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] param1 Extra information related to the event. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ +typedef ErrorCode_t (*USB_PARAM_CB_T) (USBD_HANDLE_T hUsb, uint32_t param1); + +/** \ingroup USBD_Core + * \typedef USB_EP_HANDLER_T + * \brief USBD setup request and endpoint event handler type. + * + * The application layer should define the custom class's EP0 handler with function signature. + * The stack calls all the registered class handlers on any EP0 event before going through default + * handling of the event. This gives the class handlers to implement class specific request handlers + * and also to override the default stack handling for a particular event targeted to the interface. + * If an event is not handled by the callback the function should return ERR_USBD_UNHANDLED. For all + * other return codes the stack assumes that callback has taken care of the event and hence will not + * process the event any further and issues a STALL condition on EP0 indicating error to the host. + * \n + * For endpoint interrupt handler the return value is ignored by the stack. + * \n + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ +typedef ErrorCode_t (*USB_EP_HANDLER_T)(USBD_HANDLE_T hUsb, void* data, uint32_t event); + + +/** \ingroup USBD_Core + * \brief USB descriptors data structure. + * \ingroup USBD_Core + * + * \details This structure is used as part of USB device stack initialization + * parameter structure \ref USBD_API_INIT_PARAM_T. This structure contains + * pointers to various descriptor arrays needed by the stack. These descriptors + * are reported to USB host as part of enumerations process. + * + * \note All descriptor pointers assigned in this structure should be on 4 byte + * aligned address boundary. + */ +typedef struct _USB_CORE_DESCS_T +{ + uint8_t *device_desc; /**< Pointer to USB device descriptor */ + uint8_t *string_desc; /**< Pointer to array of USB string descriptors */ + uint8_t *full_speed_desc; /**< Pointer to USB device configuration descriptor + * when device is operating in full speed mode. + */ + uint8_t *high_speed_desc; /**< Pointer to USB device configuration descriptor + * when device is operating in high speed mode. For + * full-speed only implementation this pointer should + * be same as full_speed_desc. + */ + uint8_t *device_qualifier; /**< Pointer to USB device qualifier descriptor. For + * full-speed only implementation this pointer should + * be set to null (0). + */ +} USB_CORE_DESCS_T; + +/** \brief USB device stack initialization parameter data structure. + * \ingroup USBD_Core + * + * \details This data structure is used to pass initialization parameters to the + * USB device stack's init function. + * + */ +typedef struct USBD_API_INIT_PARAM +{ + uint32_t usb_reg_base; /**< USB device controller's base register address. */ + uint32_t mem_base; /**< Base memory location from where the stack can allocate + data and buffers. \note The memory address set in this field + should be accessible by USB DMA controller. Also this value + should be aligned on 2048 byte boundary. + */ + uint32_t mem_size; /**< The size of memory buffer which stack can use. + \note The \em mem_size should be greater than the size + returned by USBD_HW_API::GetMemSize() routine.*/ + uint8_t max_num_ep; /**< max number of endpoints supported by the USB device + controller instance (specified by \em usb_reg_base field) + to which this instance of stack is attached. + */ + uint8_t pad0[3]; + /* USB Device Events Callback Functions */ + /** Event for USB interface reset. This event fires when the USB host requests that the device + * reset its interface. This event fires after the control endpoint has been automatically + * configured by the library. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will prevent the device from enumerating correctly or operate properly. + * + */ + USB_CB_T USB_Reset_Event; + + /** Event for USB suspend. This event fires when the USB host suspends the device by halting its + * transmission of Start Of Frame pulses to the device. This is generally hooked in order to move + * the device over to a low power state until the host wakes up the device. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will cause other system issues. + */ + USB_CB_T USB_Suspend_Event; + + /** Event for USB wake up or resume. This event fires when a the USB device interface is suspended + * and the host wakes up the device by supplying Start Of Frame pulses. This is generally + * hooked to pull the user application out of a low power state and back into normal operating + * mode. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will cause other system issues. + * + */ + USB_CB_T USB_Resume_Event; + + /** Reserved parameter should be set to zero. */ + USB_CB_T reserved_sbz; + + /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB + * frame, once per millisecond in full-speed mode or once per 125 microseconds in high-speed mode, + * and is synchronized to the USB bus. + * + * This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers + * will significantly degrade device performance. This event should only be enabled when needed to + * reduce device wake-ups. + * + * \note This event is not normally active - it must be manually enabled and disabled via the USB interrupt + * register. + * \n\n + */ + USB_CB_T USB_SOF_Event; + + /** Event for remote wake-up configuration, when enabled. This event fires when the USB host + * request the device to configure itself for remote wake-up capability. The USB host sends + * this request to device which report remote wake-up capable in their device descriptors, + * before going to low-power state. The application layer should implement this callback if + * they have any special on board circuit to trigger remote wake up event. Also application + * can use this callback to differentiate the following SUSPEND event is caused by cable plug-out + * or host SUSPEND request. The device can wake-up host only after receiving this callback and + * remote wake-up feature is enabled by host. To signal remote wake-up the device has to generate + * resume signaling on bus by calling usapi.hw->WakeUp() routine. + * + * \n\n + * \param[in] hUsb Handle to the USB device stack. + * \param[in] param1 When 0 - Clear the wake-up configuration, 1 - Enable the wake-up configuration. + * \return The call back should return \ref ErrorCode_t type to indicate success or error condition. + */ + USB_PARAM_CB_T USB_WakeUpCfg; + + /** Reserved parameter should be set to zero. */ + USB_PARAM_CB_T USB_Power_Event; + + /** Event for error condition. This event fires when USB device controller detect + * an error condition in the system. + * + * \n\n + * \param[in] hUsb Handle to the USB device stack. + * \param[in] param1 USB device interrupt status register. + * \return The call back should return \ref ErrorCode_t type to indicate success or error condition. + */ + USB_PARAM_CB_T USB_Error_Event; + + /* USB Core Events Callback Functions */ + /** Event for USB configuration number changed. This event fires when a the USB host changes the + * selected configuration number. On receiving configuration change request from host, the stack + * enables/configures the endpoints needed by the new configuration before calling this callback + * function. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will prevent the device from enumerating correctly or operate properly. + * + */ + USB_CB_T USB_Configure_Event; + + /** Event for USB interface setting changed. This event fires when a the USB host changes the + * interface setting to one of alternate interface settings. On receiving interface change + * request from host, the stack enables/configures the endpoints needed by the new alternate + * interface setting before calling this callback function. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will prevent the device from enumerating correctly or operate properly. + * + */ + USB_CB_T USB_Interface_Event; + + /** Event for USB feature changed. This event fires when a the USB host send set/clear feature + * request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP, USB_FEATURE_TEST_MODE + * and USB_FEATURE_ENDPOINT_STALL features only. On receiving feature request from host, the + * stack handle the request appropriately and then calls this callback function. + * \n + * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this + * callback will prevent the device from enumerating correctly or operate properly. + * + */ + USB_CB_T USB_Feature_Event; + + /* cache and MMU translation functions */ + /** Reserved parameter for future use. should be set to zero. */ + uint32_t (* virt_to_phys)(void* vaddr); + /** Reserved parameter for future use. should be set to zero. */ + void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr); + +} USBD_API_INIT_PARAM_T; + + +/** \brief USBD stack Core API functions structure. + * \ingroup USBD_Core + * + * \details This module exposes functions which interact directly with USB device stack's core layer. + * The application layer uses this component when it has to implement custom class function driver or + * standard class function driver which is not part of the current USB device stack. + * The functions exposed by this interface are to register class specific EP0 handlers and corresponding + * utility functions to manipulate EP0 state machine of the stack. This interface also exposes + * function to register custom endpoint interrupt handler. + * + */ +typedef struct USBD_CORE_API +{ + /** \fn ErrorCode_t RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data) + * Function to register class specific EP0 event handler with USB device stack. + * + * The application layer uses this function when it has to register the custom class's EP0 handler. + * The stack calls all the registered class handlers on any EP0 event before going through default + * handling of the event. This gives the class handlers to implement class specific request handlers + * and also to override the default stack handling for a particular event targeted to the interface. + * Check \ref USB_EP_HANDLER_T for more details on how the callback function should be implemented. Also + * application layer could use this function to register EP0 handler which responds to vendor specific + * requests. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] pfn Class specific EP0 handler function. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) The number of class handlers registered is + greater than the number of handlers allowed by the stack. + * + */ + ErrorCode_t (*RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data); + + /** \fn ErrorCode_t RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data) + * Function to register interrupt/event handler for the requested endpoint with USB device stack. + * + * The application layer uses this function to register the endpoint event handler. + * The stack calls all the registered endpoint handlers when + * - USB_EVT_OUT or USB_EVT_OUT_NAK events happen for OUT endpoint. + * - USB_EVT_IN or USB_EVT_IN_NAK events happen for IN endpoint. + * Check USB_EP_HANDLER_T for more details on how the callback function should be implemented. + * \note By default endpoint _NAK events are not enabled. Application should call \ref USBD_HW_API_T::EnableEvent + * for the corresponding endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] ep_index Endpoint index. Computed as + * - For OUT endpoints = 2 * endpoint number eg. for EP2_OUT it is 4. + * - For IN endopoints = (2 * endpoint number) + 1 eg. for EP2_IN it is 5. + * \param[in] pfn Endpoint event handler function. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_API_INVALID_PARAM2 ep_index is outside the boundary ( < 2 * USBD_API_INIT_PARAM_T::max_num_ep). + * + */ + ErrorCode_t (*RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data); + + /** \fn void SetupStage(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in setup state. + * + * This function is called by USB stack and the application layer to + * set the EP0 state machine in setup state. This function will read + * the setup packet received from USB host into stack's buffer. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*SetupStage )(USBD_HANDLE_T hUsb); + + /** \fn void DataInStage(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in data_in state. + * + * This function is called by USB stack and the application layer to + * set the EP0 state machine in data_in state. This function will write + * the data present in EP0Data buffer to EP0 FIFO for transmission to host. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*DataInStage)(USBD_HANDLE_T hUsb); + + /** \fn void DataOutStage(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in data_out state. + * + * This function is called by USB stack and the application layer to + * set the EP0 state machine in data_out state. This function will read + * the control data (EP0 out packets) received from USB host into EP0Data buffer. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*DataOutStage)(USBD_HANDLE_T hUsb); + + /** \fn void StatusInStage(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in status_in state. + * + * This function is called by USB stack and the application layer to + * set the EP0 state machine in status_in state. This function will send + * zero length IN packet on EP0 to host, indicating positive status. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*StatusInStage)(USBD_HANDLE_T hUsb); + /** \fn void StatusOutStage(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in status_out state. + * + * This function is called by USB stack and the application layer to + * set the EP0 state machine in status_out state. This function will read + * the zero length OUT packet received from USB host on EP0. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*StatusOutStage)(USBD_HANDLE_T hUsb); + + /** \fn void StallEp0(USBD_HANDLE_T hUsb) + * Function to set EP0 state machine in stall state. + * + * This function is called by USB stack and the application layer to + * generate STALL signaling on EP0 endpoint. This function will also + * reset the EP0Data buffer. + * \n + * \note This interface is provided to users to invoke this function in other + * scenarios which are not handle by current stack. In most user applications + * this function is not called directly.Also this function can be used by + * users who are selectively modifying the USB device stack's standard handlers + * through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*StallEp0)(USBD_HANDLE_T hUsb); + +} USBD_CORE_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes + *-----------------------------------------------------------------------------*/ + + /** @cond ADVANCED_API */ + +/* forward declaration */ +struct _USB_CORE_CTRL_T; +typedef struct _USB_CORE_CTRL_T USB_CORE_CTRL_T; + +/* USB device Speed status defines */ +#define USB_FULL_SPEED 0 +#define USB_HIGH_SPEED 1 + +/* USB Endpoint Data Structure */ +typedef struct _USB_EP_DATA +{ + uint8_t *pData; + uint16_t Count; + uint16_t pad0; +} USB_EP_DATA; + + +/* USB core controller data structure */ +struct _USB_CORE_CTRL_T +{ + /* override-able function pointers ~ c++ style virtual functions*/ + USB_CB_T USB_EvtSetupHandler; + USB_CB_T USB_EvtOutHandler; + USB_PARAM_CB_T USB_ReqVendor; + USB_CB_T USB_ReqGetStatus; + USB_CB_T USB_ReqGetDescriptor; + USB_CB_T USB_ReqGetConfiguration; + USB_CB_T USB_ReqSetConfiguration; + USB_CB_T USB_ReqGetInterface; + USB_CB_T USB_ReqSetInterface; + USB_PARAM_CB_T USB_ReqSetClrFeature; + + /* USB Device Events Callback Functions */ + USB_CB_T USB_Reset_Event; + USB_CB_T USB_Suspend_Event; + USB_CB_T USB_Resume_Event; + USB_CB_T USB_SOF_Event; + USB_PARAM_CB_T USB_Power_Event; + USB_PARAM_CB_T USB_Error_Event; + USB_PARAM_CB_T USB_WakeUpCfg; + + /* USB Core Events Callback Functions */ + USB_CB_T USB_Configure_Event; + USB_CB_T USB_Interface_Event; + USB_CB_T USB_Feature_Event; + + /* cache and MMU translation functions */ + uint32_t (* virt_to_phys)(void* vaddr); + void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr); + + /* event handlers for endpoints. */ + USB_EP_HANDLER_T ep_event_hdlr[2 * USB_MAX_EP_NUM]; + void* ep_hdlr_data[2 * USB_MAX_EP_NUM]; + + /* USB class handlers */ + USB_EP_HANDLER_T ep0_hdlr_cb[USB_MAX_IF_NUM]; + void* ep0_cb_data[USB_MAX_IF_NUM]; + uint8_t num_ep0_hdlrs; + /* USB Core data Variables */ + uint8_t max_num_ep; /* max number of endpoints supported by the HW */ + uint8_t device_speed; + uint8_t num_interfaces; + uint8_t device_addr; + uint8_t config_value; + uint16_t device_status; + uint8_t *device_desc; + uint8_t *string_desc; + uint8_t *full_speed_desc; + uint8_t *high_speed_desc; + uint8_t *device_qualifier; + uint32_t ep_mask; + uint32_t ep_halt; + uint32_t ep_stall; + uint8_t alt_setting[USB_MAX_IF_NUM]; + /* HW driver data pointer */ + void* hw_data; + + /* USB Endpoint 0 Data Info */ + USB_EP_DATA EP0Data; + + /* USB Endpoint 0 Buffer */ + //ALIGNED(4) + uint8_t EP0Buf[64]; + + /* USB Setup Packet */ + //ALIGNED(4) + USB_SETUP_PACKET SetupPacket; + +}; + +/* USB Core Functions */ +extern void mwUSB_InitCore(USB_CORE_CTRL_T* pCtrl, USB_CORE_DESCS_T* pdescr, USBD_API_INIT_PARAM_T* param); +extern void mwUSB_ResetCore(USBD_HANDLE_T hUsb); + +/* inline functions */ +static INLINE void USB_SetSpeedMode(USB_CORE_CTRL_T* pCtrl, uint8_t mode) +{ + pCtrl->device_speed = mode; +} + +static INLINE bool USB_IsConfigured(USBD_HANDLE_T hUsb) +{ + USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*) hUsb; + return (bool) (pCtrl->config_value != 0); +} + +/** @cond DIRECT_API */ +/* midleware API */ +extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data); +extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data); +extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb); +extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb); +extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb); +extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data); +extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data); +extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb); +extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb); +extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb); +extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb); +/** @endcond */ + +/** @endcond */ + +#endif /* __MW_USBD_CORE_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_desc.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_desc.h new file mode 100644 index 0000000000000..ccd0ce1964aa4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_desc.h @@ -0,0 +1,54 @@ +/*********************************************************************** +* $Id:: mw_usbd_desc.h 165 2011-04-14 17:41:11Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Descriptors Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ + +#ifndef __USBDESC_H__ +#define __USBDESC_H__ + +#include "usbd.h" + +#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) +#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF) + +#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) +#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) +#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) +#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) +#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR)) +#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION)) + +//#define HID_DESC_SIZE (sizeof(HID_DESCRIPTOR)) +//#define HID_REPORT_DESC_SIZE (sizeof(HID_ReportDescriptor)) + +extern const uint8_t HID_ReportDescriptor[]; +extern const uint16_t HID_ReportDescSize; +extern const uint16_t HID_DescOffset; + + +#endif /* __USBDESC_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfu.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfu.h new file mode 100644 index 0000000000000..f4ab888151cf5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfu.h @@ -0,0 +1,126 @@ +/*********************************************************************** +* $Id:: mw_usbd_dfu.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* Device Firmware Upgrade (DFU) module. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __MW_USBD_DFU_H__ +#define __MW_USBD_DFU_H__ + +#include "usbd.h" + +/** \file + * \brief Device Firmware Upgrade (DFU) class descriptors. + * + * Definition of DFU class descriptors and their bit defines. + * + */ + +/** + * If USB device is only DFU capable, DFU Interface number is always 0. + * if USB device is (DFU + Other Class (Audio/Mass Storage/HID), DFU + * Interface number should also be 0 in this implementation. + */ +#define USB_DFU_IF_NUM 0x0 + +#define USB_DFU_DESCRIPTOR_TYPE 0x21 +#define USB_DFU_DESCRIPTOR_SIZE 9 +#define USB_DFU_SUBCLASS 0x01 + +/* DFU class-specific requests (Section 3, DFU Rev 1.1) */ +#define USB_REQ_DFU_DETACH 0x00 +#define USB_REQ_DFU_DNLOAD 0x01 +#define USB_REQ_DFU_UPLOAD 0x02 +#define USB_REQ_DFU_GETSTATUS 0x03 +#define USB_REQ_DFU_CLRSTATUS 0x04 +#define USB_REQ_DFU_GETSTATE 0x05 +#define USB_REQ_DFU_ABORT 0x06 + +#define DFU_STATUS_OK 0x00 +#define DFU_STATUS_errTARGET 0x01 +#define DFU_STATUS_errFILE 0x02 +#define DFU_STATUS_errWRITE 0x03 +#define DFU_STATUS_errERASE 0x04 +#define DFU_STATUS_errCHECK_ERASED 0x05 +#define DFU_STATUS_errPROG 0x06 +#define DFU_STATUS_errVERIFY 0x07 +#define DFU_STATUS_errADDRESS 0x08 +#define DFU_STATUS_errNOTDONE 0x09 +#define DFU_STATUS_errFIRMWARE 0x0a +#define DFU_STATUS_errVENDOR 0x0b +#define DFU_STATUS_errUSBR 0x0c +#define DFU_STATUS_errPOR 0x0d +#define DFU_STATUS_errUNKNOWN 0x0e +#define DFU_STATUS_errSTALLEDPKT 0x0f + +enum dfu_state { + DFU_STATE_appIDLE = 0, + DFU_STATE_appDETACH = 1, + DFU_STATE_dfuIDLE = 2, + DFU_STATE_dfuDNLOAD_SYNC = 3, + DFU_STATE_dfuDNBUSY = 4, + DFU_STATE_dfuDNLOAD_IDLE = 5, + DFU_STATE_dfuMANIFEST_SYNC = 6, + DFU_STATE_dfuMANIFEST = 7, + DFU_STATE_dfuMANIFEST_WAIT_RST= 8, + DFU_STATE_dfuUPLOAD_IDLE = 9, + DFU_STATE_dfuERROR = 10 +}; + +#define DFU_EP0_NONE 0 +#define DFU_EP0_UNHANDLED 1 +#define DFU_EP0_STALL 2 +#define DFU_EP0_ZLP 3 +#define DFU_EP0_DATA 4 + +#define USB_DFU_CAN_DOWNLOAD (1 << 0) +#define USB_DFU_CAN_UPLOAD (1 << 1) +#define USB_DFU_MANIFEST_TOL (1 << 2) +#define USB_DFU_WILL_DETACH (1 << 3) + +PRE_PACK struct POST_PACK _USB_DFU_FUNC_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; + uint16_t wDetachTimeOut; + uint16_t wTransferSize; + uint16_t bcdDFUVersion; +}; +typedef struct _USB_DFU_FUNC_DESCRIPTOR USB_DFU_FUNC_DESCRIPTOR; + +PRE_PACK struct POST_PACK _DFU_STATUS { + uint8_t bStatus; + uint8_t bwPollTimeout[3]; + uint8_t bState; + uint8_t iString; +}; +typedef struct _DFU_STATUS DFU_STATUS_T; + +#define DFU_FUNC_DESC_SIZE sizeof(USB_DFU_FUNC_DESCRIPTOR) +#define DFU_GET_STATUS_SIZE 0x6 + + +#endif /* __MW_USBD_DFU_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfuuser.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfuuser.h new file mode 100644 index 0000000000000..a135cac054746 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_dfuuser.h @@ -0,0 +1,276 @@ +/*********************************************************************** +* $Id:: mw_usbd_dfuuser.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* Device Firmware Upgrade Class Custom User Module Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ + +#ifndef __DFUUSER_H__ +#define __DFUUSER_H__ + +#include "usbd.h" +#include "usbd_dfu.h" +#include "usbd_core.h" + +/** \file + * \brief Device Firmware Upgrade (DFU) API structures and function prototypes. + * + * Definition of functions exported by ROM based DFU function driver. + * + */ + + +/** \ingroup Group_USBD + * @defgroup USBD_DFU Device Firmware Upgrade (DFU) Class Function Driver + * \section Sec_MSCModDescription Module Description + * DFU Class Function Driver module. This module contains an internal implementation of the USB DFU Class. + * User applications can use this class driver instead of implementing the DFU class manually + * via the low-level USBD_HW and USBD_Core APIs. + * + * This module is designed to simplify the user code by exposing only the required interface needed to interface with + * Devices using the USB DFU Class. + */ + +/** \brief USB descriptors data structure. + * \ingroup USBD_DFU + * + * \details This module exposes functions which interact directly with USB device stack's core layer. + * The application layer uses this component when it has to implement custom class function driver or + * standard class function driver which is not part of the current USB device stack. + * The functions exposed by this interface are to register class specific EP0 handlers and corresponding + * utility functions to manipulate EP0 state machine of the stack. This interface also exposes + * function to register custom endpoint interrupt handler. + * + */ +typedef struct USBD_DFU_INIT_PARAM +{ + /* memory allocation params */ + uint32_t mem_base; /**< Base memory location from where the stack can allocate + data and buffers. \note The memory address set in this field + should be accessible by USB DMA controller. Also this value + should be aligned on 4 byte boundary. + */ + uint32_t mem_size; /**< The size of memory buffer which stack can use. + \note The \em mem_size should be greater than the size + returned by USBD_DFU_API::GetMemSize() routine.*/ + /* DFU paramas */ + uint16_t wTransferSize; /**< DFU transfer block size in number of bytes. + This value should match the value set in DFU descriptor + provided as part of the descriptor array + (\em high_speed_desc) passed to Init() through + \ref USB_CORE_DESCS_T structure. */ + + uint16_t pad; + /** Pointer to the DFU interface descriptor within the descriptor + * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T + * structure. + */ + uint8_t* intf_desc; + /* user defined functions */ + /** + * DFU Write callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a write command. For application using zero-copy buffer scheme + * this function is called for the first time with \em length parameter set to 0. + * The application code should update the buffer pointer. + * + * \param[in] block_num Destination start address. + * \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer + * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy + * for more details on zero-copy concept. + * \param[out] bwPollTimeout Pointer to a 3 byte buffer which the callback implementer + * should fill with the amount of minimum time, in milliseconds, + * that the host should wait before sending a subsequent + * DFU_GETSTATUS request. + * \param[in] length Number of bytes to be written. + * \return Returns DFU_STATUS_ values defined in mw_usbd_dfu.h. + * + */ + uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout); + + /** + * DFU Read callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a read command. + * + * \param[in] block_num Destination start address. + * \param[in, out] dst Pointer to a pointer to the source of data. Pointer-to-pointer + * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy + * for more details on zero-copy concept. + * \param[in] length Amount of data copied to destination buffer. + * \return Returns + * - DFU_STATUS_ values defined in mw_usbd_dfu.h to return error conditions. + * - 0 if there is no more data to be read. Stack will send EOF frame and set + * DFU state-machine to dfuIdle state. + * - length of the data copied, should be greater than or equal to 16. If the data copied + * is less than DFU \em wTransferSize the stack will send EOF frame and + * goes to dfuIdle state. + * + */ + uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length); + + /** + * DFU done callback function. + * + * This function is provided by the application software. This function gets called + * after firmware download completes. + * + * \return Nothing. + * + */ + void (*DFU_Done)(void); + + /** + * DFU detach callback function. + * + * This function is provided by the application software. This function gets called + * after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH + * bit in DFU descriptor should define this function. As part of this function + * application can call Connect() routine to disconnect and then connect back with + * host. For application which rely on WinUSB based host application should use this + * feature since USB reset can be invoked only by kernel drivers on Windows host. + * By implementing this feature host doen't have to issue reset instead the device + * has to do it automatically by disconnect and connect procedure. + * + * \param[in] hUsb Handle DFU control structure. + * \return Nothing. + * + */ + void (*DFU_Detach)(USBD_HANDLE_T hUsb); + + /** + * Optional user override-able function to replace the default DFU class handler. + * + * The application software could override the default EP0 class handler with their + * own by providing the handler function address as this data member of the parameter + * structure. Application which like the default handler should set this data member + * to zero before calling the USBD_DFU_API::Init(). + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*DFU_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + +} USBD_DFU_INIT_PARAM_T; + + +/** \brief DFU class API functions structure. + * \ingroup USBD_DFU + * + * This module exposes functions which interact directly with USB device controller hardware. + * + */ +typedef struct USBD_DFU_API +{ + /** \fn uint32_t GetMemSize(USBD_DFU_INIT_PARAM_T* param) + * Function to determine the memory required by the DFU function driver module. + * + * This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used + * by DFU function driver module. The application should allocate the memory which is accessible by USB + * controller/DMA controller. + * \note Some memory areas are not accessible by all bus masters. + * + * \param[in] param Structure containing DFU function driver module initialization parameters. + * \return Returns the required memory size in bytes. + */ + uint32_t (*GetMemSize)(USBD_DFU_INIT_PARAM_T* param); + + /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param) + * Function to initialize DFU function driver module. + * + * This function is called by application layer to initialize DFU function driver module. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in, out] param Structure containing DFU function driver module initialization parameters. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte aligned or smaller than required. + * \retval ERR_API_INVALID_PARAM2 Either DFU_Write() or DFU_Done() or DFU_Read() call-backs are not defined. + * \retval ERR_USBD_BAD_DESC + * - USB_DFU_DESCRIPTOR_TYPE is not defined immediately after + * interface descriptor. + * - wTransferSize in descriptor doesn't match the value passed + * in param->wTransferSize. + * - DFU_Detach() is not defined while USB_DFU_WILL_DETACH is set + * in DFU descriptor. + * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. + */ + ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state); + +} USBD_DFU_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes + *-----------------------------------------------------------------------------*/ +/** @cond ADVANCED_API */ + +typedef struct _USBD_DFU_CTRL_T +{ + /*ALIGNED(4)*/ DFU_STATUS_T dfu_req_get_status; + uint16_t pad; + uint8_t dfu_state; + uint8_t dfu_status; + uint8_t download_done; + uint8_t if_num; /* interface number */ + + uint8_t* xfr_buf; + USB_DFU_FUNC_DESCRIPTOR* dfu_desc; + + USB_CORE_CTRL_T* pUsbCtrl; + /* user defined functions */ + /* return DFU_STATUS_ values defined in mw_usbd_dfu.h */ + uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout); + /* return + * DFU_STATUS_ : values defined in mw_usbd_dfu.h in case of errors + * 0 : If end of memory reached + * length : Amount of data copied to destination buffer + */ + uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length); + /* callback called after download is finished */ + void (*DFU_Done)(void); + /* callback called after USB_REQ_DFU_DETACH is recived */ + void (*DFU_Detach)(USBD_HANDLE_T hUsb); + +} USBD_DFU_CTRL_T; + +/** @cond DIRECT_API */ +uint32_t mwDFU_GetMemSize(USBD_DFU_INIT_PARAM_T* param); +extern ErrorCode_t mwDFU_init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state); +/** @endcond */ + +/** @endcond */ + +#endif /* __DFUUSER_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hid.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hid.h new file mode 100644 index 0000000000000..ae852401f9412 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hid.h @@ -0,0 +1,437 @@ +/*********************************************************************** +* $Id: mw_usbd_hid.h.rca 1.2 Tue Nov 1 11:45:07 2011 nlv09221 Experimental $ +* +* Project: USB device ROM Stack +* +* Description: +* HID Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __HID_H__ +#define __HID_H__ + +#include "usbd.h" + +/** \file + * \brief Common definitions and declarations for the library USB HID Class driver. + * + * Common definitions and declarations for the library USB HID Class driver. + * \addtogroup USBD_HID + * @{ + */ + + +/** HID Subclass Codes + * @{ + */ +/** Descriptor Subclass value indicating that the device or interface does not implement a HID boot protocol. */ +#define HID_SUBCLASS_NONE 0x00 +/** Descriptor Subclass value indicating that the device or interface implements a HID boot protocol. */ +#define HID_SUBCLASS_BOOT 0x01 +/** @} */ + +/** HID Protocol Codes + * @{ + */ +/** Descriptor Protocol value indicating that the device or interface does not belong to a HID boot protocol. */ +#define HID_PROTOCOL_NONE 0x00 +/** Descriptor Protocol value indicating that the device or interface belongs to the Keyboard HID boot protocol. */ +#define HID_PROTOCOL_KEYBOARD 0x01 +/** Descriptor Protocol value indicating that the device or interface belongs to the Mouse HID boot protocol. */ +#define HID_PROTOCOL_MOUSE 0x02 +/** @} */ + + + +/** Descriptor Types + * @{ + */ +/** Descriptor header type value, to indicate a HID class HID descriptor. */ +#define HID_HID_DESCRIPTOR_TYPE 0x21 +/** Descriptor header type value, to indicate a HID class HID report descriptor. */ +#define HID_REPORT_DESCRIPTOR_TYPE 0x22 +/** Descriptor header type value, to indicate a HID class HID Physical descriptor. */ +#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23 +/** @} */ + + +/** \brief HID class-specific HID Descriptor. + * + * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID + * specification for details on the structure elements. + * + */ +PRE_PACK struct POST_PACK _HID_DESCRIPTOR { + uint8_t bLength; /**< Size of the descriptor, in bytes. */ + uint8_t bDescriptorType; /**< Type of HID descriptor. */ + uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */ + uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */ + uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */ + + PRE_PACK struct POST_PACK _HID_DESCRIPTOR_LIST { + uint8_t bDescriptorType; /**< Type of HID report. */ + uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */ + } DescriptorList[1]; /**< Array of one or more descriptors */ +} ; +/** HID class-specific HID Descriptor. */ +typedef struct _HID_DESCRIPTOR HID_DESCRIPTOR; + +#define HID_DESC_SIZE sizeof(HID_DESCRIPTOR) + +/** HID Request Codes + * @{ + */ +#define HID_REQUEST_GET_REPORT 0x01 +#define HID_REQUEST_GET_IDLE 0x02 +#define HID_REQUEST_GET_PROTOCOL 0x03 +#define HID_REQUEST_SET_REPORT 0x09 +#define HID_REQUEST_SET_IDLE 0x0A +#define HID_REQUEST_SET_PROTOCOL 0x0B +/** @} */ + +/** HID Report Types + * @{ + */ +#define HID_REPORT_INPUT 0x01 +#define HID_REPORT_OUTPUT 0x02 +#define HID_REPORT_FEATURE 0x03 +/** @} */ + + +/** Usage Pages + * @{ + */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 +#define HID_USAGE_PAGE_GENERIC 0x01 +#define HID_USAGE_PAGE_SIMULATION 0x02 +#define HID_USAGE_PAGE_VR 0x03 +#define HID_USAGE_PAGE_SPORT 0x04 +#define HID_USAGE_PAGE_GAME 0x05 +#define HID_USAGE_PAGE_DEV_CONTROLS 0x06 +#define HID_USAGE_PAGE_KEYBOARD 0x07 +#define HID_USAGE_PAGE_LED 0x08 +#define HID_USAGE_PAGE_BUTTON 0x09 +#define HID_USAGE_PAGE_ORDINAL 0x0A +#define HID_USAGE_PAGE_TELEPHONY 0x0B +#define HID_USAGE_PAGE_CONSUMER 0x0C +#define HID_USAGE_PAGE_DIGITIZER 0x0D +#define HID_USAGE_PAGE_UNICODE 0x10 +#define HID_USAGE_PAGE_ALPHANUMERIC 0x14 +/** @} */ + + +/** Generic Desktop Page (0x01) + * @{ + */ +#define HID_USAGE_GENERIC_POINTER 0x01 +#define HID_USAGE_GENERIC_MOUSE 0x02 +#define HID_USAGE_GENERIC_JOYSTICK 0x04 +#define HID_USAGE_GENERIC_GAMEPAD 0x05 +#define HID_USAGE_GENERIC_KEYBOARD 0x06 +#define HID_USAGE_GENERIC_KEYPAD 0x07 +#define HID_USAGE_GENERIC_X 0x30 +#define HID_USAGE_GENERIC_Y 0x31 +#define HID_USAGE_GENERIC_Z 0x32 +#define HID_USAGE_GENERIC_RX 0x33 +#define HID_USAGE_GENERIC_RY 0x34 +#define HID_USAGE_GENERIC_RZ 0x35 +#define HID_USAGE_GENERIC_SLIDER 0x36 +#define HID_USAGE_GENERIC_DIAL 0x37 +#define HID_USAGE_GENERIC_WHEEL 0x38 +#define HID_USAGE_GENERIC_HATSWITCH 0x39 +#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A +#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B +#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C +#define HID_USAGE_GENERIC_VX 0x40 +#define HID_USAGE_GENERIC_VY 0x41 +#define HID_USAGE_GENERIC_VZ 0x42 +#define HID_USAGE_GENERIC_VBRX 0x43 +#define HID_USAGE_GENERIC_VBRY 0x44 +#define HID_USAGE_GENERIC_VBRZ 0x45 +#define HID_USAGE_GENERIC_VNO 0x46 +#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80 +#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81 +#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82 +#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83 +#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84 +#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85 +#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86 +#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87 +#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88 +#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89 +#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A +#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B +#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C +#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D +/** @} */ + +/** Simulation Controls Page (0x02) + * @{ + */ +#define HID_USAGE_SIMULATION_RUDDER 0xBA +#define HID_USAGE_SIMULATION_THROTTLE 0xBB +/** @} */ + +/* Virtual Reality Controls Page (0x03) */ +/* ... */ + +/* Sport Controls Page (0x04) */ +/* ... */ + +/* Game Controls Page (0x05) */ +/* ... */ + +/* Generic Device Controls Page (0x06) */ +/* ... */ + +/** Keyboard/Keypad Page (0x07) + * @{ + */ +/** Error "keys" */ +#define HID_USAGE_KEYBOARD_NOEVENT 0x00 +#define HID_USAGE_KEYBOARD_ROLLOVER 0x01 +#define HID_USAGE_KEYBOARD_POSTFAIL 0x02 +#define HID_USAGE_KEYBOARD_UNDEFINED 0x03 + +/** Letters */ +#define HID_USAGE_KEYBOARD_aA 0x04 +#define HID_USAGE_KEYBOARD_zZ 0x1D + +/** Numbers */ +#define HID_USAGE_KEYBOARD_ONE 0x1E +#define HID_USAGE_KEYBOARD_ZERO 0x27 + +#define HID_USAGE_KEYBOARD_RETURN 0x28 +#define HID_USAGE_KEYBOARD_ESCAPE 0x29 +#define HID_USAGE_KEYBOARD_DELETE 0x2A + +/** Funtion keys */ +#define HID_USAGE_KEYBOARD_F1 0x3A +#define HID_USAGE_KEYBOARD_F12 0x45 + +#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46 + +/** Modifier Keys */ +#define HID_USAGE_KEYBOARD_LCTRL 0xE0 +#define HID_USAGE_KEYBOARD_LSHFT 0xE1 +#define HID_USAGE_KEYBOARD_LALT 0xE2 +#define HID_USAGE_KEYBOARD_LGUI 0xE3 +#define HID_USAGE_KEYBOARD_RCTRL 0xE4 +#define HID_USAGE_KEYBOARD_RSHFT 0xE5 +#define HID_USAGE_KEYBOARD_RALT 0xE6 +#define HID_USAGE_KEYBOARD_RGUI 0xE7 +#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47 +#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53 +#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39 +/** @} */ + +/* ... */ + +/** LED Page (0x08) + * @{ + */ +#define HID_USAGE_LED_NUM_LOCK 0x01 +#define HID_USAGE_LED_CAPS_LOCK 0x02 +#define HID_USAGE_LED_SCROLL_LOCK 0x03 +#define HID_USAGE_LED_COMPOSE 0x04 +#define HID_USAGE_LED_KANA 0x05 +#define HID_USAGE_LED_POWER 0x06 +#define HID_USAGE_LED_SHIFT 0x07 +#define HID_USAGE_LED_DO_NOT_DISTURB 0x08 +#define HID_USAGE_LED_MUTE 0x09 +#define HID_USAGE_LED_TONE_ENABLE 0x0A +#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B +#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C +#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D +#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E +#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F +#define HID_USAGE_LED_REPEAT 0x10 +#define HID_USAGE_LED_STEREO 0x11 +#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12 +#define HID_USAGE_LED_SPINNING 0x13 +#define HID_USAGE_LED_CAV 0x14 +#define HID_USAGE_LED_CLV 0x15 +#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16 +#define HID_USAGE_LED_OFF_HOOK 0x17 +#define HID_USAGE_LED_RING 0x18 +#define HID_USAGE_LED_MESSAGE_WAITING 0x19 +#define HID_USAGE_LED_DATA_MODE 0x1A +#define HID_USAGE_LED_BATTERY_OPERATION 0x1B +#define HID_USAGE_LED_BATTERY_OK 0x1C +#define HID_USAGE_LED_BATTERY_LOW 0x1D +#define HID_USAGE_LED_SPEAKER 0x1E +#define HID_USAGE_LED_HEAD_SET 0x1F +#define HID_USAGE_LED_HOLD 0x20 +#define HID_USAGE_LED_MICROPHONE 0x21 +#define HID_USAGE_LED_COVERAGE 0x22 +#define HID_USAGE_LED_NIGHT_MODE 0x23 +#define HID_USAGE_LED_SEND_CALLS 0x24 +#define HID_USAGE_LED_CALL_PICKUP 0x25 +#define HID_USAGE_LED_CONFERENCE 0x26 +#define HID_USAGE_LED_STAND_BY 0x27 +#define HID_USAGE_LED_CAMERA_ON 0x28 +#define HID_USAGE_LED_CAMERA_OFF 0x29 +#define HID_USAGE_LED_ON_LINE 0x2A +#define HID_USAGE_LED_OFF_LINE 0x2B +#define HID_USAGE_LED_BUSY 0x2C +#define HID_USAGE_LED_READY 0x2D +#define HID_USAGE_LED_PAPER_OUT 0x2E +#define HID_USAGE_LED_PAPER_JAM 0x2F +#define HID_USAGE_LED_REMOTE 0x30 +#define HID_USAGE_LED_FORWARD 0x31 +#define HID_USAGE_LED_REVERSE 0x32 +#define HID_USAGE_LED_STOP 0x33 +#define HID_USAGE_LED_REWIND 0x34 +#define HID_USAGE_LED_FAST_FORWARD 0x35 +#define HID_USAGE_LED_PLAY 0x36 +#define HID_USAGE_LED_PAUSE 0x37 +#define HID_USAGE_LED_RECORD 0x38 +#define HID_USAGE_LED_ERROR 0x39 +#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A +#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B +#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C +#define HID_USAGE_LED_INDICATOR_ON 0x3D +#define HID_USAGE_LED_INDICATOR_FLASH 0x3E +#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F +#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40 +#define HID_USAGE_LED_INDICATOR_OFF 0x41 +#define HID_USAGE_LED_FLASH_ON_TIME 0x42 +#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43 +#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44 +#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45 +#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46 +#define HID_USAGE_LED_INDICATOR_COLOR 0x47 +#define HID_USAGE_LED_RED 0x48 +#define HID_USAGE_LED_GREEN 0x49 +#define HID_USAGE_LED_AMBER 0x4A +#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B +/** @} */ + +/* Button Page (0x09) + */ +/* There is no need to label these usages. */ + +/* Ordinal Page (0x0A) + */ +/* There is no need to label these usages. */ + +/** Telephony Device Page (0x0B) + * @{ + */ +#define HID_USAGE_TELEPHONY_PHONE 0x01 +#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02 +#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03 +#define HID_USAGE_TELEPHONY_HANDSET 0x04 +#define HID_USAGE_TELEPHONY_HEADSET 0x05 +#define HID_USAGE_TELEPHONY_KEYPAD 0x06 +#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07 +/** @} */ +/* ... */ + +/** Consumer Page (0x0C) + * @{ + */ +#define HID_USAGE_CONSUMER_CONTROL 0x01 +#define HID_USAGE_CONSUMER_FAST_FORWARD 0xB3 +#define HID_USAGE_CONSUMER_REWIND 0xB4 +#define HID_USAGE_CONSUMER_PLAY_PAUSE 0xCD +#define HID_USAGE_CONSUMER_VOLUME_INCREMENT 0xE9 +#define HID_USAGE_CONSUMER_VOLUME_DECREMENT 0xEA +/** @} */ +/* ... */ + +/* and others ... */ + + +/** HID Report Item Macros + * @{ + */ +/** Main Items */ +#define HID_Input(x) 0x81,x +#define HID_Output(x) 0x91,x +#define HID_Feature(x) 0xB1,x +#define HID_Collection(x) 0xA1,x +#define HID_EndCollection 0xC0 + +/** Data (Input, Output, Feature) */ +#define HID_Data 0<<0 +#define HID_Constant 1<<0 +#define HID_Array 0<<1 +#define HID_Variable 1<<1 +#define HID_Absolute 0<<2 +#define HID_Relative 1<<2 +#define HID_NoWrap 0<<3 +#define HID_Wrap 1<<3 +#define HID_Linear 0<<4 +#define HID_NonLinear 1<<4 +#define HID_PreferredState 0<<5 +#define HID_NoPreferred 1<<5 +#define HID_NoNullPosition 0<<6 +#define HID_NullState 1<<6 +#define HID_NonVolatile 0<<7 +#define HID_Volatile 1<<7 + +/** Collection Data */ +#define HID_Physical 0x00 +#define HID_Application 0x01 +#define HID_Logical 0x02 +#define HID_Report 0x03 +#define HID_NamedArray 0x04 +#define HID_UsageSwitch 0x05 +#define HID_UsageModifier 0x06 + +/** Global Items */ +#define HID_UsagePage(x) 0x05,x +#define HID_UsagePageVendor(x) 0x06,x,0xFF +#define HID_LogicalMin(x) 0x15,x +#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF) +#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_LogicalMax(x) 0x25,x +#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF) +#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_PhysicalMin(x) 0x35,x +#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF) +#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_PhysicalMax(x) 0x45,x +#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF) +#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_UnitExponent(x) 0x55,x +#define HID_Unit(x) 0x65,x +#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF) +#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_ReportSize(x) 0x75,x +#define HID_ReportID(x) 0x85,x +#define HID_ReportCount(x) 0x95,x +#define HID_ReportCount16(x) 0x96,(x&0xFF),((x>>8)&0xFF) +#define HID_Push 0xA0 +#define HID_Pop 0xB0 + +/** Local Items */ +#define HID_Usage(x) 0x09,x +#define HID_UsageMin(x) 0x19,x +#define HID_UsageMax(x) 0x29,x +/** @} */ + +/** @} */ + +#endif /* __HID_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hiduser.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hiduser.h new file mode 100644 index 0000000000000..9b9a6f0e09efc --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hiduser.h @@ -0,0 +1,427 @@ +/*********************************************************************** +* $Id:: mw_usbd_hiduser.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* HID Custom User Module Definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ + +#ifndef __HIDUSER_H__ +#define __HIDUSER_H__ + +#include "usbd.h" +#include "usbd_hid.h" +#include "usbd_core.h" + +/** \file + * \brief Human Interface Device (HID) API structures and function prototypes. + * + * Definition of functions exported by ROM based HID function driver. + * + */ + +/** \ingroup Group_USBD + * @defgroup USBD_HID HID Class Function Driver + * \section Sec_HIDModDescription Module Description + * HID Class Function Driver module. This module contains an internal implementation of the USB HID Class. + * User applications can use this class driver instead of implementing the HID class manually + * via the low-level HW and core APIs. + * + * This module is designed to simplify the user code by exposing only the required interface needed to interface with + * Devices using the USB HID Class. + */ + +/** \brief HID report descriptor data structure. + * \ingroup USBD_HID + * + * \details This structure is used as part of HID function driver initialization + * parameter structure \ref USBD_HID_INIT_PARAM. This structure contains + * details of a report type supported by the application. An application + * can support multiple report types as a single HID device. The application + * should define this report type data structure per report it supports and + * the array of report types to USBD_HID_API::init() through \ref USBD_HID_INIT_PARAM + * structure. + * + * \note All descriptor pointers assigned in this structure should be on 4 byte + * aligned address boundary. + * + */ +typedef struct _HID_REPORT_T { + uint16_t len; /**< Size of the report descriptor in bytes. */ + uint8_t idle_time; /**< This value is used by stack to respond to Set_Idle & + GET_Idle requests for the specified report ID. The value + of this field specified the rate at which duplicate reports + are generated for the specified Report ID. For example, a + device with two input reports could specify an idle rate of + 20 milliseconds for report ID 1 and 500 milliseconds for + report ID 2. + */ + uint8_t __pad; /**< Padding space. */ + uint8_t* desc; /**< Report descriptor. */ +} USB_HID_REPORT_T; + +/** \brief USB descriptors data structure. + * \ingroup USBD_HID + * + * \details This module exposes functions which interact directly with USB device stack's core layer. + * The application layer uses this component when it has to implement custom class function driver or + * standard class function driver which is not part of the current USB device stack. + * The functions exposed by this interface are to register class specific EP0 handlers and corresponding + * utility functions to manipulate EP0 state machine of the stack. This interface also exposes + * function to register custom endpoint interrupt handler. + * + */ +typedef struct USBD_HID_INIT_PARAM +{ + /* memory allocation params */ + uint32_t mem_base; /**< Base memory location from where the stack can allocate + data and buffers. \note The memory address set in this field + should be accessible by USB DMA controller. Also this value + should be aligned on 4 byte boundary. + */ + uint32_t mem_size; /**< The size of memory buffer which stack can use. + \note The \em mem_size should be greater than the size + returned by USBD_HID_API::GetMemSize() routine.*/ + /* HID paramas */ + uint8_t max_reports; /**< Number of HID reports supported by this instance + of HID class driver. + */ + uint8_t pad[3]; + uint8_t* intf_desc; /**< Pointer to the HID interface descriptor within the + descriptor array (\em high_speed_desc) passed to Init() + through \ref USB_CORE_DESCS_T structure. + */ + USB_HID_REPORT_T* report_data; /**< Pointer to an array of HID report descriptor + data structure (\ref USB_HID_REPORT_T). The number + of elements in the array should be same a \em max_reports + value. The stack uses this array to respond to + requests received for various HID report descriptor + information. \note This array should be of global scope. + */ + + /* user defined functions */ + /* required functions */ + /** + * HID get report callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a HID_REQUEST_GET_REPORT request. The setup packet data (\em pSetup) + * is passed to the callback so that application can extract the report ID, report + * type and other information need to generate the report. \note HID reports are sent + * via interrupt IN endpoint also. This function is called only when report request + * is received on control endpoint. Application should implement \em HID_EpIn_Hdlr to + * send reports to host via interrupt IN endpoint. + * + * + * \param[in] hHid Handle to HID function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data. + * Pointer-to-pointer is used to implement zero-copy buffers. + * See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in] length Amount of data copied to destination buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); + + /** + * HID set report callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a HID_REQUEST_SET_REPORT request. The setup packet data (\em pSetup) + * is passed to the callback so that application can extract the report ID, report + * type and other information need to modify the report. An application might choose + * to ignore input Set_Report requests as meaningless. Alternatively these reports + * could be used to reset the origin of a control (that is, current position should + * report zero). + * + * \param[in] hHid Handle to HID function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data. + * Pointer-to-pointer is used to implement zero-copy buffers. + * See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in] length Amount of data copied to destination buffer. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length); + + /* optional functions */ + + /** + * Optional callback function to handle HID_GetPhysDesc request. + * + * The application software could provide this callback HID_GetPhysDesc handler to + * handle get physical descriptor requests sent by the host. When host requests + * Physical Descriptor set 0, application should return a special descriptor + * identifying the number of descriptor sets and their sizes. A Get_Descriptor + * request with the Physical Index equal to 1 should return the first Physical + * Descriptor set. A device could possibly have alternate uses for its items. + * These can be enumerated by issuing subsequent Get_Descriptor requests while + * incrementing the Descriptor Index. A device should return the last descriptor + * set to requests with an index greater than the last number defined in the HID + * descriptor. + * \note Applications which don't have physical descriptor should set this data member + * to zero before calling the USBD_HID_API::Init(). + * \n + * + * \param[in] hHid Handle to HID function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in] pBuf Pointer to a pointer of data buffer containing physical descriptor + * data. If the physical descriptor is in USB accessible memory area + * application could just update the pointer or else it should copy + * the descriptor to the address pointed by this pointer. + * \param[in] length Amount of data copied to destination buffer or descriptor length. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length); + + /** + * Optional callback function to handle HID_REQUEST_SET_IDLE request. + * + * The application software could provide this callback to handle HID_REQUEST_SET_IDLE + * requests sent by the host. This callback is provided to applications to adjust + * timers associated with various reports, which are sent to host over interrupt + * endpoint. The setup packet data (\em pSetup) is passed to the callback so that + * application can extract the report ID, report type and other information need + * to modify the report's idle time. + * \note Applications which don't send reports on Interrupt endpoint or don't + * have idle time between reports should set this data member to zero before + * calling the USBD_HID_API::Init(). + * \n + * + * \param[in] hHid Handle to HID function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in] idleTime Idle time to be set for the specified report. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime); + + /** + * Optional callback function to handle HID_REQUEST_SET_PROTOCOL request. + * + * The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL + * requests sent by the host. This callback is provided to applications to adjust + * modes of their code between boot mode and report mode. + * \note Applications which don't support protocol modes should set this data member + * to zero before calling the USBD_HID_API::Init(). + * \n + * + * \param[in] hHid Handle to HID function driver. + * \param[in] pSetup Pointer to setup packet received from host. + * \param[in] protocol Protocol mode. + * 0 = Boot Protocol + * 1 = Report Protocol + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol); + + /** + * Optional Interrupt IN endpoint event handler. + * + * The application software could provide Interrupt IN endpoint event handler. + * Application which send reports to host on interrupt endpoint should provide + * an endpoint event handler through this data member. This data member is + * ignored if the interface descriptor \em intf_desc doesn't have any IN interrupt + * endpoint descriptor associated. + * \n + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Handle to HID function driver. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should return \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_EpIn_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + /** + * Optional Interrupt OUT endpoint event handler. + * + * The application software could provide Interrupt OUT endpoint event handler. + * Application which receives reports from host on interrupt endpoint should provide + * an endpoint event handler through this data member. This data member is + * ignored if the interface descriptor \em intf_desc doesn't have any OUT interrupt + * endpoint descriptor associated. + * \n + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Handle to HID function driver. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should return \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_EpOut_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + + /* user override-able function */ + /** + * Optional user override-able function to replace the default HID_GetReportDesc handler. + * + * The application software could override the default HID_GetReportDesc handler with their + * own by providing the handler function address as this data member of the parameter + * structure. Application which like the default handler should set this data member + * to zero before calling the USBD_HID_API::Init() and also provide report data array + * \em report_data field. + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length); + /** + * Optional user override-able function to replace the default HID class handler. + * + * The application software could override the default EP0 class handler with their + * own by providing the handler function address as this data member of the parameter + * structure. Application which like the default handler should set this data member + * to zero before calling the USBD_HID_API::Init(). + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*HID_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + +} USBD_HID_INIT_PARAM_T; + +/** \brief HID class API functions structure. + * \ingroup USBD_HID + * + * This structure contains pointers to all the function exposed by HID function driver module. + * + */ +typedef struct USBD_HID_API +{ + /** \fn uint32_t GetMemSize(USBD_HID_INIT_PARAM_T* param) + * Function to determine the memory required by the HID function driver module. + * + * This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used + * by HID function driver module. The application should allocate the memory which is accessible by USB + * controller/DMA controller. + * \note Some memory areas are not accessible by all bus masters. + * + * \param[in] param Structure containing HID function driver module initialization parameters. + * \return Returns the required memory size in bytes. + */ + uint32_t (*GetMemSize)(USBD_HID_INIT_PARAM_T* param); + + /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param) + * Function to initialize HID function driver module. + * + * This function is called by application layer to initialize HID function driver + * module. On successful initialization the function returns a handle to HID + * function driver module in passed param structure. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in, out] param Structure containing HID function driver module + * initialization parameters. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte + * aligned or smaller than required. + * \retval ERR_API_INVALID_PARAM2 Either HID_GetReport() or HID_SetReport() + * callback are not defined. + * \retval ERR_USBD_BAD_DESC HID_HID_DESCRIPTOR_TYPE is not defined + * immediately after interface descriptor. + * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. + * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. + */ + ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param); + +} USBD_HID_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes + *-----------------------------------------------------------------------------*/ +/** @cond ADVANCED_API */ + +typedef struct _HID_CTRL_T { + /* pointer to controller */ + USB_CORE_CTRL_T* pUsbCtrl; + /* descriptor pointers */ + uint8_t* hid_desc; + USB_HID_REPORT_T* report_data; + + uint8_t protocol; + uint8_t if_num; /* interface number */ + uint8_t epin_adr; /* IN interrupt endpoint */ + uint8_t epout_adr; /* OUT interrupt endpoint */ + + /* user defined functions */ + ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); + ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length); + ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length); + ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime); + ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol); + + /* virtual overridable functions */ + ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length); + +}USB_HID_CTRL_T; + +/** @cond DIRECT_API */ +extern uint32_t mwHID_GetMemSize(USBD_HID_INIT_PARAM_T* param); +extern ErrorCode_t mwHID_init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param); +/** @endcond */ + +/** @endcond */ + +#endif /* __HIDUSER_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hw.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hw.h new file mode 100644 index 0000000000000..8dc98ff381309 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_hw.h @@ -0,0 +1,463 @@ +/*********************************************************************** +* $Id:: mw_usbd_hw.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* USB Hardware Function prototypes. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __USBHW_H__ +#define __USBHW_H__ + +#include "error.h" +#include "usbd.h" +#include "usbd_core.h" + +/** \file + * \brief USB Hardware Function prototypes. + * + * Definition of functions exported by ROM based Device Controller Driver (DCD). + * + */ + +/** \ingroup Group_USBD + * @defgroup USBD_HW USB Device Controller Driver + * \section Sec_HWModDescription Module Description + * The Device Controller Driver Layer implements the routines to deal directly with the hardware. + */ + +/** \ingroup USBD_HW +* USB Endpoint/class handler Callback Events. +* +*/ +enum USBD_EVENT_T { + USB_EVT_SETUP =1, /**< 1 Setup Packet received */ + USB_EVT_OUT, /**< 2 OUT Packet received */ + USB_EVT_IN, /**< 3 IN Packet sent */ + USB_EVT_OUT_NAK, /**< 4 OUT Packet - Not Acknowledged */ + USB_EVT_IN_NAK, /**< 5 IN Packet - Not Acknowledged */ + USB_EVT_OUT_STALL, /**< 6 OUT Packet - Stalled */ + USB_EVT_IN_STALL, /**< 7 IN Packet - Stalled */ + USB_EVT_OUT_DMA_EOT, /**< 8 DMA OUT EP - End of Transfer */ + USB_EVT_IN_DMA_EOT, /**< 9 DMA IN EP - End of Transfer */ + USB_EVT_OUT_DMA_NDR, /**< 10 DMA OUT EP - New Descriptor Request */ + USB_EVT_IN_DMA_NDR, /**< 11 DMA IN EP - New Descriptor Request */ + USB_EVT_OUT_DMA_ERR, /**< 12 DMA OUT EP - Error */ + USB_EVT_IN_DMA_ERR, /**< 13 DMA IN EP - Error */ + USB_EVT_RESET, /**< 14 Reset event recieved */ + USB_EVT_SOF, /**< 15 Start of Frame event */ + USB_EVT_DEV_STATE, /**< 16 Device status events */ + USB_EVT_DEV_ERROR /**< 17 Device error events */ +}; + +/** + * \brief Hardware API functions structure. + * \ingroup USBD_HW + * + * This module exposes functions which interact directly with USB device controller hardware. + * + */ +typedef struct USBD_HW_API +{ + /** \fn uint32_t GetMemSize(USBD_API_INIT_PARAM_T* param) + * Function to determine the memory required by the USB device stack's DCD and core layers. + * + * This function is called by application layer before calling pUsbApi->hw->Init(), to allocate memory used + * by DCD and core layers. The application should allocate the memory which is accessible by USB + * controller/DMA controller. + * \note Some memory areas are not accessible by all bus masters. + * + * \param[in] param Structure containing USB device stack initialization parameters. + * \return Returns the required memory size in bytes. + */ + uint32_t (*GetMemSize)(USBD_API_INIT_PARAM_T* param); + + /** \fn ErrorCode_t Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param) + * Function to initialize USB device stack's DCD and core layers. + * + * This function is called by application layer to initialize USB hardware and core layers. + * On successful initialization the function returns a handle to USB device stack which should + * be passed to the rest of the functions. + * + * \param[in,out] phUsb Pointer to the USB device stack handle of type USBD_HANDLE_T. + * \param[in] pDesc Structure containing pointers to various descriptor arrays needed by the stack. + * These descriptors are reported to USB host as part of enumerations process. + * \param[in] param Structure containing USB device stack initialization parameters. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK(0) On success + * \retval ERR_USBD_BAD_MEM_BUF(0x0004000b) When insufficient memory buffer is passed or memory + * is not aligned on 2048 boundary. + */ + ErrorCode_t (*Init)(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param); + + /** \fn void Connect(USBD_HANDLE_T hUsb, uint32_t con) + * Function to make USB device visible/invisible on the USB bus. + * + * This function is called after the USB initialization. This function uses the soft connect + * feature to make the device visible on the USB bus. This function is called only after the + * application is ready to handle the USB data. The enumeration process is started by the + * host after the device detection. The driver handles the enumeration process according to + * the USB descriptors passed in the USB initialization function. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] con States whether to connect (1) or to disconnect (0). + * \return Nothing. + */ + void (*Connect)(USBD_HANDLE_T hUsb, uint32_t con); + + /** \fn void ISR(USBD_HANDLE_T hUsb) + * Function to USB device controller interrupt events. + * + * When the user application is active the interrupt handlers are mapped in the user flash + * space. The user application must provide an interrupt handler for the USB interrupt and + * call this function in the interrupt handler routine. The driver interrupt handler takes + * appropriate action according to the data received on the USB bus. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*ISR)(USBD_HANDLE_T hUsb); + + /** \fn void Reset(USBD_HANDLE_T hUsb) + * Function to Reset USB device stack and hardware controller. + * + * Reset USB device stack and hardware controller. Disables all endpoints except EP0. + * Clears all pending interrupts and resets endpoint transfer queues. + * This function is called internally by pUsbApi->hw->init() and from reset event. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*Reset)(USBD_HANDLE_T hUsb); + + /** \fn void ForceFullSpeed(USBD_HANDLE_T hUsb, uint32_t cfg) + * Function to force high speed USB device to operate in full speed mode. + * + * This function is useful for testing the behavior of current device when connected + * to a full speed only hosts. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] cfg When 1 - set force full-speed or + * 0 - clear force full-speed. + * \return Nothing. + */ + void (*ForceFullSpeed )(USBD_HANDLE_T hUsb, uint32_t cfg); + + /** \fn void WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg) + * Function to configure USB device controller to wake-up host on remote events. + * + * This function is called by application layer to configure the USB device controller + * to wakeup on remote events. It is recommended to call this function from users's + * USB_WakeUpCfg() callback routine registered with stack. + * \note User's USB_WakeUpCfg() is registered with stack by setting the USB_WakeUpCfg member + * of USBD_API_INIT_PARAM_T structure before calling pUsbApi->hw->Init() routine. + * Certain USB device controllers needed to keep some clocks always on to generate + * resume signaling through pUsbApi->hw->WakeUp(). This hook is provided to support + * such controllers. In most controllers cases this is an empty routine. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] cfg When 1 - Configure controller to wake on remote events or + * 0 - Configure controller not to wake on remote events. + * \return Nothing. + */ + void (*WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg); + + /** \fn void SetAddress(USBD_HANDLE_T hUsb, uint32_t adr) + * Function to set USB address assigned by host in device controller hardware. + * + * This function is called automatically when USB_REQUEST_SET_ADDRESS request is received + * by the stack from USB host. + * This interface is provided to users to invoke this function in other scenarios which are not + * handle by current stack. In most user applications this function is not called directly. + * Also this function can be used by users who are selectively modifying the USB device stack's + * standard handlers through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] adr USB bus Address to which the device controller should respond. Usually + * assigned by the USB host. + * \return Nothing. + */ + void (*SetAddress)(USBD_HANDLE_T hUsb, uint32_t adr); + + /** \fn void Configure(USBD_HANDLE_T hUsb, uint32_t cfg) + * Function to configure device controller hardware with selected configuration. + * + * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received + * by the stack from USB host. + * This interface is provided to users to invoke this function in other scenarios which are not + * handle by current stack. In most user applications this function is not called directly. + * Also this function can be used by users who are selectively modifying the USB device stack's + * standard handlers through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] cfg Configuration index. + * \return Nothing. + */ + void (*Configure)(USBD_HANDLE_T hUsb, uint32_t cfg); + + /** \fn void ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) + * Function to configure USB Endpoint according to descriptor. + * + * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received + * by the stack from USB host. All the endpoints associated with the selected configuration + * are configured. + * This interface is provided to users to invoke this function in other scenarios which are not + * handle by current stack. In most user applications this function is not called directly. + * Also this function can be used by users who are selectively modifying the USB device stack's + * standard handlers through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] pEPD Endpoint descriptor structure defined in USB 2.0 specification. + * \return Nothing. + */ + void (*ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD); + + /** \fn void DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir) + * Function to set direction for USB control endpoint EP0. + * + * This function is called automatically by the stack on need basis. + * This interface is provided to users to invoke this function in other scenarios which are not + * handle by current stack. In most user applications this function is not called directly. + * Also this function can be used by users who are selectively modifying the USB device stack's + * standard handlers through callback interface exposed by the stack. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] cfg When 1 - Set EP0 in IN transfer mode + * 0 - Set EP0 in OUT transfer mode + * \return Nothing. + */ + void (*DirCtrlEP)(USBD_HANDLE_T hUsb, uint32_t dir); + + /** \fn void EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum) + * Function to enable selected USB endpoint. + * + * This function enables interrupts on selected endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \return Nothing. + */ + void (*EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum); + + /** \fn void DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum) + * Function to disable selected USB endpoint. + * + * This function disables interrupts on selected endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \return Nothing. + */ + void (*DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum); + + /** \fn void ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum) + * Function to reset selected USB endpoint. + * + * This function flushes the endpoint buffers and resets data toggle logic. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \return Nothing. + */ + void (*ResetEP)(USBD_HANDLE_T hUsb, uint32_t EPNum); + + /** \fn void SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum) + * Function to STALL selected USB endpoint. + * + * Generates STALL signaling for requested endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \return Nothing. + */ + void (*SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum); + + /** \fn void ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum) + * Function to clear STALL state for the requested endpoint. + * + * This function clears STALL state for the requested endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \return Nothing. + */ + void (*ClrStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum); + + /** \fn ErrorCode_t SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode) + * Function to set high speed USB device controller in requested test mode. + * + * USB-IF requires the high speed device to be put in various test modes + * for electrical testing. This USB device stack calls this function whenever + * it receives USB_REQUEST_CLEAR_FEATURE request for USB_FEATURE_TEST_MODE. + * Users can put the device in test mode by directly calling this function. + * Returns ERR_USBD_INVALID_REQ when device controller is full-speed only. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] mode Test mode defined in USB 2.0 electrical testing specification. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK(0) - On success + * \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid test mode or + * Device controller is full-speed only. + */ + ErrorCode_t (*SetTestMode)(USBD_HANDLE_T hUsb, uint8_t mode); + + /** \fn uint32_t ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) + * Function to read data received on the requested endpoint. + * + * This function is called by USB stack and the application layer to read the data + * received on the requested endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \param[in,out] pData Pointer to the data buffer where data is to be copied. + * \return Returns the number of bytes copied to the buffer. + */ + uint32_t (*ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData); + + /** \fn uint32_t ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len) + * Function to queue read request on the specified endpoint. + * + * This function is called by USB stack and the application layer to queue a read request + * on the specified endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \param[in,out] pData Pointer to the data buffer where data is to be copied. This buffer + * address should be accessible by USB DMA master. + * \param[in] len Length of the buffer passed. + * \return Returns the length of the requested buffer. + */ + uint32_t (*ReadReqEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len); + + /** \fn uint32_t ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData) + * Function to read setup packet data received on the requested endpoint. + * + * This function is called by USB stack and the application layer to read setup packet data + * received on the requested endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP0_IN is represented by 0x80 number. + * \param[in,out] pData Pointer to the data buffer where data is to be copied. + * \return Returns the number of bytes copied to the buffer. + */ + uint32_t (*ReadSetupPkt)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData); + + /** \fn uint32_t WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt) + * Function to write data to be sent on the requested endpoint. + * + * This function is called by USB stack and the application layer to send data + * on the requested endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number as per USB specification. + * ie. An EP1_IN is represented by 0x81 number. + * \param[in] pData Pointer to the data buffer from where data is to be copied. + * \param[in] cnt Number of bytes to write. + * \return Returns the number of bytes written. + */ + uint32_t (*WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt); + + /** \fn void WakeUp(USBD_HANDLE_T hUsb) + * Function to generate resume signaling on bus for remote host wakeup. + * + * This function is called by application layer to remotely wakeup host controller + * when system is in suspend state. Application should indicate this remote wakeup + * capability by setting USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration + * Descriptor. Also this routine will generate resume signalling only if host + * enables USB_FEATURE_REMOTE_WAKEUP by sending SET_FEATURE request before suspending + * the bus. + * + * \param[in] hUsb Handle to the USB device stack. + * \return Nothing. + */ + void (*WakeUp)(USBD_HANDLE_T hUsb); + + /** \fn void EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable) + * Function to enable/disable selected USB event. + * + * This function enables interrupts on selected endpoint. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] EPNum Endpoint number corresponding to the event. + * ie. An EP1_IN is represented by 0x81 number. For device events + * set this param to 0x0. + * \param[in] event_type Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \param[in] enable 1 - enable event, 0 - disable event. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK(0) - On success + * \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid event type. + */ + ErrorCode_t (*EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable); + +} USBD_HW_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes used by stack internally + *-----------------------------------------------------------------------------*/ +/** @cond DIRECT_API */ + +/* Driver functions */ +uint32_t hwUSB_GetMemSize(USBD_API_INIT_PARAM_T* param); +ErrorCode_t hwUSB_Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param); +void hwUSB_Connect(USBD_HANDLE_T hUsb, uint32_t con); +void hwUSB_ISR(USBD_HANDLE_T hUsb); + +/* USB Hardware Functions */ +extern void hwUSB_Reset(USBD_HANDLE_T hUsb); +extern void hwUSB_ForceFullSpeed (USBD_HANDLE_T hUsb, uint32_t con); +extern void hwUSB_WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg); +extern void hwUSB_SetAddress(USBD_HANDLE_T hUsb, uint32_t adr); +extern void hwUSB_Configure(USBD_HANDLE_T hUsb, uint32_t cfg); +extern void hwUSB_ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD); +extern void hwUSB_DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir); +extern void hwUSB_EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum); +extern void hwUSB_DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum); +extern void hwUSB_ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum); +extern void hwUSB_SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum); +extern void hwUSB_ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum); +extern ErrorCode_t hwUSB_SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode); /* for FS only devices return ERR_USBD_INVALID_REQ */ +extern uint32_t hwUSB_ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData); +extern uint32_t hwUSB_ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len); +extern uint32_t hwUSB_ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t, uint32_t *); +extern uint32_t hwUSB_WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt); + +/* generate resume signaling on the bus */ +extern void hwUSB_WakeUp(USBD_HANDLE_T hUsb); +extern ErrorCode_t hwUSB_EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable); +/* TODO implement following routines +- function to program TD and queue them to ep Qh +*/ + +/** @endcond */ + + +#endif /* __USBHW_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_msc.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_msc.h new file mode 100644 index 0000000000000..9b0dcb6d17f89 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_msc.h @@ -0,0 +1,125 @@ +/*********************************************************************** +* $Id:: mw_usbd_msc.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* Mass Storage Class definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ + +#ifndef __MSC_H__ +#define __MSC_H__ + +#include "usbd.h" + +/** \file + * \brief Mass Storage class (MSC) descriptors. + * + * Definition of MSC class descriptors and their bit defines. + * + */ + +/* MSC Subclass Codes */ +#define MSC_SUBCLASS_RBC 0x01 +#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 +#define MSC_SUBCLASS_QIC157 0x03 +#define MSC_SUBCLASS_UFI 0x04 +#define MSC_SUBCLASS_SFF8070I 0x05 +#define MSC_SUBCLASS_SCSI 0x06 + +/* MSC Protocol Codes */ +#define MSC_PROTOCOL_CBI_INT 0x00 +#define MSC_PROTOCOL_CBI_NOINT 0x01 +#define MSC_PROTOCOL_BULK_ONLY 0x50 + + +/* MSC Request Codes */ +#define MSC_REQUEST_RESET 0xFF +#define MSC_REQUEST_GET_MAX_LUN 0xFE + + +/* MSC Bulk-only Stage */ +#define MSC_BS_CBW 0 /* Command Block Wrapper */ +#define MSC_BS_DATA_OUT 1 /* Data Out Phase */ +#define MSC_BS_DATA_IN 2 /* Data In Phase */ +#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */ +#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */ +#define MSC_BS_CSW 5 /* Command Status Wrapper */ +#define MSC_BS_ERROR 6 /* Error */ + + +/* Bulk-only Command Block Wrapper */ +PRE_PACK struct POST_PACK _MSC_CBW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} ; +typedef struct _MSC_CBW MSC_CBW; + +/* Bulk-only Command Status Wrapper */ +PRE_PACK struct POST_PACK _MSC_CSW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} ; +typedef struct _MSC_CSW MSC_CSW; + +#define MSC_CBW_Signature 0x43425355 +#define MSC_CSW_Signature 0x53425355 + + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + + +/* SCSI Commands */ +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_MEDIA_REMOVAL 0x1E +#define SCSI_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_READ_CAPACITY 0x25 +#define SCSI_READ10 0x28 +#define SCSI_WRITE10 0x2A +#define SCSI_VERIFY10 0x2F +#define SCSI_READ12 0xA8 +#define SCSI_WRITE12 0xAA +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE10 0x5A + + +#endif /* __MSC_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_mscuser.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_mscuser.h new file mode 100644 index 0000000000000..60ef45a95c9ad --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_mscuser.h @@ -0,0 +1,276 @@ +/*********************************************************************** +* $Id:: mw_usbd_mscuser.h 577 2012-11-20 01:42:04Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* Mass Storage Class Custom User Module definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __MSCUSER_H__ +#define __MSCUSER_H__ + +#include "error.h" +#include "usbd.h" +#include "usbd_msc.h" +#include "usbd_core.h" +#include "app_usbd_cfg.h" + +/** \file + * \brief Mass Storage Class (MSC) API structures and function prototypes. + * + * Definition of functions exported by ROM based MSC function driver. + * + */ + +/** \ingroup Group_USBD + * @defgroup USBD_MSC Mass Storage Class (MSC) Function Driver + * \section Sec_MSCModDescription Module Description + * MSC Class Function Driver module. This module contains an internal implementation of the USB MSC Class. + * User applications can use this class driver instead of implementing the MSC class manually + * via the low-level USBD_HW and USBD_Core APIs. + * + * This module is designed to simplify the user code by exposing only the required interface needed to interface with + * Devices using the USB MSC Class. + */ + +/** \brief Mass Storage class function driver initialization parameter data structure. + * \ingroup USBD_MSC + * + * \details This data structure is used to pass initialization parameters to the + * Mass Storage class function driver's init function. + * + */ +typedef struct USBD_MSC_INIT_PARAM +{ + /* memory allocation params */ + uint32_t mem_base; /**< Base memory location from where the stack can allocate + data and buffers. \note The memory address set in this field + should be accessible by USB DMA controller. Also this value + should be aligned on 4 byte boundary. + */ + uint32_t mem_size; /**< The size of memory buffer which stack can use. + \note The \em mem_size should be greater than the size + returned by USBD_MSC_API::GetMemSize() routine.*/ + /* mass storage params */ + uint8_t* InquiryStr; /**< Pointer to the 28 character string. This string is + sent in response to the SCSI Inquiry command. \note The data + pointed by the pointer should be of global scope. + */ + uint32_t BlockCount; /**< Number of blocks present in the mass storage device */ + uint32_t BlockSize; /**< Block size in number of bytes */ + uint32_t MemorySize; /**< Memory size in number of bytes */ + /** Pointer to the interface descriptor within the descriptor + * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T + * structure. The stack assumes both HS and FS use same BULK endpoints. + */ + + uint8_t* intf_desc; + /* user defined functions */ + + /** + * MSC Write callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a write command. + * + * \param[in] offset Destination start address. + * \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer + * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy + * for more details on zero-copy concept. + * \param[in] length Number of bytes to be written. + * \return Nothing. + * + */ + void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset); + /** + * MSC Read callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a read command. + * + * \param[in] offset Source start address. + * \param[in, out] dst Pointer to a pointer to the source of data. The MSC function drivers + * implemented in stack are written with zero-copy model. Meaning the stack doesn't make an + * extra copy of buffer before writing/reading data from USB hardware FIFO. Hence the + * parameter is pointer to a pointer containing address buffer (uint8_t** dst). + * So that the user application can update the buffer pointer instead of copying data to + * address pointed by the parameter. /note The updated buffer address should be accessible + * by USB DMA master. If user doesn't want to use zero-copy model, then the user should copy + * data to the address pointed by the passed buffer pointer parameter and shouldn't change + * the address value. See \ref USBD_ZeroCopy for more details on zero-copy concept. + * \param[in] length Number of bytes to be read. + * \return Nothing. + * + */ + void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset); + /** + * MSC Verify callback function. + * + * This function is provided by the application software. This function gets called + * when host sends a verify command. The callback function should compare the buffer + * with the destination memory at the requested offset and + * + * \param[in] offset Destination start address. + * \param[in] buf Buffer containing the data sent by the host. + * \param[in] length Number of bytes to verify. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK If data in the buffer matches the data at destination + * \retval ERR_FAILED At least one byte is different. + * + */ + ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t buf[], uint32_t length, uint32_t high_offset); + /** + * Optional callback function to optimize MSC_Write buffer transfer. + * + * This function is provided by the application software. This function gets called + * when host sends SCSI_WRITE10/SCSI_WRITE12 command. The callback function should + * update the \em buff_adr pointer so that the stack transfers the data directly + * to the target buffer. /note The updated buffer address should be accessible + * by USB DMA master. If user doesn't want to use zero-copy model, then the user + * should not update the buffer pointer. See \ref USBD_ZeroCopy for more details + * on zero-copy concept. + * + * \param[in] offset Destination start address. + * \param[in,out] buf Buffer containing the data sent by the host. + * \param[in] length Number of bytes to write. + * \return Nothing. + * + */ + void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset); + + /** + * Optional user override-able function to replace the default MSC class handler. + * + * The application software could override the default EP0 class handler with their + * own by providing the handler function address as this data member of the parameter + * structure. Application which like the default handler should set this data member + * to zero before calling the USBD_MSC_API::Init(). + * \n + * \note + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. + * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details. + * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success. + * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. + * \retval ERR_USBD_xxx For other error conditions. + * + */ + ErrorCode_t (*MSC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event); + + uint64_t MemorySize64; + +} USBD_MSC_INIT_PARAM_T; + +/** \brief MSC class API functions structure. + * \ingroup USBD_MSC + * + * This module exposes functions which interact directly with USB device controller hardware. + * + */ +typedef struct USBD_MSC_API +{ + /** \fn uint32_t GetMemSize(USBD_MSC_INIT_PARAM_T* param) + * Function to determine the memory required by the MSC function driver module. + * + * This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used + * by MSC function driver module. The application should allocate the memory which is accessible by USB + * controller/DMA controller. + * \note Some memory areas are not accessible by all bus masters. + * + * \param[in] param Structure containing MSC function driver module initialization parameters. + * \return Returns the required memory size in bytes. + */ + uint32_t (*GetMemSize)(USBD_MSC_INIT_PARAM_T* param); + + /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param) + * Function to initialize MSC function driver module. + * + * This function is called by application layer to initialize MSC function driver module. + * + * \param[in] hUsb Handle to the USB device stack. + * \param[in, out] param Structure containing MSC function driver module initialization parameters. + * \return Returns \ref ErrorCode_t type to indicate success or error condition. + * \retval LPC_OK On success + * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte + * aligned or smaller than required. + * \retval ERR_API_INVALID_PARAM2 Either MSC_Write() or MSC_Read() or + * MSC_Verify() callbacks are not defined. + * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. + * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. + */ + ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param); + +} USBD_MSC_API_T; + +/*----------------------------------------------------------------------------- + * Private functions & structures prototypes + *-----------------------------------------------------------------------------*/ +/** @cond ADVANCED_API */ + +typedef struct _MSC_CTRL_T +{ + /* If it's a USB HS, the max packet is 512, if it's USB FS, + the max packet is 64. Use 512 for both HS and FS. */ + /*ALIGNED(4)*/ uint8_t BulkBuf[USB_HS_MAX_BULK_PACKET]; /* Bulk In/Out Buffer */ + /*ALIGNED(4)*/MSC_CBW CBW; /* Command Block Wrapper */ + /*ALIGNED(4)*/MSC_CSW CSW; /* Command Status Wrapper */ + + USB_CORE_CTRL_T* pUsbCtrl; + + uint64_t Offset; /* R/W Offset */ + uint32_t Length; /* R/W Length */ + uint32_t BulkLen; /* Bulk In/Out Length */ + uint8_t* rx_buf; + + uint8_t BulkStage; /* Bulk Stage */ + uint8_t if_num; /* interface number */ + uint8_t epin_num; /* BULK IN endpoint number */ + uint8_t epout_num; /* BULK OUT endpoint number */ + uint32_t MemOK; /* Memory OK */ + + uint8_t* InquiryStr; + uint32_t BlockCount; + uint32_t BlockSize; + uint64_t MemorySize; + /* user defined functions */ + void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset); + void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset); + ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t src[], uint32_t length, uint32_t high_offset); + /* optional call back for MSC_Write optimization */ + void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset); + + +}USB_MSC_CTRL_T; + +/** @cond DIRECT_API */ +extern uint32_t mwMSC_GetMemSize(USBD_MSC_INIT_PARAM_T* param); +extern ErrorCode_t mwMSC_init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param); +/** @endcond */ + +/** @endcond */ + + +#endif /* __MSCUSER_H__ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_rom_api.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_rom_api.h new file mode 100644 index 0000000000000..275ce03226d69 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbd_rom/usbd_rom_api.h @@ -0,0 +1,98 @@ +/*********************************************************************** +* $Id:: mw_usbd_rom_api.h 331 2012-08-09 18:54:34Z usb10131 $ +* +* Project: USB device ROM Stack +* +* Description: +* ROM API Module definitions. +* +*********************************************************************** +* Copyright(C) 2011, NXP Semiconductor +* All rights reserved. +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +**********************************************************************/ +#ifndef __MW_USBD_ROM_API_H +#define __MW_USBD_ROM_API_H +/** \file + * \brief ROM API for USB device stack. + * + * Definition of functions exported by ROM based USB device stack. + * + */ + +#include "error.h" +#include "usbd.h" +#include "usbd_hw.h" +#include "usbd_core.h" +#include "usbd_mscuser.h" +#include "usbd_dfuuser.h" +#include "usbd_hiduser.h" +#include "usbd_cdcuser.h" + +/** \brief Main USBD API functions structure. + * \ingroup Group_USBD + * + * This structure contains pointer to various USB Device stack's sub-module + * function tables. This structure is used as main entry point to access + * various methods (grouped in sub-modules) exposed by ROM based USB device + * stack. + * + */ +typedef struct USBD_API +{ + const USBD_HW_API_T* hw; /**< Pointer to function table which exposes functions + which interact directly with USB device stack's core + layer.*/ + const USBD_CORE_API_T* core; /**< Pointer to function table which exposes functions + which interact directly with USB device controller + hardware.*/ + const USBD_MSC_API_T* msc; /**< Pointer to function table which exposes functions + provided by MSC function driver module. + */ + const USBD_DFU_API_T* dfu; /**< Pointer to function table which exposes functions + provided by DFU function driver module. + */ + const USBD_HID_API_T* hid; /**< Pointer to function table which exposes functions + provided by HID function driver module. + */ + const USBD_CDC_API_T* cdc; /**< Pointer to function table which exposes functions + provided by CDC-ACM function driver module. + */ + const uint32_t* reserved6; /**< Reserved for future function driver module. + */ + const uint32_t version; /**< Version identifier of USB ROM stack. The version is + defined as 0x0CHDMhCC where each nibble represents version + number of the corresponding component. + CC - 7:0 - 8bit core version number + h - 11:8 - 4bit hardware interface version number + M - 15:12 - 4bit MSC class module version number + D - 19:16 - 4bit DFU class module version number + H - 23:20 - 4bit HID class module version number + C - 27:24 - 4bit CDC class module version number + H - 31:28 - 4bit reserved + */ + +} USBD_API_T; + +/* Applications using USBD ROM API should define this instance. The pointer should be assigned a value computed based on chip definitions. */ +extern const USBD_API_T* g_pUsbApi; +#define USBD_API g_pUsbApi + +#endif /*__MW_USBD_ROM_API_H*/ + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/usbhs_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/usbhs_18xx_43xx.h new file mode 100644 index 0000000000000..11f62d08874df --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/usbhs_18xx_43xx.h @@ -0,0 +1,129 @@ +/* + * @brief LPC18xx/43xx High-Speed USB driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __USBHS_18XX_43XX_H_ +#define __USBHS_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup USBHS_18XX_43XX CHIP: LPC18xx/43xx USBHS Device, Host, & OTG driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief USB High-Speed register block structure + */ +typedef struct { /*!< USB Structure */ + __I uint32_t RESERVED0[64]; + __I uint32_t CAPLENGTH; /*!< Capability register length */ + __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */ + __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */ + __I uint32_t RESERVED1[5]; + __I uint32_t DCIVERSION; /*!< Device interface version number */ + __I uint32_t RESERVED2[7]; + union { + __IO uint32_t USBCMD_H; /*!< USB command (host mode) */ + __IO uint32_t USBCMD_D; /*!< USB command (device mode) */ + }; + + union { + __IO uint32_t USBSTS_H; /*!< USB status (host mode) */ + __IO uint32_t USBSTS_D; /*!< USB status (device mode) */ + }; + + union { + __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */ + __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */ + }; + + union { + __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */ + __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */ + }; + + __I uint32_t RESERVED3; + union { + __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */ + __IO uint32_t DEVICEADDR; /*!< USB device address */ + }; + + union { + __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */ + __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */ + }; + + __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */ + __IO uint32_t BURSTSIZE; /*!< Programmable burst size */ + __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */ + __I uint32_t RESERVED4[2]; + __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */ + __IO uint32_t BINTERVAL; /*!< Length of virtual frame */ + __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */ + __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */ + __I uint32_t RESERVED5; + union { + __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */ + __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */ + }; + + __I uint32_t RESERVED6[7]; + __IO uint32_t OTGSC; /*!< OTG status and control */ + union { + __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */ + __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */ + }; + + __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */ + __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */ + __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */ + __I uint32_t ENDPTSTAT; /*!< Endpoint status */ + __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */ + __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */ +} LPC_USBHS_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBHS_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/wwdt_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/wwdt_18xx_43xx.h new file mode 100644 index 0000000000000..c2449053154b2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/inc/wwdt_18xx_43xx.h @@ -0,0 +1,233 @@ +/* + * @brief LPC18xx/43xx WWDT driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __WWDT_18XX_43XX_H_ +#define __WWDT_18XX_43XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx Windowed Watchdog driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define WATCHDOG_WINDOW_SUPPORT + +/** WDT oscillator frequency value */ +#define WDT_OSC (CGU_IRC_FREQ) + +/** + * @brief Windowed Watchdog register block structure + */ +typedef struct { /*!< WWDT Structure */ + __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */ + __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ + __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ + __I uint32_t RESERVED0; +#ifdef WATCHDOG_WINDOW_SUPPORT + __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ + __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */ +#endif +} LPC_WWDT_T; + +/** + * @brief Watchdog Mode register definitions + */ +/** Watchdog Mode Bitmask */ +#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F) +/** WWDT interrupt enable bit */ +#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0)) +/** WWDT interrupt enable bit */ +#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1)) +/** WWDT time out flag bit */ +#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2)) +/** WDT Time Out flag bit */ +#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3)) +/** WWDT Protect flag bit */ +#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4)) + +/** + * @brief Initialize the Watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +void Chip_WWDT_Init(LPC_WWDT_T *pWWDT); + +/** + * @brief Shutdown the Watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT); + +/** + * @brief Set WDT timeout constant value used for feed + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return none + */ +STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->TC = timeout; +} + +/** + * @brief Feed watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + * @note If this function isn't called, a watchdog timer warning will occur. + * After the warning, a timeout will occur if a feed has happened. + */ +STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT) +{ + pWWDT->FEED = 0xAA; + pWWDT->FEED = 0x55; +} + +#if defined(WATCHDOG_WINDOW_SUPPORT) +/** + * @brief Set WWDT warning interrupt + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT warning in ticks, between 0 and 1023 + * @return None + * @note This is the number of ticks after the watchdog interrupt that the + * warning interrupt will be generated. + */ +STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->WARNINT = timeout; +} + +/** + * @brief Set WWDT window time + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return None + * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut() + * function and this function, with this function defining the last tick before the + * watchdog window interrupt occurs. + */ +STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->WINDOW = timeout; +} + +#endif + +/** + * @brief Enable watchdog timer options + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options + * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot + * be unset. + */ +STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options) +{ + pWWDT->MOD |= options; +} + +/** + * @brief Disable/clear watchdog timer options + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDTOF). + */ +STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options) +{ + pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK; +} + +/** + * @brief Enable WWDT activity + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT) +{ + Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN); + Chip_WWDT_Feed(pWWDT); +} + +/** + * @brief Read WWDT status flag + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return Watchdog status, an Or'ed value of WWDT_WDMOD_* + */ +STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT) +{ + return pWWDT->MOD; +} + +/** + * @brief Clear WWDT interrupt status flags + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param status : Or'ed value of status flag(s) that you want to clear, should be: + * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag + * - WWDT_WDMOD_WDINT: Clear watchdog warning flag + * @return None + */ +void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status); + +/** + * @brief Get the current value of WDT + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return current value of WDT + */ +STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT) +{ + return pWWDT->TV; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_18XX_43XX_H_ */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c new file mode 100644 index 0000000000000..589a2cdc72c36 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c @@ -0,0 +1,263 @@ +/* + * @brief LPC18xx/43xx A/D conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Get the number of clock for a full conversion */ +STATIC INLINE uint8_t getFullConvClk(void) +{ + return 11; +} + +/* Returns clock index for the peripheral block */ +STATIC CHIP_CCU_CLK_T Chip_ADC_GetClockIndex(LPC_ADC_T *pADC) +{ + CHIP_CCU_CLK_T clkADC; + + if (pADC == LPC_ADC1) { + clkADC = CLK_APB3_ADC1; + } + else { + clkADC = CLK_APB3_ADC0; + } + + return clkADC; +} + +/* Get divider value */ +STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks) +{ + uint32_t adcBlockFreq; + uint32_t fullAdcRate; + uint8_t div; + + /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for + A/D converter, which should be less than or equal to 4.5MHz. + A fully conversion requires (bits_accuracy+1) of these clocks. + ADC Clock = PCLK_ADC0 / (CLKDIV + 1); + ADC rate = ADC clock / (the number of clocks required for each conversion); + */ + adcBlockFreq = Chip_Clock_GetRate(Chip_ADC_GetClockIndex(pADC)); + if (burstMode) { + fullAdcRate = adcRate * clks; + } + else { + fullAdcRate = adcRate * getFullConvClk(); + } + + /* Get the round value by fomular: (2*A + B)/(2*B) */ + div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1; + return div; +} + +/* Set start mode for ADC */ +void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode) +{ + uint32_t temp; + temp = pADC->CR & (~ADC_CR_START_MASK); + pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode)); +} + +/* Get the ADC value */ +Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data) +{ + uint32_t temp; + temp = pADC->DR[channel]; + if (!ADC_DR_DONE(temp)) { + return ERROR; + } + /* if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */ + /* return ERROR; */ + *data = (uint16_t) ADC_DR_RESULT(temp); + return SUCCESS; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the ADC peripheral and the ADC setup structure to default value */ +void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup) +{ + uint8_t div; + uint32_t cr = 0; + uint32_t clk; + + Chip_Clock_EnableOpts(Chip_ADC_GetClockIndex(pADC), true, true, 1); + + pADC->INTEN = 0; /* Disable all interrupts */ + + cr |= ADC_CR_PDN; + ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE; + ADCSetup->bitsAccuracy = ADC_10BITS; + clk = 11; + ADCSetup->burstMode = false; + div = getClkDiv(pADC, false, ADCSetup->adcRate, clk); + cr |= ADC_CR_CLKDIV(div); + cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy); + pADC->CR = cr; +} + +/* Shutdown ADC */ +void Chip_ADC_DeInit(LPC_ADC_T *pADC) +{ + pADC->INTEN = 0x00000100; + pADC->CR = 0; + Chip_Clock_Disable(Chip_ADC_GetClockIndex(pADC)); +} + +/* Get the ADC value */ +Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data) +{ + return readAdcVal(pADC, channel, data); +} + +/* Get ADC Channel status from ADC data register */ +FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType) +{ + switch (StatusType) { + case ADC_DR_DONE_STAT: + return (pADC->STAT & (1UL << channel)) ? SET : RESET; + + case ADC_DR_OVERRUN_STAT: + channel += 8; + return (pADC->STAT & (1UL << channel)) ? SET : RESET; + + case ADC_DR_ADINT_STAT: + return pADC->STAT >> 16 ? SET : RESET; + + default: + break; + } + return RESET; +} + +/* Enable/Disable interrupt for ADC channel */ +void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pADC->INTEN |= (1UL << channel); + } + else { + pADC->INTEN &= (~(1UL << channel)); + } +} + +/* Select the mode starting the AD conversion */ +void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption) +{ + if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) { + if (EdgeOption) { + pADC->CR |= ADC_CR_EDGE; + } + else { + pADC->CR &= ~ADC_CR_EDGE; + } + } + setStartMode(pADC, (uint8_t) mode); +} + +/* Set the ADC Sample rate */ +void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate) +{ + uint8_t div; + uint32_t cr; + + cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK); + ADCSetup->adcRate = rate; + div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy)); + cr |= ADC_CR_CLKDIV(div); + cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy); + pADC->CR = cr; +} + +/* Set the ADC accuracy bits */ +void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution) +{ + ADCSetup->bitsAccuracy = resolution; + Chip_ADC_SetSampleRate(pADC, ADCSetup, ADCSetup->adcRate); +} + +/* Enable or disable the ADC channel on ADC peripheral */ +void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pADC->CR |= ADC_CR_CH_SEL(channel); + } + else { + pADC->CR &= ~ADC_CR_START_MASK; + pADC->CR &= ~ADC_CR_CH_SEL(channel); + } +} + +/* Enable burst mode */ +void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState) +{ + setStartMode(pADC, ADC_NO_START); + + if (NewState == DISABLE) { + pADC->CR &= ~ADC_CR_BURST; + } + else { + pADC->CR |= ADC_CR_BURST; + } +} + +/* Read the ADC value and convert it to 8bits value */ +Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data) +{ + uint16_t temp; + Status rt; + + rt = readAdcVal(pADC, channel, &temp); + *data = (uint8_t) temp; + + return rt; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/aes_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/aes_18xx_43xx.c new file mode 100644 index 0000000000000..c19840abef9fd --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/aes_18xx_43xx.c @@ -0,0 +1,180 @@ +/* + * @brief LPC18xx/43xx AES Engine driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define BOOTROM_BASE 0x10400100 +#define AES_API_TABLE_OFFSET 0x2 + +typedef void (*V_FP_V)(void); +typedef uint32_t (*U32_FP_V)(void); + +static unsigned long *BOOTROM_API_TABLE; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +static uint32_t (*aes_SetMode)(CHIP_AES_OP_MODE_T AesMode); +static void (*aes_LoadKey1)(void); +static void (*aes_LoadKey2)(void); +static void (*aes_LoadKeyRNG)(void); +static void (*aes_LoadKeySW)(uint8_t *pKey); +static void (*aes_LoadIV_SW)(uint8_t *pVector); +static void (*aes_LoadIV_IC)(void); +static uint32_t (*aes_Operate)(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t size); +static uint32_t (*aes_ProgramKey1)(uint8_t *pKey); +static uint32_t (*aes_ProgramKey2)(uint8_t *pKey); +static uint32_t (*aes_Config_DMA) (uint32_t channel_id); +static uint32_t (*aes_Operate_DMA)(uint32_t channel_id, uint8_t *dataOutAddr, uint8_t *dataInAddr, uint32_t size); +static uint32_t (*aes_Get_Status_DMA) (uint32_t channel_id); + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* CHIP AES Initialisation function */ +void Chip_AES_Init(void) +{ + uint32_t (*ROM_aes_Init)(void); + + BOOTROM_API_TABLE = *((unsigned long * *) BOOTROM_BASE + AES_API_TABLE_OFFSET); + + ROM_aes_Init = (uint32_t (*)(void))BOOTROM_API_TABLE[0]; + aes_SetMode = (uint32_t (*)(CHIP_AES_OP_MODE_T AesMode))BOOTROM_API_TABLE[1]; + aes_LoadKey1 = (void (*)(void))BOOTROM_API_TABLE[2]; + aes_LoadKey2 = (void (*)(void))BOOTROM_API_TABLE[3]; + aes_LoadKeyRNG = (void (*)(void))BOOTROM_API_TABLE[4]; + aes_LoadKeySW = (void (*)(uint8_t *pKey))BOOTROM_API_TABLE[5]; + aes_LoadIV_SW = (void (*)(uint8_t *pVector))BOOTROM_API_TABLE[6]; + aes_LoadIV_IC = (void (*)(void))BOOTROM_API_TABLE[7]; + aes_Operate = (uint32_t (*)(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t Size))BOOTROM_API_TABLE[8]; + aes_ProgramKey1 = (uint32_t (*)(uint8_t *pKey))BOOTROM_API_TABLE[9]; + aes_ProgramKey2 = (uint32_t (*)(uint8_t *pKey))BOOTROM_API_TABLE[10]; + aes_Config_DMA = (uint32_t (*)(uint32_t channel_id))BOOTROM_API_TABLE[11]; + aes_Operate_DMA = (uint32_t (*)(uint32_t channel_id, uint8_t *dataOutAddr, uint8_t *dataInAddr, uint32_t size))BOOTROM_API_TABLE[12]; + aes_Get_Status_DMA = (uint32_t (*) (uint32_t channel_id))BOOTROM_API_TABLE[13]; + + ROM_aes_Init(); +} + +/* Set Operation mode in AES Engine */ +uint32_t Chip_AES_SetMode(CHIP_AES_OP_MODE_T AesMode) +{ + return aes_SetMode(AesMode); +} + +/* Load 128-bit user key in AES Engine */ +void Chip_AES_LoadKey(uint32_t keyNum) +{ + if (keyNum) { + aes_LoadKey2(); + } + else { + aes_LoadKey1(); + } +} + +/* Load randomly generated key in AES engine */ +void Chip_AES_LoadKeyRNG(void) +{ + aes_LoadKeyRNG(); +} + +/* Load 128-bit AES software defined user key */ +void Chip_AES_LoadKeySW(uint8_t *pKey) +{ + aes_LoadKeySW(pKey); +} + +/* Load 128-bit AES initialization vector */ +void Chip_AES_LoadIV_SW(uint8_t *pVector) +{ + aes_LoadIV_SW(pVector); +} + +/* Load IC specific 128-bit AES initialization vector */ +void Chip_AES_LoadIV_IC(void) +{ + aes_LoadIV_IC(); +} + +/* Operate AES Engine */ +uint32_t Chip_AES_Operate(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t Size) +{ + return aes_Operate(pDatOut, pDatIn, Size); +} + +/* Program 128-bit AES Key in OTP */ +uint32_t Chip_AES_ProgramKey(uint32_t KeyNum, uint8_t *pKey) +{ + uint32_t status; + + if (KeyNum) { + status = aes_ProgramKey2(pKey); + } + else { + status = aes_ProgramKey1(pKey); + } + return status; +} + +/* Configure DMA channel to process AES block */ +uint32_t Chip_AES_Config_DMA(uint32_t channel_id) +{ + return aes_Config_DMA(channel_id); +} + +/* Enables DMA channel and Operates AES Engine */ +uint32_t Chip_AES_OperateDMA(uint32_t channel_id, uint8_t *dataOutAddr, uint8_t *dataInAddr, uint32_t size) +{ + return aes_Operate_DMA(channel_id,dataOutAddr,dataInAddr,size); +} + +/* Read status of DMA channels that process an AES data block. */ +uint32_t Chip_AES_GetStatusDMA(uint32_t channel_id) +{ + return aes_Get_Status_DMA(channel_id); +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/atimer_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/atimer_18xx_43xx.c new file mode 100644 index 0000000000000..c1a39c971b74e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/atimer_18xx_43xx.c @@ -0,0 +1,69 @@ +/* + * @brief LPC18xx/43xx Alarm Timer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize Alarm Timer */ +void Chip_ATIMER_Init(LPC_ATIMER_T *pATIMER, uint32_t PresetValue) +{ + Chip_ATIMER_UpdatePresetValue(pATIMER, PresetValue); + Chip_ATIMER_ClearIntStatus(pATIMER); +} + +/* Close ATIMER device */ +void Chip_ATIMER_DeInit(LPC_ATIMER_T *pATIMER) +{ + Chip_ATIMER_ClearIntStatus(pATIMER); + Chip_ATIMER_IntDisable(pATIMER); +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/ccan_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/ccan_18xx_43xx.c new file mode 100644 index 0000000000000..8268114dddf0e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/ccan_18xx_43xx.c @@ -0,0 +1,317 @@ +/* + * @brief LPC18xx/43xx CCAN driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Configure the bit timing for CCAN bus */ +STATIC void configTimming(LPC_CCAN_T *pCCAN, + uint32_t ClkDiv, + uint32_t BaudRatePrescaler, + uint8_t SynJumpWidth, + uint8_t Tseg1, + uint8_t Tseg2) +{ + /* Reset software */ + if (!(pCCAN->CNTL & CCAN_CTRL_INIT)) { + pCCAN->CNTL |= CCAN_CTRL_INIT; + } + + /*Set bus timing */ + pCCAN->CLKDIV = ClkDiv; /* Divider for CAN VPB3 clock */ + pCCAN->CNTL |= CCAN_CTRL_CCE; /* Start configuring bit timing */ + pCCAN->BT = (BaudRatePrescaler & 0x3F) | (SynJumpWidth & 0x03) << 6 | (Tseg1 & 0x0F) << 8 | (Tseg2 & 0x07) << 12; + pCCAN->BRPE = BaudRatePrescaler >> 6; /* Set Baud Rate Prescaler MSBs */ + pCCAN->CNTL &= ~CCAN_CTRL_CCE; /* Stop configuring bit timing */ + + /* Finish software initialization */ + pCCAN->CNTL &= ~CCAN_CTRL_INIT; + while ( pCCAN->CNTL & CCAN_CTRL_INIT ) {} +} + +/* Return 1->32; 0 if not find free msg */ +STATIC uint8_t getFreeMsgObject(LPC_CCAN_T *pCCAN) +{ + uint32_t msg_valid; + uint8_t i; + msg_valid = Chip_CCAN_GetValidMsg(pCCAN); + for (i = 0; i < CCAN_MSG_MAX_NUM; i++) { + if (!((msg_valid >> i) & 1UL)) { + return i + 1; + } + } + return 0; // No free object +} + +STATIC void freeMsgObject(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum) +{ + Chip_CCAN_SetValidMsg(pCCAN, IFSel, msgNum, false); +} + +/* Returns clock index for the peripheral block */ +STATIC CHIP_CCU_CLK_T Chip_CCAN_GetClockIndex(LPC_CCAN_T *pCCAN) +{ + CHIP_CCU_CLK_T clkCCAN; + + if (pCCAN == LPC_C_CAN1) { + clkCCAN = CLK_APB1_CAN1; + } + else { + clkCCAN = CLK_APB3_CAN0; + } + + return clkCCAN; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the CCAN peripheral, free all message object in RAM */ +void Chip_CCAN_Init(LPC_CCAN_T *pCCAN) +{ + uint8_t i; + + Chip_Clock_EnableOpts(Chip_CCAN_GetClockIndex(pCCAN), true, false, 1); + + for (i = 1; i <= CCAN_MSG_MAX_NUM; i++) { + freeMsgObject(pCCAN, CCAN_MSG_IF1, i); + } + Chip_CCAN_ClearStatus(pCCAN, (CCAN_STAT_RXOK | CCAN_STAT_TXOK)); +} + +/* De-initialize the CCAN peripheral */ +void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN) +{ + Chip_Clock_Disable(Chip_CCAN_GetClockIndex(pCCAN)); +} + +/* Select bit rate for CCAN bus */ +Status Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate) +{ + uint32_t pClk, div, quanta, segs, seg1, seg2, clk_per_bit, can_sjw; + pClk = Chip_Clock_GetRate(Chip_CCAN_GetClockIndex(pCCAN)); + clk_per_bit = pClk / bitRate; + + for (div = 0; div <= 15; div++) { + for (quanta = 1; quanta <= 32; quanta++) { + for (segs = 3; segs <= 17; segs++) { + if (clk_per_bit == (segs * quanta * (div + 1))) { + segs -= 3; + seg1 = segs / 2; + seg2 = segs - seg1; + can_sjw = seg1 > 3 ? 3 : seg1; + configTimming(pCCAN, div, quanta - 1, can_sjw, seg1, seg2); + return SUCCESS; + } + } + } + } + return ERROR; +} + +/* Clear the status of CCAN bus */ +void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, uint32_t val) +{ + uint32_t tmp = Chip_CCAN_GetStatus(pCCAN); + Chip_CCAN_SetStatus(pCCAN, tmp & (~val)); +} + +/* Set a message into the message object in message RAM */ +void Chip_CCAN_SetMsgObject(LPC_CCAN_T *pCCAN, + CCAN_MSG_IF_T IFSel, + CCAN_TRANSFER_DIR_T dir, + bool remoteFrame, + uint8_t msgNum, + const CCAN_MSG_OBJ_T *pMsgObj) +{ + uint16_t *pData; + uint32_t msgCtrl = 0; + + if (pMsgObj == NULL) { + return; + } + pData = (uint16_t *) (pMsgObj->data); + + msgCtrl |= CCAN_IF_MCTRL_UMSK | CCAN_IF_MCTRL_RMTEN(remoteFrame) | CCAN_IF_MCTRL_EOB | + (pMsgObj->dlc & CCAN_IF_MCTRL_DLC_MSK); + if (dir == CCAN_TX_DIR) { + msgCtrl |= CCAN_IF_MCTRL_TXIE; + if (!remoteFrame) { + msgCtrl |= CCAN_IF_MCTRL_TXRQ; + } + } + else { + msgCtrl |= CCAN_IF_MCTRL_RXIE; + } + + pCCAN->IF[IFSel].MCTRL = msgCtrl; + pCCAN->IF[IFSel].DA1 = *pData++; /* Lower two bytes of message pointer */ + pCCAN->IF[IFSel].DA2 = *pData++; /* Upper two bytes of message pointer */ + pCCAN->IF[IFSel].DB1 = *pData++; /* Lower two bytes of message pointer */ + pCCAN->IF[IFSel].DB2 = *pData; /* Upper two bytes of message pointer */ + + /* Configure arbitration */ + if (!(pMsgObj->id & (0x1 << 30))) { /* bit 30 is 0, standard frame */ + /* Mxtd: 0, Mdir: 1, Mask is 0x7FF */ + pCCAN->IF[IFSel].MSK2 = CCAN_IF_MASK2_MDIR(dir) | (CCAN_MSG_ID_STD_MASK << 2); + pCCAN->IF[IFSel].MSK1 = 0x0000; + + /* MsgVal: 1, Mtd: 0, Dir: 1, ID = 0x200 */ + pCCAN->IF[IFSel].ARB2 = CCAN_IF_ARB2_MSGVAL | CCAN_IF_ARB2_DIR(dir) | (pMsgObj->id << 2); + pCCAN->IF[IFSel].ARB1 = 0x0000; + } + else { /* Extended frame */ + /* Mxtd: 1, Mdir: 1, Mask is 0x1FFFFFFF */ + pCCAN->IF[IFSel].MSK2 = CCAN_IF_MASK2_MXTD | CCAN_IF_MASK2_MDIR(dir) | (CCAN_MSG_ID_EXT_MASK >> 16); + pCCAN->IF[IFSel].MSK1 = CCAN_MSG_ID_EXT_MASK & 0x0000FFFF; + + /* MsgVal: 1, Mtd: 1, Dir: 1, ID = 0x200000 */ + pCCAN->IF[IFSel].ARB2 = CCAN_IF_ARB2_MSGVAL | CCAN_IF_ARB2_XTD | CCAN_IF_ARB2_DIR(dir) | (pMsgObj->id >> 16); + pCCAN->IF[IFSel].ARB1 = pMsgObj->id & 0x0000FFFF; + } + + Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_WR | CCAN_IF_CMDMSK_TRANSFER_ALL, msgNum); +} + +/* Get a message object in message RAM into the message buffer */ +void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, CCAN_MSG_OBJ_T *pMsgObj) +{ + uint32_t *pData; + if (!pMsgObj) { + return; + } + pData = (uint32_t *) pMsgObj->data; + Chip_CCAN_TransferMsgObject(pCCAN, + IFSel, + CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_TRANSFER_ALL | CCAN_IF_CMDMSK_R_CLRINTPND, + msgNum); + + if (pCCAN->IF[IFSel].MCTRL & CCAN_IF_MCTRL_NEWD) { + pMsgObj->id = (pCCAN->IF[IFSel].ARB1) | (pCCAN->IF[IFSel].ARB2 << 16); + pMsgObj->dlc = pCCAN->IF[IFSel].MCTRL & CCAN_IF_MCTRL_DLC_MSK; + *pData++ = (pCCAN->IF[IFSel].DA2 << 16) | pCCAN->IF[IFSel].DA1; + *pData = (pCCAN->IF[IFSel].DB2 << 16) | pCCAN->IF[IFSel].DB1; + + if (pMsgObj->id & (0x1 << 30)) { + pMsgObj->id &= CCAN_MSG_ID_EXT_MASK; + } + else { + pMsgObj->id >>= 18; + pMsgObj->id &= CCAN_MSG_ID_STD_MASK; + } + } +} + +/* Data transfer between IF registers and Message RAM */ +void Chip_CCAN_TransferMsgObject(LPC_CCAN_T *pCCAN, + CCAN_MSG_IF_T IFSel, + uint32_t mask, + uint32_t msgNum) { + msgNum &= 0x3F; + pCCAN->IF[IFSel].CMDMSK = mask; + pCCAN->IF[IFSel].CMDREQ = msgNum; + while (pCCAN->IF[IFSel].CMDREQ & CCAN_IF_CMDREQ_BUSY ) {} +} + +/* Enable/Disable the message object to valid */ +void Chip_CCAN_SetValidMsg(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, bool valid) +{ + + uint32_t temp; + temp = pCCAN->IF[IFSel].ARB2; + if (!valid) { + pCCAN->IF[IFSel].ARB2 = (temp & (~CCAN_IF_ARB2_MSGVAL)); + } + else { + pCCAN->IF[IFSel].ARB2 = (temp | (CCAN_IF_ARB2_MSGVAL)); + } + + Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_WR | CCAN_IF_CMDMSK_ARB, msgNum); +} + +/* Send a message */ +void Chip_CCAN_Send(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, bool remoteFrame, CCAN_MSG_OBJ_T *pMsgObj) +{ + uint8_t msgNum = getFreeMsgObject(pCCAN); + if (!msgNum) { + return; + } + Chip_CCAN_SetMsgObject(pCCAN, IFSel, CCAN_TX_DIR, remoteFrame, msgNum, pMsgObj); + while (Chip_CCAN_GetTxRQST(pCCAN) >> (msgNum - 1)) { // blocking , wait for sending completed + } + if (!remoteFrame) { + freeMsgObject(pCCAN, IFSel, msgNum); + } +} + +/* Register a message ID for receiving */ +void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id) +{ + CCAN_MSG_OBJ_T temp; + uint8_t msgNum = getFreeMsgObject(pCCAN); + if (!msgNum) { + return; + } + temp.id = id; + Chip_CCAN_SetMsgObject(pCCAN, IFSel, CCAN_RX_DIR, false, msgNum, &temp); +} + +/* Remove a registered message ID from receiving */ +void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id) +{ + uint8_t i; + CCAN_MSG_OBJ_T temp; + for (i = 1; i <= CCAN_MSG_MAX_NUM; i++) { + Chip_CCAN_GetMsgObject(pCCAN, IFSel, i, &temp); + if (temp.id == id) { + freeMsgObject(pCCAN, IFSel, i); + } + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/chip_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/chip_18xx_43xx.c new file mode 100644 index 0000000000000..fef27eded5828 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/chip_18xx_43xx.c @@ -0,0 +1,123 @@ +/* + * @brief LPC18xx/LPC43xx chip driver source + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ +/* USB PLL pre-initialized setup values for 480MHz output rate */ +static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = { + 0x0000601D, /* Default control with main osc input, PLL disabled */ + 0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */ + 0x00000000, /* N-divider value */ + 0x00000000, /* Not applicable for USB PLL */ + 480000000 /* PLL output frequency */ +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ +/* System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock; + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +static void Chip_USB_PllSetup(void) +{ + /* No need to setup anything if PLL is already setup for the frequency */ + if (Chip_Clock_GetClockInputHz(CLKIN_USBPLL) == usbPLLSetup.freq) + return ; + + /* Setup default USB PLL state for a 480MHz output and attach */ + Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup); + + /* enable USB PLL */ + Chip_Clock_EnablePLL(CGU_USB_PLL); + + /* Wait for PLL lock */ + while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)) {} +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +void Chip_USB0_Init(void) +{ + /* Set up USB PLL */ + Chip_USB_PllSetup(); + + /* Setup USB0 base clock as clock out from USB PLL */ + Chip_Clock_SetBaseClock( CLK_BASE_USB0, CLKIN_USBPLL, true, true); + + /* enable USB main clock */ + Chip_Clock_EnableBaseClock(CLK_BASE_USB0); + Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1); + /* enable USB0 phy */ + Chip_CREG_EnableUSB0Phy(); +} + +void Chip_USB1_Init(void) +{ + /* Setup and enable the PLL */ + Chip_USB_PllSetup(); + + /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are + chained to make a divide by 8 function. Connect the output of + divider D to the USB1 base clock. */ + Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4); + Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2); + Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true); + + /* enable USB main clock */ + Chip_Clock_EnableBaseClock(CLK_BASE_USB1); + Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1); + /* enable USB1_DP and USB1_DN on chip FS phy.*/ + LPC_SCU->SFSUSB = 0x12; +} + + +/* Update system core clock rate, should be called if the system has + a clock rate change */ +void SystemCoreClockUpdate(void) +{ + /* CPU core speed */ + SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE); +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/clock_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/clock_18xx_43xx.c new file mode 100644 index 0000000000000..fe4cc48772531 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/clock_18xx_43xx.c @@ -0,0 +1,832 @@ +/* + * @brief LPC18xx/43xx clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Maps a peripheral clock to it's base clock */ +typedef struct { + CHIP_CCU_CLK_T clkstart; + CHIP_CCU_CLK_T clkend; + CHIP_CGU_BASE_CLK_T clkbase; +} CLK_PERIPH_TO_BASE_T; +static const CLK_PERIPH_TO_BASE_T periph_to_base[] = { + {CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3}, + {CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1}, + {CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI}, + {CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX}, +#if defined(CHIP_LPC43XX) + {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH}, +#endif + {CLK_USB0, CLK_USB0, CLK_BASE_USB0}, + {CLK_USB1, CLK_USB1, CLK_BASE_USB1}, +#if defined(CHIP_LPC43XX) + {CLK_SPI, CLK_SPI, CLK_BASE_SPI}, + {CLK_ADCHS, CLK_ADCHS, CLK_BASE_ADCHS}, +#endif + {CLK_APLL, CLK_APLL, CLK_BASE_APLL}, + {CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3}, + {CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2}, + {CLK_APB0_UART1, CLK_APB0_UART1, CLK_BASE_UART1}, + {CLK_APB0_UART0, CLK_APB0_UART0, CLK_BASE_UART0}, + {CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1}, + {CLK_APB0_SSP0, CLK_APB0_SSP0, CLK_BASE_SSP0}, + {CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO}, + {CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE} +}; + +#define CRYSTAL_32K_FREQ_IN (32 * 1024) + +/* Variables to use audio and usb pll frequency */ +static uint32_t audio_usb_pll_freq[CGU_AUDIO_PLL+1]; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ +__STATIC_INLINE uint32_t ABS(int val) +{ + if (val < 0) + return -val; + return val; +} + +static void pll_calc_divs(uint32_t freq, PLL_PARAM_T *ppll) +{ + + uint32_t prev = freq; + int n, m, p; + + /* When direct mode is set FBSEL should be a don't care */ + if (ppll->ctrl & (1 << 7)) { + ppll->ctrl &= ~(1 << 6); + } + for (n = 1; n <= 4; n++) { + for (p = 0; p < 4; p ++) { + for (m = 1; m <= 256; m++) { + uint32_t fcco, fout; + if (ppll->ctrl & (1 << 6)) { + fcco = ((m << (p + 1)) * ppll->fin) / n; + } else { + fcco = (m * ppll->fin) / n; + } + if (fcco < PLL_MIN_CCO_FREQ) continue; + if (fcco > PLL_MAX_CCO_FREQ) break; + if (ppll->ctrl & (1 << 7)) { + fout = fcco; + } else { + fout = fcco >> (p + 1); + } + + if (ABS(freq - fout) < prev) { + ppll->nsel = n; + ppll->psel = p + 1; + ppll->msel = m; + ppll->fout = fout; + ppll->fcco = fcco; + prev = ABS(freq - fout); + } + } + } + } +} + +static void pll_get_frac(uint32_t freq, PLL_PARAM_T *ppll) +{ + int diff[3]; + PLL_PARAM_T pll[3] = {{0},{0},{0}}; + + /* Try direct mode */ + pll[0].ctrl |= (1 << 7); + pll[0].fin = ppll->fin; + pll[0].srcin = ppll->srcin; + pll_calc_divs(freq, &pll[0]); + if (pll[0].fout == freq) { + *ppll = pll[0]; + return ; + } + diff[0] = ABS(freq - pll[0].fout); + + /* Try non-Integer mode */ + pll[2].ctrl &= ~(1 << 6); // need to set FBSEL to 0 + pll[2].fin = ppll->fin; + pll[2].srcin = ppll->srcin; + pll_calc_divs(freq, &pll[2]); + if (pll[2].fout == freq) { + *ppll = pll[2]; + return ; + } + diff[2] = ABS(freq - pll[2].fout); + + if (freq <= 110000000) { + /* Try integer mode */ + pll[1].ctrl = (1 << 6); + pll[1].fin = ppll->fin; + pll_calc_divs(freq, &pll[1]); + if (pll[1].fout == freq) { + *ppll = pll[1]; + return ; + } + } + diff[1] = ABS(freq - pll[1].fout); + + /* Find the min of 3 and return */ + if (diff[0] <= diff[1]) { + if (diff[0] <= diff[2]) { + *ppll = pll[0]; + } else { + *ppll = pll[2]; + } + } else { + if (diff[1] <= diff[2]) { + *ppll = pll[1]; + } else { + *ppll = pll[2]; + } + } +} + +/* Test PLL input values for a specific frequency range */ +static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz) +{ + uint32_t TestHz = TestMult * InputHz; + + if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) { + TestHz = 0; + } + + return TestHz; +} + +/* Returns clock rate out of a divider */ +static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider) +{ + CHIP_CGU_CLKIN_T input; + uint32_t div; + + input = Chip_Clock_GetDividerSource(divider); + div = Chip_Clock_GetDividerDivisor(divider); + return Chip_Clock_GetClockInputHz(input) / (div + 1); +} + +/* Finds the base clock for the peripheral clock */ +static CHIP_CGU_BASE_CLK_T Chip_Clock_FindBaseClock(CHIP_CCU_CLK_T clk) +{ + CHIP_CGU_BASE_CLK_T baseclk = CLK_BASE_NONE; + int i = 0; + + while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) { + if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) { + baseclk = periph_to_base[i].clkbase; + } + else { + i++; + } + } + + return baseclk; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Enables the crystal oscillator */ +void Chip_Clock_EnableCrystal(void) +{ + volatile uint32_t delay = 1000; + + uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL; + + /* Clear bypass mode */ + OldCrystalConfig &= (~2); + if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) { + LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig; + } + + /* Enable crystal oscillator */ + OldCrystalConfig &= (~1); + if (OscRateIn >= 20000000) { + OldCrystalConfig |= 4; /* Set high frequency mode */ + + } + LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig; + + /* Delay for 250uSec */ + while(delay--) {} +} + +/* Calculate the Main PLL div values */ +int Chip_Clock_CalcMainPLLValue(uint32_t freq, PLL_PARAM_T *ppll) +{ + ppll->fin = Chip_Clock_GetClockInputHz(ppll->srcin); + + /* Do sanity check on frequency */ + if (freq > MAX_CLOCK_FREQ || freq < (PLL_MIN_CCO_FREQ / 16) || !ppll->fin) { + return -1; + } + + ppll->ctrl = 1 << 7; /* Enable direct mode [If possible] */ + ppll->nsel = 0; + ppll->psel = 0; + ppll->msel = freq / ppll->fin; + + if (freq < PLL_MIN_CCO_FREQ || ppll->msel * ppll->fin != freq) { + pll_get_frac(freq, ppll); + if (!ppll->nsel) { + return -1; + } + ppll->nsel --; + } + + if (ppll->msel == 0) { + return - 1; + } + + if (ppll->psel) { + ppll->psel --; + } + + ppll->msel --; + + return 0; +} + +/* Disables the crystal oscillator */ +void Chip_Clock_DisableCrystal(void) +{ + /* Disable crystal oscillator */ + LPC_CGU->XTAL_OSC_CTRL |= 1; +} + +/* Configures the main PLL */ +uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz) +{ + uint32_t freqin = Chip_Clock_GetClockInputHz(Input); + uint32_t Mult, LastMult, MultEnd; + uint32_t freqout, freqout2; + + if (DesiredHz != 0xFFFFFFFF) { + /* Test DesiredHz rounded down */ + Mult = DesiredHz / freqin; + freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + /* Test DesiredHz rounded up */ + Mult++; + freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + if (freqout && !freqout2) { /* rounding up is no good? set first multiplier */ + Mult--; + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + if (!freqout && freqout2) { /* didn't work until rounded up? set 2nd multiplier */ + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + + if (freqout && freqout2) { /* either multiplier okay? choose closer one */ + if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) { + Mult--; + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + else { + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + } + } + + /* Neither multiplier okay? Try to start at MinHz and increment. + This should find the highest multiplier that is still good */ + Mult = MinHz / freqin; + MultEnd = MaxHz / freqin; + LastMult = 0; + while (1) { + freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + if (freqout) { + LastMult = Mult; + } + + if (Mult >= MultEnd) { + break; + } + Mult++; + } + + if (LastMult) { + return Chip_Clock_SetupMainPLLMult(Input, LastMult); + } + + return 0; +} + +/* Directly set the PLL multipler */ +uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult) +{ + volatile uint32_t delay = 250; + uint32_t freq = Chip_Clock_GetClockInputHz(Input); + uint32_t msel = 0, nsel = 0, psel = 0, pval = 1; + uint32_t PLLReg = LPC_CGU->PLL1_CTRL; + + freq *= mult; + msel = mult - 1; + + PLLReg &= ~(0x1F << 24);/* clear input source bits */ + PLLReg |= Input << 24; /* set input source bits to parameter */ + + /* Clear other PLL input bits */ + PLLReg &= ~((1 << 6) | /* FBSEL */ + (1 << 1) | /* BYPASS */ + (1 << 7) | /* DIRECT */ + (0x03 << 8) | (0xFF << 16) | (0x03 << 12)); /* PSEL, MSEL, NSEL- divider ratios */ + + PLLReg |= (1 << 11); /* AUTOBLOCK */ + + if (freq < 156000000) { + /* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */ + while ((2 * (pval) * freq) < 156000000) { + psel++; + pval *= 2; + } + + PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6); /* dividers + FBSEL */ + } + else if (freq < 320000000) { + PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6); /* dividers + DIRECT + FBSEL */ + } + else { + Chip_Clock_DisableMainPLL(); + return 0; + } + LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0); + + /* Wait for 50uSec */ + while(delay--) {} + + return freq; +} + +/* Returns the frequency of the main PLL */ +uint32_t Chip_Clock_GetMainPLLHz(void) +{ + uint32_t PLLReg = LPC_CGU->PLL1_CTRL; + uint32_t freq = Chip_Clock_GetClockInputHz((CHIP_CGU_CLKIN_T) ((PLLReg >> 24) & 0xF)); + uint32_t msel, nsel, psel, direct, fbsel; + uint32_t m, n, p; + const uint8_t ptab[] = {1, 2, 4, 8}; + + /* No lock? */ + if (!(LPC_CGU->PLL1_STAT & 1)) { + return 0; + } + + msel = (PLLReg >> 16) & 0xFF; + nsel = (PLLReg >> 12) & 0x3; + psel = (PLLReg >> 8) & 0x3; + direct = (PLLReg >> 7) & 0x1; + fbsel = (PLLReg >> 6) & 0x1; + + m = msel + 1; + n = nsel + 1; + p = ptab[psel]; + + if (direct || fbsel) { + return m * (freq / n); + } + + return (m / (2 * p)) * (freq / n); +} + +/* Sets up a CGU clock divider and it's input clock */ +void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor) +{ + uint32_t reg = LPC_CGU->IDIV_CTRL[Divider]; + + Divisor--; + + if (Input != CLKINPUT_PD) { + /* Mask off bits that need to changes */ + reg &= ~((0x1F << 24) | 1 | (CHIP_CGU_IDIV_MASK(Divider) << 2)); + + /* Enable autoblocking, clear PD, and set clock source & divisor */ + LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2); + } + else { + LPC_CGU->IDIV_CTRL[Divider] = reg | 1; /* Power down this divider */ + } +} + +/* Gets a CGU clock divider source */ +CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider) +{ + uint32_t reg = LPC_CGU->IDIV_CTRL[Divider]; + + if (reg & 1) { /* divider is powered down */ + return CLKINPUT_PD; + } + + return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F); +} + +/* Gets a CGU clock divider divisor */ +uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider) +{ + return (CHIP_CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & CHIP_CGU_IDIV_MASK(Divider)); +} + +/* Returns the frequency of the specified input clock source */ +uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input) +{ + uint32_t rate = 0; + + switch (input) { + case CLKIN_32K: + rate = CRYSTAL_32K_FREQ_IN; + break; + + case CLKIN_IRC: + rate = CGU_IRC_FREQ; + break; + + case CLKIN_ENET_RX: + if ((LPC_CREG->CREG6 & 0x07) != 0x4) { + /* MII mode requires 25MHz clock */ + rate = 25000000; + } + break; + + case CLKIN_ENET_TX: + if ((LPC_CREG->CREG6 & 0x07) != 0x4) { + rate = 25000000; /* MII uses 25 MHz */ + } else { + rate = 50000000; /* RMII uses 50 MHz */ + } + break; + + case CLKIN_CLKIN: + rate = ExtRateIn; + break; + + case CLKIN_CRYSTAL: + rate = OscRateIn; + break; + + case CLKIN_USBPLL: + rate = audio_usb_pll_freq[CGU_USB_PLL]; + break; + + case CLKIN_AUDIOPLL: + rate = audio_usb_pll_freq[CGU_AUDIO_PLL]; + break; + + case CLKIN_MAINPLL: + rate = Chip_Clock_GetMainPLLHz(); + break; + + case CLKIN_IDIVA: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A); + break; + + case CLKIN_IDIVB: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B); + break; + + case CLKIN_IDIVC: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C); + break; + + case CLKIN_IDIVD: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D); + break; + + case CLKIN_IDIVE: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E); + break; + + case CLKINPUT_PD: + rate = 0; + break; + + default: + break; + } + + return rate; +} + +/* Returns the frequency of the specified base clock source */ +uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock) +{ + return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock)); +} + +/* Sets a CGU Base Clock clock source */ +void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn) +{ + uint32_t reg = LPC_CGU->BASE_CLK[BaseClock]; + + if (BaseClock < CLK_BASE_NONE) { + if (Input != CLKINPUT_PD) { + /* Mask off fields we plan to update */ + reg &= ~((0x1F << 24) | 1 | (1 << 11)); + + if (autoblocken) { + reg |= (1 << 11); + } + if (powerdn) { + reg |= (1 << 0); + } + + /* Set clock source */ + reg |= (Input << 24); + + LPC_CGU->BASE_CLK[BaseClock] = reg; + } + } + else { + LPC_CGU->BASE_CLK[BaseClock] = reg | 1; /* Power down this base clock */ + } +} + +/* Reads CGU Base Clock clock source information */ +void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken, + bool *powerdn) +{ + uint32_t reg = LPC_CGU->BASE_CLK[BaseClock]; + CHIP_CGU_CLKIN_T ClkIn = (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F ); + + if (BaseClock < CLK_BASE_NONE) { + /* Get settings */ + *Input = ClkIn; + *autoblocken = (reg & (1 << 11)) ? true : false; + *powerdn = (reg & (1 << 0)) ? true : false; + } + else { + *Input = CLKINPUT_PD; + *powerdn = true; + *autoblocken = true; + } +} + +/*Enables a base clock source */ +void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock) +{ + if (BaseClock < CLK_BASE_NONE) { + LPC_CGU->BASE_CLK[BaseClock] &= ~1; + } +} + +/* Disables a base clock source */ +void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock) +{ + if (BaseClock < CLK_BASE_NONE) { + LPC_CGU->BASE_CLK[BaseClock] |= 1; + } +} + +/* Returns base clock enable state */ +bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock) +{ + bool enabled; + + if (BaseClock < CLK_BASE_NONE) { + enabled = (bool) ((LPC_CGU->BASE_CLK[BaseClock] & 1) == 0); + } + else { + enabled = false; + } + + return enabled; +} + +/* Gets a CGU Base Clock clock source */ +CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock) +{ + uint32_t reg; + + if (BaseClock >= CLK_BASE_NONE) { + return CLKINPUT_PD; + } + + reg = LPC_CGU->BASE_CLK[BaseClock]; + + /* base clock is powered down? */ + if (reg & 1) { + return CLKINPUT_PD; + } + + return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F); +} + +/* Enables a peripheral clock and sets clock states */ +void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div) +{ + uint32_t reg = 1; + + if (autoen) { + reg |= (1 << 1); + } + if (wakeupen) { + reg |= (1 << 2); + } + + /* Not all clocks support a divider, but we won't check that here. Only + dividers of 1 and 2 are allowed. Assume 1 if not 2 */ + if (div == 2) { + reg |= (1 << 5); + } + + /* Setup peripheral clock and start running */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg; + } + else { + LPC_CCU1->CLKCCU[clk].CFG = reg; + } +} + +/* Enables a peripheral clock */ +void Chip_Clock_Enable(CHIP_CCU_CLK_T clk) +{ + /* Start peripheral clock running */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1; + } + else { + LPC_CCU1->CLKCCU[clk].CFG |= 1; + } +} + +/* Enable RTC Clock */ +void Chip_Clock_RTCEnable(void) +{ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); /* Reset 32Khz oscillator */ + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* Enable 32 kHz & 1 kHz on osc32k and release reset */ +} + +/* Disables a peripheral clock */ +void Chip_Clock_Disable(CHIP_CCU_CLK_T clk) +{ + /* Stop peripheral clock */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1; + } + else { + LPC_CCU1->CLKCCU[clk].CFG &= ~1; + } +} + +/** + * Disable all branch output clocks with wake up mechanism enabled. + * Only the clocks with wake up mechanism enabled will be disabled & + * power down sequence started + */ +void Chip_Clock_StartPowerDown(void) +{ + /* Set Power Down bit */ + LPC_CCU1->PM = 1; + LPC_CCU2->PM = 1; +} + +/** + * Enable all branch output clocks after the wake up event. + * Only the clocks with wake up mechanism enabled will be enabled + */ +void Chip_Clock_ClearPowerDown(void) +{ + /* Clear Power Down bit */ + LPC_CCU1->PM = 0; + LPC_CCU2->PM = 0; +} + +/* Returns a peripheral clock rate */ +uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk) +{ + CHIP_CGU_BASE_CLK_T baseclk; + uint32_t reg, div, rate; + + /* Get CCU config register for clock */ + if (clk >= CLK_CCU2_START) { + reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG; + } + else { + reg = LPC_CCU1->CLKCCU[clk].CFG; + } + + /* Is the clock enabled? */ + if (reg & 1) { + /* Get base clock for this peripheral clock */ + baseclk = Chip_Clock_FindBaseClock(clk); + + /* Get base clock rate */ + rate = Chip_Clock_GetBaseClocktHz(baseclk); + + /* Get divider for this clock */ + if (((reg >> 5) & 0x7) == 0) { + div = 1; + } + else { + div = 2;/* No other dividers supported */ + + } + rate = rate / div; + } + else { + rate = 0; + } + + return rate; +} + +/* Get EMC Clock Rate */ +uint32_t Chip_Clock_GetEMCRate(void) + +{ + uint32_t ClkFreq; + uint32_t EMCDiv; + ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC); + + /* EMC Divider readback at pos 27 + TODO: just checked but dont mention in UM */ + EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07; + + /* Check EMC Divider to get real EMC clock out */ + if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) { + ClkFreq >>= 1; + } + return ClkFreq; +} + +/* Sets up the audio or USB PLL */ +void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum, + const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup) +{ + uint32_t reg = pPLLSetup->ctrl | (Input << 24); + + /* Setup from passed values */ + LPC_CGU->PLL[pllnum].PLL_CTRL = reg; + LPC_CGU->PLL[pllnum].PLL_MDIV = pPLLSetup->mdiv; + LPC_CGU->PLL[pllnum].PLL_NP_DIV = pPLLSetup->ndiv; + + /* Fractional divider is for audio PLL only */ + if (pllnum == CGU_AUDIO_PLL) { + LPC_CGU->PLL0AUDIO_FRAC = pPLLSetup->fract; + } + audio_usb_pll_freq[pllnum] = pPLLSetup->freq; +} + +/* Enables the audio or USB PLL */ +void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum) +{ + LPC_CGU->PLL[pllnum].PLL_CTRL &= ~1; +} + +/* Disables the audio or USB PLL */ +void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum) +{ + LPC_CGU->PLL[pllnum].PLL_CTRL |= 1; +} + +/* Returns the PLL status */ +uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum) +{ + return LPC_CGU->PLL[pllnum].PLL_STAT; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/dac_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/dac_18xx_43xx.c new file mode 100644 index 0000000000000..25d8f56307bae --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/dac_18xx_43xx.c @@ -0,0 +1,91 @@ +/* + * @brief LPC18xx/43xx D/A conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the DAC peripheral */ +void Chip_DAC_Init(LPC_DAC_T *pDAC) +{ + Chip_Clock_EnableOpts(CLK_APB3_DAC, true, true, 1); + + /* Set maximum update rate 1MHz */ + Chip_DAC_SetBias(pDAC, DAC_MAX_UPDATE_RATE_1MHz); +} + +/* Shutdown DAC peripheral */ +void Chip_DAC_DeInit(LPC_DAC_T *pDAC) +{ + Chip_Clock_Disable(CLK_APB3_DAC); +} + +/* Update value to DAC buffer*/ +void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value) +{ + uint32_t tmp; + + tmp = pDAC->CR & DAC_BIAS_EN; + tmp |= DAC_VALUE(dac_value); + /* Update value */ + pDAC->CR = tmp; +} + +/* Set Maximum update rate for DAC */ +void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias) +{ + pDAC->CR &= ~DAC_BIAS_EN; + + if (bias == DAC_MAX_UPDATE_RATE_400kHz) { + pDAC->CR |= DAC_BIAS_EN; + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/eeprom_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/eeprom_18xx_43xx.c new file mode 100644 index 0000000000000..0d1a25a353de8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/eeprom_18xx_43xx.c @@ -0,0 +1,106 @@ +/* + * @brief LPC18xx/43xx EEPROM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Setup EEPROM clock */ +STATIC void setClkDiv(LPC_EEPROM_T *pEEPROM) +{ + uint32_t clk; + + /* Setup EEPROM timing to 375KHz based on PCLK rate */ + clk = Chip_Clock_GetRate(CLK_MX_EEPROM); + + /* Set EEPROM clock divide value*/ + pEEPROM->CLKDIV = clk / EEPROM_CLOCK_DIV - 1; +} + +/* Setup EEPROM clock */ +STATIC INLINE void setWaitState(LPC_EEPROM_T *pEEPROM) +{ + /* Setup EEPROM wait states*/ + Chip_EEPROM_SetReadWaitState(pEEPROM, EEPROM_READ_WAIT_STATE_VAL); + Chip_EEPROM_SetWaitState(pEEPROM, EEPROM_WAIT_STATE_VAL); + +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the EEPROM peripheral with specified parameter */ +void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM) +{ + /* Disable EEPROM power down mode */ + Chip_EEPROM_DisablePowerDown(pEEPROM); + setClkDiv(pEEPROM); + setWaitState(pEEPROM); +} + +/* Write data from page register to non-volatile memory */ +void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM) +{ + Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE); + Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE); + Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFPROG); +} + +/* Wait for interrupt */ +void Chip_EEPROM_WaitForIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask) +{ + uint32_t status; + while (1) { + status = Chip_EEPROM_GetIntStatus(pEEPROM); + if ((status & mask) == mask) { + break; + } + } + Chip_EEPROM_ClearIntStatus(pEEPROM, mask); +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/emc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/emc_18xx_43xx.c new file mode 100644 index 0000000000000..a675641035de8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/emc_18xx_43xx.c @@ -0,0 +1,295 @@ +/* + * @brief LPC18xx/43xx EMC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* DIV function with result rounded up */ +#define EMC_DIV_ROUND_UP(x, y) ((x + y - 1) / y) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +#ifndef EMC_SUPPORT_ONLY_PL172 +/* Get ARM External Memory Controller Version */ +STATIC uint32_t getARMPeripheralID(void) +{ + uint32_t *RegAdd; + RegAdd = (uint32_t *) ((uint32_t) LPC_EMC + 0xFE0); + return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) | + ((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24); +} + +#endif + +/* Calculate Clock Count from Timing Unit(nanoseconds) */ +STATIC uint32_t convertTimmingParam(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust) +{ + uint32_t temp; + if (input_ns < 0) { + return (-input_ns) >> 8; + } + temp = EMC_Clock / 1000000; /* MHz calculation */ + temp = temp * input_ns / 1000; + + /* round up */ + temp += 0xFF; + + /* convert to simple integer number format */ + temp >>= 8; + if (temp > adjust) { + return temp - adjust; + } + + return 0; +} + +/* Get Dynamic Memory Device Colum len */ +STATIC uint32_t getColsLen(uint32_t DynConfig) +{ + uint32_t DevBusWidth; + DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03; + if (DevBusWidth == 2) { + return 8; + } + else if (DevBusWidth == 1) { + return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8; + } + else if (DevBusWidth == 0) { + return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9; + } + + return 0; +} + +/* Initializes the Dynamic Controller according to the specified parameters + in the IP_EMC_DYN_CONFIG_T */ +void initDynMem(LPC_EMC_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock) +{ + uint32_t ChipSelect, tmpclk; + volatile int i; + + for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) { + LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + (ChipSelect << 5)); + + EMC_Reg_add->DYNAMICRASCAS0 = Dynamic_Config->DevConfig[ChipSelect].RAS | + ((Dynamic_Config->DevConfig[ChipSelect].ModeRegister << + (8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00); + EMC_Reg_add->DYNAMICCONFIG0 = Dynamic_Config->DevConfig[ChipSelect].DynConfig; + } + pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig; /* Read strategy */ + + pEMC->DYNAMICRP = convertTimmingParam(EMC_Clock, Dynamic_Config->tRP, 1); + pEMC->DYNAMICRAS = convertTimmingParam(EMC_Clock, Dynamic_Config->tRAS, 1); + pEMC->DYNAMICSREX = convertTimmingParam(EMC_Clock, Dynamic_Config->tSREX, 1); + pEMC->DYNAMICAPR = convertTimmingParam(EMC_Clock, Dynamic_Config->tAPR, 1); + pEMC->DYNAMICDAL = convertTimmingParam(EMC_Clock, Dynamic_Config->tDAL, 0); + pEMC->DYNAMICWR = convertTimmingParam(EMC_Clock, Dynamic_Config->tWR, 1); + pEMC->DYNAMICRC = convertTimmingParam(EMC_Clock, Dynamic_Config->tRC, 1); + pEMC->DYNAMICRFC = convertTimmingParam(EMC_Clock, Dynamic_Config->tRFC, 1); + pEMC->DYNAMICXSR = convertTimmingParam(EMC_Clock, Dynamic_Config->tXSR, 1); + pEMC->DYNAMICRRD = convertTimmingParam(EMC_Clock, Dynamic_Config->tRRD, 1); + pEMC->DYNAMICMRD = convertTimmingParam(EMC_Clock, Dynamic_Config->tMRD, 1); + + for (i = 0; i < 1000; i++) { /* wait 100us */ + } + pEMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ + + for (i = 0; i < 1000; i++) {} + pEMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ + + pEMC->DYNAMICREFRESH = 2; /* ( 2 * 16 ) -> 32 clock cycles */ + + for (i = 0; i < 80; i++) {} + + tmpclk = EMC_DIV_ROUND_UP(convertTimmingParam(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16); + pEMC->DYNAMICREFRESH = tmpclk; + + pEMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ + + for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) { + /*uint32_t burst_length;*/ + uint32_t DynAddr; + uint8_t Col_len; + + Col_len = getColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig); + /* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */ + /* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */ + if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) { + /*32bit bus */ + /*burst_length = 2;*/ + Col_len += 2; + } + else { + /*burst_length = 4;*/ + Col_len += 1; + } + + /* Check for RBC mode */ + if (!(Dynamic_Config->DevConfig[ChipSelect].DynConfig & EMC_DYN_CONFIG_LPSDRAM)) { + if (!(Dynamic_Config->DevConfig[ChipSelect].DynConfig & (0x7 << EMC_DYN_CONFIG_DEV_SIZE_BIT))) { + /* 2 banks => 1 bank select bit */ + Col_len += 1; + } + else { + /* 4 banks => 2 bank select bits */ + Col_len += 2; + } + } + + DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr; + + + if (DynAddr != 0) { + uint32_t temp; + uint32_t ModeRegister; + ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister; + temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len))); + temp = temp; + } + } + pEMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */ + + /* enable buffers */ + pEMC->DYNAMICCONFIG0 |= 1 << 19; + pEMC->DYNAMICCONFIG1 |= 1 << 19; + pEMC->DYNAMICCONFIG2 |= 1 << 19; + pEMC->DYNAMICCONFIG3 |= 1 << 19; +} + +/* Initializes the Static Controller according to the specified parameters + * in the IP_EMC_STATIC_CONFIG_T + */ +void initStaticMem(LPC_EMC_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock) +{ + LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5)); + EMC_Reg_add->STATICCONFIG0 = Static_Config->Config; + EMC_Reg_add->STATICWAITWEN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitWen, 1); + EMC_Reg_add->STATICWAITOEN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitOen, 0); + EMC_Reg_add->STATICWAITRD0 = convertTimmingParam(EMC_Clock, Static_Config->WaitRd, 1); + EMC_Reg_add->STATICWAITPAG0 = convertTimmingParam(EMC_Clock, Static_Config->WaitPage, 1); + EMC_Reg_add->STATICWAITWR0 = convertTimmingParam(EMC_Clock, Static_Config->WaitWr, 2); + EMC_Reg_add->STATICWAITTURN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitTurn, 1); +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Dyanmic memory setup */ +void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config) +{ + uint32_t ClkFreq; + + /* Note clocks must be enabled prior to this call */ + ClkFreq = Chip_Clock_GetEMCRate(); + + initDynMem(LPC_EMC, Dynamic_Config, ClkFreq); +} + +/* Enable Dynamic Memory Controller */ +void Chip_EMC_Dynamic_Enable(uint8_t Enable) +{ + if (Enable) { + LPC_EMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE; + } + else { + LPC_EMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE; + } +} + +/* Static memory setup */ +void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config) +{ + uint32_t ClkFreq; + + /* Note clocks must be enabled prior to this call */ + ClkFreq = Chip_Clock_GetEMCRate(); + + initStaticMem(LPC_EMC, Static_Config, ClkFreq); +} + +/* Mirror CS1 to CS0 and DYCS0 */ +void Chip_EMC_Mirror(uint8_t Enable) +{ + if (Enable) { + LPC_EMC->CONTROL |= 1 << 1; + } + else { + LPC_EMC->CONTROL &= ~(1 << 1); + } +} + +/* Enable EMC */ +void Chip_EMC_Enable(uint8_t Enable) +{ + if (Enable) { + LPC_EMC->CONTROL |= 1; + } + else { + LPC_EMC->CONTROL &= ~(1); + } +} + +/* Set EMC LowPower Mode */ +void Chip_EMC_LowPowerMode(uint8_t Enable) +{ + if (Enable) { + LPC_EMC->CONTROL |= 1 << 2; + } + else { + LPC_EMC->CONTROL &= ~(1 << 2); + } +} + +/* Initialize EMC */ +void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode) +{ + LPC_EMC->CONFIG = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8); + + /* Enable EMC 001 Normal Memory Map, No low power mode */ + LPC_EMC->CONTROL = (Enable ? 1 : 0); +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/enet_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/enet_18xx_43xx.c new file mode 100644 index 0000000000000..2f8ef4bc68e49 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/enet_18xx_43xx.c @@ -0,0 +1,188 @@ +/* + * @brief LPC18xx/43xx Ethernet driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Saved address for PHY and clock divider */ +STATIC uint32_t phyCfg; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +STATIC INLINE void reset(LPC_ENET_T *pENET) +{ + Chip_RGU_TriggerReset(RGU_ETHERNET_RST); + while (Chip_RGU_InReset(RGU_ETHERNET_RST)) + {} + + /* Reset ethernet peripheral */ + Chip_ENET_Reset(pENET); +} + +STATIC uint32_t Chip_ENET_CalcMDCClock(void) +{ + uint32_t val = SystemCoreClock / 1000000UL; + + if (val >= 20 && val < 35) + return 2; + if (val >= 35 && val < 60) + return 3; + if (val >= 60 && val < 100) + return 0; + if (val >= 100 && val < 150) + return 1; + if (val >= 150 && val < 250) + return 4; + if (val >= 250 && val < 300) + return 5; + + /* Code should never reach here + unless there is BUG in frequency settings + */ + return 0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Basic Ethernet interface initialization */ +void Chip_ENET_Init(LPC_ENET_T *pENET, uint32_t phyAddr) +{ + Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); + + reset(pENET); + + /* Setup MII link divider to /102 and PHY address 1 */ + Chip_ENET_SetupMII(pENET, Chip_ENET_CalcMDCClock(), phyAddr); + + /* Enhanced descriptors, burst length = 1 */ + pENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); + + /* Initial MAC configuration for checksum offload, full duplex, + 100Mbps, disable receive own in half duplex, inter-frame gap + of 64-bits */ + pENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | + MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); + + /* Setup default filter */ + pENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; + + /* Flush transmit FIFO */ + pENET->DMA_OP_MODE = DMA_OM_FTF; + + /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at + 64 bytes */ + pENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); + + /* Clear all MAC interrupts */ + pENET->DMA_STAT = DMA_ST_ALL; + + /* Enable MAC interrupts */ + pENET->DMA_INT_EN = 0; +} + +/* Ethernet interface shutdown */ +void Chip_ENET_DeInit(LPC_ENET_T *pENET) +{ + /* Disable packet reception */ + pENET->MAC_CONFIG = 0; + + /* Flush transmit FIFO */ + pENET->DMA_OP_MODE = DMA_OM_FTF; + + /* Disable receive and transmit DMA processes */ + pENET->DMA_OP_MODE = 0; + + Chip_Clock_Disable(CLK_MX_ETHERNET); +} + +/* Sets up the PHY link clock divider and PHY address */ +void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr) +{ + /* Save clock divider and PHY address in MII address register */ + phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div); +} + +/* Starts a PHY write via the MII */ +void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data) +{ + /* Write value at PHY address and register */ + pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W; + pENET->MAC_MII_DATA = (uint32_t) data; + pENET->MAC_MII_ADDR |= MAC_MIIA_GB; +} + +/*Starts a PHY read via the MII */ +void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg) +{ + /* Read value at PHY address and register */ + pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg); + pENET->MAC_MII_ADDR |= MAC_MIIA_GB; +} + +/* Sets full or half duplex for the interface */ +void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full) +{ + if (full) { + pENET->MAC_CONFIG |= MAC_CFG_DM; + } + else { + pENET->MAC_CONFIG &= ~MAC_CFG_DM; + } +} + +/* Sets speed for the interface */ +void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100) +{ + if (speed100) { + pENET->MAC_CONFIG |= MAC_CFG_FES; + } + else { + pENET->MAC_CONFIG &= ~MAC_CFG_FES; + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/evrt_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/evrt_18xx_43xx.c new file mode 100644 index 0000000000000..40480fce52e0b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/evrt_18xx_43xx.c @@ -0,0 +1,117 @@ +/* + * @brief LPC18xx/43xx event router driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the EVRT */ +void Chip_EVRT_Init(void) +{ + uint8_t i = 0; + // Clear all register to be default + LPC_EVRT->HILO = 0x0000; + LPC_EVRT->EDGE = 0x0000; + LPC_EVRT->CLR_EN = 0xFFFF; + do { + i++; + LPC_EVRT->CLR_STAT = 0xFFFFF; + } while ((LPC_EVRT->STATUS != 0) && (i < 10)); +} + +/* Set up the type of interrupt type for a source to EVRT */ +void Chip_EVRT_ConfigIntSrcActiveType(CHIP_EVRT_SRC_T EVRT_Src, CHIP_EVRT_SRC_ACTIVE_T type) +{ + switch (type) { + case EVRT_SRC_ACTIVE_LOW_LEVEL: + LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_HIGH_LEVEL: + LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_FALLING_EDGE: + LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_RISING_EDGE: + LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src); + break; + + default: + break; + } +} + +/* Enable or disable interrupt sources to EVRT */ +void Chip_EVRT_SetUpIntSrc(CHIP_EVRT_SRC_T EVRT_Src, FunctionalState state) +{ + if (state == ENABLE) { + LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src); + } + else { + LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src); + } +} + +/* Check if a source is sending interrupt to EVRT */ +IntStatus Chip_EVRT_IsSourceInterrupting(CHIP_EVRT_SRC_T EVRT_Src) +{ + if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) { + return SET; + } + else {return RESET; } +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/fpu_init.c b/ports/lpc/chips/lpc_chip_43xx/src/fpu_init.c new file mode 100644 index 0000000000000..b9eea2cf63288 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/fpu_init.c @@ -0,0 +1,103 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#if defined(CORE_M4) + +#include "sys_config.h" +#include "cmsis.h" +#include "stdint.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define LPC_CPACR 0xE000ED88 + +#define SCB_MVFR0 0xE000EF40 +#define SCB_MVFR0_RESET 0x10110021 + +#define SCB_MVFR1 0xE000EF44 +#define SCB_MVFR1_RESET 0x11000011 + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Early initialization of the FPU */ +void fpuInit(void) +{ +#if __FPU_PRESENT != 0 + // from arm trm manual: + // ; CPACR is located at address 0xE000ED88 + // LDR.W R0, =0xE000ED88 + // ; Read CPACR + // LDR R1, [R0] + // ; Set bits 20-23 to enable CP10 and CP11 coprocessors + // ORR R1, R1, #(0xF << 20) + // ; Write back the modified value to the CPACR + // STR R1, [R0] + + volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; + volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; + volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; + volatile uint32_t Cpacr; + volatile uint32_t Mvfr0; + volatile uint32_t Mvfr1; + char vfpPresent = 0; + + Mvfr0 = *regMvfr0; + Mvfr1 = *regMvfr1; + + vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); + + if (vfpPresent) { + Cpacr = *regCpacr; + Cpacr |= (0xF << 20); + *regCpacr = Cpacr; // enable CP10 and CP11 for full access + } +#endif /* __FPU_PRESENT != 0 */ +} + +#endif /* defined(CORE_M4 */ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/gpdma_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/gpdma_18xx_43xx.c new file mode 100644 index 0000000000000..987f8216f4eee --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/gpdma_18xx_43xx.c @@ -0,0 +1,752 @@ +/* + * @brief LPC18xx/43xx GPDMA driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Channel array to monitor free channel */ +static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS]; + +/* Optimized Peripheral Source and Destination burst size (18xx,43xx) */ +static const uint8_t GPDMA_LUTPerBurst[] = { + GPDMA_BSIZE_4, /* MEMORY */ + GPDMA_BSIZE_1, /* MAT0.0 */ + GPDMA_BSIZE_1, /* UART0 Tx */ + GPDMA_BSIZE_1, /* MAT0.1 */ + GPDMA_BSIZE_1, /* UART0 Rx */ + GPDMA_BSIZE_1, /* MAT1.0 */ + GPDMA_BSIZE_1, /* UART1 Tx */ + GPDMA_BSIZE_1, /* MAT1.1 */ + GPDMA_BSIZE_1, /* UART1 Rx */ + GPDMA_BSIZE_1, /* MAT2.0 */ + GPDMA_BSIZE_1, /* UART2 Tx */ + GPDMA_BSIZE_1, /* MAT2.1 */ + GPDMA_BSIZE_1, /* UART2 Rx */ + GPDMA_BSIZE_1, /* MAT3.0 */ + GPDMA_BSIZE_1, /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + GPDMA_BSIZE_1, /* MAT3.1 */ + GPDMA_BSIZE_1, /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + GPDMA_BSIZE_4, /* SSP0 Rx */ + GPDMA_BSIZE_32, /* I2S channel 0 */ + GPDMA_BSIZE_4, /* SSP0 Tx */ + GPDMA_BSIZE_32, /* I2S channel 1 */ + GPDMA_BSIZE_4, /* SSP1 Rx */ + GPDMA_BSIZE_4, /* SSP1 Tx */ + GPDMA_BSIZE_4, /* ADC 0 */ + GPDMA_BSIZE_4, /* ADC 1 */ + GPDMA_BSIZE_1, /* DAC */ + GPDMA_BSIZE_32, /* I2S channel 0 */ + GPDMA_BSIZE_32 /* I2S channel 0 */ +}; + +/* Optimized Peripheral Source and Destination transfer width (18xx,43xx) */ +static const uint8_t GPDMA_LUTPerWid[] = { + GPDMA_WIDTH_WORD, /* MEMORY */ + GPDMA_WIDTH_WORD, /* MAT0.0 */ + GPDMA_WIDTH_BYTE, /* UART0 Tx */ + GPDMA_WIDTH_WORD, /* MAT0.1 */ + GPDMA_WIDTH_BYTE, /* UART0 Rx */ + GPDMA_WIDTH_WORD, /* MAT1.0 */ + GPDMA_WIDTH_BYTE, /* UART1 Tx */ + GPDMA_WIDTH_WORD, /* MAT1.1 */ + GPDMA_WIDTH_BYTE, /* UART1 Rx */ + GPDMA_WIDTH_WORD, /* MAT2.0 */ + GPDMA_WIDTH_BYTE, /* UART2 Tx */ + GPDMA_WIDTH_WORD, /* MAT2.1 */ + GPDMA_WIDTH_BYTE, /* UART2 Rx */ + GPDMA_WIDTH_WORD, /* MAT3.0 */ + GPDMA_WIDTH_BYTE, /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + GPDMA_WIDTH_WORD, /* MAT3.1 */ + GPDMA_WIDTH_BYTE, /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + GPDMA_WIDTH_BYTE, /* SSP0 Rx */ + GPDMA_WIDTH_WORD, /* I2S channel 0 */ + GPDMA_WIDTH_BYTE, /* SSP0 Tx */ + GPDMA_WIDTH_WORD, /* I2S channel 1 */ + GPDMA_WIDTH_BYTE, /* SSP1 Rx */ + GPDMA_WIDTH_BYTE, /* SSP1 Tx */ + GPDMA_WIDTH_WORD, /* ADC 0 */ + GPDMA_WIDTH_WORD, /* ADC 1 */ + GPDMA_WIDTH_WORD, /* DAC */ + GPDMA_WIDTH_WORD, /* I2S channel 0 */ + GPDMA_WIDTH_WORD/* I2S channel 0 */ +}; + +/* Lookup Table of Connection Type matched with (18xx,43xx) Peripheral Data (FIFO) register base address */ +volatile static const void *GPDMA_LUTPerAddr[] = { + NULL, /* MEMORY */ + (&LPC_TIMER0->MR), /* MAT0.0 */ + (&LPC_USART0-> /*RBTHDLR.*/ THR), /* UART0 Tx */ + ((uint32_t *) &LPC_TIMER0->MR + 1), /* MAT0.1 */ + (&LPC_USART0-> /*RBTHDLR.*/ RBR), /* UART0 Rx */ + (&LPC_TIMER1->MR), /* MAT1.0 */ + (&LPC_UART1-> /*RBTHDLR.*/ THR),/* UART1 Tx */ + ((uint32_t *) &LPC_TIMER1->MR + 1), /* MAT1.1 */ + (&LPC_UART1-> /*RBTHDLR.*/ RBR),/* UART1 Rx */ + (&LPC_TIMER2->MR), /* MAT2.0 */ + (&LPC_USART2-> /*RBTHDLR.*/ THR), /* UART2 Tx */ + ((uint32_t *) &LPC_TIMER2->MR + 1), /* MAT2.1 */ + (&LPC_USART2-> /*RBTHDLR.*/ RBR), /* UART2 Rx */ + (&LPC_TIMER3->MR), /* MAT3.0 */ + (&LPC_USART3-> /*RBTHDLR.*/ THR), /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + ((uint32_t *) &LPC_TIMER3->MR + 1), /* MAT3.1 */ + (&LPC_USART3-> /*RBTHDLR.*/ RBR), /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + (&LPC_SSP0->DR), /* SSP0 Rx */ + (&LPC_I2S0->TXFIFO), /* I2S0 Tx on channel 0 */ + (&LPC_SSP0->DR), /* SSP0 Tx */ + (&LPC_I2S0->RXFIFO), /* I2S0 Rx on channel 1 */ + (&LPC_SSP1->DR), /* SSP1 Rx */ + (&LPC_SSP1->DR), /* SSP1 Tx */ + (&LPC_ADC0->GDR), /* ADC 0 */ + (&LPC_ADC1->GDR), /* ADC 1 */ + (&LPC_DAC->CR), /* DAC */ + (&LPC_I2S1->TXFIFO), /* I2S1 Tx on channel 0 */ + (&LPC_I2S1->RXFIFO) /* I2S1 Rx on channel 1 */ +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ +/* Control which set of peripherals is connected to the DMA controller */ +STATIC uint8_t configDMAMux(uint32_t gpdma_peripheral_connection_number) +{ + uint8_t function, channel; + + switch (gpdma_peripheral_connection_number) { + case GPDMA_CONN_MAT0_0: + function = 0; + channel = 1; + break; + + case GPDMA_CONN_UART0_Tx: + function = 1; + channel = 1; + break; + + case GPDMA_CONN_MAT0_1: + function = 0; + channel = 2; + break; + + case GPDMA_CONN_UART0_Rx: + function = 1; + channel = 2; + break; + + case GPDMA_CONN_MAT1_0: + function = 0; + channel = 3; + break; + + case GPDMA_CONN_UART1_Tx: + function = 1; + channel = 3; + break; + + case GPDMA_CONN_I2S1_Tx_Channel_0: + function = 2; + channel = 3; + break; + + case GPDMA_CONN_MAT1_1: + function = 0; + channel = 4; + break; + + case GPDMA_CONN_UART1_Rx: + function = 1; + channel = 4; + break; + + case GPDMA_CONN_I2S1_Rx_Channel_1: + function = 2; + channel = 4; + break; + + case GPDMA_CONN_MAT2_0: + function = 0; + channel = 5; + break; + + case GPDMA_CONN_UART2_Tx: + function = 1; + channel = 5; + break; + + case GPDMA_CONN_MAT2_1: + function = 0; + channel = 6; + break; + + case GPDMA_CONN_UART2_Rx: + function = 1; + channel = 6; + break; + + case GPDMA_CONN_MAT3_0: + function = 0; + channel = 7; + break; + + case GPDMA_CONN_UART3_Tx: + function = 1; + channel = 7; + break; + + case GPDMA_CONN_SCT_0: + function = 2; + channel = 7; + break; + + case GPDMA_CONN_MAT3_1: + function = 0; + channel = 8; + break; + + case GPDMA_CONN_UART3_Rx: + function = 1; + channel = 8; + break; + + case GPDMA_CONN_SCT_1: + function = 2; + channel = 8; + break; + + case GPDMA_CONN_SSP0_Rx: + function = 0; + channel = 9; + break; + + case GPDMA_CONN_I2S_Tx_Channel_0: + function = 1; + channel = 9; + break; + + case GPDMA_CONN_SSP0_Tx: + function = 0; + channel = 10; + break; + + case GPDMA_CONN_I2S_Rx_Channel_1: + function = 1; + channel = 10; + break; + + case GPDMA_CONN_SSP1_Rx: + function = 0; + channel = 11; + break; + + case GPDMA_CONN_SSP1_Tx: + function = 0; + channel = 12; + break; + + case GPDMA_CONN_ADC_0: + function = 0; + channel = 13; + break; + + case GPDMA_CONN_ADC_1: + function = 0; + channel = 14; + break; + + case GPDMA_CONN_DAC: + function = 0; + channel = 15; + break; + + default: + function = 3; + channel = 15; + break; + } + /* Set select function to dmamux register */ + if (0 != gpdma_peripheral_connection_number) { + uint32_t temp; + temp = LPC_CREG->DMAMUX & (~(0x03 << (2 * channel))); + LPC_CREG->DMAMUX = temp | (function << (2 * channel)); + } + return channel; +} + +uint32_t makeCtrlWord(const GPDMA_CH_CFG_T *GPDMAChannelConfig, + uint32_t GPDMA_LUTPerBurstSrcConn, + uint32_t GPDMA_LUTPerBurstDstConn, + uint32_t GPDMA_LUTPerWidSrcConn, + uint32_t GPDMA_LUTPerWidDstConn) +{ + uint32_t ctrl_word = 0; + + switch (GPDMAChannelConfig->TransferType) { + /* Memory to memory */ + case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: + ctrl_word = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize((4UL)) /**< Burst size = 32 */ + | GPDMA_DMACCxControl_DBSize((4UL)) /**< Burst size = 32 */ + | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) + | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) + | GPDMA_DMACCxControl_SI + | GPDMA_DMACCxControl_DI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: + ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_DestTransUseAHBMaster1 + | GPDMA_DMACCxControl_SI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: + ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 + | GPDMA_DMACCxControl_DI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: + ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 + | GPDMA_DMACCxControl_DestTransUseAHBMaster1 + | GPDMA_DMACCxControl_I; + + break; + + /* Do not support any more transfer type, return ERROR */ + default: + return ERROR; + } + return ctrl_word; +} + +/* Set up the DPDMA according to the specification configuration details */ +Status setupChannel(LPC_GPDMA_T *pGPDMA, + GPDMA_CH_CFG_T *GPDMAChannelConfig, + uint32_t CtrlWord, + uint32_t LinkListItem, + uint8_t SrcPeripheral, + uint8_t DstPeripheral) +{ + GPDMA_CH_T *pDMAch; + + if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) { + /* This channel is enabled, return ERROR, need to release this channel first */ + return ERROR; + } + + /* Get Channel pointer */ + pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]); + + /* Reset the Interrupt status */ + pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)); + pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)); + + /* Assign Linker List Item value */ + pDMAch->LLI = LinkListItem; + + /* Enable DMA channels, little endian */ + pGPDMA->CONFIG = GPDMA_DMACConfig_E; + while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {} + + pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr; + pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr; + + /* Configure DMA Channel, enable Error Counter and Terminate counter */ + pDMAch->CONFIG = GPDMA_DMACCxConfig_IE + | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ + | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType) + | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) + | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral); + + pDMAch->CONTROL = CtrlWord; + + return SUCCESS; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the GPDMA */ +void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA) +{ + uint8_t i; + + Chip_Clock_EnableOpts(CLK_MX_DMA, true, true, 1); + + /* Reset all channel configuration register */ + for (i = 8; i > 0; i--) { + pGPDMA->CH[i - 1].CONFIG = 0; + } + + /* Clear all DMA interrupt and error flag */ + pGPDMA->INTTCCLEAR = 0xFF; + pGPDMA->INTERRCLR = 0xFF; + + /* Reset all channels are free */ + for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++) { + ChannelHandlerArray[i].ChannelStatus = DISABLE; + } +} + +/* Shutdown the GPDMA */ +void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA) +{ + Chip_Clock_Disable(CLK_MX_DMA); +} + +/* Stop a stream DMA transfer */ +void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum) +{ + Chip_GPDMA_ChannelCmd(pGPDMA, (ChannelNum), DISABLE); + if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum); + } + if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum); + } + ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE; +} + +/* The GPDMA stream interrupt status checking */ +Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum) +{ + + if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INT, ChannelNum)) { + /* Check counter terminal status */ + if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum); + return SUCCESS; + } + /* Check error terminal status */ + if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) { + /* Clear error counter Interrupt pending */ + + Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum); + return ERROR; + } + } + return ERROR; +} + +int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA, + GPDMA_CH_CFG_T *GPDMACfg, + uint8_t ChannelNum, + uint32_t src, + uint32_t dst, + uint32_t Size, + GPDMA_FLOW_CONTROL_T TransferType) +{ + int rval = -1; + GPDMACfg->ChannelNum = ChannelNum; + GPDMACfg->TransferType = TransferType; + GPDMACfg->TransferSize = Size; + + switch (TransferType) { + case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: + GPDMACfg->SrcAddr = (uint32_t) src; + GPDMACfg->DstAddr = (uint32_t) dst; + rval = 3; + GPDMACfg->TransferWidth = GPDMA_WIDTH_WORD; + GPDMACfg->TransferSize = Size / 4; + break; + + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: + GPDMACfg->SrcAddr = (uint32_t) src; + rval = 1; + GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst]; + break; + + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: + GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src]; + GPDMACfg->DstAddr = (uint32_t) dst; + rval = 2; + break; + + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: + GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src]; + GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst]; + rval = 0; + break; + + default: + break; + } + return rval; +} + +/* Read the status from different registers according to the type */ +IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel) +{ + /** + * TODO check the channel <=8 type is exited + */ + switch (type) { + case GPDMA_STAT_INT:/* check status of DMA channel interrupts */ + return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_INTTC: /* check terminal count interrupt request status for DMA */ + return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_INTERR: /* check interrupt status for DMA channels */ + return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_RAWINTTC: /* check status of the terminal count interrupt for DMA channels */ + return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_RAWINTERR: /* check status of the error interrupt for DMA channels */ + return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF))); + + default:/* check enable status for DMA channels */ + return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF))); + } +} + +/* Clear the Interrupt Flag from different registers according to the type */ +void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel) +{ + if (type == GPDMA_STATCLR_INTTC) { + /* clears the terminal count interrupt request on DMA channel */ + pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF)); + } + else { + /* clear the error interrupt request */ + pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF)); + } +} + +/* Enable or Disable the GPDMA Channel */ +void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState) +{ + GPDMA_CH_T *pDMAch; + + /* Get Channel pointer */ + pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[channelNum]); + + if (NewState == ENABLE) { + pDMAch->CONFIG |= GPDMA_DMACCxConfig_E; + } + else { + pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E; + } +} + +/* Do a DMA transfer M2M, M2P,P2M or P2P */ +Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum, + uint32_t src, + uint32_t dst, + GPDMA_FLOW_CONTROL_T TransferType, + uint32_t Size) +{ + GPDMA_CH_CFG_T GPDMACfg; + uint8_t SrcPeripheral = 0, DstPeripheral = 0; + uint32_t cwrd; + int ret; + + ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, Size, TransferType); + if (ret < 0) { + return ERROR; + } + + /* Adjust src/dst index if they are memory */ + if (ret & 1) { + src = 0; + } + else { + SrcPeripheral = configDMAMux(src); + } + + if (ret & 2) { + dst = 0; + } + else { + DstPeripheral = configDMAMux(dst); + } + + cwrd = makeCtrlWord(&GPDMACfg, + (uint32_t) GPDMA_LUTPerBurst[src], + (uint32_t) GPDMA_LUTPerBurst[dst], + (uint32_t) GPDMA_LUTPerWid[src], + (uint32_t) GPDMA_LUTPerWid[dst]); + if (setupChannel(pGPDMA, &GPDMACfg, cwrd, 0, SrcPeripheral, DstPeripheral) == ERROR) { + return ERROR; + } + + /* Start the Channel */ + Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE); + return SUCCESS; +} + +Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA, + DMA_TransferDescriptor_t *DMADescriptor, + uint32_t src, + uint32_t dst, + uint32_t Size, + GPDMA_FLOW_CONTROL_T TransferType, + const DMA_TransferDescriptor_t *NextDescriptor) +{ + int ret; + GPDMA_CH_CFG_T GPDMACfg; + + ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, 0, src, dst, Size, TransferType); + if (ret < 0) { + return ERROR; + } + + /* Adjust src/dst index if they are memory */ + if (ret & 1) { + src = 0; + } + + if (ret & 2) { + dst = 0; + } + + DMADescriptor->src = GPDMACfg.SrcAddr; + DMADescriptor->dst = GPDMACfg.DstAddr; + DMADescriptor->lli = (uint32_t) NextDescriptor; + DMADescriptor->ctrl = makeCtrlWord(&GPDMACfg, + (uint32_t) GPDMA_LUTPerBurst[src], + (uint32_t) GPDMA_LUTPerBurst[dst], + (uint32_t) GPDMA_LUTPerWid[src], + (uint32_t) GPDMA_LUTPerWid[dst]); + + /* By default set interrupt only for last transfer */ + if (NextDescriptor) { + DMADescriptor->ctrl &= ~GPDMA_DMACCxControl_I; + } + + return SUCCESS; +} + +/* Do a DMA scatter-gather transfer M2M, M2P,P2M or P2P using DMA descriptors */ +Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA, + uint8_t ChannelNum, + const DMA_TransferDescriptor_t *DMADescriptor, + GPDMA_FLOW_CONTROL_T TransferType) +{ + const DMA_TransferDescriptor_t *dsc = DMADescriptor; + GPDMA_CH_CFG_T GPDMACfg; + uint8_t SrcPeripheral = 0, DstPeripheral = 0; + uint32_t src = DMADescriptor->src, dst = DMADescriptor->dst; + int ret; + + ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, 0, TransferType); + if (ret < 0) { + return ERROR; + } + + /* Adjust src/dst index if they are memory */ + if (ret & 1) { + src = 0; + } + else { + SrcPeripheral = configDMAMux(src); + } + + if (ret & 2) { + dst = 0; + } + else { + DstPeripheral = configDMAMux(dst); + } + + if (setupChannel(pGPDMA, &GPDMACfg, dsc->ctrl, dsc->lli, SrcPeripheral, DstPeripheral) == ERROR) { + return ERROR; + } + + /* Start the Channel */ + Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE); + return SUCCESS; +} + +/* Get a free GPDMA channel for one DMA connection */ +uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA, + uint32_t PeripheralConnection_ID) +{ + uint8_t temp = 0; + for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++) { + if (!Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_ENABLED_CH, + temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) { + ChannelHandlerArray[temp].ChannelStatus = ENABLE; + return temp; + } + } + return 0; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/gpio_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/gpio_18xx_43xx.c new file mode 100644 index 0000000000000..2b849612359bc --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/gpio_18xx_43xx.c @@ -0,0 +1,66 @@ +/* + * @brief LPC18xx/43xx GPIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize GPIO block */ +void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) +{ +} + +/* De-Initialize GPIO block */ +void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) +{ +} + + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/gpiogroup_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/gpiogroup_18xx_43xx.c new file mode 100644 index 0000000000000..8e2ba2cf08271 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/gpiogroup_18xx_43xx.c @@ -0,0 +1,54 @@ +/* + * @brief LPC18xx/43xx GPIO group driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/i2c_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/i2c_18xx_43xx.c new file mode 100644 index 0000000000000..c9900096ba304 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/i2c_18xx_43xx.c @@ -0,0 +1,560 @@ +/* + * @brief LPC18xx/43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Control flags */ +#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA) +#define LPC_I2Cx(id) ((i2c[id].ip)) +#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0) + +/* I2C common interface structure */ +struct i2c_interface { + LPC_I2C_T *ip; /* IP base address of the I2C device */ + CHIP_CCU_CLK_T clk; /* Clock used by I2C */ + I2C_EVENTHANDLER_T mEvent; /* Current active Master event handler */ + I2C_EVENTHANDLER_T sEvent; /* Slave transfer events */ + I2C_XFER_T *mXfer; /* Current active xfer pointer */ + I2C_XFER_T *sXfer; /* Pointer to store xfer when bus is busy */ + uint32_t flags; /* Flags used by I2C master and slave */ +}; + +/* Slave interface structure */ +struct i2c_slave_interface { + I2C_XFER_T *xfer; + I2C_EVENTHANDLER_T event; +}; + +/* I2C interfaces */ +static struct i2c_interface i2c[I2C_NUM_INTERFACE] = { + {LPC_I2C0, CLK_APB1_I2C0, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}, + {LPC_I2C1, CLK_APB3_I2C1, Chip_I2C_EventHandler, NULL, NULL, NULL, 0} +}; + +static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE]; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +STATIC INLINE void enableClk(I2C_ID_T id) +{ + Chip_Clock_Enable(i2c[id].clk); +} + +STATIC INLINE void disableClk(I2C_ID_T id) +{ + Chip_Clock_Disable(i2c[id].clk); +} + +/* Get the ADC Clock Rate */ +STATIC INLINE uint32_t getClkRate(I2C_ID_T id) +{ + return Chip_Clock_GetRate(i2c[id].clk); +} + +/* Enable I2C and start master transfer */ +STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C) +{ + /* Reset STA, STO, SI */ + pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA | I2C_CON_AA; + + /* Enter to Master Transmitter mode */ + pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA; +} + +/* Enable I2C and enable slave transfers */ +STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C) +{ + /* Reset STA, STO, SI */ + pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA; + + /* Enter to Master Transmitter mode */ + pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA; +} + +/* Check if I2C bus is free */ +STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C) +{ + return !(pI2C->CONSET & I2C_CON_STO); +} + +/* Get current state of the I2C peripheral */ +STATIC INLINE int getCurState(LPC_I2C_T *pI2C) +{ + return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK); +} + +/* Check if the active state belongs to master mode*/ +STATIC INLINE int isMasterState(LPC_I2C_T *pI2C) +{ + return getCurState(pI2C) < 0x60; +} + +/* Set OWN slave address for specific slave ID */ +STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask) +{ + uint32_t index = (uint32_t) sid - 1; + pI2C->MASK[index] = mask; + if (sid == I2C_SLAVE_0) { + pI2C->ADR0 = addr; + } + else { + volatile uint32_t *abase = &pI2C->ADR1; + abase[index - 1] = addr; + } +} + +/* Match the slave address */ +STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask) +{ + mask |= 1; + return (addr1 & ~mask) == (addr2 & ~mask); +} + +/* Get the index of the active slave */ +STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr) +{ + if (!(slaveAddr >> 1)) { + return I2C_SLAVE_GENERAL; /* General call address */ + } + if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) { + return I2C_SLAVE_0; + } + if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) { + return I2C_SLAVE_1; + } + if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) { + return I2C_SLAVE_2; + } + if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) { + return I2C_SLAVE_3; + } + + /* If everything is fine the code should never come here */ + return I2C_SLAVE_GENERAL; +} + +/* Master transfer state change handler handler */ +int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer) +{ + uint32_t cclr = I2C_CON_FLAGS; + + switch (getCurState(pI2C)) { + case 0x08: /* Start condition on bus */ + case 0x10: /* Repeated start condition */ + pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0); + break; + + /* Tx handling */ + case 0x18: /* SLA+W sent and ACK received */ + case 0x28: /* DATA sent and ACK received */ + if (!xfer->txSz) { + cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO); + } + else { + pI2C->DAT = *xfer->txBuff++; + xfer->txSz--; + } + break; + + /* Rx handling */ + case 0x58: /* Data Received and NACK sent */ + cclr &= ~I2C_CON_STO; + + case 0x50: /* Data Received and ACK sent */ + *xfer->rxBuff++ = pI2C->DAT; + xfer->rxSz--; + + case 0x40: /* SLA+R sent and ACK received */ + if (xfer->rxSz > 1) { + cclr &= ~I2C_CON_AA; + } + break; + + /* NAK Handling */ + case 0x20: /* SLA+W sent NAK received */ + case 0x48: /* SLA+R sent NAK received */ + xfer->status = I2C_STATUS_SLAVENAK; + cclr &= ~I2C_CON_STO; + break; + + case 0x30: /* DATA sent NAK received */ + xfer->status = I2C_STATUS_NAK; + cclr &= ~I2C_CON_STO; + break; + + case 0x38: /* Arbitration lost */ + xfer->status = I2C_STATUS_ARBLOST; + break; + + /* Bus Error */ + case 0x00: + xfer->status = I2C_STATUS_BUSERR; + cclr &= ~I2C_CON_STO; + } + + /* Set clear control flags */ + pI2C->CONSET = cclr ^ I2C_CON_FLAGS; + pI2C->CONCLR = cclr & ~I2C_CON_STO; + + /* If stopped return 0 */ + if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) { + if (xfer->status == I2C_STATUS_BUSY) { + xfer->status = I2C_STATUS_DONE; + } + return 0; + } + return 1; +} + +/* Find the slave address of SLA+W or SLA+R */ +I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C) +{ + switch (getCurState(pI2C)) { + case 0x60: + case 0x68: + case 0x70: + case 0x78: + case 0xA8: + case 0xB0: + return lookupSlaveIndex(pI2C, pI2C->DAT); + } + + /* If everything is fine code should never come here */ + return I2C_SLAVE_GENERAL; +} + +/* Slave state machine handler */ +int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer) +{ + uint32_t cclr = I2C_CON_FLAGS; + int ret = RET_SLAVE_BUSY; + + xfer->status = I2C_STATUS_BUSY; + switch (getCurState(pI2C)) { + case 0x80: /* SLA: Data received + ACK sent */ + case 0x90: /* GC: Data received + ACK sent */ + *xfer->rxBuff++ = pI2C->DAT; + xfer->rxSz--; + ret = RET_SLAVE_RX; + if (xfer->rxSz > 1) { + cclr &= ~I2C_CON_AA; + } + break; + + case 0x60: /* Own SLA+W received */ + case 0x68: /* Own SLA+W received after losing arbitration */ + case 0x70: /* GC+W received */ + case 0x78: /* GC+W received after losing arbitration */ + xfer->slaveAddr = pI2C->DAT & ~1; + if (xfer->rxSz > 1) { + cclr &= ~I2C_CON_AA; + } + break; + + case 0xA8: /* SLA+R received */ + case 0xB0: /* SLA+R received after losing arbitration */ + xfer->slaveAddr = pI2C->DAT & ~1; + + case 0xB8: /* DATA sent and ACK received */ + pI2C->DAT = *xfer->txBuff++; + xfer->txSz--; + if (xfer->txSz > 0) { + cclr &= ~I2C_CON_AA; + } + ret = RET_SLAVE_TX; + break; + + case 0xC0: /* Data transmitted and NAK received */ + case 0xC8: /* Last data transmitted and ACK received */ + case 0x88: /* SLA: Data received + NAK sent */ + case 0x98: /* GC: Data received + NAK sent */ + case 0xA0: /* STOP/Repeated START condition received */ + ret = RET_SLAVE_IDLE; + cclr &= ~I2C_CON_AA; + xfer->status = I2C_STATUS_DONE; + if (xfer->slaveAddr & 1) { + cclr &= ~I2C_CON_STA; + } + break; + } + + /* Set clear control flags */ + pI2C->CONSET = cclr ^ I2C_CON_FLAGS; + pI2C->CONCLR = cclr & ~I2C_CON_STO; + + return ret; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ +/* Chip event handler interrupt based */ +void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event) +{ + struct i2c_interface *iic = &i2c[id]; + volatile I2C_STATUS_T *stat; + + /* Only WAIT event needs to be handled */ + if (event != I2C_EVENT_WAIT) { + return; + } + + stat = &iic->mXfer->status; + /* Wait for the status to change */ + while (*stat == I2C_STATUS_BUSY) {} +} + +/* Chip polling event handler */ +void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event) +{ + struct i2c_interface *iic = &i2c[id]; + volatile I2C_STATUS_T *stat; + + /* Only WAIT event needs to be handled */ + if (event != I2C_EVENT_WAIT) { + return; + } + + stat = &iic->mXfer->status; + /* Call the state change handler till xfer is done */ + while (*stat == I2C_STATUS_BUSY) { + if (Chip_I2C_IsStateChanged(id)) { + Chip_I2C_MasterStateHandler(id); + } + } +} + +/* Initializes the LPC_I2C peripheral with specified parameter */ +void Chip_I2C_Init(I2C_ID_T id) +{ + enableClk(id); + + /* Set I2C operation to default */ + LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN); +} + +/* De-initializes the I2C peripheral registers to their default reset values */ +void Chip_I2C_DeInit(I2C_ID_T id) +{ + /* Disable I2C control */ + LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STA | I2C_CON_AA; + + disableClk(id); +} + +/* Set up clock rate for LPC_I2C peripheral */ +void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate) +{ + uint32_t SCLValue; + + SCLValue = (getClkRate(id) / clockrate); + LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1); + LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH); +} + +/* Get current clock rate for LPC_I2C peripheral */ +uint32_t Chip_I2C_GetClockRate(I2C_ID_T id) +{ + return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL); +} + +/* Set the master event handler */ +int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event) +{ + struct i2c_interface *iic = &i2c[id]; + if (!iic->mXfer) { + iic->mEvent = event; + } + return iic->mEvent == event; +} + +/* Get the master event handler */ +I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id) +{ + return i2c[id].mEvent; +} + +/* Transmit and Receive data in master mode */ +int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer) +{ + struct i2c_interface *iic = &i2c[id]; + + iic->mEvent(id, I2C_EVENT_LOCK); + xfer->status = I2C_STATUS_BUSY; + iic->mXfer = xfer; + + /* If slave xfer not in progress */ + if (!iic->sXfer) { + startMasterXfer(iic->ip); + } + iic->mEvent(id, I2C_EVENT_WAIT); + iic->mXfer = 0; + + /* Wait for stop condition to appear on bus */ + while (!isI2CBusFree(iic->ip)) {} + + /* Start slave if one is active */ + if (SLAVE_ACTIVE(iic)) { + startSlaverXfer(iic->ip); + } + + iic->mEvent(id, I2C_EVENT_UNLOCK); + return (int) xfer->status; +} + +/* Master tx only */ +int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len) +{ + I2C_XFER_T xfer = {0}; + xfer.slaveAddr = slaveAddr; + xfer.txBuff = buff; + xfer.txSz = len; + while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {} + return len - xfer.txSz; +} + +/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode. + * This function is useful for communicating with the I2C slave registers + */ +int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len) +{ + I2C_XFER_T xfer = {0}; + xfer.slaveAddr = slaveAddr; + xfer.txBuff = &cmd; + xfer.txSz = 1; + xfer.rxBuff = buff; + xfer.rxSz = len; + while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {} + return len - xfer.rxSz; +} + +/* Sequential master read */ +int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len) +{ + I2C_XFER_T xfer = {0}; + xfer.slaveAddr = slaveAddr; + xfer.rxBuff = buff; + xfer.rxSz = len; + while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {} + return len - xfer.rxSz; +} + +/* Check if master state is active */ +int Chip_I2C_IsMasterActive(I2C_ID_T id) +{ + return isMasterState(i2c[id].ip); +} + +/* State change handler for master transfer */ +void Chip_I2C_MasterStateHandler(I2C_ID_T id) +{ + if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) { + i2c[id].mEvent(id, I2C_EVENT_DONE); + } +} + +/* Setup slave function */ +void Chip_I2C_SlaveSetup(I2C_ID_T id, + I2C_SLAVE_ID sid, + I2C_XFER_T *xfer, + I2C_EVENTHANDLER_T event, + uint8_t addrMask) +{ + struct i2c_interface *iic = &i2c[id]; + struct i2c_slave_interface *si2c = &i2c_slave[id][sid]; + si2c->xfer = xfer; + si2c->event = event; + + /* Set up the slave address */ + if (sid != I2C_SLAVE_GENERAL) { + setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask); + } + + if (!SLAVE_ACTIVE(iic) && !iic->mXfer) { + startSlaverXfer(iic->ip); + } + iic->flags |= 1 << (sid + 8); +} + +/* I2C Slave event handler */ +void Chip_I2C_SlaveStateHandler(I2C_ID_T id) +{ + int ret; + struct i2c_interface *iic = &i2c[id]; + + /* Get the currently addressed slave */ + if (!iic->sXfer) { + struct i2c_slave_interface *si2c; + + I2C_SLAVE_ID sid = getSlaveIndex(iic->ip); + si2c = &i2c_slave[id][sid]; + iic->sXfer = si2c->xfer; + iic->sEvent = si2c->event; + } + + iic->sXfer->slaveAddr |= iic->mXfer != 0; + ret = handleSlaveXferState(iic->ip, iic->sXfer); + if (ret) { + if (iic->sXfer->status == I2C_STATUS_DONE) { + iic->sXfer = 0; + } + iic->sEvent(id, (I2C_EVENT_T) ret); + } +} + +/* Disable I2C device */ +void Chip_I2C_Disable(I2C_ID_T id) +{ + LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC; +} + +/* State change checking */ +int Chip_I2C_IsStateChanged(I2C_ID_T id) +{ + return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/i2cm_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/i2cm_18xx_43xx.c new file mode 100644 index 0000000000000..5fab0b10a12f5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/i2cm_18xx_43xx.c @@ -0,0 +1,274 @@ +/* + * @brief LPC18xx/43xx I2C master driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Control flags */ +#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ +/* Get the ADC Clock Rate */ +static CHIP_CCU_CLK_T i2cm_getClkId(LPC_I2C_T *pI2C) +{ + return (pI2C == LPC_I2C0)? CLK_APB1_I2C0 : CLK_APB3_I2C1; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the LPC_I2C peripheral with specified parameter */ +void Chip_I2CM_Init(LPC_I2C_T *pI2C) +{ + /* Enable I2C clock */ + Chip_Clock_Enable(i2cm_getClkId(pI2C)); + /* Reset I2C state machine */ + Chip_I2CM_ResetControl(pI2C); +} + +/* De-initializes the I2C peripheral registers to their default reset values */ +void Chip_I2CM_DeInit(LPC_I2C_T *pI2C) +{ + /* Reset I2C state machine */ + Chip_I2CM_ResetControl(pI2C); + /* Disable I2C clock */ + Chip_Clock_Disable(i2cm_getClkId(pI2C)); +} + +/* Set up bus speed for LPC_I2C interface */ +void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed) +{ + uint32_t clockDiv = (Chip_Clock_GetRate(i2cm_getClkId(pI2C)) / busSpeed); + + Chip_I2CM_SetDutyCycle(pI2C, (clockDiv >> 1), (clockDiv - (clockDiv >> 1))); +} + +/* Master transfer state change handler handler */ +uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + uint32_t cclr = I2C_CON_FLAGS; + + switch (Chip_I2CM_GetCurState(pI2C)) { + case 0x08: /* Start condition on bus */ + case 0x10: /* Repeated start condition */ + pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0); + break; + + /* Tx handling */ + case 0x20: /* SLA+W sent NAK received */ + case 0x30: /* DATA sent NAK received */ + if ((xfer->options & I2CM_XFER_OPTION_IGNORE_NACK) == 0) { + xfer->status = I2CM_STATUS_NAK; + cclr &= ~I2C_CON_STO; + break; + } + + case 0x18: /* SLA+W sent and ACK received */ + case 0x28: /* DATA sent and ACK received */ + if (!xfer->txSz) { + if (xfer->rxSz) { + cclr &= ~I2C_CON_STA; + } + else { + xfer->status = I2CM_STATUS_OK; + cclr &= ~I2C_CON_STO; + } + + } + else { + pI2C->DAT = *xfer->txBuff++; + xfer->txSz--; + } + break; + + /* Rx handling */ + case 0x58: /* Data Received and NACK sent */ + case 0x50: /* Data Received and ACK sent */ + *xfer->rxBuff++ = pI2C->DAT; + xfer->rxSz--; + + case 0x40: /* SLA+R sent and ACK received */ + if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) { + cclr &= ~I2C_CON_AA; + } + if (xfer->rxSz == 0) { + xfer->status = I2CM_STATUS_OK; + cclr &= ~I2C_CON_STO; + } + break; + + /* NAK Handling */ + case 0x48: /* SLA+R sent NAK received */ + xfer->status = I2CM_STATUS_SLAVE_NAK; + cclr &= ~I2C_CON_STO; + break; + + case 0x38: /* Arbitration lost */ + xfer->status = I2CM_STATUS_ARBLOST; + break; + + case 0x00: /* Bus Error */ + xfer->status = I2CM_STATUS_BUS_ERROR; + cclr &= ~I2C_CON_STO; + break; + case 0xF8: + return 0; + + default: + xfer->status = I2CM_STATUS_ERROR; + cclr &= ~I2C_CON_STO; + break; + } + + /* Set clear control flags */ + pI2C->CONSET = cclr ^ I2C_CON_FLAGS; + /* Stop flag should not be cleared as it is a reserved bit */ + pI2C->CONCLR = cclr & (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA); + + return xfer->status != I2CM_STATUS_BUSY; +} + +/* Transmit and Receive data in master mode */ +void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + /* set the transfer status as busy */ + xfer->status = I2CM_STATUS_BUSY; + /* Clear controller state. */ + Chip_I2CM_ResetControl(pI2C); + /* Enter to Master Transmitter mode */ + Chip_I2CM_SendStart(pI2C); +} + +/* Transmit and Receive data in master mode */ +uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + uint32_t ret = 0; + /* start transfer */ + Chip_I2CM_Xfer(pI2C, xfer); + + while (ret == 0) { + /* wait for status change interrupt */ + while ( Chip_I2CM_StateChanged(pI2C) == 0) {} + /* call state change handler */ + ret = Chip_I2CM_XferHandler(pI2C, xfer); + } + return ret; +} + +/* Master tx only */ +uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len) +{ + uint32_t txLen = 0, err = 0; + + /* clear state change interrupt status */ + Chip_I2CM_ClearSI(pI2C); + /* generate START condition */ + Chip_I2CM_SendStart(pI2C); + + while ((txLen < len) && (err == 0)) { + /* wait for status change interrupt */ + while ( Chip_I2CM_StateChanged(pI2C) == 0) {} + + /* check status and send data */ + switch (Chip_I2CM_GetCurState(pI2C)) { + case 0x08: /* Start condition on bus */ + case 0x10: /* Repeated start condition */ + case 0x18: /* SLA+W sent and ACK received */ + case 0x28: /* DATA sent and ACK received */ + Chip_I2CM_WriteByte(pI2C, buff[txLen++]); + break; + + case 0x38: /* Arbitration lost */ + break; + + default: /* we shouldn't be in any other state */ + err = 1; + break; + } + /* clear state change interrupt status */ + Chip_I2CM_ClearSI(pI2C); + } + + return txLen; +} + +/* Sequential master read */ +uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len) +{ + uint32_t rxLen = 0, err = 0; + + /* clear state change interrupt status */ + Chip_I2CM_ClearSI(pI2C); + /* generate START condition and auto-ack data received */ + pI2C->CONSET = I2C_CON_AA | I2C_CON_STA; + + while ((rxLen < len) && (err == 0)) { + /* wait for status change interrupt */ + while ( Chip_I2CM_StateChanged(pI2C) == 0) {} + + /* check status and send data */ + switch (Chip_I2CM_GetCurState(pI2C)) { + case 0x08: /* Start condition on bus */ + case 0x10: /* Repeated start condition */ + case 0x40: /* SLA+R sent and ACK received */ + case 0x50: /* Data Received and ACK sent */ + buff[rxLen++] = Chip_I2CM_ReadByte(pI2C); + break; + + case 0x38: /* Arbitration lost */ + break; + + default: /* we shouldn't be in any other state */ + err = 1; + break; + } + /* clear state change interrupt status */ + Chip_I2CM_ClearSI(pI2C); + } + + return rxLen; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/i2s_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/i2s_18xx_43xx.c new file mode 100644 index 0000000000000..5af643d403b29 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/i2s_18xx_43xx.c @@ -0,0 +1,264 @@ +/* + * @brief LPC18xx/43xx I2S driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Get divider value */ +STATIC Status getClkDiv(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format, uint16_t *pxDiv, uint16_t *pyDiv, uint32_t *pN) +{ + uint32_t pClk; + uint32_t x, y; + uint64_t divider; + uint16_t dif; + uint16_t xDiv = 0, yDiv = 0; + uint32_t N; + uint16_t err, ErrorOptimal = 0xFFFF; + + pClk = Chip_Clock_GetRate(CLK_APB1_I2S); + + /* divider is a fixed point number with 16 fractional bits */ + divider = (((uint64_t) (format->SampleRate) * 2 * (format->WordWidth) * 2) << 16) / pClk; + /* find N that make x/y <= 1 -> divider <= 2^16 */ + for (N = 64; N > 0; N--) { + if ((divider * N) < (1 << 16)) { + break; + } + } + if (N == 0) { + return ERROR; + } + divider *= N; + for (y = 255; y > 0; y--) { + x = y * divider; + if (x & (0xFF000000)) { + continue; + } + dif = x & 0xFFFF; + if (dif > 0x8000) { + err = 0x10000 - dif; + } + else { + err = dif; + } + if (err == 0) { + yDiv = y; + break; + } + else if (err < ErrorOptimal) { + ErrorOptimal = err; + yDiv = y; + } + } + xDiv = ((uint64_t) yDiv * (format->SampleRate) * 2 * (format->WordWidth) * N * 2) / pClk; + if (xDiv >= 256) { + xDiv = 0xFF; + } + if (xDiv == 0) { + xDiv = 1; + } + + *pxDiv = xDiv; + *pyDiv = yDiv; + *pN = N; + return SUCCESS; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the I2S interface */ +void Chip_I2S_Init(LPC_I2S_T *pI2S) +{ + Chip_Clock_Enable(CLK_APB1_I2S); +} + +/* Shutdown I2S */ +void Chip_I2S_DeInit(LPC_I2S_T *pI2S) +{ + pI2S->DAI = 0x07E1; + pI2S->DAO = 0x87E1; + pI2S->IRQ = 0; + pI2S->TXMODE = 0; + pI2S->RXMODE = 0; + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] = 0; + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] = 0; + Chip_Clock_Disable(CLK_APB1_I2S); +} + +/* Configure I2S for Audio Format input */ +Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format) +{ + uint32_t temp; + uint16_t xDiv, yDiv; + uint32_t N; + + if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) { + return ERROR; + } + + temp = pI2S->DAO & (~(I2S_DAO_WORDWIDTH_MASK | I2S_DAO_MONO | I2S_DAO_SLAVE | I2S_DAO_WS_HALFPERIOD_MASK)); + if (format->WordWidth <= 8) { + temp |= I2S_WORDWIDTH_8; + } + else if (format->WordWidth <= 16) { + temp |= I2S_WORDWIDTH_16; + } + else { + temp |= I2S_WORDWIDTH_32; + } + + temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO; + temp |= I2S_MASTER_MODE; + temp |= I2S_DAO_WS_HALFPERIOD(format->WordWidth - 1); + pI2S->DAO = temp; + pI2S->TXMODE = I2S_TXMODE_CLKSEL(0); + pI2S->TXBITRATE = N - 1; + pI2S->TXRATE = yDiv | (xDiv << 8); + return SUCCESS; +} + +/* Configure I2S for Audio Format input */ +Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format) +{ + uint32_t temp; + uint16_t xDiv, yDiv; + uint32_t N; + + if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) { + return ERROR; + } + temp = pI2S->DAI & (~(I2S_DAI_WORDWIDTH_MASK | I2S_DAI_MONO | I2S_DAI_SLAVE | I2S_DAI_WS_HALFPERIOD_MASK)); + if (format->WordWidth <= 8) { + temp |= I2S_WORDWIDTH_8; + } + else if (format->WordWidth <= 16) { + temp |= I2S_WORDWIDTH_16; + } + else { + temp |= I2S_WORDWIDTH_32; + } + + temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO; + temp |= I2S_MASTER_MODE; + temp |= I2S_DAI_WS_HALFPERIOD(format->WordWidth - 1); + pI2S->DAI = temp; + pI2S->RXMODE = I2S_RXMODE_CLKSEL(0); + pI2S->RXBITRATE = N - 1; + pI2S->RXRATE = yDiv | (xDiv << 8); + return SUCCESS; +} + +/* Enable/Disable Interrupt with a specific FIFO depth */ +void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth) +{ + uint32_t temp; + depth &= 0x0F; + if (newState == ENABLE) { + temp = pI2S->IRQ & (~I2S_IRQ_TX_DEPTH_MASK); + pI2S->IRQ = temp | (I2S_IRQ_TX_DEPTH(depth)); + pI2S->IRQ |= 0x02; + } + else { + pI2S->IRQ &= (~0x02); + } +} + +/* Enable/Disable Interrupt with a specific FIFO depth */ +void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth) +{ + uint32_t temp; + depth &= 0x0F; + if (newState == ENABLE) { + temp = pI2S->IRQ & (~I2S_IRQ_RX_DEPTH_MASK); + pI2S->IRQ = temp | (I2S_IRQ_RX_DEPTH(depth)); + pI2S->IRQ |= 0x01; + } + else { + pI2S->IRQ &= (~0x01); + } +} + +/* Enable/Disable DMA with a specific FIFO depth */ +void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S, + I2S_DMA_CHANNEL_T dmaNum, + FunctionalState newState, + uint8_t depth) +{ + /* Enable/Disable I2S transmit*/ + if (newState == ENABLE) { + /* Set FIFO Level */ + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] &= ~(0x0F << 16); + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] |= depth << 16; + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] |= 0x02; + } + else { + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] &= ~0x02; + } +} + +/* Enable/Disable DMA with a specific FIFO depth */ +void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S, + I2S_DMA_CHANNEL_T dmaNum, + FunctionalState newState, + uint8_t depth) +{ + + /* Enable/Disable I2S Receive */ + if (newState == ENABLE) { + /* Set FIFO Level */ + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] &= ~(0x0F << 8); + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] |= depth << 8; + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] |= 0x01; + } + else { + pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] &= ~0x01; + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/iap_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/iap_18xx_43xx.c new file mode 100644 index 0000000000000..067ce6217f1b5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/iap_18xx_43xx.c @@ -0,0 +1,211 @@ +/* + * @brief Common FLASH IAP support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the IAP command interface */ +uint8_t Chip_IAP_Init(void) +{ + uint32_t command[5], result[4]; + + command[0] = 49; /* IAP_INIT */ + result[0] = IAP_CMD_SUCCESS; + iap_entry(command, result); + return result[0]; +} + +/* Prepare sector for write operation */ +uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector, uint8_t flashBank) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_PREWRRITE_CMD; + command[1] = strSector; + command[2] = endSector; + command[3] = flashBank; + iap_entry(command, result); + + return result[0]; +} + +/* Copy RAM to flash */ +uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_WRISECTOR_CMD; + command[1] = dstAdd; + command[2] = (uint32_t) srcAdd; + command[3] = byteswrt; + command[4] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} + +/* Erase sector */ +uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector, uint8_t flashBank) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_ERSSECTOR_CMD; + command[1] = strSector; + command[2] = endSector; + command[3] = SystemCoreClock / 1000; + command[4] = flashBank; + iap_entry(command, result); + + return result[0]; +} + +/* Blank check sector */ +uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector, uint8_t flashBank) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_BLANK_CHECK_SECTOR_CMD; + command[1] = strSector; + command[2] = endSector; + command[3] = flashBank; + iap_entry(command, result); + + return result[0]; +} + +/* Read part identification number */ +uint32_t Chip_IAP_ReadPID() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_REPID_CMD; + iap_entry(command, result); + + return result[1]; +} + +/* Read boot code version number */ +uint8_t Chip_IAP_ReadBootCode() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_READ_BOOT_CODE_CMD; + iap_entry(command, result); + + return result[0]; +} + +/* IAP compare */ +uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_COMPARE_CMD; + command[1] = dstAdd; + command[2] = srcAdd; + command[3] = bytescmp; + iap_entry(command, result); + + return result[0]; +} + +/* Reinvoke ISP */ +uint8_t Chip_IAP_ReinvokeISP() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_REINVOKE_ISP_CMD; + iap_entry(command, result); + + return result[0]; +} + +/* Read the unique ID */ +uint32_t Chip_IAP_ReadUID(uint32_t uid[]) +{ + uint32_t command[5], result[5], i; + + command[0] = IAP_READ_UID_CMD; + iap_entry(command, result); + for(i = 0; i < 4; i++) { + uid[i] = result[i + 1]; + } + + return result[0]; +} + +/* Erase page */ +uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_ERASE_PAGE_CMD; + command[1] = strPage; + command[2] = endPage; + command[3] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} + +/* Set active boot flash bank */ +uint8_t Chip_IAP_SetBootFlashBank(uint8_t bankNum) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_SET_BOOT_FLASH; + command[1] = bankNum; + command[2] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c new file mode 100644 index 0000000000000..0ec0cab9f7ba4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c @@ -0,0 +1,212 @@ +/* + * @brief LPC18xx/43xx LCD chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +static LCD_CURSOR_SIZE_OPT_T LCD_Cursor_Size = LCD_CURSOR_64x64; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the LCD controller */ +void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct) +{ + uint32_t i, regValue, *pPal; + uint32_t pcd; + + /* Enable LCD Clock */ + Chip_Clock_EnableOpts(CLK_MX_LCD, true, true, 1); + + /* disable the display */ + pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE; + + /* Setting LCD_TIMH register */ + regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2) + | (( (LCD_ConfigStruct->HSW - 1) & 0xFF) << 8) + | (( (LCD_ConfigStruct->HFP - 1) & 0xFF) << 16) + | (( (LCD_ConfigStruct->HBP - 1) & 0xFF) << 24) ); + pLCD->TIMH = regValue; + + /* Setting LCD_TIMV register */ + regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0) + | (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10) + | (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16) + | (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) ); + pLCD->TIMV = regValue; + + /* Generate the clock and signal polarity control word */ + regValue = 0; + regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6); + regValue |= (LCD_ConfigStruct->IOE & 1) << 14; + regValue |= (LCD_ConfigStruct->IPC & 1) << 13; + regValue |= (LCD_ConfigStruct->IHS & 1) << 12; + regValue |= (LCD_ConfigStruct->IVS & 1) << 11; + + /* Compute clocks per line based on panel type */ + switch (LCD_ConfigStruct->LCD) { + case LCD_MONO_4: + regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16); + break; + + case LCD_MONO_8: + regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16); + break; + + case LCD_CSTN: + regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16); + break; + + case LCD_TFT: + default: + regValue |= /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16); + } + + /* panel clock divisor */ + pcd = 5;// LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK + pcd &= 0x3FF; + regValue |= ((pcd >> 5) << 27) | ((pcd) & 0x1F); + pLCD->POL = regValue; + + /* disable interrupts */ + pLCD->INTMSK = 0; + + /* set bits per pixel */ + regValue = LCD_ConfigStruct->BPP << 1; + + /* set color format RGB */ + regValue |= LCD_ConfigStruct->color_format << 8; + regValue |= LCD_ConfigStruct->LCD << 4; + if (LCD_ConfigStruct->Dual == 1) { + regValue |= 1 << 7; + } + pLCD->CTRL = regValue; + + /* clear palette */ + pPal = (uint32_t *) (&(pLCD->PAL)); + for (i = 0; i < 128; i++) { + *pPal = 0; + pPal++; + } +} + +/* Shutdown the LCD controller */ +void Chip_LCD_DeInit(LPC_LCD_T *pLCD) +{ + Chip_Clock_Disable(CLK_MX_LCD); +} + +/* Configure Cursor */ +void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync) +{ + LCD_Cursor_Size = cursor_size; + pLCD->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size; +} + +/* Write Cursor Image into Internal Cursor Image Buffer */ +void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image) +{ + int i, j; + uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image; + + /* Check if Cursor Size was configured as 32x32 or 64x64*/ + if (LCD_Cursor_Size == LCD_CURSOR_32x32) { + i = cursor_num * 64; + j = i + 64; + } + else { + i = 0; + j = 256; + } + fifoptr = (void *) &(pLCD->CRSR_IMG[0]); + + /* Copy Cursor Image content to FIFO */ + for (; i < j; i++) { + + *fifoptr = *crsr_ptr; + crsr_ptr++; + fifoptr++; + } +} + +/* Load LCD Palette */ +void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette) +{ + LCD_PALETTE_ENTRY_T pal_entry = {0}; + uint8_t i, *pal_ptr; + /* This function supports loading of the color palette from + the C file generated by the bmp2c utility. It expects the + palette to be passed as an array of 32-bit BGR entries having + the following format: + 2:0 - Not used + 7:3 - Blue + 10:8 - Not used + 15:11 - Green + 18:16 - Not used + 23:19 - Red + 31:24 - Not used + arg = pointer to input palette table address */ + pal_ptr = (uint8_t *) palette; + + /* 256 entry in the palette table */ + for (i = 0; i < 256 / 2; i++) { + pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */ + pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */ + pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */ + pal_ptr++; /* skip over the unused byte */ + /* do the most significant halfword of the palette */ + pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */ + pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */ + pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */ + pal_ptr++; /* skip over the unused byte */ + + pLCD->PAL[i] = *((uint32_t *)&pal_entry); + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/otp_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/otp_18xx_43xx.c new file mode 100644 index 0000000000000..40558952d849c --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/otp_18xx_43xx.c @@ -0,0 +1,151 @@ +/* + * @brief LPC18xx/43xx OTP Controller driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define BOOTROM_BASE 0x10400100 +#define OTP_API_TABLE_OFFSET 0x1 + +static unsigned long *BOOTROM_API_TABLE; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +static uint32_t (*Otp_ProgBootSrc)(CHIP_OTP_BOOT_SRC_T BootSrc); +static uint32_t (*Otp_ProgJTAGDis)(void); +static uint32_t (*Otp_ProgUSBID)(uint32_t ProductID, uint32_t VendorID); +static uint32_t (*Otp_ProgGP0)(uint32_t Data, uint32_t Mask); +static uint32_t (*Otp_ProgGP1)(uint32_t Data, uint32_t Mask); +static uint32_t (*Otp_ProgGP2)(uint32_t Data, uint32_t Mask); +static uint32_t (*Otp_ProgKey1)(uint8_t *key); +static uint32_t (*Otp_ProgKey2)(uint8_t *key); +static uint32_t (*Otp_GenRand)(void); + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* CHIP OTP Initialisation function */ +uint32_t Chip_OTP_Init(void) +{ + uint32_t (*ROM_otp_Init)(void); + + BOOTROM_API_TABLE = *((unsigned long * *) BOOTROM_BASE + OTP_API_TABLE_OFFSET); + + ROM_otp_Init = (uint32_t (*)(void))BOOTROM_API_TABLE[0]; + Otp_ProgBootSrc = (uint32_t (*)(CHIP_OTP_BOOT_SRC_T BootSrc))BOOTROM_API_TABLE[1]; + Otp_ProgJTAGDis = (uint32_t (*)(void))BOOTROM_API_TABLE[2]; + Otp_ProgUSBID = (uint32_t (*)(uint32_t ProductID, uint32_t VendorID))BOOTROM_API_TABLE[3]; + Otp_ProgGP0 = (uint32_t (*)(uint32_t Data, uint32_t Mask))BOOTROM_API_TABLE[8]; + Otp_ProgGP1 = (uint32_t (*)(uint32_t Data, uint32_t Mask))BOOTROM_API_TABLE[9]; + Otp_ProgGP2 = (uint32_t (*)(uint32_t Data, uint32_t Mask))BOOTROM_API_TABLE[10]; + Otp_ProgKey1 = (uint32_t (*)(uint8_t *key))BOOTROM_API_TABLE[11]; + Otp_ProgKey2 = (uint32_t (*)(uint8_t *key))BOOTROM_API_TABLE[12]; + Otp_GenRand = (uint32_t (*)(void))BOOTROM_API_TABLE[13]; + + return ROM_otp_Init(); +} + +/* Program boot source in OTP Controller */ +uint32_t Chip_OTP_ProgBootSrc(CHIP_OTP_BOOT_SRC_T BootSrc) +{ + return Otp_ProgBootSrc(BootSrc); +} + +/* Program the JTAG bit in OTP Controller */ +uint32_t Chip_OTP_ProgJTAGDis(void) +{ + return Otp_ProgJTAGDis(); +} + +/* Program USB ID in OTP Controller */ +uint32_t Chip_OTP_ProgUSBID(uint32_t ProductID, uint32_t VendorID) +{ + return Otp_ProgUSBID(ProductID, VendorID); +} + +/* Program OTP GP Word memory */ +uint32_t Chip_OTP_ProgGPWord(uint32_t WordNum, uint32_t Data, uint32_t Mask) +{ + uint32_t status; + + switch (WordNum) { + case 1: + status = Otp_ProgGP1(Data, Mask); + break; + + case 2: + status = Otp_ProgGP2(Data, Mask); + break; + + case 0: + default: + status = Otp_ProgGP0(Data, Mask); + break; + } + + return status; +} + +/* Program AES Key */ +uint32_t Chip_OTP_ProgKey(uint32_t KeyNum, uint8_t *key) +{ + uint32_t status; + + if (KeyNum) { + status = Otp_ProgKey2(key); + } + else { + status = Otp_ProgKey1(key); + } + return status; +} + +/* Generate Random Number using HW Random Number Generator */ +uint32_t Chip_OTP_GenRand(void) +{ + return Otp_GenRand(); +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/pinint_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/pinint_18xx_43xx.c new file mode 100644 index 0000000000000..f725402e773eb --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/pinint_18xx_43xx.c @@ -0,0 +1,54 @@ +/* + * @brief LPC18xx/43xx Pin Interrupt and Pattern Match driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/pmc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/pmc_18xx_43xx.c new file mode 100644 index 0000000000000..fcc3615a7c37f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/pmc_18xx_43xx.c @@ -0,0 +1,75 @@ +/* + * @brief LPC18xx/43xx Power Management Controller driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set to sleep mode */ +void Chip_PMC_Sleep(void) +{ + /* Sleep Mode*/ + __WFI(); +} + +/* Set power state */ +void Chip_PMC_Set_PwrState(CHIP_PMC_PWR_STATE_T PwrState) +{ + + /* Set Deep sleep mode bit in System Control register of M4 core */ + SCB->SCR = 0x4; + + /* Set power state in PMC */ + LPC_PMC->PD0_SLEEP0_MODE = (uint32_t) PwrState; + + __WFI(); +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/ring_buffer.c b/ports/lpc/chips/lpc_chip_43xx/src/ring_buffer.c new file mode 100644 index 0000000000000..e2d2010d58c89 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/ring_buffer.c @@ -0,0 +1,173 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include +#include "ring_buffer.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1)) +#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1)) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize ring buffer */ +int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count) +{ + RingBuff->data = buffer; + RingBuff->count = count; + RingBuff->itemSz = itemSize; + RingBuff->head = RingBuff->tail = 0; + + return 1; +} + +/* Insert a single item into Ring Buffer */ +int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data) +{ + uint8_t *ptr = RingBuff->data; + + /* We cannot insert when queue is full */ + if (RingBuffer_IsFull(RingBuff)) + return 0; + + ptr += RB_INDH(RingBuff) * RingBuff->itemSz; + memcpy(ptr, data, RingBuff->itemSz); + RingBuff->head++; + + return 1; +} + +/* Insert multiple items into Ring Buffer */ +int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num) +{ + uint8_t *ptr = RingBuff->data; + int cnt1, cnt2; + + /* We cannot insert when queue is full */ + if (RingBuffer_IsFull(RingBuff)) + return 0; + + /* Calculate the segment lengths */ + cnt1 = cnt2 = RingBuffer_GetFree(RingBuff); + if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count) + cnt1 = RingBuff->count - RB_INDH(RingBuff); + cnt2 -= cnt1; + + cnt1 = MIN(cnt1, num); + num -= cnt1; + + cnt2 = MIN(cnt2, num); + num -= cnt2; + + /* Write segment 1 */ + ptr += RB_INDH(RingBuff) * RingBuff->itemSz; + memcpy(ptr, data, cnt1 * RingBuff->itemSz); + RingBuff->head += cnt1; + + /* Write segment 2 */ + ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz; + data = (const uint8_t *) data + cnt1 * RingBuff->itemSz; + memcpy(ptr, data, cnt2 * RingBuff->itemSz); + RingBuff->head += cnt2; + + return cnt1 + cnt2; +} + +/* Pop single item from Ring Buffer */ +int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data) +{ + uint8_t *ptr = RingBuff->data; + + /* We cannot pop when queue is empty */ + if (RingBuffer_IsEmpty(RingBuff)) + return 0; + + ptr += RB_INDT(RingBuff) * RingBuff->itemSz; + memcpy(data, ptr, RingBuff->itemSz); + RingBuff->tail++; + + return 1; +} + +/* Pop multiple items from Ring buffer */ +int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num) +{ + uint8_t *ptr = RingBuff->data; + int cnt1, cnt2; + + /* We cannot insert when queue is empty */ + if (RingBuffer_IsEmpty(RingBuff)) + return 0; + + /* Calculate the segment lengths */ + cnt1 = cnt2 = RingBuffer_GetCount(RingBuff); + if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count) + cnt1 = RingBuff->count - RB_INDT(RingBuff); + cnt2 -= cnt1; + + cnt1 = MIN(cnt1, num); + num -= cnt1; + + cnt2 = MIN(cnt2, num); + num -= cnt2; + + /* Write segment 1 */ + ptr += RB_INDT(RingBuff) * RingBuff->itemSz; + memcpy(data, ptr, cnt1 * RingBuff->itemSz); + RingBuff->tail += cnt1; + + /* Write segment 2 */ + ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz; + data = (uint8_t *) data + cnt1 * RingBuff->itemSz; + memcpy(data, ptr, cnt2 * RingBuff->itemSz); + RingBuff->tail += cnt2; + + return cnt1 + cnt2; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/ritimer_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/ritimer_18xx_43xx.c new file mode 100644 index 0000000000000..7e981fb6a82ca --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/ritimer_18xx_43xx.c @@ -0,0 +1,103 @@ +/* + * @brief LPC18xx/43xx RITimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the RIT */ +void Chip_RIT_Init(LPC_RITIMER_T *pRITimer) +{ + Chip_Clock_EnableOpts(CLK_MX_RITIMER, true, true, 1); + pRITimer->COMPVAL = 0xFFFFFFFF; + pRITimer->MASK = 0x00000000; + pRITimer->CTRL = 0x0C; + pRITimer->COUNTER = 0x00000000; +} + +/* DeInitialize the RIT */ +void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer) +{ + Chip_RIT_Init(pRITimer); + Chip_Clock_Disable(CLK_MX_RITIMER); +} + +/* Set timer interval value */ +void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval) +{ + uint32_t cmp_value; + + /* Determine aapproximate compare value based on clock rate and passed interval */ + cmp_value = (Chip_Clock_GetRate(CLK_MX_RITIMER) / 1000) * time_interval; + + /* Set timer compare value */ + Chip_RIT_SetCOMPVAL(pRITimer, cmp_value); + + /* Set timer enable clear bit to clear timer to 0 whenever + counter value equals the contents of RICOMPVAL */ + Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR); +} + +/* Check whether interrupt is pending */ +IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer) +{ + uint8_t result; + + if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) { + result = SET; + } + else { + return RESET; + } + + return (IntStatus) result; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/rtc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/rtc_18xx_43xx.c new file mode 100644 index 0000000000000..1ab2b6c1600e8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/rtc_18xx_43xx.c @@ -0,0 +1,226 @@ +/* + * @brief LPC18xx/43xx RTC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the RTC peripheral */ +void Chip_RTC_Init(LPC_RTC_T *pRTC) +{ + Chip_Clock_RTCEnable(); + + /* 2-Second delay after enabling RTC clock */ + LPC_ATIMER->DOWNCOUNTER = 2048; + while (LPC_ATIMER->DOWNCOUNTER); + + /* Disable RTC */ + Chip_RTC_Enable(pRTC, DISABLE); + + /* Disable Calibration */ + Chip_RTC_CalibCounterCmd(pRTC, DISABLE); + + /* Reset RTC Clock */ + Chip_RTC_ResetClockTickCounter(pRTC); + + /* Clear counter increment and alarm interrupt */ + pRTC->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF; + while (pRTC->ILR != 0) {} + + /* Clear all register to be default */ + pRTC->CIIR = 0x00; + pRTC->AMR = 0xFF; + pRTC->CALIBRATION = 0x00; +} + +/*De-initialize the RTC peripheral */ +void Chip_RTC_DeInit(LPC_RTC_T *pRTC) +{ + pRTC->CCR = 0x00; +} + +/* Reset clock tick counter in the RTC peripheral */ +void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC) +{ + /* Reset RTC clock*/ + pRTC->CCR |= RTC_CCR_CTCRST; + while (!(pRTC->CCR & RTC_CCR_CTCRST)) {} + + /* Finish resetting RTC clock */ + pRTC->CCR = (pRTC->CCR & ~RTC_CCR_CTCRST) & RTC_CCR_BITMASK; + while (pRTC->CCR & RTC_CCR_CTCRST) {} +} + +/* Start/Stop RTC peripheral */ +void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pRTC->CCR |= RTC_CCR_CLKEN; + } else { + pRTC->CCR = (pRTC->CCR & ~RTC_CCR_CLKEN) & RTC_CCR_BITMASK; + } +} + +/* Enable/Disable Counter increment interrupt for a time type in the RTC peripheral */ +void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pRTC->CIIR |= cntrMask; + } + + else { + pRTC->CIIR &= (~cntrMask) & RTC_AMR_CIIR_BITMASK; + while (pRTC->CIIR & cntrMask) {} + } +} + +/* Enable/Disable Alarm interrupt for a time type in the RTC peripheral */ +void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pRTC->AMR &= (~alarmMask) & RTC_AMR_CIIR_BITMASK; + } + else { + pRTC->AMR |= (alarmMask); + while ((pRTC->AMR & alarmMask) == 0) {} + } +} + +/* Set full time in the RTC peripheral */ +void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime) +{ + RTC_TIMEINDEX_T i; + uint32_t ccr_val = pRTC->CCR; + + /* Temporarily disable */ + if (ccr_val & RTC_CCR_CLKEN) { + pRTC->CCR = ccr_val & (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK; + } + + /* Date time setting */ + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pRTC->TIME[i] = pFullTime->time[i]; + } + + /* Restore to old setting */ + pRTC->CCR = ccr_val; +} + +/* Get full time from the RTC peripheral */ +void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime) +{ + RTC_TIMEINDEX_T i; + uint32_t secs = 0xFF; + + /* Read full time, but verify second tick didn't change during the read. If + it did, re-read the time again so it will be consistent across all fields. */ + while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) { + secs = pFullTime->time[RTC_TIMETYPE_SECOND] = pRTC->TIME[RTC_TIMETYPE_SECOND]; + for (i = RTC_TIMETYPE_MINUTE; i < RTC_TIMETYPE_LAST; i++) { + pFullTime->time[i] = pRTC->TIME[i]; + } + } +} + +/* Set full alarm time in the RTC peripheral */ +void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime) +{ + RTC_TIMEINDEX_T i; + + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pRTC->ALRM[i] = pFullTime->time[i]; + } +} + +/* Get full alarm time in the RTC peripheral */ +void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime) +{ + RTC_TIMEINDEX_T i; + + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pFullTime->time[i] = pRTC->ALRM[i]; + } +} + +/* Enable/Disable calibration counter in the RTC peripheral */ +void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState) +{ + if (NewState == ENABLE) { + do { + pRTC->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK; + } while (pRTC->CCR & RTC_CCR_CCALEN); + } + else { + pRTC->CCR |= RTC_CCR_CCALEN; + } +} + +#if RTC_EV_SUPPORT +/* Get first timestamp value */ +void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp) +{ + pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERFIRSTSTAMP[ch]); + pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERFIRSTSTAMP[ch]); + pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERFIRSTSTAMP[ch]); + pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERFIRSTSTAMP[ch]); +} + +/* Get last timestamp value */ +void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp) +{ + pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERLASTSTAMP[ch]); + pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERLASTSTAMP[ch]); + pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERLASTSTAMP[ch]); + pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERLASTSTAMP[ch]); +} + +#endif /*RTC_EV_SUPPORT*/ + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/sct_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/sct_18xx_43xx.c new file mode 100644 index 0000000000000..410f9507150e8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/sct_18xx_43xx.c @@ -0,0 +1,93 @@ +/* + * @brief LPC18xx/43xx State Configurable Timer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize SCT */ +void Chip_SCT_Init(LPC_SCT_T *pSCT) +{ + Chip_Clock_EnableOpts(CLK_MX_SCT, true, true, 1); +} + +/* Shutdown SCT */ +void Chip_SCT_DeInit(LPC_SCT_T *pSCT) +{ + Chip_Clock_Disable(CLK_MX_SCT); +} + +/* Set/Clear SCT control register */ +void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena) +{ + uint32_t tem; + + tem = pSCT->CTRL_U; + if (ena == ENABLE) { + tem |= value; + } + else { + tem &= (~value); + } + pSCT->CTRL_U = tem; +} + +/* Set Conflict resolution */ +void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value) +{ + uint32_t tem; + + tem = pSCT->RES; + tem &= ~(0x03 << (2 * outnum)); + tem |= (value << (2 * outnum)); + pSCT->RES = tem; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/sct_pwm_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/sct_pwm_18xx_43xx.c new file mode 100644 index 0000000000000..267c636d31d34 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/sct_pwm_18xx_43xx.c @@ -0,0 +1,93 @@ +/* + * @brief LPC18xx_43xx State Configurable Timer PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Setup the OUTPUT pin corresponding to the PWM index */ +void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin) +{ + int ix = (int) index; + pSCT->EVENT[ix].CTRL = index | (1 << 12); + pSCT->EVENT[ix].STATE = 1; + pSCT->OUT[pin].SET = 1; + pSCT->OUT[pin].CLR = 1 << ix; + + /* Clear the output in-case of conflict */ + pSCT->RES = (pSCT->RES & ~(3 << (pin << 1))) | (0x01 << (pin << 1)); + + /* Set and Clear do not depend on direction */ + pSCT->OUTPUTDIRCTRL = (pSCT->OUTPUTDIRCTRL & ~(3 << (pin << 1))); +} + +/* Set the PWM frequency */ +void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq) +{ + uint32_t rate; + + rate = Chip_Clock_GetRate(CLK_MX_SCT) / freq;; + + /* Stop the SCT before configuration */ + Chip_SCTPWM_Stop(pSCT); + + /* Set MATCH0 for max limit */ + pSCT->REGMODE_L = 0; + pSCT->REGMODE_H = 0; + Chip_SCT_SetMatchCount(pSCT, SCT_MATCH_0, 0); + Chip_SCT_SetMatchReload(pSCT, SCT_MATCH_0, rate); + pSCT->EVENT[0].CTRL = 1 << 12; + pSCT->EVENT[0].STATE = 1; + pSCT->LIMIT_L = 1; + + /* Set SCT Counter to count 32-bits and reset to 0 after reaching MATCH0 */ + Chip_SCT_Config(pSCT, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L); +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/sdif_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/sdif_18xx_43xx.c new file mode 100644 index 0000000000000..6d9de6be318e6 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/sdif_18xx_43xx.c @@ -0,0 +1,229 @@ +/* + * @brief LPC18xx/43xx SD/SDIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "string.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the SD/MMC controller */ +void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC) +{ + /* Enable SDIO module clock */ + Chip_Clock_EnableOpts(CLK_MX_SDIO, true, true, 1); + + /* Software reset */ + pSDMMC->BMOD = MCI_BMOD_SWR; + + /* reset all blocks */ + pSDMMC->CTRL = MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET; + while (pSDMMC->CTRL & (MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET)) {} + + /* Internal DMA setup for control register */ + pSDMMC->CTRL = MCI_CTRL_USE_INT_DMAC | MCI_CTRL_INT_ENABLE; + pSDMMC->INTMASK = 0; + + /* Clear the interrupts for the host controller */ + pSDMMC->RINTSTS = 0xFFFFFFFF; + + /* Put in max timeout */ + pSDMMC->TMOUT = 0xFFFFFFFF; + + /* FIFO threshold settings for DMA, DMA burst of 4, FIFO watermark at 16 */ + pSDMMC->FIFOTH = MCI_FIFOTH_DMA_MTS_4 | MCI_FIFOTH_RX_WM((SD_FIFO_SZ / 2) - 1) | MCI_FIFOTH_TX_WM(SD_FIFO_SZ / 2); + + /* Enable internal DMA, burst size of 4, fixed burst */ + pSDMMC->BMOD = MCI_BMOD_DE | MCI_BMOD_PBL4 | MCI_BMOD_DSL(4); + + /* disable clock to CIU (needs latch) */ + pSDMMC->CLKENA = 0; + pSDMMC->CLKSRC = 0; +} + +/* Shutdown the SD/MMC controller */ +void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC) +{ + /* Disable the clock */ + Chip_Clock_Disable(CLK_MX_SDIO); +} + +/* Function to send command to Card interface unit (CIU) */ +int32_t Chip_SDIF_SendCmd(LPC_SDMMC_T *pSDMMC, uint32_t cmd, uint32_t arg) +{ + volatile int32_t tmo = 50; + volatile int delay; + + /* set command arg reg*/ + pSDMMC->CMDARG = arg; + pSDMMC->CMD = MCI_CMD_START | cmd; + + /* poll untill command is accepted by the CIU */ + while (--tmo && (pSDMMC->CMD & MCI_CMD_START)) { + if (tmo & 1) { + delay = 50; + } + else { + delay = 18000; + } + + while (--delay > 1) {} + } + + return (tmo < 1) ? 1 : 0; +} + +/* Read the response from the last command */ +void Chip_SDIF_GetResponse(LPC_SDMMC_T *pSDMMC, uint32_t *resp) +{ + /* on this chip response is not a fifo so read all 4 regs */ + resp[0] = pSDMMC->RESP0; + resp[1] = pSDMMC->RESP1; + resp[2] = pSDMMC->RESP2; + resp[3] = pSDMMC->RESP3; +} + +/* Sets the SD bus clock speed */ +void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed) +{ + /* compute SD/MMC clock dividers */ + uint32_t div; + + div = ((clk_rate / speed) + 2) >> 1; + + if ((div == pSDMMC->CLKDIV) && pSDMMC->CLKENA) { + return; /* Closest speed is already set */ + + } + /* disable clock */ + pSDMMC->CLKENA = 0; + + /* User divider 0 */ + pSDMMC->CLKSRC = MCI_CLKSRC_CLKDIV0; + + /* inform CIU */ + Chip_SDIF_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); + + /* set divider 0 to desired value */ + pSDMMC->CLKDIV = MCI_CLOCK_DIVIDER(0, div); + + /* inform CIU */ + Chip_SDIF_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); + + /* enable clock */ + pSDMMC->CLKENA = MCI_CLKEN_ENABLE; + + /* inform CIU */ + Chip_SDIF_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); +} + +/* Function to clear interrupt & FIFOs */ +void Chip_SDIF_SetClearIntFifo(LPC_SDMMC_T *pSDMMC) +{ + /* reset all blocks */ + pSDMMC->CTRL |= MCI_CTRL_FIFO_RESET; + + /* wait till resets clear */ + while (pSDMMC->CTRL & MCI_CTRL_FIFO_RESET) {} + + /* Clear interrupt status */ + pSDMMC->RINTSTS = 0xFFFFFFFF; +} + +/* Setup DMA descriptors */ +void Chip_SDIF_DmaSetup(LPC_SDMMC_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size) +{ + int i = 0; + uint32_t ctrl, maxs; + + /* Reset DMA */ + pSDMMC->CTRL |= MCI_CTRL_DMA_RESET | MCI_CTRL_FIFO_RESET; + while (pSDMMC->CTRL & MCI_CTRL_DMA_RESET) {} + + /* Build a descriptor list using the chained DMA method */ + while (size > 0) { + /* Limit size of the transfer to maximum buffer size */ + maxs = size; + if (maxs > MCI_DMADES1_MAXTR) { + maxs = MCI_DMADES1_MAXTR; + } + size -= maxs; + + /* Set buffer size */ + psdif_dev->mci_dma_dd[i].des1 = MCI_DMADES1_BS1(maxs); + + /* Setup buffer address (chained) */ + psdif_dev->mci_dma_dd[i].des2 = addr + (i * MCI_DMADES1_MAXTR); + + /* Setup basic control */ + ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH; + if (i == 0) { + ctrl |= MCI_DMADES0_FS; /* First DMA buffer */ + + } + /* No more data? Then this is the last descriptor */ + if (!size) { + ctrl |= MCI_DMADES0_LD; + } + else { + ctrl |= MCI_DMADES0_DIC; + } + + /* Another descriptor is needed */ + psdif_dev->mci_dma_dd[i].des3 = (uint32_t) &psdif_dev->mci_dma_dd[i + 1]; + psdif_dev->mci_dma_dd[i].des0 = ctrl; + + i++; + } + + /* Set DMA derscriptor base address */ + pSDMMC->DBADDR = (uint32_t) &psdif_dev->mci_dma_dd[0]; +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/sdmmc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/sdmmc_18xx_43xx.c new file mode 100644 index 0000000000000..58c767534de79 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/sdmmc_18xx_43xx.c @@ -0,0 +1,598 @@ +/* + * @brief LPC18xx/43xx SD/SDIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "string.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Global instance of the current card */ +static mci_card_struct *g_card_info; + +/* Helper definition: all SD error conditions in the status word */ +#define SD_INT_ERROR (MCI_INT_RESP_ERR | MCI_INT_RCRC | MCI_INT_DCRC | \ + MCI_INT_RTO | MCI_INT_DTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE | \ + MCI_INT_SBE | MCI_INT_EBE) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Function to execute a command */ +static int32_t sdmmc_execute_command(LPC_SDMMC_T *pSDMMC, uint32_t cmd, uint32_t arg, uint32_t wait_status) +{ + int32_t step = (cmd & CMD_BIT_APP) ? 2 : 1; + int32_t status = 0; + uint32_t cmd_reg = 0; + + if (!wait_status) { + wait_status = (cmd & CMD_MASK_RESP) ? MCI_INT_CMD_DONE : MCI_INT_DATA_OVER; + } + + /* Clear the interrupts & FIFOs*/ + if (cmd & CMD_BIT_DATA) { + Chip_SDIF_SetClearIntFifo(pSDMMC); + } + + /* also check error conditions */ + wait_status |= MCI_INT_EBE | MCI_INT_SBE | MCI_INT_HLE | MCI_INT_RTO | MCI_INT_RCRC | MCI_INT_RESP_ERR; + if (wait_status & MCI_INT_DATA_OVER) { + wait_status |= MCI_INT_FRUN | MCI_INT_HTO | MCI_INT_DTO | MCI_INT_DCRC; + } + + while (step) { + Chip_SDIF_SetClock(pSDMMC, Chip_Clock_GetBaseClocktHz(CLK_BASE_SDIO), g_card_info->card_info.speed); + + /* Clear the interrupts */ + Chip_SDIF_ClrIntStatus(pSDMMC, 0xFFFFFFFF); + + g_card_info->card_info.evsetup_cb((void *) &wait_status); + + switch (step) { + case 1: /* Execute command */ + cmd_reg = ((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) | + ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) | + ((cmd & CMD_BIT_DATA) ? (MCI_CMD_DAT_EXP | MCI_CMD_PRV_DAT_WAIT) : 0) | + (((cmd & CMD_MASK_RESP) == CMD_RESP_R2) ? MCI_CMD_RESP_LONG : 0) | + ((cmd & CMD_MASK_RESP) ? MCI_CMD_RESP_EXP : 0) | + ((cmd & CMD_BIT_WRITE) ? MCI_CMD_DAT_WR : 0) | + ((cmd & CMD_BIT_STREAM) ? MCI_CMD_STRM_MODE : 0) | + ((cmd & CMD_BIT_BUSY) ? MCI_CMD_STOP : 0) | + ((cmd & CMD_BIT_AUTO_STOP) ? MCI_CMD_SEND_STOP : 0) | + MCI_CMD_START; + + /* wait for previos data finsh for select/deselect commands */ + if (((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) == MMC_SELECT_CARD) { + cmd_reg |= MCI_CMD_PRV_DAT_WAIT; + } + + /* wait for command to be accepted by CIU */ + if (Chip_SDIF_SendCmd(pSDMMC, cmd_reg, arg) == 0) { + --step; + } + break; + + case 0: + return 0; + + case 2: /* APP prefix */ + cmd_reg = MMC_APP_CMD | MCI_CMD_RESP_EXP | + ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) | + MCI_CMD_START; + + if (Chip_SDIF_SendCmd(pSDMMC, cmd_reg, g_card_info->card_info.rca << 16) == 0) { + --step; + } + break; + } + + /* wait for command response */ + status = g_card_info->card_info.waitfunc_cb(); + + /* We return an error if there is a timeout, even if we've fetched a response */ + if (status & SD_INT_ERROR) { + return status; + } + + if (status & MCI_INT_CMD_DONE) { + switch (cmd & CMD_MASK_RESP) { + case 0: + break; + + case CMD_RESP_R1: + case CMD_RESP_R3: + case CMD_RESP_R2: + Chip_SDIF_GetResponse(pSDMMC, &g_card_info->card_info.response[0]); + break; + } + } + } + + return 0; +} + +/* Checks whether card is acquired properly or not */ +static int32_t prv_card_acquired(void) +{ + return g_card_info->card_info.cid[0] != 0; +} + +/* Helper function to get a bit field withing multi-word buffer. Used to get + fields with-in CSD & EXT-CSD */ +static uint32_t prv_get_bits(int32_t start, int32_t end, uint32_t *data) +{ + uint32_t v; + uint32_t i = end >> 5; + uint32_t j = start & 0x1f; + + if (i == (start >> 5)) { + v = (data[i] >> j); + } + else { + v = ((data[i] << (32 - j)) | (data[start >> 5] >> j)); + } + + return v & ((1 << (end - start + 1)) - 1); +} + +/* Function to process the CSD & EXT-CSD of the card */ +static void prv_process_csd(LPC_SDMMC_T *pSDMMC) +{ + int32_t status = 0; + int32_t c_size = 0; + int32_t c_size_mult = 0; + int32_t mult = 0; + + /* compute block length based on CSD response */ + g_card_info->card_info.block_len = 1 << prv_get_bits(80, 83, g_card_info->card_info.csd); + + if ((g_card_info->card_info.card_type & CARD_TYPE_HC) && (g_card_info->card_info.card_type & CARD_TYPE_SD)) { + /* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec an explanation for the calculation of these values */ + c_size = prv_get_bits(48, 69, (uint32_t *) g_card_info->card_info.csd) + 1; + g_card_info->card_info.blocknr = c_size << 10; /* 512 byte blocks */ + } + else { + /* See section 5.3 of the 4.1 revision of the MMC specs for an explanation for the calculation of these values */ + c_size = prv_get_bits(62, 73, (uint32_t *) g_card_info->card_info.csd); + c_size_mult = prv_get_bits(47, 49, (uint32_t *) g_card_info->card_info.csd); + mult = 1 << (c_size_mult + 2); + g_card_info->card_info.blocknr = (c_size + 1) * mult; + + /* adjust blocknr to 512/block */ + if (g_card_info->card_info.block_len > MMC_SECTOR_SIZE) { + g_card_info->card_info.blocknr = g_card_info->card_info.blocknr * (g_card_info->card_info.block_len >> 9); + } + + /* get extended CSD for newer MMC cards CSD spec >= 4.0*/ + if (((g_card_info->card_info.card_type & CARD_TYPE_SD) == 0) && + (prv_get_bits(122, 125, (uint32_t *) g_card_info->card_info.csd) >= 4)) { + /* put card in trans state */ + status = sdmmc_execute_command(pSDMMC, CMD_SELECT_CARD, g_card_info->card_info.rca << 16, 0); + + /* set block size and byte count */ + Chip_SDIF_SetBlkSizeByteCnt(pSDMMC, MMC_SECTOR_SIZE); + + /* send EXT_CSD command */ + Chip_SDIF_DmaSetup(pSDMMC, + &g_card_info->sdif_dev, + (uint32_t) g_card_info->card_info.ext_csd, + MMC_SECTOR_SIZE); + + status = sdmmc_execute_command(pSDMMC, CMD_SEND_EXT_CSD, 0, 0 | MCI_INT_DATA_OVER); + if ((status & SD_INT_ERROR) == 0) { + /* check EXT_CSD_VER is greater than 1.1 */ + if ((g_card_info->card_info.ext_csd[48] & 0xFF) > 1) { + g_card_info->card_info.blocknr = g_card_info->card_info.ext_csd[53];/* bytes 212:215 represent sec count */ + + } + /* switch to 52MHz clock if card type is set to 1 or else set to 26MHz */ + if ((g_card_info->card_info.ext_csd[49] & 0xFF) == 1) { + /* for type 1 MMC cards high speed is 52MHz */ + g_card_info->card_info.speed = MMC_HIGH_BUS_MAX_CLOCK; + } + else { + /* for type 0 MMC cards high speed is 26MHz */ + g_card_info->card_info.speed = MMC_LOW_BUS_MAX_CLOCK; + } + } + } + } + + g_card_info->card_info.device_size = (uint64_t) g_card_info->card_info.blocknr << 9; /* blocknr * 512 */ +} + +/* Puts current selected card in trans state */ +static int32_t prv_set_trans_state(LPC_SDMMC_T *pSDMMC) +{ + uint32_t status; + + /* get current state of the card */ + status = sdmmc_execute_command(pSDMMC, CMD_SEND_STATUS, g_card_info->card_info.rca << 16, 0); + if (status & MCI_INT_RTO) { + /* unable to get the card state. So return immediatly. */ + return -1; + } + + /* check card state in response */ + status = R1_CURRENT_STATE(g_card_info->card_info.response[0]); + switch (status) { + case SDMMC_STBY_ST: + /* put card in 'Trans' state */ + status = sdmmc_execute_command(pSDMMC, CMD_SELECT_CARD, g_card_info->card_info.rca << 16, 0); + if (status != 0) { + /* unable to put the card in Trans state. So return immediatly. */ + return -1; + } + break; + + case SDMMC_TRAN_ST: + /*do nothing */ + break; + + default: + /* card shouldn't be in other states so return */ + return -1; + } + + return 0; +} + +/* Sets card data width and block size */ +static int32_t prv_set_card_params(LPC_SDMMC_T *pSDMMC) +{ + int32_t status; + +#if SDIO_BUS_WIDTH > 1 + if (g_card_info->card_info.card_type & CARD_TYPE_SD) { + status = sdmmc_execute_command(pSDMMC, CMD_SD_SET_WIDTH, 2, 0); + if (status != 0) { + return -1; + } + + /* if positive response */ + Chip_SDIF_SetCardType(pSDMMC, MCI_CTYPE_4BIT); + } +#elif SDIO_BUS_WIDTH > 4 +#error 8-bit mode not supported yet! +#endif + + /* set block length */ + Chip_SDIF_SetBlkSize(pSDMMC, MMC_SECTOR_SIZE); + status = sdmmc_execute_command(pSDMMC, CMD_SET_BLOCKLEN, MMC_SECTOR_SIZE, 0); + if (status != 0) { + return -1; + } + + return 0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ +/* Get card's current state (idle, transfer, program, etc.) */ +int32_t Chip_SDMMC_GetState(LPC_SDMMC_T *pSDMMC) +{ + uint32_t status; + + /* get current state of the card */ + status = sdmmc_execute_command(pSDMMC, CMD_SEND_STATUS, g_card_info->card_info.rca << 16, 0); + if (status & MCI_INT_RTO) { + return -1; + } + + /* check card state in response */ + return (int32_t) R1_CURRENT_STATE(g_card_info->card_info.response[0]); +} + +/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */ +uint32_t Chip_SDMMC_Acquire(LPC_SDMMC_T *pSDMMC, mci_card_struct *pcardinfo) +{ + int32_t status; + int32_t tries = 0; + uint32_t ocr = OCR_VOLTAGE_RANGE_MSK; + uint32_t r; + int32_t state = 0; + uint32_t command = 0; + + g_card_info = pcardinfo; + + /* clear card type */ + Chip_SDIF_SetCardType(pSDMMC, 0); + + /* set high speed for the card as 20MHz */ + g_card_info->card_info.speed = MMC_MAX_CLOCK; + + status = sdmmc_execute_command(pSDMMC, CMD_IDLE, 0, MCI_INT_CMD_DONE); + + while (state < 100) { + switch (state) { + case 0: /* Setup for SD */ + /* check if it is SDHC card */ + status = sdmmc_execute_command(pSDMMC, CMD_SD_SEND_IF_COND, SD_SEND_IF_ARG, 0); + if (!(status & MCI_INT_RTO)) { + /* check response has same echo pattern */ + if ((g_card_info->card_info.response[0] & SD_SEND_IF_ECHO_MSK) == SD_SEND_IF_RESP) { + ocr |= OCR_HC_CCS; + } + } + + ++state; + command = CMD_SD_OP_COND; + tries = INIT_OP_RETRIES; + + /* assume SD card */ + g_card_info->card_info.card_type |= CARD_TYPE_SD; + g_card_info->card_info.speed = SD_MAX_CLOCK; + break; + + case 10: /* Setup for MMC */ + /* start fresh for MMC crds */ + g_card_info->card_info.card_type &= ~CARD_TYPE_SD; + status = sdmmc_execute_command(pSDMMC, CMD_IDLE, 0, MCI_INT_CMD_DONE); + command = CMD_MMC_OP_COND; + tries = INIT_OP_RETRIES; + ocr |= OCR_HC_CCS; + ++state; + + /* for MMC cards high speed is 20MHz */ + g_card_info->card_info.speed = MMC_MAX_CLOCK; + break; + + case 1: + case 11: + status = sdmmc_execute_command(pSDMMC, command, 0, 0); + if (status & MCI_INT_RTO) { + state += 9; /* Mode unavailable */ + } + else { + ++state; + } + break; + + case 2: /* Initial OCR check */ + case 12: + ocr = g_card_info->card_info.response[0] | (ocr & OCR_HC_CCS); + if (ocr & OCR_ALL_READY) { + ++state; + } + else { + state += 2; + } + break; + + case 3: /* Initial wait for OCR clear */ + case 13: + while ((ocr & OCR_ALL_READY) && --tries > 0) { + g_card_info->card_info.msdelay_func(MS_ACQUIRE_DELAY); + status = sdmmc_execute_command(pSDMMC, command, 0, 0); + ocr = g_card_info->card_info.response[0] | (ocr & OCR_HC_CCS); + } + if (ocr & OCR_ALL_READY) { + state += 7; + } + else { + ++state; + } + break; + + case 14: + /* for MMC cards set high capacity bit */ + ocr |= OCR_HC_CCS; + + case 4: /* Assign OCR */ + tries = SET_OP_RETRIES; + ocr &= OCR_VOLTAGE_RANGE_MSK | OCR_HC_CCS; /* Mask for the bits we care about */ + do { + g_card_info->card_info.msdelay_func(MS_ACQUIRE_DELAY); + status = sdmmc_execute_command(pSDMMC, command, ocr, 0); + r = g_card_info->card_info.response[0]; + } while (!(r & OCR_ALL_READY) && --tries > 0); + + if (r & OCR_ALL_READY) { + /* is it high capacity card */ + g_card_info->card_info.card_type |= (r & OCR_HC_CCS); + ++state; + } + else { + state += 6; + } + break; + + case 5: /* CID polling */ + case 15: + status = sdmmc_execute_command(pSDMMC, CMD_ALL_SEND_CID, 0, 0); + memcpy(&g_card_info->card_info.cid, &g_card_info->card_info.response[0], 16); + ++state; + break; + + case 6: /* RCA send, for SD get RCA */ + status = sdmmc_execute_command(pSDMMC, CMD_SD_SEND_RCA, 0, 0); + g_card_info->card_info.rca = (g_card_info->card_info.response[0]) >> 16; + ++state; + break; + + case 16: /* RCA assignment for MMC set to 1 */ + g_card_info->card_info.rca = 1; + status = sdmmc_execute_command(pSDMMC, CMD_MMC_SET_RCA, g_card_info->card_info.rca << 16, 0); + ++state; + break; + + case 7: + case 17: + status = sdmmc_execute_command(pSDMMC, CMD_SEND_CSD, g_card_info->card_info.rca << 16, 0); + memcpy(&g_card_info->card_info.csd, &g_card_info->card_info.response[0], 16); + state = 100; + break; + + default: + state += 100; /* break from while loop */ + break; + } + } + + /* Compute card size, block size and no. of blocks based on CSD response recived. */ + if (prv_card_acquired()) { + prv_process_csd(pSDMMC); + + /* Setup card data width and block size (once) */ + if (prv_set_trans_state(pSDMMC) != 0) { + return 0; + } + if (prv_set_card_params(pSDMMC) != 0) { + return 0; + } + } + + return prv_card_acquired(); +} + +/* Get the device size of SD/MMC card (after enumeration) */ +uint64_t Chip_SDMMC_GetDeviceSize(LPC_SDMMC_T *pSDMMC) +{ + return g_card_info->card_info.device_size; +} + +/* Get the number of blocks in SD/MMC card (after enumeration) */ +int32_t Chip_SDMMC_GetDeviceBlocks(LPC_SDMMC_T *pSDMMC) +{ + return g_card_info->card_info.blocknr; +} + +/* Performs the read of data from the SD/MMC card */ +int32_t Chip_SDMMC_ReadBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks) +{ + int32_t cbRead = (num_blocks) * MMC_SECTOR_SIZE; + int32_t status = 0; + int32_t index; + + /* if card is not acquired return immediately */ + if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->card_info.blocknr) ) { + return 0; + } + + /* put card in trans state */ + if (prv_set_trans_state(pSDMMC) != 0) { + return 0; + } + + /* set number of bytes to read */ + Chip_SDIF_SetByteCnt(pSDMMC, cbRead); + + /* if high capacity card use block indexing */ + if (g_card_info->card_info.card_type & CARD_TYPE_HC) { + index = start_block; + } + else { /*fix at 512 bytes*/ + index = start_block << 9; // \* g_card_info->card_info.block_len; + + } + Chip_SDIF_DmaSetup(pSDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbRead); + + /* Select single or multiple read based on number of blocks */ + if (num_blocks == 1) { + status = sdmmc_execute_command(pSDMMC, CMD_READ_SINGLE, index, 0 | MCI_INT_DATA_OVER); + } + else { + status = sdmmc_execute_command(pSDMMC, CMD_READ_MULTIPLE, index, 0 | MCI_INT_DATA_OVER); + } + + if (status != 0) { + cbRead = 0; + } + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState(pSDMMC) != SDMMC_TRAN_ST) {} + + return cbRead; +} + +/* Performs write of data to the SD/MMC card */ +int32_t Chip_SDMMC_WriteBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks) +{ + int32_t cbWrote = num_blocks * MMC_SECTOR_SIZE; + int32_t status; + int32_t index; + + /* if card is not acquired return immediately */ + if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->card_info.blocknr) ) { + return 0; + } + + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState(pSDMMC) != SDMMC_TRAN_ST) {} + + /* put card in trans state */ + if (prv_set_trans_state(pSDMMC) != 0) { + return 0; + } + + /* set number of bytes to write */ + Chip_SDIF_SetByteCnt(pSDMMC, cbWrote); + + /* if high capacity card use block indexing */ + if (g_card_info->card_info.card_type & CARD_TYPE_HC) { + index = start_block; + } + else { /*fix at 512 bytes*/ + index = start_block << 9; // * g_card_info->card_info.block_len; + + } + + Chip_SDIF_DmaSetup(pSDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbWrote); + + /* Select single or multiple write based on number of blocks */ + if (num_blocks == 1) { + status = sdmmc_execute_command(pSDMMC, CMD_WRITE_SINGLE, index, 0 | MCI_INT_DATA_OVER); + } + else { + status = sdmmc_execute_command(pSDMMC, CMD_WRITE_MULTIPLE, index, 0 | MCI_INT_DATA_OVER); + } + + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState(pSDMMC) != SDMMC_TRAN_ST) {} + + if (status != 0) { + cbWrote = 0; + } + + return cbWrote; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c new file mode 100644 index 0000000000000..4f3b8d8e3bb01 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c @@ -0,0 +1,233 @@ +/* + * @brief LPC43xx SPI driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +#if defined(CHIP_LPC43XX) + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Execute callback function */ +STATIC void executeCallback(LPC_SPI_T *pSPI, SPI_CALLBACK_T pfunc) +{ + if (pfunc) { + (pfunc) (); + } +} + +/* Write byte(s) to FIFO buffer */ +STATIC void writeData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint32_t num_bytes) +{ + uint16_t data2write = 0xFFFF; + + if ( pXfSetup->pTxData) { + data2write = pXfSetup->pTxData[pXfSetup->cnt]; + if (num_bytes == 2) { + data2write |= pXfSetup->pTxData[pXfSetup->cnt + 1] << 8; + } + } + + Chip_SPI_SendFrame(pSPI, data2write); + +} + +/* Read byte(s) from FIFO buffer */ +STATIC void readData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint16_t rDat, uint32_t num_bytes) +{ + rDat = Chip_SPI_ReceiveFrame(pSPI); + if (pXfSetup->pRxData) { + pXfSetup->pRxData[pXfSetup->cnt] = rDat; + if (num_bytes == 2) { + pXfSetup->pRxData[pXfSetup->cnt + 1] = rDat >> 8; + } + } +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* SPI Polling Read/Write in blocking mode */ +uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) +{ + uint32_t status; + uint16_t rDat = 0x0000; + uint8_t bytes = 1; + + /* Clear status */ + Chip_SPI_Int_FlushData(pSPI); + + if (Chip_SPI_GetDataSize(pSPI) != SPI_BITS_8) { + bytes = 2; + } + + executeCallback(pSPI, pXfSetup->fnBefTransfer); + + while (pXfSetup->cnt < pXfSetup->length) { + + executeCallback(pSPI, pXfSetup->fnBefFrame); + + /* write data to buffer */ + writeData(pSPI, pXfSetup, bytes); + + /* Wait for transfer completes */ + while (1) { + status = Chip_SPI_GetStatus(pSPI); + /* Check error */ + if (status & SPI_SR_ERROR) { + goto rw_end; + } + if (status & SPI_SR_SPIF) { + break; + } + } + + executeCallback(pSPI, pXfSetup->fnAftFrame); + + /* Read data*/ + readData(pSPI, pXfSetup, rDat, bytes); + pXfSetup->cnt += bytes; + } + +rw_end: + executeCallback(pSPI, pXfSetup->fnAftTransfer); + return pXfSetup->cnt; +} + +/* Clean all data in RX FIFO of SPI */ +void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI) +{ + volatile uint32_t tmp; + Chip_SPI_GetStatus(pSPI); + tmp = Chip_SPI_ReceiveFrame(pSPI); + Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF); +} + +/* SPI Interrupt Read/Write with 8-bit frame width */ +Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint8_t bytes) +{ + uint32_t status; + uint16_t rDat = 0x0000; + + status = Chip_SPI_GetStatus(pSPI); + /* Check error status */ + if (status & SPI_SR_ERROR) { + return ERROR; + } + + Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF); + if (status & SPI_SR_SPIF) { + executeCallback(pSPI, pXfSetup->fnAftFrame); + if (pXfSetup->cnt < pXfSetup->length) { + /* read data */ + readData(pSPI, pXfSetup, rDat, bytes); + pXfSetup->cnt += bytes; + } + } + + if (pXfSetup->cnt < pXfSetup->length) { + + executeCallback(pSPI, pXfSetup->fnBefFrame); + + /* Write data */ + writeData(pSPI, pXfSetup, bytes); + } + else { + executeCallback(pSPI, pXfSetup->fnAftTransfer); + } + return SUCCESS; +} + +/* SPI Interrupt Read/Write with 8-bit frame width */ +Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) +{ + return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 1); +} + +/* SPI Interrupt Read/Write with 16-bit frame width */ +Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) +{ + return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 2); +} + +/* Set the clock frequency for SPI interface */ +void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate) +{ + uint32_t spiClk, counter; + /* Get SPI clock rate */ + spiClk = Chip_Clock_GetRate(CLK_SPI); + + counter = spiClk / bitRate; + if (counter < 8) { + counter = 8; + } + counter = ((counter + 1) / 2) * 2; + + if (counter > 254) { + counter = 254; + } + + Chip_SPI_SetClockCounter(pSPI, counter); +} + +/* Initialize the SPI */ +void Chip_SPI_Init(LPC_SPI_T *pSPI) +{ + Chip_Clock_Enable(CLK_SPI); + + Chip_SPI_SetMode(pSPI, SPI_MODE_MASTER); + pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | SPI_BITS_8 | SPI_CLOCK_CPHA0_CPOL0 | SPI_DATA_MSB_FIRST; + Chip_SPI_SetBitRate(pSPI, 400000); +} + +/* De-initializes the SPI peripheral */ +void Chip_SPI_DeInit(LPC_SPI_T *pSPI) +{ + Chip_Clock_Disable(CLK_SPI); +} + +#endif + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/ssp_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/ssp_18xx_43xx.c new file mode 100644 index 0000000000000..40aea60960180 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/ssp_18xx_43xx.c @@ -0,0 +1,475 @@ +/* + * @brief LPC18xx/43xx SSP driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + if (xf_setup->tx_data) { + Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data + + xf_setup->tx_cnt))); + } + else { + Chip_SSP_SendFrame(pSSP, 0xFFFF); + } + + xf_setup->tx_cnt += 2; +} + +/** SSP macro: write 1 bytes to FIFO buffer */ +STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + if (xf_setup->tx_data) { + Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt))); + } + else { + Chip_SSP_SendFrame(pSSP, 0xFF); + } + + xf_setup->tx_cnt++; +} + +/** SSP macro: read 1 bytes from FIFO buffer */ +STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + uint16_t rDat; + + while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) && + (xf_setup->rx_cnt < xf_setup->length)) { + rDat = Chip_SSP_ReceiveFrame(pSSP); + if (xf_setup->rx_data) { + *(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; + } + + xf_setup->rx_cnt += 2; + } +} + +/** SSP macro: read 2 bytes from FIFO buffer */ +STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + uint16_t rDat; + + while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) && + (xf_setup->rx_cnt < xf_setup->length)) { + rDat = Chip_SSP_ReceiveFrame(pSSP); + if (xf_setup->rx_data) { + *(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; + } + + xf_setup->rx_cnt++; + } +} + +/* Returns clock index for the register interface */ +STATIC CHIP_CCU_CLK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP) +{ + CHIP_CCU_CLK_T clkSSP; + + if (pSSP == LPC_SSP1) { + clkSSP = CLK_MX_SSP1; + } + else { + clkSSP = CLK_MX_SSP0; + } + + return clkSSP; +} + +/* Returns clock index for the peripheral block */ +STATIC CHIP_CCU_CLK_T Chip_SSP_GetPeriphClockIndex(LPC_SSP_T *pSSP) +{ + CHIP_CCU_CLK_T clkSSP; + + if (pSSP == LPC_SSP1) { + clkSSP = CLK_APB2_SSP1; + } + else { + clkSSP = CLK_APB0_SSP0; + } + + return clkSSP; +} +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/*Set up output clocks per bit for SSP bus*/ +void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale) +{ + uint32_t temp; + temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF))); + pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate)); + pSSP->CPSR = prescale; +} + +/* SSP Polling Read/Write in blocking mode */ +uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + /* Clear all remaining frames in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + Chip_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) { + /* write data to buffer */ + if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) { + SSP_Write2BFifo(pSSP, xf_setup); + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read2BFifo(pSSP, xf_setup); + } + } + else { + while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) { + /* write data to buffer */ + if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) { + SSP_Write1BFifo(pSSP, xf_setup); + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read1BFifo(pSSP, xf_setup); + } + } + if (xf_setup->tx_data) { + return xf_setup->tx_cnt; + } + else if (xf_setup->rx_data) { + return xf_setup->rx_cnt; + } + + return 0; +} + +/* SSP Polling Write in blocking mode */ +uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, const uint8_t *buffer, uint32_t buffer_len) +{ + uint32_t tx_cnt = 0, rx_cnt = 0; + + /* Clear all remaining frames in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + Chip_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + uint16_t *wdata16; + + wdata16 = (uint16_t *) buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + Chip_SSP_SendFrame(pSSP, *wdata16); + wdata16++; + tx_cnt += 2; + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) { + Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */ + rx_cnt += 2; + } + } + } + else { + const uint8_t *wdata8; + + wdata8 = buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + Chip_SSP_SendFrame(pSSP, *wdata8); + wdata8++; + tx_cnt++; + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */ + rx_cnt++; + } + } + } + + return tx_cnt; + +} + +/* SSP Polling Read in blocking mode */ +uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len) +{ + uint32_t rx_cnt = 0, tx_cnt = 0; + + /* Clear all remaining frames in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + Chip_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + uint16_t *rdata16; + + rdata16 = (uint16_t *) buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */ + tx_cnt += 2; + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + *rdata16 = Chip_SSP_ReceiveFrame(pSSP); + rdata16++; + rx_cnt += 2; + } + } + } + else { + uint8_t *rdata8; + + rdata8 = buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */ + tx_cnt++; + } + + /* Check overrun error */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + *rdata8 = Chip_SSP_ReceiveFrame(pSSP); + rdata8++; + rx_cnt++; + } + } + } + + return rx_cnt; + +} + +/* Clean all data in RX FIFO of SSP */ +void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP) +{ + if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) { + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {} + } + + /* Clear all remaining frames in RX FIFO */ + while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + Chip_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); +} + +/* SSP Interrupt Read/Write with 8-bit frame width */ +Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + /* Check overrun error in RIS register */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) { + /* check if RX FIFO contains data */ + SSP_Read1BFifo(pSSP, xf_setup); + + while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) { + /* Write data to buffer */ + SSP_Write1BFifo(pSSP, xf_setup); + + /* Check overrun error in RIS register */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read1BFifo(pSSP, xf_setup); + } + + return SUCCESS; + } + + return ERROR; +} + +/* SSP Interrupt Read/Write with 16-bit frame width */ +Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup) +{ + /* Check overrun error in RIS register */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) { + /* check if RX FIFO contains data */ + SSP_Read2BFifo(pSSP, xf_setup); + + while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) { + /* Write data to buffer */ + SSP_Write2BFifo(pSSP, xf_setup); + + /* Check overrun error in RIS register */ + if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read2BFifo(pSSP, xf_setup); + } + + return SUCCESS; + } + + return ERROR; +} + +/* Set the SSP operating modes, master or slave */ +void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master) +{ + if (master) { + Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER); + } + else { + Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE); + } +} + +/* Set the clock frequency for SSP interface */ +void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate) +{ + uint32_t ssp_clk, cr0_div, cmp_clk, prescale; + + ssp_clk = Chip_Clock_GetRate(Chip_SSP_GetPeriphClockIndex(pSSP)); + + cr0_div = 0; + cmp_clk = 0xFFFFFFFF; + prescale = 2; + + while (cmp_clk > bitRate) { + cmp_clk = ssp_clk / ((cr0_div + 1) * prescale); + if (cmp_clk > bitRate) { + cr0_div++; + if (cr0_div > 0xFF) { + cr0_div = 0; + prescale += 2; + } + } + } + + Chip_SSP_SetClockRate(pSSP, cr0_div, prescale); +} + +/* Initialize the SSP */ +void Chip_SSP_Init(LPC_SSP_T *pSSP) +{ + Chip_Clock_Enable(Chip_SSP_GetClockIndex(pSSP)); + Chip_Clock_Enable(Chip_SSP_GetPeriphClockIndex(pSSP)); + + Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER); + Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0); + Chip_SSP_SetBitRate(pSSP, 100000); +} + +/* De-initializes the SSP peripheral */ +void Chip_SSP_DeInit(LPC_SSP_T *pSSP) +{ + Chip_SSP_Disable(pSSP); + + Chip_Clock_Disable(Chip_SSP_GetPeriphClockIndex(pSSP)); + Chip_Clock_Disable(Chip_SSP_GetClockIndex(pSSP)); + +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/stopwatch_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/stopwatch_18xx_43xx.c new file mode 100644 index 0000000000000..f18fac6f7e973 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/stopwatch_18xx_43xx.c @@ -0,0 +1,112 @@ +/* + * @brief LPC18xx/43xx specific stopwatch implementation + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "stopwatch.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Precompute these to optimize runtime */ +static uint32_t ticksPerSecond; +static uint32_t ticksPerMs; +static uint32_t ticksPerUs; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize stopwatch */ +void StopWatch_Init(void) +{ + /* Use timer 1. Set prescaler to divide by 8 */ + const uint32_t prescaleDivisor = 8; + Chip_TIMER_Init(LPC_TIMER0); + Chip_TIMER_PrescaleSet(LPC_TIMER0, prescaleDivisor - 1); + Chip_TIMER_Enable(LPC_TIMER0); + + /* Pre-compute tick rate. */ + ticksPerSecond = Chip_Clock_GetRate(CLK_MX_TIMER0) / prescaleDivisor; + ticksPerMs = ticksPerSecond / 1000; + ticksPerUs = ticksPerSecond / 1000000; +} + +/* Start a stopwatch */ +uint32_t StopWatch_Start(void) +{ + /* Return the current timer count. */ + return Chip_TIMER_ReadCount(LPC_TIMER0); +} + +/* Returns number of ticks per second of the stopwatch timer */ +uint32_t StopWatch_TicksPerSecond(void) +{ + return ticksPerSecond; +} + +/* Converts from stopwatch ticks to mS. */ +uint32_t StopWatch_TicksToMs(uint32_t ticks) +{ + return ticks / ticksPerMs; +} + +/* Converts from stopwatch ticks to uS. */ +uint32_t StopWatch_TicksToUs(uint32_t ticks) +{ + return ticks / ticksPerUs; +} + +/* Converts from mS to stopwatch ticks. */ +uint32_t StopWatch_MsToTicks(uint32_t mS) +{ + return mS * ticksPerMs; +} + +/* Converts from uS to stopwatch ticks. */ +uint32_t StopWatch_UsToTicks(uint32_t uS) +{ + return uS * ticksPerUs; +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/sysinit_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/sysinit_18xx_43xx.c new file mode 100644 index 0000000000000..efbecf87716b2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/sysinit_18xx_43xx.c @@ -0,0 +1,166 @@ +/* + * @brief LPC18xx/LPC43xx Chip specific SystemInit + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CHIP_CGU_BASE_CLK_T clk; /* Base clock */ + CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab; /* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +static const struct CLK_BASE_STATES InitClkStates[] = { + {CLK_BASE_SAFE, CLKIN_IRC, true, false}, + {CLK_BASE_APB1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_APB3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_USB0, CLKIN_USBPLL, true, true}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SPI, CLKIN_MAINPLL, true, false}, + {CLK_BASE_ADCHS, CLKIN_MAINPLL, true, true}, +#endif + {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART2, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_OUT, CLKINPUT_PD, true, false}, + {CLK_BASE_APLL, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}, +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ +/* Setup Chip Core clock */ +void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase) +{ + int i; + volatile uint32_t delay = 500; + uint32_t direct = 0, pdivide = 0; + PLL_PARAM_T ppll; + + if (clkin == CLKIN_CRYSTAL) { + /* Switch main system clocking to crystal */ + Chip_Clock_EnableCrystal(); + } + Chip_Clock_SetBaseClock(CLK_BASE_MX, clkin, true, false); + Chip_Clock_DisableMainPLL(); /* Disable PLL */ + + /* Calculate the PLL Parameters */ + ppll.srcin = clkin; + Chip_Clock_CalcMainPLLValue(core_freq, &ppll); + + if (core_freq > 110000000UL) { + if (ppll.ctrl & (1 << 6)) { + while(1); // to run in integer mode above 110 MHz, you need to use IDIV clock to boot strap CPU to that freq + } else if (ppll.ctrl & (1 << 7)){ + direct = 1; + ppll.ctrl &= ~(1 << 7); + } else { + pdivide = 1; + ppll.psel++; + } + } + + /* Setup and start the PLL */ + Chip_Clock_SetupMainPLL(&ppll); + + /* Wait for the PLL to lock */ + while(!Chip_Clock_MainPLLLocked()) {} + + /* Set core clock base as PLL1 */ + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); + + if (direct) { + delay = 1000; + while(delay --){} /* Wait for approx 50 uSec -- for power supply to stabilize*/ + ppll.ctrl |= 1 << 7; + Chip_Clock_SetupMainPLL(&ppll); /* Set DIRECT to operate at full frequency */ + } else if (pdivide) { + delay = 1000; + while(delay --){} /* Wait for approx 50 uSec -- for power supply to stabilize */ + ppll.psel--; + Chip_Clock_SetupMainPLL(&ppll); /* Set PDIV to operate at full frequency */ + } + + if (setbase) { + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + } +} + +/* Setup system clocking */ +void Chip_SetupXtalClocking(void) +{ + Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); +} + +/* Set up and initialize hardware prior to call to main */ +void Chip_SetupIrcClocking(void) +{ + Chip_SetupCoreClock(CLKIN_IRC, MAX_CLOCK_FREQ, true); +} + +/* Set up and initialize hardware prior to call to main */ +void Chip_SystemInit(void) +{ + /* Initial internal clocking */ + Chip_SetupIrcClocking(); +} + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/timer_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/timer_18xx_43xx.c new file mode 100644 index 0000000000000..4f1bb34462246 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/timer_18xx_43xx.c @@ -0,0 +1,123 @@ +/* + * @brief LPC18xx/43xx 16/32-bit Timer/PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Returns clock index for the peripheral block */ +STATIC CHIP_CCU_CLK_T Chip_TIMER_GetClockIndex(LPC_TIMER_T *pTMR) +{ + CHIP_CCU_CLK_T clkTMR; + + if (pTMR == LPC_TIMER3) { + clkTMR = CLK_MX_TIMER3; + } + else if (pTMR == LPC_TIMER2) { + clkTMR = CLK_MX_TIMER2; + } + else if (pTMR == LPC_TIMER1) { + clkTMR = CLK_MX_TIMER1; + } + else { + clkTMR = CLK_MX_TIMER0; + } + + return clkTMR; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize a timer */ +void Chip_TIMER_Init(LPC_TIMER_T *pTMR) +{ + Chip_Clock_Enable(Chip_TIMER_GetClockIndex(pTMR)); +} + +/* Shutdown a timer */ +void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR) +{ + Chip_Clock_Disable(Chip_TIMER_GetClockIndex(pTMR)); +} + +/* Resets the timer terminal and prescale counts to 0 */ +void Chip_TIMER_Reset(LPC_TIMER_T *pTMR) +{ + uint32_t reg; + + /* Disable timer, set terminal count to non-0 */ + reg = pTMR->TCR; + pTMR->TCR = 0; + pTMR->TC = 1; + + /* Reset timer counter */ + pTMR->TCR = TIMER_RESET; + + /* Wait for terminal count to clear */ + while (pTMR->TC != 0) {} + + /* Restore timer state */ + pTMR->TCR = reg; +} + +/* Sets external match control (MATn.matchnum) pin control */ +void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, + TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum) +{ + uint32_t mask, reg; + + /* Clear bits corresponding to selected match register */ + mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2))); + reg = pTMR->EMR &= ~mask; + + /* Set new configuration for selected match register */ + pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) | + (((uint32_t) matchState) << (4 + (matchnum * 2))); +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c new file mode 100644 index 0000000000000..186d8b1592d21 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c @@ -0,0 +1,430 @@ +/* + * @brief LPC18xx/43xx UART chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Autobaud status flag */ +STATIC volatile FlagStatus ABsyncSts = RESET; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + /* UART Peripheral clocks */ +static const CHIP_CCU_CLK_T UART_PClock[] = {CLK_MX_UART0, CLK_MX_UART1, CLK_MX_UART2, CLK_MX_UART3}; + +/* UART Bus clocks */ +static const CHIP_CCU_CLK_T UART_BClock[] = {CLK_APB0_UART0, CLK_APB0_UART1, CLK_APB2_UART2, CLK_APB2_UART3}; + +/* Returns clock index for the peripheral block */ +static int Chip_UART_GetIndex(LPC_USART_T *pUART) +{ + uint32_t base = (uint32_t) pUART; + switch(base) { + case LPC_USART0_BASE: + return 0; + case LPC_UART1_BASE: + return 1; + case LPC_USART2_BASE: + return 2; + case LPC_USART3_BASE: + return 3; + default: + return 0; /* Should never come here */ + } +} + +/* UART Autobaud command interrupt handler */ +STATIC void Chip_UART_ABIntHandler(LPC_USART_T *pUART) +{ + /* Handle End Of Autobaud interrupt */ + if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABEO_INT) != 0) { + Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABEOINT_CLR); + Chip_UART_IntDisable(pUART, UART_IER_ABEOINT); + if (ABsyncSts == RESET) { + ABsyncSts = SET; + } + } + + /* Handle Autobaud Timeout interrupt */ + if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABTO_INT) != 0) { + Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABTOINT_CLR); + Chip_UART_IntDisable(pUART, UART_IER_ABTOINT); + } +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the pUART peripheral */ +void Chip_UART_Init(LPC_USART_T *pUART) +{ + volatile uint32_t tmp; + + /* Enable UART clocking. UART base clock(s) must already be enabled */ + Chip_Clock_EnableOpts(UART_PClock[Chip_UART_GetIndex(pUART)], true, true, 1); + + /* Enable FIFOs by default, reset them */ + Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS)); + + /* Disable Tx */ + Chip_UART_TXDisable(pUART); + + /* Disable interrupts */ + pUART->IER = 0; + /* Set LCR to default state */ + pUART->LCR = 0; + /* Set ACR to default state */ + pUART->ACR = 0; + /* Set RS485 control to default state */ + pUART->RS485CTRL = 0; + /* Set RS485 delay timer to default state */ + pUART->RS485DLY = 0; + /* Set RS485 addr match to default state */ + pUART->RS485ADRMATCH = 0; + + /* Clear MCR */ + if (pUART == LPC_UART1) { + /* Set Modem Control to default state */ + pUART->MCR = 0; + /*Dummy Reading to Clear Status */ + tmp = pUART->MSR; + } + + /* Default 8N1, with DLAB disabled */ + Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS)); + + /* Disable fractional divider */ + pUART->FDR = 0x10; +} + +/* De-initializes the pUART peripheral */ +void Chip_UART_DeInit(LPC_USART_T *pUART) +{ + /* Disable Tx */ + Chip_UART_TXDisable(pUART); + + /* Disable clock */ + Chip_Clock_Disable(UART_PClock[Chip_UART_GetIndex(pUART)]); +} + +/* Transmit a byte array through the UART peripheral (non-blocking) */ +int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes) +{ + int sent = 0; + uint8_t *p8 = (uint8_t *) data; + + /* Send until the transmit FIFO is full or out of bytes */ + while ((sent < numBytes) && + ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) { + Chip_UART_SendByte(pUART, *p8); + p8++; + sent++; + } + + return sent; +} + +/* Check whether if UART is busy or not */ +FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART) +{ + if (pUART->LSR & UART_LSR_TEMT) { + return RESET; + } + else { + return SET; + } +} + +/* Transmit a byte array through the UART peripheral (blocking) */ +int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes) +{ + int pass, sent = 0; + uint8_t *p8 = (uint8_t *) data; + + while (numBytes > 0) { + pass = Chip_UART_Send(pUART, p8, numBytes); + numBytes -= pass; + sent += pass; + p8 += pass; + } + + return sent; +} + +/* Read data through the UART peripheral (non-blocking) */ +int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes) +{ + int readBytes = 0; + uint8_t *p8 = (uint8_t *) data; + + /* Send until the transmit FIFO is full or out of bytes */ + while ((readBytes < numBytes) && + ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) { + *p8 = Chip_UART_ReadByte(pUART); + p8++; + readBytes++; + } + + return readBytes; +} + +/* Read data through the UART peripheral (blocking) */ +int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes) +{ + int pass, readBytes = 0; + uint8_t *p8 = (uint8_t *) data; + + while (numBytes > 0) { + pass = Chip_UART_Read(pUART, p8, numBytes); + numBytes -= pass; + readBytes += pass; + p8 += pass; + } + + return readBytes; +} + +/* Determines and sets best dividers to get a target bit rate */ +uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate) +{ + uint32_t div, divh, divl, clkin; + + /* Determine UART clock in rate without FDR */ + clkin = Chip_Clock_GetRate(UART_BClock[Chip_UART_GetIndex(pUART)]); + div = clkin / (baudrate * 16); + + /* High and low halves of the divider */ + divh = div / 256; + divl = div - (divh * 256); + + Chip_UART_EnableDivisorAccess(pUART); + Chip_UART_SetDivisorLatches(pUART, divl, divh); + Chip_UART_DisableDivisorAccess(pUART); + + /* Fractional FDR alreadt setup for 1 in UART init */ + + return (clkin / div) >> 4; +} + +/* UART receive-only interrupt handler for ring buffers */ +void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) +{ + /* New data will be ignored if data not popped in time */ + while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) { + uint8_t ch = Chip_UART_ReadByte(pUART); + RingBuffer_Insert(pRB, &ch); + } +} + +/* UART transmit-only interrupt handler for ring buffers */ +void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) +{ + uint8_t ch; + + /* Fill FIFO until full or until TX ring buffer is empty */ + while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 && + RingBuffer_Pop(pRB, &ch)) { + Chip_UART_SendByte(pUART, ch); + } + + /* Turn off interrupt if the ring buffer is empty */ + if (RingBuffer_IsEmpty(pRB)) { + /* Shut down transmit */ + Chip_UART_IntDisable(pUART, UART_IER_THREINT); + } +} + +/* Populate a transmit ring buffer and start UART transmit */ +uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes) +{ + uint32_t ret; + uint8_t *p8 = (uint8_t *) data; + + /* Don't let UART transmit ring buffer change in the UART IRQ handler */ + Chip_UART_IntDisable(pUART, UART_IER_THREINT); + + /* Move as much data as possible into transmit ring buffer */ + ret = RingBuffer_InsertMult(pRB, p8, bytes); + Chip_UART_TXIntHandlerRB(pUART, pRB); + + /* Add additional data to transmit ring buffer if possible */ + ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret)); + + /* Enable UART transmit interrupt */ + Chip_UART_IntEnable(pUART, UART_IER_THREINT); + + return ret; +} + +/* Copy data from a receive ring buffer */ +int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes) +{ + (void) pUART; + + return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes); +} + +/* UART receive/transmit interrupt handler for ring buffers */ +void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB) +{ + /* Handle transmit interrupt if enabled */ + if (pUART->IER & UART_IER_THREINT) { + Chip_UART_TXIntHandlerRB(pUART, pTXRB); + + /* Disable transmit interrupt if the ring buffer is empty */ + if (RingBuffer_IsEmpty(pTXRB)) { + Chip_UART_IntDisable(pUART, UART_IER_THREINT); + } + } + + /* Handle receive interrupt */ + Chip_UART_RXIntHandlerRB(pUART, pRXRB); + + /* Handle Autobaud interrupts */ + Chip_UART_ABIntHandler(pUART); +} + +/* Determines and sets best dividers to get a target baud rate */ +uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baud) +{ + uint32_t sdiv = 0, sm = 1, sd = 0; + uint32_t pclk, m, d; + uint32_t odiff = -1UL; /* old best diff */ + + /* Get base clock for the corresponding UART */ + pclk = Chip_Clock_GetRate(UART_BClock[Chip_UART_GetIndex(pUART)]); + + /* Loop through all possible fractional divider values */ + for (m = 1; odiff && m < 16; m++) { + for (d = 0; d < m; d++) { + uint32_t diff, div; + uint64_t dval = (((uint64_t) pclk << 28) * m) / (baud * (m + d)); + + /* Lower 32-bit of dval has diff */ + diff = (uint32_t) dval; + /* Upper 32-bit of dval has div */ + div = (uint32_t) (dval >> 32); + + /* Closer to next div */ + if ((int)diff < 0) { + diff = -diff; + div ++; + } + + /* Check if new value is worse than old or out of range */ + if (odiff < diff || !div || (div >> 16) || (div < 3 && d)) { + continue; + } + + /* Store the new better values */ + sdiv = div; + sd = d; + sm = m; + odiff = diff; + + /* On perfect match, break loop */ + if(!diff) { + break; + } + } + } + + /* Return 0 if a vaild divisor is not possible */ + if (!sdiv) { + return 0; + } + + /* Update UART registers */ + Chip_UART_EnableDivisorAccess(pUART); + Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(sdiv), UART_LOAD_DLM(sdiv)); + Chip_UART_DisableDivisorAccess(pUART); + + /* Set best fractional divider */ + pUART->FDR = (UART_FDR_MULVAL(sm) | UART_FDR_DIVADDVAL(sd)); + + /* Return actual baud rate */ + return (pclk >> 4) * sm / (sdiv * (sm + sd)); +} + +/* UART interrupt service routine */ +FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART) +{ + (void) pUART; + return ABsyncSts; +} + +/* Start/Stop Auto Baudrate activity */ +void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart, FunctionalState NewState) +{ + uint32_t tmp = 0; + + if (NewState == ENABLE) { + /* Clear DLL and DLM value */ + pUART->LCR |= UART_LCR_DLAB_EN; + pUART->DLL = 0; + pUART->DLM = 0; + pUART->LCR &= ~UART_LCR_DLAB_EN; + + /* FDR value must be reset to default value */ + pUART->FDR = 0x10; + + if (mode == UART_ACR_MODE1) { + tmp = UART_ACR_START | UART_ACR_MODE; + } + else { + tmp = UART_ACR_START; + } + + if (autorestart == true) { + tmp |= UART_ACR_AUTO_RESTART; + } + pUART->ACR = tmp; + } + else { + pUART->ACR = 0; + } +} + + + + + + + diff --git a/ports/lpc/chips/lpc_chip_43xx/src/wwdt_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/wwdt_18xx_43xx.c new file mode 100644 index 0000000000000..78f491ad685db --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/wwdt_18xx_43xx.c @@ -0,0 +1,84 @@ +/* + * @brief LPC18xx/43xx WWDT driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the Watchdog timer */ +void Chip_WWDT_Init(LPC_WWDT_T *pWWDT) +{ + /* Disable watchdog */ + pWWDT->MOD = 0; + pWWDT->TC = 0xFF; +#if defined(WATCHDOG_WINDOW_SUPPORT) + pWWDT->WARNINT = 0xFFFF; + pWWDT->WINDOW = 0xFFFFFF; +#endif +} + +/* Shutdown the Watchdog timer */ +void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) +{ +} + +/* Clear WWDT interrupt status flags */ +void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status) +{ + if (status & WWDT_WDMOD_WDTOF) { + pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK; + } + + if (status & WWDT_WDMOD_WDINT) { + pWWDT->MOD |= WWDT_WDMOD_WDINT; + } +} + + + + + + + From e8ffb14c45e60bc5fb398addbff4a38d777c2571 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Sat, 23 Sep 2017 11:04:34 -0300 Subject: [PATCH 2/6] lpc: Introduce LPCOpen for LPC5410x LPCOpen library for LPC5410x v3.03. Signed-off-by: Ezequiel Garcia --- ports/lpc/chips/lpc_chip_5410x/README | 1 + .../lpc/chips/lpc_chip_5410x/inc/adc_5410x.h | 637 ++++++ ports/lpc/chips/lpc_chip_5410x/inc/chip.h | 251 +++ .../chips/lpc_chip_5410x/inc/clock_5410x.h | 473 +++++ ports/lpc/chips/lpc_chip_5410x/inc/cmsis.h | 55 + .../chips/lpc_chip_5410x/inc/cmsis_5410x.h | 171 ++ .../chips/lpc_chip_5410x/inc/cmsis_5410x_m0.h | 154 ++ .../chips/lpc_chip_5410x/inc/core_cm0plus.h | 793 ++++++++ ports/lpc/chips/lpc_chip_5410x/inc/core_cm4.h | 1772 +++++++++++++++++ .../chips/lpc_chip_5410x/inc/core_cm4_simd.h | 673 +++++++ .../chips/lpc_chip_5410x/inc/core_cmFunc.h | 636 ++++++ .../chips/lpc_chip_5410x/inc/core_cmInstr.h | 688 +++++++ .../chips/lpc_chip_5410x/inc/cpuctrl_5410x.h | 117 ++ .../lpc/chips/lpc_chip_5410x/inc/crc_5410x.h | 262 +++ .../lpc/chips/lpc_chip_5410x/inc/dma_5410x.h | 714 +++++++ ports/lpc/chips/lpc_chip_5410x/inc/error.h | 272 +++ .../lpc/chips/lpc_chip_5410x/inc/fifo_5410x.h | 559 ++++++ ports/lpc/chips/lpc_chip_5410x/inc/fpu_init.h | 52 + .../lpc/chips/lpc_chip_5410x/inc/gpio_5410x.h | 471 +++++ .../lpc_chip_5410x/inc/gpiogroup_5410x.h | 223 +++ .../lpc_chip_5410x/inc/i2c_common_5410x.h | 526 +++++ .../lpc/chips/lpc_chip_5410x/inc/i2cm_5410x.h | 318 +++ .../lpc/chips/lpc_chip_5410x/inc/i2cs_5410x.h | 369 ++++ ports/lpc/chips/lpc_chip_5410x/inc/iap.h | 184 ++ .../chips/lpc_chip_5410x/inc/inmux_5410x.h | 162 ++ .../chips/lpc_chip_5410x/inc/iocon_5410x.h | 139 ++ .../lpc/chips/lpc_chip_5410x/inc/lpc_types.h | 230 +++ .../chips/lpc_chip_5410x/inc/mailbox_5410x.h | 173 ++ .../lpc/chips/lpc_chip_5410x/inc/mrt_5410x.h | 340 ++++ ports/lpc/chips/lpc_chip_5410x/inc/pdm_api.h | 130 ++ .../chips/lpc_chip_5410x/inc/pinint_5410x.h | 413 ++++ .../chips/lpc_chip_5410x/inc/pintable_5410x.h | 124 ++ .../lpc/chips/lpc_chip_5410x/inc/pll_5410x.h | 305 +++ .../lpc/chips/lpc_chip_5410x/inc/pmu_5410x.h | 184 ++ .../lpc_chip_5410x/inc/power_lib_5410x.h | 281 +++ .../chips/lpc_chip_5410x/inc/ring_buffer.h | 194 ++ .../chips/lpc_chip_5410x/inc/ritimer_5410x.h | 249 +++ .../chips/lpc_chip_5410x/inc/romapi_5410x.h | 90 + .../lpc/chips/lpc_chip_5410x/inc/rtc_5410x.h | 310 +++ ports/lpc/chips/lpc_chip_5410x/inc/rtc_ut.h | 84 + .../lpc/chips/lpc_chip_5410x/inc/sct_5410x.h | 543 +++++ .../chips/lpc_chip_5410x/inc/sct_pwm_5410x.h | 178 ++ .../lpc_chip_5410x/inc/spi_common_5410x.h | 701 +++++++ .../lpc/chips/lpc_chip_5410x/inc/spim_5410x.h | 250 +++ .../lpc/chips/lpc_chip_5410x/inc/spis_5410x.h | 133 ++ .../lpc/chips/lpc_chip_5410x/inc/stopwatch.h | 137 ++ .../chips/lpc_chip_5410x/inc/syscon_5410x.h | 575 ++++++ .../chips/lpc_chip_5410x/inc/timer_5410x.h | 456 +++++ .../lpc/chips/lpc_chip_5410x/inc/uart_5410x.h | 539 +++++ .../chips/lpc_chip_5410x/inc/utick_5410x.h | 174 ++ .../lpc/chips/lpc_chip_5410x/inc/wwdt_5410x.h | 253 +++ .../lpc/chips/lpc_chip_5410x/src/adc_5410x.c | 129 ++ .../lpc/chips/lpc_chip_5410x/src/chip_5410x.c | 59 + .../chips/lpc_chip_5410x/src/clock_5410x.c | 393 ++++ .../lpc/chips/lpc_chip_5410x/src/crc_5410x.c | 118 ++ .../lpc/chips/lpc_chip_5410x/src/dma_5410x.c | 67 + .../lpc/chips/lpc_chip_5410x/src/fifo_5410x.c | 306 +++ ports/lpc/chips/lpc_chip_5410x/src/fpu_init.c | 96 + .../lpc/chips/lpc_chip_5410x/src/gpio_5410x.c | 108 + .../lpc_chip_5410x/src/gpiogroup_5410x.c | 48 + .../lpc/chips/lpc_chip_5410x/src/i2cm_5410x.c | 226 +++ .../lpc/chips/lpc_chip_5410x/src/i2cs_5410x.c | 104 + ports/lpc/chips/lpc_chip_5410x/src/iap.c | 175 ++ .../chips/lpc_chip_5410x/src/iocon_5410x.c | 58 + .../chips/lpc_chip_5410x/src/pinint_5410x.c | 83 + .../lpc/chips/lpc_chip_5410x/src/pll_5410x.c | 931 +++++++++ .../chips/lpc_chip_5410x/src/ring_buffer.c | 181 ++ .../chips/lpc_chip_5410x/src/ritimer_5410x.c | 105 + ports/lpc/chips/lpc_chip_5410x/src/rtc_ut.c | 196 ++ .../lpc/chips/lpc_chip_5410x/src/sct_5410x.c | 81 + .../chips/lpc_chip_5410x/src/sct_pwm_5410x.c | 86 + .../lpc_chip_5410x/src/spi_common_5410x.c | 71 + .../lpc/chips/lpc_chip_5410x/src/spim_5410x.c | 201 ++ .../lpc/chips/lpc_chip_5410x/src/spis_5410x.c | 154 ++ .../lpc_chip_5410x/src/stopwatch_5410x.c | 109 + .../chips/lpc_chip_5410x/src/syscon_5410x.c | 192 ++ .../chips/lpc_chip_5410x/src/sysinit_5410x.c | 181 ++ .../chips/lpc_chip_5410x/src/timer_5410x.c | 133 ++ .../lpc/chips/lpc_chip_5410x/src/uart_5410x.c | 364 ++++ .../lpc/chips/lpc_chip_5410x/src/wwdt_5410x.c | 61 + 80 files changed, 22734 insertions(+) create mode 100644 ports/lpc/chips/lpc_chip_5410x/README create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/adc_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/chip.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/clock_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/cmsis.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x_m0.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/core_cm0plus.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/core_cm4.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/core_cm4_simd.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/core_cmFunc.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/core_cmInstr.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/cpuctrl_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/crc_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/dma_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/error.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/fifo_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/fpu_init.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/gpio_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/gpiogroup_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/i2c_common_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/i2cm_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/i2cs_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/iap.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/inmux_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/iocon_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/lpc_types.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/mailbox_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/mrt_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/pdm_api.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/pinint_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/pintable_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/pll_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/pmu_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/power_lib_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/ring_buffer.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/ritimer_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/romapi_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/rtc_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/rtc_ut.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/sct_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/sct_pwm_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/spi_common_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/spim_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/spis_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/stopwatch.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/syscon_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/timer_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/uart_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/utick_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/inc/wwdt_5410x.h create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/adc_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/chip_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/clock_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/crc_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/dma_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/fifo_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/fpu_init.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/gpio_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/gpiogroup_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/i2cm_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/i2cs_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/iap.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/iocon_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/pinint_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/pll_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/ring_buffer.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/ritimer_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/rtc_ut.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/sct_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/sct_pwm_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/spi_common_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/spim_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/spis_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/stopwatch_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/syscon_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/sysinit_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/timer_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/uart_5410x.c create mode 100644 ports/lpc/chips/lpc_chip_5410x/src/wwdt_5410x.c diff --git a/ports/lpc/chips/lpc_chip_5410x/README b/ports/lpc/chips/lpc_chip_5410x/README new file mode 100644 index 0000000000000..e1095ced57fcf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/README @@ -0,0 +1 @@ +LPCOPen v3.03.000 (Release Date 10/24/2016) diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/adc_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/adc_5410x.h new file mode 100644 index 0000000000000..5c863a81efdf7 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/adc_5410x.h @@ -0,0 +1,637 @@ +/* + * @brief LPC5410X ADC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ADC_5410X_H_ +#define __ADC_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ADC_5410X CHIP: LPC5410X A/D conversion driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** Sequence index enumerations, used in various parts of the code for + register indexing and sequencer selection */ +typedef enum { + ADC_SEQA_IDX = 0, + ADC_SEQB_IDX +} ADC_SEQ_IDX_T; + +/** + * @brief ADC register block structure + */ +typedef struct { /*!< ADCn Structure */ + __IO uint32_t CTRL; + __O uint32_t RESERVED0; + __IO uint32_t SEQ_CTRL[2]; + __IO uint32_t SEQ_GDAT[2]; + __IO uint32_t RESERVED1[2]; + __IO uint32_t DAT[12]; + __IO uint32_t THR_LOW[2]; + __IO uint32_t THR_HIGH[2]; + __IO uint32_t CHAN_THRSEL; + __IO uint32_t INTEN; + __IO uint32_t FLAGS; + __IO uint32_t STARTUP; + __IO uint32_t CALIBR; +} LPC_ADC_T; + +/** Maximum sample rate in Hz (12-bit conversions) */ +#define ADC_MAX_SAMPLE_RATE 48000000 +#define ADC_MAX_CHANNEL_NUM 12 + +/** + * @brief ADC register support bitfields and mask + */ +/** ADC Control register bit fields */ +#define ADC_CR_CLKDIV_MASK (0xFF << 0) /*!< Mask for Clock divider value */ +#define ADC_CR_CLKDIV_BITPOS (0) /*!< Bit position for Clock divider value */ +#define ADC_CR_ASYNC_MODE (1 << 8) /*!< Asynchronous mode enable bit */ +#define ADC_CR_RESOL(n) ((n) << 9) /*!< 2-bits, 6(0x0),8(0x1),10(0x2),12(0x3)-bit mode enable bit */ +#define ADC_CR_LPWRMODEBIT (1 << 10) /*!< Low power mode enable bit */ +#define ADC_CR_BYPASS (1 << 11) /*!< Bypass mode */ +#define ADC_CR_TSAMP(n) ((n) << 12) /*!< 3-bits, 2.5(0x0),3.5(0x1),4.5(0x2),5.5(0x3),6.5(0x4),7.5(0x5),8.5(0x6),9.5(0x7) ADC clocks sampling time */ +#define ADC_CR_CALMODEBIT (1 << 30) /*!< Self calibration cycle enable bit */ +#define ADC_CR_BITACC(n) ((((n) & 0x1) << 9)) /*!< 12-bit or 10-bit ADC accuracy */ +#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 0)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */ +#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01)) + +/** ADC Sequence Control register bit fields */ +#define ADC_SEQ_CTRL_CHANSEL(n) (1 << (n)) /*!< Channel select macro */ +#define ADC_SEQ_CTRL_CHANSEL_BITPOS(n) ((n) << 0) /*!< Channel select macro */ +#define ADC_SEQ_CTRL_CHANSEL_MASK (0xFFF) /*!< Channel select mask */ + +/** + * @brief ADC sampling time bits 12, 13 and 14 + */ +typedef enum _ADC_TSAMP_T { + ADC_TSAMP_2CLK5 = 0, + ADC_TSAMP_3CLK5, + ADC_TSAMP_4CLK5, + ADC_TSAMP_5CLK5, + ADC_TSAMP_6CLK5, + ADC_TSAMP_7CLK5, + ADC_TSAMP_8CLK5, + ADC_TSAMP_9CLK5, +} ADC_TSAMP_T; + +/** SEQ_CTRL register bit fields */ +// #define ADC_SEQ_CTRL_TRIGGER(n) ((n)<<12) +#define ADC_SEQ_CTRL_HWTRIG_POLPOS (1 << 18) /*!< HW trigger polarity - positive edge */ +#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS (1 << 19) /*!< HW trigger bypass synchronisation */ +#define ADC_SEQ_CTRL_START (1 << 26) /*!< Start conversion enable bit */ +#define ADC_SEQ_CTRL_BURST (1 << 27) /*!< Repeated conversion enable bit */ +#define ADC_SEQ_CTRL_SINGLESTEP (1 << 28) /*!< Single step enable bit */ +#define ADC_SEQ_CTRL_LOWPRIO (1 << 29) /*!< High priority enable bit (regardless of name) */ +#define ADC_SEQ_CTRL_MODE_EOS (1 << 30) /*!< Mode End of sequence enable bit */ +#define ADC_SEQ_CTRL_SEQ_ENA (1UL << 31) /*!< Sequence enable bit */ + +/** ADC global data register bit fields */ +#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF << 4) /*!< Result value mask */ +#define ADC_SEQ_GDAT_RESULT_BITPOS (4) /*!< Result start bit position */ +#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ +#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ +#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ +#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ +#define ADC_SEQ_GDAT_CHAN_MASK (0xF << 26) /*!< Channel number mask */ +#define ADC_SEQ_GDAT_CHAN_BITPOS (26) /*!< Channel number bit position */ +#define ADC_SEQ_GDAT_OVERRUN (1 << 30) /*!< Overrun bit */ +#define ADC_SEQ_GDAT_DATAVALID (1UL << 31) /*!< Data valid bit */ + +/** ADC Data register bit fields */ +#define ADC_DR_RESULT_BITPOS (4) /*!< Result start bit position */ +#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Macro for getting the ADC data value */ +#define ADC_DR_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ +#define ADC_DR_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ +#define ADC_DR_THCMPRANGE(n) (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3) +#define ADC_DR_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ +#define ADC_DR_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ +#define ADC_DR_THCMPCROSS(n) (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3) +#define ADC_DR_CHAN_MASK (0xF << 26) /*!< Channel number mask */ +#define ADC_DR_CHAN_BITPOS (26) /*!< Channel number bit position */ +#define ADC_DR_CHANNEL(n) (((n) >> ADC_DR_CHAN_BITPOS) & 0xF) /*!< Channel number bit position */ +#define ADC_DR_OVERRUN (1 << 30) /*!< Overrun bit */ +#define ADC_DR_DATAVALID (1UL << 31) /*!< Data valid bit */ +#define ADC_DR_DONE(n) (((n) >> 31)) + +/** ADC low/high Threshold register bit fields */ +#define ADC_THR_VAL_MASK (0xFFF << 4) /*!< Threshold value bit mask */ +#define ADC_THR_VAL_POS (4) /*!< Threshold value bit position */ + +/** ADC Threshold select register bit fields */ +#define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n)) /*!< Select THR1 register for channel n */ + +/** ADC Interrupt Enable register bit fields */ +#define ADC_INTEN_SEQA_ENABLE (1 << 0) /*!< Sequence A Interrupt enable bit */ +#define ADC_INTEN_SEQB_ENABLE (1 << 1) /*!< Sequence B Interrupt enable bit */ +#define ADC_INTEN_SEQN_ENABLE(seq) (1 << (seq)) /*!< Sequence A/B Interrupt enable bit */ +#define ADC_INTEN_OVRRUN_ENABLE (1 << 2) /*!< Overrun Interrupt enable bit */ +#define ADC_INTEN_CMP_DISBALE (0) /*!< Disable comparison interrupt value */ +#define ADC_INTEN_CMP_OUTSIDETH (1) /*!< Outside threshold interrupt value */ +#define ADC_INTEN_CMP_CROSSTH (2) /*!< Crossing threshold interrupt value */ +#define ADC_INTEN_CMP_MASK (3) /*!< Comparison interrupt value mask */ +#define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3)) /*!< Interrupt selection for channel */ + +/** ADC Flags register bit fields */ +#define ADC_FLAGS_THCMP_MASK(ch) (1 << (ch)) /*!< Threshold comparison status for channel */ +#define ADC_FLAGS_OVRRUN_MASK(ch) (1 << (12 + (ch))) /*!< Overrun status for channel */ +#define ADC_FLAGS_SEQA_OVRRUN_MASK (1 << 24) /*!< Seq A Overrun status */ +#define ADC_FLAGS_SEQB_OVRRUN_MASK (1 << 25) /*!< Seq B Overrun status */ +#define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq))) /*!< Seq A/B Overrun status */ +#define ADC_FLAGS_SEQA_INT_MASK (1 << 28) /*!< Seq A Interrupt status */ +#define ADC_FLAGS_SEQB_INT_MASK (1 << 29) /*!< Seq B Interrupt status */ +#define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))/*!< Seq A/B Interrupt status */ +#define ADC_FLAGS_THCMP_INT_MASK (1 << 30) /*!< Threshold comparison Interrupt status */ +#define ADC_FLAGS_OVRRUN_INT_MASK (1UL << 31) /*!< Overrun Interrupt status */ + +/** ADC Startup register bit fields */ +#define ADC_STARTUP_ENABLE (0x1 << 0) +#define ADC_STARTUP_INIT (0x1 << 1) + +/* ADC Calibration register definition */ +#define ADC_CALIB (0x1 << 0) +#define ADC_CALREQD (0x1 << 1) + +/** + * @brief Set Interrupt bits (safe) + * @param pADC : Pointer to ADC peripheral + * @param intMask : Mask of bits to be set + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_SetIntBits(LPC_ADC_T *pADC, uint32_t intMask) +{ + /* Read and write values may not be the same, write 0 to undefined bits */ + pADC->INTEN = (pADC->INTEN | intMask) & 0x07FFFFFF; +} + +/** + * @brief Clear Interrupt bits (safe) + * @param pADC : Pointer to ADC peripheral + * @param intMask : Mask of bits to be cleared + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_ClearIntBits(LPC_ADC_T *pADC, uint32_t intMask) +{ + /* Read and write values may not be the same, write 0 to undefined bits */ + pADC->INTEN = pADC->INTEN & (0x07FFFFFF & ~intMask); +} + +/** + * @brief Set Threshold select bits (safe) + * @param pADC : Pointer to ADC peripheral + * @param mask : Mask of bits to be set + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_SetTHRSELBits(LPC_ADC_T *pADC, uint32_t mask) +{ + /* Read and write values may not be the same, write 0 to undefined bits */ + pADC->CHAN_THRSEL = (pADC->CHAN_THRSEL | mask) & 0x00000FFF; +} + +/** + * @brief Clear Threshold select bits (safe) + * @param pADC : Pointer to ADC peripheral + * @param mask : Mask of bits to be cleared + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_ClearTHRSELBits(LPC_ADC_T *pADC, uint32_t mask) +{ + /* Read and write values may not be the same, write 0 to undefined bits */ + pADC->CHAN_THRSEL = pADC->CHAN_THRSEL & (0x00000FFF & ~mask); +} + +/** + * @brief Initialize the ADC peripheral + * @param pADC : The base of ADC peripheral on the chip + * @param flags : ADC flags for init (ADC_CR_MODE10BIT and/or ADC_CR_LPWRMODEBIT) + * @return Nothing + * @note To select low-power ADC mode, enable the ADC_CR_LPWRMODEBIT flag. + * To select 10-bit conversion mode, enable the ADC_CR_MODE10BIT flag.
+ * Example: Chip_ADC_Init(LPC_ADC, (ADC_CR_MODE10BIT | ADC_CR_LPWRMODEBIT)); + */ +void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags); + +/** + * @brief Shutdown ADC + * @param pADC : The base of ADC peripheral on the chip + * @return Nothing + * @note Disables the ADC clocks and ADC power + */ +void Chip_ADC_DeInit(LPC_ADC_T *pADC); + +/** + * @brief Set ADC divider + * @param pADC : The base of ADC peripheral on the chip + * @param div : ADC divider value to set minus 1 + * @return Nothing + * @note The value is used as a divider to generate the ADC + * clock rate from the ADC input clock. The ADC input clock is based + * on the system clock. Valid values for this function are from 0 to 255 + * with 0=divide by 1, 1=divide by 2, 2=divide by 3, etc.
+ * Do not decrement this value by 1.
+ * To set the ADC clock rate to 1MHz, use the following function:
+ * Chip_ADC_SetDivider(LPC_ADC, (Chip_Clock_GetSystemClockRate() / 1000000) - 1); + */ +__STATIC_INLINE void Chip_ADC_SetDivider(LPC_ADC_T *pADC, uint8_t div) +{ + uint32_t temp; + + temp = pADC->CTRL & ~(ADC_CR_CLKDIV_MASK); + pADC->CTRL = temp | (uint32_t) div; +} + +/** + * @brief Set ADC clock rate + * @param pADC : The base of ADC peripheral on the chip + * @param rate : rate in Hz to set ADC clock to (maximum ADC_MAX_SAMPLE_RATE) + * @return Nothing + */ +void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate); + +/** + * @brief Get ADC divider + * @param pADC : The base of ADC peripheral on the chip + * @return the current ADC divider + * @note This function returns the divider that is used to generate the + * ADC frequency. The returned value must be incremented by 1. The + * frequency can be determined with the following function:
+ * adc_freq = Chip_Clock_GetSystemClockRate() / (Chip_ADC_GetDivider(LPC_ADC) + 1); + */ +__STATIC_INLINE uint8_t Chip_ADC_GetDivider(LPC_ADC_T *pADC) +{ + return pADC->CTRL & ADC_CR_CLKDIV_MASK; +} + +/** + * @brief Calibrate ADC upon startup or wakeup after powerdown + * @pre ADC must be Initialized and Configured + * @param pADC : Pointer to ADC peripheral + * @return Result of calibrarion operation + * @retval LPC_OK Calibration is successful + * @retval ERR_ADC_NO_POWER Unable to powerup ADC + * @retval ERR_TIME_OUT Calibration operation timed-out + */ +uint32_t Chip_ADC_Calibration(LPC_ADC_T *pADC); + +/** + * @brief Helper function for safely setting ADC sequencer register bits + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to set bits for + * @param bits : Or'ed bits of a sequencer register to set + * @return Nothing + * @note This function will safely set the ADC sequencer register bits + * while maintaining bits 20..25 as 0, regardless of the read state of those bits. + */ +__STATIC_INLINE void Chip_ADC_SetSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits) +{ + /* OR in passed bits */ + pADC->SEQ_CTRL[seqIndex] = (pADC->SEQ_CTRL[seqIndex] & ~(0x3F << 20)) | bits; +} + +/** + * @brief Helper function for safely clearing ADC sequencer register bits + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to clear bits for + * @param bits : Or'ed bits of a sequencer register to clear + * @return Nothing + * @note This function will safely clear the ADC sequencer register bits + * while maintaining bits 20..25 as 0, regardless of the read state of those bits. + */ +__STATIC_INLINE void Chip_ADC_ClearSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits) +{ + /* Read sequencer register and mask off bits 20..25 */ + pADC->SEQ_CTRL[seqIndex] = pADC->SEQ_CTRL[seqIndex] & ~((0x3F << 20) | bits); +} + +/** + * @brief Sets up ADC conversion sequencer A or B + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to setup + * @param options : OR'ed Sequencer options to setup (see notes) + * @return Nothing + * @note Sets up sequencer options for a conversion sequence. This function + * should be used to setup the selected channels for the sequence, the sequencer + * trigger, the trigger polarity, synchronization bypass, priority, and mode. All + * options are passed to the functions as a OR'ed list of values. This function will + * disable/clear the sequencer start/burst/single step/enable if they are enabled.
+ * Select the channels by OR'ing in one or more ADC_SEQ_CTRL_CHANSEL(ch) values.
+ * Select the hardware trigger by OR'ing in one ADC_SEQ_CTRL_HWTRIG_* value.
+ * Select a positive edge hardware trigger by OR'ing in ADC_SEQ_CTRL_HWTRIG_POLPOS.
+ * Select trigger bypass synchronisation by OR'ing in ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS.
+ * Select ADC single step on trigger/start by OR'ing in ADC_SEQ_CTRL_SINGLESTEP.
+ * Select higher priority conversion on the other sequencer by OR'ing in ADC_SEQ_CTRL_LOWPRIO.
+ * Select end of seqeuence instead of end of conversion interrupt by OR'ing in ADC_SEQ_CTRL_MODE_EOS.
+ * Example for setting up sequencer A (channels 0-2, trigger on high edge of PIO0_2, interrupt on end of sequence):
+ * Chip_ADC_SetupSequencer(LPC_ADC, ADC_SEQA_IDX, ( + * ADC_SEQ_CTRL_CHANSEL(0) | ADC_SEQ_CTRL_CHANSEL(1) | ADC_SEQ_CTRL_CHANSEL(2) | + * ADC_SEQ_CTRL_HWTRIG_PIO0_2 | ADC_SEQ_CTRL_HWTRIG_POLPOS | ADC_SEQ_CTRL_MODE_EOS)); + */ +__STATIC_INLINE void Chip_ADC_SetupSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t options) +{ + pADC->SEQ_CTRL[seqIndex] = options; +} + +/** + * @brief Get sequenceX control register value + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to setup + * @return Sequencer control register value + */ +__STATIC_INLINE uint32_t Chip_ADC_GetSequencerCtrl(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + return pADC->SEQ_CTRL[seqIndex]; +} + +/** + * @brief Enables a sequencer + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to enable + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_EnableSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_SEQ_ENA); +} + +/** + * @brief Disables a sequencer + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to disable + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_DisableSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_SEQ_ENA); +} + +/** + * @brief Forces a sequencer trigger event (software trigger of ADC) + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to start + * @return Nothing + * @note This function sets the START bit for the sequencer to force a + * single conversion sequence or a single step conversion. START and BURST bits can not + * be set at the same time, thus, BURST bit will be cleared. + */ +__STATIC_INLINE void Chip_ADC_StartSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_BURST); + Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_START); +} + +/** + * @brief Starts sequencer burst mode + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to start burst on + * @return Nothing + * @note This function sets the BURST bit for the sequencer to force + * continuous conversion. Use Chip_ADC_StopBurstSequencer() to stop the + * ADC burst sequence. START and BURST bits can not be set at the same time, thus, + * START bit will be cleared. + */ +__STATIC_INLINE void Chip_ADC_StartBurstSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + /* START and BURST bits can not be set at the same time. */ + Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_START); + Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_BURST); +} + +/** + * @brief Stops sequencer burst mode + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to stop burst on + * @return Nothing + */ +__STATIC_INLINE void Chip_ADC_StopBurstSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_BURST); +} + +/** ADC sequence global data register threshold comparison range enumerations */ +typedef enum { + ADC_DR_THCMPRANGE_INRANGE, + ADC_DR_THCMPRANGE_RESERVED, + ADC_DR_THCMPRANGE_BELOW, + ADC_DR_THCMPRANGE_ABOVE +} ADC_DR_THCMPRANGE_T; + +/** ADC sequence global data register threshold comparison cross enumerations */ +typedef enum { + ADC_DR_THCMPCROSS_NOCROSS, + ADC_DR_THCMPCROSS_RESERVED, + ADC_DR_THCMPCROSS_DOWNWARD, + ADC_DR_THCMPCROSS_UPWARD +} ADC_DR_THCMPCROSS_T; + +/** + * @brief Read a ADC sequence global data register + * @param pADC : The base of ADC peripheral on the chip + * @param seqIndex : Sequencer to read + * @return Current raw value of the ADC sequence A or B global data register + * @note This function returns the raw value of the data register and clears + * the overrun and datavalid status for the register. Once this register is read, + * the following functions can be used to parse the raw value:
+ * uint32_t adcDataRawValue = Chip_ADC_GetGlobalDataReg(LPC_ADC, ADC_SEQA_IDX); // Get raw value + * uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value + * ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high + * ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low + * uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data + * bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag + * bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag + */ +__STATIC_INLINE uint32_t Chip_ADC_GetGlobalDataReg(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) +{ + return pADC->SEQ_GDAT[seqIndex]; +} + +/** + * @brief Read a ADC data register + * @param pADC : The base of ADC peripheral on the chip + * @param index : Data register to read, 0-11 + * @return Current raw value of the ADC data register + * @note This function returns the raw value of the data register and clears + * the overrun and datavalid status for the register. Once this register is read, + * the following functions can be used to parse the raw value:
+ * uint32_t adcDataRawValue = Chip_ADC_GetDataReg(LPC_ADC, ADC_MAX_CHANNEL_NUM); // Get raw value + * uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value + * ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high + * ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low + * uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data + * bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag + * bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag + */ +__STATIC_INLINE uint32_t Chip_ADC_GetDataReg(LPC_ADC_T *pADC, uint8_t index) +{ + return pADC->DAT[index]; +} + +/** + * @brief Set Threshold low value in ADC + * @param pADC : The base of ADC peripheral on the chip + * @param thrnum : Threshold register value (1 for threshold register 1, 0 for threshold register 0) + * @param value : Threshold low data value (should be 12-bit value) + * @return None + */ +__STATIC_INLINE void Chip_ADC_SetThrLowValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value) +{ + pADC->THR_LOW[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS); +} + +/** + * @brief Set Threshold high value in ADC + * @param pADC : The base of ADC peripheral on the chip + * @param thrnum : Threshold register value (1 for threshold register 1, 0 for threshold register 0) + * @param value : Threshold high data value (should be 12-bit value) + * @return None + */ +__STATIC_INLINE void Chip_ADC_SetThrHighValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value) +{ + pADC->THR_HIGH[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS); +} + +/** + * @brief Select threshold 0 values for comparison for selected channels + * @param pADC : The base of ADC peripheral on the chip + * @param channels : An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values + * @return None + * @note Select multiple channels to use the threshold 0 comparison.
+ * Example:
+ * Chip_ADC_SelectTH0Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(1) | ADC_THRSEL_CHAN_SEL_THR1(2))); // Selects channels 1 and 2 for threshold 0 + */ +__STATIC_INLINE void Chip_ADC_SelectTH0Channels(LPC_ADC_T *pADC, uint32_t channels) +{ + Chip_ADC_ClearTHRSELBits(pADC, channels); +} + +/** + * @brief Select threshold 1 value for comparison for selected channels + * @param pADC : The base of ADC peripheral on the chip + * @param channels : An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values + * @return None + * @note Select multiple channels to use the 1 threshold comparison.
+ * Example:
+ * Chip_ADC_SelectTH1Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(4) | ADC_THRSEL_CHAN_SEL_THR1(5))); // Selects channels 4 and 5 for 1 threshold + */ +__STATIC_INLINE void Chip_ADC_SelectTH1Channels(LPC_ADC_T *pADC, uint32_t channels) +{ + Chip_ADC_SetTHRSELBits(pADC, channels); +} + +/** + * @brief Enable interrupts in ADC (sequencers A/B and overrun) + * @param pADC : The base of ADC peripheral on the chip + * @param intMask : Interrupt values to be enabled (see notes) + * @return None + * @note Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, + * ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to enable the + * specific ADC interrupts. + */ +__STATIC_INLINE void Chip_ADC_EnableInt(LPC_ADC_T *pADC, uint32_t intMask) +{ + Chip_ADC_SetIntBits(pADC, intMask); +} + +/** + * @brief Disable interrupts in ADC (sequencers A/B and overrun) + * @param pADC : The base of ADC peripheral on the chip + * @param intMask : Interrupt values to be disabled (see notes) + * @return None + * @note Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, + * ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to disable the + * specific ADC interrupts. + */ +__STATIC_INLINE void Chip_ADC_DisableInt(LPC_ADC_T *pADC, uint32_t intMask) +{ + Chip_ADC_ClearIntBits(pADC, intMask); +} + +/** Threshold interrupt event options */ +typedef enum { + ADC_INTEN_THCMP_DISABLE, + ADC_INTEN_THCMP_OUTSIDE, + ADC_INTEN_THCMP_CROSSING, +} ADC_INTEN_THCMP_T; + +/** + * @brief Enable a threshold event interrupt in ADC + * @param pADC : The base of ADC peripheral on the chip + * @param ch : ADC channel to set threshold inetrrupt for, 1-8 + * @param thInt : Selected threshold interrupt type + * @return None + */ +__STATIC_INLINE void Chip_ADC_SetThresholdInt(LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt) +{ + int shiftIndex = 3 + (ch * 2); + + /* Clear current bits first */ + Chip_ADC_ClearIntBits(pADC, (ADC_INTEN_CMP_MASK << shiftIndex)); + + /* Set new threshold interrupt type */ + Chip_ADC_SetIntBits(pADC, ((uint32_t) thInt << shiftIndex)); +} + +/** + * @brief Get flags register in ADC + * @param pADC : The base of ADC peripheral on the chip + * @return Flags register value (ORed ADC_FLAG* values) + * @note Mask the return value of this function with the ADC_FLAGS_* + * definitions to determine the overall ADC interrupt events.
+ * Example:
+ * if (Chip_ADC_GetFlags(LPC_ADC) & ADC_FLAGS_THCMP_MASK(3) // Check of threshold comp status for ADC channel 3 + */ +__STATIC_INLINE uint32_t Chip_ADC_GetFlags(LPC_ADC_T *pADC) +{ + return pADC->FLAGS; +} + +/** + * @brief Clear flags register in ADC + * @param pADC : The base of ADC peripheral on the chip + * @param flags : An Or'ed values of ADC_FLAGS_* values to clear + * @return Flags register value (ORed ADC_FLAG* values) + */ +__STATIC_INLINE void Chip_ADC_ClearFlags(LPC_ADC_T *pADC, uint32_t flags) +{ + pADC->FLAGS = flags; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/chip.h b/ports/lpc/chips/lpc_chip_5410x/inc/chip.h new file mode 100644 index 0000000000000..ee266f39591d2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/chip.h @@ -0,0 +1,251 @@ +/* + * @brief LPC5410x basic chip inclusion file + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_H_ +#define __CHIP_H_ + +#include "lpc_types.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* LPCXpresso macro LPCOpen macro defines */ +#ifdef __LPC5410X__ +#define CHIP_LPC5410X +#endif + +#ifndef CORE_M4 +#ifndef CORE_M0PLUS +#error "CORE_M4 or CORE_M0PLUS is not defined for the LPC5410x architecture" +#error "CORE_M4 or CORE_M0PLUS should be defined as part of your compiler define list" +#endif +#endif + +#ifndef CHIP_LPC5410X +#error "The LPC5410X Chip include path is used for this build, but" +#error "CHIP_LPC5410X is not defined!" +#endif + +/** @defgroup PERIPH_5410X_BASE CHIP: LPC5410X Peripheral addresses and register set declarations + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* Main memory addresses */ +#define LPC_FLASHMEM_BASE 0x00000000UL +#define LPC_SRAM0_BASE 0x02000000UL +#define LPC_SRAM1_BASE 0x02010000UL +#define LPC_ROM_BASE 0x03000000UL +#define LPC_SRAM2_BASE 0x03400000UL +#define LPC_GPIO_PORT_BASE 0x1C000000UL +#define LPC_DMA_BASE 0x1C004000UL +#define LPC_CRC_BASE 0x1C010000UL +#define LPC_SCT_BASE 0x1C018000UL +#define LPC_MBOX_BASE 0x1C02C000UL +#define LPC_ADC_BASE 0x1C034000UL +#define LPC_FIFO_BASE 0x1C038000UL + +/* APB0 peripheral group addresses */ +#define LPC_SYSCON_BASE 0x40000000UL +#define LPC_TIMER2_BASE 0x40004000UL +#define LPC_TIMER3_BASE 0x40008000UL +#define LPC_TIMER4_BASE 0x4000C000UL +#define LPC_GPIO_GROUPINT0_BASE 0x40010000UL +#define LPC_GPIO_GROUPINT1_BASE 0x40014000UL +#define LPC_PIN_INT_BASE 0x40018000UL +#define LPC_IOCON_BASE 0x4001C000UL +#define LPC_UTICK_BASE 0x40020000UL +#define LPC_FMC_BASE 0x40024000UL +#define LPC_PMU_BASE 0x4002C000UL +#define LPC_WWDT_BASE 0x40038000UL +#define LPC_RTC_BASE 0x4003C000UL + +/* APB1 peripheral group addresses */ +#define LPC_ASYNC_SYSCON_BASE 0x40080000UL +#define LPC_USART0_BASE 0x40084000UL +#define LPC_USART1_BASE 0x40088000UL +#define LPC_USART2_BASE 0x4008C000UL +#define LPC_USART3_BASE 0x40090000UL +#define LPC_I2C0_BASE 0x40094000UL +#define LPC_I2C1_BASE 0x40098000UL +#define LPC_I2C2_BASE 0x4009C000UL +#define LPC_SPI0_BASE 0x400A4000UL +#define LPC_SPI1_BASE 0x400A8000UL +#define LPC_TIMER0_BASE 0x400B4000UL +#define LPC_TIMER1_BASE 0x400B8000UL +#define LPC_INMUX_BASE 0x40050000UL +#define LPC_RITIMER_BASE 0x40070000UL +#define LPC_MRT_BASE 0x40074000UL + +/* Main memory register access */ +#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE) +#define LPC_DMA ((LPC_DMA_T *) LPC_DMA_BASE) +#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE) +#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE) +#define LPC_MBOX ((LPC_MBOX_T *) LPC_MBOX_BASE) +#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE) +#define LPC_FIFO ((LPC_FIFO_T *) LPC_FIFO_BASE) + +/* APB0 peripheral group register access */ +#define LPC_SYSCON ((LPC_SYSCON_T *) LPC_SYSCON_BASE) +#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE) +#define LPC_TIMER4 ((LPC_TIMER_T *) LPC_TIMER4_BASE) +#define LPC_GINT ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUPINT0_BASE) +#define LPC_PININT ((LPC_PIN_INT_T *) LPC_PIN_INT_BASE) +#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE) +#define LPC_UTICK ((LPC_UTICK_T *) LPC_UTICK_BASE) +#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE) +#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE) + +/* APB1 peripheral group register access */ +#define LPC_ASYNC_SYSCON ((LPC_ASYNC_SYSCON_T *) LPC_ASYNC_SYSCON_BASE) +#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE) +#define LPC_USART1 ((LPC_USART_T *) LPC_USART1_BASE) +#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE) +#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE) +#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE) +#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE) +#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE) +#define LPC_SCT0 LPC_SCT +#define LPC_SPI0 ((LPC_SPI_T *) LPC_SPI0_BASE) +#define LPC_SPI1 ((LPC_SPI_T *) LPC_SPI1_BASE) +#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE) +#define LPC_INMUX ((LPC_INMUX_T *) LPC_INMUX_BASE) +#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE) +#define LPC_MRT ((LPC_MRT_T *) LPC_MRT_BASE) +#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE) + +/** + * @} + */ + +/** @ingroup CHIP_5410X_DRIVER_OPTIONS + * @{ + */ + +/** + * @brief Clock rate on the CLKIN pin + * This value is defined externally to the chip layer and contains + * the value in Hz for the CLKIN pin for the board. If this pin isn't used, + * this rate can be 0. + */ +extern const uint32_t ExtClockIn; + +/** + * @} + */ + +/* Include order is important! */ +#include "romapi_5410x.h" +#include "syscon_5410x.h" +#include "cpuctrl_5410x.h" +#include "clock_5410x.h" +#include "pmu_5410x.h" +#include "iocon_5410x.h" +#include "pinint_5410x.h" +#include "inmux_5410x.h" +#include "crc_5410x.h" +#include "gpio_5410x.h" +#include "fifo_5410x.h" +#include "mrt_5410x.h" +#include "wwdt_5410x.h" +#include "sct_5410x.h" +#include "sct_pwm_5410x.h" +#include "rtc_5410x.h" +#include "timer_5410x.h" +#include "ritimer_5410x.h" +#include "utick_5410x.h" +#include "gpiogroup_5410x.h" +#include "mailbox_5410x.h" +#include "fpu_init.h" +#include "power_lib_5410x.h" +#include "adc_5410x.h" +#include "dma_5410x.h" +#include "uart_5410x.h" +#include "spi_common_5410x.h" +#include "spim_5410x.h" +#include "spis_5410x.h" +#include "i2c_common_5410x.h" +#include "i2cm_5410x.h" +#include "i2cs_5410x.h" + +/** @defgroup SUPPORT_5410X_FUNC CHIP: LPC5410X support functions + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief Current system clock rate, mainly used for peripherals in SYSCON + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Update system core and ASYNC syscon clock rate, should be called if the + * system has a clock rate change + * @return None + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Set up and initialize hardware prior to call to main() + * @return None + * @note Chip_SystemInit() is called prior to the application and sets up + * system clocking prior to the application starting. + */ +void Chip_SystemInit(void); + +/** + * @brief Clock and PLL initialization based on the internal oscillator + * @param iFreq : Rate (in Hz) to set the main system clock to + * @return None + */ +void Chip_SetupIrcClocking(uint32_t iFreq); + +/** + * @brief Clock and PLL initialization based on the external clock input + * @param iFreq : Rate (in Hz) to set the main system clock to + * @return None + */ +void Chip_SetupExtInClocking(uint32_t iFreq); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/clock_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/clock_5410x.h new file mode 100644 index 0000000000000..ec1328cdac58d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/clock_5410x.h @@ -0,0 +1,473 @@ +/* + * @brief LPC5410X clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CLOCK_5410X_H_ +#define __CLOCK_5410X_H_ + +#include "pll_5410x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CLOCK_5410X CHIP: LPC5410X Clock Driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* Internal oscillator frequency */ +#define SYSCON_IRC_FREQ (12000000) +#define SYSCON_WDTOSC_FREQ (500000) +#define SYSCON_RTC_FREQ (32768) + +/** + * @brief Returns the internal oscillator (IRC) clock rate + * @return internal oscillator (IRC) clock rate + */ +__STATIC_INLINE uint32_t Chip_Clock_GetIntOscRate(void) +{ + return SYSCON_IRC_FREQ; +} + +/** + * @brief Returns the external clock input rate + * @return External clock input rate + */ +__STATIC_INLINE uint32_t Chip_Clock_GetExtClockInRate(void) +{ + return ExtClockIn; +} + +/** + * @brief Returns the RTC clock rate + * @return RTC oscillator clock rate in Hz + */ +__STATIC_INLINE uint32_t Chip_Clock_GetRTCOscRate(void) +{ + return SYSCON_RTC_FREQ; +} + +/** + * @brief Return estimated watchdog oscillator rate + * @return Estimated watchdog oscillator rate + * @note This rate is accurate to plus or minus 40%. + */ +__STATIC_INLINE uint32_t Chip_Clock_GetWDTOSCRate(void) +{ + return SYSCON_WDTOSC_FREQ; +} + +/** + * Clock source selections for only the main A system clock. The main A system + * clock is used as an input into the main B system clock selector. Main clock A + * only needs to be setup if the main clock A input is used in the main clock + * system selector. + */ +typedef enum { + SYSCON_MAIN_A_CLKSRC_IRC = 0, /*!< Internal oscillator */ + SYSCON_MAIN_A_CLKSRCA_CLKIN, /*!< Crystal (main) oscillator in */ + SYSCON_MAIN_A_CLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */ +} CHIP_SYSCON_MAIN_A_CLKSRC_T; + +/** + * @brief Set main A system clock source + * @param src : Clock source for main A + * @return Nothing + * @note This function only needs to be setup if main clock A will be + * selected in the Chip_Clock_GetMain_B_ClockRate() function. + */ +__STATIC_INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCON_MAIN_A_CLKSRC_T src) +{ + LPC_SYSCON->MAINCLKSELA = (uint32_t) src; +} + +/** + * @brief Returns the main A clock source + * @return Returns which clock is used for the main A + */ +__STATIC_INLINE CHIP_SYSCON_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void) +{ + return (CHIP_SYSCON_MAIN_A_CLKSRC_T) (LPC_SYSCON->MAINCLKSELA); +} + +/** + * @brief Return main A clock rate + * @return main A clock rate in Hz + */ +uint32_t Chip_Clock_GetMain_A_ClockRate(void); + +/** + * Clock sources for only main B system clock + */ +typedef enum { + SYSCON_MAIN_B_CLKSRC_MAINCLKSELA = 0, /*!< main clock A */ + SYSCON_MAIN_B_CLKSRC_SYSPLLIN, /*!< System PLL input */ + SYSCON_MAIN_B_CLKSRC_SYSPLLOUT, /*!< System PLL output */ + SYSCON_MAIN_B_CLKSRC_RTC, /*!< RTC oscillator 32KHz output */ +} CHIP_SYSCON_MAIN_B_CLKSRC_T; + +/** + * @brief Set main B system clock source + * @param src : Clock source for main B + * @return Nothing + */ +__STATIC_INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCON_MAIN_B_CLKSRC_T src) +{ + LPC_SYSCON->MAINCLKSELB = (uint32_t) src; +} + +/** + * @brief Returns the main B clock source + * @return Returns which clock is used for the main B + */ +__STATIC_INLINE CHIP_SYSCON_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void) +{ + return (CHIP_SYSCON_MAIN_B_CLKSRC_T) (LPC_SYSCON->MAINCLKSELB); +} + +/** + * @brief Return main B clock rate + * @return main B clock rate + */ +uint32_t Chip_Clock_GetMain_B_ClockRate(void); + +/** + * Clock sources for CLKOUT + */ +typedef enum { + SYSCON_CLKOUTSRC_MAINCLK = 0, /*!< Main system clock for CLKOUT */ + SYSCON_CLKOUTSRC_CLKIN, /*!< CLKIN for CLKOUT */ + SYSCON_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */ + SYSCON_CLKOUTSRC_IRC, /*!< Internal oscillator for CLKOUT */ + SYSCON_CLKOUTSRCA_OUTPUT, /*!< clkoutA output route to input of clkoutB */ + SYSCON_CLKOUTSRC_RTC = 7 /*!< RTC oscillator 32KHz for CLKOUT */ +} CHIP_SYSCON_CLKOUTSRC_T; + +/** + * @brief Set CLKOUT clock source and divider + * @param src : Clock source for CLKOUT + * @param div : divider for CLKOUT clock + * @return Nothing + * @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock + * rate is the clock source divided by the divider. This function will + * also toggle the clock source update register to update the clock + * source. + */ +void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div); + +/** + * System and peripheral clocks enum + */ +typedef enum CHIP_SYSCON_CLOCK { + /* Peripheral clock enables for SYSAHBCLKCTRL0 */ + SYSCON_CLOCK_ROM = 1, /*!< ROM clock */ + SYSCON_CLOCK_SRAM1 = 3, /*!< SRAM1 clock */ + SYSCON_CLOCK_SRAM2, /*!< SRAM2 clock */ + SYSCON_CLOCK_FLASH = 7, /*!< FLASH controller clock */ + SYSCON_CLOCK_FMC, /*!< FMC clock */ + SYSCON_CLOCK_INPUTMUX = 11, /*!< Input mux clock */ + SYSCON_CLOCK_IOCON = 13, /*!< IOCON clock */ + SYSCON_CLOCK_GPIO0, /*!< GPIO0 clock */ + SYSCON_CLOCK_GPIO1, /*!< GPIO1 clock */ + SYSCON_CLOCK_PINT = 18, /*!< PININT clock */ + SYSCON_CLOCK_GINT, /*!< grouped pin interrupt block clock */ + SYSCON_CLOCK_DMA, /*!< DMA clock */ + SYSCON_CLOCK_CRC, /*!< CRC clock */ + SYSCON_CLOCK_WWDT, /*!< WDT clock */ + SYSCON_CLOCK_RTC, /*!< RTC clock */ + SYSCON_CLOCK_MAILBOX = 26, /*!< Mailbox clock */ + SYSCON_CLOCK_ADC0, /*!< ADC0 clock */ + + /* Peripheral clock enables for SYSAHBCLKCTRL1 */ + SYSCON_CLOCK_MRT = 32, /*!< multi-rate timer clock */ + SYSCON_CLOCK_RIT, /*!< Repetitive interval timer clock */ + SYSCON_CLOCK_SCT0, /*!< SCT0 clock */ + SYSCON_CLOCK_FIFO = 32 + 9, /*!< System FIFO clock */ + SYSCON_CLOCK_UTICK, /*!< UTICK clock */ + SYSCON_CLOCK_TIMER2 = 32 + 22, /*!< TIMER2 clock */ + SYSCON_CLOCK_TIMER3 = 32 + 26, /*!< TIMER3 clock */ + SYSCON_CLOCK_TIMER4, /*!< TIMER4 clock */ + + /* Peripheral clock enables for ASYNCAPBCLKCTRLCLR */ + SYSCON_CLOCK_USART0 = 128 + 1, /*!< USART0 clock */ + SYSCON_CLOCK_USART1, /*!< USART1 clock */ + SYSCON_CLOCK_USART2, /*!< USART2 clock */ + SYSCON_CLOCK_USART3, /*!< USART3 clock */ + SYSCON_CLOCK_I2C0, /*!< I2C0 clock */ + SYSCON_CLOCK_I2C1, /*!< I2C1 clock */ + SYSCON_CLOCK_I2C2, /*!< I2C2 clock */ + SYSCON_CLOCK_SPI0 = 128 + 9, /*!< SPI0 clock */ + SYSCON_CLOCK_SPI1, /*!< SPI1 clock */ + SYSCON_CLOCK_TIMER0 = 128 + 13, /*!< TIMER0 clock */ + SYSCON_CLOCK_TIMER1, /*!< TIMER1 clock */ + SYSCON_CLOCK_FRG /*!< FRG clock */ +} CHIP_SYSCON_CLOCK_T; + +/** + * @brief Enable a system or peripheral clock + * @param clk : Clock to enable + * @return Nothing + */ +void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk); + +/** + * @brief Disable a system or peripheral clock + * @param clk : Clock to disable + * @return Nothing + */ +void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk); + +/** + * @brief Set system tick clock divider (external CLKIN as SYSTICK reference only) + * @param div : divider for system clock + * @return Nothing + * @note Use 0 to disable, or a divider value of 1 to 255. The system tick + * rate is the external CLKIN rate divided by this value. The extern CLKIN pin + * signal, divided by the SYSTICKCLKDIV divider, is selected by clearing + * CLKSOURCE bit 2 in the System Tick CSR register. The core clock must be at least + * 2.5 times faster than the reference system tick clock otherwise the count + * values are unpredictable. + */ +__STATIC_INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div) +{ + LPC_SYSCON->SYSTICKCLKDIV = div; +} + +/** + * @brief Returns system tick clock divider + * @return system tick clock divider + */ +__STATIC_INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void) +{ + return LPC_SYSCON->SYSTICKCLKDIV; +} + +/** + * @brief Returns the system tick rate as used with the system tick divider + * @return the system tick rate + */ +uint32_t Chip_Clock_GetSysTickClockRate(void); + +/** + * @brief Set system clock divider + * @param div : divider for system clock + * @return Nothing + * @note Use 0 to disable, or a divider value of 1 to 255. The system clock + * rate is the main system clock divided by this value. + */ +__STATIC_INLINE void Chip_Clock_SetSysClockDiv(uint32_t div) +{ + LPC_SYSCON->AHBCLKDIV = div; +} + +/** + * @brief Set system tick clock divider + * @param div : divider for system clock + * @return Nothing + * @note Use 0 to disable, or a divider value of 1 to 255. The system tick + * rate is the main system clock divided by this value. Use caution when using + * the CMSIS SysTick_Config() functions as they typically use SystemCoreClock + * for setup. + */ +__STATIC_INLINE void Chip_Clock_SetADCClockDiv(uint32_t div) +{ + LPC_SYSCON->ADCCLKDIV = div; +} + +/** + * @brief Returns ADC clock divider + * @return ADC clock divider, 0 = disabled + */ +__STATIC_INLINE uint32_t Chip_Clock_GetADCClockDiv(void) +{ + return LPC_SYSCON->ADCCLKDIV; +} + +/** + * Clock sources for ADC clock source select + */ +typedef enum { + SYSCON_ADCCLKSELSRC_MAINCLK = 0, /*!< Main clock */ + SYSCON_ADCCLKSELSRC_SYSPLLOUT, /*!< PLL output */ + SYSCON_ADCCLKSELSRC_IRC /*!< Internal oscillator */ +} CHIP_SYSCON_ADCCLKSELSRC_T; + +/** + * @brief Set the ADC clock source + * @param src : ADC clock source + * @return Nothing + */ +__STATIC_INLINE void Chip_Clock_SetADCClockSource(CHIP_SYSCON_ADCCLKSELSRC_T src) +{ + LPC_SYSCON->ADCCLKSEL = (uint32_t) src; +} + +/** + * @brief Returns the ADC clock source + * @return Returns which clock is used for the ADC clock source + */ +__STATIC_INLINE CHIP_SYSCON_ADCCLKSELSRC_T Chip_Clock_GetADCClockSource(void) +{ + return (CHIP_SYSCON_ADCCLKSELSRC_T) (LPC_SYSCON->ADCCLKSEL); +} + +/** + * @brief Return ADC clock rate + * @return ADC clock rate + */ +uint32_t Chip_Clock_GetADCClockRate(void); + +/** + * @brief Enable the RTC 32KHz output + * @return Nothing + * @note This clock can be used for the main clock directly, but + * do not use this clock with the system PLL. + */ +__STATIC_INLINE void Chip_Clock_EnableRTCOsc(void) +{ + LPC_SYSCON->RTCOSCCTRL = 1; +} + +/** + * @brief Disable the RTC 32KHz output + * @return Nothing + */ +__STATIC_INLINE void Chip_Clock_DisableRTCOsc(void) +{ + LPC_SYSCON->RTCOSCCTRL = 0; +} + +/** + * Clock source selections for the asynchronous APB clock + */ +typedef enum { + SYSCON_ASYNC_IRC = 0, /*!< IRC input */ + SYSCON_ASYNC_WDTOSC, /*!< Watchdog oscillator */ + SYSCON_ASYNC_MAINCLK = 4, /*!< Main clock */ + SYSCON_ASYNC_CLKIN, /*!< external CLK input */ + SYSCON_ASYNC_SYSPLLOUT /*!< System PLL output */ +} CHIP_ASYNC_SYSCON_SRC_T; + +/** + * @brief Set asynchronous APB clock source + * @param src : Clock source for asynchronous APB clock + * @return Nothing + */ +void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src); + +/** + * @brief Get asynchronous APB clock source + * @return Clock source for asynchronous APB clock + */ +CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void); + +/** + * @brief Return asynchronous APB clock rate + * @return Asynchronous APB clock rate + * @note Includes adjustments by Async clock divider (ASYNCCLKDIV). + */ +uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void); + +/** + * @brief Set UART divider clock + * @param div : divider for UART clock + * @return Nothing + * @note Use 0 to disable, or a divider value of 1 to 255. The UART clock + * rate is the main system clock divided by this value. + */ +__STATIC_INLINE void Chip_Clock_SetAsyncSysconClockDiv(uint32_t div) +{ + LPC_ASYNC_SYSCON->ASYNCCLKDIV = div; +} + +/** + * Clock sources for main system clock. This is a mix of both main clock A + * and B selections. + */ +typedef enum { + SYSCON_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */ + SYSCON_MAINCLKSRC_CLKIN, /*!< Crystal (main) oscillator in */ + SYSCON_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */ + SYSCON_MAINCLKSRC_PLLIN = 5, /*!< System PLL input */ + SYSCON_MAINCLKSRC_PLLOUT, /*!< System PLL output */ + SYSCON_MAINCLKSRC_RTC /*!< RTC oscillator 32KHz output */ +} CHIP_SYSCON_MAINCLKSRC_T; + +/** + * @brief Set main system clock source + * @param src : Clock source for main system + * @return Nothing + */ +void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src); + +/** + * @brief Get main system clock source + * @return Clock source for main system + * @note + */ +CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void); + +/** + * @brief Return main clock rate + * @return main clock rate + */ +uint32_t Chip_Clock_GetMainClockRate(void); + +/** + * @brief Return system clock rate + * @return system clock rate + * @note This is the main clock rate divided by AHBCLKDIV. + */ +uint32_t Chip_Clock_GetSystemClockRate(void); + +/** + * @brief Get UART base clock rate + * @return UART base clock rate + */ +uint32_t Chip_Clock_GetUARTBaseClockRate(void); + +/** + * @brief Get UART base clock rate using FRG + * @return Actual UART base clock rate + * @note It's recommended to set a base rate at least 16x the + * expected maximum UART transfer bit rate. + */ +uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLOCK_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/cmsis.h b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis.h new file mode 100644 index 0000000000000..dea61c8b04380 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis.h @@ -0,0 +1,55 @@ +/* + * @brief LPC5410x selective CMSIS inclusion file + * + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_H_ +#define __CMSIS_H_ + +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Select correct CMSIS include file based on CORE_* definition */ +#if defined(CORE_M4) +#include "cmsis_5410x.h" +typedef LPC5410X_IRQn_Type IRQn_Type; +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#elif defined(CORE_M0PLUS) +#include "cmsis_5410x_m0.h" +typedef LPC5410X_M0_IRQn_Type IRQn_Type; +#include "core_cm0plus.h" /*!< Cortex-M0 Plus processor and core peripherals */ +#else +#error "No CORE_* definition is defined" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x.h new file mode 100644 index 0000000000000..b14c4c3382dd7 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x.h @@ -0,0 +1,171 @@ +/* + * @brief Basic CMSIS include file for LPC5410x M4 core + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_5410X_H_ +#define __CMSIS_5410X_H_ + +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_5410X_M4 CHIP: LPC5410X M4 core CMSIS include file + * @ingroup CHIP_5410X_CMSIS_DRIVERS + * @{ + */ + +#if defined(__ARMCC_VERSION) +// Kill warning "#pragma push with no matching #pragma pop" + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) +// #pragma push // FIXME not usable for IAR + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +#if !defined(CORE_M4) +#error "CORE_M4 is not defined" +#endif + +/** @defgroup CMSIS_5410X_M4_IRQ CHIP_5410X: LPC5410X M4 core peripheral interrupt numbers + * @{ + */ + +typedef enum { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /****** LPC5410X Specific Interrupt Numbers ********************************************************/ + WDT_IRQn = 0, /*!< WWDT */ + BOD_IRQn = 1, /*!< BOD */ + Reserved2_IRQn = 2, /*!< Reserved Interrupt */ + DMA_IRQn = 3, /*!< DMA */ + GINT0_IRQn = 4, /*!< GINT0 */ + PIN_INT0_IRQn = 5, /*!< PININT0 */ + PIN_INT1_IRQn = 6, /*!< PININT1 */ + PIN_INT2_IRQn = 7, /*!< PININT2 */ + PIN_INT3_IRQn = 8, /*!< PININT3 */ + UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */ + MRT_IRQn = 10, /*!< Multi-rate timer interrupt */ + CT32B0_IRQn = 11, /*!< CTMR0 */ + CT32B1_IRQn = 12, /*!< CTMR1 */ + CT32B2_IRQn = 13, /*!< CTMR2 */ + CT32B3_IRQn = 14, /*!< CTMR3 */ + CT32B4_IRQn = 15, /*!< CTMR4 */ + SCT0_IRQn = 16, /*!< SCT */ + UART0_IRQn = 17, /*!< UART0 */ + UART1_IRQn = 18, /*!< UART1 */ + UART2_IRQn = 19, /*!< UART2 */ + UART3_IRQn = 20, /*!< UART3 */ + I2C0_IRQn = 21, /*!< I2C0 */ + I2C1_IRQn = 22, /*!< I2C1 */ + I2C2_IRQn = 23, /*!< I2C2 */ + SPI0_IRQn = 24, /*!< SPI0 */ + SPI1_IRQn = 25, /*!< SPI1 */ + ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */ + ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */ + ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */ + RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */ + Reserved30_IRQn = 30, /*!< Reserved Interrupt */ + MAILBOX_IRQn = 31, /*!< Mailbox */ + GINT1_IRQn = 32, /*!< GINT1 */ + PIN_INT4_IRQn = 33, /*!< External Interrupt 4 */ + PIN_INT5_IRQn = 34, /*!< External Interrupt 5 */ + PIN_INT6_IRQn = 35, /*!< External Interrupt 6 */ + PIN_INT7_IRQn = 36, /*!< External Interrupt 7 */ + Reserved37_IRQn = 37, /*!< Reserved Interrupt */ + Reserved38_IRQn = 38, /*!< Reserved Interrupt */ + Reserved39_IRQn = 39, /*!< Reserved Interrupt */ + RIT_IRQn = 40, /*!< Repetitive Interrupt Timer */ + Reserved41_IRQn = 41, /*!< Reserved Interrupt */ + Reserved42_IRQn = 42, /*!< Reserved Interrupt */ + Reserved43_IRQn = 43, /*!< Reserved Interrupt */ + Reserved44_IRQn = 44, /*!< Reserved Interrupt */ +} LPC5410X_IRQn_Type; + +/** + * @} + */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** @defgroup CMSIS_5410X_M4_COMMON CHIP: LPC5410X M4 core Cortex CMSIS definitions + * @{ + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x_m0.h b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x_m0.h new file mode 100644 index 0000000000000..c258e71279245 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/cmsis_5410x_m0.h @@ -0,0 +1,154 @@ +/* + * @brief Basic CMSIS include file for LPC5410x M0+ core + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_5410X_M0_H_ +#define __CMSIS_5410X_M0_H_ + +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_5410X_M0 CHIP: LPC5410X M0 core CMSIS include file + * @ingroup CHIP_5410X_CMSIS_DRIVERS + * @{ + */ + +#if defined(__ARMCC_VERSION) +// Kill warning "#pragma push with no matching #pragma pop" + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) +// #pragma push // FIXME not usable for IAR + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +#if !defined(CORE_M0PLUS) +#error "CORE_M0PLUS is not defined" +#endif + +/** @defgroup CMSIS_5410X_M0_IRQ CHIP_5410X: LPC5410X M0 core peripheral interrupt numbers + * @{ + */ + +typedef enum { + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /****** LPC5410X Specific Interrupt Numbers ********************************************************/ + WDT_IRQn = 0, /*!< WWDT */ + BOD_IRQn = 1, /*!< BOD */ + Reserved2_IRQn = 2, /*!< Reserved Interrupt */ + DMA_IRQn = 3, /*!< DMA */ + GINT0_IRQn = 4, /*!< GINT0 */ + PIN_INT0_IRQn = 5, /*!< PININT0 */ + PIN_INT1_IRQn = 6, /*!< PININT1 */ + PIN_INT2_IRQn = 7, /*!< PININT2 */ + PIN_INT3_IRQn = 8, /*!< PININT3 */ + UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */ + MRT_IRQn = 10, /*!< Multi-rate timer interrupt */ + CT32B0_IRQn = 11, /*!< CTMR0 */ + CT32B1_IRQn = 12, /*!< CTMR1 */ + CT32B2_IRQn = 13, /*!< CTMR2 */ + CT32B3_IRQn = 14, /*!< CTMR3 */ + CT32B4_IRQn = 15, /*!< CTMR4 */ + SCT0_IRQn = 16, /*!< SCT */ + UART0_IRQn = 17, /*!< UART0 */ + UART1_IRQn = 18, /*!< UART1 */ + UART2_IRQn = 19, /*!< UART2 */ + UART3_IRQn = 20, /*!< UART3 */ + I2C0_IRQn = 21, /*!< I2C0 */ + I2C1_IRQn = 22, /*!< I2C1 */ + I2C2_IRQn = 23, /*!< I2C2 */ + SPI0_IRQn = 24, /*!< SPI0 */ + SPI1_IRQn = 25, /*!< SPI1 */ + ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */ + ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */ + ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */ + RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */ + Reserved30_IRQn = 30, /*!< Reserved Interrupt */ + MAILBOX_IRQn = 31, /*!< Mailbox */ +} LPC5410X_M0_IRQn_Type; + +/** + * @} + */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** @defgroup CMSIS_5410X_M0_COMMON CHIP: LPC5410X M0 core Cortex CMSIS definitions + * @{ + */ + +/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_5410X_M0_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/core_cm0plus.h b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm0plus.h new file mode 100644 index 0000000000000..5cea74e9af368 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm0plus.h @@ -0,0 +1,793 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4.h b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4.h new file mode 100644 index 0000000000000..d65016c714944 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4.h @@ -0,0 +1,1772 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4_simd.h b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4_simd.h new file mode 100644 index 0000000000000..83db95b5f112d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/core_cm4_simd.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/core_cmFunc.h b/ports/lpc/chips/lpc_chip_5410x/inc/core_cmFunc.h new file mode 100644 index 0000000000000..0a18fafc301e0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/core_cmInstr.h b/ports/lpc/chips/lpc_chip_5410x/inc/core_cmInstr.h new file mode 100644 index 0000000000000..ab3a01097c12e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/cpuctrl_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/cpuctrl_5410x.h new file mode 100644 index 0000000000000..3f483938f8ba5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/cpuctrl_5410x.h @@ -0,0 +1,117 @@ +/* + * @brief LPC5410X CPU multi-core support driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CPUCTRL_5410X_H_ +#define __CPUCTRL_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver + * @ingroup CHIP_5410X_DRIVERS + * This driver helps with determine which MCU core the software is running, + * whether the MCU core is in master or slave mode, and provides functions + * for master and slave core control.
+ * + * The functions for the driver are provided as part of the + * @ref POWER_LIBRARY_5410X library. For more information on using the + * LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE
. + * @{ + */ + +/** + * @brief Determine which MCU this code is running on + * @return true if executing on the CM4, or false if executing on the CM0+ + */ +__STATIC_INLINE bool Chip_CPU_IsM4Core(void) { + /* M4 core is designated by values 0xC24 on bits 15..4 */ + if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) { + return true; + } + + return false; +} + +/* Core selection */ +typedef enum { + CORESELECT_M0PLUS = 0, + CORESELECT_M4 +} CORESELECT_T; + +/** + * @brief Select master core and system power control ownership + * @return Nothing + * @note This function can be used to select the master core and which + * core can powerdown the system. The master core can be re-selected on + * either the current master or slave core. Power control ownership is used + * to select which core can place the system in DEEP SLEEP, POWERDOWN, and + * DEEP POWERDOWN modes. (See @ref Chip_POWER_EnterPowerMode). Note both + * the master and slave cores can used SLEEP mode, but only the master core + * can use the other modes. + */ +void Chip_CPU_SelectMasterCore(CORESELECT_T master, CORESELECT_T ownerPower); + +/** + * @brief Determine if this core is a slave or master + * @return true if this MCU is operating as the master, or false if operating as a slave + */ +bool Chip_CPU_IsMasterCore(void); + +/** + * @brief Setup M0+ boot and reset M0+ core + * @param coentry : Pointer to boot entry point for M0+ core + * @param costackptr : Pointer to where stack should be located for M0+ core + * @return Nothing + * @note Will setup boot stack and entry point, enable M0+ clock and then + * reset M0+ core. + */ +void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr); + +/** + * @brief Setup M4 boot and reset M4 core + * @param coentry : Pointer to boot entry point for M4 core + * @param costackptr : Pointer to where stack should be located for M4 core + * @return Nothing + * @note Will setup boot stack and entry point, enable M4 clock and then + * reset M0+ core. + */ +void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CPUCTRL_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/crc_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/crc_5410x.h new file mode 100644 index 0000000000000..3695cc1b49f32 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/crc_5410x.h @@ -0,0 +1,262 @@ +/* + * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CRC_5410X_H_ +#define __CRC_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CRC_5410X CHIP: LPC5410X Cyclic Redundancy Check Engine driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief CRC register block structure + */ +typedef struct { /*!< CRC Structure */ + __IO uint32_t MODE; /*!< CRC Mode Register */ + __IO uint32_t SEED; /*!< CRC SEED Register */ + union { + __I uint32_t SUM; /*!< CRC Checksum Register. */ + __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/ + __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/ + __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/ + }; + +} LPC_CRC_T; + +/* + * @brief CRC MODE register description + */ +#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */ +#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */ +#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */ +#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */ +#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */ +#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */ +#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */ +#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */ +#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */ +#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */ + +#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */ +#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */ +#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */ + +#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */ +#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */ +#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */ + +/** + * @brief CRC polynomial + */ +typedef enum IP_CRC_001_POLY { + CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */ + CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */ + CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */ + CRC_POLY_LAST, +} CRC_POLY_T; + +/** + * @brief Initializes the CRC Engine + * @return Nothing + */ +void Chip_CRC_Init(void); + +/** + * @brief Deinitializes the CRC Engine + * @return Nothing + */ +void Chip_CRC_Deinit(void); + +/** + * @brief Set the polynomial used for the CRC calculation + * @param poly : The enumerated polynomial to be used + * @param flags : An Or'ed value of flags that setup the mode + * @return Nothing + * @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS, + * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL. + */ +__STATIC_INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags) +{ + LPC_CRC->MODE = (uint32_t) poly | flags; +} + +/** + * @brief Sets up the CRC engine for CRC16 mode + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_UseCRC16(void) +{ + LPC_CRC->MODE = MODE_CFG_CRC16; + LPC_CRC->SEED = CRC_SEED_CRC16; +} + +/** + * @brief Sets up the CRC engine for CRC32 mode + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_UseCRC32(void) +{ + LPC_CRC->MODE = MODE_CFG_CRC32; + LPC_CRC->SEED = CRC_SEED_CRC32; +} + +/** + * @brief Sets up the CRC engine for CCITT mode + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_UseCCITT(void) +{ + LPC_CRC->MODE = MODE_CFG_CCITT; + LPC_CRC->SEED = CRC_SEED_CCITT; +} + +/** + * @brief Engage the CRC engine with defaults based on the polynomial to be used + * @param poly : The enumerated polynomial to be used + * @return Nothing + */ +void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly); + +/** + * @brief Set the CRC Mode bits + * @param mode : Mode value + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_SetMode(uint32_t mode) +{ + LPC_CRC->MODE = mode; +} + +/** + * @brief Get the CRC Mode bits + * @return The current value of the CRC Mode bits + */ +__STATIC_INLINE uint32_t Chip_CRC_GetMode(void) +{ + return LPC_CRC->MODE; +} + +/** + * @brief Set the seed bits used by the CRC_SUM register + * @param seed : Seed value + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_SetSeed(uint32_t seed) +{ + LPC_CRC->SEED = seed; +} + +/** + * @brief Get the CRC seed value + * @return Seed value + */ +__STATIC_INLINE uint32_t Chip_CRC_GetSeed(void) +{ + return LPC_CRC->SEED; +} + +/** + * @brief Convenience function for writing 8-bit data to the CRC engine + * @param data : 8-bit data to write + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_Write8(uint8_t data) +{ + LPC_CRC->WRDATA8 = data; +} + +/** + * @brief Convenience function for writing 16-bit data to the CRC engine + * @param data : 16-bit data to write + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_Write16(uint16_t data) +{ + LPC_CRC->WRDATA16 = data; +} + +/** + * @brief Convenience function for writing 32-bit data to the CRC engine + * @param data : 32-bit data to write + * @return Nothing + */ +__STATIC_INLINE void Chip_CRC_Write32(uint32_t data) +{ + LPC_CRC->WRDATA32 = data; +} + +/** + * @brief Gets the CRC Sum based on the Mode and Seed as previously configured + * @return CRC Checksum value + */ +__STATIC_INLINE uint32_t Chip_CRC_Sum(void) +{ + return LPC_CRC->SUM; +} + +/** + * @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block + * @param data : Pointer to the block of 8-bit data + * @param bytes : The number of bytes pointed to by data + * @return Check sum value + */ +uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes); + +/** + * @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block + * @param data : Pointer to the block of 16-bit data + * @param hwords : The number of 16 byte entries pointed to by data + * @return Check sum value + */ +uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords); + +/** + * @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block + * @param data : Pointer to the block of 32-bit data + * @param words : The number of 32-bit entries pointed to by data + * @return Check sum value + */ +uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/dma_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/dma_5410x.h new file mode 100644 index 0000000000000..cbc5239e2f695 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/dma_5410x.h @@ -0,0 +1,714 @@ +/* + * @brief LPC5410X DMA driver declarations and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __DMA_5410X_H +#define __DMA_5410X_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup DMALEG_5410X CHIP: LPC5410X DMA Engine driver (legacy) + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ +/** + * @brief DMA Controller shared registers structure + */ +typedef struct { /*!< DMA shared registers structure */ + __IO uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */ + __I uint32_t RESERVED0; + __O uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */ + __I uint32_t RESERVED1; + __I uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */ + __I uint32_t RESERVED2; + __I uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */ + __I uint32_t RESERVED3; + __IO uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */ + __I uint32_t RESERVED4; + __IO uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */ + __I uint32_t RESERVED5; + __O uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */ + __I uint32_t RESERVED6; + __IO uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */ + __I uint32_t RESERVED7; + __IO uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */ + __I uint32_t RESERVED8; + __O uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */ + __I uint32_t RESERVED9; + __O uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */ + __I uint32_t RESERVED10; + __O uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */ +} LPC_DMA_COMMON_T; + +/** + * @brief DMA Controller shared registers structure + */ +typedef struct { /*!< DMA channel register structure */ + __IO uint32_t CFG; /*!< DMA Configuration register */ + __I uint32_t CTLSTAT; /*!< DMA Control and status register */ + __IO uint32_t XFERCFG; /*!< DMA Transfer configuration register */ + __I uint32_t RESERVED; +} LPC_DMA_CHANNEL_T; + +/* On LPC540XX, Max DMA channel is 22 */ +#define MAX_DMA_CHANNEL (22) + +/** + * @brief DMA Controller register block structure + */ +typedef struct { /*!< DMA Structure */ + __IO uint32_t CTRL; /*!< DMA control register */ + __I uint32_t INTSTAT; /*!< DMA Interrupt status register */ + __IO uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */ + __I uint32_t RESERVED2[5]; + LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */ + __I uint32_t RESERVED0[225]; + LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */ +} LPC_DMA_T; + +/* DMA interrupt status bits (common) */ +#define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */ +#define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */ + +/* Support macro for DMA_CHDESC_T */ +#define DMA_ADDR(addr) ((uint32_t) (addr)) + +/* Support definitions for setting the configuration of a DMA channel. You + will need to get more information on these options from the User manual. */ +#define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */ +#define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */ +#define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */ +#define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */ +#define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */ +#define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */ +#define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */ +#define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */ +#define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */ +#define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */ +#define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */ +#define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */ +#define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */ +#define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */ +#define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */ +#define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */ +#define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */ +#define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */ +#define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */ +#define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */ +#define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */ +#define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */ +#define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */ + +/* DMA channel control and status register definitions */ +#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */ +#define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */ + +/* DMA channel transfer configuration registers definitions */ +#define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */ +#define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */ +#define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */ +#define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */ +#define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */ +#define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */ +#define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */ +#define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */ +#define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */ +#define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */ +#define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */ +#define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */ +#define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */ +#define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */ +#define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */ +#define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */ +#define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */ +#define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */ + +/* DMA channel mapping - each channel is mapped to an individual peripheral + and direction or a DMA imput mux trigger */ +typedef enum { + DMAREQ_UART0_RX = 0, /*!< UART00 receive DMA channel */ + DMA_CH0 = DMAREQ_UART0_RX, + DMAREQ_UART0_TX, /*!< UART0 transmit DMA channel */ + DMA_CH1 = DMAREQ_UART0_TX, + DMAREQ_UART1_RX, /*!< UART1 receive DMA channel */ + DMA_CH2 = DMAREQ_UART1_RX, + DMAREQ_UART1_TX, /*!< UART1 transmit DMA channel */ + DMA_CH3 = DMAREQ_UART1_TX, + DMAREQ_UART2_RX, /*!< UART2 receive DMA channel */ + DMA_CH4 = DMAREQ_UART2_RX, + DMAREQ_UART2_TX, /*!< UART2 transmit DMA channel */ + DMA_CH5 = DMAREQ_UART2_TX, + DMAREQ_UART3_RX, /*!< UART3 receive DMA channel */ + DMA_CH6 = DMAREQ_UART3_RX, + DMAREQ_UART3_TX, /*!< UART3 transmit DMA channel */ + DMA_CH7 = DMAREQ_UART3_TX, + DMAREQ_SPI0_RX, /*!< SPI0 receive DMA channel */ + DMA_CH8 = DMAREQ_SPI0_RX, + DMAREQ_SPI0_TX, /*!< SPI0 transmit DMA channel */ + DMA_CH9 = DMAREQ_SPI0_TX, + DMAREQ_SPI1_RX, /*!< SPI1 receive DMA channel */ + DMA_CH10 = DMAREQ_SPI1_RX, + DMAREQ_SPI1_TX, /*!< SPI1 transmit DMA channel */ + DMA_CH11 = DMAREQ_SPI1_TX, + DMAREQ_I2C0_SLAVE, /*!< I2C0 Slave DMA channel */ + DMA_CH12 = DMAREQ_I2C0_SLAVE, + DMAREQ_I2C0_MASTER, /*!< I2C0 Master DMA channel */ + DMA_CH13 = DMAREQ_I2C0_MASTER, + DMAREQ_I2C1_SLAVE, /*!< I2C1 Slave DMA channel */ + DMA_CH14 = DMAREQ_I2C1_SLAVE, + DMAREQ_I2C1_MASTER, /*!< I2C1 Master DMA channel */ + DMA_CH15 = DMAREQ_I2C1_MASTER, + DMAREQ_I2C2_SLAVE, /*!< I2C2 Slave DMA channel */ + DMA_CH16 = DMAREQ_I2C2_SLAVE, + DMAREQ_I2C2_MASTER, /*!< I2C2 Master DMA channel */ + DMA_CH17 = DMAREQ_I2C2_MASTER, + DMAREQ_I2C0_MONITOR, /*!< I2C0 Monitor DMA channel */ + DMA_CH18 = DMAREQ_I2C0_MONITOR, + DMAREQ_I2C1_MONITOR, /*!< I2C1 Monitor DMA channel */ + DMA_CH19 = DMAREQ_I2C1_MONITOR, + DMAREQ_I2C2_MONITOR, /*!< I2C2 Monitor DMA channel */ + DMA_CH20 = DMAREQ_I2C2_MONITOR, + RESERVED_SPARE_DMA, + DMA_CH21 = RESERVED_SPARE_DMA +} DMA_CHID_T; + +/** @defgroup DMALEG_COMMON_5410X CHIP: LPC5410X DMA Controller driver common functions (legacy) + * @{ + */ + +/** + * @brief Initialize DMA controller + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_Init(LPC_DMA_T *pDMA) +{ + (void) pDMA; + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_DMA); +} + +/** + * @brief De-Initialize DMA controller + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_DeInit(LPC_DMA_T *pDMA) +{ + (void) pDMA; + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_DMA); +} + +/** + * @brief Enable DMA controller + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_Enable(LPC_DMA_T *pDMA) +{ + pDMA->CTRL = 1; +} + +/** + * @brief Disable DMA controller + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_Disable(LPC_DMA_T *pDMA) +{ + pDMA->CTRL = 0; +} + +/** + * @brief Get pending interrupt or error interrupts + * @param pDMA : The base of DMA controller on the chip + * @return An Or'ed value of DMA_INTSTAT_* types + * @note If any DMA channels have an active interrupt or error interrupt + * pending, this functional will a common status that applies to all + * channels. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetIntStatus(LPC_DMA_T *pDMA) +{ + return pDMA->INTSTAT; +} + +/** + * @brief Set DMA controller SRAM base address + * @param pDMA : The base of DMA controller on the chip + * @param base : The base address where the DMA descriptors will be stored + * @return Nothing + * @note A 256 byte block of memory aligned on a 256 byte boundary must be + * provided for this function. It sets the base address used for + * DMA descriptor table (16 descriptors total that use 16 bytes each).
+ * + * A pre-defined table with correct alignment can be used for this + * function by calling Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table)); + */ +__STATIC_INLINE void Chip_DMA_SetSRAMBase(LPC_DMA_T *pDMA, uint32_t base) +{ + pDMA->SRAMBASE = base; +} + +/** + * @brief Returns DMA controller SRAM base address + * @param pDMA : The base of DMA controller on the chip + * @return The base address where the DMA descriptors are stored + */ +__STATIC_INLINE uint32_t Chip_DMA_GetSRAMBase(LPC_DMA_T *pDMA) +{ + return pDMA->SRAMBASE; +} + +/** + * @} + */ + +/** @defgroup DMALEG_COMMONCHAN_5410X CHIP: LPC5410X DMA Controller driver common channel functions (legacy) + * @{ + */ + +/** + * @brief Enables a single DMA channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_EnableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].ENABLESET = (1 << ch); +} + +/** + * @brief Disables a single DMA channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_DisableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].ENABLECLR = (1 << ch); +} + +/** + * @brief Returns all enabled DMA channels + * @param pDMA : The base of DMA controller on the chip + * @return An Or'ed value of all enabled DMA channels (0 - 15) + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) is enabled. A low state is disabled. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetEnabledChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].ENABLESET; +} + +/** + * @brief Returns all active DMA channels + * @param pDMA : The base of DMA controller on the chip + * @return An Or'ed value of all active DMA channels (0 - 15) + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) is active. A low state is inactive. A active + * channel indicates that a DMA operation has been started but + * not yet fully completed. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].ACTIVE; +} + +/** + * @brief Returns all busy DMA channels + * @param pDMA : The base of DMA controller on the chip + * @return An Or'ed value of all busy DMA channels (0 - 15) + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) is busy. A low state is not busy. A DMA + * channel is considered busy when there is any operation + * related to that channel in the DMA controller�s internal + * pipeline. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].BUSY; +} + +/** + * @brief Returns pending error interrupt status for all DMA channels + * @param pDMA : The base of DMA controller on the chip + * @return An Or'ed value of all channels (0 - 15) error interrupt status + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) has a pending error interrupt. A low state + * indicates no error interrupt. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetErrorIntChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].ERRINT; +} + +/** + * @brief Clears a pending error interrupt status for a single DMA channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_ClearErrorIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].ERRINT = (1 << ch); +} + +/** + * @brief Enables a single DMA channel's interrupt used in common DMA interrupt + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_EnableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].INTENSET = (1 << ch); +} + +/** + * @brief Disables a single DMA channel's interrupt used in common DMA interrupt + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_DisableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].INTENCLR = (1 << ch); +} + +/** + * @brief Returns all enabled interrupt channels + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) has an enabled interrupt for the channel. + * A low state indicates that the DMA channel will not contribute + * to the common DMA interrupt status. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetEnableIntChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].INTENSET; +} + +/** + * @brief Returns active A interrupt status for all channels + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) has an active A interrupt for the channel. + * A low state indicates that the A interrupt is not active. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetActiveIntAChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].INTA; +} + +/** + * @brief Clears active A interrupt status for a single channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].INTA = (1 << ch); +} + +/** + * @brief Returns active B interrupt status for all channels + * @param pDMA : The base of DMA controller on the chip + * @return Nothing + * @note A high values in bits 0 .. 15 in the return values indicates + * that the channel for that bit (bit 0 = channel 0, bit 1 - + * channel 1, etc.) has an active B interrupt for the channel. + * A low state indicates that the B interrupt is not active. + */ +__STATIC_INLINE uint32_t Chip_DMA_GetActiveIntBChannels(LPC_DMA_T *pDMA) +{ + return pDMA->DMACOMMON[0].INTB; +} + +/** + * @brief Clears active B interrupt status for a single channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].INTB = (1 << ch); +} + +/** + * @brief Sets the VALIDPENDING control bit for a single channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + * @note See the User Manual for more information for what this bit does. + * + */ +__STATIC_INLINE void Chip_DMA_SetValidChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].SETVALID = (1 << ch); +} + +/** + * @brief Sets the TRIG bit for a single channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + * @note See the User Manual for more information for what this bit does. + */ +__STATIC_INLINE void Chip_DMA_SetTrigChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].SETTRIG = (1 << ch); +} + +/** + * @brief Aborts a DMA operation for a single channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + * @note To abort a channel, the channel should first be disabled. Then wait + * until the channel is no longer busy by checking the corresponding + * bit in BUSY. Finally, abort the channel operation. This prevents the + * channel from restarting an incomplete operation when it is enabled + * again. + */ +__STATIC_INLINE void Chip_DMA_AbortChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + pDMA->DMACOMMON[0].ABORT = (1 << ch); +} + +/** + * @} + */ + +/** @defgroup DMALEG_CHANNEL_5410X CHIP: LPC5410X DMA Controller driver channel specific functions (legacy) + * @{ + */ + +/* DMA channel source/address/next descriptor */ +typedef struct { + uint32_t xfercfg; /*!< Transfer configuration (only used in linked lists and ping-pong configs) */ + uint32_t source; /*!< DMA transfer source end address */ + uint32_t dest; /*!< DMA transfer desintation end address */ + uint32_t next; /*!< Link to next DMA descriptor, must be 16 byte aligned */ +} DMA_CHDESC_T; + +/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase() + function if a DMA SRAM table is needed. */ +extern DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL]; + +/** + * @brief Setup a DMA channel configuration + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param cfg : An Or'ed value of DMA_CFG_* values that define the channel's configuration + * @return Nothing + * @note This function sets up all configurable options for the DMA channel. + * These options are usually set once for a channel and then unchanged.
+ * + * The following example show how to configure the channel for peripheral + * DMA requests, burst transfer size of 1 (in 'transfers', not bytes), + * continuous reading of the same source address, incrementing destination + * address, and highest channel priority.
+ * Example: Chip_DMA_SetupChannelConfig(pDMA, SSP0_RX_DMA, + * (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_1 | + * DMA_CFG_SRCBURSTWRAP | DMA_CFG_CHPRIORITY(0)));
+ * + * The following example show how to configure the channel for an external + * trigger from the imput mux with low edge polarity, a burst transfer size of 8, + * incrementing source and destination addresses, and lowest channel + * priority.
+ * Example: Chip_DMA_SetupChannelConfig(pDMA, DMA_CH14, + * (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGPOL_LOW | DMA_CFG_TRIGTYPE_EDGE | + * DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_8 | + * DMA_CFG_CHPRIORITY(3)));
+ * + * For non-peripheral DMA triggering (DMA_CFG_HWTRIGEN definition), use the + * DMA input mux functions to configure the DMA trigger source for a DMA channel. + */ +__STATIC_INLINE void Chip_DMA_SetupChannelConfig(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg) +{ + pDMA->DMACH[ch].CFG = cfg; +} + +/** + * @brief Returns channel specific status flags + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return AN Or'ed value of DMA_CTLSTAT_VALIDPENDING and DMA_CTLSTAT_TRIG + */ +__STATIC_INLINE uint32_t Chip_DMA_GetChannelStatus(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + return pDMA->DMACH[ch].XFERCFG; +} + +/** + * @brief Setup a DMA channel transfer configuration + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param cfg : An Or'ed value of DMA_XFERCFG_* values that define the channel's transfer configuration + * @return Nothing + * @note This function sets up the transfer configuration for the DMA channel.
+ * + * The following example show how to configure the channel's transfer for + * multiple transfer descriptors (ie, ping-pong), interrupt 'A' trigger on + * transfer descriptor completion, 128 byte size transfers, and source and + * destination address increment.
+ * Example: Chip_DMA_SetupChannelTransfer(pDMA, SSP0_RX_DMA, + * (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_RELOAD | DMA_XFERCFG_SETINTA | + * DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_1 | + * DMA_XFERCFG_XFERCOUNT(128)));
+ */ +__STATIC_INLINE void Chip_DMA_SetupChannelTransfer(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg) +{ + pDMA->DMACH[ch].XFERCFG = cfg; +} + +/** + * @brief Set DMA transfer register interrupt bits (safe) + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param mask : Bits to set + * @return Nothing + * @note This function safely sets bits in the DMA channel specific XFERCFG + * register. + */ +__STATIC_INLINE void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask) +{ + /* Read and write values may not be the same, write 0 to + undefined bits */ + pDMA->DMACH[ch].XFERCFG = (pDMA->DMACH[ch].XFERCFG | mask) & ~0xFC000CC0; + +} + +/** + * @brief Clear DMA transfer register interrupt bits (safe) + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param mask : Bits to clear + * @return Nothing + * @note This function safely clears bits in the DMA channel specific XFERCFG + * register. + */ +__STATIC_INLINE void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask) +{ + /* Read and write values may not be the same, write 0 to + undefined bits */ + pDMA->DMACH[ch].XFERCFG = pDMA->DMACH[ch].XFERCFG & ~(0xFC000CC0 | mask); + +} + +/** + * @brief Update the transfer size in an existing DMA channel transfer configuration + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param trans : Number of transfers to update the transfer configuration to (1 - 1023) + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans) +{ + Chip_DMA_ClearTranBits(pDMA, ch, (0x3FF << 16)); + Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_XFERCOUNT(trans)); +} + +/** + * @brief Sets a DMA channel configuration as valid + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_SetChannelValid(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID); +} + +/** + * @brief Sets a DMA channel configuration as invalid + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_SetChannelInValid(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + Chip_DMA_ClearTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID); +} + +/** + * @brief Performs a software trigger of the DMA channel + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @return Nothing + */ +__STATIC_INLINE void Chip_DMA_SWTriggerChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) +{ + Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_SWTRIG); +} + +/** + * @brief Sets up a DMA channel with the passed DMA transfer descriptor + * @param pDMA : The base of DMA controller on the chip + * @param ch : DMA channel ID + * @param desc : Pointer to DMA transfer descriptor + * @return false if the DMA channel was active, otherwise true + * @note This function will set the DMA descriptor in the SRAM table to the + * the passed descriptor. This function is only meant to be used when + * the DMA channel is not active and can be used to setup the + * initial transfer for a linked list or ping-pong buffer or just a + * single transfer without a next descriptor.
+ * + * If using this function to write the initial transfer descriptor in + * a linked list or ping-pong buffer configuration, it should contain a + * non-NULL 'next' field pointer. + */ +bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_5410X_H */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/error.h b/ports/lpc/chips/lpc_chip_5410x/inc/error.h new file mode 100644 index 0000000000000..201e6f7f51d6f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/error.h @@ -0,0 +1,272 @@ +/* + * @brief Error code returned by Boot ROM drivers/library functions + * + * This file contains unified error codes to be used across driver, + * middleware, applications, hal and demo software. + * + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_ERROR_H__ +#define __LPC_ERROR_H__ + +/** Error code returned by Boot ROM drivers/library functions + * + * Error codes are a 32-bit value with : + * - The 16 MSB contains the peripheral code number + * - The 16 LSB contains an error code number associated to that peripheral + * + */ +typedef enum { + /**\b 0x00000000*/ LPC_OK = 0, /**< enum value returned on Success */ + /**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */ + /**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */ + /**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */ + + /* ISP related errors */ + ERR_ISP_BASE = 0x00000000, + /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1, + /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */ + /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */ + /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED, + /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED, + /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */ + /*0x00000007*/ ERR_ISP_INVALID_SECTOR, + /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, + /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, + /*0x0000000A*/ ERR_ISP_COMPARE_ERROR, + /*0x0000000B*/ ERR_ISP_BUSY,/* Flash programming hardware interface is busy */ + /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */ + /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */ + /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED, + /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */ + /*0x00000010*/ ERR_ISP_INVALID_CODE,/* Unlock code is invalid */ + /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE, + /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT, + /*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED, + /*0x00000014*/ ERR_ISP_INVALID_FLASH_UNIT, + /*0x00000015*/ ERR_ISP_USER_CODE_CHECKSUM, + /*0x00000016*/ ERR_ISP_SETTING_ACTIVE_PARTITION, + /*0x00000017*/ ERR_ISP_IRC_NO_POWER, + /*0x00000018*/ ERR_ISP_FLASH_NO_POWER, + /*0x00000019*/ ERR_ISP_EEPROM_NO_POWER, + /*0x0000001A*/ ERR_ISP_EEPROM_NO_CLOCK, + /*0x0000001B*/ ERR_ISP_FLASH_NO_CLOCK, + /*0x0000001C*/ ERR_ISP_REINVOKE_ISP_CONFIG, + + /* ROM API related errors */ + ERR_API_BASE = 0x00010000, + /**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/ + /**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */ + /**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */ + /**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */ + /**\b 0x00010005*/ ERR_API_MOD_INIT,/**< API is called before module init */ + + /* SPIFI API related errors */ + ERR_SPIFI_BASE = 0x00020000, + /*0x00020001*/ ERR_SPIFI_DEVICE_ERROR = ERR_SPIFI_BASE + 1, + /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR, + /*0x00020003*/ ERR_SPIFI_TIMEOUT, + /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR, + /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM, + /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT, + /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID, + /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE, + /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG, + /*0x0002000A*/ ERR_SPIFI_NO_DEVICE, + /*0x0002000B*/ ERR_SPIFI_ERASE_NEEDED, + + SEC_AES_NO_ERROR = 0, + /* Security API related errors */ + ERR_SEC_AES_BASE = 0x00030000, + /*0x00030001*/ ERR_SEC_AES_WRONG_CMD = ERR_SEC_AES_BASE + 1, + /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED, + /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED, + /*0x00030004*/ ERR_SEC_AES_DMA_CHANNEL_CFG, + /*0x00030005*/ ERR_SEC_AES_DMA_MUX_CFG, + /*0x00030006*/ SEC_AES_DMA_BUSY, + + /* USB device stack related errors */ + ERR_USBD_BASE = 0x00040000, + /**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1,/**< invalid request */ + /**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */ + /**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */ + /**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */ + /**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */ + /**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/ + /**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC, /**< Bad config descriptor*/ + /**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC, /**< Bad interface descriptor*/ + /**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/ + /**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF,/**< Bad alignment of buffer passed. */ + /**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR,/**< Too many class handlers. */ + + /* CGU related errors */ + ERR_CGU_BASE = 0x00050000, + /*0x00050001*/ ERR_CGU_NOT_IMPL = ERR_CGU_BASE + 1, + /*0x00050002*/ ERR_CGU_INVALID_PARAM, + /*0x00050003*/ ERR_CGU_INVALID_SLICE, + /*0x00050004*/ ERR_CGU_OUTPUT_GEN, + /*0x00050005*/ ERR_CGU_DIV_SRC, + /*0x00050006*/ ERR_CGU_DIV_VAL, + /*0x00050007*/ ERR_CGU_SRC, + + /* I2C related errors */ + ERR_I2C_BASE = 0x00060000, + /*0x00060000*/ ERR_I2C_BUSY = ERR_I2C_BASE, + /*0x00060001*/ ERR_I2C_NAK, + /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, + /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, + /*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, + /*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, + /*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, + /*0x00060007*/ ERR_I2C_GENERAL_FAILURE, + /*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT, + /*0x00060009*/ ERR_I2C_TIMEOUT, + /*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW, + /*0x0006000B*/ ERR_I2C_PARAM, + + /* OTP related errors */ + ERR_OTP_BASE = 0x00070000, + /*0x00070001*/ ERR_OTP_WR_ENABLE_INVALID = ERR_OTP_BASE + 1, + /*0x00070002*/ ERR_OTP_SOME_BITS_ALREADY_PROGRAMMED, + /*0x00070003*/ ERR_OTP_ALL_DATA_OR_MASK_ZERO, + /*0x00070004*/ ERR_OTP_WRITE_ACCESS_LOCKED, + /*0x00070005*/ ERR_OTP_READ_DATA_MISMATCH, + /*0x00070006*/ ERR_OTP_USB_ID_ENABLED, + /*0x00070007*/ ERR_OTP_ETH_MAC_ENABLED, + /*0x00070008*/ ERR_OTP_AES_KEYS_ENABLED, + /*0x00070009*/ ERR_OTP_ILLEGAL_BANK, + + /* UART related errors */ + ERR_UART_BASE = 0x00080000, + /*0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE + 1, // UART rxd is busy + /*0x00080002*/ ERR_UART_TXD_BUSY, // UART txd is busy + /*0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, // overrun err, frame err, parity err, RxNoise err + /*0x00080004*/ ERR_UART_UNDERRUN, // underrun err + /*0x00080005*/ ERR_UART_PARAM, // parameter is error + /*0x00080006*/ ERR_UART_BAUDRATE, // baudrate setting is error + + /* CAN related errors */ + ERR_CAN_BASE = 0x00090000, + /*0x00090001*/ ERR_CAN_BAD_MEM_BUF = ERR_CAN_BASE + 1, + /*0x00090002*/ ERR_CAN_INIT_FAIL, + /*0x00090003*/ ERR_CANOPEN_INIT_FAIL, + + /* SPIFI Lite API related errors */ + ERR_SPIFI_LITE_BASE = 0x000A0000, + /*0x000A0001*/ ERR_SPIFI_LITE_INVALID_ARGUMENTS = ERR_SPIFI_LITE_BASE + 1, + /*0x000A0002*/ ERR_SPIFI_LITE_BUSY, + /*0x000A0003*/ ERR_SPIFI_LITE_MEMORY_MODE_ON, + /*0x000A0004*/ ERR_SPIFI_LITE_MEMORY_MODE_OFF, + /*0x000A0005*/ ERR_SPIFI_LITE_IN_DMA, + /*0x000A0006*/ ERR_SPIFI_LITE_NOT_IN_DMA, + /*0x000A0100*/ PENDING_SPIFI_LITE, + + /* CLK related errors */ + ERR_CLK_BASE = 0x000B0000, + /*0x000B0001*/ ERR_CLK_NOT_IMPL = ERR_CLK_BASE + 1, + /*0x000B0002*/ ERR_CLK_INVALID_PARAM, + /*0x000B0003*/ ERR_CLK_INVALID_SLICE, + /*0x000B0004*/ ERR_CLK_OUTPUT_GEN, + /*0x000B0005*/ ERR_CLK_DIV_SRC, + /*0x000B0006*/ ERR_CLK_DIV_VAL, + /*0x000B0007*/ ERR_CLK_SRC, + /*0x000B0008*/ ERR_CLK_PLL_FIN_TOO_SMALL, + /*0x000B0009*/ ERR_CLK_PLL_FIN_TOO_LARGE, + /*0x000B000A*/ ERR_CLK_PLL_FOUT_TOO_SMALL, + /*0x000B000B*/ ERR_CLK_PLL_FOUT_TOO_LARGE, + /*0x000B000C*/ ERR_CLK_PLL_NO_SOLUTION, + /*0x000B000D*/ ERR_CLK_PLL_MIN_PCT, + /*0x000B000E*/ ERR_CLK_PLL_MAX_PCT, + /*0x000B000F*/ ERR_CLK_OSC_FREQ, + /*0x000B0010*/ ERR_CLK_CFG, + /*0x000B0011*/ ERR_CLK_TIMEOUT, + /*0x000B0012*/ ERR_CLK_BASE_OFF, + /*0x000B0013*/ ERR_CLK_OFF_DEADLOCK, + + /*Power API*/ + ERR_PWR_BASE = 0x000C0000, + /*0x000C0001*/ PWR_ERROR_ILLEGAL_MODE = ERR_PWR_BASE + 1, + /*0x000C0002*/ PWR_ERROR_CLOCK_FREQ_TOO_HIGH, + /*0x000C0003*/ PWR_ERROR_INVALID_STATE, + /*0x000C0004*/ PWR_ERROR_INVALID_CFG, + /*0x000C0005*/ PWR_ERROR_PVT_DETECT, + /*0x000C0006*/ PWR_ERROR_INVALID_VOLTAGE, + + /* DMA related errors */ + ERR_DMA_BASE = 0x000D0000, + /*0x000D0001*/ ERR_DMA_ERROR_INT = ERR_DMA_BASE + 1, + /*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER, + /*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED, + /*0x000D0004*/ ERR_DMA_BUSY, + /*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT, + /*0x000D0006*/ ERR_DMA_PING_PONG_EN, + /*0x000D0007*/ ERR_DMA_CHANNEL_VALID_PENDING, + /*0x000D0008*/ ERR_DMA_PARAM, + /*0x000D0009*/ ERR_DMA_QUEUE_EMPTY, + /*0x000D000A*/ ERR_DMA_GENERAL, + + /* SPI related errors */ + ERR_SPI_BASE = 0x000E0000, + /*0x000E0000*/ ERR_SPI_BUSY = ERR_SPI_BASE, + /*0x000E0001*/ ERR_SPI_RXOVERRUN, + /*0x000E0002*/ ERR_SPI_TXUNDERRUN, + /*0x000E0003*/ ERR_SPI_SELNASSERT, + /*0x000E0004*/ ERR_SPI_SELNDEASSERT, + /*0x000E0005*/ ERR_SPI_CLKSTALL, + /*0x000E0006*/ ERR_SPI_PARAM, + /*0x000E0007*/ ERR_SPI_INVALID_LENGTH, + + /* ADC related errors */ + ERR_ADC_BASE = 0x000F0000, + /*0x000F0001*/ ERR_ADC_OVERRUN = ERR_ADC_BASE + 1, + /*0x000F0002*/ ERR_ADC_INVALID_CHANNEL, + /*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE, + /*0x000F0004*/ ERR_ADC_INVALID_SETUP, + /*0x000F0005*/ ERR_ADC_PARAM, + /*0x000F0006*/ ERR_ADC_INVALID_LENGTH, + /*0x000F0007*/ ERR_ADC_NO_POWER, + + /* Debugger Mailbox related errors */ + ERR_DM_BASE = 0x00100000, + /*0x00100001*/ ERR_DM_NOT_ENTERED = ERR_DM_BASE + 1, + /*0x00100002*/ ERR_DM_UNKNOWN_CMD, + /*0x00100003*/ ERR_DM_COMM_FAIL + +} ErrorCode_t; + +#ifndef offsetof +#define offsetof(s, m) (int) &(((s *) 0)->m) +#endif + +#define COMPILE_TIME_ASSERT(pred) switch (0) { \ + case 0: \ + case pred:; } + +#endif /* __LPC_ERROR_H__ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/fifo_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/fifo_5410x.h new file mode 100644 index 0000000000000..4cc1166766481 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/fifo_5410x.h @@ -0,0 +1,559 @@ +/* + * @brief LPC5410X System FIFO chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __FIFO_5410X_H_ +#define __FIFO_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup FIFO_5410X CHIP: LPC5410X System FIFO chip driver + * @ingroup CHIP_5410X_DRIVERS + * This driver provides basic functionality for the system FIFO + * and can be used to increase the amount of FIFO space available + * to the UART and SPI peripherals. If using the system FIFO with the + * UART or SPI drivers, the standard UART and SPI transfer handlers + * cannot be used and buffer/stream management and status checking + * must occur in the user application. + * @{ + */ + +/** Maximum USART peripherals */ +#define LPC_FIFO_USART_MAX (4) + +/** Maximum SPI peripherals */ +#define LPC_FIFO_SPI_MAX (2) + +/** + * @brief LPC5410X System FIFO USART register block structure + */ +typedef struct { + __IO uint32_t CFG; /*!< USART configuration Register */ + __IO uint32_t STAT; /*!< USART status Register */ + __IO uint32_t INTSTAT; /*!< USART interrupt status Register */ + __IO uint32_t CTLSET; /*!< USART control read and set Register */ + __IO uint32_t CTLCLR; /*!< USART control clear Register */ + __IO uint32_t RXDAT; /*!< USART received data Register */ + __IO uint32_t RXDATSTAT; /*!< USART received data with status Register */ + __IO uint32_t TXDAT; /*!< USART transmit data Register */ + __I uint32_t RESERVED[0x38]; +} LPC_FIFO_USART_T; + +/** + * @brief LPC5410X System FIFO SPI register block structure + */ +typedef struct { + __IO uint32_t CFG; /*!< SPI configuration Register */ + __IO uint32_t STAT; /*!< SPI status Register */ + __IO uint32_t INTSTAT; /*!< SPI interrupt status Register */ + __IO uint32_t CTLSET; /*!< SPI control read and set Register */ + __IO uint32_t CTLCLR; /*!< SPI control clear Register */ + __I uint32_t RXDAT; /*!< SPI received data Register */ + union { + __O uint32_t TXDATSPI; /*!< SPI transmit data and control Register */ + struct { + __O uint16_t TXDATSPI_DATA; /*!< SPI transmit data Register */ + __O uint16_t TXDATSPI_CTRL; /*!< SPI transmit control Register */ + }; + + }; + + __I uint32_t RESERVED[0x39]; +} LPC_FIFO_SPI_T; + +/** + * @brief LPC5410X System FIFO common register block structure + */ +typedef struct { + __I uint32_t reserved0[0x40]; + __IO uint32_t FIFOCTLUSART; /*!< USART FIFO global control Register */ + __O uint32_t FIFOUPDATEUSART; /*!< USART FIFO global update Register */ + __I uint32_t reserved1[0x2]; + __IO uint32_t FIFOCFGUSART[LPC_FIFO_USART_MAX]; /*!< USART FIFO configuration Registers */ + __I uint32_t reserved2[0x38]; + __IO uint32_t FIFOCTLSPI; /*!< SPI FIFO global control Register */ + __O uint32_t FIFOUPDATESPI; /*!< SPI FIFO global update Register */ + __I uint32_t reserved3[0x2]; + __IO uint32_t FIFOCFGSPI[LPC_FIFO_SPI_MAX]; /*!< SPI FIFO configuration Registers */ + __I uint32_t reserved4[0x3A]; + __I uint32_t reserved5[((0x1000 - 0x300) / sizeof(uint32_t))]; +} LPC_FIFO_CMN_T; + +/** + * @brief LPC5410X Complete system FIFO register block structure + */ +typedef struct { + LPC_FIFO_CMN_T common; + LPC_FIFO_USART_T usart[LPC_FIFO_USART_MAX]; + __I uint32_t reserved0[((0x2000 - 0x1400) / sizeof(uint32_t))]; + LPC_FIFO_SPI_T spi[LPC_FIFO_SPI_MAX]; +} LPC_FIFO_T; + +/** @defgroup FIFO_CMN_5410X CHIP: Common FIFO functions + * These functions are for both the USART and SPI configuration and + * status. + * @{ + */ + +/** + * @brief Initializes the system FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @return Nothing + */ +void Chip_FIFO_Init(LPC_FIFO_T *pFIFO); + +/** + * @brief Deinitializes the system FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @return Nothing + */ +void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO); + +/** USART/SPI peripheral identifier */ +typedef enum {FIFO_USART, FIFO_SPI} LPC_FIFO_PERIPHID_T; + +/** USART/SPI FIFO direction identifier */ +typedef enum {FIFO_RX, FIFO_TX} LPC_FIFO_DIR_T; + +/** + * @brief Get the FIFO space available for the USART/SPI direction + * @brief pFIFO : Pointer to system FIFO registers + * @brief periphId : Peripheral identifer + * @brief dir : FIFO direction + * @return Amount of FIFO space available for the peripheral + */ +uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); + +/** USART and SPI FIFO common statuses */ +#define LPC_FIFO_STAT_RXPAUSED (1 << 1) /*!< Receive FIFOs paused status */ +#define LPC_FIFO_STAT_RXEMPTY (1 << 2) /*!< Receive FIFOs empty status */ +#define LPC_FIFO_STAT_TXPAUSED (1 << 9) /*!< Transmit FIFOs paused status */ +#define LPC_FIFO_STAT_TXEMPTY (1 << 10) /*!< Transmit FIFOs empty status */ + +/** + * @brief Get periperhal FIFO status + * @brief pFIFO : Pointer to system FIFO registers + * @return A bitfield of status values, mask with LPC_FIFO_STAT_* values + * @note Mask with one or more LPC_FIFO_STAT_* definitions to get the + * status of the peripherals. + */ +__STATIC_INLINE uint32_t Chip_FIFO_GetFifoStatus(LPC_FIFO_T *pFIFO) +{ + return pFIFO->common.FIFOCTLUSART; +} + +/** + * @brief Pause a peripheral FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @brief periphId : Peripheral identifer + * @brief dir : FIFO direction + * @return Nothing + */ +void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); + +/** + * @brief Unpause a peripheral FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @brief periphId : Peripheral identifer + * @brief dir : FIFO direction + * @return Nothing + */ +void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); + +/** Stucture for setting USART or SPI FIFO sizes */ +typedef struct { + uint16_t fifoRXSize[4]; /*!< FIFO RX size, 0-3 for USARTS 0-3, or 0-1 for SPIS 0-1 */ + uint16_t fifoTXSize[4]; /*!< FIFO TX size, 0-3 for USARTS 0-3, or 0-1 for SPIS 0-1 */ +} LPC_FIFO_CFGSIZE_T; + +/** + * @brief Configure a peripheral's FIFO sizes + * @brief pFIFO : Pointer to system FIFO registers + * @brief periphId : Peripheral identifer + * @brief pSizes : Pointer to s structure filled out with the peripherla FIFO sizes + * @return Nothing + * @note This function configures all the FIFOs for a supported peripheral + * in a single call. Use 0 to disable the FIFO. This function will pause the FIFO + * and leave it paused after configuration, call Chip_FIFO_UnpauseFifo() after + * calling this function. + */ +void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes); + +/** Stucture for setting USART and SPI FIFO configuration */ +typedef struct { + uint32_t noTimeoutContWrite : 1; /*!< Timeout Continue On Write, set to 0 to reset timeout on each TX FIFO data, or 1 for accumulated timeout */ + uint32_t noTimeoutContEmpty : 1; /*!< Timeout Continue On Empty., set to 0 to reset timeout on each RX FIFO data, or 1 for accumulated timeout */ + uint32_t timeoutBase : 4; /*!< Specifies the least significant timer bit to compare to TimeoutValue. See User Manual */ + uint32_t timeoutValue : 4; /*!< Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. See User Manual */ + uint32_t rxThreshold : 8; /*!< Receive FIFO Threshold, number of data to receive prior to interrupt */ + uint32_t txThreshold : 8; /*!< Transmit FIFO Threshold, number of free TX data entries available prior to interrupt */ +} LPC_FIFO_CFG_T; + +/** USART and SPI FIFO statuses */ +#define LPC_PERIPFIFO_STAT_RXTH (1 << 0) /*!< When 1, the receive FIFO threshold has been reached */ +#define LPC_PERIPFIFO_STAT_TXTH (1 << 1) /*!< When 1, the transmit FIFO threshold has been reached */ +#define LPC_PERIPFIFO_STATCLR_RXTIMEOUT (1 << 4) /*!< When 1, the receive FIFO has timed out, based on the timeout configuration in the CFG register */ +#define LPC_PERIPFIFO_STATCLR_BUSERR (1 << 7) /*!< Bus Error. When 1, a bus error has occurred while processing data for the peripheral. The bus error flag can be cleared by writing a 1 to this bit. */ +#define LPC_PERIPFIFO_STAT_RXEMPTY (1 << 8) /*!< Receive FIFO Empty. When 1, the receive FIFO is currently empty. */ +#define LPC_PERIPFIFO_STAT_TXEMPTY (1 << 9) /*!< Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. */ + +/** USART interrupt enable/disable bits */ +#define LPC_PERIPFIFO_INT_RXTH (1 << 0) /*!< Receive FIFO Threshold Interrupt Enable */ +#define LPC_PERIPFIFO_INT_TXTH (1 << 1) /*!< Transmit FIFO Threshold Interrupt Enable */ +#define LPC_PERIPFIFO_INT_RXTIMEOUT (1 << 4) /*!< Receive FIFO Timeout Interrupt Enable */ +#define LPC_PERIPFIFO_INT_RXFLUSH (1 << 8) /*!< Receive FIFO flush */ +#define LPC_PERIPFIFO_INT_TXFLUSH (1 << 9) /*!< Transmit FIFO flush */ + +/** + * @} + */ + +/** @defgroup FIFO_USART_5410X CHIP: USART FIFO functions + * These functions are for both the USART configuration, control, and status. + * @{ + */ + +/** + * @brief Configure the USART system FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief pUSARTCfg : Pointer to USART configuration + * @return Nothing + */ +void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg); + +/** + * @brief Get USART FIFO statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @return USART system FIFO statuses (mask with LPC_PERIPFIFO_STAT* values) + */ +__STATIC_INLINE uint32_t Chip_FIFOUSART_GetStatus(LPC_FIFO_T *pFIFO, int usartIndex) +{ + return pFIFO->usart[usartIndex].STAT; +} + +/** + * @brief Get USART RX FIFO count + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @return Returns how many entries may be read from the receive FIFO. 0 = FIFO empty. + */ +__STATIC_INLINE uint32_t Chip_FIFOUSART_GetRxCount(LPC_FIFO_T *pFIFO, int usartIndex) +{ + return (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; +} + +/** + * @brief Get USART TC FIFO count + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @return Returns how many entries may be written to the transmit FIFO. 0 = FIFO full. + */ +__STATIC_INLINE uint32_t Chip_FIFOUSART_GetTxCount(LPC_FIFO_T *pFIFO, int usartIndex) +{ + return (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF; +} + +/** + * @brief Clear USART FIFO statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief clearMask : Mask of latched bits to cleared, Or'ed values of LPC_PERIPFIFO_STATCLR* + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOUSART_ClearStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t clearMask) +{ + pFIFO->usart[usartIndex].STAT = clearMask; +} + +/** + * @brief Get USART FIFO pending interrupt statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @return USART system FIFO pending interrupt statuses (mask with LPC_PERIPFIFO_STAT* values) + */ +__STATIC_INLINE uint32_t Chip_FIFOUSART_GetIntStatus(LPC_FIFO_T *pFIFO, int usartIndex) +{ + return pFIFO->usart[usartIndex].INTSTAT; +} + +/** + * @brief Enable USART system FIFO interrupts + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief intMask : Interrupts to enable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOUSART_EnableInts(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t intMask) +{ + pFIFO->usart[usartIndex].CTLSET = intMask; +} + +/** + * @brief Disable USART system FIFO interrupts + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief intMask : Interrupts to disable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOUSART_DisableInts(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t intMask) +{ + pFIFO->usart[usartIndex].CTLCLR = intMask; +} + +/** + * @brief Flush TX and/or RX USART system FIFOs + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief flushMask : FIFOS to flush (Or'ed LPC_PERIPFIFO_INT_RXFLUSH and/or LPC_PERIPFIFO_INT_TXFLUSH) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOUSART_FlushFIFO(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t flushMask) +{ + flushMask = flushMask & (LPC_PERIPFIFO_INT_RXFLUSH | LPC_PERIPFIFO_INT_TXFLUSH); + + pFIFO->usart[usartIndex].CTLSET = flushMask; + pFIFO->usart[usartIndex].CTLCLR = flushMask; +} + +/** + * @brief Write data to a USART system FIFO (non-blocking) + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief sz8 : Set to true for 8-bit or less data, or false for >8-bit + * @brief buff : Pointer to data in buffer to write + * @brief numData : Maximum number of data values to write + * @return The number of data values written to the USART system FIFO + */ +int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData); + +/** + * @brief Read data from a USART system FIFO (non-blocking) + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief sz8 : Set to true for 8-bit or less data, or false for >8-bit + * @brief buff : Pointer to data buffer to read into + * @brief numData : Maximum number of data values to read + * @return The number of data values read from the USART system FIFO + */ +int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData); + +/** USART FIFO read FIFO statuses */ +#define LPC_USARTRXFIFO_STAT_FRAMERR (1 << 13) /*!< Framing Error status flag */ +#define LPC_USARTRXFIFO_STAT_PARITYERR (1 << 14) /*!< Parity Error status flag */ +#define LPC_USARTRXFIFO_STAT_RXNOISE (1 << 15) /*!< Received Noise flag */ + +/** + * @brief Read data from a USART system FIFO with status (non-blocking) + * @brief pFIFO : Pointer to system FIFO registers + * @brief usartIndex : USART system FIFO index, 0 - 3 + * @brief buff : Pointer to data buffer to read into + * @brief numData : Maximum number of data values to read + * @return The number of data values with status read from the USART system FIFO. Mask + * the upper bits of each word in the buffer with the LPC_USARTRXFIFO_STAT_* flags to + * determine individual data status. + */ +int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData); + +/** + * @} + */ + +/** @defgroup FIFO_SPI_5410X CHIP: SPI FIFO functions + * These functions are for both the SPI configuration, control, and status. + * @{ + */ + +/** + * @brief Configure the SPI system FIFO + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @brief pUSARTCfg : Pointer to SPI configuration + * @return Nothing + */ +void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg); + +/** + * @brief Get SPI FIFO statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @return SPI system FIFO statuses (mask with LPC_PERIPFIFO_STAT* values) + */ +__STATIC_INLINE uint32_t Chip_FIFOSPI_GetStatus(LPC_FIFO_T *pFIFO, int spiIndex) +{ + return pFIFO->spi[spiIndex].STAT; +} + +/** + * @brief Get SPI RX FIFO count + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @return Returns how many entries may be read from the receive FIFO. 0 = FIFO empty. + */ +__STATIC_INLINE uint32_t Chip_FIFOSPI_GetRxCount(LPC_FIFO_T *pFIFO, int spiIndex) +{ + return (pFIFO->spi[spiIndex].STAT >> 16) & 0xFF; +} + +/** + * @brief Get SPI TX FIFO count + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @return Returns how many entries may be written to the transmit FIFO. 0 = FIFO full. + */ +__STATIC_INLINE uint32_t Chip_FIFOSPI_GetTxCount(LPC_FIFO_T *pFIFO, int spiIndex) +{ + return (pFIFO->spi[spiIndex].STAT >> 24) & 0xFF; +} + +/** + * @brief Clear SPI FIFO statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @brief clearMask : Mask of latched bits to cleared, Or'ed values of LPC_PERIPFIFO_STATCLR* + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOSPI_ClearStatus(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t clearMask) +{ + pFIFO->spi[spiIndex].STAT = clearMask; +} + +/** + * @brief Get SPI FIFO pending interrupt statuses + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @return SPI system FIFO pending interrupt statuses (mask with LPC_PERIPFIFO_STAT* values) + */ +__STATIC_INLINE uint32_t Chip_FIFOSPI_GetIntStatus(LPC_FIFO_T *pFIFO, int spiIndex) +{ + return pFIFO->spi[spiIndex].INTSTAT; +} + +/** + * @brief Enable SPI system FIFO interrupts + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @brief intMask : Interrupts to enable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOSPI_EnableInts(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t intMask) +{ + pFIFO->spi[spiIndex].CTLSET = intMask; +} + +/** + * @brief Disable SPI system FIFO interrupts + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @brief intMask : Interrupts to disable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOSPI_DisableInts(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t intMask) +{ + pFIFO->spi[spiIndex].CTLCLR = intMask; +} + +/** + * @brief Flush TX and/or RX SPI system FIFOs + * @brief pFIFO : Pointer to system FIFO registers + * @brief spiIndex : SPI system FIFO index, 0 - 1 + * @brief flushMask : FIFOS to flush (Or'ed LPC_PERIPFIFO_INT_RXFLUSH and/or LPC_PERIPFIFO_INT_TXFLUSH) + * @return Nothing + */ +__STATIC_INLINE void Chip_FIFOSPI_FlushFIFO(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t flushMask) +{ + flushMask = flushMask & (LPC_PERIPFIFO_INT_RXFLUSH | LPC_PERIPFIFO_INT_TXFLUSH); + + pFIFO->spi[spiIndex].CTLSET = flushMask; + pFIFO->spi[spiIndex].CTLCLR = flushMask; +} + +/** SPI transfer flags */ +#define LPC_SPIFIFO_FLAG_EOF (1 << 21) /*!< Add a delay between frames */ +#define LPC_SPIFIFO_FLAG_RXIGNORE (1 << 22) /*!< Ignore RX data */ + +/** SPI transfer error statuses */ +#define LPC_SPIFIFO_STAT_BUSY (0x0) /*!< SPI transfer busy/in progress */ +#define LPC_SPIFIFO_STAT_BADPARAM (0x1) /*!< SPI paramaters for transfer are invalid */ +#define LPC_SPIFIFO_STAT_TXUNDERRUN (0x2) /*!< Slave mode only, transmit FIFO underrun */ +#define LPC_SPIFIFO_STAT_RXOVERRUN (0x3) /*!< Slave mode only, receive FIFO overrun */ +#define LPC_SPIFIFO_STAT_COMPLETE (0xF) /*!< SPI transfer completed successfully */ + +#if 0 /* Sorry, not yet support */ +/** Stucture for SPI control */ +typedef struct { + uint32_t start : 1; /*!< Indicates transfer start, 0 = transfer resume, 1 = transfer start (automatically set by Chip_FIFOSPI_StartTransfer()) */ + uint32_t end : 1; /*!< Transfer wil end once buffers are empty */ + uint32_t sz8 : 1; /*!< Specifies the in and out buffer sizes, 0 = 16-bit, 1 = 8-bit */ + uint32_t sselNum : 2; /*!< SPI chip select number, 0 - 3 */ + void *inBuff; /*!< SPI transfer in data buffer pointer */ + uint32_t inIndex; /*!< SPI transfer in buffer index */ + void *outBuff; /*!< SPI transfer out data buffer pointer */ + uint32_t outIndex; /*!< SPI transfer out buffer index */ + uint32_t numData; /*!< Size of data both the receive and transfer buffers */ + int spiIndex; /*!< SPI system FIFO index, 0 - 1 */ +} LPC_FIFO_SPICTL_T; + +/** + * @brief Start a SPI data transfer (non-blocking) + * @brief pFIFO : Pointer to system FIFO registers + * @brief pSetupData : Pointer to SPI transfer setup structure + * @return Nothing + * @note Simply calls Chip_FIFOSPI_Transfer() with pSetupData->start = 1. + */ +void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData); + +/** + * @brief Feed a SPI data transfer (non-blocking) + * @brief pFIFO : Pointer to system FIFO registers + * @brief pSetupData : Pointer to SPI transfer setup structure + * @return Nothing + * @note Continues SPI transfer usng the system FIFO. + */ +void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData); + +#endif + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FIFO_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/fpu_init.h b/ports/lpc/chips/lpc_chip_5410x/inc/fpu_init.h new file mode 100644 index 0000000000000..86e71c89875a1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/fpu_init.h @@ -0,0 +1,52 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __FPU_INIT_H_ +#define __FPU_INIT_H_ + +/** + * @defgroup CHIP_FPU_CMX CHIP: FPU initialization + * @ingroup CHIP_Common + * Cortex FPU initialization + * @{ + */ + +/** + * @brief Early initialization of the FPU + * @return Nothing + */ +void fpuInit(void); + +/** + * @} + */ + +#endif /* __FPU_INIT_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/gpio_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/gpio_5410x.h new file mode 100644 index 0000000000000..082ce0649adcf --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/gpio_5410x.h @@ -0,0 +1,471 @@ +/* + * @brief LPC5410X GPIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIO_5410X_H_ +#define __GPIO_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIO_5410X CHIP: LPC5410X GPIO driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief GPIO port register block structure + */ +typedef struct { /*!< GPIO_PORT Structure */ + __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */ + __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */ + __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */ + __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */ + __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */ + __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */ + __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */ + __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */ + __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */ +} LPC_GPIO_T; + +/** + * @brief Initialize GPIO block + * @param pGPIO : The base of GPIO peripheral on the chip + * @return Nothing + */ +void Chip_GPIO_Init(LPC_GPIO_T *pGPIO); + +/** + * @brief De-Initialize GPIO block + * @param pGPIO : The base of GPIO peripheral on the chip + * @return Nothing + */ +void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO); + +/** + * @brief Set a GPIO port/pin state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set + * @param setting : true for high, false for low + * @return Nothing + * @note It is recommended to use the Chip_GPIO_SetPinState() function instead. + */ +__STATIC_INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting) +{ + pGPIO->B[port][pin] = setting; +} + +/** + * @brief Set a GPIO pin state via the GPIO byte register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set + * @param setting : true for high, false for low + * @return Nothing + * @note This function replaces Chip_GPIO_WritePortBit() + */ +__STATIC_INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting) +{ + pGPIO->B[port][pin] = setting; +} + +/** + * @brief Read a GPIO pin state via the GPIO byte register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read + * @param pin : GPIO pin to read + * @return true if the GPIO pin is high, false if low + * @note It is recommended to use the Chip_GPIO_GetPinState() function instead. + */ +__STATIC_INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin) +{ + return (bool) pGPIO->B[port][pin]; +} + +/** + * @brief Get a GPIO pin state via the GPIO byte register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read + * @param pin : GPIO pin to get state for + * @return true if the GPIO is high, false if low + * @note This function replaces Chip_GPIO_ReadPortBit() + */ +__STATIC_INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + return (bool) pGPIO->B[port][pin]; +} + +/** + * @brief Set GPIO direction for a single GPIO pin + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set + * @param setting : true for output, false for input + * @return Nothing + * @note It is recommended to use the Chip_GPIO_SetPinDIROutput(), + * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead + * of this function. + */ +void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting); + +/** + * @brief Set GPIO direction for a single GPIO pin to an output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set direction on as output + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->DIR[port] |= 1UL << pin; +} + +/** + * @brief Set GPIO direction for a single GPIO pin to an input + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set direction on as input + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->DIR[port] &= ~(1UL << pin); +} + +/** + * @brief Set GPIO direction for a single GPIO pin + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to set + * @param pin : GPIO pin to set direction for + * @param output : true for output, false for input + * @return Nothing + */ +void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output); + +/** + * @brief Read a GPIO direction (out or in) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read + * @param bit : GPIO bit direction to read + * @return true if the GPIO is an output, false if input + * @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead. + */ +__STATIC_INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit) +{ + return (bool) (((pGPIO->DIR[port]) >> bit) & 1); +} + +/** + * @brief Get GPIO direction for a single GPIO pin + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : GPIO port to read (supports port 0 only) + * @param pin : GPIO pin to get direction for + * @return true if the GPIO is an output, false if input + */ +__STATIC_INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + return Chip_GPIO_ReadDirBit(pGPIO, port, pin); +} + +/** + * @brief Set Direction for a GPIO port + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port Number + * @param bitValue : GPIO bit to set + * @param out : Direction value, 0 = input, !0 = output + * @return None + * @note Bits set to '0' are not altered. It is recommended to use the + * Chip_GPIO_SetPortDIR() function instead. + */ +void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out); + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n) + * @return Nothing + * @note Sets multiple GPIO pins to the output direction, each bit's position that is + * high sets the corresponding pin number for that bit to an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) +{ + pGPIO->DIR[port] |= pinMask; +} + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an input + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n) + * @return Nothing + * @note Sets multiple GPIO pins to the input direction, each bit's position that is + * high sets the corresponding pin number for that bit to an input. + */ +__STATIC_INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) +{ + pGPIO->DIR[port] &= ~pinMask; +} + +/** + * @brief Set GPIO direction for a all selected GPIO pins to an input or output + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n) + * @param outSet : Direction value, false = set as inputs, true = set as outputs + * @return Nothing + * @note Sets multiple GPIO pins to the input direction, each bit's position that is + * high sets the corresponding pin number for that bit to an input. + */ +void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet); + +/** + * @brief Get GPIO direction for a all GPIO pins + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number + * @return a bitfield containing the input and output states for each pin + * @note For pins 0..n, a high state in a bit corresponds to an output state for the + * same pin, while a low state corresponds to an input state. + */ +__STATIC_INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->DIR[port]; +} + +/** + * @brief Set GPIO port mask value for GPIO masked read and write + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param mask : Mask value for read and write + * @return Nothing + * @note Controls which bits corresponding to PIO0_n are active in the P0MPORT + * register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17). + */ +__STATIC_INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask) +{ + pGPIO->MASK[port] = mask; +} + +/** + * @brief Get GPIO port mask value used for GPIO masked read and write + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @return Returns value set with the Chip_GPIO_SetPortMask() function. + */ +__STATIC_INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->MASK[port]; +} + +/** + * @brief Set all GPIO raw pin states (regardless of masking) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param value : Value to set all GPIO pin states (0..n) to + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) +{ + pGPIO->PIN[port] = value; +} + +/** + * @brief Get all GPIO raw pin states (regardless of masking) + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @return Current (raw) state of all GPIO pins + */ +__STATIC_INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->PIN[port]; +} + +/** + * @brief Set all GPIO pin states, but mask via the MASKP0 register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param value : Value to set all GPIO pin states (0..n) to + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) +{ + pGPIO->MPIN[port] = value; +} + +/** + * @brief Get all GPIO pin statesm but mask via the MASKP0 register + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @return Current (masked) state of all GPIO pins + */ +__STATIC_INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port) +{ + return pGPIO->MPIN[port]; +} + +/** + * @brief Set a GPIO port/bit to the high state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number (supports port 0 only) + * @param bitValue : bit(s) in the port to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. It is recommended to use the + * Chip_GPIO_SetPortOutHigh() function instead. + */ +__STATIC_INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) +{ + pGPIO->SET[portNum] = bitValue; +} + +/** + * @brief Set selected GPIO output pins to the high state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pins : pins (0..n) to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->SET[port] = pins; +} + +/** + * @brief Set an individual GPIO output pin to the high state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pin : pin number (0..n) to set high + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->SET[port] = (1 << pin); +} + +/** + * @brief Set a GPIO port/bit to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number (support port 0 only) + * @param bitValue : bit(s) in the port to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. It is recommended to use the + * Chip_GPIO_SetPortOutLow() function instead. + */ +__STATIC_INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) +{ + pGPIO->CLR[portNum] = bitValue; +} + +/** + * @brief Set selected GPIO output pins to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pins : pins (0..n) to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->CLR[port] = pins; +} + +/** + * @brief Set an individual GPIO output pin to the low state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pin : pin number (0..n) to set low + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->CLR[port] = (1 << pin); +} + +/** + * @brief Toggle selected GPIO output pins to the opposite state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pins : pins (0..n) to toggle + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) +{ + pGPIO->NOT[port] = pins; +} + +/** + * @brief Toggle an individual GPIO output pin to the opposite state + * @param pGPIO : The base of GPIO peripheral on the chip + * @param port : port Number (supports port 0 only) + * @param pin : pin number (0..n) to toggle + * @return None + * @note Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +__STATIC_INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) +{ + pGPIO->NOT[port] = (1 << pin); +} + +/** + * @brief Read current bit states for the selected port + * @param pGPIO : The base of GPIO peripheral on the chip + * @param portNum : port number to read (supports port 0 only) + * @return Current value of GPIO port + * @note The current states of the bits for the port are read, regardless of + * whether the GPIO port bits are input or output. It is recommended to use the + * Chip_GPIO_GetPortValue() function instead. + */ +__STATIC_INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum) +{ + return pGPIO->PIN[portNum]; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/gpiogroup_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/gpiogroup_5410x.h new file mode 100644 index 0000000000000..ded0bb479fb0d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/gpiogroup_5410x.h @@ -0,0 +1,223 @@ +/* + * @brief LPC5410x GPIO group driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIOGROUP_5410X_H_ +#define __GPIOGROUP_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIOGP_5410X CHIP: LPC5410X GPIO group driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief GPIO grouped interrupt register block structure + */ +typedef struct { /*!< GPIO_GROUP_INTn Structure */ + __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */ + uint32_t RESERVED1[4072]; +} LPC_GPIOGROUPINT_T; + +/** + * LPC5410x GPIO group bit definitions + */ +#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */ +#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */ +#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */ + +/** + * @brief Initialize GPIO group interrupt block + * @param pGPIOGPINT : The base of GPIO group peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIOGP_Init(LPC_GPIOGROUPINT_T *pGPIOGPINT) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GINT); + Chip_SYSCON_PeriphReset(RESET_GINT); +} + +/** + * @brief De-Initialize GPIO group interrupt block + * @param pGPIOGPINT : The base of GPIO group peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_GPIOGP_DeInit(LPC_GPIOGROUPINT_T *pGPIOGPINT) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GINT); +} + +/** + * @brief Clear interrupt pending status for the selected group + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL |= GPIOGR_INT; +} + +/** + * @brief Returns current GPIO group inetrrupt pending status + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return true if the group interrupt is pending, otherwise false. + */ +__STATIC_INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0); +} + +/** + * @brief Selected GPIO group functionality for trigger on any pin in group (OR mode) + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL &= ~(GPIOGR_COMB | GPIOGR_INT); +} + +/** + * @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode) + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_COMB; +} + +/** + * @brief Selected GPIO group functionality edge trigger mode + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL &= ~(GPIOGR_TRIG | GPIOGR_INT); +} + +/** + * @brief Selected GPIO group functionality level trigger mode + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) +{ + pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_TRIG; +} + +/** + * @brief Set selected pins for the group and port to low level trigger + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_POL[port] &= ~pinMask; +} + +/** + * @brief Set selected pins for the group and port to high level trigger + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + */ +__STATIC_INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_POL[port] |= pinMask; +} + +/** + * @brief Disabled selected pins for the group interrupt + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + * @note Disabled pins do not contribute to the group interrupt. + */ +__STATIC_INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask; +} + +/** + * @brief Enable selected pins for the group interrupt + * @param pGPIOGPINT : Pointer to GPIO group register block + * @param group : GPIO group number + * @param port : GPIO port number + * @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) + * @return None + * @note Enabled pins contribute to the group interrupt. + */ +__STATIC_INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, + uint8_t group, + uint8_t port, + uint32_t pinMask) +{ + pGPIOGPINT[group].PORT_ENA[port] |= pinMask; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIOGROUP_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/i2c_common_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/i2c_common_5410x.h new file mode 100644 index 0000000000000..0aa8d68ea4996 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/i2c_common_5410x.h @@ -0,0 +1,526 @@ +/* + * @brief LPC5410x I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2C_COMMON_5410X_H_ +#define __I2C_COMMON_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2C_5410X CHIP: LPC5410x I2C driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief I2C register block structure + */ +typedef struct { /* I2C0 Structure */ + __IO uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */ + __IO uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */ + __IO uint32_t INTENSET; /*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */ + __O uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */ + __IO uint32_t TIMEOUT; /*!< I2C Timeout value Register */ + __IO uint32_t CLKDIV; /*!< I2C Clock Divider Register */ + __IO uint32_t INTSTAT; /*!< I2C Interrupt Status Register */ + __I uint32_t RESERVED0; + __IO uint32_t MSTCTL; /*!< I2C Master Control Register */ + __IO uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */ + __IO uint32_t MSTDAT; /*!< I2C Master Data Register */ + __I uint32_t RESERVED1[5]; + __IO uint32_t SLVCTL; /*!< I2C Slave Control Register */ + __IO uint32_t SLVDAT; /*!< I2C Slave Data Register */ + __IO uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */ + __IO uint32_t SLVQUAL0; /*!< I2C Slave Address Qualifier 0 Register */ + __I uint32_t RESERVED2[9]; + __IO uint32_t MONRXDAT; /*!< I2C Monitor Data Register */ +} LPC_I2C_T; + +/* + * @brief I2C Configuration register Bit definition + */ +#define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */ +#define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */ +#define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */ +#define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */ +#define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */ +#define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration Register Mask */ + +/* + * @brief I2C Status register Bit definition + */ +#define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */ +#define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */ +#define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */ +#define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */ +#define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */ +#define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */ +#define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */ +#define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */ +#define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */ +#define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */ +#define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */ +#define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */ +#define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */ +#define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */ +#define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */ +#define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */ + +#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ + +#define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */ +#define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */ +#define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */ + +/* + * @brief I2C Interrupt Enable Set register Bit definition + */ +#define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */ +#define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */ +#define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */ +#define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */ +#define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */ +#define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */ +#define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */ +#define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */ +#define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */ +#define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */ +#define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */ + +/* + * @brief I2C Interrupt Enable Clear register Bit definition + */ +#define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */ +#define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */ +#define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */ +#define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */ +#define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */ +#define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */ +#define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */ +#define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */ + +/* + * @brief I2C TimeOut Value Macro + */ +#define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */ + +/* + * @brief I2C Interrupt Status register Bit definition + */ +#define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */ +#define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */ +#define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */ +#define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */ +#define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */ +#define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */ +#define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */ +#define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */ +#define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */ +#define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */ +#define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */ + +/* + * @brief I2C Master Control register Bit definition + */ +#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */ +#define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */ +#define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */ +#define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */ + +/* + * @brief I2C Master Time Register Field definition + */ +#define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */ +#define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */ + +/* + * @brief I2C Master Data Mask + */ +#define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */ + +/* + * @brief I2C Slave Control register Bit definition + */ +#define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */ +#define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */ +#define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */ + +/* + * @brief I2C Slave Data Mask + */ +#define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */ + +/* + * @brief I2C Slave Address register Bit definition + */ +#define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */ +#define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */ +#define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */ + +/* + * @brief I2C Slave Address Qualifier 0 Register Bit definition + */ +#define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */ +#define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */ + +/* + * @brief I2C Monitor Data Register Bit definition + */ +#define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */ +#define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */ +#define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */ +#define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */ + +/* + * @brief I2C Configuration register Bit definition + */ +#define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */ +#define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */ +#define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */ +#define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */ +#define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */ +#define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration Register Mask */ + +/* + * @brief I2C Status register Bit definition + */ +#define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */ +#define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */ +#define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */ +#define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */ +#define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */ +#define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */ +#define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */ +#define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */ +#define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */ +#define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */ +#define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */ +#define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */ +#define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */ +#define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */ +#define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */ +#define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */ + +#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ + +#define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */ +#define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */ +#define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */ + +/* + * @brief I2C Interrupt Enable Set register Bit definition + */ +#define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */ +#define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */ +#define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */ +#define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */ +#define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */ +#define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */ +#define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */ +#define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */ +#define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */ +#define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */ +#define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */ + +/* + * @brief I2C Interrupt Enable Clear register Bit definition + */ +#define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */ +#define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */ +#define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */ +#define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */ +#define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */ +#define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */ +#define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */ +#define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */ +#define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */ + +/* + * @brief I2C TimeOut Value Macro + */ +#define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */ + +/* + * @brief I2C Interrupt Status register Bit definition + */ +#define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */ +#define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */ +#define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */ +#define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */ +#define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */ +#define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */ +#define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */ +#define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */ +#define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */ +#define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */ +#define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */ + +/* + * @brief I2C Master Control register Bit definition + */ +#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */ +#define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */ +#define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */ +#define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */ + +/* + * @brief I2C Master Time Register Field definition + */ +#define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */ +#define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */ + +/* + * @brief I2C Master Data Mask + */ +#define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */ + +/* + * @brief I2C Slave Control register Bit definition + */ +#define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */ +#define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */ +#define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */ + +/* + * @brief I2C Slave Data Mask + */ +#define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */ + +/* + * @brief I2C Slave Address register Bit definition + */ +#define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */ +#define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */ +#define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */ + +/* + * @brief I2C Slave Address Qualifier 0 Register Bit definition + */ +#define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */ +#define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */ + +/* + * @brief I2C Monitor Data Register Bit definition + */ +#define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */ +#define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */ +#define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */ +#define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */ + +/** + * @brief Initialize I2C Interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function enables the I2C clock for both the master and + * slave interfaces if the I2C channel. + + */ +__STATIC_INLINE void Chip_I2C_Init(LPC_I2C_T *pI2C) +{ + /* Compiler must be able to optimize out non applicable cases */ + switch ((uint32_t) pI2C) { + case LPC_I2C2_BASE: + /* Enable clock to I2C peripheral and reset */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_I2C2); + Chip_SYSCON_PeriphReset(RESET_I2C2); + return; + + case LPC_I2C1_BASE: + /* Enable clock to I2C peripheral and reset */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_I2C1); + Chip_SYSCON_PeriphReset(RESET_I2C1); + return; + + default: + /* Enable clock to I2C peripheral and reset */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_I2C0); + Chip_SYSCON_PeriphReset(RESET_I2C0); + return; + } +} + +/** + * @brief Shutdown I2C Interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function disables the I2C clock for both the master and + * slave interfaces if the I2C channel. + */ +__STATIC_INLINE void Chip_I2C_DeInit(LPC_I2C_T *pI2C) +{ + /* Compiler must be able to optimize out non applicable cases */ + switch ((uint32_t) pI2C) { + case LPC_I2C2_BASE: + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_I2C2); + return; + + case LPC_I2C1_BASE: + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_I2C1); + return; + + default: + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_I2C0); + return; + } +} + +/** + * @brief Sets register bit values with mask + * @param pReg32 : Pointer to 32-bit register to set bits for + * @param mask : Zero write mask, will mask these bits are write back as 0 + * @param bits : Bits to set + * @return Nothing + * @note This function is needed for read-modify-write operations where the register + * being changed has read bits that are undefined, but must be written back as 0. + */ +static INLINE void Chip_I2C_SetRegMask(volatile uint32_t *pReg32, uint32_t mask, uint32_t bits) +{ + *pReg32 = (*pReg32 & mask) | bits; +} + +/** + * @brief Clears register bit values with mask + * @param pReg32 : Pointer to 32-bit register to clear bits for + * @param mask : Zero write mask, will mask these bits are write back as 0 + * @param bits : Bits to clear + * @return Nothing + * @note This function is needed for read-modify-write operations where the register + * being changed has read bits that are undefined, but must be written back as 0. + */ +static INLINE void Chip_I2C_ClearRegMask(volatile uint32_t *pReg32, uint32_t mask, uint32_t bits) +{ + *pReg32 = (*pReg32 & mask) & ~bits; +} + +/** + * @brief Sets I2C Clock Divider registers + * @param pI2C : Pointer to selected I2C peripheral + * @param clkdiv : Clock Divider value for I2C, value is between (1 - 65536) + * @return Nothing + * @note The clock to I2C block is determined by the following formula (I2C_PCLK + * is the frequency of the system clock):
+ * I2C Clock Frequency = (I2C_PCLK)/clkdiv;
+ * This divider must be setup for both the master and slave modes of the + * controller. When used in master mode, this divider is used with the MSTTIME + * register to generate the master I2C clock. Since the MSTTIME register has a + * limited range of divide values, this value should be selected to give an I2C + * clock rate that is about 2x to 18x greater than the desired master clock rate. + */ +__STATIC_INLINE void Chip_I2C_SetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv) +{ + if ((clkdiv >= 1) && (clkdiv <= 65536)) { + pI2C->CLKDIV = clkdiv - 1; + } + else { + pI2C->CLKDIV = 0; + } +} + +/** + * @brief Get I2C Clock Divider registers + * @param pI2C : Pointer to selected I2C peripheral + * @return Clock Divider value + * @note Return the divider value for the I2C block + * It is the CLKDIV register value + 1 + */ +static INLINE uint32_t Chip_I2C_GetClockDiv(LPC_I2C_T *pI2C) +{ + return (pI2C->CLKDIV & 0xFFFF) + 1; +} + +/** + * @brief Enable I2C Interrupts + * @param pI2C : Pointer to selected I2C peripheral + * @param intEn : ORed Value of I2C_INTENSET_* values to enable + * @return Nothing + */ +static INLINE void Chip_I2C_EnableInt(LPC_I2C_T *pI2C, uint32_t intEn) +{ + pI2C->INTENSET = intEn; +} + +/** + * @brief Disable I2C Interrupts + * @param pI2C : Pointer to selected I2C peripheral + * @param intClr : ORed Value of I2C_INTENSET_* values to disable + * @return Nothing + */ +static INLINE void Chip_I2C_DisableInt(LPC_I2C_T *pI2C, uint32_t intClr) +{ + pI2C->INTENCLR = intClr; +} + +/** + * @brief Disable I2C Interrupts + * @param pI2C : Pointer to selected I2C peripheral + * @param intClr : ORed Value of I2C_INTENSET_* values to disable + * @return Nothing + * @note It is recommended to use the Chip_I2C_DisableInt() function + * instead of this function. + */ +static INLINE void Chip_I2C_ClearInt(LPC_I2C_T *pI2C, uint32_t intClr) +{ + Chip_I2C_DisableInt(pI2C, intClr); +} + +/** + * @brief Returns pending I2C Interrupts + * @param pI2C : Pointer to selected I2C peripheral + * @return All pending interrupts, mask with I2C_INTENSET_* to determine specific interrupts + */ +static INLINE uint32_t Chip_I2C_GetPendingInt(LPC_I2C_T *pI2C) +{ + return pI2C->INTSTAT; +} + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __I2C_COMMON_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/i2cm_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/i2cm_5410x.h new file mode 100644 index 0000000000000..46bfc108c5637 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/i2cm_5410x.h @@ -0,0 +1,318 @@ +/* + * @brief LPC5410x I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2CM_5410X_H_ +#define __I2CM_5410X_H_ + +#include "i2c_common_5410x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2CM_5410X CHIP: LPC5410X I2C master-only driver + * @ingroup I2C_5410X + * This driver only works in master mode. To describe the I2C transactions + * following symbols are used in driver documentation. + * + * Key to symbols + * ============== + * S (1 bit) : Start bit + * P (1 bit) : Stop bit + * Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0. + * A, NA (1 bit) : Acknowledge and Not-Acknowledge bit. + * Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to + * get a 10 bit I2C address. + * Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh + * for 16 bit data. + * [..]: Data sent by I2C device, as opposed to data sent by the host adapter. + * @{ + */ + +/** I2CM_5410X_STATUS_TYPES I2C master transfer status types + */ + +#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */ +#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */ +#define I2CM_STATUS_NAK_ADR 0x02 /*!< No acknowledgement received from slave during address phase. */ +#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */ +#define I2CM_STATUS_NAK_DAT 0x04 /*!< No acknowledgement received from slave during address phase. */ +#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */ +#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmistter is busy. */ + +/** + * @brief Master transfer data structure definitions + */ +typedef struct { + const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */ + uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */ + volatile uint16_t txSz; /*!< Number of bytes in transmit array, + if 0 only receive transfer will be carried on */ + volatile uint16_t rxSz; /*!< Number of bytes to received, + if 0 only transmission we be carried on */ + volatile uint16_t status; /*!< Status of the current I2C transfer */ + uint8_t slaveAddr; /*!< 7-bit I2C Slave address */ +} I2CM_XFER_T; + +/** + * @brief Sets HIGH and LOW duty cycle registers + * @param pI2C : Pointer to selected I2C peripheral + * @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time value between (2 - 9). + * @param sclL : Number of I2C_PCLK cycles for the SCL LOW time value between (2 - 9). + * @return Nothing + * @note The I2C clock divider should be set to the appropriate value before calling this function + * The I2C baud is determined by the following formula:
+ * I2C_bitFrequency = (I2C_PCLK)/(I2C_CLKDIV * (sclH + sclL))
+ * where I2C_PCLK is the frequency of the System clock and I2C_CLKDIV is I2C clock divider + */ +void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL); + +/** + * @brief Set up bus speed for LPC_I2C controller + * @param pI2C : Pointer to selected I2C peripheral + * @param busSpeed : I2C bus clock rate + * @return Nothing + * @note Per I2C specification the busSpeed should be + * @li 100000 for Standard mode + * @li 400000 for Fast mode + * @li 1000000 for Fast mode plus + * IOCON registers corresponding to I2C pads should be updated + * according to the bus mode. + */ +void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed); + +/** + * @brief Enable I2C Master interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note + */ +static INLINE void Chip_I2CM_Enable(LPC_I2C_T *pI2C) +{ + Chip_I2C_SetRegMask(&pI2C->CFG, I2C_CFG_MASK, I2C_CFG_MSTEN); +} + +/** + * @brief Disable I2C Master interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note + */ +static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C) +{ + Chip_I2C_ClearRegMask(&pI2C->CFG, I2C_CFG_MASK, I2C_CFG_MSTEN); +} + +/** + * @brief Get I2C Status + * @param pI2C : Pointer to selected I2C peripheral + * @return I2C Status register value + * @note This function returns the value of the status register. + */ +static INLINE uint32_t Chip_I2CM_GetStatus(LPC_I2C_T *pI2C) +{ + return pI2C->STAT; +} + +/** + * @brief Clear I2C status bits (master) + * @param pI2C : Pointer to selected I2C peripheral + * @param clrStatus : Status bit to clear, ORed Value of I2C_STAT_MSTRARBLOSS and I2C_STAT_MSTSTSTPERR + * @return Nothing + * @note This function clears selected status flags. + */ +static INLINE void Chip_I2CM_ClearStatus(LPC_I2C_T *pI2C, uint32_t clrStatus) +{ + /* Clear Master Arbitration Loss and Start, Stop Error */ + pI2C->STAT = clrStatus & (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); +} + +/** + * @brief Check if I2C Master is pending + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns TRUE if the Master is pending else returns FALSE + * @note + */ +static INLINE bool Chip_I2CM_IsMasterPending(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_MSTPENDING) != 0; +} + +/** + * @brief Get current state of the I2C Master + * @param pI2C : Pointer to selected I2C peripheral + * @return Master State Code, a value in the range of 0 - 4 + * @note After the Master is pending this state code tells the reason + * for Master pending. + */ +static INLINE uint32_t Chip_I2CM_GetMasterState(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_MSTSTATE) >> 1; +} + +/** + * @brief Transmit START or Repeat-START signal on I2C bus + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to transmit START condition when + * the bus becomes free. This should be called only when master is pending. + * The function writes a complete value to Master Control register, ORing is not advised. + */ +static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C) +{ + pI2C->MSTCTL = I2C_MSTCTL_MSTSTART; +} + +/** + * @brief Transmit STOP signal on I2C bus + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the controller to transmit STOP condition. + * This should be called only when master is pending. The function writes a + * complete value to Master Control register, ORing is not advised. + */ +static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C) +{ + pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP; +} + +/** + * @brief Master Continue transfer operation + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the master controller to continue transmission. + * This should be called only when master is pending. The function writes a + * complete value to Master Control register, ORing is not advised. + */ +static INLINE void Chip_I2CM_MasterContinue(LPC_I2C_T *pI2C) +{ + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; +} + +/** + * @brief Transmit a single data byte through the I2C peripheral (master) + * @param pI2C : Pointer to selected I2C peripheral + * @param data : Byte to transmit + * @return Nothing + * @note This function attempts to place a byte into the I2C Master + * Data Register + * + */ +static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data) +{ + pI2C->MSTDAT = (uint32_t) data; +} + +/** + * @brief Read a single byte data from the I2C peripheral (master) + * @param pI2C : Pointer to selected I2C peripheral + * @return A single byte of data read + * @note This function reads a byte from the I2C receive hold register + * regardless of I2C state. + */ +static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C) +{ + return (uint8_t) (pI2C->MSTDAT & I2C_MSTDAT_DATAMASK); +} + +/** + * @brief Transfer state change handler + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Returns non-zero value on completion of transfer. The @a status + * member of @a xfer structure contains the current status of the + * transfer at the end of the call. + * @note + * The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer() + * routine. This function should be called from the I2C interrupt handler + * only when a master interrupt occurs. + */ +uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @brief Transmit and Receive data in master mode + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Nothing + * @note + * The parameter @a xfer should have its member @a slaveAddr initialized + * to the 7-Bit slave address to which the master will do the xfer, Bit0 + * to bit6 should have the address and Bit8 is ignored. During the transfer + * no code (like event handler) must change the content of the memory + * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be + * initialized to the memory from which the I2C must pick the data to be + * transfered to slave and the number of bytes to send respectively, similarly + * @a rxBuff and @a rxSz must have pointer to memroy where data received + * from slave be stored and the number of data to get from slave respectilvely. + * Following types of transfers are possible: + * - Write-only transfer: When @a rxSz member of @a xfer is set to 0. + * + * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P + * + * - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber + * + * S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P + * + * - Read-only transfer: When @a txSz member of @a xfer is set to 0. + * + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P + * + * - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber + * + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P + * + * - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero. + * + * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] + * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P + * + */ +void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @brief Transmit and Receive data in master mode + * @param pI2C : Pointer to selected I2C peripheral + * @param xfer : Pointer to a I2CM_XFER_T structure see notes below + * @return Returns non-zero value on successful completion of transfer. + * @note + * This function operates same as Chip_I2CM_Xfer(), but is a blocking call. + */ +uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __I2CM_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/i2cs_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/i2cs_5410x.h new file mode 100644 index 0000000000000..59afd1db9db6f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/i2cs_5410x.h @@ -0,0 +1,369 @@ +/* + * @brief LPC5410X I2C slave driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2CS_5410X_H_ +#define __I2CS_5410X_H_ + +#include "i2c_common_5410x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2CS_5410X CHIP: LPC5410X I2C slave-only driver + * @ingroup I2C_5410X + * This driver only works in slave mode. + * @{ + */ + +/** @brief I2C slave service start callback + * This callback is called from the I2C slave handler when an I2C slave address is + * received and needs servicing. It's used to indicate the start of a slave transfer + * that will happen on the slave bus. + */ +typedef void (*I2CSlaveXferStart)(uint8_t addr); + +/** @brief I2C slave send data callback + * This callback is called from the I2C slave handler when an I2C slave address needs + * data to send.
+ * If you want to NAK the master, return I2C_SLVCTL_SLVNACK to the caller. + * Return I2C_SLVCTL_SLVCONTINUE or 0 to the caller for normal non-DMA data transfer. + * If you've setup a DMA descriptor for the transfer, return I2C_SLVCTL_SLVDMA to the caller.
+ */ +typedef uint8_t (*I2CSlaveXferSend)(uint8_t *data); + +/** @brief I2C slave receive data callback + * This callback is called from the I2C slave handler when an I2C slave address has + * receive data.
+ * If you want to NAK the master, return I2C_SLVCTL_SLVNACK to the caller. + * Return I2C_SLVCTL_SLVCONTINUE or 0 to the caller for normal non-DMA data transfer. + * If you've setup a DMA descriptor for the transfer, return I2C_SLVCTL_SLVDMA to the caller.
+ */ +typedef uint8_t (*I2CSlaveXferRecv)(uint8_t data); + +/** @brief I2C slave service done callback + * This callback is called from the I2C slave handler when an I2C slave transfer is + * completed. It's used to indicate the end of a slave transfer. + */ +typedef void (*I2CSlaveXferDone)(void); + +/** + * Slave transfer are performed using 4 callbacks. These 3 callbacks handle most I2C + * slave transfer cases. When the slave is setup and a slave interrupt is receive + * and processed with the Chip_I2CS_XferHandler() function in the I2C interrupt handler, + * one of these 4 callbacks is called. The callbacks can be used for unsized transfers + * from the master. + * + * When an address is received, the SlaveXferAddr() callback is called with the + * received address. Only addresses enabled in the slave controller will be handled. + * The slave controller can support up to 4 slave addresses. + * + * If the master is going to perform a read operation, the SlaveXferSend() callback + * is called. Place the data byte to send in *data and return a value of 0 or + * I2C_SLVCTL_SLVCONTINUE to the caller, or return a value o I2C_SLVCTL_SLVNACK to + * NACK the master. If you are using DMA and have setup a DMA descriptor in the + * callback, return I2C_SLVCTL_SLVDMA.
+ * + * If the master performs a write operation, the SlaveXferRecv() callback is called + * with the received data. Return a value of 0 or I2C_SLVCTL_SLVCONTINUE to the caller + * to continue data transfer. Return I2C_SLVCTL_SLVNACK to NACk the master. If you + * are using DMA and have setup a DMA descriptor in the callback, return + * I2C_SLVCTL_SLVDMA.
+ * + * Once the transfer completes, the SlaveXferDone() callback will be called.
+ */ +typedef struct { + I2CSlaveXferStart slaveStart; /*!< Called when an matching I2C slave address is received */ + I2CSlaveXferSend slaveSend; /*!< Called when a byte is needed to send to master */ + I2CSlaveXferRecv slaveRecv; /*!< Called when a byte is received from master */ + I2CSlaveXferDone slaveDone; /*!< Called when a slave transfer is complete */ +} I2CS_XFER_T; + +/** + * @brief Enable I2C slave interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note Do not call this function until the slave interface is fully configured. + */ +__STATIC_INLINE void Chip_I2CS_Enable(LPC_I2C_T *pI2C) +{ + Chip_I2C_SetRegMask(&pI2C->CFG, I2C_CFG_MASK, I2C_CFG_SLVEN); +} + +/** + * @brief Disable I2C slave interface + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + */ +__STATIC_INLINE void Chip_I2CS_Disable(LPC_I2C_T *pI2C) +{ + Chip_I2C_ClearRegMask(&pI2C->CFG, I2C_CFG_MASK, I2C_CFG_SLVEN); +} + +/** + * @brief Get I2C Status + * @param pI2C : Pointer to selected I2C peripheral + * @return I2C Status register value + * @note This function returns the value of the status register. + */ +__STATIC_INLINE uint32_t Chip_I2CS_GetStatus(LPC_I2C_T *pI2C) +{ + return pI2C->STAT; +} + +/** + * @brief Clear I2C status bits (slave) + * @param pI2C : Pointer to selected I2C peripheral + * @param clrStatus : Status bit to clear, must be I2C_STAT_SLVDESEL + * @return Nothing + * @note This function clears selected status flags. + */ +__STATIC_INLINE void Chip_I2CS_ClearStatus(LPC_I2C_T *pI2C, uint32_t clrStatus) +{ + pI2C->STAT = clrStatus & I2C_STAT_SLVDESEL; +} + +/** + * @brief Check if I2C slave is pending + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns TRUE if the slave is pending else returns FALSE + * @note + */ +__STATIC_INLINE bool Chip_I2CS_IsSlavePending(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_SLVPENDING) != 0; +} + +/** + * @brief Check if I2C slave is selected + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns TRUE if the slave is is selected, otherwise FALSE + * @note + */ +__STATIC_INLINE bool Chip_I2CS_IsSlaveSelected(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_SLVSEL) != 0; +} + +/** + * @brief Check if I2C slave is deselected + * @param pI2C : Pointer to selected I2C peripheral + * @return Returns TRUE if the slave is is deselected, otherwise FALSE + * @note + */ +__STATIC_INLINE bool Chip_I2CS_IsSlaveDeSelected(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_SLVDESEL) != 0; +} + +/** + * @brief Get current state of the I2C slave + * @param pI2C : Pointer to selected I2C peripheral + * @return slave State Code, a value of type I2C_STAT_SLVCODE_* + * @note After the slave is pending this state code tells the reason + * for slave pending. + */ +__STATIC_INLINE uint32_t Chip_I2CS_GetSlaveState(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_SLVSTATE) >> 9; +} + +/** + * @brief Returns the current slave address match index + * @param pI2C : Pointer to selected I2C peripheral + * @return slave match index, 0 - 3 + */ +__STATIC_INLINE uint32_t Chip_I2CS_GetSlaveMatchIndex(LPC_I2C_T *pI2C) +{ + return (pI2C->STAT & I2C_STAT_SLVIDX) >> 12; +} + +/** + * @brief Slave Continue transfer operation (ACK) + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the slave controller to continue transmission. + * This should be called only when slave is pending. The function writes a + * complete value to slave Control register, ORing is not advised. + */ +__STATIC_INLINE void Chip_I2CS_SlaveContinue(LPC_I2C_T *pI2C) +{ + pI2C->SLVCTL = I2C_SLVCTL_SLVCONTINUE; +} + +/** + * @brief Slave NACK operation + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function sets the slave controller to NAK the master. + */ +__STATIC_INLINE void Chip_I2CS_SlaveNACK(LPC_I2C_T *pI2C) +{ + pI2C->SLVCTL = I2C_SLVCTL_SLVNACK; +} + +/** + * @brief Enable slave DMA operation + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function enables DMA mode for the slave controller. In DMA + * mode, the 'continue' and 'NACK' operations aren't used and the I2C slave + * controller will automatically NACK any bytes beyond the available DMA + * buffer size. + */ +__STATIC_INLINE void Chip_I2CS_SlaveEnableDMA(LPC_I2C_T *pI2C) +{ + pI2C->SLVCTL = I2C_SLVCTL_SLVDMA; +} + +/** + * @brief Disable slave DMA operation + * @param pI2C : Pointer to selected I2C peripheral + * @return Nothing + * @note This function disables DMA mode for the slave controller. + */ +__STATIC_INLINE void Chip_I2CS_SlaveDisableDMA(LPC_I2C_T *pI2C) +{ + pI2C->SLVCTL = 0; +} + +/** + * @brief Transmit a single data byte through the I2C peripheral (slave) + * @param pI2C : Pointer to selected I2C peripheral + * @param data : Byte to transmit + * @return Nothing + * @note This function attempts to place a byte into the I2C slave + * Data Register + * + */ +__STATIC_INLINE void Chip_I2CS_WriteByte(LPC_I2C_T *pI2C, uint8_t data) +{ + pI2C->SLVDAT = (uint32_t) data; +} + +/** + * @brief Read a single byte data from the I2C peripheral (slave) + * @param pI2C : Pointer to selected I2C peripheral + * @return A single byte of data read + * @note This function reads a byte from the I2C receive hold register + * regardless of I2C state. + */ +__STATIC_INLINE uint8_t Chip_I2CS_ReadByte(LPC_I2C_T *pI2C) +{ + return (uint8_t) (pI2C->SLVDAT & I2C_SLVDAT_DATAMASK); +} + +/** + * @brief Set a I2C slave address for slave operation + * @param pI2C : Pointer to selected I2C peripheral + * @param slvNum : Possible slave address number, between 0 - 3 + * @param slvAddr : Slave Address for the index (7-bits, bit 7 = 0) + * @return Nothing + * @note Setting a slave address also enables the slave address. Do + * not 'pre-shift' the slave address. + */ +__STATIC_INLINE void Chip_I2CS_SetSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum, uint8_t slvAddr) +{ + pI2C->SLVADR[slvNum] = (uint32_t) (slvAddr << 1); +} + +/** + * @brief Return a I2C programmed slave address + * @param pI2C : Pointer to selected I2C peripheral + * @param slvNum : Possible slave address number, between 0 - 3 + * @return Nothing + */ +__STATIC_INLINE uint8_t Chip_I2CS_GetSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) +{ + return (pI2C->SLVADR[slvNum] >> 1) & 0x7F; +} + +/** + * @brief Enable a I2C address + * @param pI2C : Pointer to selected I2C peripheral + * @param slvNum : Possible slave address number, between 0 - 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_I2CS_EnableSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) +{ + pI2C->SLVADR[slvNum] = (pI2C->SLVADR[slvNum] & I2C_SLVADR_MASK) & ~I2C_SLVADR_SADISABLE; +} + +/** + * @brief Disable a I2C address + * @param pI2C : Pointer to selected I2C peripheral + * @param slvNum : Possible slave address number, between 0 - 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_I2CS_DisableSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) +{ + pI2C->SLVADR[slvNum] = (pI2C->SLVADR[slvNum] & I2C_SLVADR_MASK) | I2C_SLVADR_SADISABLE; +} + +/** + * @brief Setup slave qialifier address + * @param pI2C : Pointer to selected I2C peripheral + * @param extend : true to extend I2C slave detect address 0 range, or false to match to corresponding bits + * @param slvAddr : Slave address qualifier, see SLVQUAL0 register in User Manual + * @return Nothing + * @note Do not 'pre-shift' the slave address. + */ +__STATIC_INLINE void Chip_I2CS_SetSlaveQual0(LPC_I2C_T *pI2C, bool extend, uint8_t slvAddr) +{ + slvAddr = slvAddr << 1; + if (extend) { + slvAddr |= I2C_SLVQUAL_QUALMODE0; + } + + pI2C->SLVQUAL0 = slvAddr; +} + +/** + * @brief Slave transfer state change handler + * @param pI2C : Pointer to selected I2C peripheral + * @param xfers : Pointer to a I2CS_MULTI_XFER_T structure see notes below + * @return Returns non-zero value on completion of transfer or NAK + * @note See @ref I2CS_XFER_T for more information on this function. When using + * this function, the I2C_INTENSET_SLVPENDING and I2C_INTENSET_SLVDESEL interrupts + * should be enabled and setup in the I2C interrupt handler to call this function + * when they fire. + */ +uint32_t Chip_I2CS_XferHandler(LPC_I2C_T *pI2C, const I2CS_XFER_T *xfers); + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __I2CS_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/iap.h b/ports/lpc/chips/lpc_chip_5410x/inc/iap.h new file mode 100644 index 0000000000000..a90e87c9b7ba6 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/iap.h @@ -0,0 +1,184 @@ +/* + * @brief Common IAP support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __IAP_H_ +#define __IAP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes + * @ingroup CHIP_Common + * @{ + */ + +/* IAP command definitions */ +#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */ +#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */ +#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */ +#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */ +#define IAP_REPID_CMD 54 /*!< Read PartID command */ +#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */ +#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */ +#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */ +#define IAP_READ_UID_CMD 58 /*!< Read UID */ +#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */ +#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */ +#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */ + +/* IAP response definitions */ +#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */ +#define IAP_INVALID_COMMAND 1 /*!< Invalid command */ +#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */ +#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */ +#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */ +#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */ +#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */ +#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */ +#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */ +#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */ +#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */ +#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */ +#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */ +#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */ +#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */ +#define IAP_CMD_LOCKED 15 /*!< Command is locked */ +#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */ +#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */ +#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */ +#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ + +/* IAP_ENTRY API function type */ +typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]); + +/** + * @brief Prepare sector for write operation + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Status code to indicate the command is executed successfully or not + * @note This command must be executed before executing "Copy RAM to flash" + * or "Erase Sector" command. + * The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector); + +/** + * @brief Copy RAM to flash + * @param dstAdd : Destination flash address where data bytes are to be written + * @param srcAdd : Source flash address where data bytes are to be read + * @param byteswrt : Number of bytes to be written + * @return Status code to indicate the command is executed successfully or not + * @note The addresses should be a 256 byte boundary and the number of bytes + * should be 256 | 512 | 1024 | 4096 + */ +uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt); + +/** + * @brief Erase sector + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Status code to indicate the command is executed successfully or not + * @note The end sector must be greater than or equal to start sector number + */ +uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector); + +/** + * @brief Blank check a sector or multiples sector of on-chip flash memory + * @param strSector : Start sector number + * @param endSector : End sector number + * @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK + * @note The end sector must be greater than or equal to start sector number + */ +// FIXME - There are two return value (result[0] & result[1] +// Result0:Offset of the first non blank word location if the Status Code is +// SECTOR_NOT_BLANK. +// Result1:Contents of non blank word location. +uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector); + +/** + * @brief Read part identification number + * @return Part identification number + */ +uint32_t Chip_IAP_ReadPID(void); + +/** + * @brief Read boot code version number + * @return Boot code version number + */ +uint8_t Chip_IAP_ReadBootCode(void); + +/** + * @brief Compare the memory contents at two locations + * @param dstAdd : Destination of the RAM address of data bytes to be compared + * @param srcAdd : Source of the RAM address of data bytes to be compared + * @param bytescmp : Number of bytes to be compared + * @return Offset of the first mismatch of the status code is COMPARE_ERROR + * @note The addresses should be a word boundary and number of bytes should be + * a multiply of 4 + */ +uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp); + +/** + * @brief IAP reinvoke ISP to invoke the bootloader in ISP mode + * @return none + */ +uint8_t Chip_IAP_ReinvokeISP(void); + +/** + * @brief Read the unique ID + * @return Status code to indicate the command is executed successfully or not + */ +uint32_t Chip_IAP_ReadUID(void); + +/** + * @brief Erase a page or multiple papers of on-chip flash memory + * @param strPage : Start page number + * @param endPage : End page number + * @return Status code to indicate the command is executed successfully or not + * @note The page number must be greater than or equal to start page number + */ +// FIXME - There are four return value +// Result0:The first 32-bit word (at the lowest address) +// Result1:The second 32-bit word. +// Result2:The third 32-bit word. +// Result3:The fourth 32-bit word. +uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IAP_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/inmux_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/inmux_5410x.h new file mode 100644 index 0000000000000..b06ed4ef2dc55 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/inmux_5410x.h @@ -0,0 +1,162 @@ +/* + * @brief LPC5410X Input Mux Registers and Driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __INMUX_5410X_H_ +#define __INMUX_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup INMUX_5410X CHIP: LPC5410X Input Mux Registers and Driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X Input Mux Register Block Structure + */ +typedef struct { /*!< INMUX Structure */ + __IO uint32_t RESERVED0[6]; + __I uint32_t RESERVED1[42]; + __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */ + __IO uint32_t DMA_ITRIG_INMUX[22]; /*!< Input mux register for DMA trigger inputs */ + __I uint32_t RESERVED2[2]; + __IO uint32_t DMA_OTRIG_INMUX[4]; /*!< Input mux register for DMA trigger inputs */ + __I uint32_t RESERVED3[4]; + __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */ + __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */ +} LPC_INMUX_T; + +/** + * @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register) + * @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7 + * @param portNum : GPIO port number interrupt, should be: 0 to 1 + * @param pinNum : GPIO pin number Interrupt, should be: 0 to 31 + * @return Nothing + */ +__STATIC_INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum) +{ + LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum; +} + +/* DMA triggers that can mapped to DMA channels */ +typedef enum { + DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */ + DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */ + DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */ + DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */ + DMATRIG_TIMER0_MATCH0, /*!< Timer 0, match 0 trigger */ + DMATRIG_TIMER0_MATCH1, /*!< Timer 0, match 1 trigger */ + DMATRIG_TIMER1_MATCH0, /*!< Timer 1, match 0 trigger */ + DMATRIG_TIMER1_MATCH1, /*!< Timer 1, match 1 trigger */ + DMATRIG_TIMER2_MATCH0, /*!< Timer 2, match 0 trigger */ + DMATRIG_TIMER2_MATCH1, /*!< Timer 2, match 1 trigger */ + DMATRIG_TIMER3_MATCH0, /*!< Timer 3, match 0 trigger */ + DMATRIG_TIMER3_MATCH1, /*!< Timer 3, match 1 trigger */ + DMATRIG_TIMER4_MATCH0, /*!< Timer 4, match 0 trigger */ + DMATRIG_TIMER4_MATCH1, /*!< Timer 4, match 1 trigger */ + DMATRIG_PININT0, /*!< Pin interrupt 0 trigger */ + DMATRIG_PININT1, /*!< Pin interrupt 1 trigger */ + DMATRIG_PININT2, /*!< Pin interrupt 2 trigger */ + DMATRIG_PININT3, /*!< Pin interrupt 3 trigger */ + DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ + DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ + DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ + DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ +} DMA_TRIGSRC_T; + +/** + * @brief Select a trigger source for a DMA channel + * @param ch : DMA channel number + * @param trig : Trigger source for the DMA channel + * @return Nothing + */ +__STATIC_INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig) +{ + LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig; +} + +/** + * @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs + * @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3 + * @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source + * @return Nothing + * @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn + * trigger source. + */ +__STATIC_INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh) +{ + LPC_INMUX->DMA_OTRIG_INMUX[index] = (uint32_t) dmaCh; +} + +/* Freqeuency measure reference and target clock sources */ +typedef enum { + FREQMSR_CLKIN = 0, /*!< CLKIN pin */ + FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */ + FREQMSR_WDOSC, /*!< Watchdog oscillator */ + FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */ + FREQ_MEAS_MAIN_CLK, /*!< main system clock */ + FREQMSR_PIO0_4, /*!< External pin PIO0_4 as input rate */ + FREQMSR_PIO0_20, /*!< External pin PIO0_20 as input rate */ + FREQMSR_PIO0_24, /*!< External pin PIO0_24 as input rate */ + FREQMSR_PIO1_4 /*!< External pin PIO1_4 as input rate */ +} FREQMSR_SRC_T; + +/** + * @brief Selects a reference clock used with the frequency measure function + * @param ref : Frequency measure function reference clock + * @return Nothing + */ +__STATIC_INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref) +{ + LPC_INMUX->FREQMEAS_REF = (uint32_t) ref; +} + +/** + * @brief Selects a target clock used with the frequency measure function + * @param targ : Frequency measure function reference clock + * @return Nothing + */ +__STATIC_INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ) +{ + LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __INMUX_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/iocon_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/iocon_5410x.h new file mode 100644 index 0000000000000..fb71264ae6203 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/iocon_5410x.h @@ -0,0 +1,139 @@ +/* + * @brief LPC5410X IOCON register block and driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __IOCON_5410X_H_ +#define __IOCON_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IOCON_5410X CHIP: LPC5410X IOCON register block and driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X IO Configuration Unit register block structure + */ +typedef struct { /*!< LPC5410X IOCON Structure */ + __IO uint32_t PIO[2][32]; +} LPC_IOCON_T; + +/** + * @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format + */ +typedef struct { + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t modefunc : 16; /* Function and mode */ +} PINMUX_GRP_T; + +/** + * IOCON function and mode selection definitions + * See the User Manual for specific modes and functions supported by the + * various LPC15XX pins. + */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ + +/** + * @brief Sets I/O Control pin mux + * @param pIOCON : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values or type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + pIOCON->PIO[port][pin] = modefunc; +} + +/** + * @brief I/O Control pin mux + * @param pIOCON : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param mode : OR'ed values or type IOCON_* + * @param func : Pin function, value of type IOCON_FUNC? + * @return Nothing + */ +__STATIC_INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func) +{ + Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func)); +} + +/** + * @brief Set all I/O Control pin muxing + * @param pIOCON : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCON_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/lpc_types.h b/ports/lpc/chips/lpc_chip_5410x/inc/lpc_types.h new file mode 100644 index 0000000000000..78e04436950a4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/lpc_types.h @@ -0,0 +1,230 @@ +/* + * @brief Common types used in LPC functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_TYPES_H_ +#define __LPC_TYPES_H_ + +#include +#include + +/** @defgroup LPC_Types CHIP: LPC Common Types + * @ingroup CHIP_Common + * @{ + */ + +/** @defgroup LPC_Types_Public_Types LPC Public Types + * @{ + */ + +/** + * @brief Boolean Type definition + */ +//typedef enum {FALSE = 0, TRUE = !FALSE} Bool; // in earlier versions +#ifndef TRUE +#define TRUE (1) +#endif +#ifndef FALSE +#define FALSE (0) +#endif + +/** + * @brief Boolean Type definition + */ +#if !defined(__cplusplus) +// typedef enum {false = 0, true = !false} bool; +#endif + +/** + * @brief Flag Status and Interrupt Flag Status type definition + */ +typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; +#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET)) + +/** + * @brief Functional State Definition + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE)) + +/** + * @ Status type definition + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; + +/** + * Read/Write transfer type mode (Block or non-block) + */ +typedef enum { + NONE_BLOCKING = 0, /**< None Blocking type */ + BLOCKING, /**< Blocking type */ +} TRANSFER_BLOCK_T; + +/** Pointer to Function returning Void (any number of parameters) */ +typedef void (*PFV)(); + +/** Pointer to Function returning int32_t (any number of parameters) */ +typedef int32_t (*PFI)(); + +/** + * @} + */ + +/** @defgroup LPC_Types_Public_Macros LPC Public Macros + * @{ + */ + +/* _BIT(n) sets the bit at position "n" + * _BIT(n) is intended to be used in "OR" and "AND" expressions: + * e.g., "(_BIT(3) | _BIT(7))". + */ +#undef _BIT +/* Set bit macro */ +#define _BIT(n) (1 << (n)) + +/* _SBF(f,v) sets the bit field starting at position "f" to value "v". + * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: + * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" + */ +#undef _SBF +/* Set bit field macro */ +#define _SBF(f, v) ((v) << (f)) + +/* _BITMASK constructs a symbol with 'field_width' least significant + * bits set. + * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF + * The symbol is intended to be used to limit the bit field width + * thusly: + * = (any_expression) & _BITMASK(x), where 0 < x <= 32. + * If "any_expression" results in a value that is larger than can be + * contained in 'x' bits, the bits above 'x - 1' are masked off. When + * used with the _SBF example above, the example would be written: + * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) + * This ensures that the value written to a_reg is no wider than + * 16 bits, and makes the code easier to read and understand. + */ +#undef _BITMASK +/* Bitmask creation macro */ +#define _BITMASK(field_width) ( _BIT(field_width) - 1) + +/* NULL pointer */ +#ifndef NULL +#define NULL ((void *) 0) +#endif + +/* Number of elements in an array */ +#define NELEMENTS(array) (sizeof(array) / sizeof(array[0])) + +/* Static data/function define */ +#define STATIC static +/* External data/function define */ +#define EXTERN extern + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/** + * @} + */ + +/* Old Type Definition compatibility */ +/** @addtogroup LPC_Types_Public_Types + * @{ + */ + +/** LPC type for character type */ +typedef char CHAR; + +/** LPC type for 8 bit unsigned value */ +typedef uint8_t UNS_8; + +/** LPC type for 8 bit signed value */ +typedef int8_t INT_8; + +/** LPC type for 16 bit unsigned value */ +typedef uint16_t UNS_16; + +/** LPC type for 16 bit signed value */ +typedef int16_t INT_16; + +/** LPC type for 32 bit unsigned value */ +typedef uint32_t UNS_32; + +/** LPC type for 32 bit signed value */ +typedef int32_t INT_32; + +/** LPC type for 64 bit signed value */ +typedef int64_t INT_64; + +/** LPC type for 64 bit unsigned value */ +typedef uint64_t UNS_64; + +#ifdef __CODE_RED +#define BOOL_32 bool +#define BOOL_16 bool +#define BOOL_8 bool +#else +/** 32 bit boolean type */ +typedef bool BOOL_32; + +/** 16 bit boolean type */ +typedef bool BOOL_16; + +/** 8 bit boolean type */ +typedef bool BOOL_8; +#endif + +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif + +// Needed for the different syntaxes used by various compilers for 'alignment' +#ifdef __ICCARM__ +#define ALIGNSTR(x) # x +#define ALIGN(x) _Pragma(ALIGNSTR(data_alignment = x)) +#else /* __CC_ARM || __GNUC__ */ +#define ALIGN(x) __attribute__ ((aligned(x))) +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __LPC_TYPES_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/mailbox_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/mailbox_5410x.h new file mode 100644 index 0000000000000..6c935b55ad5da --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/mailbox_5410x.h @@ -0,0 +1,173 @@ +/* + * @brief LPC5410X Mailbox M4/M0+ driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __MAILBOX_5410X_H_ +#define __MAILBOX_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup MAILBOX_5410X CHIP: LPC5410X Mailbox M4/M0+ driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* Mailbox indexes */ +typedef enum { + MAILBOX_CM0PLUS = 0, + MAILBOX_CM4 +} MBOX_IDX_T; +#define MAILBOX_AVAIL (MAILBOX_CM4 + 1) /* Number of available mailboxes */ + +/** Individual mailbox IRQ structure */ +typedef struct { + __IO uint32_t IRQ; /*!< Mailbox data */ + __O uint32_t IRQSET; /*!< Mailbox data set bits only */ + __O uint32_t IRQCLR; /*!< Mailbox dataclearset bits only */ + __I uint32_t RESERVED; +} LPC_MBOXIRQ_T; + +/** Mailbox register structure */ +typedef struct { /*!< Mailbox register structure */ + LPC_MBOXIRQ_T BOX[MAILBOX_AVAIL]; /*!< Mailbox, offset 0 = M0+, offset 1 = M4 */ + LPC_MBOXIRQ_T RESERVED1[15 - MAILBOX_AVAIL]; + __I uint32_t RESERVED2[2]; + __IO uint32_t MUTEX; /*!< Mutex */ +} LPC_MBOX_T; + +/** + * @brief Initialize mailbox + * @param pMBOX : Pointer to the mailbox register structure + * @return Nothing + * @note Even if both cores use the amilbox, only 1 core should initialize it. + */ +__STATIC_INLINE void Chip_MBOX_Init(LPC_MBOX_T *pMBOX) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_MAILBOX); + Chip_SYSCON_PeriphReset(RESET_MAILBOX); +} + +/** + * @brief Shutdown mailbox + * @param pMBOX : Pointer to the mailbox register structure + * @return Nothing + */ +__STATIC_INLINE void Chip_MBOX_DeInit(LPC_MBOX_T *pMBOX) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_MAILBOX); +} + +/** + * @brief Set data value in the mailbox based on the CPU ID + * @param pMBOX : Pointer to the mailbox register structure + * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 + * @param mboxData : data to send in the mailbox + * @return Nothing + * @note Sets a data value to send via the MBOX to the other core. + */ +__STATIC_INLINE void Chip_MBOX_SetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxData) +{ + pMBOX->BOX[cpu_id].IRQ = mboxData; +} + +/** + * @brief Set data bits in the mailbox based on the CPU ID + * @param pMBOX : Pointer to the mailbox register structure + * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 + * @param mboxSetBits : data bits to set in the mailbox + * @return Nothing + * @note Sets data bits to send via the MBOX to the other core, A value of 0 will + * do nothing. Only sets bits selected with a 1 in it's bit position. + */ +__STATIC_INLINE void Chip_MBOX_SetValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxSetBits) +{ + pMBOX->BOX[cpu_id].IRQSET = mboxSetBits; +} + +/** + * @brief Clear data bits in the mailbox based on the CPU ID + * @param pMBOX : Pointer to the mailbox register structure + * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 + * @param mboxClrBits : data bits to clear in the mailbox + * @return Nothing + * @note Clear data bits to send via the MBOX to the other core. A value of 0 will + * do nothing. Only clears bits selected with a 1 in it's bit position. + */ +__STATIC_INLINE void Chip_MBOX_ClearValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxClrBits) +{ + pMBOX->BOX[cpu_id].IRQCLR = mboxClrBits; +} + +/** + * @brief Get data in the mailbox based on the cpu_id + * @param pMBOX : Pointer to the mailbox register structure + * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 + * @return Current mailbox data + */ +__STATIC_INLINE uint32_t Chip_MBOX_GetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id) +{ + return pMBOX->BOX[cpu_id].IRQ; +} + +/** + * @brief Get MUTEX state and lock mutex + * @param pMBOX : Pointer to the mailbox register structure + * @return See note + * @note Returns '1' if the mutex was taken or '0' if another resources has the + * mutex locked. Once a mutex is taken, it can be returned with the Chip_MBOX_SetMutex() + * function. + */ +__STATIC_INLINE uint32_t Chip_MBOX_GetMutex(LPC_MBOX_T *pMBOX) +{ + return pMBOX->MUTEX; +} + +/** + * @brief Set MUTEX state + * @param pMBOX : Pointer to the mailbox register structure + * @return Nothing + * @note Sets mutex state to '1' and allows other resources to get the mutex + */ +__STATIC_INLINE void Chip_MBOX_SetMutex(LPC_MBOX_T *pMBOX) +{ + pMBOX->MUTEX = 1; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAILBOX_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/mrt_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/mrt_5410x.h new file mode 100644 index 0000000000000..e552a24c3065c --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/mrt_5410x.h @@ -0,0 +1,340 @@ +/* + * @brief LPC5410X Multi-Rate Timer (MRT) registers and driver functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __MRT_5410X_H_ +#define __MRT_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup MRT_5410X CHIP: LPC5410X Multi-Rate Timer driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X MRT chip configuration + */ +#define MRT_CHANNELS_NUM (4) +#define MRT_NO_IDLE_CHANNEL (0x40) + +/** + * @brief MRT register block structure + */ +typedef struct { + __IO uint32_t INTVAL; /*!< Timer interval register */ + __O uint32_t TIMER; /*!< Timer register */ + __IO uint32_t CTRL; /*!< Timer control register */ + __IO uint32_t STAT; /*!< Timer status register */ +} LPC_MRT_CH_T; + +/** + * @brief MRT register block structure + */ +typedef struct { + LPC_MRT_CH_T CHANNEL[MRT_CHANNELS_NUM]; + uint32_t unused[44]; + __IO uint32_t MODCFG; + __O uint32_t IDLE_CH; + __IO uint32_t IRQ_FLAG; +} LPC_MRT_T; + +/** + * @brief MRT Interrupt Modes enum + */ +typedef enum MRT_MODE { + MRT_MODE_REPEAT = (0 << 1), /*!< MRT Repeat interrupt mode */ + MRT_MODE_ONESHOT = (1 << 1) /*!< MRT One-shot interrupt mode */ +} MRT_MODE_T; + +/** + * @brief MRT register bit fields & masks + */ +/* MRT Time interval register bit fields */ +#define MRT_INTVAL_IVALUE (0x7FFFFFFF) /* Maximum interval load value and mask */ +#define MRT_INTVAL_LOAD (0x80000000UL) /* Force immediate load of timer interval register bit */ + +/* MRT Control register bit fields & masks */ +#define MRT_CTRL_INTEN_MASK (0x01) +#define MRT_CTRL_MODE_MASK (0x06) + +/* MRT Status register bit fields & masks */ +#define MRT_STAT_INTFLAG (0x01) +#define MRT_STAT_RUNNING (0x02) + +/* Pointer to individual MR register blocks */ +#define LPC_MRT_CH0 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[0]) +#define LPC_MRT_CH1 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[1]) +#define LPC_MRT_CH2 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[2]) +#define LPC_MRT_CH3 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[3]) +#define LPC_MRT_CH(ch) ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[(ch)]) + +/* Global interrupt flag register interrupt mask/clear values */ +#define MRT0_INTFLAG (1) +#define MRT1_INTFLAG (2) +#define MRT2_INTFLAG (4) +#define MRT3_INTFLAG (8) +#define MRTn_INTFLAG(ch) (1 << (ch)) + +/** + * @brief Initializes the MRT + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_Init(void) +{ + /* Enable the clock to the register interface */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_MRT); + + /* Reset MRT */ + Chip_SYSCON_PeriphReset(RESET_MRT); +} + +/** + * @brief De-initializes the MRT Channel + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_DeInit(void) +{ + /* Disable the clock to the MRT */ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_MRT); +} + +/** + * @brief Returns a pointer to the register block for a MRT channel + * @param ch : MRT channel tog et register block for (0..3) + * @return Pointer to the MRT register block for the channel + */ +__STATIC_INLINE LPC_MRT_CH_T *Chip_MRT_GetRegPtr(uint8_t ch) +{ + return LPC_MRT_CH(ch); +} + +/** + * @brief Returns the timer time interval value + * @param pMRT : Pointer to selected MRT Channel + * @return Timer time interval value (IVALUE) + */ +__STATIC_INLINE uint32_t Chip_MRT_GetInterval(LPC_MRT_CH_T *pMRT) +{ + return pMRT->INTVAL; +} + +/** + * @brief Sets the timer time interval value + * @param pMRT : Pointer to selected MRT Channel + * @param interval : The interval timeout (31-bits) + * @return Nothing + * @note Setting bit 31 in timer time interval register causes the time interval value + * to load immediately, otherwise the time interval value will be loaded in + * next timer cycle.
+ * Example: Chip_MRT_SetInterval(pMRT, 0x500 | MRT_INTVAL_LOAD); // Will load timer interval immediately
+ * Example: Chip_MRT_SetInterval(pMRT, 0x500); // Will load timer interval after internal expires + */ +__STATIC_INLINE void Chip_MRT_SetInterval(LPC_MRT_CH_T *pMRT, uint32_t interval) +{ + pMRT->INTVAL = interval; +} + +/** + * @brief Returns the current timer value + * @param pMRT : Pointer to selected MRT Channel + * @return The current timer value + */ +__STATIC_INLINE uint32_t Chip_MRT_GetTimer(LPC_MRT_CH_T *pMRT) +{ + return pMRT->TIMER; +} + +/** + * @brief Returns true if the timer is enabled + * @param pMRT : Pointer to selected MRT Channel + * @return True if enabled, Flase if not enabled + */ +__STATIC_INLINE bool Chip_MRT_GetEnabled(LPC_MRT_CH_T *pMRT) +{ + return (bool) ((pMRT->CTRL & MRT_CTRL_INTEN_MASK) != 0); +} + +/** + * @brief Enables the timer + * @param pMRT : Pointer to selected MRT Channel + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_SetEnabled(LPC_MRT_CH_T *pMRT) +{ + pMRT->CTRL |= MRT_CTRL_INTEN_MASK; +} + +/** + * @brief Disables the timer + * @param pMRT : Pointer to selected MRT Channel + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_SetDisabled(LPC_MRT_CH_T *pMRT) +{ + pMRT->CTRL &= ~MRT_CTRL_INTEN_MASK; +} + +/** + * @brief Returns the timer mode (repeat or one-shot) + * @param pMRT : Pointer to selected MRT Channel + * @return The current timer mode + */ +__STATIC_INLINE MRT_MODE_T Chip_MRT_GetMode(LPC_MRT_CH_T *pMRT) +{ + return (MRT_MODE_T) (pMRT->CTRL & MRT_CTRL_MODE_MASK); +} + +/** + * @brief Sets the timer mode (repeat or one-shot) + * @param pMRT : Pointer to selected MRT Channel + * @param mode : Timer mode + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_SetMode(LPC_MRT_CH_T *pMRT, MRT_MODE_T mode) +{ + uint32_t reg; + + reg = pMRT->CTRL & ~MRT_CTRL_MODE_MASK; + pMRT->CTRL = reg | (uint32_t) mode; +} + +/** + * @brief Check if the timer is configured in repeat mode + * @param pMRT : Pointer to selected MRT Channel + * @return True if in repeat mode, False if in one-shot mode + */ +__STATIC_INLINE bool Chip_MRT_IsRepeatMode(LPC_MRT_CH_T *pMRT) +{ + return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? false : true; +} + +/** + * @brief Check if the timer is configured in one-shot mode + * @param pMRT : Pointer to selected MRT Channel + * @return True if in one-shot mode, False if in repeat mode + */ +__STATIC_INLINE bool Chip_MRT_IsOneShotMode(LPC_MRT_CH_T *pMRT) +{ + return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? true : false; +} + +/** + * @brief Check if the timer has an interrupt pending + * @param pMRT : Pointer to selected MRT Channel + * @return True if interrupt is pending, False if no interrupt is pending + */ +__STATIC_INLINE bool Chip_MRT_IntPending(LPC_MRT_CH_T *pMRT) +{ + return (bool) ((pMRT->STAT & MRT_STAT_INTFLAG) != 0); +} + +/** + * @brief Clears the pending interrupt (if any) + * @param pMRT : Pointer to selected MRT Channel + * @return Nothing + */ +__STATIC_INLINE void Chip_MRT_IntClear(LPC_MRT_CH_T *pMRT) +{ + pMRT->STAT |= MRT_STAT_INTFLAG; +} + +/** + * @brief Check if the timer is running + * @param pMRT : Pointer to selected MRT Channel + * @return True if running, False if stopped + */ +__STATIC_INLINE bool Chip_MRT_Running(LPC_MRT_CH_T *pMRT) +{ + return (bool) ((pMRT->STAT & MRT_STAT_RUNNING) != 0); +} + +/** + * @brief Returns the IDLE channel value + * @return IDLE channel value (unshifted in bits 7..4) + */ +__STATIC_INLINE uint8_t Chip_MRT_GetIdleChannel(void) +{ + return (uint8_t) (LPC_MRT->IDLE_CH); +} + +/** + * @brief Returns the IDLE channel value + * @return IDLE channel value (shifted in bits 3..0) + */ +__STATIC_INLINE uint8_t Chip_MRT_GetIdleChannelShifted(void) +{ + return (uint8_t) (Chip_MRT_GetIdleChannel() >> 4); +} + +/** + * @brief Returns the interrupt pending status for all MRT channels + * @return IRQ pending channel bitfield(bit 0 = MRT0, bit 1 = MRT1, etc.) + */ +__STATIC_INLINE uint32_t Chip_MRT_GetIntPending(void) +{ + return LPC_MRT->IRQ_FLAG; +} + +/** + * @brief Returns the interrupt pending status for a singel MRT channel + * @param ch : Channel to check pending interrupt status for + * @return IRQ pending channel number + */ +__STATIC_INLINE bool Chip_MRT_GetIntPendingByChannel(uint8_t ch) +{ + return (bool) (((LPC_MRT->IRQ_FLAG >> ch) & 1) != 0); +} + +/** + * @brief Clears the interrupt pending status for one or more MRT channels + * @param mask : Channels to clear (bit 0 = MRT0, bit 1 = MRT1, etc.) + * @return Nothing + * @note Use this function to clear multiple interrupt pending states in + * a single call via the IRQ_FLAG register. Performs the same function for + * all MRT channels in a single call as the Chip_MRT_IntClear() does for a + * single channel. + */ +__STATIC_INLINE void Chip_MRT_ClearIntPending(uint32_t mask) +{ + LPC_MRT->IRQ_FLAG = mask; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MRT_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/pdm_api.h b/ports/lpc/chips/lpc_chip_5410x/inc/pdm_api.h new file mode 100644 index 0000000000000..450c82d982160 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/pdm_api.h @@ -0,0 +1,130 @@ +/* + * @brief PDM mic interface module + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PDM_API_H_ +#define __PDM_API_H_ + +#include +#include +#include +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SH_PDM PDMLIB: PDM interface API + * @ingroup SENSOR_HUB + * @{ + */ + +/** + * @brief Initialize PDM module + * @return Nothing + * @note PDM Clock (Clk out or Timer1) should be configured by the application. + */ +extern void PDM_Init(void); + +/** + * @brief Reset PDM interface + * @return Nothing + * @note This function resets the PDM (SI interface) state variables for a fresh start. + */ +extern void PDM_Reset(void); + +/** + * @brief Start capturing PDM data + * @return Nothing + */ +extern void PDM_Start(void); + +/** + * @brief Stop capturing PDM data + * @return Nothing + */ +extern void PDM_Stop(void); + +/** + * @brief Change PDM Decimation factor. + * @return 0 Success, 1 Error New decimation factor is not within 8 - 216. + */ +extern uint32_t PDM_ChgDecm(uint32_t new_decm); + +/** + * @brief Change PDM Clock & Data pin. This function should be called after + * @ref PDM_Init if pdm clock and data pins needs to be changed. + * @return 0 Success, 1 Error PDM Clock and/or Data pin is not within 0 - 15. + */ +extern uint32_t PDM_ChgPin(uint8_t pdm_clk_pin, uint8_t pdm_data_pin); + +/****************************************************************************** + * Callback routines + *****************************************************************************/ +/** + * @brief PDM data ready callback + * @return Nothing + * @note This function is called by PDM block when data is ready. Partially + * decimated data is available through @ref pdm_audio buffer. + * data for voice activity detection is available through @ref envelope_buffer. + */ +extern void PDM_DataReady(void); + +/** + * @brief Audio envelop data. + * Envelope information: + * - envelope_buffer[0] Fast detector + * - envelope_buffer[1] Slow detector + * - envelope_buffer[2] Reserved for internal use + * - envelope_buffer[3] Reserved for internal use + * - envelope_buffer[4] Latest biggest difference between fast and slow detector + * - envelope_buffer[5] latest output of pre envelope lowpass filter + * - envelope_buffer[6] latest output of pre envelope highpass filter + */ +extern volatile int32_t envelope_buffer[]; + +/** @brief Decimated PDM data. + A DC cut filter should be applied on this data to get 16bit PCM samples @ 16KHz + */ +extern volatile int32_t pdm_audio[]; + +#define PDM_PONG (*((volatile unsigned *) 0x4004C044)) & (1 << 6) + +#define PDM_IRQn (IRQn_Type) 30 + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDM_API_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/pinint_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/pinint_5410x.h new file mode 100644 index 0000000000000..c9f55081885b0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/pinint_5410x.h @@ -0,0 +1,413 @@ +/* + * @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PININT_5410X_H_ +#define __PININT_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PININT_5410X CHIP: LPC5410X Pin Interrupt and Pattern Match driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X Pin Interrupt and Pattern Match register block structure + */ +typedef struct { /*!< PIN_INT Structure */ + __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< Pin Interrupt Status register */ + __IO uint32_t PMCTRL; /*!< GPIO pattern match interrupt control register */ + __IO uint32_t PMSRC; /*!< GPIO pattern match interrupt bit-slice source register */ + __IO uint32_t PMCFG; /*!< GPIO pattern match interrupt bit slice configuration register */ +} LPC_PIN_INT_T; + +/** + * LPC5410X Pin Interrupt and Pattern match engine register + * bit fields and macros + */ + +/* PININT Interrupt Mode Mask */ +#define PININT_ISEL_PMODE_MASK ((uint32_t) 0x00FF) + +/* PININT Pattern Match Control Register Mask */ +#define PININT_PMCTRL_MASK ((uint32_t) 0xFF000003) + +/* PININT interrupt control register */ +#define PININT_PMCTRL_PMATCH_SEL (1 << 0) +#define PININT_PMCTRL_RXEV_ENA (1 << 1) + +/* PININT Bit slice source register bits */ +#define PININT_SRC_BITSOURCE_START 8 +#define PININT_SRC_BITSOURCE_MASK 7 + +/* PININT Bit slice configuration register bits */ +#define PININT_SRC_BITCFG_START 8 +#define PININT_SRC_BITCFG_MASK 7 + +/** + * LPC5410X Pin Interrupt channel values + */ +#define PININTCH0 (1 << 0) +#define PININTCH1 (1 << 1) +#define PININTCH2 (1 << 2) +#define PININTCH3 (1 << 3) +#define PININTCH4 (1 << 4) +#define PININTCH5 (1 << 5) +#define PININTCH6 (1 << 6) +#define PININTCH7 (1 << 7) +#define PININTCH(ch) (1 << (ch)) + +/** + * LPC5410X Pin Interrupt select enum values + */ +typedef enum Chip_PININT_SELECT { + PININTSELECT0 = 0, + PININTSELECT1 = 1, + PININTSELECT2 = 2, + PININTSELECT3 = 3, + PININTSELECT4 = 4, + PININTSELECT5 = 5, + PININTSELECT6 = 6, + PININTSELECT7 = 7 +} Chip_PININT_SELECT_T; + +/** + * LPC5410X Pin Matching Interrupt bit slice enum values + */ +typedef enum Chip_PININT_BITSLICE { + PININTBITSLICE0 = 0, /*!< PININT Bit slice 0 */ + PININTBITSLICE1 = 1, /*!< PININT Bit slice 1 */ + PININTBITSLICE2 = 2, /*!< PININT Bit slice 2 */ + PININTBITSLICE3 = 3, /*!< PININT Bit slice 3 */ + PININTBITSLICE4 = 4, /*!< PININT Bit slice 4 */ + PININTBITSLICE5 = 5, /*!< PININT Bit slice 5 */ + PININTBITSLICE6 = 6, /*!< PININT Bit slice 6 */ + PININTBITSLICE7 = 7 /*!< PININT Bit slice 7 */ +} Chip_PININT_BITSLICE_T; + +/** + * LPC5410X Pin Matching Interrupt bit slice configuration enum values + */ +typedef enum Chip_PININT_BITSLICE_CFG { + PININT_PATTERNCONST1 = 0x0, /*!< Contributes to product term match */ + PININT_PATTERNRISING = 0x1, /*!< Rising edge */ + PININT_PATTERNFALLING = 0x2, /*!< Falling edge */ + PININT_PATTERNRISINGORFALLING = 0x3, /*!< Rising or Falling edge */ + PININT_PATTERNHIGH = 0x4, /*!< High level */ + PININT_PATTERNLOW = 0x5, /*!< Low level */ + PININT_PATTERNCONST0 = 0x6, /*!< Never contributes for match */ + PININT_PATTERNEVENT = 0x7 /*!< Match occurs on event */ +} Chip_PININT_BITSLICE_CFG_T; + +/** + * @brief Initialize Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + * @note This function should be used after the Chip_GPIO_Init() function. + */ +__STATIC_INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_PINT); + Chip_SYSCON_PeriphReset(RESET_PINT); +} + +/** + * @brief De-Initialize Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_PINT); +} + +/** + * @brief Configure the pins as edge sensitive in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) & ~pins; +} + +/** + * @brief Configure the pins as level sensitive in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) | pins; +} + +/** + * @brief Return current PININT edge or level sensitive interrupt selection state + * @param pPININT : The base address of Pin interrupt block + * @return A bifield containing the edge/level sensitive selection for each + * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. + * For each bit, a 0 means the edge sensitive interrupt is selected, while a 1 + * means the level sensitive interrupt is selected. + */ +__STATIC_INLINE uint32_t Chip_PININT_GetPinMode(LPC_PIN_INT_T *pPININT) +{ + return pPININT->ISEL & PININT_ISEL_PMODE_MASK; +} + +/** + * @brief Return current PININT rising edge or level interrupt enable state + * @param pPININT : The base address of Pin interrupt block + * @return A bifield containing the rising edge/level enable for each + * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. + * For each bit, a 0 means the rising edge/level interrupt is disabled, while a 1 + * means it's enabled. + */ +__STATIC_INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IENR; +} + +/** + * @brief Enable rising edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to enable (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->SIENR = pins; +} + +/** + * @brief Disable rising edge/level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to disable (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->CIENR = pins; +} + +/** + * @brief Return current PININT falling edge or level interrupt active level enable state + * @param pPININT : The base address of Pin interrupt block + * @return A bifield containing the falling edge/level interrupt active level enable for each + * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. + * For each bit, a 0 means the falling edge is disabled/level interrupt active low is enabled, while a 1 + * means the falling edge is enabled/level interrupt active high is enabled. + */ +__STATIC_INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IENF; +} + +/** + * @brief Enable falling edge/level active level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to enable (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->SIENF = pins; +} + +/** + * @brief Disable low edge/level active level PININT interrupts for pins + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins to disable (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->CIENF = pins; +} + +/** + * @brief Return pin states that have a detected latched rising edge (RISE) state + * @param pPININT : The base address of Pin interrupt block + * @return PININT states (bit n = high) with a latched rise state detected + */ +__STATIC_INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT) +{ + return pPININT->RISE; +} + +/** + * @brief Clears pin states that had a latched rising edge (RISE) state + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins with latched states to clear + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->RISE = pins; +} + +/** + * @brief Return pin states that have a detected latched falling edge (FALL) state + * @param pPININT : The base address of Pin interrupt block + * @return PININT states (bit n = high) with a latched rise state detected + */ +__STATIC_INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT) +{ + return pPININT->FALL; +} + +/** + * @brief Clears pin states that had a latched falling edge (FALL) state + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pins with latched states to clear + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->FALL = pins; +} + +/** + * @brief Get interrupt status from Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Interrupt status (bit n for PININTn = high means interrupt ie pending) + */ +__STATIC_INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT) +{ + return pPININT->IST; +} + +/** + * @brief Clear interrupt status in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param pins : Pin interrupts to clear (ORed value of PININTCH*) + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins) +{ + pPININT->IST = pins; +} + +/** + * @brief Set source for pattern match in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param channelNum : PININT channel number (From 0 to 7) + * @param sliceNum : PININT slice number + * @return Nothing + */ +void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT, + Chip_PININT_SELECT_T channelNum, + Chip_PININT_BITSLICE_T sliceNum); + +/** + * @brief Configure the pattern matcch in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @param sliceNum : PININT slice number + * @param slice_cfg : PININT slice configuration value (enum Chip_PININT_BITSLICE_CFG_T) + * @param end_point : If true, current slice is final component + * @return Nothing + */ +void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum, + Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point); + +/** + * @brief Enable pattern match interrupts in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_EnablePatternMatch(LPC_PIN_INT_T *pPININT) +{ + pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_PMATCH_SEL; +} + +/** + * @brief Disable pattern match interrupts in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_DisablePatternMatch(LPC_PIN_INT_T *pPININT) +{ + pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_PMATCH_SEL; +} + +/** + * @brief Enable RXEV output in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_EnablePatternMatchRxEv(LPC_PIN_INT_T *pPININT) +{ + pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_RXEV_ENA; +} + +/** + * @brief Disable RXEV output in Pin interrupt block + * @param pPININT : The base address of Pin interrupt block + * @return Nothing + */ +__STATIC_INLINE void Chip_PININT_DisablePatternMatchRxEv(LPC_PIN_INT_T *pPININT) +{ + pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_RXEV_ENA; +} + +/** + * @brief Return pattern match state + * @param pPININT : The base address of Pin interrupt block + * @return 8 bit pattern match state, where a 1 in any bit indicates that + * the corresponding product term has matched by the current state + * of its inputs. + */ +__STATIC_INLINE uint32_t Chip_PININT_GetPatternMatchState(LPC_PIN_INT_T *pPININT) +{ + return pPININT->PMCTRL >> 24; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PININT_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/pintable_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/pintable_5410x.h new file mode 100644 index 0000000000000..e1c51cd3407a9 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/pintable_5410x.h @@ -0,0 +1,124 @@ +/* + * @brief LPC5410x enhanced boot block + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PINTABLE_5410X_H_ +#define __PINTABLE_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PINTAB_5410X CHIP: LPC5410X Enhanced boot block support + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* Enhanced image signature offset */ +#define IMAGE_ENH_MARKER_OFF 0x24 + +/* Enhanced single image signature */ +#define IMAGE_SINGLE_ENH_SIG 0xEDDC9494 + +/* Enhanced dual image signature */ +#define IMAGE_DUAL_ENH_SIG 0x0FFEB6B6 + +/* Boot block offset */ +#define IMAGE_BOOT_BLOCK_OFF 0x28 + +/* Enhanced image block marker */ +#define IMAGE_ENH_BLOCK_MARKER 0xFEEDA5A5 + +/* Macro for assigning a pin to a PINTABLE pin entry */ +#define SETPORTPIN(port, pin) (((port) & 0x7) << 5) | ((pin) & 0x1F) + +/** Image type (img_type) for the pin table structure */ +typedef enum { + IMG_NORMAL = 0, /*!< Normal image check, assert dynamic ISP to halt boot */ + IMG_ISP_WAIT, /*!< Wait for host system to send SH_CMD_BOOT command */ + IMG_NO_WAIT, /*!< Boot image without checking dynamic ISP, CRC is still done */ + IMG_NO_CRC, /*!< No CRC check made. Used during development. Dynamic ISP still works */ + IMG_JUST_BOOT = 0xFF /*!< Disables XOR and CRC checks, will always boot */ +} IMAGE_T; + +/** Host interface sources (ifSel) for the pin table structure */ +typedef enum { + SL_AUTO = 0, /*!< Auto-detect used for host interface */ + SL_I2C0, /*!< I2C0 used for host interface */ + SL_I2C1, /*!< I2C1 used for host interface */ + SL_I2C2, /*!< I2C2 used for host interface */ + SL_SPI0, /*!< SPI0 used for host interface */ + SL_SPI1, /*!< SPI1 used for host interface */ +} IFSEL_T; + +/** + * @brief LPC5410X Pin table structure used for enhanced boot block support + */ +typedef struct PINTABLE { + /* pin table marker: Should be 0xFEEDA5A5 */ + uint32_t marker; + /* img_type: Image type (IMAGE_T) + 0 = Normal image check, assert dynamic ISP to halt boot + 1 = Wait for host system to send SH_CMD_BOOT command + 2 = Boot image without checking dynamic ISP, CRC is still done + 3 = No CRC check made. Used during development. Dynamic ISP still works. + 0xFF = Disables XOR and CRC checks, will always boot */ + uint8_t img_type; + /* ifSel: Interface selection for host (IFSEL_T) + (0,=AUTODETECT, 1=I2C0, 2=I2C1, 3=I2C2, 4=SPI0, 5=SPI1) */ + uint8_t ifSel; + /* hostIrqPortPin: Host IRQ port (bits 7:5) and pins (bits 4:0) */ + uint8_t hostIrqPortPin; + /* hostMisoPortPin: SPI MISO port (bits 7:5) and pins (bits 4:0) */ + uint8_t hostMisoPortPin; + /* hostMosiPortPin: SPI MOSI port (bits 7:5) and pins (bits 4:0) */ + uint8_t hostMosiPortPin; + /* hostSselPortPin: SPI SEL port (bits 7:5) and pins (bits 4:0) */ + uint8_t hostSselPortPin; + /* hostSckPortPin: SPI SCK port (bits 7:5) and pins (bits 4:0) */ + uint8_t hostSckPortPin; + /* xorVal: XOR value of the 7 bytes above */ + uint8_t xorVal; + /* CRC32 length and value fields */ + uint32_t crc32_len; + uint32_t crc32_val; + /* Application image version number */ + uint32_t version; +} PINTABLE_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PINTAB_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/pll_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/pll_5410x.h new file mode 100644 index 0000000000000..1608a9f8219c7 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/pll_5410x.h @@ -0,0 +1,305 @@ +/* + * @brief LPC5410X PLL driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PLL_5410X_H_ +#define __PLL_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PLL_5410X CHIP: LPC5410X PLL Driver + * @ingroup CHIP_5410X_DRIVERS + * The PLL in the LPC5410x is flexible, but can be complex to use. This driver + * provides functions to help setup and use the PLL in it's various supported + * modes.
+ * + * This driver does not alter PLL clock source or system clocks outside the + * PLL (like the main clock source) that may be referenced from the PLL. It + * may optionally setup system voltages, wait for PLL lock, and power cycle + * the PLL during setup based on setup flags. + * + * The driver works by first generating a PLL setup structure from a desired + * PLL configuration structure. The PLL setup structure is then passed to the + * PLL setup function to setup the PLL. In a user spplication, the PLL setup + * structure can be pre-populated with PLL setup data to avoid using the PLL + * configuration structure (or multiple PLL setup structures can be used to + * more dynamically control PLL output rate). + * + * How to use this driver
+ @verbatim + // Setup PLL configuration + PLL_CONFIG_T pllConfig = { + 75000000, // desiredRate = 75MHz + 0, // InputRate = 0Hz (not used) + 0 // No flags, function will determine best setup to get closest rate + }; + + // Get closest PLL setup to get the desired configuration + PLL_SETUP_T pllSetup; + uint32_t actualPllRate; + PLL_ERROR_T pllError; + pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup, &actualPllRate); + if (pllError != PLL_ERROR_SUCCESS) { + printf("PLL setup error #%x\r\n", (uint32_t) pllError); + while (1); + } + else { + printf("PLL config successful, actual config rate = %uHz\r\n", actualPllRate); + } + + // Make sure main system clock is not using PLL, as the PLL setup + // function will power off and optionally power on the PLL + Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_IRC); + + // Setup PLL source + Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC); + + // Now to apply the configuration to the PLL + pllSetup.flags = PLL_SETUPFLAG_WAITLOCK; + Chip_Clock_SetupSystemPLLPrec(&pllSetup); + + // Switch main system clock to PLL + Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); + @endverbatim + * + * @{ + */ + +/** + * Clock sources for system PLLs + */ +typedef enum CHIP_SYSCON_PLLCLKSRC { + SYSCON_PLLCLKSRC_IRC = 0, /*!< Internal oscillator */ + SYSCON_PLLCLKSRC_CLKIN, /*!< External clock input pin */ + SYSCON_PLLCLKSRC_WDTOSC, /*!< WDT oscillator */ + SYSCON_PLLCLKSRC_RTC, /*!< RTC 32KHz oscillator */ +} CHIP_SYSCON_PLLCLKSRC_T; + +/** + * @brief Set System PLL clock source + * @param src : Clock source for system PLL + * @return Nothing + * @note The PLL should be pwoered down prior to changing the source. + */ +__STATIC_INLINE void Chip_Clock_SetSystemPLLSource(CHIP_SYSCON_PLLCLKSRC_T src) +{ + LPC_SYSCON->SYSPLLCLKSEL = (uint32_t) src; +} + +/** + * @brief Return System PLL input clock rate + * @return System PLL input clock rate + */ +uint32_t Chip_Clock_GetSystemPLLInClockRate(void); + +/** + * @brief Return System PLL output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return System PLL output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute); + +/** + * @brief Enables and disables PLL bypass mode + * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass + * @return System PLL output clock rate + */ +void Chip_Clock_SetBypassPLL(bool bypass); + +/** + * @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool Chip_Clock_IsSystemPLLLocked(void) +{ + return (bool) ((LPC_SYSCON->SYSPLLSTAT & 1) != 0); +} + +/** @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/** @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum { + SS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ˜ 3.9 - 7.8 kHz) */ + SS_MF_384 = (1 << 20), /*!< Nss ˜= 384 (fm ˜ 5.2 - 10.4 kHz) */ + SS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ˜ 7.8 - 15.6 kHz) */ + SS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ˜ 15.6 - 31.3 kHz) */ + SS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ˜ 32.3 - 64.5 kHz) */ + SS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ˜ 62.5- 125 kHz) */ + SS_MF_24 = (6 << 20), /*!< Nss ˜= 24 (fm ˜ 83.3- 166.6 kHz) */ + SS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ˜ 125- 250 kHz) */ +} SS_PROGMODFM_T; + +/** @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum { + SS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + SS_MR_K1 = (1 << 23), /*!< k = 1 */ + SS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + SS_MR_K2 = (3 << 23), /*!< k = 2 */ + SS_MR_K3 = (4 << 23), /*!< k = 3 */ + SS_MR_K4 = (5 << 23), /*!< k = 4 */ + SS_MR_K6 = (6 << 23), /*!< k = 6 */ + SS_MR_K8 = (7 << 23) /*!< k = 8 */ +} SS_PROGMODDP_T; + +/** @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum { + SS_MC_NOC = (0 << 26), /*!< no compensation */ + SS_MC_RECC = (2 << 26), /*!< recommended setting */ + SS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} SS_MODWVCTRL_T; + +/** @brief PLL configuration structure + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct { + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t InputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + SS_PROGMODFM_T ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + SS_PROGMODDP_T ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + SS_MODWVCTRL_T ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ +} PLL_CONFIG_T; + +/** @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ + +/** @brief PLL setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct { + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ + uint32_t SYSPLLCTRL; /*!< PLL control register */ + uint32_t SYSPLLNDEC; /*!< PLL NDEC register */ + uint32_t SYSPLLPDEC; /*!< PLL PDEC register */ + uint32_t SYSPLLSSCTRL[2]; /*!< PLL SSCTL registers */ +} PLL_SETUP_T; + +/** @brief PLL status definitions + */ +typedef enum { + PLL_ERROR_SUCCESS = 0, /*!< PLL operation was successful */ + PLL_ERROR_OUTPUT_TOO_LOW, /*!< PLL output rate request was too low */ + PLL_ERROR_OUTPUT_TOO_HIGH, /*!< PLL output rate request was too high */ + PLL_ERROR_INPUT_TOO_LOW, /*!< PLL input rate is too low */ + PLL_ERROR_INPUT_TOO_HIGH, /*!< PLL input rate is too high */ + PLL_ERROR_OUTSIDE_INTLIMIT /*!< Requested output rate isn't possible */ +} PLL_ERROR_T; + +/** + * @brief Return System PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup); + +/** + * @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup); + +/** + * @brief Set PLL output based on the multiplier and input frequency + * @param multiply_by : multiplier + * @param input_freq : Clock input frequency of the PLL + * @return Nothing + * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PLL_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/pmu_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/pmu_5410x.h new file mode 100644 index 0000000000000..a1acd4424a8a1 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/pmu_5410x.h @@ -0,0 +1,184 @@ +/* + * @brief LPC5410X Power Management declarations and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PMU_5410X_H_ +#define __PMU_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup PMU_5410X CHIP: LPC5410X Power Management declarations and functions + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief PMU register block structure + * @note Most of the PMU support is handled by the PMU library. + */ +typedef struct { + __I uint32_t RESERVED0[4]; + __I uint32_t RESERVED1[4]; + __I uint32_t RESERVED2[4]; + __I uint32_t RESERVED3[4]; + __I uint32_t RESERVED4; + __IO uint32_t BODCTRL; + __I uint32_t RESERVED5; + __I uint32_t RESERVED6; + __IO uint32_t DPDWAKESRC; +} LPC_PMU_T; + +/** + * Brown-out detector reset level + */ +typedef enum { + PMU_BODRSTLVL_0, /*!< Brown-out reset at ~1.5v */ + PMU_BODRSTLVL_1_50V = PMU_BODRSTLVL_0, + PMU_BODRSTLVL_1, /*!< Brown-out reset at ~1.85v */ + PMU_BODRSTLVL_1_85V = PMU_BODRSTLVL_1, + PMU_BODRSTLVL_2, /*!< Brown-out reset at ~2.0v */ + PMU_BODRSTLVL_2_00V = PMU_BODRSTLVL_2, + PMU_BODRSTLVL_3, /*!< Brown-out reset at ~2.3v */ + PMU_BODRSTLVL_2_30V = PMU_BODRSTLVL_3 +} CHIP_PMU_BODRSTLVL_T; + +/** + * Brown-out detector interrupt level + */ +typedef enum CHIP_PMU_BODRINTVAL { + PMU_BODINTVAL_LVL0, /*!< Brown-out interrupt at ~2.05v */ + PMU_BODINTVAL_2_05v = PMU_BODINTVAL_LVL0, + PMU_BODINTVAL_LVL1, /*!< Brown-out interrupt at ~2.45v */ + PMU_BODINTVAL_2_45v = PMU_BODINTVAL_LVL1, + PMU_BODINTVAL_LVL2, /*!< Brown-out interrupt at ~2.75v */ + PMU_BODINTVAL_2_75v = PMU_BODINTVAL_LVL2, + PMU_BODINTVAL_LVL3, /*!< Brown-out interrupt at ~3.05v */ + PMU_BODINTVAL_3_05v = PMU_BODINTVAL_LVL3 +} CHIP_PMU_BODRINTVAL_T; + +/** + * brown-out detection reset status (in BODCTRL register) + */ +#define PMU_BOD_RST (1 << 6) +/** + * brown-out detection interrupt status (in BODCTRL register) + */ +#define PMU_BOD_INT (1 << 7) + +/** + * @brief Set brown-out detection interrupt and reset levels + * @param rstlvl : Brown-out detector reset level + * @param intlvl : Brown-out interrupt level + * @return Nothing + * @note Brown-out detection reset will be disabled upon exiting this function. + * Use Chip_PMU_EnableBODReset() to re-enable. + */ +__STATIC_INLINE void Chip_PMU_SetBODLevels(CHIP_PMU_BODRSTLVL_T rstlvl, + CHIP_PMU_BODRINTVAL_T intlvl) +{ + LPC_PMU->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2); +} + +/** + * @brief Enable brown-out detection reset + * @return Nothing + */ +__STATIC_INLINE void Chip_PMU_EnableBODReset(void) +{ + LPC_PMU->BODCTRL |= (1 << 4); +} + +/** + * @brief Disable brown-out detection reset + * @return Nothing + */ +__STATIC_INLINE void Chip_PMU_DisableBODReset(void) +{ + LPC_PMU->BODCTRL &= ~(1 << 4); +} + +/** + * @brief Enable brown-out detection interrupt + * @return Nothing + */ +__STATIC_INLINE void Chip_PMU_EnableBODInt(void) +{ + LPC_PMU->BODCTRL |= (1 << 5); +} + +/** + * @brief Disable brown-out detection interrupt + * @return Nothing + */ +__STATIC_INLINE void Chip_PMU_DisableBODInt(void) +{ + LPC_PMU->BODCTRL &= ~(1 << 5); +} + +/** + * Deep power down reset sources + */ +#define PMU_DPDWU_RESET (1 << 0) /*!< Deep powerdown wakeup by reset pin */ +#define PMU_DPDWU_RTC (1 << 1) /*!< Deep powerdown wakeup by RTC */ +#define PMU_DPDWU_BODRESET (1 << 2) /*!< Deep powerdown wakeup by brown out reset*/ +#define PMU_DPDWU_BODINTR (1 << 3) /*!< Deep powerdown wakeup by brown out interrupt */ + +/** + * @brief Return wakeup sources from deep power down mode + * @return Deep power down mode wakeup sources + * @note Mask the return value with a PMU_DPDWU_* value to determine + * the wakeup source from deep power down. + */ +__STATIC_INLINE uint32_t Chip_PMU_GetDPDWUSource(void) +{ + return LPC_PMU->DPDWAKESRC; +} + +/** + * @brief Clear a deep power down mode wakeup source + * @param mask : Or'ed PMU_DPDWU_* values to clear + * @return Nothing + */ +__STATIC_INLINE void Chip_PMU_ClearDPDWUSource(uint32_t mask) +{ + LPC_PMU->DPDWAKESRC = mask; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PMU_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/power_lib_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/power_lib_5410x.h new file mode 100644 index 0000000000000..683db7ef0f027 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/power_lib_5410x.h @@ -0,0 +1,281 @@ +/* + * @brief LPC5410x Power library functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __POWER_LIB_5410X_H_ +#define __POWER_LIB_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup POWER_LIBRARY_5410X CHIP: LPC5410X Power LIBRARY functions + * The power library provides functions to control system power usage and + * place the device into low power modes.
+ * + * Clock shutdown in sleep and power down modes
+ * When using the Chip_POWER_EnterPowerMode() function, system clocks are + * shutdown based on the selected sleep or power down mode and the device + * version being used. The following list details which clocks are shut down + * in which modes for which device versions. You can keep a clock enabled + * for a sleep or power down mode by enabling it in the 'peripheral_ctrl' + * field in the Chip_POWER_EnterPowerMode() function.
+ * + * Mode: Sleep
+ * No clocks are disabled for any chip version.
+ * + * Mode: Deep sleep
+ * SYSCON_PDRUNCFG_PD_IRC_OSC
+ * SYSCON_PDRUNCFG_PD_IRC
+ * SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)
+ * SYSCON_PDRUNCFG_PD_BOD_INTR
+ * SYSCON_PDRUNCFG_PD_ADC0
+ * SYSCON_PDRUNCFG_PD_ROM
+ * SYSCON_PDRUNCFG_PD_VDDA_ENA
+ * SYSCON_PDRUNCFG_PD_SYS_PLL
+ * SYSCON_PDRUNCFG_PD_VREFP
+ * + * Mode: Power down
+ * SYSCON_PDRUNCFG_PD_IRC_OSC
+ * SYSCON_PDRUNCFG_PD_IRC
+ * SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)
+ * SYSCON_PDRUNCFG_PD_BOD_RST
+ * SYSCON_PDRUNCFG_PD_BOD_INTR
+ * SYSCON_PDRUNCFG_PD_ADC0
+ * SYSCON_PDRUNCFG_PD_SRAM0B
+ * SYSCON_PDRUNCFG_PD_SRAM1
+ * SYSCON_PDRUNCFG_PD_SRAM2
+ * SYSCON_PDRUNCFG_PD_ROM
+ * SYSCON_PDRUNCFG_PD_VDDA_ENA
+ * SYSCON_PDRUNCFG_PD_WDT_OSC
+ * SYSCON_PDRUNCFG_PD_SYS_PLL
+ * SYSCON_PDRUNCFG_PD_VREFP
+ * SYSCON_PDRUNCFG_PD_32K_OSC
+ * + * Mode: Deep power down
+ * All clocks are disabled for all chip versions.
+ * + * If you are using a peripheral was a wakeup source for a power down mode, + * it needs to be kept active with the call to Chip_POWER_EnterPowerMode(). For + * example, if you are using the RTC to wake the system up from power down mode, + * the 32KHz RTC oscillator needs to remain active, so the power down call would + * look like this:
+ * Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, SYSCON_PDRUNCFG_PD_32K_OSC);
+ * If your application uses internal RAM beyond the first 8K, you will also need + * to prevent power down of the IRAM like this:
+ * Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, (SYSCON_PDRUNCFG_PD_32K_OSC | SYSCON_PDRUNCFG_PD_SRAM0A));
+ * @ingroup CHIP_5410X_DRIVERS + * @{ + */ +// Saved in case they need to be re-installed publicly later +/* Power domains */ +typedef enum { + POWER_VD1 = 0x0, + POWER_VD2 = 0x1, + POWER_VD3 = 0x2, + POWER_VD8 = 0x3 +} POWER_DOMAIN_T; + +/* Power coarse voltage levels */ +typedef enum { + POWER_V0650 = 0x0, + POWER_V0700 = 0x1, + POWER_V0750 = 0x2, + POWER_V0800 = 0x3, + POWER_V0850 = 0x4, + POWER_V0900 = 0x5, + POWER_V0950 = 0x6, + POWER_V1000 = 0x7, + POWER_V1050 = 0x8, + POWER_V1100 = 0x9, + POWER_V1150 = 0xA, + POWER_V1200 = 0xB, + POWER_V1250 = 0xC, + POWER_V1300 = 0xD, + POWER_V1350 = 0xE, + POWER_V1400 = 0xF +} POWER_VOLTAGELEVEL_T; + +/* Power fine voltage levels */ +typedef enum { + POWER_FINE_V_NONE = 0x0, + POWER_FINE_V_M025 = 0x1, + POWER_FINE_V_P025 = 0x3 +} POWER_FINEVOLTAGELEVEL_T; + +/* Low power voltage selection */ +typedef enum { + POWER_LP_V0700 = 0x0, + POWER_LP_V1200 = 0x1 +} POWER_LPVOLTAGELEVEL_T; + +/* Low power fine voltage selection */ +typedef enum { + POWER_FINE_LP_V_M050 = 0x0, + POWER_FINE_LP_V_NONE = 0x1, + POWER_FINE_LP_V_P050 = 0x2, + POWER_FINE_LP_V_P100 = 0x3 +} POWER_LPFINEVOLTAGELEVEL_T; + +/* 'mode' input values to set_voltage ROM function */ +typedef enum { + POWER_LOW_POWER_MODE = 0, + POWER_BALANCED_MODE, + POWER_HIGH_PERFORMANCE +} PERF_MODE_T; + +/* 'mode' input values to power_mode_configure ROM function */ +typedef enum { + POWER_SLEEP = 0, + POWER_DEEP_SLEEP, + POWER_POWER_DOWN, + POWER_DEEP_POWER_DOWN +} POWER_MODE_T; + +/** + * @brief Sets up the System PLL given the PLL input frequency and feedback multiplier + * @param multiply_by : PLL multiplier, minimum of 1, maximum of 16 + * @param input_freq : Input frequency into the PLL + * @return LPC_OK on success, or an error code (see error.h) + */ +uint32_t Chip_POWER_SetPLL(uint32_t multiply_by, uint32_t input_freq); + +/** + * @brief Turn flash power on / off + * @param new_power_mode : 0 = power off, != 0 = power on + * @return nothing + */ +void Chip_POWER_SetFLASHPower(uint32_t new_power_mode); + +/** + * @brief Set optimal system voltage based on passed system frequency + * @param mode : Power mode + * @param desired_freq : System (CPU) frequency + * @return LPC_OK on success, or an error code (see error.h) + * @note This function will adjust the system voltages to the lowest + * levels that will support the passed mode and CPU frequency. + */ +uint32_t Chip_POWER_SetVoltage(PERF_MODE_T mode, uint32_t desired_freq); + +/** + * @brief Set voltage levels on individual voltage domains + * @param domain : Power domain + * @param level : Coarse voltage level + * @param flevel : Fine voltage level + * @return Nothing + */ +uint32_t Chip_POWER_SetVDLevel(POWER_DOMAIN_T domain, POWER_VOLTAGELEVEL_T level, POWER_FINEVOLTAGELEVEL_T flevel); + +/** + * @brief Set low-power voltage levels for LP mode + * @return Nothing + */ +void Chip_POWER_SetLPVDLevel(void); + +/** + * @brief Enters the selected power state + * @param mode : Power mode + * @param peripheral_ctrl : Peripherals that will remain powered up in the power state + * @return Nothing + * @note The 'peripheral_ctrl' field is a bitmask of bits from the + * PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which + * peripherals can wake up the chip from the power state. These + * peripherals are not powered down during the power state.
+ */ +void Chip_POWER_EnterPowerMode(POWER_MODE_T mode, uint32_t peripheral_ctrl); + +/** + * @brief Enters the selected power state (Relocated) + * @param mode : Power mode + * @param peripheral_ctrl : Peripherals that will remain powered up in the power state + * @param relMem : Address of the memory where relocated power function is [see Chip_POWER_RelocAPI()] + * @return Nothing + * @note This API is to be used when the powerdown mode [ @a mode is #POWER_POWER_DOWN ] is to be entered from flash. + * Since powerdown mode turns off the flash memory the powerdown API, if executed from flash, can be relocated to RAM + * using Chip_POWER_RelocAPI(), and powerdown mode can be entered using this API. @a relMem should be the pointer to the + * memory used when calling Chip_POWER_RelocAPI(). For all power modes other than + * #POWER_POWER_DOWN this API works exactly same as Chip_POWER_EnterPowerMode() API and @a relMem can be 0.
+ */ +void Chip_POWER_EnterPowerModeReloc(POWER_MODE_T mode, uint32_t peripheral_ctrl, uint32_t relMem); + +/** + * @brief Relocate the PowerDown code to given memory + * + * When executing from flash, entering PowerDown mode is not possible as the PowerDown mode turns + * off the flash. This function will relocate the powerdown code to memory allocated in RAM and this + * relocated function can be invoked using Chip_POWER_EnterPowerModeReloc() hence entering powerdown + * mode from RAM and let the flash power be turned off. + * + * @param relMem : Memory where the function to be relocated [Needs to be word aligned] + * @param size : Size of the memory in Bytes + * @return Nothing + */ +void Chip_POWER_RelocAPI(uint32_t *relMem, uint32_t size); + +/* ROM versions */ +#define LPC5410X_ROMVER_0 (0x1100) +#define LPC5410X_ROMVER_1 (0x1101) +#define LPC5410X_ROMVER_2 (0x1102) + +/** + * @brief Fast powerdown for IRAM based applications + * @param peripheral_ctrl : Peripherals that will remain powered up in the power down state + * @return Nothing + * @note The 'peripheral_ctrl' field is a bitmask of bits from the + * PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which + * peripherals can wake up the chip from the power state. These + * peripherals are not powered down during the power state.
+ * This function should only be used when not executing code in FLASH. + * It will power down FLASH and leave it powered down on exit, so all + * code should be placed in IRAM prior to calling. It provides a quicker + * wakeup response than the default powerdown function + * (Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, ...)). + */ +void Chip_POWER_EnterPowerModeIramOnly(uint32_t peripheral_ctrl); + +/** + * @brief Return ROM version + * @return ROM version + * @note Will return one of the following version numbers:
+ * (0x1100) for v17.0 ROMs.
+ * (0x1101) for v17.1 ROMs.
+ * (0x1102) for v17.2 ROMs.
+ */ +uint32_t Chip_POWER_GetROMVersion(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __POWER_LIB_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/ring_buffer.h b/ports/lpc/chips/lpc_chip_5410x/inc/ring_buffer.h new file mode 100644 index 0000000000000..17086bfe4cdc5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/ring_buffer.h @@ -0,0 +1,194 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RING_BUFFER_H_ +#define __RING_BUFFER_H_ + +#include "lpc_types.h" +#include "cmsis.h" + +/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Ring buffer structure + */ +typedef struct { + void *data; + int count; + int itemSz; + uint32_t head; + uint32_t tail; + void *(*copy)(void *dst, const void *src, uint32_t len); +} RINGBUFF_T; + +/** + * @def RB_VHEAD(rb) + * volatile typecasted head index + */ +#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head) + +/** + * @def RB_VTAIL(rb) + * volatile typecasted tail index + */ +#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail) + +/** + * @brief Initialize ring buffer + * @param RingBuff : Pointer to ring buffer to initialize + * @param buffer : Pointer to buffer to associate with RingBuff + * @param itemSize : Size of each buffer item size + * @param count : Size of ring buffer + * @param cpyFunc : Call-back function that copies data (if NULL library @a memcpy will be used) + * @note Memory pointed by @a buffer must have correct alignment of + * @a itemSize, and @a count must be a power of 2 and must at + * least be 2 or greater. @a len of the @a cpyFunc is in bytes. + * @return Nothing + */ +int RingBuffer_Init(RINGBUFF_T *RingBuff, + void *buffer, + int itemSize, + int count, + void *(*cpyFunc)(void *dst, const void *src, uint32_t len)); + +/** + * @brief Resets the ring buffer to empty + * @param RingBuff : Pointer to ring buffer + * @return Nothing + */ +__STATIC_INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff) +{ + RingBuff->head = RingBuff->tail = 0; +} + +/** + * @brief Return size the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Size of the ring buffer in bytes + */ +__STATIC_INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff) +{ + return RingBuff->count; +} + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Number of items in the ring buffer + */ +__STATIC_INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff) +{ + return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff); +} + +/** + * @brief Return number of free items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Number of free items in the ring buffer + */ +__STATIC_INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff) +{ + return RingBuff->count - RingBuffer_GetCount(RingBuff); +} + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return 1 if the ring buffer is full, otherwise 0 + */ +__STATIC_INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff) +{ + return RingBuffer_GetCount(RingBuff) >= RingBuff->count; +} + +/** + * @brief Return empty status of ring buffer + * @param RingBuff : Pointer to ring buffer + * @return 1 if the ring buffer is empty, otherwise 0 + */ +__STATIC_INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff) +{ + return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff); +} + +/** + * @brief Insert a single item into ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : pointer to item + * @return 1 when successfully inserted, + * 0 on error (Buffer not initialized using + * RingBuffer_Init() or attempted to insert + * when buffer is full) + */ +int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data); + +/** + * @brief Insert an array of items into ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to first element of the item array + * @param num : Number of items in the array + * @return number of items successfully inserted, + * 0 on error (Buffer not initialized using + * RingBuffer_Init() or attempted to insert + * when buffer is full) + */ +int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num); + +/** + * @brief Pop an item from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to memory where popped item be stored + * @return 1 when item popped successfuly onto @a data, + * 0 When error (Buffer not initialized using + * RingBuffer_Init() or attempted to pop item when + * the buffer is empty) + */ +int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data); + +/** + * @brief Pop an array of items from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data : Pointer to memory where popped items be stored + * @param num : Max number of items array @a data can hold + * @return Number of items popped onto @a data, + * 0 on error (Buffer not initialized using RingBuffer_Init() + * or attempted to pop when the buffer is empty) + */ +int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num); + +/** + * @} + */ + +#endif /* __RING_BUFFER_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/ritimer_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/ritimer_5410x.h new file mode 100644 index 0000000000000..5f55ea92ae096 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/ritimer_5410x.h @@ -0,0 +1,249 @@ +/* + * @brief LPC5410x RITimer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RITIMER_5410X_H_ +#define __RITIMER_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RITIMER_5410X CHIP: LPC5410X Repetitive Interrupt Timer driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief Repetitive Interrupt Timer register block structure + */ +typedef struct { /*!< RITIMER Structure */ + __IO uint32_t COMPVAL; /*!< Compare register */ + __IO uint32_t MASK; /*!< Mask register */ + __IO uint32_t CTRL; /*!< Control register */ + __IO uint32_t COUNTER; /*!< 32-bit counter */ + __IO uint32_t COMPVAL_H; /*!< Compare register, upper 16-bits */ + __IO uint32_t MASK_H; /*!< Compare register, upper 16-bits */ + __I uint32_t reserved; + __IO uint32_t COUNTER_H; /*!< Counter register, upper 16-bits */ +} LPC_RITIMER_T; + +/* + * @brief RITIMER register support bitfields and mask + */ + +/* + * RIT control register + */ +/** Set by H/W when the counter value equals the masked compare value */ +#define RIT_CTRL_INT ((uint32_t) (1)) +/** Set timer enable clear to 0 when the counter value equals the masked compare value */ +#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1)) +/** Set timer enable on debug */ +#define RIT_CTRL_ENBR ((uint32_t) _BIT(2)) +/** Set timer enable */ +#define RIT_CTRL_TEN ((uint32_t) _BIT(3)) + +/** + * @brief Initialize the RIT + * @param pRITimer : RITimer peripheral selected + * @return None + */ +void Chip_RIT_Init(LPC_RITIMER_T *pRITimer); + +/** + * @brief Shutdown the RIT + * @param pRITimer : RITimer peripheral selected + * @return None + */ +void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer); + +/** + * @brief Enable Timer + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_TEN; +} + +/** + * @brief Disable Timer + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL &= ~RIT_CTRL_TEN; +} + +/** + * @brief Enable timer debug + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_DebugEnable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_ENBR; +} + +/** + * @brief Disable timer debug + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_DebugDisable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL &= ~RIT_CTRL_ENBR; +} + +/** + * @brief Enable clear on compare match + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_CompClearEnable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_ENCLR; +} + +/** + * @brief Disable clear on compare match + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_CompClearDisable(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL &= ~RIT_CTRL_ENCLR; +} + +/** + * @brief Check whether interrupt flag is set or not + * @param pRITimer : RITimer peripheral selected + * @return Current interrupt status, either ET or UNSET + */ +IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer); + +/** + * @brief Set a tick value for the interrupt to time out + * @param pRITimer : RITimer peripheral selected + * @param val : value (in ticks) of the interrupt to be set + * @return None + */ +__STATIC_INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val) +{ + pRITimer->COMPVAL = val; + pRITimer->COMPVAL_H = 0; +} + +/** + * @brief Set a tick value for the interrupt to time out (48-bits) + * @param pRITimer : RITimer peripheral selected + * @param val : value (in ticks) of the interrupt to be set, 48-bits max + * @return None + */ +__STATIC_INLINE void Chip_RIT_SetCOMPVAL64(LPC_RITIMER_T *pRITimer, uint64_t val) +{ + pRITimer->COMPVAL = (uint32_t) (val & 0xFFFFFFFF); + pRITimer->COMPVAL_H = (uint32_t) ((val >> 32) & 0xFFFF); +} + +/** + * @brief Enables or clears the RIT or interrupt + * @param pRITimer : RITimer peripheral selected + * @param val : RIT to be set, one or more RIT_CTRL_* values + * @return None + */ +__STATIC_INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val) +{ + pRITimer->CTRL |= val; +} + +/** + * @brief Clears the RIT interrupt + * @param pRITimer : RITimer peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL |= RIT_CTRL_INT; +} + +/** + * @brief Returns the current RIT Counter value + * @param pRITimer : RITimer peripheral selected + * @return the current timer counter value + */ +__STATIC_INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer) +{ + return pRITimer->COUNTER; +} + +/** + * @brief Returns the current RIT Counter value (48-bit) + * @param pRITimer : RITimer peripheral selected + * @return the current timer counter value + */ +__STATIC_INLINE uint64_t Chip_RIT_GetCounter64(LPC_RITIMER_T *pRITimer) +{ + uint64_t retVal; + + retVal = (uint64_t) pRITimer->COUNTER; + retVal = retVal | (((uint64_t) pRITimer->COUNTER_H) << 32); + + return retVal; +} + +/** + * @brief Set timer interval value + * @param pRITimer : RITimer peripheral selected + * @param time_interval : timer interval value (ms) + * @return None + */ +void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval); + +/** + * @brief Set timer interval value (48-bit) + * @param pRITimer : RITimer peripheral selected + * @param time_interval : timer interval value (ms) + * @return None + */ +void Chip_RIT_SetTimerInterval64(LPC_RITIMER_T *pRITimer, uint64_t time_interval); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RITIMER_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/romapi_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/romapi_5410x.h new file mode 100644 index 0000000000000..63a4920c7a141 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/romapi_5410x.h @@ -0,0 +1,90 @@ +/* + * @brief LPC5410X ROM API declarations and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ROMAPI_5410X_H_ +#define __ROMAPI_5410X_H_ + +#include +#include "iap.h" +#include "error.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ROMAPI_5410X CHIP: LPC5410X ROM API declarations and functions + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief High level ROM API structure + */ +typedef struct { + const uint32_t reserved_usb; /*!< Reserved */ + const uint32_t reserved_clib; /*!< Reserved */ + const uint32_t reserved_can; /*!< Reserved */ + const uint32_t reserved_pwrd; /*!< Reserved */ + const uint32_t reserved_div; /*!< Reserved */ + const uint32_t reserved_i2cd; /*!< Reserved */ + const uint32_t reserved_dmad; /*!< Reserved */ + const uint32_t reserved_spid; /*!< Reserved */ + const uint32_t reserved_adcd; /*!< Reserved */ + const uint32_t reserved_uartd; /*!< Reserved */ + const uint32_t reserved_vfifo; /*!< Reserved */ + const uint32_t reserved_usart; /*!< Reserved */ +} LPC_ROM_API_T; + +/* Pointer to ROM API function address */ +#define LPC_ROM_API_BASE_LOC 0x03000200UL +#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC) + +/* Pointer to ROM IAP entry functions */ +#define IAP_ENTRY_LOCATION 0x03000205 + +/** + * @brief LPC5410x IAP_ENTRY API function type + */ +static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4]) +{ + ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ROMAPI_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/rtc_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/rtc_5410x.h new file mode 100644 index 0000000000000..8320d591da3e7 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/rtc_5410x.h @@ -0,0 +1,310 @@ +/* + * @brief LPC5410X RTC chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_5410X_H_ +#define __RTC_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RTC_5410X CHIP: LPC5410X Real Time clock + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X Real Time clock register block structure + */ +typedef struct { /*!< RTC */ + __IO uint32_t CTRL; /*!< RTC control register */ + __IO uint32_t MATCH; /*!< PRTC match (alarm) register */ + __IO uint32_t COUNT; /*!< RTC counter register */ + __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */ +} LPC_RTC_T; + +/* CTRL register defniitions */ +#define RTC_CTRL_SWRESET (1 << 0) /*!< Apply reset to RTC */ +#define RTC_CTRL_OFD (1 << 1) /*!< Oscillator fail detect status (failed bit) */ +#define RTC_CTRL_ALARM1HZ (1 << 2) /*!< RTC 1 Hz timer alarm flag status (match) bit */ +#define RTC_CTRL_WAKE1KHZ (1 << 3) /*!< RTC 1 kHz timer wake-up flag status (timeout) bit */ +#define RTC_CTRL_ALARMDPD_EN (1 << 4) /*!< RTC 1 Hz timer alarm for Deep power-down enable bit */ +#define RTC_CTRL_WAKEDPD_EN (1 << 5) /*!< RTC 1 kHz timer wake-up for Deep power-down enable bit */ +#define RTC_CTRL_RTC1KHZ_EN (1 << 6) /*!< RTC 1 kHz clock enable bit */ +#define RTC_CTRL_RTC_EN (1 << 7) /*!< RTC enable bit */ +#define RTC_CTRL_MASK ((uint32_t) 0xF1) /*!< RTC Control register Mask for reserved and status bits */ + +/** + * @brief Initialize the RTC peripheral + * @param pRTC : RTC peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RTC_Init(LPC_RTC_T *pRTC) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_RTC); + Chip_SYSCON_PeriphReset(RESET_RTC); +} + +/** + * @brief De-initialize the RTC peripheral + * @param pRTC : RTC peripheral selected + * @return None + */ +__STATIC_INLINE void Chip_RTC_DeInit(LPC_RTC_T *pRTC) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_RTC); +} + +/** + * @brief Enable RTC options + * @param pRTC : The base address of RTC block + * @param flags : And OR'ed value of RTC_CTRL_* definitions to enable + * @return Nothing + * @note You can enable multiple RTC options at once using this function + * by OR'ing them together. It is recommended to only use the + * RTC_CTRL_ALARMDPD_EN, RTC_CTRL_WAKEDPD_EN, RTC_CTRL_RTC1KHZ_EN, and + * RTC_CTRL_RTC_EN flags with this function. + */ +__STATIC_INLINE void Chip_RTC_EnableOptions(LPC_RTC_T *pRTC, uint32_t flags) +{ + pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) | flags; +} + +/** + * @brief Disable RTC options + * @param pRTC : The base address of RTC block + * @param flags : And OR'ed value of RTC_CTRL_* definitions to disable + * @return Nothing + * @note You can enable multiple RTC options at once using this function + * by OR'ing them together. It is recommended to only use the + * RTC_CTRL_ALARMDPD_EN, RTC_CTRL_WAKEDPD_EN, RTC_CTRL_RTC1KHZ_EN, and + * RTC_CTRL_RTC_EN flags with this function. + */ +__STATIC_INLINE void Chip_RTC_DisableOptions(LPC_RTC_T *pRTC, uint32_t flags) +{ + pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) & ~flags; +} + +/** + * @brief Reset RTC + * @param pRTC : The base address of RTC block + * @return Nothing + * @note The RTC state will be returned to it's default. + */ +__STATIC_INLINE void Chip_RTC_Reset(LPC_RTC_T *pRTC) +{ + Chip_RTC_EnableOptions(pRTC, RTC_CTRL_SWRESET); + Chip_RTC_DisableOptions(pRTC, RTC_CTRL_SWRESET); +} + +/** + * @brief Enables the RTC + * @param pRTC : The base address of RTC block + * @return Nothing + * @note You can also use Chip_RTC_EnableOptions() with the + * RTC_CTRL_RTC_EN flag to enable the RTC. + */ +__STATIC_INLINE void Chip_RTC_Enable(LPC_RTC_T *pRTC) +{ + Chip_RTC_EnableOptions(pRTC, RTC_CTRL_RTC_EN); +} + +/** + * @brief Disables the RTC + * @param pRTC : The base address of RTC block + * @return Nothing + * @note You can also use Chip_RTC_DisableOptions() with the + * RTC_CTRL_RTC_EN flag to enable the RTC. + */ +__STATIC_INLINE void Chip_RTC_Disable(LPC_RTC_T *pRTC) +{ + Chip_RTC_DisableOptions(pRTC, RTC_CTRL_RTC_EN); +} + +/** + * @brief Enables the RTC 1KHz high resolution timer + * @param pRTC : The base address of RTC block + * @return Nothing + * @note You can also use Chip_RTC_EnableOptions() with the + * RTC_CTRL_RTC1KHZ_EN flag to enable the high resolution + * timer. + */ +__STATIC_INLINE void Chip_RTC_Enable1KHZ(LPC_RTC_T *pRTC) +{ + Chip_RTC_EnableOptions(pRTC, RTC_CTRL_RTC1KHZ_EN); +} + +/** + * @brief Disables the RTC 1KHz high resolution timer + * @param pRTC : The base address of RTC block + * @return Nothing + * @note You can also use Chip_RTC_DisableOptions() with the + * RTC_CTRL_RTC1KHZ_EN flag to disable the high resolution + * timer. + */ +__STATIC_INLINE void Chip_RTC_Disable1KHZ(LPC_RTC_T *pRTC) +{ + Chip_RTC_DisableOptions(pRTC, RTC_CTRL_RTC1KHZ_EN); +} + +/** + * @brief Enables selected RTC wakeup events + * @param pRTC : The base address of RTC block + * @param ints : Wakeup events to enable + * @return Nothing + * @note Select either one or both (OR'ed) RTC_CTRL_ALARMDPD_EN + * and RTC_CTRL_WAKEDPD_EN values to enabled. You can also + * use Chip_RTC_EnableOptions() with the flags to enable + * the events. + */ +__STATIC_INLINE void Chip_RTC_EnableWakeup(LPC_RTC_T *pRTC, uint32_t ints) +{ + Chip_RTC_EnableOptions(pRTC, ints); +} + +/** + * @brief Disables selected RTC wakeup events + * @param pRTC : The base address of RTC block + * @param ints : Wakeup events to disable + * @return Nothing + * @note Select either one or both (OR'ed) RTC_CTRL_ALARMDPD_EN + * and RTC_CTRL_WAKEDPD_EN values to disabled. You can also + * use Chip_RTC_DisableOptions() with the flags to disable + * the events. + */ +__STATIC_INLINE void Chip_RTC_DisableWakeup(LPC_RTC_T *pRTC, uint32_t ints) +{ + Chip_RTC_DisableOptions(pRTC, ints); +} + +/** + * @brief Clears latched RTC statuses + * @param pRTC : The base address of RTC block + * @param stsMask : OR'ed status bits to clear + * @return Nothing + * @note Use and OR'ed stsMask value of RTC_CTRL_OFD, RTC_CTRL_ALARM1HZ, + * and RTC_CTRL_WAKE1KHZ to clear specific RTC states. + */ +__STATIC_INLINE void Chip_RTC_ClearStatus(LPC_RTC_T *pRTC, uint32_t stsMask) +{ + pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) | stsMask; +} + +/** + * @brief Return RTC control/status register + * @param pRTC : The base address of RTC block + * @return The current RTC control/status register + * @note Mask the return value with a RTC_CTRL_* definitions to determine + * which bits are set. For example, mask the return value with + * RTC_CTRL_ALARM1HZ to determine if the alarm interrupt is pending. + */ +__STATIC_INLINE uint32_t Chip_RTC_GetStatus(LPC_RTC_T *pRTC) +{ + return pRTC->CTRL; +} + +/** + * @brief Set RTC match value for alarm status/interrupt + * @param pRTC : The base address of RTC block + * @param count : Alarm event time + * @return Nothing + */ +__STATIC_INLINE void Chip_RTC_SetAlarm(LPC_RTC_T *pRTC, uint32_t count) +{ + pRTC->MATCH = count; +} + +/** + * @brief Return the RTC match value used for alarm status/interrupt + * @param pRTC : The base address of RTC block + * @return Alarm event time + */ +__STATIC_INLINE uint32_t Chip_RTC_GetAlarm(LPC_RTC_T *pRTC) +{ + return pRTC->MATCH; +} + +/** + * @brief Set RTC match count for 1 second timer count + * @param pRTC : The base address of RTC block + * @param count : Initial count to set + * @return Nothing + * @note Only write to this register when the RTC_CTRL_RTC_EN bit in + * the CTRL Register is 0. The counter increments one second + * after the RTC_CTRL_RTC_EN bit is set. + */ +__STATIC_INLINE void Chip_RTC_SetCount(LPC_RTC_T *pRTC, uint32_t count) +{ + pRTC->COUNT = count; +} + +/** + * @brief Get current RTC 1 second timer count + * @param pRTC : The base address of RTC block + * @return current RTC 1 second timer count + */ +__STATIC_INLINE uint32_t Chip_RTC_GetCount(LPC_RTC_T *pRTC) +{ + return pRTC->COUNT; +} + +/** + * @brief Set RTC wake count countdown value (in mS ticks) + * @param pRTC : The base address of RTC block + * @param count : wakeup time in milliSeconds + * @return Nothing + * @note A write pre-loads a start count value into the wake-up + * timer and initializes a count-down sequence. + */ +__STATIC_INLINE void Chip_RTC_SetWake(LPC_RTC_T *pRTC, uint16_t count) +{ + pRTC->WAKE = count; +} + +/** + * @brief Get RTC wake count countdown value + * @param pRTC : The base address of RTC block + * @return current RTC wake count countdown value (in mS) + */ +__STATIC_INLINE uint16_t Chip_RTC_GetWake(LPC_RTC_T *pRTC) +{ + return pRTC->WAKE; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/rtc_ut.h b/ports/lpc/chips/lpc_chip_5410x/inc/rtc_ut.h new file mode 100644 index 0000000000000..f535b6ae327ab --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/rtc_ut.h @@ -0,0 +1,84 @@ +/* + * @brief RTC tick to (a more) Universal Time + * Adds conversion functions to use an RTC that only provides a + * seconds capability to provide "struct tm" support. + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_UT_H_ +#define __RTC_UT_H_ + +#include "chip.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RTC_UT CHIP: RTC tick to (a more) Universal Time conversion functions + * @ingroup CHIP_Common + * This driver converts between a RTC 1-second tick value and + * a Universal time format in a structure of type 'struct tm'. + * @{ + */ + +/* Starting year and starting day of week for the driver */ +#define TM_YEAR_BASE (1970) +#define TM_DAYOFWEEK (3) + +/** + * @brief Converts a RTC tick time to Universal time + * @param rtcTick : Current RTC time value + * @param pTime : Pointer to time structure to fill + * @return Nothing + * @note When setting time, the 'tm_wday', 'tm_yday', and 'tm_isdst' + * fields are not used. + */ +void ConvertRtcTime(uint32_t rtcTick, struct tm *pTime); + +/** + * @brief Converts a Universal time to RTC tick time + * @param pTime : Pointer to time structure to use + * @param rtcTick : Pointer to RTC time value to fill + * @return Nothing + * @note When converting time, the 'tm_isdst' field is not + * populated by the conversion function. + */ +void ConvertTimeRtc(struct tm *pTime, uint32_t *rtcTick); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_UT_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/sct_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/sct_5410x.h new file mode 100644 index 0000000000000..afb2d0bfa4a4e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/sct_5410x.h @@ -0,0 +1,543 @@ +/* + * @brief LPC5410X State Configurable Timer (SCT) Chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCT_5410X_H_ +#define __SCT_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCT_5410X CHIP: LPC5410X State Configurable Timer driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* match/cap registers, events, states, inputs, outputs + * + * @brief SCT Module configuration + */ +#define CONFIG_SCT_nEV (13) /*!< Number of events */ +#define CONFIG_SCT_nRG (13) /*!< Number of match/compare registers */ +#define CONFIG_SCT_nOU (8) /*!< Number of outputs */ +#define CONFIG_SCT_nIN (8) /*!< Number of outputs */ + +/** + * @brief State Configurable Timer register block structure + */ +typedef struct { + __IO uint32_t CONFIG; /*!< configuration Register (offset (0x000) */ + union { + __IO uint32_t CTRL_U; /*!< control Register */ + struct { + __IO uint16_t CTRL_L; /*!< low control register */ + __IO uint16_t CTRL_H; /*!< high control register */ + }; + + }; + + union { + __IO uint32_t LIMIT_U; /*!< limit Register */ + struct { + __IO uint16_t LIMIT_L; /*!< limit register for counter L */ + __IO uint16_t LIMIT_H; /*!< limit register for counter H */ + }; + + }; + + union { + __IO uint32_t HALT_U; /*!< halt Register */ + struct { + __IO uint16_t HALT_L; /*!< halt register for counter L */ + __IO uint16_t HALT_H; /*!< halt register for counter H */ + }; + + }; + + union { + __IO uint32_t STOP_U; /*!< stop Register */ + struct { + __IO uint16_t STOP_L; /*!< stop register for counter L */ + __IO uint16_t STOP_H; /*!< stop register for counter H */ + }; + + }; + + union { + __IO uint32_t START_U; /*!< start Register */ + struct { + __IO uint16_t START_L; /*!< start register for counter L */ + __IO uint16_t START_H; /*!< start register for counter H */ + }; + + }; + + uint32_t RESERVED1[10]; /*!< 0x018 - 0x03C reserved */ + + union { + __IO uint32_t COUNT_U; /*!< counter register (offset 0x040)*/ + struct { + __IO uint16_t COUNT_L; /*!< counter register for counter L */ + __IO uint16_t COUNT_H; /*!< counter register for counter H */ + }; + + }; + + union { + __IO uint32_t STATE_U; /*!< State register */ + struct { + __IO uint16_t STATE_L; /*!< state register for counter L */ + __IO uint16_t STATE_H; /*!< state register for counter H */ + }; + + }; + + __I uint32_t INPUT; /*!< input register */ + union { + __IO uint32_t REGMODE_U; /*!< RegMode register */ + struct { + __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */ + __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */ + }; + + }; + + __IO uint32_t OUTPUT; /*!< output register */ + __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */ + __IO uint32_t RES; /*!< conflict resolution register */ + __IO uint32_t DMAREQ0; /*!< DMA0 Request Register */ + __IO uint32_t DMAREQ1; /*!< DMA1 Request Register */ + uint32_t RESERVED2[35]; + __IO uint32_t EVEN; /*!< event enable register */ + __IO uint32_t EVFLAG; /*!< event flag register */ + __IO uint32_t CONEN; /*!< conflict enable register */ + __IO uint32_t CONFLAG; /*!< conflict flag register */ + + union { + + __IO union { /*!< ... Match / Capture value */ + uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */ + + struct { + uint16_t L; /*!< SCTMATCH[i].L Access to L value */ + uint16_t H; /*!< SCTMATCH[i].H Access to H value */ + }; + + } MATCH[CONFIG_SCT_nRG]; + + __I union { + uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */ + + struct { + uint16_t L; /*!< SCTCAP[i].L Access to L value */ + uint16_t H; /*!< SCTCAP[i].H Access to H value */ + }; + + } CAP[CONFIG_SCT_nRG]; + + }; + + uint32_t RESERVED3[48 + (16 - CONFIG_SCT_nRG)]; + + union { + + __IO union { /* 0x200-... Match Reload / Capture Control value */ + uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ + + struct { + uint16_t L; /* SCTMATCHREL[i].L Access to L value */ + uint16_t H; /* SCTMATCHREL[i].H Access to H value */ + }; + + } MATCHREL[CONFIG_SCT_nRG]; + + __IO union { + uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ + + struct { + uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ + uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ + }; + + } CAPCTRL[CONFIG_SCT_nRG]; + + }; + + uint32_t RESERVED6[48 + (16 - CONFIG_SCT_nRG)]; + + __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ + uint32_t STATE; /* Event State Register */ + uint32_t CTRL; /* Event Control Register */ + } EVENT[CONFIG_SCT_nEV]; + + uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */ + + __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ + uint32_t SET; /*!< Output n Set Register */ + uint32_t CLR; /*!< Output n Clear Register */ + } OUT[CONFIG_SCT_nOU]; + + uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */ + __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */ +} LPC_SCT_T; + +/** + * @brief Macro defines for SCT configuration register + */ +#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */ +#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */ + +#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */ +#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */ +#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */ +#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */ + +#define SCT_CONFIG_CLKMODE_SYSCLK (0x0 << 1) /*!< System clock */ +#define SCT_CONFIG_CLKMODE_PRESCALED_SYSCLK (0x1 << 1) /*!< Prescaled system clock */ +#define SCT_CONFIG_CLKMODE_SCT_INPUT (0x2 << 1) /*!< Input clock/edge selected in CKSEL field */ +#define SCT_CONFIG_CLKMODE_PRESCALED_SCT_INPUT (0x3 << 1) /*!< Prescaled input clock/edge selected in CKSEL field */ + +#define SCT_CONFIG_CKSEL_RISING_IN_0 (0x0UL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_0 (0x1UL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_1 (0x2UL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_1 (0x3UL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_2 (0x4UL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_2 (0x5UL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_3 (0x6UL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_3 (0x7UL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_4 (0x8UL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_4 (0x9UL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_5 (0xAUL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_5 (0xBUL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_6 (0xCUL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_6 (0xDUL << 3) +#define SCT_CONFIG_CKSEL_RISING_IN_7 (0xEUL << 3) +#define SCT_CONFIG_CKSEL_FALLING_IN_7 (0xFUL << 3) +#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */ +#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */ +#define SCT_CONFIG_AUTOLIMIT_U (0x1UL << 17) +#define SCT_CONFIG_AUTOLIMIT_L (0x1UL << 17) +#define SCT_CONFIG_AUTOLIMIT_H (0x1UL << 18) + +/** + * @brief Macro defines for SCT control register + */ +#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */ +#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 + +#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */ +#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */ +#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */ +#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */ +#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */ + +#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */ +#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 +#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */ +#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */ +#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */ +#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20) +#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */ + +#define SCT_EV_CTRL_MATCHSEL(reg) (reg << 0) +#define SCT_EV_CTRL_HEVENT_L (0UL << 4) +#define SCT_EV_CTRL_HEVENT_H (1UL << 4) +#define SCT_EV_CTRL_OUTSEL_INPUT (0UL << 5) +#define SCT_EV_CTRL_OUTSEL_OUTPUT (0UL << 5) +#define SCT_EV_CTRL_IOSEL(signal) (signal << 6) + +#define SCT_EV_CTRL_IOCOND_LOW (0UL << 10) +#define SCT_EV_CTRL_IOCOND_RISE (0x1UL << 10) +#define SCT_EV_CTRL_IOCOND_FALL (0x2UL << 10) +#define SCT_EV_CTRL_IOCOND_HIGH (0x3UL << 10) +#define SCT_EV_CTRL_COMBMODE_OR (0x0UL << 12) +#define SCT_EV_CTRL_COMBMODE_MATCH (0x1UL << 12) +#define SCT_EV_CTRL_COMBMODE_IO (0x2UL << 12) +#define SCT_EV_CTRL_COMBMODE_AND (0x3UL << 12) +#define SCT_EV_CTRL_STATELD (0x1UL << 14) +#define SCT_EV_CTRL_STATEV(x) (x << 15) +#define SCT_EV_CTRL_MATCHMEM (0x1UL << 20) +#define SCT_EV_CTRL_DIRECTION_INDEPENDENT (0x0UL << 21) +#define SCT_EV_CTRL_DIRECTION_UP (0x1UL << 21) +#define SCT_EV_CTRL_DIRECTION_DOWN (0x2UL << 21) + +/** + * @brief Macro defines for SCT Conflict resolution register + */ +#define SCT_RES_NOCHANGE (0) +#define SCT_RES_SET_OUTPUT (1) +#define SCT_RES_CLEAR_OUTPUT (2) +#define SCT_RES_TOGGLE_OUTPUT (3) + +/** + * SCT Match register values enum + */ +typedef enum CHIP_SCT_MATCH_REG { + SCT_MATCH_0 = 0, /*!< SCT Match register 0 */ + SCT_MATCH_1, + SCT_MATCH_2, + SCT_MATCH_3, + SCT_MATCH_4, + SCT_MATCH_5, + SCT_MATCH_6, + SCT_MATCH_7, + SCT_MATCH_8, + SCT_MATCH_9, + SCT_MATCH_10, + SCT_MATCH_11, + SCT_MATCH_12, + SCT_MATCH_13, + SCT_MATCH_14, + SCT_MATCH_15 +} CHIP_SCT_MATCH_REG_T; + +/** + * SCT Event values enum + */ +typedef enum CHIP_SCT_EVENT { + SCT_EVT_0 = (1 << 0), /*!< Event 0 */ + SCT_EVT_1 = (1 << 1), /*!< Event 1 */ + SCT_EVT_2 = (1 << 2), /*!< Event 2 */ + SCT_EVT_3 = (1 << 3), /*!< Event 3 */ + SCT_EVT_4 = (1 << 4), /*!< Event 4 */ + SCT_EVT_5 = (1 << 5), /*!< Event 5 */ + SCT_EVT_6 = (1 << 6), /*!< Event 6 */ + SCT_EVT_7 = (1 << 7), /*!< Event 7 */ + SCT_EVT_8 = (1 << 8), /*!< Event 8 */ + SCT_EVT_9 = (1 << 9), /*!< Event 9 */ + SCT_EVT_10 = (1 << 10), /*!< Event 10 */ + SCT_EVT_11 = (1 << 11), /*!< Event 11 */ + SCT_EVT_12 = (1 << 12), /*!< Event 12 */ + SCT_EVT_13 = (1 << 13), /*!< Event 13 */ + SCT_EVT_14 = (1 << 14), /*!< Event 14 */ + SCT_EVT_15 = (1 << 15) /*!< Event 15 */ +} CHIP_SCT_EVENT_T; + +/** + * @brief Set event control register + * @param pSCT : The base of SCT peripheral on the chip + * @param event_number + * @param value : The 32-bit event control setting + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_EventControl(LPC_SCT_T *pSCT, uint32_t event_number, + uint32_t value) { + pSCT->EVENT[event_number].CTRL = value; +} + +/** + * @brief Set event state mask register + * @param pSCT : The base of SCT peripheral on the chip + * @param event_number + * @param event_state_mask : The 32-bit event state mask setting + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_EventStateMask(LPC_SCT_T *pSCT, uint32_t event_number, + uint32_t event_state_mask) { + pSCT->EVENT[event_number].STATE = event_state_mask; +} + +/** + * @brief Set configuration register + * @param pSCT : The base of SCT peripheral on the chip + * @param cfg : The 32-bit configuration setting + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t cfg) { + pSCT->CONFIG = cfg; +} + +/** + * @brief Configures the Limit register + * @param pSCT : The base of SCT peripheral on the chip + * @param value : The 32-bit Limit register value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_Limit(LPC_SCT_T *pSCT, uint32_t value) { + pSCT->LIMIT_L = value; +} + +/** + * @brief Set or Clear the Control register + * @param pSCT : Pointer to SCT register block + * @param value : SCT Control register value + * @param ena : ENABLE - To set the fields specified by value + * : DISABLE - To clear the field specified by value + * @return Nothing + * Set or clear the control register bits as specified by the \a value + * parameter. If \a ena is set to ENABLE, the mentioned register fields + * will be set. If \a ena is set to DISABLE, the mentioned register + * fields will be cleared + */ +void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena); + +/** + * @brief Set the conflict resolution + * @param pSCT : Pointer to SCT register block + * @param outnum : Output number + * @param value : Output value + * - SCT_RES_NOCHANGE :No change + * - SCT_RES_SET_OUTPUT :Set output + * - SCT_RES_CLEAR_OUTPUT :Clear output + * - SCT_RES_TOGGLE_OUTPUT :Toggle output + * : SCT_RES_NOCHANGE + * : DISABLE - To clear the field specified by value + * @return Nothing + * Set conflict resolution for the output \a outnum + */ +void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value); + +/** + * @brief Set unified count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 32-bit count value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count) { + pSCT->COUNT_U = count; +} + +/** + * @brief Set lower count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 16-bit count value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count) { + pSCT->COUNT_L = count; +} + +/** + * @brief Set higher count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param count : The 16-bit count value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count) { + pSCT->COUNT_H = count; +} + +/** + * @brief Set unified match count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param n : Match register value + * @param value : The 32-bit match count value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetMatchCount(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) { + pSCT->MATCH[n].U = value; +} + +/** + * @brief Set unified match reload count value in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param n : Match register value + * @param value : The 32-bit match count reload value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetMatchReload(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) { + pSCT->MATCHREL[n].U = value; +} + +/** + * @brief Enable the interrupt for the specified event in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_EnableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { + pSCT->EVEN |= evt; +} + +/** + * @brief Disable the interrupt for the specified event in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_DisableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { + pSCT->EVEN &= ~(evt); +} + +/** + * @brief Clear the specified event flag in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param evt : Event value + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_ClearEventFlag(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { + pSCT->EVFLAG |= evt; +} + +/** + * @brief Set control register in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param value : Value (ORed value of SCT_CTRL_* bits) + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value) { + pSCT->CTRL_U |= value; +} + +/** + * @brief Clear control register in State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @param value : Value (ORed value of SCT_CTRL_* bits) + * @return Nothing + */ +__STATIC_INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value) { + pSCT->CTRL_U &= ~(value); +} + +/** + * @brief Initializes the State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @return Nothing + */ +void Chip_SCT_Init(LPC_SCT_T *pSCT); + +/** + * @brief Deinitializes the State Configurable Timer + * @param pSCT : The base of SCT peripheral on the chip + * @return Nothing + */ +void Chip_SCT_DeInit(LPC_SCT_T *pSCT); + +/** + * @} + */ + +#ifdef __cplusplus +} + +#endif + +#endif /* __SCT_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/sct_pwm_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/sct_pwm_5410x.h new file mode 100644 index 0000000000000..342a31f95fbac --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/sct_pwm_5410x.h @@ -0,0 +1,178 @@ +/* + * @brief LPC5410x State Configurable Timer (SCT/PWM) Chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCT_PWM_5410X_H_ +#define __SCT_PWM_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCT_PWM_5410X CHIP: LPC5410X State Configurable Timer PWM driver + * + * For more information on how to use the driver please visit the FAQ page at + * + * www.lpcware.com + * + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief Get number of ticks per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @return Number ot ticks that will be counted per cycle + * @note Return value of this function will be vaild only + * after calling Chip_SCTPWM_SetRate() + */ +__STATIC_INLINE uint32_t Chip_SCTPWM_GetTicksPerCycle(LPC_SCT_T *pSCT) +{ + return pSCT->MATCHREL[0].U; +} + +/** + * @brief Converts a percentage to ticks + * @param pSCT : The base of SCT peripheral on the chip + * @param percent : Percentage to convert (0 - 100) + * @return Number ot ticks corresponding to given percentage + * @note Do not use this function when using very low + * pwm rate (like 100Hz or less), on a chip that has + * very high frequency as the calculation might + * cause integer overflow + */ +__STATIC_INLINE uint32_t Chip_SCTPWM_PercentageToTicks(LPC_SCT_T *pSCT, uint8_t percent) +{ + return (Chip_SCTPWM_GetTicksPerCycle(pSCT) * percent) / 100; +} + +/** + * @brief Get number of ticks on per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @param index : Index of the PWM 1 to N (see notes) + * @return Number ot ticks for which the output will be ON per cycle + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. + */ +__STATIC_INLINE uint32_t Chip_SCTPWM_GetDutyCycle(LPC_SCT_T *pSCT, uint8_t index) +{ + return pSCT->MATCHREL[index].U; +} + +/** + * @brief Get number of ticks on per PWM cycle + * @param pSCT : The base of SCT peripheral on the chip + * @param index : Index of the PWM 1 to N (see notes) + * @param ticks : Number of ticks the output should say ON + * @return None + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. The new duty cycle will be effective only + * after completion of current PWM cycle. + */ +__STATIC_INLINE void Chip_SCTPWM_SetDutyCycle(LPC_SCT_T *pSCT, uint8_t index, uint32_t ticks) +{ + Chip_SCT_SetMatchReload(pSCT, (CHIP_SCT_MATCH_REG_T) index, ticks); +} + +/** + * @brief Initialize the SCT/PWM clock and reset + * @param pSCT : The base of SCT peripheral on the chip + * @return None + */ +__STATIC_INLINE void Chip_SCTPWM_Init(LPC_SCT_T *pSCT) +{ + Chip_SCT_Init(pSCT); +} + +/** + * @brief Start the SCT PWM + * @param pSCT : The base of SCT peripheral on the chip + * @return None + * @note This function must be called after all the + * configuration is completed. Do not call Chip_SCTPWM_SetRate() + * or Chip_SCTPWM_SetOutPin() after the SCT/PWM is started. Use + * Chip_SCTPWM_Stop() to stop the SCT/PWM before reconfiguring, + * Chip_SCTPWM_SetDutyCycle() can be called when the SCT/PWM is + * running to change the DutyCycle. + */ +__STATIC_INLINE void Chip_SCTPWM_Start(LPC_SCT_T *pSCT) +{ + Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); +} + +/** + * @brief Stop the SCT PWM + * @param pSCT : The base of SCT peripheral on the chip + * @return None + */ +__STATIC_INLINE void Chip_SCTPWM_Stop(LPC_SCT_T *pSCT) +{ + /* Stop SCT */ + Chip_SCT_SetControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); + + /* Clear the counter */ + Chip_SCT_SetControl(pSCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_CLRCTR_H); +} + +/** + * @brief Sets the frequency of the generated PWM wave + * @param pSCT : The base of SCT peripheral on the chip + * @param freq : Frequency in Hz + * @return None + */ +void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq); + +/** + * @brief Setup the OUTPUT pin and associate it with an index + * @param pSCT : The base of the SCT peripheral on the chip + * @param index : Index of PWM 1 to N (see notes) + * @param pin : COUT pin to be associated with the index + * @return None + * @note @a index will be 1 to N where N is the "Number of + * match registers available in the SCT - 1" or + * "Number of OUTPUT pins available in the SCT" whichever + * is minimum. + */ +void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin); + +/** + * @} + */ + +#ifdef __cplusplus +} + +#endif + +#endif /* __SCT_PWM_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/spi_common_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/spi_common_5410x.h new file mode 100644 index 0000000000000..24d20ab5ded1b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/spi_common_5410x.h @@ -0,0 +1,701 @@ +/* + * @brief LPC5410X SPI common functions and definitions + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPI_COMMON_5410X_H_ +#define __SPI_COMMON_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SPI_COMMON_5410X CHIP: LPC5410X SPI driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief SPI register block structure + */ +typedef struct { /*!< SPI Structure */ + __IO uint32_t CFG; /*!< SPI Configuration register */ + __IO uint32_t DLY; /*!< SPI Delay register */ + __IO uint32_t STAT; /*!< SPI Status register */ + __IO uint32_t INTENSET; /*!< SPI Interrupt Enable Set register */ + __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear register */ + __I uint32_t RXDAT; /*!< SPI Receive Data register */ + __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control register */ + __O uint32_t TXDAT; /*!< SPI Transmit Data register */ + __IO uint32_t TXCTRL; /*!< SPI Transmit Control register */ + __IO uint32_t DIV; /*!< SPI clock Divider register */ + __I uint32_t INTSTAT; /*!< SPI Interrupt Status register */ +} LPC_SPI_T; + +/** + * Macro defines for SPI Configuration register + */ +#define SPI_CFG_BITMASK (0xFBD) /** SPI register bit mask */ +#define SPI_CFG_SPI_EN (1 << 0) /** SPI Slave Mode Select */ +#define SPI_CFG_SLAVE_EN (0 << 0) /** SPI Master Mode Select */ +#define SPI_CFG_MASTER_EN (1 << 2) /** SPI MSB First mode enable */ +#define SPI_CFG_MSB_FIRST_EN (0 << 3) /** SPI LSB First mode enable */ +#define SPI_CFG_LSB_FIRST_EN (1 << 3) /** SPI Clock Phase Select */ +#define SPI_CFG_CPHA_FIRST (0 << 4) /** Capture data on the first edge, Change data on the following edge */ +#define SPI_CFG_CPHA_SECOND (1 << 4) /** SPI Clock Polarity Select */ +#define SPI_CFG_CPOL_LO (0 << 5) /** The rest state of the clock (between frames) is low. */ +#define SPI_CFG_CPOL_HI (1 << 5) /** The rest state of the clock (between frames) is high. */ +#define SPI_CFG_LBM_EN (1 << 7) /** SPI control 1 loopback mode enable */ +#define SPI_CFG_SPOL_LO (0 << 8) /** SPI SSEL0 Polarity Select */ +#define SPI_CFG_SPOL_HI (1 << 8) /** SSEL0 is active High */ +#define SPI_CFG_SPOLNUM_HI(n) (1 << ((n) + 8)) /** SSELN is active High, selects 0 - 3 */ + +/** + * Macro defines for SPI Delay register + */ +#define SPI_DLY_BITMASK (0xFFFF) /** SPI DLY Register Mask */ +#define SPI_DLY_PRE_DELAY(n) (((n) & 0x0F) << 0) /** Time in SPI clocks between SSEL assertion and the beginning of a data frame */ +#define SPI_DLY_POST_DELAY(n) (((n) & 0x0F) << 4) /** Time in SPI clocks between the end of a data frame and SSEL deassertion. */ +#define SPI_DLY_FRAME_DELAY(n) (((n) & 0x0F) << 8) /** Minimum time in SPI clocks between adjacent data frames. */ +#define SPI_DLY_TRANSFER_DELAY(n) (((n) & 0x0F) << 12) /** Minimum time in SPI clocks that the SSEL is deasserted between transfers. */ + +/** + * Macro defines for SPI Status register + */ +#define SPI_STAT_BITMASK (0x1FF) /** SPI STAT Register BitMask */ +#define SPI_STAT_RXRDY (1 << 0) /** Receiver Ready Flag */ +#define SPI_STAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ +#define SPI_STAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ +#define SPI_STAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ +#define SPI_STAT_SSA (1 << 4) /** Slave Select Assert */ +#define SPI_STAT_SSD (1 << 5) /** Slave Select Deassert */ +#define SPI_STAT_STALLED (1 << 6) /** Stalled status flag */ +#define SPI_STAT_EOT (1 << 7) /** End Transfer flag */ +#define SPI_STAT_MSTIDLE (1 << 8) /** Idle status flag */ + +/** + * Macro defines for SPI Interrupt Enable read and Set register + */ +#define SPI_INTENSET_BITMASK (0x3F) /** SPI INTENSET Register BitMask */ +#define SPI_INTENSET_RXDYEN (1 << 0) /** Enable Interrupt when receiver data is available */ +#define SPI_INTENSET_TXDYEN (1 << 1) /** Enable Interrupt when the transmitter holding register is available. */ +#define SPI_INTENSET_RXOVEN (1 << 2) /** Enable Interrupt when a receiver overrun occurs */ +#define SPI_INTENSET_TXUREN (1 << 3) /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/ +#define SPI_INTENSET_SSAEN (1 << 4) /** Enable Interrupt when the Slave Select is asserted.*/ +#define SPI_INTENSET_SSDEN (1 << 5) /** Enable Interrupt when the Slave Select is deasserted..*/ + +/** + * Macro defines for SPI Interrupt Enable Clear register + */ +#define SPI_INTENCLR_BITMASK (0x3F) /** SPI INTENCLR Register BitMask */ +#define SPI_INTENCLR_RXDYEN (1 << 0) /** Disable Interrupt when receiver data is available */ +#define SPI_INTENCLR_TXDYEN (1 << 1) /** Disable Interrupt when the transmitter holding register is available. */ +#define SPI_INTENCLR_RXOVEN (1 << 2) /** Disable Interrupt when a receiver overrun occurs */ +#define SPI_INTENCLR_TXUREN (1 << 3) /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only) */ +#define SPI_INTENCLR_SSAEN (1 << 4) /** Disable Interrupt when the Slave Select is asserted. */ +#define SPI_INTENCLR_SSDEN (1 << 5) /** Disable Interrupt when the Slave Select is deasserted.. */ + +/** + * Macro defines for SPI Receiver Data register + */ +#define SPI_RXDAT_BITMASK (0x1FFFFF) /** SPI RXDAT Register BitMask */ +#define SPI_RXDAT_DATA(n) ((n) & 0xFFFF) /** Receiver Data */ +#define SPI_RXDAT_RXSSELN_ACTIVE (0 << 16) /** The state of SSEL pin is active */ +#define SPI_RXDAT_RXSSELN_INACTIVE ((1 << 16) /** The state of SSEL pin is inactive */ +#define SPI_RXDAT_RXSSELNUM_INACTIVE(n) (1 << ((n) + 16)) /** The state of SSELN pin is inactive */ +#define SPI_RXDAT_SOT (1 << 20) /** Start of Transfer flag */ + +/** + * Macro defines for SPI Transmitter Data and Control register + */ +#define SPI_TXDATCTL_BITMASK (0xF7FFFFF) /** SPI TXDATCTL Register BitMask */ +#define SPI_TXDATCTL_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ +#define SPI_TXDATCTL_CTRLMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask for control bits only */ +#define SPI_TXDATCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ +#define SPI_TXDATCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ +#define SPI_TXDATCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ +#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ +#define SPI_TXDATCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ +#define SPI_TXDATCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ +#define SPI_TXDATCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ +#define SPI_TXDATCTL_FLEN(n) (((n) & 0x0F) << 24) /** Frame length - 1 */ + +/** + * Macro defines for SPI Transmitter Data Register + */ +#define SPI_TXDAT_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ + +/** + * Macro defines for SPI Transmitter Control register + */ +#define SPI_TXCTL_BITMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask */ +#define SPI_TXCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ +#define SPI_TXCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ +#define SPI_TXCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ +#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ +#define SPI_TXCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ +#define SPI_TXCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ +#define SPI_TXCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ +#define SPI_TXCTL_FLEN(n) ((((n) - 1) & 0x0F) << 24) /** Frame length, 0 - 16 */ +#define SPI_TXCTL_FLENMASK (0xF << 24) /** Frame length mask */ + +/** + * Macro defines for SPI Divider register + */ +#define SPI_DIV_VAL(n) ((n) & 0xFFFF) /** Rate divider value mask (In Master Mode only)*/ + +/** + * Macro defines for SPI Interrupt Status register + */ +#define SPI_INTSTAT_BITMASK (0x3F) /** SPI INTSTAT Register Bitmask */ +#define SPI_INTSTAT_RXRDY (1 << 0) /** Receiver Ready Flag */ +#define SPI_INTSTAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ +#define SPI_INTSTAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ +#define SPI_INTSTAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ +#define SPI_INTSTAT_SSA (1 << 4) /** Slave Select Assert */ +#define SPI_INTSTAT_SSD (1 << 5) /** Slave Select Deassert */ + +/** @brief SPI Clock Mode*/ +typedef enum { + ROM_SPI_CLOCK_CPHA0_CPOL0 = 0, /**< CPHA = 0, CPOL = 0 */ + ROM_SPI_CLOCK_MODE0 = ROM_SPI_CLOCK_CPHA0_CPOL0, /**< Alias for CPHA = 0, CPOL = 0 */ + ROM_SPI_CLOCK_CPHA1_CPOL0 = 1, /**< CPHA = 0, CPOL = 1 */ + ROM_SPI_CLOCK_MODE1 = ROM_SPI_CLOCK_CPHA1_CPOL0, /**< Alias for CPHA = 0, CPOL = 1 */ + ROM_SPI_CLOCK_CPHA0_CPOL1 = 2, /**< CPHA = 1, CPOL = 0 */ + ROM_SPI_CLOCK_MODE2 = ROM_SPI_CLOCK_CPHA0_CPOL1, /**< Alias for CPHA = 1, CPOL = 0 */ + ROM_SPI_CLOCK_CPHA1_CPOL1 = 3, /**< CPHA = 1, CPOL = 1 */ + ROM_SPI_CLOCK_MODE3 = ROM_SPI_CLOCK_CPHA1_CPOL1, /**< Alias for CPHA = 1, CPOL = 1 */ +} ROM_SPI_CLOCK_MODE_T; + +/** + * Macro defines for SPI Configuration register + */ +#define SPI_CFG_BITMASK (0xFBD) /** SPI register bit mask */ +#define SPI_CFG_SPI_EN (1 << 0) /** SPI Slave Mode Select */ +#define SPI_CFG_SLAVE_EN (0 << 0) /** SPI Master Mode Select */ +#define SPI_CFG_MASTER_EN (1 << 2) /** SPI MSB First mode enable */ +#define SPI_CFG_MSB_FIRST_EN (0 << 3) /** SPI LSB First mode enable */ +#define SPI_CFG_LSB_FIRST_EN (1 << 3) /** SPI Clock Phase Select */ +#define SPI_CFG_CPHA_FIRST (0 << 4) /** Capture data on the first edge, Change data on the following edge */ +#define SPI_CFG_CPHA_SECOND (1 << 4) /** SPI Clock Polarity Select */ +#define SPI_CFG_CPOL_LO (0 << 5) /** The rest state of the clock (between frames) is low. */ +#define SPI_CFG_CPOL_HI (1 << 5) /** The rest state of the clock (between frames) is high. */ +#define SPI_CFG_LBM_EN (1 << 7) /** SPI control 1 loopback mode enable */ +#define SPI_CFG_SPOL_LO (0 << 8) /** SPI SSEL0 Polarity Select */ +#define SPI_CFG_SPOL_HI (1 << 8) /** SSEL0 is active High */ +#define SPI_CFG_SPOLNUM_HI(n) (1 << ((n) + 8)) /** SSELN is active High, selects 0 - 3 */ + +/** + * Macro defines for SPI Delay register + */ +#define SPI_DLY_BITMASK (0xFFFF) /** SPI DLY Register Mask */ +#define SPI_DLY_PRE_DELAY(n) (((n) & 0x0F) << 0) /** Time in SPI clocks between SSEL assertion and the beginning of a data frame */ +#define SPI_DLY_POST_DELAY(n) (((n) & 0x0F) << 4) /** Time in SPI clocks between the end of a data frame and SSEL deassertion. */ +#define SPI_DLY_FRAME_DELAY(n) (((n) & 0x0F) << 8) /** Minimum time in SPI clocks between adjacent data frames. */ +#define SPI_DLY_TRANSFER_DELAY(n) (((n) & 0x0F) << 12) /** Minimum time in SPI clocks that the SSEL is deasserted between transfers. */ + +/** + * Macro defines for SPI Status register + */ +#define SPI_STAT_BITMASK (0x1FF) /** SPI STAT Register BitMask */ +#define SPI_STAT_RXRDY (1 << 0) /** Receiver Ready Flag */ +#define SPI_STAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ +#define SPI_STAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ +#define SPI_STAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ +#define SPI_STAT_SSA (1 << 4) /** Slave Select Assert */ +#define SPI_STAT_SSD (1 << 5) /** Slave Select Deassert */ +#define SPI_STAT_STALLED (1 << 6) /** Stalled status flag */ +#define SPI_STAT_EOT (1 << 7) /** End Transfer flag */ +#define SPI_STAT_MSTIDLE (1 << 8) /** Idle status flag */ + +/** + * Macro defines for SPI Interrupt Enable read and Set register + */ +#define SPI_INTENSET_BITMASK (0x3F) /** SPI INTENSET Register BitMask */ +#define SPI_INTENSET_RXDYEN (1 << 0) /** Enable Interrupt when receiver data is available */ +#define SPI_INTENSET_TXDYEN (1 << 1) /** Enable Interrupt when the transmitter holding register is available. */ +#define SPI_INTENSET_RXOVEN (1 << 2) /** Enable Interrupt when a receiver overrun occurs */ +#define SPI_INTENSET_TXUREN (1 << 3) /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/ +#define SPI_INTENSET_SSAEN (1 << 4) /** Enable Interrupt when the Slave Select is asserted.*/ +#define SPI_INTENSET_SSDEN (1 << 5) /** Enable Interrupt when the Slave Select is deasserted..*/ + +/** + * Macro defines for SPI Interrupt Enable Clear register + */ +#define SPI_INTENCLR_BITMASK (0x3F) /** SPI INTENCLR Register BitMask */ +#define SPI_INTENCLR_RXDYEN (1 << 0) /** Disable Interrupt when receiver data is available */ +#define SPI_INTENCLR_TXDYEN (1 << 1) /** Disable Interrupt when the transmitter holding register is available. */ +#define SPI_INTENCLR_RXOVEN (1 << 2) /** Disable Interrupt when a receiver overrun occurs */ +#define SPI_INTENCLR_TXUREN (1 << 3) /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only) */ +#define SPI_INTENCLR_SSAEN (1 << 4) /** Disable Interrupt when the Slave Select is asserted. */ +#define SPI_INTENCLR_SSDEN (1 << 5) /** Disable Interrupt when the Slave Select is deasserted.. */ + +/** + * Macro defines for SPI Receiver Data register + */ +#define SPI_RXDAT_BITMASK (0x1FFFFF) /** SPI RXDAT Register BitMask */ +#define SPI_RXDAT_DATA(n) ((n) & 0xFFFF) /** Receiver Data */ +#define SPI_RXDAT_RXSSELN_ACTIVE (0 << 16) /** The state of SSEL pin is active */ +#define SPI_RXDAT_RXSSELN_INACTIVE ((1 << 16) /** The state of SSEL pin is inactive */ +#define SPI_RXDAT_RXSSELNUM_INACTIVE(n) (1 << ((n) + 16)) /** The state of SSELN pin is inactive */ +#define SPI_RXDAT_SOT (1 << 20) /** Start of Transfer flag */ + +/** + * Macro defines for SPI Transmitter Data and Control register + */ +#define SPI_TXDATCTL_BITMASK (0xF7FFFFF) /** SPI TXDATCTL Register BitMask */ +#define SPI_TXDATCTL_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ +#define SPI_TXDATCTL_CTRLMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask for control bits only */ +#define SPI_TXDATCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ +#define SPI_TXDATCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ +#define SPI_TXDATCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ +#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ +#define SPI_TXDATCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ +#define SPI_TXDATCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ +#define SPI_TXDATCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ +#define SPI_TXDATCTL_FLEN(n) (((n) & 0x0F) << 24) /** Frame length - 1 */ + +/** + * Macro defines for SPI Transmitter Data Register + */ +#define SPI_TXDAT_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ + +/** + * Macro defines for SPI Transmitter Control register + */ +#define SPI_TXCTL_BITMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask */ +#define SPI_TXCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ +#define SPI_TXCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ +#define SPI_TXCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ +#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ +#define SPI_TXCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ +#define SPI_TXCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ +#define SPI_TXCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ +#define SPI_TXCTL_FLEN(n) ((((n) - 1) & 0x0F) << 24) /** Frame length, 0 - 16 */ +#define SPI_TXCTL_FLENMASK (0xF << 24) /** Frame length mask */ + +/** + * Macro defines for SPI Divider register + */ +#define SPI_DIV_VAL(n) ((n) & 0xFFFF) /** Rate divider value mask (In Master Mode only)*/ + +/** + * Macro defines for SPI Interrupt Status register + */ +#define SPI_INTSTAT_BITMASK (0x3F) /** SPI INTSTAT Register Bitmask */ +#define SPI_INTSTAT_RXRDY (1 << 0) /** Receiver Ready Flag */ +#define SPI_INTSTAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ +#define SPI_INTSTAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ +#define SPI_INTSTAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ +#define SPI_INTSTAT_SSA (1 << 4) /** Slave Select Assert */ +#define SPI_INTSTAT_SSD (1 << 5) /** Slave Select Deassert */ + +/** + * @brief Set SPI CFG register values + * @param pSPI : The base of SPI peripheral on the chip + * @param bits : CFG register bits to set, amd OR'ed value of SPI_CFG_* definitions + * @return Nothing + * @note This function safely sets only the selected bits in the SPI CFG register. + * It can be used to enable multiple bits at once. + */ +__STATIC_INLINE void Chip_SPI_SetCFGRegBits(LPC_SPI_T *pSPI, uint32_t bits) +{ + /* Mask off bits that are write as 0, read as undefined */ + pSPI->CFG = (pSPI->CFG | bits) & SPI_CFG_BITMASK; +} + +/** + * @brief Clear SPI CFG register values + * @param pSPI : The base of SPI peripheral on the chip + * @param bits : CFG register bits to clear, amd OR'ed value of SPI_CFG_* definitions + * @return Nothing + * @note This function safely clears only the selected bits in the SPI CFG register. + * It can be used to disable multiple bits at once. + */ +__STATIC_INLINE void Chip_SPI_ClearCFGRegBits(LPC_SPI_T *pSPI, uint32_t bits) +{ + /* Mask off bits that are write as 0, read as undefined */ + pSPI->CFG = pSPI->CFG & (SPI_CFG_BITMASK & ~bits); +} + +/** + * @brief Enable SPI peripheral + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_Enable(LPC_SPI_T *pSPI) +{ + Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_SPI_EN); +} + +/** + * @brief Disable SPI peripheral + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_Disable(LPC_SPI_T *pSPI) +{ + Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_SPI_EN); +} + +/** + * @brief Initialize the SPI + * @param pSPI : The base SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_Init(LPC_SPI_T *pSPI) +{ + if (pSPI == LPC_SPI1) { + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SPI1); + Chip_SYSCON_PeriphReset(RESET_SPI1); + } + else { + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SPI0); + Chip_SYSCON_PeriphReset(RESET_SPI0); + } +} + +/** + * @brief Disable SPI operation + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note The SPI controller is disabled. + */ +__STATIC_INLINE void Chip_SPI_DeInit(LPC_SPI_T *pSPI) +{ + Chip_SPI_Disable(pSPI); + if (pSPI == LPC_SPI1) { + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_SPI1); + } + else { + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_SPI0); + } +} + +/** + * @brief Enable SPI master mode + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note SPI slave mode will be disabled with this call. All SPI SSEL + * lines will also be deasserted. + */ +__STATIC_INLINE void Chip_SPI_EnableMasterMode(LPC_SPI_T *pSPI) +{ + Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_MASTER_EN); + + /* Deassert all chip selects, only in master mode */ + pSPI->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; +} + +/** + * @brief Enable SPI slave mode + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note SPI master mode will be disabled with this call. + */ +__STATIC_INLINE void Chip_SPI_EnableSlaveMode(LPC_SPI_T *pSPI) +{ + Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_MASTER_EN); +} + +/** + * @brief Enable LSB First transfers + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_EnableLSBFirst(LPC_SPI_T *pSPI) +{ + Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_LSB_FIRST_EN); +} + +/** + * @brief Enable MSB First transfers + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_EnableMSBFirst(LPC_SPI_T *pSPI) +{ + Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_LSB_FIRST_EN); +} + +/** @brief SPI Clock Mode*/ +typedef enum IP_SPI_CLOCK_MODE { + SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */ + SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /**< Alias for CPHA = 0, CPOL = 0 */ + SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND, /**< CPHA = 0, CPOL = 1 */ + SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /**< Alias for CPHA = 0, CPOL = 1 */ + SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST, /**< CPHA = 1, CPOL = 0 */ + SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /**< Alias for CPHA = 1, CPOL = 0 */ + SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */ + SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /**< Alias for CPHA = 1, CPOL = 1 */ +} SPI_CLOCK_MODE_T; + +/** + * @brief Set SPI mode + * @param pSPI : The base of SPI peripheral on the chip + * @param mode : SPI mode to set the SPI interface to + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_SetSPIMode(LPC_SPI_T *pSPI, SPI_CLOCK_MODE_T mode) +{ + Chip_SPI_ClearCFGRegBits(pSPI, (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND)); + Chip_SPI_SetCFGRegBits(pSPI, (uint32_t) mode); +} + +/** + * @brief Set polarity on the SPI chip select high + * @param pSPI : The base of SPI peripheral on the chip + * @param csNum : Chip select number, 0 - 3 + * @return Nothing + * @note SPI chip select polarity is active high. + */ +__STATIC_INLINE void Chip_SPI_SetCSPolHigh(LPC_SPI_T *pSPI, uint8_t csNum) +{ + Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_SPOLNUM_HI(csNum)); +} + +/** + * @brief Set polarity on the SPI chip select low + * @param pSPI : The base of SPI peripheral on the chip + * @param csNum : Chip select number, 0 - 3 + * @return Nothing + * @note SPI chip select polarity is active low. + */ +__STATIC_INLINE void Chip_SPI_SetCSPolLow(LPC_SPI_T *pSPI, uint8_t csNum) +{ + Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_SPOLNUM_HI(csNum)); +} + +/** SPI configuration structure used for setting up master/slave mode, LSB or + * MSB first, and SPI mode in a single function call. */ +typedef struct { + uint32_t master : 8; /* Set to non-0 value to use master mode, 0 for slave */ + uint32_t lsbFirst : 8; /* Set to non-0 value to send LSB first, 0 for MSB first */ + SPI_CLOCK_MODE_T mode : 8; /* Mode selection */ + uint32_t reserved : 8; /* Reserved, for alignment only */ +} SPI_CFGSETUP_T; + +/** + * @brief Setup SPI configuration + * @param pSPI : The base of SPI peripheral on the chip + * @param pCFG : Pointer to SPI configuration structure + * @return Nothing + */ +void Chip_SPI_ConfigureSPI(LPC_SPI_T *pSPI, SPI_CFGSETUP_T *pCFG); + +/** + * @brief Get the current status of SPI controller + * @param pSPI : The base of SPI peripheral on the chip + * @return SPI Status (Or-ed bit value of SPI_STAT_*) + * @note Mask the return value with a value of type SPI_STAT_* to determine + * if that status is active. + */ +__STATIC_INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI) +{ + return pSPI->STAT; +} + +/** + * @brief Clear SPI status + * @param pSPI : The base of SPI peripheral on the chip + * @param Flag : Clear Flag (Or-ed bit value of SPI_STAT_*) + * @return Nothing + * @note Only SPI_STAT_RXOV, SPI_STAT_TXUR, SPI_STAT_SSA, and + * SPI_STAT_SSD statuses can be cleared. + */ +__STATIC_INLINE void Chip_SPI_ClearStatus(LPC_SPI_T *pSPI, uint32_t Flag) +{ + pSPI->STAT = Flag; +} + +/** + * @brief Enable a SPI interrupt + * @param pSPI : The base of SPI peripheral on the chip + * @param intMask : Or'ed value of SPI_INTENSET_* values to enable + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_EnableInts(LPC_SPI_T *pSPI, uint32_t intMask) +{ + pSPI->INTENSET = intMask; +} + +/** + * @brief Disable a SPI interrupt + * @param pSPI : The base of SPI peripheral on the chip + * @param intMask : Or'ed value of SPI_INTENCLR_* values to disable + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_DisableInts(LPC_SPI_T *pSPI, uint32_t intMask) +{ + pSPI->INTENCLR = intMask; +} + +/** + * @brief Return enabled SPI interrupts + * @param pSPI : The base of SPI peripheral on the chip + * @return An Or'ed value of SPI_INTENSET_* values + * @note Mask the return value with a SPI_INTENSET_* value to determine + * if the interrupt is enabled. + */ +__STATIC_INLINE uint32_t Chip_SPI_GetEnabledInts(LPC_SPI_T *pSPI) +{ + return pSPI->INTENSET; +} + +/** + * @brief Return pending SPI interrupts + * @param pSPI : The base of SPI peripheral on the chip + * @return An Or'ed value of SPI_INTSTAT_* values + * @note Mask the return value with a SPI_INTSTAT_* value to determine + * if the interrupt is pending. + */ +__STATIC_INLINE uint32_t Chip_SPI_GetPendingInts(LPC_SPI_T *pSPI) +{ + return pSPI->INTSTAT; +} + +/** + * @brief Flush FIFOs + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_FlushFifos(LPC_SPI_T *pSPI) +{ + Chip_SPI_Disable(pSPI); + Chip_SPI_Enable(pSPI); +} + +/** + * @brief Read raw data from receive FIFO with status bits + * @param pSPI : The base of SPI peripheral on the chip + * @return Current value in receive data FIFO plus status bits + */ +__STATIC_INLINE uint32_t Chip_SPI_ReadRawRXFifo(LPC_SPI_T *pSPI) +{ + return pSPI->RXDAT; +} + +/** + * @brief Read data from receive FIFO masking off status bits + * @param pSPI : The base of SPI peripheral on the chip + * @return Current value in receive data FIFO + * @note The return value is masked with 0xFFFF to not exceed 16-bits. All + * other status bits are thrown away. This register should only be read if it + * has data in it. This function is useful for systems that don't need SPI + * select (SSEL) monitoring. + */ +__STATIC_INLINE uint32_t Chip_SPI_ReadRXData(LPC_SPI_T *pSPI) +{ + return pSPI->RXDAT & 0xFFFF; +} + +/** + * @brief Write data to transmit FIFO + * @param pSPI : The base of SPI peripheral on the chip + * @param data : Data to write + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_WriteTXData(LPC_SPI_T *pSPI, uint16_t data) +{ + pSPI->TXDAT = (uint32_t) data; +} + +/** + * @brief Set SPI TXCTRL register control options + * @param pSPI : The base of SPI peripheral on the chip + * @param bits : TXCTRL register bits to set, amd OR'ed value of SPI_TXDATCTL_* definitions + * @return Nothing + * @note This function safely sets only the selected bits in the SPI TXCTRL register. + * It can be used to enable multiple bits at once. + */ +__STATIC_INLINE void Chip_SPI_SetTXCTRLRegBits(LPC_SPI_T *pSPI, uint32_t bits) +{ + pSPI->TXCTRL = (pSPI->TXCTRL | bits) & SPI_TXDATCTL_CTRLMASK; +} + +/** + * @brief Clear SPI TXCTRL register control options + * @param pSPI : The base of SPI peripheral on the chip + * @param bits : TXCTRL register bits to clear, amd OR'ed value of SPI_TXDATCTL_* definitions + * @return Nothing + * @note This function safely clears only the selected bits in the SPI TXCTRL register. + * It can be used to disable multiple bits at once. + */ +__STATIC_INLINE void Chip_SPI_ClearTXCTRLRegBits(LPC_SPI_T *pSPI, uint32_t bits) +{ + pSPI->TXCTRL = pSPI->TXCTRL & (SPI_TXDATCTL_CTRLMASK & ~bits); +} + +/** + * @brief Set TX control options (safe) + * @param pSPI : The base of SPI peripheral on the chip + * @param ctrlBits : Or'ed control bits to set + * @return Nothing + * @note Selectable control states include SPI_TXCTL_DEASSERTNUM_SSEL(0/1/2/3), + * SPI_TXCTL_EOT, SPI_TXCTL_EOF, SPI_TXCTL_RXIGNORE, and SPI_TXCTL_FLEN(bits). + */ +__STATIC_INLINE void Chip_SPI_SetTXCtl(LPC_SPI_T *pSPI, uint32_t ctrlBits) +{ + Chip_SPI_SetTXCTRLRegBits(pSPI, ctrlBits); +} + +/** + * @brief Clear TX control options (safe) + * @param pSPI : The base of SPI peripheral on the chip + * @param ctrlBits : Or'ed control bits to clear + * @return Nothing + * @note Selectable control states include SPI_TXCTL_DEASSERTNUM_SSEL(0/1/2/3), + * SPI_TXCTL_EOT, SPI_TXCTL_EOF, SPI_TXCTL_RXIGNORE, and SPI_TXCTL_FLEN(bits). + */ +__STATIC_INLINE void Chip_SPI_ClearTXCtl(LPC_SPI_T *pSPI, uint32_t ctrlBits) +{ + Chip_SPI_ClearTXCTRLRegBits(pSPI, ctrlBits); +} + +/** + * @brief Set TX data transfer size in bits + * @param pSPI : The base of SPI peripheral on the chip + * @param ctrlBits : Number of bits to transmit and receive, must be 1 to 16 + * @return Nothing + */ +__STATIC_INLINE void Chip_SPI_SetXferSize(LPC_SPI_T *pSPI, uint32_t ctrlBits) +{ + Chip_SPI_ClearTXCTRLRegBits(pSPI, SPI_TXCTL_FLENMASK); + Chip_SPI_SetTXCTRLRegBits(pSPI, SPI_TXCTL_FLEN(ctrlBits)); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_COMMON_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/spim_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/spim_5410x.h new file mode 100644 index 0000000000000..470a48f9471ae --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/spim_5410x.h @@ -0,0 +1,250 @@ +/* + * @brief LPC5410X SPI master driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPIM_5410X_H_ +#define __SPIM_5410X_H_ + +#include "spi_common_5410x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SPI_MASTER_5410X CHIP: LPC5410X SPI master driver + * @ingroup SPI_COMMON_5410X + * @{ + */ + +/** + * @brief Get SPI master bit rate + * @param pSPI : The base of SPI peripheral on the chip + * @return The actual SPI clock bit rate + */ +uint32_t Chip_SPIM_GetClockRate(LPC_SPI_T *pSPI); + +/** + * @brief Set SPI master bit rate + * @param pSPI : The base of SPI peripheral on the chip + * @param rate : Desired clock bit rate for the SPI interface + * @return The actual SPI clock bit rate + * @note This function will set the SPI clock divider to get closest + * to the desired rate as possible. + */ +uint32_t Chip_SPIM_SetClockRate(LPC_SPI_T *pSPI, uint32_t rate); + +/** + * @brief SPI Delay Configure Struct + */ +typedef struct { + uint8_t PreDelay; /** Pre-delay value in SPI clocks, 0 - 15 */ + uint8_t PostDelay; /** Post-delay value in SPI clocks, 0 - 15 */ + uint8_t FrameDelay; /** Delay value between frames of a transfer in SPI clocks, 0 - 15 */ + uint8_t TransferDelay; /** Delay value between transfers in SPI clocks, 1 - 16 */ +} SPIM_DELAY_CONFIG_T; + +/** + * @brief Config SPI Delay parameters + * @param pSPI : The base of SPI peripheral on the chip + * @param pConfig : SPI Delay Configure Struct + * @return Nothing + */ +__STATIC_INLINE void Chip_SPIM_DelayConfig(LPC_SPI_T *pSPI, SPIM_DELAY_CONFIG_T *pConfig) +{ + pSPI->DLY = (SPI_DLY_PRE_DELAY(pConfig->PreDelay) | + SPI_DLY_POST_DELAY(pConfig->PostDelay) | + SPI_DLY_FRAME_DELAY(pConfig->FrameDelay) | + SPI_DLY_TRANSFER_DELAY(pConfig->TransferDelay - 1)); +} + +/** + * @brief Forces an end of transfer for the current master transfer + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note Use this function to perform an immediate end of trasnfer for the + * current master operation. If the master is currently transferring data started + * with the Chip_SPIM_Xfer function, this terminates the transfer after the + * current byte completes and completes the transfer. + */ +__STATIC_INLINE void Chip_SPIM_ForceEndOfTransfer(LPC_SPI_T *pSPI) +{ + pSPI->STAT = SPI_STAT_EOT; +} + +/** + * @brief Assert a SPI select + * @param pSPI : The base of SPI peripheral on the chip + * @param sselNum : SPI select to assert, 0 - 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_SPIM_AssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum) +{ + pSPI->TXCTRL = pSPI->TXCTRL & (SPI_TXDATCTL_CTRLMASK & ~SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum)); +} + +/** + * @brief Deassert a SPI select + * @param pSPI : The base of SPI peripheral on the chip + * @param sselNum : SPI select to deassert, 0 - 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_SPIM_DeAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum) +{ + pSPI->TXCTRL = (pSPI->TXCTRL | SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum)) & SPI_TXDATCTL_CTRLMASK; +} + +/** + * @brief Enable loopback mode + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + * @note Serial input is taken from the serial output (MOSI or MISO) rather + * than the serial input pin. + */ +__STATIC_INLINE void Chip_SPIM_EnableLoopBack(LPC_SPI_T *pSPI) +{ + Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_LBM_EN); +} + +/** + * @brief Disable loopback mode + * @param pSPI : The base of SPI peripheral on the chip + * @return Nothing + */ +__STATIC_INLINE void Chip_SPIM_DisableLoopBack(LPC_SPI_T *pSPI) +{ + Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_LBM_EN); +} + +/** + * @brief Event handler ID passed during a call-back event + */ +typedef enum { + SPIM_EVT_SSELASSERT, /**< Event identifier for Slave Assert */ + SPIM_EVT_SSELDEASSERT, /**< Event identifier for Slave deassert */ + SPIM_EVT_TXDONE, /**< Event identifier for TX complete */ + SPIM_EVT_RXDONE, /**< Event identifier for RX complete */ +} SPIM_EVENT_T; + +/** @brief SPI Master XFER states */ +#define SPIM_XFER_STATE_IDLE 0 /**< SPI XFER is IDLE */ +#define SPIM_XFER_STATE_BUSY 1 /**< SPI XFER is busy transfering data */ +#define SPIM_XFER_STATE_DONE 2 /**< SPI XFER is complete */ + +/** @brief SPI master xfer options */ +#define SPIM_XFER_OPTION_EOT (1 << 4) /**< SPI SLAVE Select will be deasserted when xfer is done */ +#define SPIM_XFER_OPTION_EOF (1 << 5) /**< Insert a frame delay */ +#define SPIM_XFER_OPTION_SIZE(x) ((((x) - 1) & 0xF) << 8) /**< Number of bits in transfer data */ + +/** Slave transfer data context */ +typedef struct SPIM_XFER { + int (*cbFunc)(SPIM_EVENT_T event, struct SPIM_XFER *xfer); /**< Callback function for event handling; NULL when no call-back required + @a event will be one of #SPIS_EVENT_T and @a xfer is pointer to xfer structure */ + + void *txBuff; /**< TX buffer pointer; Must be a uint16_t pointer when transfer + size is 16 bits and uint8_t pointer when transfer size is 8 bits (can be NULL only when *txCount is 0) */ + void *rxBuff; /**< RX buffer pointer; Must be uint16_t pointer when transfer size is 16 bits or + must be uint8_t pointer when transfer is 8-bits (can be NULL only when *txCount is 0) */ + int32_t txCount; /**< Pointer to an int32_t memory (never initialize to NULL) that has the Size of the txBuff in items (not bytes), not modified by driver */ + int32_t rxCount; /**< Number of items (not bytes) to send in rxBuff buffer (Never initialize to NULL), not modified by driver */ + int32_t txDoneCount; /**< Total items (not bytes) transmitted (initialize to 0), modified by driver [In case of underflow txDoneCount will be greater than *txCount] */ + int32_t rxDoneCount; /**< Total items (not bytes) received (initialize to 0), modified by driver [In case of over flow rxDoneCount will be greater than *rxCount] */ + uint8_t sselNum; /**< Slave number assigned to this transfer, 0 - 3, modified by driver */ + uint8_t state; /**< Initialize to #SPIS_XFER_STATE_IDLE; driver sets to #SPIS_XFER_STATE_BUSY or #SPIS_XFER_STATE_DONE */ + uint16_t options; /**< SPI Transfer options (or'd values of #SPIM_XFER_OPTION_EOT, #SPIM_XFER_OPTION_EOF, #SPIM_XFER_OPTION_SIZE) */ +} SPIM_XFER_T; + +/** + * @brief SPI master transfer state change handler + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIM_XFER_T structure see notes below + * @return Nothing + * @note See @ref SPIM_XFER_T for more information on this function. When using + * this function, the SPI master interrupts should be enabled and setup in the SPI + * interrupt handler to call this function when they fire. This function is meant + * to be called from the interrupt handler. + */ +void Chip_SPIM_XferHandler(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); + +/** + * @brief Start non-blocking SPI master transfer + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIM_XFER_T structure see notes below + * @return Nothing + * @note This function starts a non-blocking SPI master transfer with the + * parameters setup in the passed @ref SPIM_XFER_T structure. Once the transfer is + * started, the interrupt handler must call Chip_SPIM_XferHandler to keep the + * transfer going and fed with data. This function should only be called when + * the master is idle.
+ * + * This function must be called with the options and sselNum fields correctly + * setup. Initial data buffers and the callback pointer must also be setup. No + * sanity checks are performed on the passed data.
+ * + * Example call:
+ * SPIM_XFER_T mxfer; + * mxfer.pCB = (&)masterCallbacks; + * mxfer.sselNum = 2; // Use chip select 2 + * mxfer.options = SPI_TXCTL_FLEN(8); // 8 data bits, supports 1 - 16 bits + * mxfer.options |= SPI_TXCTL_EOT | SPI_TXCTL_EOF; // Apply frame and transfer delays to master transfer + * mxfer.options |= SPI_TXCTL_RXIGNORE; // Ignore RX data, will toss receive data regardless of pRXData8 or pRXData16 buffer + * mxfer.pTXData8 = SendBuffer; + * mxfer.txCount = 16; // Number of bytes to send before SPIMasterXferSend callback is called + * mxfer.pRXData8 = RecvBuffer; // Will not receive data if pRXData8/pRXData16 is NULL or SPI_TXCTL_RXIGNORE option is set + * mxfer.rxCount = 16; // Number of bytes to receive before SPIMasterXferRecv callback is called + * Chip_SPIM_Xfer(LPC_SPI0, &mxfer); // Start transfer + * + * Note that the transfer, once started, needs to be constantly fed by the callbacks. + * The txCount and rxCount field only indicate the buffer size before the callbacks are called. + * To terminate the transfer, the SPIMasterXferSend callback must set the terminate field. + */ +void Chip_SPIM_Xfer(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); + +/** + * @brief Perform blocking SPI master transfer + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIM_XFER_T structure see notes below + * @return Nothing + * @note This function starts a blocking SPI master transfer with the + * parameters setup in the passed @ref SPIM_XFER_T structure. Once the transfer is + * started, the callbacks in Chip_SPIM_XferHandler may be called to keep the + * transfer going and fed with data. SPI interrupts must be disabled prior to + * calling this function. It is not recommended to use this function.
+ */ +void Chip_SPIM_XferBlocking(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIM_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/spis_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/spis_5410x.h new file mode 100644 index 0000000000000..07dcf292a14a5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/spis_5410x.h @@ -0,0 +1,133 @@ +/* + * @brief LPC5410X SPI slave driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPIS_5410X_H_ +#define __SPIS_5410X_H_ + +#include "spi_common_5410x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SPI_SLAVE_5410X CHIP: LPC5410X SPI slave driver + * @ingroup SPI_COMMON_5410X + * @{ + */ + +/** + * @brief Event handler ID passed during a call-back event + */ +typedef enum { + SPIS_EVT_SSELASSERT, /**< Event identifier for Slave Assert */ + SPIS_EVT_SSELDEASSERT, /**< Event identifier for Slave deassert */ + SPIS_EVT_TXDONE, /**< Event identifier for TX complete */ + SPIS_EVT_RXDONE, /**< Event identifier for RX complete */ +} SPIS_EVENT_T; + +/** @brief SPI XFER states */ +#define SPIS_XFER_STATE_IDLE 0 /**< SPI XFER is IDLE */ +#define SPIS_XFER_STATE_BUSY 1 /**< SPI XFER is busy transfering data */ +#define SPIS_XFER_STATE_DONE 2 /**< SPI XFER is complete */ + +/** Slave transfer data context */ +typedef struct SPIS_XFER { + int (*cbFunc)(SPIS_EVENT_T event, struct SPIS_XFER *xfer); /**< Callback function for event handling; NULL when no call-back required + @a event will be one of #SPIS_EVENT_T and @a xfer is pointer to xfer structure [Return value ignored] */ + + void *txBuff; /**< TX buffer pointer; Must be a uint16_t pointer when transfer + size is 16 bits and uint8_t pointer when transfer size is 8 bits */ + void *rxBuff; /**< RX buffer pointer; Must be uint16_t pointer when transfer size is 16 bits or + must be uint8_t pointer when transfer is 8-bits */ + int32_t txCount; /**< Pointer to an int32_t memory (never initialize to NULL) that has the Size of the txBuff in items (not bytes), not modified by driver */ + int32_t rxCount; /**< Number of items (not bytes) to send in rxBuff buffer (Never initialize to NULL), not modified by driver */ + int32_t txDoneCount; /**< Total items (not bytes) transmitted (initialize to 0), modified by driver [In case of underflow txDoneCount will be greater than *txCount] */ + int32_t rxDoneCount; /**< Total items (not bytes) received (initialize to 0), modified by driver [In case of over flow rxDoneCount will be greater than *rxCount] */ + uint8_t sselNum; /**< Slave number assigned to this transfer, 0 - 3, modified by driver */ + uint8_t state; /**< Initialize to #SPIS_XFER_STATE_IDLE; driver sets to #SPIS_XFER_STATE_BUSY or #SPIS_XFER_STATE_DONE */ + uint16_t reserved0; /**< Reserved field */ +} SPIS_XFER_T; + +/** + * @brief SPI slave transfer state change handler + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIS_XFER_T structure see notes below + * @return returns 0 on success, or SPI_STAT_RXOV and/or SPI_STAT_TXUR on an error + * @note See @ref SPIS_XFER_T for more information on this function. When using + * this function, the SPI slave interrupts should be enabled and setup in the SPI + * interrupt handler to call this function when they fire. This function is meant + * to be called from the interrupt handler. The @ref SPIS_XFER_T data does not need + * to be setup prior to the call and should be setup by the callbacks instead.
+ * + * The callbacks are handled in the interrupt handler. If you are getting overflow + * or underflow errors, you might need to lower the speed of the master clock or + * extend the master's select assetion time.
+ */ +uint32_t Chip_SPIS_XferHandler(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer); + +/** + * @brief Pre-buffers slave transmit data + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIS_XFER_T structure see notes below + * @return Nothing + * @note Pre-buffering allows the slave to prime the transmit FIFO with data prior to + * the master starting a transfer. If data is not pre-buffered, the initial slave + * transmit data will always be 0x0 with a slave transmit underflow status. + * Pre-buffering is best used when only a single slave select is used by an + * application. + */ +__STATIC_INLINE void Chip_SPIS_PreBuffSlave(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) +{ + Chip_SPIS_XferHandler(pSPI, xfer); +} + +/** + * @brief SPI slave transfer blocking function + * @param pSPI : The base of SPI peripheral on the chip + * @param xfer : Pointer to a SPIS_XFER_T structure + * @return returns 0 on success, or SPI_STAT_RXOV and/or SPI_STAT_TXUR on an error + * @note This function performs a blocking transfer on the SPI slave interface. + * It is not recommended to use this function. Once this function is called, it + * will block forever until a slave transfer consisting of a slave SSEL assertion, + * and de-assertion occur. The callbacks are still used for slave data buffer + * management. SPI interrupts must be disabled prior to calling this function. + */ +uint32_t Chip_SPIS_XferBlocking(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIS_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/stopwatch.h b/ports/lpc/chips/lpc_chip_5410x/inc/stopwatch.h new file mode 100644 index 0000000000000..0224180c03383 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/stopwatch.h @@ -0,0 +1,137 @@ +/* + * @brief Common stopwatch support + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __STOPWATCH_H_ +#define __STOPWATCH_H_ + +#include "cmsis.h" + +/** @defgroup Stop_Watch CHIP: Stopwatch primitives. + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Initialize stopwatch + * @return Nothing + */ +void StopWatch_Init(void); + +/** + * @brief Start a stopwatch + * @return Current cycle count + */ +uint32_t StopWatch_Start(void); + +/** + * @brief Returns number of ticks elapsed since stopwatch was started + * @param startTime : Time returned by StopWatch_Start(). + * @return Number of ticks elapsed since stopwatch was started + */ +__STATIC_INLINE uint32_t StopWatch_Elapsed(uint32_t startTime) +{ + return StopWatch_Start() - startTime; +} + +/** + * @brief Returns number of ticks per second of the stopwatch timer + * @return Number of ticks per second of the stopwatch timer + */ +uint32_t StopWatch_TicksPerSecond(void); + +/** + * @brief Converts from stopwatch ticks to mS. + * @param ticks : Duration in ticks to convert to mS. + * @return Number of mS in given number of ticks + */ +uint32_t StopWatch_TicksToMs(uint32_t ticks); + +/** + * @brief Converts from stopwatch ticks to uS. + * @param ticks : Duration in ticks to convert to uS. + * @return Number of uS in given number of ticks + */ +uint32_t StopWatch_TicksToUs(uint32_t ticks); + +/** + * @brief Converts from mS to stopwatch ticks. + * @param mS : Duration in mS to convert to ticks. + * @return Number of ticks in given number of mS + */ +uint32_t StopWatch_MsToTicks(uint32_t mS); + +/** + * @brief Converts from uS to stopwatch ticks. + * @param uS : Duration in uS to convert to ticks. + * @return Number of ticks in given number of uS + */ +uint32_t StopWatch_UsToTicks(uint32_t uS); + +/** + * @brief Delays the given number of ticks using stopwatch primitives + * @param ticks : Number of ticks to delay + * @return Nothing + */ +__STATIC_INLINE void StopWatch_DelayTicks(uint32_t ticks) +{ + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @brief Delays the given number of mS using stopwatch primitives + * @param mS : Number of mS to delay + * @return Nothing + */ +__STATIC_INLINE void StopWatch_DelayMs(uint32_t mS) +{ + uint32_t ticks = StopWatch_MsToTicks(mS); + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @brief Delays the given number of uS using stopwatch primitives + * @param uS : Number of uS to delay + * @return Nothing + */ +__STATIC_INLINE void StopWatch_DelayUs(uint32_t uS) +{ + uint32_t ticks = StopWatch_UsToTicks(uS); + uint32_t startTime = StopWatch_Start(); + while (StopWatch_Elapsed(startTime) < ticks) {} +} + +/** + * @} + */ + +#endif /* __STOPWATCH_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/syscon_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/syscon_5410x.h new file mode 100644 index 0000000000000..c98fbfff1fea3 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/syscon_5410x.h @@ -0,0 +1,575 @@ +/* + * @brief LPC5410X System & Control driver inclusion file + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYSCON_5410X_H_ +#define __SYSCON_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SYSCON_5410X CHIP: LPC5410X System and Control Driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief LPC5410X Main system configuration register block structure + */ +typedef struct { + __IO uint32_t SYSMEMREMAP; /*!< System Remap register */ + __I uint32_t RESERVED0[4]; + __IO uint32_t SYSTCKCAL; /*!< System Tick Calibration register */ + __I uint32_t RESERVED1[1]; + __IO uint32_t NMISRC; /*!< NMI Source select register */ + __IO uint32_t ASYNCAPBCTRL; /*!< Asynch APB chiplet control register */ + __I uint32_t RESERVED2[7]; + __IO uint32_t SYSRSTSTAT; /*!< System Reset Stat register */ + __IO uint32_t PRESETCTRL[2]; /*!< Peripheral Reset Ctrl register */ + __IO uint32_t PRESETCTRLSET[2]; /*!< Peripheral Reset Ctrl Set register */ + __IO uint32_t PRESETCTRLCLR[2]; /*!< Peripheral Reset Ctrl Clr register */ + __IO uint32_t PIOPORCAP[2]; /*!< PIO Power-On Reset Capture register */ + __I uint32_t RESERVED3[1]; + __IO uint32_t PIORESCAP[2]; /*!< PIO Pad Reset Capture register */ + __I uint32_t RESERVED4[4]; + __IO uint32_t MAINCLKSELA; /*!< Main Clk sel Source Sel A register */ + __IO uint32_t MAINCLKSELB; /*!< Main Clk sel Source Sel B register */ + __I uint32_t RESERVED5; + __IO uint32_t ADCCLKSEL; /*!< ADC Async Clk Sel register */ + __I uint32_t RESERVED6; + __IO uint32_t CLKOUTSELA; /*!< Clk Out Sel Source A register */ + __IO uint32_t CLKOUTSELB; /*!< Clk Out Sel Source B register */ + __I uint32_t RESERVED7; + __IO uint32_t SYSPLLCLKSEL; /*!< System PLL Clk Selregister */ + __I uint32_t RESERVED8[7]; + __IO uint32_t AHBCLKCTRL[2]; /*!< AHB Peripheral Clk Enable register */ + __IO uint32_t AHBCLKCTRLSET[2]; /*!< AHB Peripheral Clk Enable Set register */ + __IO uint32_t AHBCLKCTRLCLR[2]; /*!< AHB Peripheral Clk Enable Clr register */ + __I uint32_t RESERVED9[2]; + __IO uint32_t SYSTICKCLKDIV; /*!< Systick Clock divider register */ + __I uint32_t RESERVED10[7]; + __IO uint32_t AHBCLKDIV; /*!< Main Clk Divider register */ + __IO uint32_t RESERVED11; + __IO uint32_t ADCCLKDIV; /*!< ADC Async Clk Divider register */ + __IO uint32_t CLKOUTDIV; /*!< Clk Out Divider register */ + __I uint32_t RESERVED12[4]; + __IO uint32_t FREQMECTRL; /*!< Frequency Measure Control register */ + __IO uint32_t FLASHCFG; /*!< Flash Config register */ + __I uint32_t RESERVED13[8]; + __IO uint32_t FIFOCTRL; /*!< VFIFO control register */ + __I uint32_t RESERVED14[14]; + __I uint32_t RESERVED15[1]; + __I uint32_t RESERVED16[2]; + __IO uint32_t RTCOSCCTRL; /*!< RTC Oscillator Control register */ + __I uint32_t RESERVED17[7]; + __IO uint32_t SYSPLLCTRL; /*!< System PLL control register */ + __IO uint32_t SYSPLLSTAT; /*!< PLL status register */ + __IO uint32_t SYSPLLNDEC; /*!< PLL N decoder register */ + __IO uint32_t SYSPLLPDEC; /*!< PLL P decoder register */ + __IO uint32_t SYSPLLSSCTRL[2]; /*!< Spread Spectrum control registers */ + __I uint32_t RESERVED18[18]; + __IO uint32_t PDRUNCFG; /*!< Power Down Run Config register */ + __IO uint32_t PDRUNCFGSET; /*!< Power Down Run Config Set register */ + __IO uint32_t PDRUNCFGCLR; /*!< Power Down Run Config Clr register */ + __I uint32_t RESERVED19[9]; + __IO uint32_t STARTERP[2]; /*!< Start Signal Enable Register */ + __IO uint32_t STARTERSET[2]; /*!< Start Signal Enable Set Register */ + __IO uint32_t STARTERCLR[2]; /*!< Start Signal Enable Clr Register */ + __I uint32_t RESERVED20[42]; + __I uint32_t RESERVED20A[4]; + __I uint32_t RESERVED21[57]; + __IO uint32_t JTAG_IDCODE; + __IO uint32_t DEVICE_ID0; /*!< Boot ROM and die revision register */ + __IO uint32_t DEVICE_ID1; /*!< Boot ROM and die revision register */ +} LPC_SYSCON_T; + +/** + * @brief LPC5410X Asynchronous system configuration register block structure + */ +typedef struct { + __IO uint32_t AYSNCPRESETCTRL; /*!< peripheral reset register */ + __IO uint32_t ASYNCPRESETCTRLSET; /*!< peripheral reset Set register */ + __IO uint32_t ASYNCPRESETCTRLCLR; /*!< peripheral reset Clr register */ + __I uint32_t RESERVED0; + __IO uint32_t ASYNCAPBCLKCTRL; /*!< clk enable register */ + __IO uint32_t ASYNCAPBCLKCTRLSET; /*!< clk enable Set register */ + __IO uint32_t ASYNCAPBCLKCTRLCLR; /*!< clk enable Clr register */ + __I uint32_t RESERVED1; + __IO uint32_t ASYNCAPBCLKSELA; /*!< clk source mux A register */ + __IO uint32_t ASYNCAPBCLKSELB; /*!< clk source mux B register */ + __IO uint32_t ASYNCCLKDIV; /*!< clk div register */ + __I uint32_t RESERVED2; + __IO uint32_t FRGCTRL; /*!< Fraction Rate Generator Ctrl register */ +} LPC_ASYNC_SYSCON_T; + +/** + * System memory remap modes used to remap interrupt vectors + */ +typedef enum CHIP_SYSCON_BOOT_MODE_REMAP { + REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */ + REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to user Static RAM */ + REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */ +} CHIP_SYSCON_BOOT_MODE_REMAP_T; + +/** @brief V4 CHIP PART ID */ +#define V4_UID (0x08C1FECE) + +/** + * @brief Re-map interrupt vectors + * @param remap : system memory map value + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_Map(CHIP_SYSCON_BOOT_MODE_REMAP_T remap) +{ + LPC_SYSCON->SYSMEMREMAP = (uint32_t) remap; +} + +/** + * @brief Get system remap setting + * @return System remap setting + */ +__STATIC_INLINE CHIP_SYSCON_BOOT_MODE_REMAP_T Chip_SYSCON_GetMemoryMap(void) +{ + return (CHIP_SYSCON_BOOT_MODE_REMAP_T) LPC_SYSCON->SYSMEMREMAP; +} + +/** + * @brief Set System tick timer calibration value + * @param sysCalVal : System tick timer calibration value + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_SetSYSTCKCAL(uint32_t sysCalVal) +{ + LPC_SYSCON->SYSTCKCAL = sysCalVal; +} + +/** + * Non-Maskable Interrupt Enable/Disable value + */ +#define SYSCON_NMISRC_M0_ENABLE ((uint32_t) 1 << 30) /*!< Enable the Non-Maskable Interrupt M0 (NMI) source */ +#define SYSCON_NMISRC_M4_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt M4 (NMI) source */ + +/** + * @brief Set source for non-maskable interrupt (NMI) + * @param intsrc : IRQ number to assign to the NMI + * @return Nothing + * @note The NMI source will be disabled upon exiting this function. Use the + * Chip_SYSCON_EnableNMISource() function to enable the NMI source. + */ +void Chip_SYSCON_SetNMISource(uint32_t intsrc); + +/** + * @brief Enable interrupt used for NMI source + * @return Nothing + */ +void Chip_SYSCON_EnableNMISource(void); + +/** + * @brief Disable interrupt used for NMI source + * @return Nothing + */ +void Chip_SYSCON_DisableNMISource(void); + +/** + * @brief Enable or disable asynchronous APB bridge and subsystem + * @param enable : true to enable, false to disable + * @return Nothing + * @note This bridge must be enabled to access peripherals on the + * associated bridge. + */ +void Chip_SYSCON_Enable_ASYNC_Syscon(bool enable); + +/** + * @brief Set UART Fractional divider value + * @param fmul : Fractional multiplier value + * @param fdiv : Fractional divider value (Must always be 0xFF) + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_SetUSARTFRGCtrl(uint8_t fmul, uint8_t fdiv) +{ + LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) fmul << 8) | fdiv; +} + +/** + * System reset status values + */ +#define SYSCON_RST_POR (1 << 0) /*!< POR reset status */ +#define SYSCON_RST_EXTRST (1 << 1) /*!< External reset status */ +#define SYSCON_RST_WDT (1 << 2) /*!< Watchdog reset status */ +#define SYSCON_RST_BOD (1 << 3) /*!< Brown-out detect reset status */ +#define SYSCON_RST_SYSRST (1 << 4) /*!< software system reset status */ + +/** + * @brief Get system reset status + * @return An Or'ed value of SYSCON_RST_* + * @note This function returns the detected reset source(s). + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetSystemRSTStatus(void) +{ + return LPC_SYSCON->SYSRSTSTAT; +} + +/** + * @brief Clear system reset status + * @param reset : An Or'ed value of SYSCON_RST_* status to clear + * @return Nothing + * @note This function clears the specified reset source(s). + */ +__STATIC_INLINE void Chip_SYSCON_ClearSystemRSTStatus(uint32_t reset) +{ + LPC_SYSCON->SYSRSTSTAT = reset; +} + +/** + * Peripheral reset identifiers + */ +typedef enum { + /* Peripheral reset enables for PRESETCTRL0 */ + RESET_FLASH = 7, /*!< Flash controller */ + RESET_FMC, /*!< Flash accelerator */ + RESET_INMUX = 11, /*!< Input mux */ + RESET_IOCON = 13, /*!< IOCON */ + RESET_GPIO0, /*!< GPIO Port 0 */ + RESET_GPIO1, /*!< GPIO Port 1 */ + RESET_PINT = 18, /*!< Pin interrupt */ + RESET_GINT, /*!< Grouped interrupt (GINT) */ + RESET_DMA, /*!< DMA */ + RESET_CRC, /*!< CRC */ + RESET_WWDT, /*!< Watchdog timer */ + RESET_RTC, /*!< RTC */ + RESET_MAILBOX = 26, /*!< Mailbox */ + RESET_ADC0, /*!< ADC0 */ + + /* Peripheral reset enables for PRESETCTRL1 */ + RESET_MRT = 32 + 0, /*!< multi-rate timer */ + RESET_RIT, /*!< Repetitive interrupt timer */ + RESET_SCT0, /*!< SCT0 */ + RESET_FIFO = 32 + 9, /*!< System FIFO */ + RESET_UTICK, /*!< Micro-tick Timer */ + RESET_TIMER2 = 32 + 22, /*!< TIMER2 */ + RESET_TIMER3 = 32 + 26, /*!< TIMER3 */ + RESET_TIMER4, /*!< TIMER4 */ + + /* Async peripheral reset enables for ASYNCPRESETCTRL */ + RESET_USART0 = 128 + 1, /*!< UART0 */ + RESET_USART1, /*!< UART1 */ + RESET_USART2, /*!< UART2 */ + RESET_USART3, /*!< UART3 */ + RESET_I2C0, /*!< I2C0 */ + RESET_I2C1, /*!< I2C1 */ + RESET_I2C2, /*!< I2C2 */ + RESET_SPI0 = 128 + 9, /*!< SPI0 */ + RESET_SPI1, /*!< SPI1 */ + RESET_TIMER0 = 128 + 13, /*!< TIMER0 */ + RESET_TIMER1, /*!< TIMER1 */ + RESET_FRG0 /*!< FRG */ +} CHIP_SYSCON_PERIPH_RESET_T; + +/** + * @brief Resets a peripheral + * @param periph : Peripheral to reset + * @return Nothing + * Will assert and de-assert reset for a peripheral. + */ +void Chip_SYSCON_PeriphReset(CHIP_SYSCON_PERIPH_RESET_T periph); + +/** + * @brief Read POR captured PIO status + * @param port : 0 for port 0 pins, 1 for port 1 pins, 2 for port 2 pins, etc. + * @return captured Power-On-Reset (POR) PIO status + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetPORPIOStatus(uint8_t port) +{ + return LPC_SYSCON->PIOPORCAP[port]; +} + +/** + * @brief Read reset captured PIO status + * @param port : 0 for port 0 pins, 1 for port 1 pins, 2 for port 2 pins, etc. + * @return captured reset PIO status + * @note Used when reset other than a Power-On-Reset (POR) occurs. + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetResetPIOStatus(uint8_t port) +{ + return LPC_SYSCON->PIORESCAP[port]; +} + +/** + * @brief Starts a frequency measurement cycle + * @return Nothing + * @note This function is meant to be used with the Chip_INMUX_SetFreqMeasRefClock() + * and Chip_INMUX_SetFreqMeasTargClock() functions. + */ +__STATIC_INLINE void Chip_SYSCON_StartFreqMeas(void) +{ + LPC_SYSCON->FREQMECTRL = 0; + LPC_SYSCON->FREQMECTRL = (1UL << 31); +} + +/** + * @brief Indicates when a frequency measurement cycle is complete + * @return true if a measurement cycle is active, otherwise false + */ +__STATIC_INLINE bool Chip_SYSCON_IsFreqMeasComplete(void) +{ + return (bool) ((LPC_SYSCON->FREQMECTRL & (1UL << 31)) == 0); +} + +/** + * @brief Returns the raw capture value for a frequency measurement cycle + * @return raw cpature value (this is not a frequency) + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetRawFreqMeasCapval(void) +{ + return LPC_SYSCON->FREQMECTRL & 0x3FFF; +} + +/** + * @brief Returns the computed value for a frequency measurement cycle + * @param refClockRate : Reference clock rate used during the frequency measurement cycle + * @return Computed cpature value + */ +uint32_t Chip_SYSCON_GetCompFreqMeas(uint32_t refClockRate); + +/** + * @brief FLASH Access time definitions + */ +typedef enum { + SYSCON_FLASH_1CYCLE = 0, /*!< Flash accesses use 1 CPU clock */ + FLASHTIM_20MHZ_CPU = SYSCON_FLASH_1CYCLE, + SYSCON_FLASH_2CYCLE, /*!< Flash accesses use 2 CPU clocks */ + SYSCON_FLASH_3CYCLE, /*!< Flash accesses use 3 CPU clocks */ + SYSCON_FLASH_4CYCLE, /*!< Flash accesses use 4 CPU clocks */ + SYSCON_FLASH_5CYCLE, /*!< Flash accesses use 5 CPU clocks */ + SYSCON_FLASH_6CYCLE, /*!< Flash accesses use 6 CPU clocks */ + SYSCON_FLASH_7CYCLE, /*!< Flash accesses use 7 CPU clocks */ + SYSCON_FLASH_8CYCLE /*!< Flash accesses use 8 CPU clocks */ +} SYSCON_FLASHTIM_T; + +/** + * @brief Set FLASH memory access time in clocks + * @param clks : Clock cycles for FLASH access + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_SetFLASHAccess(SYSCON_FLASHTIM_T clks) +{ + uint32_t tmp; + + tmp = LPC_SYSCON->FLASHCFG & ~(0xF << 12); + + /* Don't alter lower bits */ + LPC_SYSCON->FLASHCFG = tmp | ((uint32_t) clks << 12); +} + +/** + * @brief System FIFO bit definitions + */ +#define SYSCON_FIFO_U0TXFIFOEN (1 << 0) /*!< USART0 transmitter FIFO enable bit */ +#define SYSCON_FIFO_U1TXFIFOEN (1 << 1) /*!< USART1 transmitter FIFO enable bit */ +#define SYSCON_FIFO_U2TXFIFOEN (1 << 2) /*!< USART2 transmitter FIFO enable bit */ +#define SYSCON_FIFO_U3TXFIFOEN (1 << 3) /*!< USART3 transmitter FIFO enable bit */ +#define SYSCON_FIFO_SPI0TXFIFOEN (1 << 4) /*!< SPI0 transmitter FIFO enable bit */ +#define SYSCON_FIFO_SPI1TXFIFOEN (1 << 5) /*!< SPI1 transmitter FIFO enable bit */ +#define SYSCON_FIFO_U0RXFIFOEN (1 << 8) /*!< USART0 receiver FIFO enable bit */ +#define SYSCON_FIFO_U1RXFIFOEN (1 << 9) /*!< USART1 receiver FIFO enable bit */ +#define SYSCON_FIFO_U2RXFIFOEN (1 << 10) /*!< USART2 receiver FIFO enable bit */ +#define SYSCON_FIFO_U3RXFIFOEN (1 << 11) /*!< USART3 receiver FIFO enable bit */ +#define SYSCON_FIFO_SPI0RXFIFOEN (1 << 12) /*!< SPI0 receiver FIFO enable bit */ +#define SYSCON_FIFO_SPI1RXFIFOEN (1 << 13) /*!< SPI1 receiver FIFO enable bit */ + +/** + * @brief Enable System FIFO(s) for a peripheral + * @param enMask : Or'ed bits or type SYSCON_FIFO_* for enabling system FIFOs + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_EnableSysFIFO(uint32_t enMask) +{ + LPC_SYSCON->FIFOCTRL |= enMask; +} + +/** + * @brief Disable System FIFO(s) for a peripheral + * @param disMask : Or'ed bits or type SYSCON_FIFO_* for disabling system FIFOs + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_DisableSysFIFO(uint32_t disMask) +{ + LPC_SYSCON->FIFOCTRL &= ~disMask; +} + +/** + * Power control definition bits (0 = powered, 1 = powered down) + */ +#define SYSCON_PDRUNCFG_LP_VD1 (1 << 2) +#define SYSCON_PDRUNCFG_PD_IRC_OSC (1 << 3) /*!< IRC oscillator output */ +#define SYSCON_PDRUNCFG_PD_IRC (1 << 4) /*!< IRC oscillator */ +#define SYSCON_PDRUNCFG_PD_FLASH (1 << 5) /*!< Flash memory */ +#define SYSCON_PDRUNCFG_PD_BOD_RST (1 << 7) /*!< Brown-out Detect reset */ +#define SYSCON_PDRUNCFG_PD_BOD_INTR (1 << 8) /*!< Brown-out Detect interrupt */ +#define SYSCON_PDRUNCFG_PD_VD2_ANA (1 << 9) /*!< Analog power */ +#define SYSCON_PDRUNCFG_PD_ADC0 (1 << 10) /*!< ADC0 */ +#define SYSCON_PDRUNCFG_PD_SRAM0A (1 << 13) /*!< First 8 kB of SRAM0 */ +#define SYSCON_PDRUNCFG_PD_SRAM0B (1 << 14) /*!< Remaining portion of SRAM0 */ +#define SYSCON_PDRUNCFG_PD_SRAM1 (1 << 15) /*!< SRAM1 */ +#define SYSCON_PDRUNCFG_PD_SRAM2 (1 << 16) /*!< SRAM2 */ +#define SYSCON_PDRUNCFG_PD_ROM (1 << 17) /*!< ROM */ +#define SYSCON_PDRUNCFG_PD_VDDA_ENA (1 << 19) /*!< Vdda to the ADC, must be enabled for the ADC to work */ +#define SYSCON_PDRUNCFG_PD_WDT_OSC (1 << 20) /*!< Watchdog oscillator */ +#define SYSCON_PDRUNCFG_PD_SYS_PLL (1 << 22) /*!< PLL0 */ +#define SYSCON_PDRUNCFG_PD_VREFP (1 << 23) /*!< Vrefp to the ADC, must be enabled for the ADC to work */ +#define SYSCON_PDRUNCFG_PD_32K_OSC (1 << 24) /*!< 32 kHz RTC oscillator */ +#define SYSCON_PDRUNCFG_LP_VD2 (1 << 27) +#define SYSCON_PDRUNCFG_LP_VD3 (1 << 28) +#define SYSCON_PDRUNCFG_LP_VD8 (1UL << 29) + +/** + * @brief Power up one or more blocks or peripherals + * @return OR'ed values of SYSCON_PDRUNCFG_* values + * @note A high state indicates the peripheral is powered down. + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetPowerStates(void) +{ + return LPC_SYSCON->PDRUNCFG; +} + +/** + * @brief Power down one or more blocks or peripherals + * @param powerdownmask : OR'ed values of SYSCON_PDRUNCFG_* values + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_PowerDown(uint32_t powerdownmask) +{ + /* Disable peripheral states by setting high */ + LPC_SYSCON->PDRUNCFGSET = powerdownmask; +} + +/** + * @brief Power up one or more blocks or peripherals + * @param powerupmask : OR'ed values of SYSCON_PDRUNCFG_* values + * @return Nothing + */ +void Chip_SYSCON_PowerUp(uint32_t powerupmask); + +/** + * Start enable enumerations - for enabling and disabling peripheral wakeup + */ +typedef enum { + SYSCON_STARTER_WWDT = 0, + SYSCON_STARTER_BOD, + SYSCON_STARTER_DMA = 3, + SYSCON_STARTER_GINT0, + SYSCON_STARTER_PINT0, + SYSCON_STARTER_PINT1, + SYSCON_STARTER_PINT2, + SYSCON_STARTER_PINT3, + SYSCON_STARTER_UTICK, + SYSCON_STARTER_MRT, + SYSCON_STARTER_TIMER0, + SYSCON_STARTER_TIMER1, + SYSCON_STARTER_TIMER2, + SYSCON_STARTER_TIMER3, + SYSCON_STARTER_TIMER4, + SYSCON_STARTER_SCT0, + SYSCON_STARTER_USART0, + SYSCON_STARTER_USART1, + SYSCON_STARTER_USART2, + SYSCON_STARTER_USART3, + SYSCON_STARTER_I2C0, + SYSCON_STARTER_I2C1, + SYSCON_STARTER_I2C2, + SYSCON_STARTER_SPI0, + SYSCON_STARTER_SPI1, + SYSCON_STARTER_ADC0_SEQA, + SYSCON_STARTER_ADC0_SEQB, + SYSCON_STARTER_ADC0_THCMP, + SYSCON_STARTER_RTC, + SYSCON_STARTER_MAILBOX = 31, + /* For M4 only */ + SYSCON_STARTER_GINT1 = 32 + 0, + SYSCON_STARTER_PINT4, + SYSCON_STARTER_PINT5, + SYSCON_STARTER_PINT6, + SYSCON_STARTER_PINT7, + SYSCON_STARTER_RIT = 32 + 8, +} CHIP_SYSCON_WAKEUP_T; + +/** + * @brief Enables a pin's (PINT) wakeup logic + * @param periphId : Peripheral identifier + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_EnableWakeup(CHIP_SYSCON_WAKEUP_T periphId) +{ + uint32_t pid = (uint32_t) periphId; + + if (pid < 32) { + LPC_SYSCON->STARTERSET[0] = (1 << pid); + } + else { + LPC_SYSCON->STARTERSET[1] = (1 << (pid - 32)); + } +} + +/** + * @brief Disables peripheral's wakeup logic + * @param periphId : Peripheral identifier + * @return Nothing + */ +__STATIC_INLINE void Chip_SYSCON_DisableWakeup(CHIP_SYSCON_WAKEUP_T periphId) +{ + uint32_t pid = (uint32_t) periphId; + + if (pid < 32) { + LPC_SYSCON->STARTERCLR[0] = (1 << pid); + } + else { + LPC_SYSCON->STARTERCLR[1] = (1 << (pid - 32)); + } +} + +/** + * @brief Return the device ID + * @return Device ID + */ +__STATIC_INLINE uint32_t Chip_SYSCON_GetDeviceID(void) +{ + return LPC_SYSCON->DEVICE_ID0; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSCON_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/timer_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/timer_5410x.h new file mode 100644 index 0000000000000..b2a455536c640 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/timer_5410x.h @@ -0,0 +1,456 @@ +/* + * @brief LPC5410X 32-bit Timer/PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __TIMER_5410X_H_ +#define __TIMER_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup TIMER_5410X CHIP: LPC5410X 32-bit Timer driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief 32-bit Standard timer register block structure + */ +typedef struct { /*!< TIMERn Structure */ + __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ + __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ + __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ + __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ + __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ + __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ + __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ + __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ + __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ + __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ + __IO uint32_t PWMC; +} LPC_TIMER_T; + +/** Macro to clear interrupt pending */ +#define TIMER_IR_CLR(n) _BIT(n) + +/** Macro for getting a timer match interrupt bit */ +#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F)) +/** Macro for getting a capture event interrupt bit */ +#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4))) + +/** Timer/counter enable bit */ +#define TIMER_ENABLE ((uint32_t) (1 << 0)) +/** Timer/counter reset bit */ +#define TIMER_RESET ((uint32_t) (1 << 1)) +/** Timer Control register Mask */ +#define TIMER_CTRL_MASK ((uint32_t) 0x03) + +/** Bit location for interrupt on MRx match, n = 0 to 3 */ +#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3))) +/** Bit location for reset on MRx match, n = 0 to 3 */ +#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1))) +/** Bit location for stop on MRx match, n = 0 to 3 */ +#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2))) +/** Match Control register Mask */ +#define TIMER_MCR_MASK ((uint32_t) 0x0FFF) + +/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ +#define TIMER_CAP_RISING(n) (_BIT(((n) * 3))) +/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ +#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1))) +/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ +#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2))) +/** Capture Control register Mask */ +#define TIMER_CCR_MASK ((uint32_t) 0x0FFF) +/** External Match register Mask */ +#define TIMER_EMR_MASK ((uint32_t) 0x0FFF) +/** Counter Control register Mask */ +#define TIMER_CTCR_MASK ((uint32_t) 0x0F) + +/** + * @brief Initialize a timer + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_Init(LPC_TIMER_T *pTMR); + +/** + * @brief Shutdown a timer + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR); + +/** + * @brief Determine if a match interrupt is pending + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * @note Determine if the match interrupt for the passed timer and match + * counter is pending. + */ +__STATIC_INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0); +} + +/** + * @brief Determine if a capture interrupt is pending + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * @note Determine if the capture interrupt for the passed capture pin is + * pending. + */ +__STATIC_INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum) +{ + return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0); +} + +/** + * @brief Clears a (pending) match interrupt + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match interrupt number to clear + * @return Nothing + * @note Clears a pending timer match interrupt. + */ +__STATIC_INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->IR = TIMER_IR_CLR(matchnum); +} + +/** + * @brief Clears a (pending) capture interrupt + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture interrupt number to clear + * @return Nothing + * @note Clears a pending timer capture interrupt. + */ +__STATIC_INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->IR = (0x10 << capnum); +} + +/** + * @brief Enables the timer (starts count) + * @param pTMR : Pointer to timer IP register address + * @return Nothing + * @note Enables the timer to start counting. + */ +__STATIC_INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR) +{ + pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) | TIMER_ENABLE; +} + +/** + * @brief Disables the timer (stops count) + * @param pTMR : Pointer to timer IP register address + * @return Nothing + * @note Disables the timer to stop counting. + */ +__STATIC_INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR) +{ + pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) & ~TIMER_ENABLE; +} + +/** + * @brief Returns the current timer count + * @param pTMR : Pointer to timer IP register address + * @return Current timer terminal count value + * @note Returns the current timer terminal count. + */ +__STATIC_INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR) +{ + return pTMR->TC; +} + +/** + * @brief Returns the current prescale count + * @param pTMR : Pointer to timer IP register address + * @return Current timer prescale count value + * @note Returns the current prescale count. + */ +__STATIC_INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR) +{ + return pTMR->PC; +} + +/** + * @brief Sets the prescaler value + * @param pTMR : Pointer to timer IP register address + * @param prescale : Prescale value to set the prescale register to + * @return Nothing + * @note Sets the prescale count value. + */ +__STATIC_INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale) +{ + pTMR->PR = prescale; +} + +/** + * @brief Sets a timer match value + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer to set match count for + * @param matchval : Match value for the selected match count + * @return Nothing + * @note Sets one of the timer match values. + */ +__STATIC_INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval) +{ + pTMR->MR[matchnum] = matchval; +} + +/** + * @brief Reads a capture register + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture register to read + * @return The selected capture register value + * @note Returns the selected capture register value. + */ +__STATIC_INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum) +{ + return pTMR->CR[capnum]; +} + +/** + * @brief Resets the timer terminal and prescale counts to 0 + * @param pTMR : Pointer to timer IP register address + * @return Nothing + */ +void Chip_TIMER_Reset(LPC_TIMER_T *pTMR); + +/** + * @brief Enables a match interrupt that fires when the terminal count + * matches the match counter value. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief Disables a match interrupt for a match counter. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, enables reset of the terminal count register when a match occurs + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, disables reset of the terminal count register when a match occurs + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief Enable a match timer to stop the terminal count when a + * match count equals the terminal count. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Disable stop on match for a match timer. Disables a match timer + * to stop the terminal count when a match count equals the terminal count. + * @param pTMR : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) +{ + pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Enables capture on on rising edge of selected CAP signal for the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_RISING(capnum); +} + +/** + * @brief Disables capture on on rising edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_RISING(capnum); +} + +/** + * @brief Enables capture on on falling edge of selected CAP signal. For the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Disables capture on on falling edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Enables interrupt on capture of selected CAP signal. For the + * selected capture register, an interrupt will be generated when the enabled + * rising or falling edge on CAPn.capnum is detected. + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Disables interrupt on capture of selected CAP signal + * @param pTMR : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +__STATIC_INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum) +{ + pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Standard timer initial match pin state and change state + */ +typedef enum IP_TIMER_PIN_MATCH_STATE { + TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */ + TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */ + TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */ + TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */ +} TIMER_PIN_MATCH_STATE_T; + +/** + * @brief Sets external match control (MATn.matchnum) pin control. For the pin + * selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + * @param pTMR : Pointer to timer IP register address + * @param initial_state : Initial state of the pin, high(1) or low(0) + * @param matchState : Selects the match state for the pin + * @param matchnum : MATn.matchnum signal to use + * @return Nothing + * @note For the pin selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + */ +void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, + TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum); + +/** + * @brief Standard timer clock and edge for count source + */ +typedef enum IP_TIMER_CAP_SRC_STATE { + TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */ + TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */ + TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */ + TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */ +} TIMER_CAP_SRC_STATE_T; + +/** + * @brief Sets timer count source and edge with the selected passed from CapSrc. + * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + * @param pTMR : Pointer to timer IP register address + * @param capSrc : timer clock source and edge + * @param capnum : CAPn.capnum pin to use (0 - 2) + * @return Nothing + * @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + */ +__STATIC_INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR, + TIMER_CAP_SRC_STATE_T capSrc, + int8_t capnum) +{ + pTMR->CTCR = (pTMR->CTCR & ~TIMER_CTCR_MASK) | ((uint32_t) capSrc | ((uint32_t) capnum) << 2); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/uart_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/uart_5410x.h new file mode 100644 index 0000000000000..4da9574d4d8e2 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/uart_5410x.h @@ -0,0 +1,539 @@ +/* + * @brief LPC5410X UART driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __UART_5410X_H_ +#define __UART_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ring_buffer.h" + +/** @defgroup UART_5410X CHIP: LPC5410X UART Driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/* UART Status Register bits */ +#define UART_RXRDY (1 << 0) /* Receive data ready */ +#define UART_RXIDLE (1 << 1) /* Receiver Idle */ +#define UART_TXRDY (1 << 2) /* Transmitter ready */ +#define UART_TXIDLE (1 << 3) /* Transmitter Idle */ +#define UART_RXDERR (0xF100) /* overrun err, frame err, parity err, RxNoise err */ +#define UART_TXDERR (0x0200) /* underrun err */ +#define UART_START (0x1000) + +/* UART Interrupt register bits */ +#define UART_INT_RXRDY (1 << 0) +#define UART_INT_TXRDY (1 << 2) +#define UART_INT_TXIDLE (1 << 3) +#define UART_INT_CTS (1 << 5) +#define UART_INT_TXDIS (1 << 6) +#define UART_INT_OVR (1 << 8) +#define UART_INT_BREAK (1 << 11) +#define UART_INT_START (1 << 12) +#define UART_INT_FRMERR (1 << 13) +#define UART_INT_PARERR (1 << 14) +#define UART_INT_RXNOISE (1 << 15) +#define UART_INT_ABAUDERR (1 << 16) + +/* Configuration register bits */ +#define UARTEN 1 + +#define UART_CTL_TXDIS (1UL << 6) +#define UART_CTL_TXBRKEN (1UL << 1) +#define UART_CTL_AUTOBAUD (1UL << 16) +#define UART_CFG_RES (2UL | (1UL << 10) | (1UL << 13) | (1UL << 17) | (0xFFUL << 24)) +#define UART_CFG_ENABLE 1 +#define UART_PAR_MASK (3 << 4) +#define UART_DATA_MASK (3 << 2) +#define UART_CTL_RES (1UL | (7UL << 3) | (1UL << 7) | (0x3FUL << 10) | (0x7FFFUL << 17)) +#define UART_IDLE_MASK (1 << 3) +#define UART_STAT_CTS (1 << 4) +#define UART_STAT_BREAK (1 << 10) +#define UART_STAT_RXIDLE (1 << 1) + +/******************* + * EXPORTED MACROS * + ********************/ +#define ECHO_EN 1 +#define ECHO_DIS 0 + +/********************* + * EXPORTED TYPEDEFS * + **********************/ + +typedef struct { /* UART registers Structure */ + __IO uint32_t CFG; /*!< Offset: 0x000 Configuration register */ + __IO uint32_t CTL; /*!< Offset: 0x004 Control register */ + __IO uint32_t STAT; /*!< Offset: 0x008 Status register */ + __IO uint32_t INTENSET; /*!< Offset: 0x00C Interrupt Enable Read and Set register */ + __O uint32_t INTENCLR; /*!< Offset: 0x010 Interrupt Enable Clear register */ + __I uint32_t RXDAT; /*!< Offset: 0x014 Receiver Data register */ + __I uint32_t RXDATSTAT; /*!< Offset: 0x018 Rx Data with status */ + __O uint32_t TXDAT; /*!< Offset: 0x01C Transmitter Data Register */ + __IO uint32_t BRG; /*!< Offset: 0x020 Baud Rate Generator register */ + __I uint32_t INTSTAT; /*!< Offset: 0x024 Interrupt Status register */ + __IO uint32_t OSR; /*!< Offset: 0x028 Oversampling register */ + __IO uint32_t ADR; /*!< Offset: 0x02C Address register (for automatic address matching) */ +} LPC_USART_T; + +/** + * @brief UART CFG register definitions + */ +// #define UART_CFG_ENABLE (0x01 << 0) +#define UART_CFG_DATALEN_7 (0x00 << 2) /*!< UART 7 bit length mode */ +#define UART_CFG_DATALEN_8 (0x01 << 2) /*!< UART 8 bit length mode */ +#define UART_CFG_DATALEN_9 (0x02 << 2) /*!< UART 9 bit length mode */ +#define UART_CFG_PARITY_NONE (0x00 << 4) /*!< No parity */ +#define UART_CFG_PARITY_EVEN (0x02 << 4) /*!< Even parity */ +#define UART_CFG_PARITY_ODD (0x03 << 4) /*!< Odd parity */ +#define UART_CFG_STOPLEN_1 (0x00 << 6) /*!< UART One Stop Bit Select */ +#define UART_CFG_STOPLEN_2 (0x01 << 6) /*!< UART Two Stop Bits Select */ +#define UART_CFG_MODE32K (0x01 << 7) /*!< UART 32K MODE */ +#define UART_CFG_LINMODE (0x01 << 8) /*!< UART LIN MODE */ +#define UART_CFG_CTSEN (0x01 << 9) /*!< CTS enable bit */ +#define UART_CFG_SYNCEN (0x01 << 11) /*!< Synchronous mode enable bit */ +#define UART_CFG_CLKPOL (0x01 << 12) /*!< Un_RXD rising edge sample enable bit */ +#define UART_CFG_SYNCMST (0x01 << 14) /*!< Select master mode (synchronous mode) enable bit */ +#define UART_CFG_LOOP (0x01 << 15) /*!< Loopback mode enable bit */ + +/** + * @brief UART CTRL register definitions + */ +#define UART_CTRL_TXBRKEN (0x01 << 1) /*!< Continuous break enable bit */ +#define UART_CTRL_ADDRDET (0x01 << 2) /*!< Address detect mode enable bit */ +#define UART_CTRL_TXDIS (0x01 << 6) /*!< Transmit disable bit */ +#define UART_CTRL_CC (0x01 << 8) /*!< Continuous Clock mode enable bit */ +#define UART_CTRL_CLRCC (0x01 << 9) /*!< Clear Continuous Clock bit */ +#define UART_CTRL_AUTOBAUD (0x01 << 16) /*!< Auto baud bit */ + +/** + * @brief UART STAT register definitions + */ +#define UART_STAT_RXRDY (0x01 << 0) /*!< Receiver ready */ +// #define UART_STAT_RXIDLE (0x01 << 1) /*!< Receiver idle */ +#define UART_STAT_TXRDY (0x01 << 2) /*!< Transmitter ready for data */ +#define UART_STAT_TXIDLE (0x01 << 3) /*!< Transmitter idle */ +// #define UART_STAT_CTS (0x01 << 4) /*!< Status of CTS signal */ +#define UART_STAT_DELTACTS (0x01 << 5) /*!< Change in CTS state */ +#define UART_STAT_TXDISINT (0x01 << 6) /*!< Transmitter disabled */ +#define UART_STAT_OVERRUNINT (0x01 << 8) /*!< Overrun Error interrupt flag. */ +#define UART_STAT_RXBRK (0x01 << 10) /*!< Received break */ +#define UART_STAT_DELTARXBRK (0x01 << 11) /*!< Change in receive break detection */ +#define UART_STAT_START (0x01 << 12) /*!< Start detected */ +#define UART_STAT_FRM_ERRINT (0x01 << 13) /*!< Framing Error interrupt flag */ +#define UART_STAT_PAR_ERRINT (0x01 << 14) /*!< Parity Error interrupt flag */ +#define UART_STAT_RXNOISEINT (0x01 << 15) /*!< Received Noise interrupt flag */ +#define UART_STAT_ABERR (0x01 << 16) /*!< Auto baud error flag */ + +/** + * @brief UART INTENSET/INTENCLR register definitions + */ +#define UART_INTEN_RXRDY (0x01 << 0) /*!< Receive Ready interrupt */ +#define UART_INTEN_TXRDY (0x01 << 2) /*!< Transmit Ready interrupt */ +#define UART_INTEN_DELTACTS (0x01 << 5) /*!< Change in CTS state interrupt */ +#define UART_INTEN_TXDIS (0x01 << 6) /*!< Transmitter disable interrupt */ +#define UART_INTEN_OVERRUN (0x01 << 8) /*!< Overrun error interrupt */ +#define UART_INTEN_DELTARXBRK (0x01 << 11) /*!< Change in receiver break detection interrupt */ +#define UART_INTEN_START (0x01 << 12) /*!< Start detect interrupt */ +#define UART_INTEN_FRAMERR (0x01 << 13) /*!< Frame error interrupt */ +#define UART_INTEN_PARITYERR (0x01 << 14) /*!< Parity error interrupt */ +#define UART_INTEN_RXNOISE (0x01 << 15) /*!< Received noise interrupt */ + +/** + * @brief UART Baud rate calculation structure + * @note + * Use oversampling (@a ovr) value other than 16, only if the difference + * between the actual baud and desired baud has an unacceptable error percentage. + * Smaller @a ovr values can cause the sampling position within the data-bit + * less accurate an may potentially cause more noise errors or incorrect data + * set ovr to < 10 only when there is no other higher values suitable. Note that + * the UART OSR and BRG are -1 encoded i.e., when writing to register BRG @a div must + * be (div - 1) and when writing to OSR @a ovr must be (ovr - 1) + */ +typedef struct { + uint32_t clk; /*!< IN: Base clock to fractional divider; OUT: "Base clock rate for UART" */ + uint32_t baud; /*!< IN: Required baud rate; OUT: Actual baud rate */ + uint8_t ovr; /*!< IN: Number of desired over samples [0-auto detect or values 5 to 16]; OUT: Auto detected over samples [unchanged if IN is not 0] */ + uint8_t mul; /*!< IN: 0 - calculate MUL, 1 - do't calculate (@a clk) has UART base clock; OUT: MUL value to be set in FRG register */ + uint16_t div; /*!< OUT: Integer divider to divide the "Base clock rate for UART" */ +} UART_BAUD_T; + +/** + * @brief Calculate baudrate parameters for a UART + * @param pUART : Pointer to selected UARTx peripheral (Ignored) + * @param pBaud : Pointer to baud structure #UART_BAUD_T + * @return LPC_OK(0) on success; non-zero on failure + * @note Values returned by pBaud is valid only if the return value is LPC_OK. + */ +uint32_t Chip_UART_CalcBaud(LPC_USART_T *pUART, UART_BAUD_T *pBaud); + +/** + * @brief Enable the UART + * @param pUART : Pointer to selected UARTx peripheral + * @return Nothing + */ +__STATIC_INLINE void Chip_UART_Enable(LPC_USART_T *pUART) +{ + pUART->CFG |= UART_CFG_ENABLE; +} + +/** + * @brief Disable the UART + * @param pUART : Pointer to selected UARTx peripheral + * @return Nothing + */ +__STATIC_INLINE void Chip_UART_Disable(LPC_USART_T *pUART) +{ + pUART->CFG &= ~UART_CFG_ENABLE; +} + +/** + * @brief Enable transmission on UART TxD pin + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +__STATIC_INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART) +{ + pUART->CTL &= ~UART_CTRL_TXDIS; +} + +/** + * @brief Disable transmission on UART TxD pin + * @param pUART : Pointer to selected pUART peripheral + * @return Nothing + */ +__STATIC_INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART) +{ + pUART->CTL |= UART_CTRL_TXDIS; +} + +/** + * @brief Set auto baud + * @param pUART : Pointer to selected pUART peripheral + * @return true if auto baud succeeds, false if fails + */ +__STATIC_INLINE uint32_t Chip_UART_AutoBaud(LPC_USART_T *pUART) +{ + while ( (pUART->STAT & UART_STAT_RXIDLE) != UART_STAT_RXIDLE ) {} + pUART->CTL |= UART_CTRL_AUTOBAUD; + while ( pUART->CTL & UART_CTRL_AUTOBAUD ) { + if ( pUART->STAT & UART_STAT_ABERR ) { + pUART->STAT = UART_STAT_ABERR; + return false; + } + } + return true; +} + +/** + * @brief Transmit a single data byte through the UART peripheral + * @param pUART : Pointer to selected UART peripheral + * @param data : Byte to transmit + * @return Nothing + * @note This function attempts to place a byte into the UART transmit + * holding register regard regardless of UART state. + */ +__STATIC_INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data) +{ + pUART->TXDAT = (uint32_t) data; +} + +/** + * @brief Read a single byte data from the UART peripheral + * @param pUART : Pointer to selected UART peripheral + * @return A single byte of data read + * @note This function reads a byte from the UART receive FIFO or + * receive hold register regard regardless of UART state. The + * FIFO status should be read first prior to using this function + */ +__STATIC_INLINE uint32_t Chip_UART_ReadByte(LPC_USART_T *pUART) +{ + /* Strip off undefined reserved bits, keep 9 lower bits */ + return (uint32_t) (pUART->RXDAT & 0x000001FF); +} + +/** + * @brief Sets the UART baudrate divider values (BRG and OSR) + * @param pUART : Pointer to selected UART peripheral + * @param div : Baud rate clock divider value + * @param ovr : Over sampling value to be used + * @return Nothing + */ +__STATIC_INLINE void Chip_UART_Div(LPC_USART_T *pUART, uint32_t div, uint32_t ovr) +{ + if (div) { + pUART->BRG = div - 1; + } + if (ovr) { + pUART->OSR = ovr - 1; + } +} + +/** + * @brief Enable UART interrupts + * @param pUART : Pointer to selected UART peripheral + * @param intMask : OR'ed Interrupts to enable + * @return Nothing + * @note Use an OR'ed value of UART_INTEN_* definitions with this function + * to enable specific UART interrupts. + */ +__STATIC_INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask) +{ + pUART->INTENSET = intMask; +} + +/** + * @brief Disable UART interrupts + * @param pUART : Pointer to selected UART peripheral + * @param intMask : OR'ed Interrupts to disable + * @return Nothing + * @note Use an OR'ed value of UART_INTEN_* definitions with this function + * to disable specific UART interrupts. + */ +__STATIC_INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask) +{ + pUART->INTENCLR = intMask; +} + +/** + * @brief Returns UART interrupts that are enabled + * @param pUART : Pointer to selected UART peripheral + * @return Returns the enabled UART interrupts + * @note Use an OR'ed value of UART_INTEN_* definitions with this function + * to determine which interrupts are enabled. You can check + * for multiple enabled bits if needed. + */ +__STATIC_INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART) +{ + return pUART->INTENSET; +} + +/** + * @brief Get UART interrupt status + * @param pUART : The base of UART peripheral on the chip + * @return The Interrupt status register of UART + * @note Multiple interrupts may be pending. Mask the return value + * with one or more UART_INTEN_* definitions to determine + * pending interrupts. + */ +__STATIC_INLINE uint32_t Chip_UART_GetIntStatus(LPC_USART_T *pUART) +{ + return pUART->INTSTAT; +} + +/** + * @brief Configure data width, parity and stop bits + * @param pUART : Pointer to selected pUART peripheral + * @param config : UART configuration, OR'ed values of select UART_CFG_* defines + * @return Nothing + * @note Select OR'ed config options for the UART from the UART_CFG_PARITY_*, + * UART_CFG_STOPLEN_*, and UART_CFG_DATALEN_* definitions. For example, + * a configuration of 8 data bits, 1 stop bit, and even (enabled) parity would be + * (UART_CFG_DATALEN_8 | UART_CFG_STOPLEN_1 | UART_CFG_PARITY_EVEN). Will not + * alter other bits in the CFG register. + */ +__STATIC_INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config) +{ + pUART->CFG = config; +} + +/** + * @brief Get the UART status register + * @param pUART : Pointer to selected UARTx peripheral + * @return UART status register + * @note Multiple statuses may be pending. Mask the return value + * with one or more UART_STAT_* definitions to determine + * statuses. + */ +__STATIC_INLINE uint32_t Chip_UART_GetStatus(LPC_USART_T *pUART) +{ + return pUART->STAT; +} + +/** + * @brief Clear the UART status register + * @param pUART : Pointer to selected UARTx peripheral + * @param stsMask : OR'ed statuses to disable + * @return Nothing + * @note Multiple interrupts may be pending. Mask the return value + * with one or more UART_INTEN_* definitions to determine + * pending interrupts. + */ +__STATIC_INLINE void Chip_UART_ClearStatus(LPC_USART_T *pUART, uint32_t stsMask) +{ + pUART->STAT = stsMask; +} + +/** + * @brief Initialize the UART peripheral + * @param pUART : The base of UART peripheral on the chip + * @return Nothing + */ +void Chip_UART_Init(LPC_USART_T *pUART); + +/** + * @brief Deinitialize the UART peripheral + * @param pUART : The base of UART peripheral on the chip + * @return Nothing + */ +void Chip_UART_DeInit(LPC_USART_T *pUART); + +/** + * @brief Transmit a byte array through the UART peripheral (non-blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to bytes to transmit + * @param numBytes : Number of bytes to transmit + * @return The actual number of bytes placed into the FIFO + * @note This function places data into the transmit FIFO until either + * all the data is in the FIFO or the FIFO is full. This function + * will not block in the FIFO is full. The actual number of bytes + * placed into the FIFO is returned. This function ignores errors. + */ +int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes); + +/** + * @brief Read data through the UART peripheral (non-blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to bytes array to fill + * @param numBytes : Size of the passed data array + * @return The actual number of bytes read + * @note This function reads data from the receive FIFO until either + * all the data has been read or the passed buffer is completely full. + * This function will not block. This function ignores errors. + */ +int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes); + +/** + * @brief Set baud rate for UART + * @param pUART : The base of UART peripheral on the chip + * @param baudrate: Baud rate to be set + * @return Nothing + * @note + * Setting the baud rate of one UART will affect the baud rate of other + * UART's as the Fractional divider is shared between all the UART. + */ +void Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate); + +/** + * @brief Transmit a byte array through the UART peripheral (blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to data to transmit + * @param numBytes : Number of bytes to transmit + * @return The number of bytes transmitted + * @note This function will send or place all bytes into the transmit + * FIFO. This function will block until the last bytes are in the FIFO. + */ +int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes); + +/** + * @brief Read data through the UART peripheral (blocking) + * @param pUART : Pointer to selected UART peripheral + * @param data : Pointer to data array to fill + * @param numBytes : Size of the passed data array + * @return The size of the dat array + * @note This function reads data from the receive FIFO until the passed + * buffer is completely full. The function will block until full. + * This function ignores errors. + */ +int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes); + +/** + * @brief UART receive-only interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @return Nothing + * @note If ring buffer support is desired for the receive side + * of data transfer, the UART interrupt should call this + * function for a receive based interrupt status. + */ +void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); + +/** + * @brief UART transmit-only interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @return Nothing + * @note If ring buffer support is desired for the transmit side + * of data transfer, the UART interrupt should call this + * function for a transmit based interrupt status. + */ +void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); + +/** + * @brief Populate a transmit ring buffer and start UART transmit + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @param data : Pointer to buffer to move to ring buffer + * @param count : Number of bytes to move + * @return The number of bytes placed into the ring buffer + * @note Will move the data into the TX ring buffer and start the + * transfer. If the number of bytes returned is less than the + * number of bytes to send, the ring buffer is considered full. + */ +uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int count); + +/** + * @brief Copy data from a receive ring buffer + * @param pUART : Pointer to selected UART peripheral + * @param pRB : Pointer to ring buffer structure to use + * @param data : Pointer to buffer to fill from ring buffer + * @param bytes : Size of the passed buffer in bytes + * @return The number of bytes placed into the ring buffer + * @note Will move the data from the RX ring buffer up to the + * the maximum passed buffer size. Returns 0 if there is + * no data in the ring buffer. + */ +int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes); + +/** + * @brief UART receive/transmit interrupt handler for ring buffers + * @param pUART : Pointer to selected UART peripheral + * @param pRXRB : Pointer to transmit ring buffer + * @param pTXRB : Pointer to receive ring buffer + * @return Nothing + * @note This provides a basic implementation of the UART IRQ + * handler for support of a ring buffer implementation for + * transmit and receive. + */ +void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/utick_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/utick_5410x.h new file mode 100644 index 0000000000000..21cca7e9a8ddb --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/utick_5410x.h @@ -0,0 +1,174 @@ +/* + * @brief LPC5410X Micro Tick chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __UTICK_5410X_H_ +#define __UTICK_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup UTICK_5410X CHIP: LPC5410X Micro Tick driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief Micro Tick register block structure + */ +typedef struct { + __IO uint32_t CTRL; /*!< UTick Control register */ + __IO uint32_t STATUS; /*!< UTick Status register */ +} LPC_UTICK_T; + +/** + * @brief UTick register definitions + */ +/** UTick repeat delay bit */ +#define UTICK_CTRL_REPEAT ((uint32_t) 1UL << 31) +/** UTick Delay Value Mask */ +#define UTICK_CTRL_DELAY_MASK ((uint32_t) 0x7FFFFFFF) +/** UTick Interrupt Status bit */ +#define UTICK_STATUS_INTR ((uint32_t) 1 << 0) +/** UTick Active Status bit */ +#define UTICK_STATUS_ACTIVE ((uint32_t) 1 << 1) +/** UTick Status Register Mask */ +#define UTICK_STATUS_MASK ((uint32_t) 0x03) + +/** + * @brief Initialize the UTICK peripheral + * @param pUTICK : UTICK peripheral selected + * @return Nothing + */ +__STATIC_INLINE void Chip_UTICK_Init(LPC_UTICK_T *pUTICK) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_UTICK); + Chip_SYSCON_PeriphReset(RESET_UTICK); +} + +/** + * @brief De-initialize the UTICK peripheral + * @param pUTICK : UTICK peripheral selected + * @return Nothing + */ +__STATIC_INLINE void Chip_UTICK_DeInit(LPC_UTICK_T *pUTICK) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_UTICK); +} + +/** + * @brief Setup UTICK + * @param pUTICK : The base address of UTICK block + * @param tick_value : Tick value, should not exceed UTICK_CTRL_DELAY_MASK + * @param repeat : If true then delay repeats continuously else it is one time + * @return Nothing + */ +__STATIC_INLINE void Chip_UTICK_SetTick(LPC_UTICK_T *pUTICK, uint32_t tick_value, bool repeat) +{ + if (repeat) { + tick_value |= UTICK_CTRL_REPEAT; + } + + pUTICK->CTRL = tick_value; +} + +/** + * @brief Setup UTICK for the passed delay (in mS) + * @param pUTICK : The base address of UTICK block + * @param delayMs : Delay value in mS (Maximum is 1000mS) + * @param repeat : If true then delay repeats continuously else it is one time + * @return Nothing + * @note The WDT oscillator runs at about 500KHz, so delays in uS won't be + * too accurate. + */ +__STATIC_INLINE void Chip_UTICK_SetDelayMs(LPC_UTICK_T *pUTICK, uint32_t delayMs, bool repeat) +{ + uint32_t tick_value = (delayMs * Chip_Clock_GetWDTOSCRate()) / 1000; + + if (repeat) { + tick_value |= UTICK_CTRL_REPEAT; + } + else { + tick_value &= ~UTICK_CTRL_REPEAT; + } + + pUTICK->CTRL = tick_value; +} + +/** + * @brief Read UTICK Value + * @param pUTICK : The base address of UTICK block + * @return Current tick value + */ +__STATIC_INLINE uint32_t Chip_UTICK_GetTick(LPC_UTICK_T *pUTICK) +{ + return pUTICK->CTRL & UTICK_CTRL_DELAY_MASK; +} + +/** + * @brief Halt UTICK timer + * @param pUTICK : The base address of UTICK block + * @return Nothing + */ +__STATIC_INLINE void Chip_UTICK_Halt(LPC_UTICK_T *pUTICK) +{ + pUTICK->CTRL = 0; +} + +/** + * @brief Returns the status of UTICK + * @param pUTICK : The base address of UTICK block + * @return Micro tick timer status register value + */ +__STATIC_INLINE uint32_t Chip_UTICK_GetStatus(LPC_UTICK_T *pUTICK) +{ + return pUTICK->STATUS; +} + +/** + * @brief Clears UTICK Interrupt flag + * @param pUTICK : The base address of UTICK block + * @return Nothing + */ +__STATIC_INLINE void Chip_UTICK_ClearInterrupt(LPC_UTICK_T *pUTICK) +{ + pUTICK->STATUS = UTICK_STATUS_INTR; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UTICK_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/inc/wwdt_5410x.h b/ports/lpc/chips/lpc_chip_5410x/inc/wwdt_5410x.h new file mode 100644 index 0000000000000..da801ec47153f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/inc/wwdt_5410x.h @@ -0,0 +1,253 @@ +/* + * @brief LPC5410X WWDT chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __WWDT_5410X_H_ +#define __WWDT_5410X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup LPC_WWDT CHIP: LPC5410X Windowed Watchdog driver + * @ingroup CHIP_5410X_DRIVERS + * @{ + */ + +/** + * @brief Windowed Watchdog register block structure + */ +typedef struct { /*!< WWDT Structure */ + __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */ + __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ + __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ + __I uint32_t RESERVED0; + __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ + __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */ +} LPC_WWDT_T; + +/** + * @brief Watchdog Mode register definitions + */ +/** Watchdog Mode Bitmask */ +#define WWDT_WDMOD_BITMASK ((uint32_t) 0x3F) +/** WWDT enable bit */ +#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0)) +/** WWDT reset enable bit */ +#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1)) +/** WWDT time-out flag bit */ +#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2)) +/** WWDT warning interrupt flag bit */ +#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3)) +/** WWDT Protect flag bit */ +#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4)) +/** WWDT lock bit */ +#define WWDT_WDMOD_LOCK ((uint32_t) (1 << 5)) + +/** + * @brief Initialize the Watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +void Chip_WWDT_Init(LPC_WWDT_T *pWWDT); + +/** + * @brief Shutdown the Watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +__STATIC_INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_WWDT); +} + +/** + * @brief Set WDT timeout constant value used for feed + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return none + */ +__STATIC_INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->TC = timeout; +} + +/** + * @brief Feed watchdog timer + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + * @note If this function isn't called, a watchdog timer warning will occur. + * After the warning, a timeout will occur if a feed has happened. + * Note that if WWDT registers are modified in an interrupt then it is a good + * idea to prevent those interrupts when writing the feed sequence. + */ +__STATIC_INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT) +{ + pWWDT->FEED = 0xAA; + pWWDT->FEED = 0x55; +} + +/** + * @brief Set WWDT warning interrupt + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT warning in ticks, between 0 and 1023 + * @return None + * @note This is the number of ticks after the watchdog interrupt that the + * warning interrupt will be generated. + */ +__STATIC_INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->WARNINT = timeout; +} + +/** + * @brief Get WWDT warning interrupt + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return WWDT warning interrupt + */ +__STATIC_INLINE uint32_t Chip_WWDT_GetWarning(LPC_WWDT_T *pWWDT) +{ + return pWWDT->WARNINT; +} + +/** + * @brief Set WWDT window time + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return None + * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut() + * function and this function, with this function defining the last tick before the + * watchdog window interrupt occurs. + */ +__STATIC_INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout) +{ + pWWDT->WINDOW = timeout; +} + +/** + * @brief Get WWDT window time + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return WWDT window time + */ +__STATIC_INLINE uint32_t Chip_WWDT_GetWindow(LPC_WWDT_T *pWWDT) +{ + return pWWDT->WINDOW; +} + +/** + * @brief Enable watchdog timer options + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options + * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot + * be unset. + */ +__STATIC_INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options) +{ + pWWDT->MOD = (pWWDT->MOD & WWDT_WDMOD_BITMASK) | options; +} + +/** + * @brief Disable/clear watchdog timer options + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDTOF). + */ +__STATIC_INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options) +{ + pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK; +} + +/** + * @brief Enable WWDT activity + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return None + */ +__STATIC_INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT) +{ + Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN); + Chip_WWDT_Feed(pWWDT); +} + +/** + * @brief Read WWDT status flag + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return Watchdog status, an Or'ed value of WWDT_WDMOD_* + */ +__STATIC_INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT) +{ + return pWWDT->MOD; +} + +/** + * @brief Clear WWDT interrupt status flags + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @param status : Or'ed value of status flag(s) that you want to clear, should be: + * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag + * - WWDT_WDMOD_WDINT: Clear watchdog warning flag + * @return None + */ +__STATIC_INLINE void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status) +{ + if (status & WWDT_WDMOD_WDTOF) { + pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK; + } + /* Interrupt flag is cleared by writing a 1 */ + if (status & WWDT_WDMOD_WDINT) { + pWWDT->MOD = (pWWDT->MOD & WWDT_WDMOD_BITMASK) | WWDT_WDMOD_WDINT; + } +} + +/** + * @brief Get the current value of WDT + * @param pWWDT : The base of WatchDog Timer peripheral on the chip + * @return current value of WDT + */ +__STATIC_INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT) +{ + return pWWDT->TV; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_5410X_H_ */ diff --git a/ports/lpc/chips/lpc_chip_5410x/src/adc_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/adc_5410x.c new file mode 100644 index 0000000000000..b46f7d26ad0a5 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/adc_5410x.c @@ -0,0 +1,129 @@ +/* + * @brief LPC5410X ADC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the ADC peripheral */ +void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags) +{ + /* Power up ADC and enable ADC base clock */ + Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_ADC0 | SYSCON_PDRUNCFG_PD_VDDA_ENA | SYSCON_PDRUNCFG_PD_VREFP); + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_ADC0); + + /* Disable ADC interrupts */ + pADC->INTEN = 0; + + /* Set ADC control options */ + pADC->CTRL = flags; +} + +/* Shutdown ADC */ +void Chip_ADC_DeInit(LPC_ADC_T *pADC) +{ + pADC->INTEN = 0; + pADC->CTRL = 0; + + /* Stop ADC clock and then power down ADC */ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_ADC0); + Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_ADC0 | SYSCON_PDRUNCFG_PD_VDDA_ENA | SYSCON_PDRUNCFG_PD_VREFP); +} + +/* Calibrate ADC for system clock frequency */ +uint32_t Chip_ADC_Calibration(LPC_ADC_T *pADC) +{ + volatile uint32_t i; + uint32_t sysclk_freq = Chip_Clock_GetSystemClockRate(); + + pADC->STARTUP = ADC_STARTUP_ENABLE; + for ( i = 0; i < 0x10; i++ ) {} + if ( !(pADC->STARTUP & ADC_STARTUP_ENABLE) ) { + return ERR_ADC_NO_POWER; + } + + /* If not in by-pass mode do the calibration */ + if ( (pADC->CALIBR & ADC_CALREQD) && !(pADC->CTRL & ADC_CR_BYPASS) ) { + uint32_t ctrl = pADC->CTRL & 0x7FFF; + uint32_t tmp = ctrl; + + /* Set ADC to SYNC mode */ + tmp &= ~ADC_CR_ASYNC_MODE; + + /* To be safe run calibration at 1MHz UM permits upto 30MHz */ + if (sysclk_freq > 1000000UL) { + pADC->CTRL = tmp | (((sysclk_freq / 1000000UL) - 1) & 0xFF); + } + + /* Calibration is needed, do it now. */ + pADC->CALIBR = ADC_CALIB; + i = 0xF0000; + while ( (pADC->CALIBR & ADC_CALIB) && --i ) {} + pADC->CTRL = ctrl; + return i ? LPC_OK : ERR_TIME_OUT; + } + + /* A dummy conversion cycle will be performed. */ + pADC->STARTUP = (pADC->STARTUP | ADC_STARTUP_INIT) & 0x03; + i = 0x7FFFF; + while ( (pADC->STARTUP & ADC_STARTUP_INIT) && --i ) {} + return i ? LPC_OK : ERR_TIME_OUT; +} + +/* Set ADC clock rate */ +void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate) +{ + uint32_t div; + + /* Get ADC clock source to determine base ADC rate. IN sychronous mode, + the ADC base clock comes from the system clock. In ASYNC mode, it + comes from the ASYNC ADC clock and this function doesn't work. */ + div = Chip_Clock_GetSystemClockRate() / rate; + if (div == 0) { + div = 1; + } + + Chip_ADC_SetDivider(pADC, (uint8_t) div - 1); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/chip_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/chip_5410x.c new file mode 100644 index 0000000000000..38d5c63ce81e3 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/chip_5410x.c @@ -0,0 +1,59 @@ +/* + * @brief LPC5410X Miscellaneous chip specific functions + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/* System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock; + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Update system core clock rate, should be called if the system has + a clock rate change */ +void SystemCoreClockUpdate(void) +{ + /* CPU core speed (main clock speed adjusted by system clock divider) */ + SystemCoreClock = Chip_Clock_GetSystemClockRate(); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/clock_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/clock_5410x.c new file mode 100644 index 0000000000000..2512498fed05f --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/clock_5410x.c @@ -0,0 +1,393 @@ +/* + * @brief LPC5410X clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Return asynchronous APB clock rate (no regard for divider) */ +static uint32_t Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv(void) +{ + CHIP_ASYNC_SYSCON_SRC_T src; + uint32_t clkRate; + + src = Chip_Clock_GetAsyncSysconClockSource(); + switch (src) { + case SYSCON_ASYNC_IRC: + clkRate = Chip_Clock_GetIntOscRate(); + break; + + case SYSCON_ASYNC_WDTOSC: + clkRate = Chip_Clock_GetWDTOSCRate(); + break; + + case SYSCON_ASYNC_MAINCLK: + clkRate = Chip_Clock_GetMainClockRate(); + break; + + case SYSCON_ASYNC_CLKIN: + clkRate = Chip_Clock_GetSystemPLLInClockRate(); + break; + + case SYSCON_ASYNC_SYSPLLOUT: + clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); + break; + + default: + clkRate = 0; + break; + } + + return clkRate; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Return main A clock rate */ +uint32_t Chip_Clock_GetMain_A_ClockRate(void) +{ + uint32_t clkRate = 0; + + switch (Chip_Clock_GetMain_A_ClockSource()) { + case SYSCON_MAIN_A_CLKSRC_IRC: + clkRate = Chip_Clock_GetIntOscRate(); + break; + + case SYSCON_MAIN_A_CLKSRCA_CLKIN: + clkRate = Chip_Clock_GetExtClockInRate(); + break; + + case SYSCON_MAIN_A_CLKSRCA_WDTOSC: + clkRate = Chip_Clock_GetWDTOSCRate(); + break; + + default: + clkRate = 0; + break; + } + + return clkRate; +} + +/* Return main B clock rate */ +uint32_t Chip_Clock_GetMain_B_ClockRate(void) +{ + uint32_t clkRate = 0; + + switch (Chip_Clock_GetMain_B_ClockSource()) { + case SYSCON_MAIN_B_CLKSRC_MAINCLKSELA: + clkRate = Chip_Clock_GetMain_A_ClockRate(); + break; + + case SYSCON_MAIN_B_CLKSRC_SYSPLLIN: + clkRate = Chip_Clock_GetSystemPLLInClockRate(); + break; + + case SYSCON_MAIN_B_CLKSRC_SYSPLLOUT: + clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); + break; + + case SYSCON_MAIN_B_CLKSRC_RTC: + clkRate = Chip_Clock_GetRTCOscRate(); + break; + } + + return clkRate; +} + +/* Set CLKOUT clock source and divider */ +void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div) +{ + uint32_t srcClk = (uint32_t) src; + + /* Use a clock A source? */ + if (src >= SYSCON_CLKOUTSRCA_OUTPUT) { + /* Not using a CLKOUT A source */ + LPC_SYSCON->CLKOUTSELB = srcClk - SYSCON_CLKOUTSRCA_OUTPUT; + } + else { + /* Using a clock A source, select A and then switch B to A */ + LPC_SYSCON->CLKOUTSELA = srcClk; + LPC_SYSCON->CLKOUTSELB = 0; + } + + LPC_SYSCON->CLKOUTDIV = div; +} + +/* Enable a system or peripheral clock */ +void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk) +{ + uint32_t clkEnab = (uint32_t) clk; + + if (clkEnab >= 128) { + clkEnab = clkEnab - 128; + + LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << clkEnab); + } + else if (clkEnab >= 32) { + LPC_SYSCON->AHBCLKCTRLSET[1] = (1 << (clkEnab - 32)); + } + else { + LPC_SYSCON->AHBCLKCTRLSET[0] = (1 << clkEnab); + } +} + +/* Disable a system or peripheral clock */ +void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk) +{ + uint32_t clkEnab = (uint32_t) clk; + + if (clkEnab >= 128) { + clkEnab = clkEnab - 128; + + LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1 << clkEnab); + } + else if (clkEnab >= 32) { + LPC_SYSCON->AHBCLKCTRLCLR[1] = (1 << (clkEnab - 32)); + } + else { + LPC_SYSCON->AHBCLKCTRLCLR[0] = (1 << clkEnab); + } +} + +/* Returns the system tick rate as used with the system tick divider */ +uint32_t Chip_Clock_GetSysTickClockRate(void) +{ + uint32_t sysRate, div; + + div = LPC_SYSCON->SYSTICKCLKDIV; + + /* If divider is 0, the system tick clock is disabled */ + if (div == 0) { + sysRate = 0; + } + else { + sysRate = Chip_Clock_GetSystemClockRate() / LPC_SYSCON->SYSTICKCLKDIV; + } + + return sysRate; +} + +/* Return ADC clock rate */ +uint32_t Chip_Clock_GetADCClockRate(void) +{ + uint32_t div, clkRate = 0; + + div = Chip_Clock_GetADCClockDiv(); + + /* ADC clock only enabled if div>0 */ + if (div > 0) { + switch (Chip_Clock_GetADCClockSource()) { + case SYSCON_ADCCLKSELSRC_MAINCLK: + clkRate = Chip_Clock_GetMainClockRate(); + break; + + case SYSCON_ADCCLKSELSRC_SYSPLLOUT: + clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); + break; + + case SYSCON_ADCCLKSELSRC_IRC: + clkRate = Chip_Clock_GetIntOscRate(); + break; + } + + clkRate = clkRate / div; + } + + return clkRate; +} + +/* Set asynchronous APB clock source */ +void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src) +{ + uint32_t clkSrc = (uint32_t) src; + + if (src >= SYSCON_ASYNC_MAINCLK) { + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = (clkSrc - 4); + } + else { + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA = clkSrc; + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = 3; + } +} + +/* Get asynchronous APB clock source */ +CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void) +{ + uint32_t clkSrc; + + if (LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB == 3) { + clkSrc = LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA; + } + else { + clkSrc = 4 + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB; + } + + return (CHIP_ASYNC_SYSCON_SRC_T) clkSrc; +} + +/* Return asynchronous APB clock rate */ +uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void) +{ + uint32_t clkRate, div; + + clkRate = Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv(); + div = LPC_ASYNC_SYSCON->ASYNCCLKDIV; + if (div == 0) { + /* Clock is disabled */ + return 0; + } + + return clkRate / div; +} + +/* Set main system clock source */ +void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src) +{ + uint32_t clkSrc = (uint32_t) src; + + if (clkSrc >= 4) { + /* Main B source only, not using main A */ + Chip_Clock_SetMain_B_ClockSource((CHIP_SYSCON_MAIN_B_CLKSRC_T) (clkSrc - 4)); + } + else { + /* Select main A clock source and set main B source to use main A */ + Chip_Clock_SetMain_A_ClockSource((CHIP_SYSCON_MAIN_A_CLKSRC_T) clkSrc); + Chip_Clock_SetMain_B_ClockSource(SYSCON_MAIN_B_CLKSRC_MAINCLKSELA); + } +} + +/* Returns the main clock source */ +CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void) +{ + CHIP_SYSCON_MAIN_B_CLKSRC_T srcB; + uint32_t clkSrc; + + /* Get main B clock source */ + srcB = Chip_Clock_GetMain_B_ClockSource(); + if (srcB == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) { + /* Using source A, so return source A */ + clkSrc = (uint32_t) Chip_Clock_GetMain_A_ClockSource(); + } + else { + /* Using source B */ + clkSrc = 4 + (uint32_t) srcB; + } + + return (CHIP_SYSCON_MAINCLKSRC_T) clkSrc; +} + +/* Return main clock rate */ +uint32_t Chip_Clock_GetMainClockRate(void) +{ + uint32_t clkRate; + + if (Chip_Clock_GetMain_B_ClockSource() == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) { + /* Return main A clock rate */ + clkRate = Chip_Clock_GetMain_A_ClockRate(); + } + else { + /* Return main B clock rate */ + clkRate = Chip_Clock_GetMain_B_ClockRate(); + } + + return clkRate; +} + +/* Return system clock rate */ +uint32_t Chip_Clock_GetSystemClockRate(void) +{ + /* No point in checking for divide by 0 */ + return Chip_Clock_GetMainClockRate() / LPC_SYSCON->AHBCLKDIV; +} + +/* Get UART base rate */ +uint32_t Chip_Clock_GetUARTBaseClockRate(void) +{ + uint64_t inclk; + + /* Get clock rate into FRG */ + inclk = (uint64_t) Chip_Clock_GetAsyncSyscon_ClockRate(); + + if (inclk != 0) { + uint32_t mult, divmult; + + divmult = LPC_ASYNC_SYSCON->FRGCTRL & 0xFF; + if ((divmult & 0xFF) == 0xFF) { + /* Fractional part is enabled, get multiplier */ + mult = (divmult >> 8) & 0xFF; + + /* Get fractional error */ + inclk = (inclk * 256) / (uint64_t) (256 + mult); + } + } + + return (uint32_t) inclk; +} + +/* Set UART base rate */ +uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate) +{ + uint32_t div, inclk, err; + uint64_t uart_fra_multiplier; + + /* Input clock into FRG block is the main system cloock */ + inclk = Chip_Clock_GetAsyncSyscon_ClockRate(); + + /* Get integer divider for coarse rate */ + div = inclk / rate; + if (div == 0) { + div = 1; + } + + /* Enable FRG clock */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FRG); + + err = inclk - (rate * div); + uart_fra_multiplier = (((uint64_t) err + (uint64_t) rate) * 256) / (uint64_t) (rate * div); + + /* Enable fractional divider and set multiplier */ + LPC_ASYNC_SYSCON->FRGCTRL = 0xFF | (uart_fra_multiplier << 8); + + return Chip_Clock_GetUARTBaseClockRate(); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/crc_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/crc_5410x.c new file mode 100644 index 0000000000000..a4305a481a0ae --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/crc_5410x.c @@ -0,0 +1,118 @@ +/* + * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize CRC engine */ +void Chip_CRC_Init(void) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_CRC); + Chip_SYSCON_PeriphReset(RESET_CRC); +} + +/* De-initialize CRC engine */ +void Chip_CRC_Deinit(void) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_CRC); +} + +/* Sets up the CRC engine with defaults based on the polynomial to be used */ +void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly) +{ + switch (poly) { + case CRC_POLY_CRC16: + Chip_CRC_UseCRC16(); + break; + + case CRC_POLY_CRC32: + Chip_CRC_UseCRC32(); + break; + + case CRC_POLY_CCITT: + default: + Chip_CRC_UseCCITT(); + break; + } +} + +/* configure CRC engine and compute CCITT checksum from 8-bit data */ +uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes) +{ + Chip_CRC_UseCCITT(); + while (bytes > 0) { + Chip_CRC_Write8(*data); + data++; + bytes--; + } + + return Chip_CRC_Sum(); +} + +/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */ +uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords) +{ + Chip_CRC_UseCRC16(); + while (hwords > 0) { + Chip_CRC_Write16(*data); + data++; + hwords--; + } + + return Chip_CRC_Sum(); +} + +/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */ +uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words) +{ + Chip_CRC_UseCRC32(); + while (words > 0) { + Chip_CRC_Write32(*data); + data++; + words--; + } + + return Chip_CRC_Sum(); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/dma_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/dma_5410x.c new file mode 100644 index 0000000000000..3a58f948e51f0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/dma_5410x.c @@ -0,0 +1,67 @@ +/* + * @brief DMA driver declarations and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase() + function if a DMA SRAM table is needed. This table is correctly aligned for + the DMA controller. */ + +/* Set alignement to 512 bytes */ +ALIGN(512) DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL]; + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Sets up a DMA channel with the passed DMA transfer descriptor */ +bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc) +{ + bool good = false; + DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) pDMA->SRAMBASE; + + if ((Chip_DMA_GetActiveChannels(pDMA) & (1 << ch)) == 0) { + /* Channel is not active, so update the descriptor */ + pDesc[ch] = *desc; + + good = true; + } + + return good; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/fifo_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/fifo_5410x.c new file mode 100644 index 0000000000000..a9e4702af4e81 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/fifo_5410x.c @@ -0,0 +1,306 @@ +/* + * @brief LPC5410X System FIFO chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/** SPI FIFO read FIFO statuses */ +#define LPC_SPIRXFIFO_STAT_SSEL0N (1 << 16) /*!< Slave select for receive on SSEL0 (active low) */ +#define LPC_SPIRXFIFO_STAT_SSEL1N (1 << 17) /*!< Slave select for receive on SSEL1 (active low) */ +#define LPC_SPIRXFIFO_STAT_SSEL2N (1 << 18) /*!< Slave select for receive on SSEL2 (active low) */ +#define LPC_SPIRXFIFO_STAT_SSEL3N (1 << 19) /*!< Slave select for receive on SSEL3 (active low) */ +#define LPC_SPIRXFIFO_STAT_SOT (1 << 20) /*!< This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted */ + +/** SPI FIFO write FIFO control */ +#define LPC_SPITXFIFO_CTRL_SSEL0N (1 << 16) /*!< Master assert for receive on SSEL0 (active low) */ +#define LPC_SPITXFIFO_CTRL_SSEL1N (1 << 17) /*!< Master assert for receive on SSEL1 (active low) */ +#define LPC_SPITXFIFO_CTRL_SSEL2N (1 << 18) /*!< Master assert for receive on SSEL2 (active low) */ +#define LPC_SPITXFIFO_CTRL_SSEL3N (1 << 19) /*!< Master assert for receive on SSEL3 (active low) */ +#define LPC_SPITXFIFO_CTRL_EOT (1 << 20) /*!< End of Transfer. The asserted SSEL will be deasserted at the end of a transfer */ +#define LPC_SPITXFIFO_CTRL_EOF (1 << 21) /*!< End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register */ +#define LPC_SPITXFIFO_CTRL_RXIGNORE (1 << 22) /*!< Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver */ +#define LPC_SPITXFIFO_CTRL_LEN(n) ((n) << 24) /*!< Data Length. Specifies the data length from 1 to 16 bits ((n-1) encoded) */ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the system FIFO */ +void Chip_FIFO_Init(LPC_FIFO_T *pFIFO) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FIFO); + Chip_SYSCON_PeriphReset(RESET_FIFO); +} + +/* Deinitializes the system FIFO */ +void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_FIFO); +} + +/* Get the FIFO space available for the USART/SPI direction */ +uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) +{ + uint32_t pcfg; + + if (periphId == FIFO_USART) { + pcfg = pFIFO->common.FIFOCTLUSART; + } + else { + pcfg = pFIFO->common.FIFOCTLSPI; + } + + if (dir == FIFO_RX) { + pcfg = pcfg >> 16; + } + else { + pcfg = pcfg >> 24; + } + + return pcfg & 0xFF; +} + +/* Pause a peripheral FIFO */ +void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) +{ + if (periphId == FIFO_USART) { + if (dir == FIFO_RX) { + pFIFO->common.FIFOCTLUSART |= (1 << 0); + } + else { + pFIFO->common.FIFOCTLUSART |= (1 << 8); + } + } + else { + if (dir == FIFO_RX) { + pFIFO->common.FIFOCTLSPI |= (1 << 0); + } + else { + pFIFO->common.FIFOCTLSPI |= (1 << 8); + } + } +} + +/* Unpause a peripheral FIFO */ +void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) +{ + if (periphId == FIFO_USART) { + if (dir == FIFO_RX) { + pFIFO->common.FIFOCTLUSART &= ~(1 << 0); + } + else { + pFIFO->common.FIFOCTLUSART &= ~(1 << 8); + } + } + else { + if (dir == FIFO_RX) { + pFIFO->common.FIFOCTLSPI &= ~(1 << 0); + } + else { + pFIFO->common.FIFOCTLSPI &= ~(1 << 8); + } + } +} + +/* Configure a peripheral's FIFO sizes */ +void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes) +{ + int maxP, i; + uint32_t upDateMask; + volatile uint32_t *updateReg, *pFifoSizes, *pFifoPause; + + /* Pause FIFOs */ + Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_RX); + Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_TX); + + /* Maximum peripheral FIFOs supported */ + if (periphId == FIFO_USART) { + maxP = LPC_FIFO_USART_MAX; + updateReg = &pFIFO->common.FIFOUPDATEUSART; + upDateMask = 0xF | (0xF << 16); + pFifoSizes = &pFIFO->common.FIFOCFGUSART[0]; + pFifoPause = &pFIFO->common.FIFOCTLUSART; + } + else { + maxP = LPC_FIFO_SPI_MAX; + updateReg = &pFIFO->common.FIFOUPDATESPI; + upDateMask = 0x3 | (0x3 << 16); + pFifoSizes = &pFIFO->common.FIFOCFGSPI[0]; + pFifoPause = &pFIFO->common.FIFOCTLSPI; + } + + /* Wait for FIFO pause */ + while ((*pFifoPause & ((1 << 0) | (1 << 8))) != ((1 << 0) | (1 << 8))) {} + + /* Update FIFO sizes */ + for (i = 0; i < maxP; i++) { + pFifoSizes[i] = ((uint32_t) (pSizes->fifoRXSize[i]) << 0) | + ((uint32_t) (pSizes->fifoTXSize[i]) << 8); + } + + /* Update all peripheral FIFO sizes */ + *updateReg = upDateMask; +} + +/* Configure the USART system FIFO */ +void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg) +{ + pFIFO->usart[usartIndex].CFG = + (pUSARTCfg->noTimeoutContWrite << 4) | + (pUSARTCfg->noTimeoutContEmpty << 5) | + (pUSARTCfg->timeoutBase << 8) | + (pUSARTCfg->timeoutValue << 12) | + (pUSARTCfg->rxThreshold << 16) | + (pUSARTCfg->txThreshold << 24); +} + +/* Write data to a system FIFO (non-blocking) */ +int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData) +{ + int datumWritten, sz16; + uint8_t *p8 = (uint8_t *) buff; + uint16_t *p16 = (uint16_t *) buff; + + /* Get configured FIFO size to determine write size, limit to buffer size */ + sz16 = (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF; + if (sz16 > numData) { + sz16 = numData; + } + datumWritten = sz16; + + /* Write from buffer */ + while (sz16 > 0) { + if (sz8) { + pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p8; + p8++; + } + else { + pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p16; + p16++; + } + + sz16--; + } + + return datumWritten; +} + +/* Read data from a system FIFO (non-blocking) */ +int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData) +{ + int datumRead, sz16; + uint8_t *p8 = (uint8_t *) buff; + uint16_t *p16 = (uint16_t *) buff; + + /* Get configured FIFO size to determine read size, limit to buffer size */ + sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; + if (sz16 > numData) { + sz16 = numData; + } + datumRead = sz16; + + /* Read into buffer */ + while (sz16 > 0) { + if (sz8) { + *p8 = (uint8_t) (pFIFO->usart[usartIndex].RXDAT & 0xFF); + p8++; + } + else { + *p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDAT & 0x1FF); + p16++; + } + + sz16--; + } + + return datumRead; +} + +/* Read data from a system FIFO with status (non-blocking) */ +int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData) +{ + int datumRead, sz16; + uint16_t *p16 = (uint16_t *) buff; + + /* Get configured FIFO size to determine read size, limit to buffer size */ + sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; + if (sz16 > numData) { + sz16 = numData; + } + datumRead = sz16; + + /* Read into buffer */ + while (sz16 > 0) { + *p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDATSTAT & 0xFFFF); + p16++; + sz16--; + } + + return datumRead; +} + +#if 0 /* Sorry, not yet support */ +/* Configure the USART system FIFO */ +void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg) +{ + pFIFO->spi[spiIndex].CFG = + (pSPICfg->noTimeoutContWrite << 4) | + (pSPICfg->noTimeoutContEmpty << 5) | + (pSPICfg->timeoutBase << 6) | + (pSPICfg->timeoutValue << 12) | + (pSPICfg->rxThreshold << 16) | + (pSPICfg->txThreshold << 24); +} + +/* Start a data transfer (non-blocking) */ +void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData) +{ + pSetupData->start = 1; + Chip_FIFOSPI_Transfer(pFIFO, pSetupData); +} + +/* Feed a SPI data transfer (non-blocking) */ +void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData) +{ + // FIXME - not yet ready +} + +#endif diff --git a/ports/lpc/chips/lpc_chip_5410x/src/fpu_init.c b/ports/lpc/chips/lpc_chip_5410x/src/fpu_init.c new file mode 100644 index 0000000000000..2ba51f41703b0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/fpu_init.c @@ -0,0 +1,96 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#if defined(CORE_M4) + +#include "cmsis.h" +#include "stdint.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define LPC_CPACR 0xE000ED88 + +#define SCB_MVFR0 0xE000EF40 +#define SCB_MVFR0_RESET 0x10110021 + +#define SCB_MVFR1 0xE000EF44 +#define SCB_MVFR1_RESET 0x11000011 + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Early initialization of the FPU */ +void fpuInit(void) +{ +#if __FPU_PRESENT != 0 + // from arm trm manual: + // ; CPACR is located at address 0xE000ED88 + // LDR.W R0, =0xE000ED88 + // ; Read CPACR + // LDR R1, [R0] + // ; Set bits 20-23 to enable CP10 and CP11 coprocessors + // ORR R1, R1, #(0xF << 20) + // ; Write back the modified value to the CPACR + // STR R1, [R0] + + volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; + volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; + volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; + volatile uint32_t Cpacr; + volatile uint32_t Mvfr0; + volatile uint32_t Mvfr1; + char vfpPresent = 0; + + Mvfr0 = *regMvfr0; + Mvfr1 = *regMvfr1; + + vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); + + if (vfpPresent) { + Cpacr = *regCpacr; + Cpacr |= (0xF << 20); + *regCpacr = Cpacr; // enable CP10 and CP11 for full access + } +#endif /* __FPU_PRESENT != 0 */ +} + +#endif /* defined(CORE_M4 */ diff --git a/ports/lpc/chips/lpc_chip_5410x/src/gpio_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/gpio_5410x.c new file mode 100644 index 0000000000000..c97d365e04500 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/gpio_5410x.c @@ -0,0 +1,108 @@ +/* + * @brief LPC5410X GPIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* GPIO initilisation function */ +void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0); + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1); + Chip_SYSCON_PeriphReset(RESET_GPIO0); + Chip_SYSCON_PeriphReset(RESET_GPIO1); +} + +/* GPIO deinitialisation function */ +void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO0); + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO1); +} + +/* Set GPIO direction for a single GPIO pin */ +void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting) +{ + if (setting) { + pGPIO->DIR[port] |= 1UL << pin; + } + else { + pGPIO->DIR[port] &= ~(1UL << pin); + } +} + +/* Set GPIO direction for a single GPIO pin */ +void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output) +{ + if (output) { + Chip_GPIO_SetPinDIROutput(pGPIO, port, pin); + } + else { + Chip_GPIO_SetPinDIRInput(pGPIO, port, pin); + } +} + +/* Set Direction for a GPIO port */ +void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out) +{ + if (out) { + pGPIO->DIR[portNum] |= bitValue; + } + else { + pGPIO->DIR[portNum] &= ~bitValue; + } +} + +/* Set GPIO direction for a all selected GPIO pins to an input or output */ +void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet) +{ + if (outSet) { + Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask); + } + else { + Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask); + } +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/gpiogroup_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/gpiogroup_5410x.c new file mode 100644 index 0000000000000..8fa7bb45d6aad --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/gpiogroup_5410x.c @@ -0,0 +1,48 @@ +/* + * @brief LPC5410x GPIO group driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ diff --git a/ports/lpc/chips/lpc_chip_5410x/src/i2cm_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/i2cm_5410x.c new file mode 100644 index 0000000000000..8b08c44fd2731 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/i2cm_5410x.c @@ -0,0 +1,226 @@ +/* + * @brief LPC5410x I2C master driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Sets HIGH and LOW duty cycle registers */ +void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL) +{ + /* Limit to usable range of timing values */ + if (sclH < 2) { + sclH = 2; + } + else if (sclH > 9) { + sclH = 9; + } + if (sclL < 2) { + sclL = 2; + } + else if (sclL > 9) { + sclL = 9; + } + + pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07); +} + +/* Set up bus speed for LPC_I2C interface */ +void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed) +{ + uint32_t scl; + + scl = Chip_Clock_GetAsyncSyscon_ClockRate() / (Chip_I2C_GetClockDiv(pI2C) * busSpeed); + Chip_I2CM_SetDutyCycle(pI2C, (scl >> 1), (scl - (scl >> 1))); +} + +/* Master transfer state change handler handler */ +uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + uint32_t status = Chip_I2CM_GetStatus(pI2C); + + if (status & I2C_STAT_MSTRARBLOSS) { + /* Master Lost Arbitration */ + /* Set transfer status as Arbitration Lost */ + xfer->status = I2CM_STATUS_ARBLOST; + /* Clear Status Flags */ + Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS); + /* Master continue */ + if (status & I2C_STAT_MSTPENDING) { + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; + } + } + else if (status & I2C_STAT_MSTSTSTPERR) { + /* Master Start Stop Error */ + /* Set transfer status as Bus Error */ + xfer->status = I2CM_STATUS_BUS_ERROR; + /* Clear Status Flags */ + Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTSTSTPERR); + + /* Master continue */ + if (status & I2C_STAT_MSTPENDING) { + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; + } + } + else if (status & I2C_STAT_MSTPENDING) { + /* Master is Pending */ + /* Branch based on Master State Code */ + switch (Chip_I2CM_GetMasterState(pI2C)) { + case I2C_STAT_MSTCODE_IDLE: /* Master idle */ + /* Can transition to idle between transmit and receive states */ + if (xfer->txSz) { + /* Start transmit state */ + Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1)); + pI2C->MSTCTL = I2C_MSTCTL_MSTSTART; + } + else if (xfer->rxSz) { + /* Start receive state with start ot repeat start */ + Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | 0x1); + pI2C->MSTCTL = I2C_MSTCTL_MSTSTART; + } + else { + /* No data to send, done */ + xfer->status = I2CM_STATUS_OK; + } + break; + + case I2C_STAT_MSTCODE_RXREADY: /* Receive data is available */ + /* Read Data up until the buffer size */ + if (xfer->rxSz) { + *xfer->rxBuff = pI2C->MSTDAT; + xfer->rxBuff++; + xfer->rxSz--; + } + + if (xfer->rxSz) { + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; + } + else { + /* Last byte to receive, send stop after byte received */ + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE | I2C_MSTCTL_MSTSTOP; + } + break; + + case I2C_STAT_MSTCODE_TXREADY: /* Master Transmit available */ + if (xfer->txSz) { + /* If Tx data available transmit data and continue */ + pI2C->MSTDAT = (uint32_t) *xfer->txBuff; + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; + xfer->txBuff++; + xfer->txSz--; + } + else if (xfer->rxSz == 0) { + pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP; + } + else { + /* Start receive state with start ot repeat start */ + Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | 0x1); + pI2C->MSTCTL = I2C_MSTCTL_MSTSTART; + } + break; + + case I2C_STAT_MSTCODE_NACKADR: /* Slave address was NACK'ed */ + /* Set transfer status as NACK on address */ + xfer->status = I2CM_STATUS_NAK_ADR; + pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP; + break; + + case I2C_STAT_MSTCODE_NACKDAT: /* Slave data was NACK'ed */ + /* Set transfer status as NACK on data */ + xfer->status = I2CM_STATUS_NAK_DAT; + pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP; + break; + + default: + /* Illegal I2C master state machine case. This should never happen. + Try to advance state machine by continuing. */ + xfer->status = I2CM_STATUS_ERROR; + pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; + break; + } + } + else { + /* Unsupported operation. This may be a call to the master handler + for a wrong interrupt type. This handler should only be called when a + master arbitration loss, master start/stop error, or master pending status + occurs. */ + xfer->status = I2CM_STATUS_ERROR; + } + + return xfer->status != I2CM_STATUS_BUSY; +} + +/* Transmit and Receive data in master mode */ +void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + /* set the transfer status as busy */ + xfer->status = I2CM_STATUS_BUSY; + + /* Reset master state machine */ + Chip_I2CM_Disable(pI2C); + Chip_I2CM_Enable(pI2C); + + /* Clear controller state. */ + Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); + + /* Handle transfer via initial call to handler */ + Chip_I2CM_XferHandler(pI2C, xfer); +} + +/* Transmit and Receive data in master mode */ +uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) +{ + /* start transfer */ + Chip_I2CM_Xfer(pI2C, xfer); + + while (xfer->status == I2CM_STATUS_BUSY) { + /* wait for status change interrupt */ + while (!Chip_I2CM_IsMasterPending(pI2C)) {} + /* call state change handler */ + Chip_I2CM_XferHandler(pI2C, xfer); + } + + return xfer->status == I2CM_STATUS_OK; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/i2cs_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/i2cs_5410x.c new file mode 100644 index 0000000000000..5bbe39cdd06a9 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/i2cs_5410x.c @@ -0,0 +1,104 @@ +/* + * @brief LPC5410x I2C slave driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Slave transfer state change handler */ +uint32_t Chip_I2CS_XferHandler(LPC_I2C_T *pI2C, const I2CS_XFER_T *xfers) +{ + uint32_t done = 0, xferDone = 0; + + uint8_t data; + uint32_t state; + + /* Transfer complete? */ + if ((Chip_I2C_GetPendingInt(pI2C) & I2C_INTENSET_SLVDESEL) != 0) { + Chip_I2CS_ClearStatus(pI2C, I2C_STAT_SLVDESEL); + xfers->slaveDone(); + xferDone = 1; + } + else { + /* Determine the current I2C slave state */ + state = Chip_I2CS_GetSlaveState(pI2C); + + switch (state) { + case I2C_STAT_SLVCODE_ADDR: /* Slave address received */ + /* Get slave address that needs servicing */ + data = Chip_I2CS_GetSlaveAddr(pI2C, Chip_I2CS_GetSlaveMatchIndex(pI2C)); + + /* Call address callback */ + xfers->slaveStart(data); + break; + + case I2C_STAT_SLVCODE_RX: /* Data byte received, not used with DMA */ + /* Get received data */ + data = Chip_I2CS_ReadByte(pI2C); + done = xfers->slaveRecv(data); + break; + + case I2C_STAT_SLVCODE_TX: /* Get byte that needs to be sent, or start DMA */ + /* Get data to send */ + done = xfers->slaveSend(&data); + if (!((done == I2C_SLVCTL_SLVNACK) || (done == I2C_SLVCTL_SLVDMA))) { + Chip_I2CS_WriteByte(pI2C, data); + } + break; + } + + if (done == I2C_SLVCTL_SLVNACK) { + Chip_I2CS_SlaveNACK(pI2C); + } + else if (done == I2C_SLVCTL_SLVDMA) { + Chip_I2CS_SlaveEnableDMA(pI2C); + } + else { + Chip_I2CS_SlaveContinue(pI2C); + } + } + + return xferDone; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/iap.c b/ports/lpc/chips/lpc_chip_5410x/src/iap.c new file mode 100644 index 0000000000000..76f72a2f59b63 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/iap.c @@ -0,0 +1,175 @@ +/* + * @brief Common FLASH support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Prepare sector for write operation */ +uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_PREWRRITE_CMD; + command[1] = strSector; + command[2] = endSector; + iap_entry(command, result); + + return result[0]; +} + +/* Copy RAM to flash */ +uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_WRISECTOR_CMD; + command[1] = dstAdd; + command[2] = (uint32_t) srcAdd; + command[3] = byteswrt; + command[4] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} + +/* Erase sector */ +uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_ERSSECTOR_CMD; + command[1] = strSector; + command[2] = endSector; + command[3] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} + +/* Blank check sector */ +uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_BLANK_CHECK_SECTOR_CMD; + command[1] = strSector; + command[2] = endSector; + iap_entry(command, result); + + return result[0]; +} + +/* Read part identification number */ +uint32_t Chip_IAP_ReadPID() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_REPID_CMD; + iap_entry(command, result); + + return result[1]; +} + +/* Read boot code version number */ +uint8_t Chip_IAP_ReadBootCode() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_READ_BOOT_CODE_CMD; + iap_entry(command, result); + + return result[0]; +} + +/* IAP compare */ +uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_COMPARE_CMD; + command[1] = dstAdd; + command[2] = srcAdd; + command[3] = bytescmp; + iap_entry(command, result); + + return result[0]; +} + +/* Reinvoke ISP */ +uint8_t Chip_IAP_ReinvokeISP() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_REINVOKE_ISP_CMD; + iap_entry(command, result); + + return result[0]; +} + +/* Read the unique ID */ +uint32_t Chip_IAP_ReadUID() +{ + uint32_t command[5], result[4]; + + command[0] = IAP_READ_UID_CMD; + iap_entry(command, result); + + return result[1]; +} + +/* Erase page */ +uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage) +{ + uint32_t command[5], result[4]; + + command[0] = IAP_ERASE_PAGE_CMD; + command[1] = strPage; + command[2] = endPage; + command[3] = SystemCoreClock / 1000; + iap_entry(command, result); + + return result[0]; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/iocon_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/iocon_5410x.c new file mode 100644 index 0000000000000..865279a788886 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/iocon_5410x.c @@ -0,0 +1,58 @@ +/* + * @brief LPC5410X IOCON driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set all I/O Control pin muxing */ +void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength) +{ + uint32_t ix; + + for (ix = 0; ix < arrayLength; ix++ ) { + Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].port, pinArray[ix].pin, pinArray[ix].modefunc); + } +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/pinint_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/pinint_5410x.c new file mode 100644 index 0000000000000..8659472884f2b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/pinint_5410x.c @@ -0,0 +1,83 @@ +/* + * @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set source for pattern match engine */ +void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT, + Chip_PININT_SELECT_T channelNum, + Chip_PININT_BITSLICE_T sliceNum) +{ + uint32_t pmsrc_reg; + + /* Source source for pattern matching */ + pmsrc_reg = pPININT->PMSRC & ~(PININT_SRC_BITSOURCE_MASK << (PININT_SRC_BITSOURCE_START + (sliceNum * 3))); + pPININT->PMSRC = pmsrc_reg | (channelNum << (PININT_SRC_BITSOURCE_START + (sliceNum * 3))); +} + +/* Configure Pattern match engine */ +void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum, + Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point) +{ + uint32_t pmcfg_reg, idx = PININT_SRC_BITCFG_START + (sliceNum * 3); + + /* Configure bit slice configuration */ + pmcfg_reg = pPININT->PMCFG; + pmcfg_reg = (pmcfg_reg & ~(PININT_SRC_BITCFG_MASK << idx)) | (slice_cfg << idx); + + /* If end point is true, enable the bits */ + if (sliceNum != PININTBITSLICE7) { + if (end_point) { + pmcfg_reg |= (0x1 << sliceNum); + } + else { + pmcfg_reg &= ~(0x1 << sliceNum); + } + } + + pPININT->PMCFG = pmcfg_reg; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/pll_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/pll_5410x.c new file mode 100644 index 0000000000000..052992c6c95b0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/pll_5410x.c @@ -0,0 +1,931 @@ +/* + * @brief LPC5410X PLL driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define NVALMAX (0x100) +#define PVALMAX (0x20) +#define MVALMAX (0x8000) + +/* SYS PLL related bit fields */ +#define SYS_PLL_SELR(d) (((d) & 0xf) << 0) /*!< Bandwidth select R value */ +#define SYS_PLL_SELI(d) (((d) & 0x3f) << 4) /*!< Bandwidth select I value */ +#define SYS_PLL_SELP(d) (((d) & 0x1f) << 10) /*!< Bandwidth select P value */ +#define SYS_PLL_BYPASS (1 << 15) /*!< Enable PLL bypass */ +#define SYS_PLL_BYPASSCCODIV2 (1 << 16) /*!< Enable bypass of extra divider by 2 */ +#define SYS_PLL_UPLIMOFF (1 << 17) /*!< Enable spread spectrum/fractional mode */ +#define SYS_PLL_BANDSEL (1 << 18) /*!< Enable MDEC control */ +#define SYS_PLL_DIRECTI (1 << 19) /*!< PLL0 direct input enable */ +#define SYS_PLL_DIRECTO (1 << 20) /*!< PLL0 direct output enable */ + +// #define FRAC_BITS_SELI (8) // For retaining fractions in divisions +#define PLL_SSCG0_MDEC_VAL_P (0) // MDEC is in bits 16 downto 0 +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) // NDEC is in bits 9 downto 0 +#define PLL_NDEC_VAL_P (0) // NDEC is in bits 9:0 +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0) // PDEC is in bits 6:0 +#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (75000000) +#define PLL_MAX_CCO_FREQ_MHZ (150000000) +#define PLL_LOWER_IN_LIMIT (4000) /*!< Minimum PLL input rate */ +#define PLL_MIN_IN_SSMODE (2000000) +#define PLL_MAX_IN_SSMODE (4000000) + +// Middle of the range values for spread-spectrum +#define PLL_SSCG_MF_FREQ_VALUE 4 +#define PLL_SSCG_MC_COMP_VALUE 2 +#define PLL_SSCG_MR_DEPTH_VALUE 4 +#define PLL_SSCG_DITHER_VALUE 0 + +// pll SYSPLLCTRL Bits +#define SYSCON_SYSPLLCTRL_SELR_P 0 +#define SYSCON_SYSPLLCTRL_SELR_M (0xFUL << SYSCON_SYSPLLCTRL_SELR_P) +#define SYSCON_SYSPLLCTRL_SELI_P 4 +#define SYSCON_SYSPLLCTRL_SELI_M (0x3FUL << SYSCON_SYSPLLCTRL_SELI_P) +#define SYSCON_SYSPLLCTRL_SELP_P 10 +#define SYSCON_SYSPLLCTRL_SELP_M (0x1FUL << SYSCON_SYSPLLCTRL_SELP_P) +#define SYSCON_SYSPLLCTRL_BYPASS_P 15 // sys_pll150_ctrl +#define SYSCON_SYSPLLCTRL_BYPASS (1UL << SYSCON_SYSPLLCTRL_BYPASS_P) +#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P 16 +#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2 (1UL << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_P 17 +#define SYSCON_SYSPLLCTRL_UPLIMOFF (1UL << SYSCON_SYSPLLCTRL_UPLIMOFF_P) +#define SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P 18 +#define SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N (1UL << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) +#define SYSCON_SYSPLLCTRL_DIRECTI_P 19 +#define SYSCON_SYSPLLCTRL_DIRECTI (1UL << SYSCON_SYSPLLCTRL_DIRECTI_P) +#define SYSCON_SYSPLLCTRL_DIRECTO_P 20 +#define SYSCON_SYSPLLCTRL_DIRECTO (1UL << SYSCON_SYSPLLCTRL_DIRECTO_P) + +#define SYSCON_SYSPLLSTAT_LOCK_P 0 +#define SYSCON_SYSPLLSTAT_LOCK (1UL << SYSCON_SYSPLLSTAT_LOCK_P) + +#define PLL_CTRL_BYPASS_P 15 // sys_pll150_ctrl +#define PLL_CTRL_BYPASS_FBDIV2_P 16 +#define PLL_CTRL_UPLIMOFF_P 17 +#define PLL_CTRL_BANDSEL_SSCGREG_N_P 18 +#define PLL_CTRL_DIRECTI_P 19 +#define PLL_CTRL_DIRECTO_P 20 + +#define PLL_CTRL_BYPASS (1 << PLL_CTRL_BYPASS_P) +#define PLL_CTRL_DIRECTI (1 << PLL_CTRL_DIRECTI_P) +#define PLL_CTRL_DIRECTO (1 << PLL_CTRL_DIRECTO_P) +#define PLL_CTRL_UPLIMOFF (1 << PLL_CTRL_UPLIMOFF_P) +#define PLL_CTRL_BANDSEL_SSCGREG_N (1 << PLL_CTRL_BANDSEL_SSCGREG_N_P) +#define PLL_CTRL_BYPASS_FBDIV2 (1 << PLL_CTRL_BYPASS_FBDIV2_P) + +// SSCG control[0] +// #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0 +#define PLL_SSCG0_MREQ_P 17 +#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18 +#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P) +#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P) + +// SSCG control[1] +#define PLL_SSCG1_MD_REQ_P 19 +#define PLL_SSCG1_MOD_PD_SSCGCLK_N_P 28 +#define PLL_SSCG1_DITHER_P 29 +#define PLL_SSCG1_MOD_PD_SSCGCLK_N (1 << PLL_SSCG1_MOD_PD_SSCGCLK_N_P) +#define PLL_SSCG1_DITHER (1 << PLL_SSCG1_DITHER_P) +#define PLL_SSCG1_MD_REQ (1 << PLL_SSCG1_MD_REQ_P) + +// PLL NDEC reg +#define PLL_NDEC_VAL_SET(value) (((unsigned long) (value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +#define PLL_NDEC_NREQ_P 10 +#define PLL_NDEC_NREQ (1 << PLL_NDEC_NREQ_P) + +// PLL PDEC reg +#define PLL_PDEC_VAL_SET(value) (((unsigned long) (value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +#define PLL_PDEC_PREQ_P 7 +#define PLL_PDEC_PREQ (1 << PLL_PDEC_PREQ_P) + +// SSCG control[0] +#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long) (value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) +#define PLL_SSCG0_MREQ_P 17 +#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P) +#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18 +#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P) + +// SSCG control[1] +#define PLL_SSCG1_MD_FRACT_P 0 +#define PLL_SSCG1_MD_INT_P 11 +#define PLL_SSCG1_MF_P 20 +#define PLL_SSCG1_MC_P 26 +#define PLL_SSCG1_MR_P 23 + +#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) +#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) +#define PLL_SSCG1_MF_M (0x7UL << PLL_SSCG1_MF_P) +#define PLL_SSCG1_MC_M (0x3UL << PLL_SSCG1_MC_P) +#define PLL_SSCG1_MR_M (0x7UL << PLL_SSCG1_MR_P) + +#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long) (value) << \ + PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) +#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long) (value) << \ + PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) + +// Middle of the range values for spread-spectrum +#define PLL0_SSCG_MF_FREQ_VALUE 4 +#define PLL0_SSCG_MC_COMP_VALUE 2 +#define PLL0_SSCG_MR_DEPTH_VALUE 4 +#define PLL0_SSCG_DITHER_VALUE 0 + +#define PLL_MAX_N_DIV 0x100 + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t curPllRate; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N) +{ + uint32_t x, i; + + /* Find NDec */ + switch (N) { + case 0: + x = 0x3FF; + break; + + case 1: + x = 0x302; + break; + + case 2: + x = 0x202; + break; + + default: + x = 0x080; + for (i = N; i <= NVALMAX; i++) { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + } + break; + } + + return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) { + case 0x3FF: + n = 0; + break; + + case 0x302: + n = 1; + break; + + case 0x202: + n = 2; + break; + + default: + x = 0x080; + n = 0xFFFFFFFF; + for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + + return n; +} + +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P) +{ + uint32_t x, i; + + /* Find PDec */ + switch (P) { + case 0: + x = 0xFF; + break; + + case 1: + x = 0x62; + break; + + case 2: + x = 0x42; + break; + + default: + x = 0x10; + for (i = P; i <= PVALMAX; i++) { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); + } + break; + } + + return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + + /* Find PDec */ + switch (PDEC) { + case 0xFF: + p = 0; + break; + + case 0x62: + p = 1; + break; + + case 0x42: + p = 2; + break; + + default: + x = 0x10; + p = 0xFFFFFFFF; + for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + + return p; +} + +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M) +{ + uint32_t i, x; + + /* Find MDec */ + switch (M) { + case 0: + x = 0x1FFFF; + break; + + case 1: + x = 0x18003; + break; + + case 2: + x = 0x10003; + break; + + case 7: + x = 0x1F; + break; + + case 8: + x = 0x3F; + break; + + case 10: + x = 0xFF; + break; + + case 12: + x = 0x3FF; + break; + + default: + x = 0x04000; + for (i = M; i <= MVALMAX; i++) { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + } + break; + } + + return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) { + case 0x1FFFF: + m = 0; + break; + + case 0x18003: + m = 1; + break; + + case 0x10003: + m = 2; + break; + + case 0x1F: + m = 7; + break; + + case 0x3F: + m = 8; + break; + + case 0xFF: + m = 10; + break; + + case 0x3FF: + m = 12; + break; + + default: + x = 0x04000; + m = 0xFFFFFFFF; + for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + + return m; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + /* bandwidth: compute selP from Multiplier */ + if (M < 60) { + *pSelP = (M >> 1) + 1; + } + else { + *pSelP = PVALMAX - 1; + } + + /* bandwidth: compute selI from Multiplier */ + if (M > 16384) { + *pSelI = 1; + } + else if (M > 8192) { + *pSelI = 2; + } + else if (M > 2048) { + *pSelI = 4; + } + else if (M >= 501) { + *pSelI = 8; + } + else if (M >= 60) { + *pSelI = 4 * (1024 / (M + 9)); + } + else { + *pSelI = (M & 0x3C) + 4; + } + + if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P)) { + *pSelI = (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P); + } + + *pSelR = 0; +} + +/* Get predivider (N) from PLL NDEC setting */ +uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0) { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FF); + if (preDiv == 0) { + preDiv = 1; + } + } + + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYS_PLL_DIRECTO) == 0) { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2 * pllDecodeP(pDecReg & 0x7F); + if (postDiv == 0) { + postDiv = 2; + } + } + + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFF); + + /* Extra multiply by 2 needed? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0) { + mMult = mMult << 1; + } + + if (mMult == 0) { + mMult = 1; + } + + return mMult; +} + +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0) { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* Set PLL output based on desired output rate */ +static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_SETUP_T *pSetup, + bool useFeedbackDiv2, bool useSS) +{ + uint32_t nDivOutHz, fccoHz, multFccoDiv; + uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0; /* 0 implies post-divider will be disabled */ + pllDirectOutput = 1; + if (useFeedbackDiv2) { + /* Using feedback divider for M, so disable bypass */ + pllBypassFBDIV2 = 0; + } + else { + pllBypassFBDIV2 = 1; + } + multFccoDiv = (2 - pllBypassFBDIV2); + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return PLL_ERROR_OUTPUT_TOO_HIGH; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1))) { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return PLL_ERROR_OUTPUT_TOO_LOW; + } + + /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ + if (useSS) { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) { + /* Input clock into the PLL cannot be lower than this */ + return PLL_ERROR_INPUT_TOO_LOW; + } + + /* PLL input in SS mode must be under 4MHz */ + pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); + if (pllPreDivider > NVALMAX) { + return PLL_ERROR_INPUT_TOO_HIGH; + } + } + else { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) { + /* Input clock into the PLL cannot be lower than this */ + return PLL_ERROR_INPUT_TOO_LOW; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) { + return PLL_ERROR_OUTSIDE_INTLIMIT; + } + + /* Target CCO goes up, PLL output goes down */ + fccoHz = foutHz * (pllPostDivider * 2); + pllDirectOutput = 0; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) { + uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); + + if (a > 20000) { + a = (multFccoDiv * finHz) / a; + if ((a != 0) && (a < PLL_MAX_N_DIV)) { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1) { + pllDirectInput = 0; + } + else { + pllDirectInput = 1; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; + + /* Find optimal values for filter */ + if (useSS == false) { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2)) { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); + bandsel = 1; + uplimoff = 0; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->SYSPLLSSCTRL[0] = (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | + (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)); + + /* Power down SSC, not used */ + pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MOD_PD_SSCGCLK_N; + } + else { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = pllSelI = pllSelP = 0; + bandsel = 0; + uplimoff = 1; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t) (fccoHz % (multFccoDiv * nDivOutHz)) << 11) / (multFccoDiv * nDivOutHz); + + /* MDEC set by SSC */ + pSetup->SYSPLLSSCTRL[0] = 0; + + /* Set multiplier */ + pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | + PLL_SSCG1_MD_FRACT_SET((uint32_t) fc); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->SYSPLLNDEC = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); + pSetup->SYSPLLPDEC = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); + + /* PLL control */ + pSetup->SYSPLLCTRL = + (pllSelR << SYSCON_SYSPLLCTRL_SELR_P) | /* Filter coefficient */ + (pllSelI << SYSCON_SYSPLLCTRL_SELI_P) | /* Filter coefficient */ + (pllSelP << SYSCON_SYSPLLCTRL_SELP_P) | /* Filter coefficient */ + (0 << SYSCON_SYSPLLCTRL_BYPASS_P) | /* PLL bypass mode disabled */ + (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) | /* Extra M / 2 divider? */ + (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_P) | /* SS/fractional mode disabled */ + (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) | /* Manual bandwidth selection enabled */ + (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_P) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_P); /* Bypass post-divider? */ + + return PLL_ERROR_SUCCESS; +} + +/* Update local PLL rate variable */ +static void Chip_Clock_GetSystemPLLOutFromSetupUpdate(PLL_SETUP_T *pSetup) +{ + curPllRate = Chip_Clock_GetSystemPLLOutFromSetup(pSetup); +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Return System PLL input clock rate */ +uint32_t Chip_Clock_GetSystemPLLInClockRate(void) +{ + uint32_t clkRate = 0; + + switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3)) { + case SYSCON_PLLCLKSRC_IRC: + clkRate = Chip_Clock_GetIntOscRate(); + break; + + case SYSCON_PLLCLKSRC_CLKIN: + clkRate = Chip_Clock_GetExtClockInRate(); + break; + + case SYSCON_PLLCLKSRC_WDTOSC: + clkRate = Chip_Clock_GetWDTOSCRate(); + break; + + case SYSCON_PLLCLKSRC_RTC: + clkRate = Chip_Clock_GetRTCOscRate(); + break; + } + + return clkRate; +} + +/* Return System PLL output clock rate from setup structure */ +uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup) +{ + uint32_t prediv, postdiv, mMult, inPllRate; + uint64_t workRate; + + inPllRate = Chip_Clock_GetSystemPLLInClockRate(); + if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS) == 0) { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPllPreDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLNDEC); + postdiv = findPllPostDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLPDEC); + + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + /* If using the SS, use the multiplier */ + if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N) { + /* MDEC used for rate */ + mMult = findPllMMult(pSetup->SYSPLLCTRL, pSetup->SYSPLLSSCTRL[0]); + workRate = (uint64_t) inPllRate * (uint64_t) mMult; + } + else { + uint64_t fract; + + /* SS multipler used for rate */ + mMult = (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; + workRate = (uint64_t) inPllRate * (uint64_t) mMult; + + /* Adjust by fractional */ + fract = (uint64_t) (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; + workRate = workRate + ((inPllRate * fract) / 0x800); + } + + workRate = workRate / ((uint64_t) postdiv); + } + else { + /* In bypass mode */ + workRate = (uint64_t) inPllRate; + } + + return (uint32_t) workRate; +} + +/* Return System PLL output clock rate */ +uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute) +{ + PLL_SETUP_T Setup; + uint32_t rate; + + if ((recompute == true) || (curPllRate == 0)) { + Setup.SYSPLLCTRL = LPC_SYSCON->SYSPLLCTRL; + Setup.SYSPLLNDEC = LPC_SYSCON->SYSPLLNDEC; + Setup.SYSPLLPDEC = LPC_SYSCON->SYSPLLPDEC; + Setup.SYSPLLSSCTRL[0] = LPC_SYSCON->SYSPLLSSCTRL[0]; + Setup.SYSPLLSSCTRL[1] = LPC_SYSCON->SYSPLLSSCTRL[1]; + + Chip_Clock_GetSystemPLLOutFromSetupUpdate(&Setup); + } + + rate = curPllRate; + + return rate; +} + +/* Enables and disables PLL bypass mode */ +void Chip_Clock_SetBypassPLL(bool bypass) +{ + if (bypass) { + LPC_SYSCON->SYSPLLCTRL |= SYSCON_SYSPLLCTRL_BYPASS; + } + else { + LPC_SYSCON->SYSPLLCTRL &= ~SYSCON_SYSPLLCTRL_BYPASS; + } +} + +/* Set PLL output based on the passed PLL setup data */ +PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup) +{ + uint32_t inRate; + bool useSS = (bool) ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0); + PLL_ERROR_T pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0) { + inRate = pControl->InputRate; + } + else { + inRate = Chip_Clock_GetSystemPLLInClockRate(); + } + + /* PLL flag options */ + pllError = Chip_Clock_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS); + if ((useSS) && (pllError == PLL_ERROR_SUCCESS)) { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->SYSPLLSSCTRL[1] |= (uint32_t) pControl->ss_mf | (uint32_t) pControl->ss_mr | + (uint32_t) pControl->ss_mc; + if (pControl->mfDither) { + pSetup->SYSPLLSSCTRL[1] |= PLL_SSCG1_DITHER; + } + } + + return pllError; +} + +/* Set PLL output from PLL setup structure */ +PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup) +{ + /* Power off PLL during setup changes */ + Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); + + /* Write PLL setup data */ + LPC_SYSCON->SYSPLLCTRL = pSetup->SYSPLLCTRL; + LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC; + LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC | PLL_NDEC_NREQ;/* latch */ + LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC; + LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC | PLL_PDEC_PREQ;/* latch */ + LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0]; + LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0] | PLL_SSCG0_MREQ; /* latch */ + LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1]; + LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1] | PLL_SSCG1_MD_REQ; /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) { + Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SYS_PLL); + } + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0) { + while (Chip_Clock_IsSystemPLLLocked() == false) {} + } + + /* Update current programmed PLL rate var */ + Chip_Clock_GetSystemPLLOutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0) { + Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, curPllRate); + } + curPllRate = 0; + + return PLL_ERROR_SUCCESS; +} + +/* + Set System PLL clock based on the input frequency and multiplier + + Here is the configuration used by this function: + - input divider -- set to 2 + - output -- direct (p-divider is not used) + - direct in = off + - direct out = on + + There is a subtle doubling of the "multiply_by" factor. + There is a feedback clock that is not disabled. + Because it halves the divider, it doubles the frequency. + This is used to compensate for the input divider value. + + */ + +void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + uint32_t directo = SYS_PLL_DIRECTO; + + while (cco_freq < 75000000) { + multiply_by <<= 1; /* double value in each iteration */ + pdec <<= 1; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + selr = 0; + if(multiply_by < 60) { + seli = (multiply_by & 0x3c) + 4; + selp = (multiply_by >> 1) + 1; + } + else { + selp = 31; + if (multiply_by > 16384) { + seli = 1; + } + else if(multiply_by > 8192) { + seli = 2; + } + else if (multiply_by > 2048) { + seli = 4; + } + else if (multiply_by >= 501) { + seli = 8; + } + else { + seli = 4*(1024/(multiply_by+9)); + } + } + + if (pdec > 1) { + directo = 0; /* use post divider */ + pdec = pdec / 2; /* Account for minus 1 encoding */ + /* Translate P value */ + pdec = (pdec == 1) ? 0x62 : /* 1 * 2 */ + (pdec == 2) ? 0x42 : /* 2 * 2 */ + (pdec == 4) ? 0x02 : /* 4 * 2 */ + (pdec == 8) ? 0x0b : /* 8 * 2 */ + (pdec == 16) ? 0x11 : /* 16 * 2 */ + (pdec == 32) ? 0x08 : 0x08; /* 32 * 2 */ + } + + mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); + ndec = 0x302; /* pre divide by 1 (hardcoded) */ + + LPC_SYSCON->SYSPLLCTRL = SYS_PLL_BANDSEL | directo | SYS_PLL_BYPASSCCODIV2 | (selr << SYSCON_SYSPLLCTRL_SELR_P) | + (seli << SYSCON_SYSPLLCTRL_SELI_P) | (selp << SYSCON_SYSPLLCTRL_SELP_P); + + LPC_SYSCON->SYSPLLPDEC = pdec; /* set PDEC value */ + LPC_SYSCON->SYSPLLPDEC = pdec | (1 << 7); /* Assert PDEC reload request: load register into PLL */ + + LPC_SYSCON->SYSPLLNDEC = ndec; /* set NDEC value */ + LPC_SYSCON->SYSPLLNDEC = ndec | (1 << 10); /* Assert NDEC reload request: load register into PLL */ + + LPC_SYSCON->SYSPLLSSCTRL[0] = (1 << 18) | mdec; /* set MDEC value*/ + LPC_SYSCON->SYSPLLSSCTRL[0] = (1 << 18) | (1 << 17) | mdec; /* Load register into the PLL */ + + curPllRate = 0; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/ring_buffer.c b/ports/lpc/chips/lpc_chip_5410x/src/ring_buffer.c new file mode 100644 index 0000000000000..6411efa4bd816 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/ring_buffer.c @@ -0,0 +1,181 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include +#include "ring_buffer.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1)) +#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1)) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize ring buffer */ +int RingBuffer_Init(RINGBUFF_T *RingBuff, + void *buffer, + int itemSize, + int count, + void *(*cpyFunc)(void *dst, const void *src, uint32_t len)) +{ + RingBuff->data = buffer; + RingBuff->count = count; + RingBuff->itemSz = itemSize; + RingBuff->head = RingBuff->tail = 0; + if (!cpyFunc) { + cpyFunc = memcpy; + } + RingBuff->copy = cpyFunc; + + return 1; +} + +/* Insert a single item into Ring Buffer */ +int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data) +{ + uint8_t *ptr = RingBuff->data; + + /* We cannot insert when queue is full */ + if (RingBuffer_IsFull(RingBuff)) { + return 0; + } + + ptr += RB_INDH(RingBuff) * RingBuff->itemSz; + RingBuff->copy(ptr, data, RingBuff->itemSz); + RingBuff->head++; + + return 1; +} + +/* Insert multiple items into Ring Buffer */ +int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num) +{ + uint8_t *ptr = RingBuff->data; + int cnt1, cnt2; + + /* We cannot insert when queue is full */ + if (RingBuffer_IsFull(RingBuff)) { + return 0; + } + + /* Calculate the segment lengths */ + cnt1 = cnt2 = RingBuffer_GetFree(RingBuff); + if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count) { + cnt1 = RingBuff->count - RB_INDH(RingBuff); + } + cnt2 -= cnt1; + + cnt1 = MIN(cnt1, num); + num -= cnt1; + + cnt2 = MIN(cnt2, num); + num -= cnt2; + + /* Write segment 1 */ + ptr += RB_INDH(RingBuff) * RingBuff->itemSz; + RingBuff->copy(ptr, data, cnt1 * RingBuff->itemSz); + RingBuff->head += cnt1; + + /* Write segment 2 */ + ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz; + data = (const uint8_t *) data + cnt1 * RingBuff->itemSz; + RingBuff->copy(ptr, data, cnt2 * RingBuff->itemSz); + RingBuff->head += cnt2; + + return cnt1 + cnt2; +} + +/* Pop single item from Ring Buffer */ +int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data) +{ + uint8_t *ptr = RingBuff->data; + + /* We cannot pop when queue is empty */ + if (RingBuffer_IsEmpty(RingBuff)) { + return 0; + } + + ptr += RB_INDT(RingBuff) * RingBuff->itemSz; + RingBuff->copy(data, ptr, RingBuff->itemSz); + RingBuff->tail++; + + return 1; +} + +/* Pop multiple items from Ring buffer */ +int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num) +{ + uint8_t *ptr = RingBuff->data; + int cnt1, cnt2; + + /* We cannot insert when queue is empty */ + if (RingBuffer_IsEmpty(RingBuff)) { + return 0; + } + + /* Calculate the segment lengths */ + cnt1 = cnt2 = RingBuffer_GetCount(RingBuff); + if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count) { + cnt1 = RingBuff->count - RB_INDT(RingBuff); + } + cnt2 -= cnt1; + + cnt1 = MIN(cnt1, num); + num -= cnt1; + + cnt2 = MIN(cnt2, num); + num -= cnt2; + + /* Write segment 1 */ + ptr += RB_INDT(RingBuff) * RingBuff->itemSz; + RingBuff->copy(data, ptr, cnt1 * RingBuff->itemSz); + RingBuff->tail += cnt1; + + /* Write segment 2 */ + ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz; + data = (uint8_t *) data + cnt1 * RingBuff->itemSz; + RingBuff->copy(data, ptr, cnt2 * RingBuff->itemSz); + RingBuff->tail += cnt2; + + return cnt1 + cnt2; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/ritimer_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/ritimer_5410x.c new file mode 100644 index 0000000000000..e9aab5924e299 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/ritimer_5410x.c @@ -0,0 +1,105 @@ +/* + * @brief LPC5410X RITimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the RIT */ +void Chip_RIT_Init(LPC_RITIMER_T *pRITimer) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_RIT); + Chip_SYSCON_PeriphReset(RESET_RIT); + + /* Default is timer disabled */ + pRITimer->CTRL = 0x0; +} + +/* DeInitialize the RIT */ +void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer) +{ + pRITimer->CTRL = 0x0; + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_RIT); +} + +/* Set timer interval value */ +void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval) +{ + uint32_t cmp_value; + + /* Determine aapproximate compare value based on clock rate and passed interval */ + cmp_value = (Chip_Clock_GetMainClockRate() / 1000) * time_interval; + + /* Set timer compare value */ + Chip_RIT_SetCOMPVAL(pRITimer, cmp_value); +} + +/* Set timer interval value (48-bit) */ +void Chip_RIT_SetTimerInterval64(LPC_RITIMER_T *pRITimer, uint64_t time_interval) +{ + uint64_t cmp_value; + + /* Determine aapproximate compare value based on clock rate and passed interval */ + cmp_value = (uint64_t) Chip_Clock_GetMainClockRate() / 1000; + cmp_value = cmp_value * time_interval; + + /* Set timer compare value */ + Chip_RIT_SetCOMPVAL64(pRITimer, cmp_value); +} + +/* Check whether interrupt is pending */ +IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer) +{ + uint8_t result; + + if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) { + result = SET; + } + else { + return RESET; + } + + return (IntStatus) result; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/rtc_ut.c b/ports/lpc/chips/lpc_chip_5410x/src/rtc_ut.c new file mode 100644 index 0000000000000..53df6595fc7f0 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/rtc_ut.c @@ -0,0 +1,196 @@ +/* + * @brief RTC tick to (a more) Universal Time + * Adds conversion functions to use an RTC that only provides a + * seconds capability to provide "struct tm" support. + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "rtc_ut.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define SECSPERMIN (60) +#define MINSPERHOUR (60) +#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) +#define HOURSPERDAY (24) +#define SECSPERDAY (SECSPERMIN * MINSPERHOUR * HOURSPERDAY) +#define DAYSPERWEEK (7) +#define MONETHSPERYEAR (12) +#define DAYSPERYEAR (365) +#define DAYSPERLEAPYEAR (366) + +/* Days per month, LY is special */ +static uint8_t daysPerMonth[2][MONETHSPERYEAR] = { + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, /* Normal year */ + {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, /* Leap year */ +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Converts the number of days offset from the start year to real year + data accounting for leap years */ +static void GetDMLY(int dayOff, struct tm *pTime) +{ + bool YearFound = false; + int daysYear = dayOff; + int leapYear, curLeapYear, year = TM_YEAR_BASE, monthYear = 0; + bool MonthFound = false; + + /* Leap year check for less than 1 year time */ + if ( ((year % 4) == 0) && (year != 2000) ) { + curLeapYear = 1; + } + else { + curLeapYear = 0; + } + + /* Determine offset of years from days offset */ + while (YearFound == false) { + if ( ((year % 4) == 0) && (year != 2000) ) { + /* Leap year, 366 days */ + daysYear = DAYSPERLEAPYEAR; + leapYear = 1; + } + else { + /* Leap year, 365 days */ + daysYear = DAYSPERYEAR; + leapYear = 0; + } + + if (dayOff >= daysYear) { + dayOff -= daysYear; + year++; + } + else { + YearFound = true; + curLeapYear = leapYear; /* In a leap year */ + } + + } + + /* Save relative year and day into year */ + pTime->tm_year = year - TM_YEAR_BASE; /* Base year relative */ + pTime->tm_yday = dayOff;/* 0 relative */ + + /* Determine offset of months from days offset */ + while (MonthFound == false) { + if ((dayOff + 1) > daysPerMonth[curLeapYear][monthYear]) { + /* Next month */ + dayOff -= daysPerMonth[curLeapYear][monthYear]; + monthYear++; + } + else { + /* Month found */ + MonthFound = true; + } + } + + pTime->tm_mday = dayOff + 1;/* 1 relative */ + pTime->tm_mon = monthYear; /* 0 relative */ +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Converts an RTC tick time to Universal time */ +void ConvertRtcTime(uint32_t rtcTick, struct tm *pTime) +{ + int daySeconds, dayNum; + + /* Get day offset and seconds since start */ + dayNum = (int) (rtcTick / SECSPERDAY); + daySeconds = (int) (rtcTick % SECSPERDAY); + + /* Fill in secs, min, hours */ + pTime->tm_sec = daySeconds % 60; + pTime->tm_hour = daySeconds / SECSPERHOUR; + pTime->tm_min = (daySeconds - (pTime->tm_hour * SECSPERHOUR)) / SECSPERMIN; + + /* Weekday, 0 = Sunday, 6 = Saturday */ + pTime->tm_wday = (dayNum + TM_DAYOFWEEK) % DAYSPERWEEK; + + /* Get year, month, day of month, and day of year */ + GetDMLY(dayNum, pTime); + + /* Not supported in this driver */ + pTime->tm_isdst = 0; +} + +/* Converts a Universal time to RTC tick time */ +void ConvertTimeRtc(struct tm *pTime, uint32_t *rtcTick) +{ + int leapYear, year = TM_YEAR_BASE; + uint32_t dayOff, monthOff, monthCur, rtcTicks = 0; + + /* Add days for each year and leap year */ + while (year < pTime->tm_year + TM_YEAR_BASE) { + if ( ((year % 4) == 0) && (year != 2000) ) { + /* Leap year, 366 days */ + rtcTicks += DAYSPERLEAPYEAR * SECSPERDAY; + } + else { + /* Leap year, 365 days */ + rtcTicks += DAYSPERYEAR * SECSPERDAY; + } + year++; + } + + /* Day and month are 0 relative offsets since day and month start at 1 */ + dayOff = (uint32_t) pTime->tm_mday - 1; + monthOff = (uint32_t) pTime->tm_mon; + + /* Add in seconds for passed months */ + if ( ((year % 4) == 0) && (year != 2000) ) + leapYear = 1; + else + leapYear = 0; + + for (monthCur = 0; monthCur < monthOff; monthCur++) { + rtcTicks += (uint32_t) (daysPerMonth[leapYear][monthCur] * SECSPERDAY); + } + + /* Add in seconds for day offset into the current month */ + rtcTicks += (dayOff * SECSPERDAY); + + /* Add in seconds for hours, minutes, and seconds */ + rtcTicks += (uint32_t) (pTime->tm_hour * SECSPERHOUR); + rtcTicks += (uint32_t) (pTime->tm_min * SECSPERMIN); + rtcTicks += (uint32_t) pTime->tm_sec; + + *rtcTick = rtcTicks; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/sct_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/sct_5410x.c new file mode 100644 index 0000000000000..aac69a27afe5b --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/sct_5410x.c @@ -0,0 +1,81 @@ +/* + * @brief LPC5410X State Configurable Timer driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize SCT */ +void Chip_SCT_Init(LPC_SCT_T *pSCT) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SCT0); + Chip_SYSCON_PeriphReset(RESET_SCT0); +} + +/* Shutdown SCT */ +void Chip_SCT_DeInit(LPC_SCT_T *pSCT) +{ + Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_SCT0); +} + +/* Set/Clear SCT control register */ +void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena) +{ + if (ena == ENABLE) { + Chip_SCT_SetControl(pSCT, value); + } + else { + Chip_SCT_ClearControl(pSCT, value); + } +} + +/* Set Conflict resolution */ +void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value) +{ + uint32_t tem; + + tem = pSCT->RES & (~(0x03 << (2 * outnum))); + pSCT->RES = tem | (value << (2 * outnum)); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/sct_pwm_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/sct_pwm_5410x.c new file mode 100644 index 0000000000000..aca4565054534 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/sct_pwm_5410x.c @@ -0,0 +1,86 @@ +/* + * @brief LPC5410x State Configurable Timer PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Setup the OUTPUT pin corresponding to the PWM index */ +void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin) +{ + int ix = (int) index; + pSCT->EVENT[ix].CTRL = index | (1 << 12); + pSCT->EVENT[ix].STATE = 1; + pSCT->OUT[pin].SET = 1; + pSCT->OUT[pin].CLR = 1 << ix; + + /* Clear the output in-case of conflict */ + pSCT->RES = (pSCT->RES & ~(3 << (pin << 1))) | (0x01 << (pin << 1)); + + /* Set and Clear do not depend on direction */ + pSCT->OUTPUTDIRCTRL = (pSCT->OUTPUTDIRCTRL & ~(3 << (pin << 1))); +} + +/* Set the PWM frequency */ +void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq) +{ + uint32_t rate; + + rate = Chip_Clock_GetSystemClockRate() / freq; + + /* Stop the SCT before configuration */ + Chip_SCTPWM_Stop(pSCT); + + /* Set MATCH0 for max limit */ + pSCT->REGMODE_L = 0; + pSCT->REGMODE_H = 0; + Chip_SCT_SetMatchCount(pSCT, SCT_MATCH_0, 0); + Chip_SCT_SetMatchReload(pSCT, SCT_MATCH_0, rate); + pSCT->EVENT[0].CTRL = 1 << 12; + pSCT->EVENT[0].STATE = 1; + + /* Set SCT Counter to count 32-bits and reset to 0 after reaching MATCH0 */ + Chip_SCT_Config(pSCT, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/spi_common_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/spi_common_5410x.c new file mode 100644 index 0000000000000..601fe0cbd6f56 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/spi_common_5410x.c @@ -0,0 +1,71 @@ +/* + * @brief LPC5410X SPI driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Setup SAPI configuration */ +void Chip_SPI_ConfigureSPI(LPC_SPI_T *pSPI, SPI_CFGSETUP_T *pCFG) +{ + uint32_t reg; + + /* Get register and mask off config bits this function alters */ + reg = pSPI->CFG & ~(SPI_CFG_MASTER_EN | SPI_CFG_LSB_FIRST_EN | + SPI_CFG_CPHA_SECOND | SPI_CFG_CPOL_HI); + + if (pCFG->master) { + reg |= SPI_CFG_MASTER_EN; + } + if (pCFG->lsbFirst) { + reg |= SPI_CFG_LSB_FIRST_EN; + } + reg |= (uint32_t) pCFG->mode; + + Chip_SPI_SetCFGRegBits(pSPI, reg); + + /* Deassert all chip selects, only in master mode */ + pSPI->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/spim_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/spim_5410x.c new file mode 100644 index 0000000000000..69a22d52adc66 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/spim_5410x.c @@ -0,0 +1,201 @@ +/* + * @brief LPC5410X SPI master driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Get SPI master bit rate */ +uint32_t Chip_SPIM_GetClockRate(LPC_SPI_T *pSPI) +{ + return Chip_Clock_GetAsyncSyscon_ClockRate() / (pSPI->DIV + 1); +} + +/* Set SPI master bit rate */ +uint32_t Chip_SPIM_SetClockRate(LPC_SPI_T *pSPI, uint32_t rate) +{ + uint32_t baseClock, div; + + /* Get peripheral base clock rate */ + baseClock = Chip_Clock_GetAsyncSyscon_ClockRate(); + + /* Compute divider */ + div = baseClock / rate; + + /* Limit values */ + if (div == 0) { + div = 1; + } + else if (div > 0x10000) { + div = 0x10000; + } + pSPI->DIV = div - 1; + + return Chip_SPIM_GetClockRate(pSPI); +} + +/* Handler SPI transfer RX */ +__STATIC_INLINE int Chip_SPIM_HandlerRx(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) +{ + int ret = 0; + int flen = (xfer->options >> 8) & 0xF; + uint32_t data = Chip_SPI_ReadRawRXFifo(pSPI); + + if (xfer->rxCount > xfer->rxDoneCount) { + if (flen > 8) { + ((uint16_t *) xfer->rxBuff)[xfer->rxDoneCount] = data; + } + else { + ((uint8_t *) xfer->rxBuff)[xfer->rxDoneCount] = data; + } + ret = 1; + } + xfer->rxDoneCount++; + if ((xfer->rxCount == xfer->rxDoneCount) && xfer->cbFunc) { + xfer->cbFunc(SPIM_EVT_RXDONE, xfer); + } + return ret; +} + +/* SPI master transfer state change handler */ +void Chip_SPIM_XferHandler(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) +{ + uint32_t data; + uint8_t flen; + + /* Get length of a receive value */ + flen = (pSPI->TXCTRL >> 24) & 0xF; + + /* Master asserts slave */ + if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSA) != 0) { + Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSA); + + xfer->state = SPIM_XFER_STATE_BUSY; + /* SSEL assertion callback */ + if (xfer->cbFunc) { + xfer->cbFunc(SPIM_EVT_SSELASSERT, xfer); + } + } + + /* Slave de-assertion */ + if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD) != 0) { + Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD); + + xfer->state = SPIM_XFER_STATE_DONE; + /* SSEL assertion callback */ + if (xfer->cbFunc) { + xfer->cbFunc(SPIM_EVT_SSELDEASSERT, xfer); + } + } + + /* Data received? */ + while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) != 0 && Chip_SPIM_HandlerRx(pSPI, xfer)) {} + + /* Transmit data? */ + while (((Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY) != 0)) { + int32_t len = xfer->rxCount > xfer->txCount ? xfer->rxCount : xfer->txCount; + if ((xfer->rxCount <= xfer->rxDoneCount) && (xfer->txCount <= xfer->txDoneCount)) { + xfer->state = SPIM_XFER_STATE_DONE; + /* Transfer is done, this will be last data */ + Chip_SPIM_ForceEndOfTransfer(pSPI); + return; + } + data = 0; + if (xfer->txCount > xfer->txDoneCount) { + if (flen > 8) { + data = ((uint16_t *) xfer->txBuff)[xfer->txDoneCount]; + } + else { + data = ((uint8_t *) xfer->txBuff)[xfer->txDoneCount]; + } + } + + /* Check for end of transfer and end the transfer if needed */ + if ((len == (xfer->txDoneCount + 1)) && (xfer->options & SPIM_XFER_OPTION_EOT)) { + pSPI->TXDATCTL = pSPI->TXCTRL | SPI_TXDATCTL_EOT | data; + } + else { + Chip_SPI_WriteTXData(pSPI, data); + } + + xfer->txDoneCount++; + if ((xfer->txCount == xfer->txDoneCount) && xfer->cbFunc) { + xfer->cbFunc(SPIM_EVT_TXDONE, xfer); + } + + /* Check if we have a data ready to receive */ + if (Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) { + Chip_SPIM_HandlerRx(pSPI, xfer); + } + } +} + +/* Start non-blocking SPI master transfer */ +void Chip_SPIM_Xfer(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) +{ + /* Setup SPI master select, data length, EOT/EOF timing, and RX data ignore */ + pSPI->TXCTRL = + ((xfer->options << + 16) | SPI_TXDATCTL_DEASSERT_ALL | (xfer->rxBuff ? 0 : SPI_TXDATCTL_RXIGNORE)) & ~SPI_TXDATCTL_EOT; + Chip_SPIM_AssertSSEL(pSPI, xfer->sselNum); + + /* Clear initial transfer states */ + xfer->txDoneCount = xfer->rxDoneCount = 0; + + /* Call main handler to start transfer */ + Chip_SPIM_XferHandler(pSPI, xfer); +} + +/* Perform blocking SPI master transfer */ +void Chip_SPIM_XferBlocking(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) +{ + /* Start trasnfer */ + Chip_SPIM_Xfer(pSPI, xfer); + + /* Wait for termination */ + while (xfer->state != SPIM_XFER_STATE_DONE) { + Chip_SPIM_XferHandler(pSPI, xfer); + } +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/spis_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/spis_5410x.c new file mode 100644 index 0000000000000..eb0b37cb30e0d --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/spis_5410x.c @@ -0,0 +1,154 @@ +/* + * @brief LPC5410X SPI master driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Determine SSEL associated with the current data value */ +static uint8_t Chip_SPIS_FindSSEL(LPC_SPI_T *pSPI, uint32_t data) +{ + int i; + uint8_t ssel = 0; + + for (i = 0; i <= 3; i++) { + if ((data & SPI_RXDAT_RXSSELNUM_INACTIVE(i)) == 0) { + /* Signal is active on low */ + ssel = (uint8_t) i; + } + } + + return ssel; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* SPI slave transfer state change handler */ +uint32_t Chip_SPIS_XferHandler(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) +{ + uint32_t staterr, data; + uint8_t flen; + + /* Get length of a receive value */ + flen = (pSPI->TXCTRL >> 24) & 0xF; + + /* Data received? */ + while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) != 0) { + /* Get raw data and status */ + data = Chip_SPI_ReadRXData(pSPI); + if (xfer->rxCount > xfer->rxDoneCount) { + if (flen > 8) { + ((uint16_t *) xfer->rxBuff)[xfer->rxDoneCount] = data; + } + else { + ((uint8_t *) xfer->rxBuff)[xfer->rxDoneCount] = data; + } + } + xfer->rxDoneCount++; + if (xfer->cbFunc && (xfer->rxCount == xfer->rxDoneCount)) { + xfer->cbFunc(SPIS_EVT_RXDONE, xfer); + } + } + + /* Get errors for later, we'll continue even if errors occur, but we notify + caller on return */ + staterr = Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR); + if (staterr != 0) { + Chip_SPI_ClearStatus(pSPI, staterr); + } + + /* Slave assertion */ + if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSA) != 0) { + Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSA); + + /* Determine SPI select. Read the data FIFO to get the slave number. Data + should not be in the receive FIFO yet, only the statuses */ + xfer->sselNum = Chip_SPIS_FindSSEL(pSPI, Chip_SPI_ReadRawRXFifo(pSPI)); + + xfer->state = SPIS_XFER_STATE_BUSY; + /* SSEL assertion callback */ + if (xfer->cbFunc) { + xfer->cbFunc(SPIS_EVT_SSELASSERT, xfer); + } + } + + /* Transmit data? */ + while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY) != 0) { + data = 0; + if (xfer->txCount > xfer->txDoneCount) { + data = flen > 8 ? + (uint32_t) ((uint16_t *) xfer->txBuff)[xfer->txDoneCount] : + (uint32_t) ((uint8_t *) xfer->txBuff)[xfer->txDoneCount]; + } + Chip_SPI_WriteTXData(pSPI, data); + xfer->txDoneCount++; + if (xfer->cbFunc && (xfer->txCount == xfer->txDoneCount)) { + xfer->cbFunc(SPIS_EVT_TXDONE, xfer); + } + } + + /* Slave de-assertion */ + if (((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD) != 0) && ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) == 0)) { + Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD); + xfer->state = SPIS_XFER_STATE_DONE; + /* SSEL assertion callback */ + if (xfer->cbFunc) { + xfer->cbFunc(SPIS_EVT_SSELDEASSERT, xfer); + } + } + + return staterr; +} + +/* SPI slave transfer blocking function */ +uint32_t Chip_SPIS_XferBlocking(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) +{ + uint32_t status = 0; + + /* Wait forever until deassertion event */ + while (xfer->state != SPIS_XFER_STATE_DONE) { + status = Chip_SPIS_XferHandler(pSPI, xfer); + } + + return status; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/stopwatch_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/stopwatch_5410x.c new file mode 100644 index 0000000000000..483df42692021 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/stopwatch_5410x.c @@ -0,0 +1,109 @@ +/* + * @brief LPC5410x specific stopwatch implementation + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "stopwatch.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Precompute these to optimize runtime */ +static uint32_t ticksPerSecond; +static uint32_t ticksPerMs; +static uint32_t ticksPerUs; + +/* Use this timer for stopwatch */ +#define LPC_TIMER32_1 LPC_TIMER0 + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize stopwatch */ +void StopWatch_Init(void) +{ + /* Set prescaler to divide by 8 */ + const uint32_t prescaleDivisor = 8; + Chip_TIMER_Init(LPC_TIMER32_1); + Chip_TIMER_PrescaleSet(LPC_TIMER32_1, prescaleDivisor - 1); + Chip_TIMER_Enable(LPC_TIMER32_1); + + /* Pre-compute tick rate. */ + ticksPerSecond = Chip_Clock_GetAsyncSyscon_ClockRate() / prescaleDivisor; + ticksPerMs = ticksPerSecond / 1000; + ticksPerUs = ticksPerSecond / 1000000; +} + +/* Start a stopwatch */ +uint32_t StopWatch_Start(void) +{ + /* Return the current timer count. */ + return Chip_TIMER_ReadCount(LPC_TIMER32_1); +} + +/* Returns number of ticks per second of the stopwatch timer */ +uint32_t StopWatch_TicksPerSecond(void) +{ + return ticksPerSecond; +} + +/* Converts from stopwatch ticks to mS. */ +uint32_t StopWatch_TicksToMs(uint32_t ticks) +{ + return ticks / ticksPerMs; +} + +/* Converts from stopwatch ticks to uS. */ +uint32_t StopWatch_TicksToUs(uint32_t ticks) +{ + return ticks / ticksPerUs; +} + +/* Converts from mS to stopwatch ticks. */ +uint32_t StopWatch_MsToTicks(uint32_t mS) +{ + return mS * ticksPerMs; +} + +/* Converts from uS to stopwatch ticks. */ +uint32_t StopWatch_UsToTicks(uint32_t uS) +{ + return uS * ticksPerUs; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/syscon_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/syscon_5410x.c new file mode 100644 index 0000000000000..35ecff95ced45 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/syscon_5410x.c @@ -0,0 +1,192 @@ +/* + * @brief LPC5410X System & Control driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set source for non-maskable interrupt (NMI) */ +void Chip_SYSCON_SetNMISource(uint32_t intsrc) +{ + uint32_t reg; + + reg = LPC_SYSCON->NMISRC; +#if defined(CORE_M4) + reg &= ~SYSCON_NMISRC_M4_ENABLE; +#else + reg &= ~SYSCON_NMISRC_M0_ENABLE; + intsrc = (intsrc << 8); +#endif + + /* First write without NMI bit, and then write source */ + LPC_SYSCON->NMISRC = reg; + LPC_SYSCON->NMISRC = reg | intsrc; +} + +/* Enable interrupt used for NMI source */ +void Chip_SYSCON_EnableNMISource(void) +{ +#if defined(CORE_M4) + LPC_SYSCON->NMISRC |= SYSCON_NMISRC_M4_ENABLE; +#else + LPC_SYSCON->NMISRC |= SYSCON_NMISRC_M0_ENABLE; +#endif +} + +/* Disable interrupt used for NMI source */ +void Chip_SYSCON_DisableNMISource(void) +{ +#if defined(CORE_M4) + LPC_SYSCON->NMISRC &= ~SYSCON_NMISRC_M4_ENABLE; +#else + LPC_SYSCON->NMISRC &= ~SYSCON_NMISRC_M0_ENABLE; +#endif +} + +/* Enable or disable asynchronous APB bridge and subsystem */ +void Chip_SYSCON_Enable_ASYNC_Syscon(bool enable) +{ + if (enable) { + LPC_SYSCON->ASYNCAPBCTRL = 0x01; + } + else { + LPC_SYSCON->ASYNCAPBCTRL = 0x00; + } +} + +/* Resets a peripheral */ +void Chip_SYSCON_PeriphReset(CHIP_SYSCON_PERIPH_RESET_T periph) +{ + uint32_t pid = (uint32_t) periph; + + if (pid >= 128) { + /* Async resets mapped to 128 and above, offset for peripheral bit index */ + pid = 1 << (((uint32_t) periph) - 128); + LPC_ASYNC_SYSCON->ASYNCPRESETCTRLSET = pid; + LPC_ASYNC_SYSCON->ASYNCPRESETCTRLCLR = pid; + } + else if (periph >= 32) { + pid = 1 << (((uint32_t) periph) - 32); + LPC_SYSCON->PRESETCTRLSET[1] = pid; + LPC_SYSCON->PRESETCTRLCLR[1] = pid; + } + else { + pid = 1 << ((uint32_t) periph); + LPC_SYSCON->PRESETCTRLSET[0] = pid; + LPC_SYSCON->PRESETCTRLCLR[0] = pid; + } +} + +/* Returns the computed value for a frequency measurement cycle */ +uint32_t Chip_SYSCON_GetCompFreqMeas(uint32_t refClockRate) +{ + uint32_t capval; + uint64_t clkrate = 0; + + /* Get raw capture value */ + capval = Chip_SYSCON_GetRawFreqMeasCapval(); + + /* Limit CAPVAL check */ + if (capval > 2) { + clkrate = (((uint64_t) capval - 2) * (uint64_t) refClockRate) / 0x4000; + } + + return (uint32_t) clkrate; +} + +uint32_t Chip_SYSCON_PLLDelay(void) +{ + uint32_t ifreq = Chip_Clock_GetSystemPLLInClockRate(); + uint32_t coreclk = Chip_Clock_GetMainClockRate(), div = 0; + if (coreclk) { + div = 12000000 / coreclk; + } + if (!div) { + div = 1; + } + if (ifreq <= 100000) { + /* Dealy for 600 uSecs */ + return 1430 / div; + } + else if (ifreq <= 1000000) { + /* Delay for 300 uSecs */ + return 1210 / div; + } + else if (ifreq <= 10000000) { + return 657 / div; + } + else { + return 172 / div; /* 72 uSecs */ + } +} + +void Chip_SYSCON_PowerUp(uint32_t powerupmask) +{ + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + if (powerupmask & SYSCON_PDRUNCFG_PD_SYS_PLL) { + volatile uint32_t delayX; + uint32_t maxCCO = (1 << 18) | 0x5dd2; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = LPC_SYSCON->SYSPLLSSCTRL[0] & ~(1 << 17); /* current value with mreq cleared */ + + /* Initialize and power up PLL */ + LPC_SYSCON->SYSPLLSSCTRL[0] = maxCCO; + LPC_SYSCON->PDRUNCFGCLR = SYSCON_PDRUNCFG_PD_SYS_PLL; + + /* Set mreq to activate */ + LPC_SYSCON->SYSPLLSSCTRL[0] = maxCCO | (1 << 17); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = Chip_SYSCON_PLLDelay(); delayX; --delayX) {} + + /* clear mreq to prepare for restoring mreq */ + LPC_SYSCON->SYSPLLSSCTRL[0] = curSSCTRL; + + /* set original value back and activate */ + LPC_SYSCON->SYSPLLSSCTRL[0] = curSSCTRL | (1 << 17); + } + + /* Enable peripheral states by setting low */ + LPC_SYSCON->PDRUNCFGCLR = powerupmask; +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/sysinit_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/sysinit_5410x.c new file mode 100644 index 0000000000000..346a59019aab8 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/sysinit_5410x.c @@ -0,0 +1,181 @@ +/* + * @brief LPC5410X Chip specific SystemInit + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Sets the best FLASH clock arte for the passed frequency */ +static void setupFlashClocks(uint32_t freq) +{ + /* v17.0 ROM support only - coarse FLASH clocking timing. + FLASH access is setup based on voltage for v17.1 and later ROMs + as part of the power library. */ + if (Chip_POWER_GetROMVersion() == LPC5410X_ROMVER_0) { + if (freq < 20000000) { + Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_1CYCLE); + } + else if (freq < 48000000) { + Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_2CYCLE); + } + else if (freq < 72000000) { + Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_3CYCLE); + } + else { + Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_4CYCLE); + } + } +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Clock and PLL initialization based on the internal oscillator */ +void Chip_SetupIrcClocking(uint32_t iFreq) +{ + PLL_CONFIG_T pllConfig; + PLL_SETUP_T pllSetup; + PLL_ERROR_T pllError; + bool usePLL = false; + + /* Turn on the IRC by clearing the power down bit */ + Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_IRC_OSC | SYSCON_PDRUNCFG_PD_IRC); + + /* Select the PLL input to the IRC */ + Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC); + + /* Setup FLASH access */ + setupFlashClocks(iFreq); + + if (iFreq > 12000000) { + usePLL = true; + } + + if (usePLL) { + /* Select the PLL input to the IRC */ + + /* Power down PLL to change the PLL divider ratio */ + Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); + + /* Setup PLL configuration */ + pllConfig.desiredRate = iFreq; + pllConfig.InputRate = 0; + pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT; + pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup); + if (pllError == PLL_ERROR_SUCCESS) { + pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT; + pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup); + } + } + + /* Set system clock divider to 1 */ + Chip_Clock_SetSysClockDiv(1); + + /* Set main clock source to the system PLL. This will drive 24MHz + for the main clock and 24MHz for the system clock */ + if (usePLL) + Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); + else + Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_IRC); + + /* ASYSNC SYSCON needs to be on or all serial peripheral won't work. + Be careful if PLL is used or not, ASYNC_SYSCON source needs to be + selected carefully. */ + Chip_SYSCON_Enable_ASYNC_Syscon(true); + Chip_Clock_SetAsyncSysconClockDiv(1); + Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_IRC); +} + +/* Clock and PLL initialization based on the external clock input */ +void Chip_SetupExtInClocking(uint32_t iFreq) +{ + PLL_CONFIG_T pllConfig; + PLL_SETUP_T pllSetup; + PLL_ERROR_T pllError; + + /* IOCON clock left on, this is needed is CLKIN is used. */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_IOCON); + + /* Select external clock input pin */ + Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 22, (IOCON_MODE_PULLUP | + IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF)); + + /* Select the PLL input to the EXT clock input */ + Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_CLKIN); + + /* Setup FLASH access */ + setupFlashClocks(iFreq); + + /* Power down PLL to change the PLL divider ratio */ + Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); + + /* Setup PLL configuration */ + pllConfig.desiredRate = iFreq; + pllConfig.InputRate = 0; + pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT; + pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup); + if (pllError == PLL_ERROR_SUCCESS) { + pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT; + pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup); + } + + /* Set system clock divider to 1 */ + Chip_Clock_SetSysClockDiv(1); + + /* Set main clock source to the system PLL. This will drive 24MHz + for the main clock and 24MHz for the system clock */ + Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); + + /* ASYSNC SYSCON needs to be on or all serial peripheral won't work. + Be careful if PLL is used or not, ASYNC_SYSCON source needs to be + selected carefully. */ + Chip_SYSCON_Enable_ASYNC_Syscon(true); + Chip_Clock_SetAsyncSysconClockDiv(1); + Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_IRC); +} + +/* Set up and initialize hardware prior to call to main */ +void Chip_SystemInit(void) +{ + /* Initial internal clocking @100MHz */ + Chip_SetupIrcClocking(100000000); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/timer_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/timer_5410x.c new file mode 100644 index 0000000000000..7938a1988aa9e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/timer_5410x.c @@ -0,0 +1,133 @@ +/* + * @brief LPC5410X 32-bit Timer/PWM driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +struct TBASE_TO_TMRBITS { + uint32_t base; + uint8_t clockID; + uint8_t resetID; +}; + +#define LAST_TIMER (4) +static const struct TBASE_TO_TMRBITS tbaseToTimerIDs[LAST_TIMER + 1] = { + {LPC_TIMER0_BASE, (uint8_t) SYSCON_CLOCK_TIMER0, (uint8_t) RESET_TIMER0}, + {LPC_TIMER1_BASE, (uint8_t) SYSCON_CLOCK_TIMER1, (uint8_t) RESET_TIMER1}, + {LPC_TIMER2_BASE, (uint8_t) SYSCON_CLOCK_TIMER2, (uint8_t) RESET_TIMER2}, + {LPC_TIMER3_BASE, (uint8_t) SYSCON_CLOCK_TIMER3, (uint8_t) RESET_TIMER3}, + {LPC_TIMER4_BASE, (uint8_t) SYSCON_CLOCK_TIMER4, (uint8_t) RESET_TIMER4} +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Return index into tbaseToTimerIDs for timers 0-4 */ +static int GetClockID(LPC_TIMER_T *pTMR) +{ + int timerId = LAST_TIMER; + + while (timerId >= 0) { + if (pTMR == (LPC_TIMER_T *) tbaseToTimerIDs[timerId].base) { + return timerId; + } + + timerId--; + } + + /* Waill return timer 0 if no timer match */ + return 0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize a timer */ +void Chip_TIMER_Init(LPC_TIMER_T *pTMR) +{ + int clockId = GetClockID(pTMR); + + Chip_Clock_EnablePeriphClock((CHIP_SYSCON_CLOCK_T) tbaseToTimerIDs[clockId].clockID); + Chip_SYSCON_PeriphReset((CHIP_SYSCON_PERIPH_RESET_T) tbaseToTimerIDs[clockId].resetID); +} + +/* Shutdown a timer */ +void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR) +{ + int clockId = GetClockID(pTMR); + + Chip_Clock_DisablePeriphClock((CHIP_SYSCON_CLOCK_T) tbaseToTimerIDs[clockId].clockID); +} + +/* Resets the timer counter and prescale counts to 0 */ +void Chip_TIMER_Reset(LPC_TIMER_T *pTMR) +{ + uint32_t reg; + + /* Disable timer, set terminal count to non-0 */ + reg = pTMR->TCR; + pTMR->TCR = 0; + pTMR->TC = 1; + + /* Reset timer counter */ + pTMR->TCR = TIMER_RESET; + + /* Wait for terminal count to clear */ + while (pTMR->TC != 0) {} + + /* Restore timer state */ + pTMR->TCR = reg; +} + +/* Sets external match control (MATn.matchnum) pin control */ +void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, + TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum) +{ + uint32_t mask, reg; + + /* Clear bits corresponding to selected match register */ + mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2))); + /* Also mask reserved bits */ + reg = (pTMR->EMR & TIMER_EMR_MASK) & ~mask; + + /* Set new configuration for selected match register */ + pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) | + (((uint32_t) matchState) << (4 + (matchnum * 2))); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/uart_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/uart_5410x.c new file mode 100644 index 0000000000000..1e07e1fa68cc4 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/uart_5410x.c @@ -0,0 +1,364 @@ +/* + * @brief LPC5410X UART driver + * + * @note + * Copyright(C) NXP Semiconductors, 2015 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Return UART clock ID from the UART register address */ +static CHIP_SYSCON_CLOCK_T getUARTClockID(LPC_USART_T *pUART) +{ + if (pUART == LPC_USART0) { + return SYSCON_CLOCK_USART0; + } + else if (pUART == LPC_USART1) { + return SYSCON_CLOCK_USART1; + } + else if (pUART == LPC_USART2) { + return SYSCON_CLOCK_USART2; + } + return SYSCON_CLOCK_USART3; +} + +/* PRIVATE: Division logic to divide without integer overflow */ +static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m) +{ + uint32_t q, r, u = pclk >> 24, l = pclk << 8; + m = m + 256; + q = (1 << 24) / m; + r = (1 << 24) - (q * m); + return ((q * u) << 8) + (((r * u) << 8) + l) / m; +} + +/* PRIVATE: Get highest Over sampling value */ +static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict) +{ + int32_t i, max = strict ? 16 : 5; + for (i = 16; i >= max; i--) { + if (!(val % i)) { + return i; + } + } + return 0; +} + +/* Calculate error difference */ +static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev) +{ + uint32_t err = n - (n / d) * d; + uint32_t herr = ((n / d) + 1) * d - n; + if (herr < err) { + err = herr; + } + + if (*prev <= err) { + return 0; + } + *prev = err; + return (herr == err) + 1; +} + +/* Calculate the base DIV value */ +static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub) +{ + int32_t i = 0; + uint32_t perr = ~0UL; + + if (!ub->div) { + i = ub->ovr ? ub->ovr : 16; + } + + for (; i > 4; i--) { + int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr); + + /* Continue when no improvement seen in err value */ + if (!tmp) { + continue; + } + + ub->div = tmp - 1; + if (ub->ovr == i) { + break; + } + ub->ovr = i; + } + + if (!ub->ovr) { + return ERR_UART_BAUDRATE; + } + + ub->div += ub->clk / (ub->baud * ub->ovr); + if (!ub->div) { + return ERR_UART_BAUDRATE; + } + + ub->baud = ub->clk / (ub->div * ub->ovr); + return LPC_OK; +} + +/* Calculate the best MUL value */ +static void _UART_CalcMul(UART_BAUD_T *ub) +{ + uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr; + + /* If clock is UART's base clock calculate only the divider */ + for (m = 0; m < 256; m++) { + uint32_t ov = ovr, x, v, tmp; + + /* Get clock and calculate error */ + x = _UART_DivClk(pclk, m); + tmp = _CalcErr(x, ub->baud, &perr); + v = (x / ub->baud) + tmp - 1; + + /* Update if new error is better than previous best */ + if (!tmp || (ovr && (v % ovr)) || + (!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) { + continue; + } + + ub->ovr = ov; + ub->mul = m; + ub->clk = x; + ub->div = tmp - 1; + } +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Function to calculate UART Baud rate */ +uint32_t Chip_UART_CalcBaud(LPC_USART_T *pUART, UART_BAUD_T *pBaud) +{ + if (!pBaud->mul) { + _UART_CalcMul(pBaud); + } + + return _UART_CalcDiv(pBaud); +} + +/* Initialize the UART peripheral */ +void Chip_UART_Init(LPC_USART_T *pUART) +{ + /* Enable USART clock */ + Chip_Clock_EnablePeriphClock(getUARTClockID(pUART)); + + /* UART reset */ + if (pUART == LPC_USART0) { + /* Peripheral reset control to USART0 */ + Chip_SYSCON_PeriphReset(RESET_USART0); + } + else if (pUART == LPC_USART1) { + /* Peripheral reset control to USART1 */ + Chip_SYSCON_PeriphReset(RESET_USART1); + } + else if (pUART == LPC_USART2) { + /* Peripheral reset control to USART2 */ + Chip_SYSCON_PeriphReset(RESET_USART2); + } + else if (pUART == LPC_USART3) { + /* Peripheral reset control to USART3 */ + Chip_SYSCON_PeriphReset(RESET_USART3); + } + +} + +/* Initialize the UART peripheral */ +void Chip_UART_DeInit(LPC_USART_T *pUART) +{ + /* Enable USART clock */ + Chip_Clock_DisablePeriphClock(getUARTClockID(pUART)); +} + +/* Transmit a byte array through the UART peripheral (non-blocking) */ +int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes) +{ + int sent = 0; + uint8_t *p8 = (uint8_t *) data; + + /* Send until the transmit FIFO is full or out of bytes */ + while ((sent < numBytes) && + ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0)) { + Chip_UART_SendByte(pUART, *p8); + p8++; + sent++; + } + + return sent; +} + +/* Transmit a byte array through the UART peripheral (blocking) */ +int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes) +{ + int pass, sent = 0; + uint8_t *p8 = (uint8_t *) data; + + while (numBytes > 0) { + pass = Chip_UART_Send(pUART, p8, numBytes); + numBytes -= pass; + sent += pass; + p8 += pass; + } + + return sent; +} + +/* Read data through the UART peripheral (non-blocking) */ +int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes) +{ + int readBytes = 0; + uint8_t *p8 = (uint8_t *) data; + + /* Send until the transmit FIFO is full or out of bytes */ + while ((readBytes < numBytes) && + ((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0)) { + *p8 = Chip_UART_ReadByte(pUART); + p8++; + readBytes++; + } + + return readBytes; +} + +/* Read data through the UART peripheral (blocking) */ +int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes) +{ + int pass, readBytes = 0; + uint8_t *p8 = (uint8_t *) data; + + while (numBytes > 0) { + pass = Chip_UART_Read(pUART, p8, numBytes); + readBytes += pass; + numBytes -= pass; + p8 += pass; + } + + return readBytes; +} + +/* Set baud rate for UART */ +void Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate) +{ + UART_BAUD_T baud; + + /* Set up baudrate parameters */ + baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */ + baud.baud = baudrate; /* Required baud rate */ + baud.ovr = 0; /* Set the oversampling to the recommended rate */ + baud.mul = baud.div = 0; + Chip_UART_CalcBaud(pUART, &baud); + + /* Enable register clock to the fractional divider */ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FRG); + + /* Set fractional control register */ + Chip_SYSCON_SetUSARTFRGCtrl(baud.mul, 0xFF); + Chip_UART_Div(pUART, baud.div, baud.ovr); +} + +/* UART receive-only interrupt handler for ring buffers */ +void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) +{ + /* New data will be ignored if data not popped in time */ + while ((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0) { + uint8_t ch = Chip_UART_ReadByte(pUART); + RingBuffer_Insert(pRB, &ch); + } +} + +/* UART transmit-only interrupt handler for ring buffers */ +void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) +{ + uint8_t ch; + + /* Fill FIFO until full or until TX ring buffer is empty */ + while (((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) && + RingBuffer_Pop(pRB, &ch)) { + Chip_UART_SendByte(pUART, ch); + } +} + +/* Populate a transmit ring buffer and start UART transmit */ +uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int count) +{ + uint32_t ret; + uint8_t *p8 = (uint8_t *) data; + + /* Don't let UART transmit ring buffer change in the UART IRQ handler */ + Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY); + + /* Move as much data as possible into transmit ring buffer */ + ret = RingBuffer_InsertMult(pRB, p8, count); + Chip_UART_TXIntHandlerRB(pUART, pRB); + + /* Add additional data to transmit ring buffer if possible */ + ret += RingBuffer_InsertMult(pRB, (p8 + ret), (count - ret)); + + /* Enable UART transmit interrupt */ + Chip_UART_IntEnable(pUART, UART_INTEN_TXRDY); + + return ret; +} + +/* Copy data from a receive ring buffer */ +int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes) +{ + (void) pUART; + + return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes); +} + +/* UART receive/transmit interrupt handler for ring buffers */ +void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB) +{ + /* Handle transmit interrupt if enabled */ + if ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) { + Chip_UART_TXIntHandlerRB(pUART, pTXRB); + + /* Disable transmit interrupt if the ring buffer is empty */ + if (RingBuffer_IsEmpty(pTXRB)) { + Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY); + } + } + + /* Handle receive interrupt */ + Chip_UART_RXIntHandlerRB(pUART, pRXRB); +} diff --git a/ports/lpc/chips/lpc_chip_5410x/src/wwdt_5410x.c b/ports/lpc/chips/lpc_chip_5410x/src/wwdt_5410x.c new file mode 100644 index 0000000000000..d1786cf2dfb03 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_5410x/src/wwdt_5410x.c @@ -0,0 +1,61 @@ +/* + * @brief LPC5410X WWDT chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2014 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the Watchdog timer */ +void Chip_WWDT_Init(LPC_WWDT_T *pWWDT) +{ + Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_WWDT); + Chip_SYSCON_PeriphReset(RESET_WWDT); + + /* Disable watchdog */ + pWWDT->MOD = 0; + pWWDT->TC = 0xFF; + pWWDT->WARNINT = 0x3FF; + pWWDT->WINDOW = 0xFFFFFF; +} From 6655ba4ebadd01be0a45e08d3caebb89bd9821ef Mon Sep 17 00:00:00 2001 From: Martin Ribelotta Date: Fri, 22 Sep 2017 18:16:12 -0300 Subject: [PATCH 3/6] lpc: Fix compiler errors on LPCOpen Let's make the bloody compiler happy. This commit fixes -Werror errors throwed by the compiler on LPCOpen library. We want to keep this commit separate from the initial LPCOpen library drop, to allow this commit to be cherry-picked and make library bumps easier. Signed-off-by: Martin Ribelotta Signed-off-by: Ezequiel Garcia --- ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h | 2 +- ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h | 2 +- ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c | 2 +- ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c | 3 ++- ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c | 1 + ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c | 1 + 6 files changed, 7 insertions(+), 4 deletions(-) diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h index 93f2eeef153f5..4ad183be893ef 100644 --- a/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h +++ b/ports/lpc/chips/lpc_chip_43xx/inc/iap_18xx_43xx.h @@ -79,7 +79,7 @@ extern "C" { #define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ /* IAP_ENTRY API function type */ -typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]); +typedef void (*IAP_ENTRY_T)(uint32_t[5], uint32_t[4]); /** * @brief Initialize IAP diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h index 50cec255dd935..7097570408670 100644 --- a/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h +++ b/ports/lpc/chips/lpc_chip_43xx/inc/romapi_18xx_43xx.h @@ -112,7 +112,7 @@ typedef struct { * @} */ -static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[]) +static INLINE void iap_entry(uint32_t cmd_param[], uint32_t status_result[]) { ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); } diff --git a/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c index 589a2cdc72c36..765a363b068e2 100644 --- a/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c +++ b/ports/lpc/chips/lpc_chip_43xx/src/adc_18xx_43xx.c @@ -246,7 +246,7 @@ void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState) /* Read the ADC value and convert it to 8bits value */ Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data) { - uint16_t temp; + uint16_t temp = 0; Status rt; rt = readAdcVal(pADC, channel, &temp); diff --git a/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c index 0ec0cab9f7ba4..e5156760b1110 100644 --- a/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c +++ b/ports/lpc/chips/lpc_chip_43xx/src/lcd_18xx_43xx.c @@ -200,7 +200,8 @@ void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette) pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */ pal_ptr++; /* skip over the unused byte */ - pLCD->PAL[i] = *((uint32_t *)&pal_entry); + void *aliased = ((void*)&pal_entry); + pLCD->PAL[i] = *((uint32_t *)aliased); } } diff --git a/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c index 4f3b8d8e3bb01..cd2819bc2f662 100644 --- a/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c +++ b/ports/lpc/chips/lpc_chip_43xx/src/spi_18xx_43xx.c @@ -138,6 +138,7 @@ void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI) volatile uint32_t tmp; Chip_SPI_GetStatus(pSPI); tmp = Chip_SPI_ReceiveFrame(pSPI); + (void) tmp; Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF); } diff --git a/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c index 186d8b1592d21..c9dce71f3de5d 100644 --- a/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c +++ b/ports/lpc/chips/lpc_chip_43xx/src/uart_18xx_43xx.c @@ -125,6 +125,7 @@ void Chip_UART_Init(LPC_USART_T *pUART) pUART->MCR = 0; /*Dummy Reading to Clear Status */ tmp = pUART->MSR; + (void) tmp; } /* Default 8N1, with DLAB disabled */ From f733eadd783297ffcda6cfad46f4ea1096b7483f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Sat, 23 Sep 2017 10:27:42 -0300 Subject: [PATCH 4/6] lpc: chips: Extend LPCOpen API allowing to clear all interrupts This commit introduces a new function NVIC_ClearAll, which will be used by the reset vector handler to clear all the interrupts. Signed-off-by: Ezequiel Garcia --- ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h | 10 ++++++++++ ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h index 195e3c75ccbbd..4ac68311c7744 100644 --- a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm3.h @@ -1378,6 +1378,16 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) } +/** \brief Clear all interrupts + */ +__STATIC_INLINE void NVIC_ClearAll(void) +{ + uint32_t irqpendloop; + for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { + NVIC->ICPR[irqpendloop] = 0xFFFFFFFF; + } +} + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h index 2a6e37807bc17..0bbb44ec28623 100644 --- a/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h +++ b/ports/lpc/chips/lpc_chip_43xx/inc/core_cm4.h @@ -1523,6 +1523,17 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) } +/** \brief Clear all interrupts + */ +__STATIC_INLINE void NVIC_ClearAll(void) +{ + uint32_t irqpendloop; + for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { + NVIC->ICPR[irqpendloop] = 0xFFFFFFFF; + } +} + + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. From f7eddfe51dd7f8a2ab859df9a23e8b985bfc8717 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Sat, 23 Sep 2017 10:29:28 -0300 Subject: [PATCH 5/6] lpc: chips: Extend LPCOpen allowing to reset all peripherals This commit introduces a new LPCOpen API "Chip_RGU_TriggerResetAll", which will be used by the reset vector handler to reset all peripheral blocks. Signed-off-by: Ezequiel Garcia --- .../chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h b/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h index 68569edaf4373..ad27ef7dd2fe8 100644 --- a/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h +++ b/ports/lpc/chips/lpc_chip_43xx/inc/rgu_18xx_43xx.h @@ -122,6 +122,25 @@ STATIC INLINE void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber) /* Reset will auto clear after 1 clock cycle */ } +/** + * @brief Reset the entire chip + * @return Nothing + */ +STATIC INLINE void Chip_RGU_TriggerResetAll(void) +{ + /* GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST| + * USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST + */ + LPC_RGU->RESET_CTRL[0] = 0x10DF1000; + + /* M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST| + * I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST| + * DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST| + * RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST + */ + LPC_RGU->RESET_CTRL[1] = 0x10DF1000; +} + /** * @brief Checks the reset status of a peripheral * @param ResetNumber : Peripheral reset number to trigger From 534e2b4861603f7cea6fc9f6d5a6c37a79b66427 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 22 Sep 2017 18:33:41 -0300 Subject: [PATCH 6/6] lpc: Add basic micropython port to LPC Cortex-M series microcontrollers First board introduced is EDU CIAA LPC4337 (educational board), using LPCOpen library for LPC18xx/43xx v3.01. This first commit should introduce some infrastructure for other boards to be easily supported. For now, let's just enable a very simple REPL. Signed-off-by: Ernesto Gigliotti Signed-off-by: Martin Ribelotta Signed-off-by: Ezequiel Garcia --- .travis.yml | 1 + README.md | 1 + ports/lpc/Makefile | 81 +++++++ .../lpc/boards/lpc_board_ciaa_edu_4337/README | 3 + .../boards/lpc_board_ciaa_edu_4337/board.mk | 2 + .../lpc_board_ciaa_edu_4337/inc/board.h | 178 +++++++++++++++ .../lpc_board_ciaa_edu_4337/inc/board_api.h | 176 +++++++++++++++ .../boards/lpc_board_ciaa_edu_4337/memory.lds | 9 + .../lpc_board_ciaa_edu_4337/mpconfigboard.h | 2 + .../lpc_board_ciaa_edu_4337/openocd.cfg | 79 +++++++ .../lpc_board_ciaa_edu_4337/src/board.c | 202 ++++++++++++++++++ .../src/board_sysinit.c | 159 ++++++++++++++ ports/lpc/chips/lpc_chip_43xx/README | 3 +- ports/lpc/chips/lpc_chip_43xx/chip.mk | 2 + ports/lpc/chips/lpc_chip_43xx/linker.lds | 60 ++++++ .../lpc_chip_43xx/src/startup_18xx_43xx.c | 185 ++++++++++++++++ ports/lpc/main.c | 92 ++++++++ ports/lpc/mpconfigport.h | 90 ++++++++ ports/lpc/mphalport.c | 17 ++ ports/lpc/mphalport.h | 2 + ports/lpc/qstrdefsport.h | 4 + tools/dfuheader.py | 15 ++ 22 files changed, 1361 insertions(+), 2 deletions(-) create mode 100644 ports/lpc/Makefile create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/README create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board.h create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board_api.h create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/mpconfigboard.h create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c create mode 100644 ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board_sysinit.c create mode 100644 ports/lpc/chips/lpc_chip_43xx/chip.mk create mode 100644 ports/lpc/chips/lpc_chip_43xx/linker.lds create mode 100644 ports/lpc/chips/lpc_chip_43xx/src/startup_18xx_43xx.c create mode 100644 ports/lpc/main.c create mode 100644 ports/lpc/mpconfigport.h create mode 100644 ports/lpc/mphalport.c create mode 100644 ports/lpc/mphalport.h create mode 100644 ports/lpc/qstrdefsport.h create mode 100755 tools/dfuheader.py diff --git a/.travis.yml b/.travis.yml index 83ac2a112b4eb..921348db65b79 100644 --- a/.travis.yml +++ b/.travis.yml @@ -42,6 +42,7 @@ script: - make -C ports/stm32 BOARD=PYBV11 MICROPY_PY_WIZNET5K=1 MICROPY_PY_CC3K=1 - make -C ports/stm32 BOARD=STM32F769DISC - make -C ports/stm32 BOARD=STM32L476DISC + - make -C ports/lpc - make -C ports/teensy - make -C ports/cc3200 BTARGET=application BTYPE=release - make -C ports/cc3200 BTARGET=bootloader BTYPE=release diff --git a/README.md b/README.md index 13529ff4f313f..d1c8f3df75dee 100644 --- a/README.md +++ b/README.md @@ -52,6 +52,7 @@ Additional components: - ports/pic16bit/ -- a version of MicroPython for 16-bit PIC microcontrollers. - ports/cc3200/ -- a version of MicroPython that runs on the CC3200 from TI. - ports/esp8266/ -- an experimental port for ESP8266 WiFi modules. +- ports/lpc/ -- a version of MicroPython for NXP LPC microcontrollers. - extmod/ -- additional (non-core) modules implemented in C. - tools/ -- various tools, including the pyboard.py module. - examples/ -- a few example Python scripts. diff --git a/ports/lpc/Makefile b/ports/lpc/Makefile new file mode 100644 index 0000000000000..a18b143ea7068 --- /dev/null +++ b/ports/lpc/Makefile @@ -0,0 +1,81 @@ +include ../../py/mkenv.mk + +BOARD=lpc_board_ciaa_edu_4337 + +MPY_CROSS=$(TOP)/mpy-cross/mpy-cross + +-include boards/$(BOARD)/board.mk + +# qstr definitions (must come before including py.mk) +QSTR_DEFS = qstrdefsport.h + +# include py core make definitions +include $(TOP)/py/py.mk + +CROSS_COMPILE = arm-none-eabi- + +INC += -I. +INC += -I$(TOP) +INC += -I$(BUILD) +INC += -Iboards/$(BOARD) +INC += -Iboards/$(BOARD)/inc +INC += -Ichips/$(CHIP)/inc + +-include chips/$(CHIP)/chip.mk + +OPENOCD = openocd +OPENOCD_CONFIG = boards/$(BOARD)/openocd.cfg +DFU = dfu-util +DFUHDR = $(TOP)/tools/dfuheader.py +CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion +CFLAGS = $(INC) -Wall -Werror -std=c99 -nostdlib $(CFLAGS_CORTEX_M4) $(COPT) +LDFLAGS = -nostdlib -Lboards/$(BOARD) -Lchips/$(CHIP) -T chips/$(CHIP)/linker.lds -Map=$@.map --cref --gc-sections + +# Tune for Debugging or Optimization +ifeq ($(DEBUG), 1) +CFLAGS += -O0 -ggdb +else +CFLAGS += -Os -DNDEBUG +CFLAGS += -fdata-sections -ffunction-sections +endif + +CFLAGS += $(BOARD_CFLAGS) $(CHIP_CFLAGS) + +LIBS = $(shell $(CROSS_COMPILE)gcc $(CFLAGS_CORTEX_M4) --print-libgcc-file-name) + +SRC_C = \ + main.c \ + mphalport.c \ + $(wildcard boards/$(BOARD)/src/*.c) \ + $(wildcard chips/$(CHIP)/src/*.c) \ + lib/utils/stdout_helpers.c \ + lib/utils/pyexec.c \ + lib/libc/string0.c \ + lib/mp-readline/readline.c + +OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) + +all: $(BUILD)/firmware.bin + +$(BUILD)/firmware.elf: $(OBJ) + $(ECHO) "LINK $@" + $(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS) + $(Q)$(SIZE) $@ + +$(BUILD)/firmware.bin: $(BUILD)/firmware.elf + $(ECHO) "Create $@" + $(Q)$(OBJCOPY) -O binary -j .isr_vector -j .text -j .data $^ $(BUILD)/firmware.bin + +$(BUILD)/firmware.dfu: $(BUILD)/firmware.bin + $(ECHO) "Create $@" + $(Q)$(DFUHDR) $^ $@ + +deploy-dfu: $(BUILD)/firmware.dfu + $(ECHO) "Writing $< to the board via DFU" + $(Q)$(DFU) -R -D $^ + +deploy-openocd: $(BUILD)/firmware.bin + $(ECHO) "Writing $< to the board via OpenOCD" + $(Q)$(OPENOCD) -f $(OPENOCD_CONFIG) -c "lpc_flash $<" + +include $(TOP)/py/mkrules.mk diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/README b/ports/lpc/boards/lpc_board_ciaa_edu_4337/README new file mode 100644 index 0000000000000..fe41408c63698 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/README @@ -0,0 +1,3 @@ +LPCOpen v3.01 + +Release Date: 03/24/2017 diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk b/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk new file mode 100644 index 0000000000000..269024ad30ce6 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk @@ -0,0 +1,2 @@ +CHIP=lpc_chip_43xx +BOARD_CFLAGS=-D__USE_LPCOPEN diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board.h b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board.h new file mode 100644 index 0000000000000..c3ae0f8c22014 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board.h @@ -0,0 +1,178 @@ +/* + * @brief NGX Xplorer 4330 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_H_ +#define __BOARD_H_ + +#include "chip.h" +/* board_api.h is included at the bottom of this file after DEBUG setup */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_NGX_XPLORER_4330 LPC4330 NGX Xplorer board support software API functions + * @ingroup LPCOPEN_43XX_BOARD_NGX4330 + * The board support software API functions provide some simple abstracted + * functions used across multiple LPCOpen board examples. See @ref BOARD_COMMON_API + * for the functions defined by this board support layer.
+ * @{ + */ + +/** @defgroup BOARD_NGX_XPLORER_4330_OPTIONS BOARD: LPC4330 NGX Xplorer board options + * This board has options that configure its operation at build-time.
+ * @{ + */ + +/** Define DEBUG_ENABLE to enable IO via the DEBUGSTR, DEBUGOUT, and + DEBUGIN macros. If not defined, DEBUG* functions will be optimized + out of the code at build time. + */ +#define DEBUG_ENABLE + +/** Define DEBUG_SEMIHOSTING along with DEBUG_ENABLE to enable IO support + via semihosting. You may need to use a C library that supports + semihosting with this option. + */ +//#define DEBUG_SEMIHOSTING + +/** Board UART used for debug output and input using the DEBUG* macros. This + is also the port used for Board_UARTPutChar, Board_UARTGetChar, and + Board_UARTPutSTR functions. */ +#define DEBUG_UART LPC_USART2 + +/** + * @} + */ + +/* Board name */ +#define BOARD_CIAA_EDU_NXP_4337 + +/* Build for RMII interface */ +#define USE_RMII +#define BOARD_ENET_PHY_ADDR 0x00 + +#define LED_3 2 +#define LED_2 1 +#define LED_1 0 +#define LED_RED 3 +#define LED_GREEN 4 +#define LED_BLUE 5 + +/** + * @brief Sets up board specific I2C interface + * @param id : I2C Peripheral ID (I2C0, I2C1) + * @return Nothing + */ +void Board_I2C_Init(I2C_ID_T id); + +/** + * @brief Sets up I2C Fast Plus mode + * @param id : Must always be I2C0 + * @return Nothing + * @note This function must be called before calling + * Chip_I2C_SetClockRate() to set clock rates above + * normal range 100KHz to 400KHz. Only I2C0 supports + * this mode. + */ +STATIC INLINE void Board_I2C_EnableFastPlus(I2C_ID_T id) +{ + Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS); +} + +/** + * @brief Disable I2C Fast Plus mode and enables default mode + * @param id : Must always be I2C0 + * @return Nothing + * @sa Board_I2C_EnableFastPlus() + */ +STATIC INLINE void Board_I2C_DisableFastPlus(I2C_ID_T id) +{ + Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE); +} + +/** + * @brief Initializes board specific GPIO Interrupt + * @return Nothing + */ +void Board_GPIO_Int_Init(void); + +/** + * @brief Initialize pin muxing for SSP interface + * @param pSSP : Pointer to SSP interface to initialize + * @return Nothing + */ +void Board_SSP_Init(LPC_SSP_T *pSSP); + +/** + * @brief Returns the MAC address assigned to this board + * @param mcaddr : Pointer to 6-byte character array to populate with MAC address + * @return Nothing + */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr); + +/** + * @brief Initialize pin muxing for a UART + * @param pUART : Pointer to UART register block for UART pins to init + * @return Nothing + */ +void Board_UART_Init(LPC_USART_T *pUART); + +/** + * @brief Initialize pin muxing for SDMMC interface + * @return Nothing + */ +void Board_SDMMC_Init(void); + +/** + * @brief Initialize DAC + * @param pDAC : Pointer to DAC register interface used on this board + * @return Nothing + */ +void Board_DAC_Init(LPC_DAC_T *pDAC); + +/** + * @brief Initialize ADC + * @return Nothing + */ +STATIC INLINE void Board_ADC_Init(void){} + +/** + * @} + */ + +#include "board_api.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H_ */ diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board_api.h b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board_api.h new file mode 100644 index 0000000000000..5d804796af161 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/board_api.h @@ -0,0 +1,176 @@ +/* + * @brief Common board API functions + * + * @note + * Copyright(C) NXP Semiconductors, 2013 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_API_H_ +#define __BOARD_API_H_ + +#include "lpc_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_COMMON_API BOARD: Common board functions + * @ingroup BOARD_Common + * This file contains common board definitions that are shared across + * boards and devices. All of these functions do not need to be + * implemented for a specific board, but if they are implemented, they + * should use this API standard. + * @{ + */ + +/** + * @brief Setup and initialize hardware prior to call to main() + * @return None + * @note Board_SystemInit() is called prior to the application and sets up system + * clocking, memory, and any resources needed prior to the application + * starting. + */ +void Board_SystemInit(void); + +/** + * @brief Setup pin multiplexer per board schematics + * @return None + * @note Board_SetupMuxing() should be called from SystemInit() prior to application + * main() is called. So that the PINs are set in proper state. + */ +void Board_SetupMuxing(void); + +/** + * @brief Setup system clocking + * @return None + * @note This sets up board clocking. + */ +void Board_SetupClocking(void); + +/** + * @brief Setup external system memory + * @return None + * @note This function is typically called after pin mux setup and clock setup and + * sets up any external memory needed by the system (DRAM, SRAM, etc.). Not all + * boards need this function. + */ +void Board_SetupExtMemory(void); + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + * @return None + */ +void Board_Init(void); + +/** + * @brief Initializes board UART for output, required for printf redirection + * @return None + */ +void Board_Debug_Init(void); + +/** + * @brief Sends a single character on the UART, required for printf redirection + * @param ch : character to send + * @return None + */ +void Board_UARTPutChar(char ch); + +/** + * @brief Get a single character from the UART, required for scanf input + * @return EOF if not character was received, or character value + */ +int Board_UARTGetChar(void); + +/** + * @brief Prints a string to the UART + * @param str : Terminated string to output + * @return None + */ +void Board_UARTPutSTR(const char *str); + +/** + * @brief Sets the state of a board LED to on or off + * @param LEDNumber : LED number to set state for + * @param State : true for on, false for off + * @return None + */ +void Board_LED_Set(uint8_t LEDNumber, bool State); + +/** + * @brief Returns the current state of a board LED + * @param LEDNumber : LED number to set state for + * @return true if the LED is on, otherwise false + */ +bool Board_LED_Test(uint8_t LEDNumber); + +/** + * @brief Toggles the current state of a board LED + * @param LEDNumber : LED number to change state for + * @return None + */ +void Board_LED_Toggle(uint8_t LEDNumber); + +/** + * @brief Function prototype for a MS delay function. Board layers or example code may + * define this function as needed. + */ +typedef void (*p_msDelay_func_t)(uint32_t); + +/* The DEBUG* functions are selected based on system configuration. + Code that uses the DEBUG* functions will have their I/O routed to + the UART, semihosting, or nowhere. */ +#if defined(DEBUG_ENABLE) +#if defined(DEBUG_SEMIHOSTING) +#define DEBUGINIT() +#define DEBUGOUT(...) printf(__VA_ARGS__) +#define DEBUGSTR(str) printf(str) +#define DEBUGIN() (int) EOF + +#else +#define DEBUGINIT() Board_Debug_Init() +#define DEBUGOUT(...) printf(__VA_ARGS__) +#define DEBUGSTR(str) Board_UARTPutSTR(str) +#define DEBUGIN() Board_UARTGetChar() +#endif /* defined(DEBUG_SEMIHOSTING) */ + +#else +#define DEBUGINIT() +#define DEBUGOUT(...) +#define DEBUGSTR(str) +#define DEBUGIN() (int) EOF +#endif /* defined(DEBUG_ENABLE) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_API_H_ */ diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds b/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds new file mode 100644 index 0000000000000..ccbea32b5738e --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds @@ -0,0 +1,9 @@ +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x1a000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + + FLASHB (rx) : ORIGIN = 0x1b000000, LENGTH = 512K + RAMB (rwx) : ORIGIN = 0x10000000, LENGTH = 32K +} diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/mpconfigboard.h b/ports/lpc/boards/lpc_board_ciaa_edu_4337/mpconfigboard.h new file mode 100644 index 0000000000000..de38645fc4dcd --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/mpconfigboard.h @@ -0,0 +1,2 @@ +#define MICROPY_HW_BOARD_NAME "EDU-CIAA" +#define MICROPY_HW_MCU_NAME "LPC4337" diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg b/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg new file mode 100644 index 0000000000000..c5941312ee4b1 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg @@ -0,0 +1,79 @@ +############################################################################### +# +# Copyright 2014, Juan Cecconi (UTN-FRBA, Numetron) +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################### + +interface ftdi + +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0x0708 0xFFFB +ftdi_layout_signal nTRST -data 0x0100 +ftdi_layout_signal nSRST -data 0x0200 + +transport select jtag +adapter_khz 2000 + +set _CHIPNAME lpc4337 + +set _M4_JTAG_TAPID 0x4ba00477 +set _M0_JTAG_TAPID 0x0ba01477 + +jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M4_JTAG_TAPID +jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M0_JTAG_TAPID + +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 + +set _WORKAREASIZE 0x8000 +$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x1a000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 96000 calc_checksum + +reset_config none +cortex_m reset_config vectreset + +targets $_CHIPNAME.m4 + +$_CHIPNAME.m4 configure -event gdb-attach { + echo "Reset Halt, due to gdb attached...!" + reset halt +} + +init + +proc lpc_flash { BIN } { + init + halt 0 + flash write_image erase unlock $BIN 0x1a000000 bin + reset run + shutdown +} diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c new file mode 100644 index 0000000000000..f154aff18945a --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c @@ -0,0 +1,202 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" +#include "string.h" + +#include + +/** @ingroup BOARD_NGX_XPLORER_18304330 + * @{ + */ + +/* SDIO Data pin configuration bits */ +#define SDIO_DAT_PINCFG (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_PULLUP | SCU_MODE_FUNC7) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/* System configuration variables used by chip driver */ +const uint32_t ExtRateIn = 0; +const uint32_t OscRateIn = 12000000; + +typedef struct { + uint8_t port; + uint8_t pin; +} io_port_t; + +static const io_port_t gpioLEDBits[] = {{0, 14}, {1, 11}, {1, 12}, {5, 0}, {5, 1}, {5, 2}}; + +void Board_UART_Init(LPC_USART_T *pUART) +{ + Chip_SCU_PinMuxSet(0x7, 1, (SCU_MODE_INACT | SCU_MODE_FUNC6)); /* P7.1 : UART2_TXD */ + Chip_SCU_PinMuxSet(0x7, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6));/* P7.2 : UART2_RXD */ +} + +/* Initialize debug output via UART for board */ +void Board_Debug_Init(void) +{ +#if defined(DEBUG_UART) + Board_UART_Init(DEBUG_UART); + + Chip_UART_Init(DEBUG_UART); + Chip_UART_SetBaudFDR(DEBUG_UART, 115200); + Chip_UART_ConfigData(DEBUG_UART, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS); + + /* Enable UART Transmit */ + Chip_UART_TXEnable(DEBUG_UART); +#endif +} + +/* Sends a character on the UART */ +void Board_UARTPutChar(char ch) +{ +#if defined(DEBUG_UART) + /* Wait for space in FIFO */ + while ((Chip_UART_ReadLineStatus(DEBUG_UART) & UART_LSR_THRE) == 0) {} + Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch); +#endif +} + +/* Gets a character from the UART, returns EOF if no character is ready */ +int Board_UARTGetChar(void) +{ +#if defined(DEBUG_UART) + if (Chip_UART_ReadLineStatus(DEBUG_UART) & UART_LSR_RDR) { + return (int) Chip_UART_ReadByte(DEBUG_UART); + } +#endif + return EOF; +} + +/* Outputs a string on the debug UART */ +void Board_UARTPutSTR(const char *str) +{ +#if defined(DEBUG_UART) + while (*str != '\0') { + Board_UARTPutChar(*str++); + } +#endif +} + +static void Board_LED_Init() +{ + uint32_t idx; + + for (idx = 0; idx < (sizeof(gpioLEDBits) / sizeof(io_port_t)); ++idx) { + /* Set pin direction and init to off */ + Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, gpioLEDBits[idx].port, gpioLEDBits[idx].pin); + Chip_GPIO_SetPinState(LPC_GPIO_PORT, gpioLEDBits[idx].port, gpioLEDBits[idx].pin, (bool) false); + } +} + +void Board_LED_Set(uint8_t LEDNumber, bool On) +{ + if (LEDNumber < (sizeof(gpioLEDBits) / sizeof(io_port_t))) + Chip_GPIO_SetPinState(LPC_GPIO_PORT, gpioLEDBits[LEDNumber].port, gpioLEDBits[LEDNumber].pin, (bool) !On); +} + +bool Board_LED_Test(uint8_t LEDNumber) +{ + if (LEDNumber < (sizeof(gpioLEDBits) / sizeof(io_port_t))) + return (bool) !Chip_GPIO_GetPinState(LPC_GPIO_PORT, gpioLEDBits[LEDNumber].port, gpioLEDBits[LEDNumber].pin); + + return false; +} + +void Board_LED_Toggle(uint8_t LEDNumber) +{ + Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber)); +} + +/* Returns the MAC address assigned to this board */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr) +{ + uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56}; + + memcpy(mcaddr, boardmac, 6); +} + +/* Set up and initialize all required blocks and functions related to the + board hardware */ +void Board_Init(void) +{ + /* Sets up DEBUG UART */ + DEBUGINIT(); + + /* Initializes GPIO */ + Chip_GPIO_Init(LPC_GPIO_PORT); + + /* Initialize LEDs */ + Board_LED_Init(); + Chip_ENET_RMIIEnable(LPC_ETHERNET); +} + +void Board_I2C_Init(I2C_ID_T id) +{ + if (id == I2C1) { + /* Configure pin function for I2C1*/ + Chip_SCU_PinMuxSet(0x2, 3, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.3 : I2C1_SDA */ + Chip_SCU_PinMuxSet(0x2, 4, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.4 : I2C1_SCL */ + } else { + Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE); + } +} + +void Board_SDMMC_Init(void) +{ + Chip_SCU_PinMuxSet(0x1, 9, SDIO_DAT_PINCFG); /* P1.9 connected to SDIO_D0 */ + Chip_SCU_PinMuxSet(0x1, 10, SDIO_DAT_PINCFG); /* P1.10 connected to SDIO_D1 */ + Chip_SCU_PinMuxSet(0x1, 11, SDIO_DAT_PINCFG); /* P1.11 connected to SDIO_D2 */ + Chip_SCU_PinMuxSet(0x1, 12, SDIO_DAT_PINCFG); /* P1.12 connected to SDIO_D3 */ + + Chip_SCU_ClockPinMuxSet(2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* CLK2 connected to SDIO_CLK */ + Chip_SCU_PinMuxSet(0x1, 6, SDIO_DAT_PINCFG); /* P1.6 connected to SDIO_CMD */ + Chip_SCU_PinMuxSet(0x1, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7)); /* P1.13 connected to SDIO_CD */ +} + +void Board_SSP_Init(LPC_SSP_T *pSSP) +{ + if (pSSP == LPC_SSP1) { + Chip_SCU_PinMuxSet(0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC5)); /* P1.5 => SSEL1 */ + Chip_SCU_PinMuxSet(0xF, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC0)); /* PF.4 => SCK1 */ + Chip_SCU_PinMuxSet(0x1, 4, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5)); /* P1.4 => MOSI1 */ + Chip_SCU_PinMuxSet(0x1, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5)); /* P1.3 => MISO1 */ + } else { + return; + } +} + +/* Initialize DAC interface for the board */ +void Board_DAC_Init(LPC_DAC_T *pDAC) +{ + Chip_SCU_DAC_Analog_Config(); +} + +/** + * @} + */ diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board_sysinit.c b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board_sysinit.c new file mode 100644 index 0000000000000..ffb303d7c2607 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board_sysinit.c @@ -0,0 +1,159 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" + +/* The System initialization code is called prior to the application and + initializes the board for run-time operation. Board initialization + includes clock setup and default pin muxing configuration. */ + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CHIP_CGU_BASE_CLK_T clk; /* Base clock */ + CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +/* Initial base clock states are mostly on */ +STATIC const struct CLK_BASE_STATES InitClkStates[] = { + + /* Ethernet Clock base */ + {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false}, + {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false}, + + /* Clocks derived from dividers */ + {CLK_BASE_USB0, CLKIN_IDIVD, true, true} +}; + +STATIC const PINMUX_GRP_T pinmuxing[] = { + /* Board LEDs */ + {2, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + {2, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + {2, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + + /* UART 3 */ + {2, 3, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + {2, 4, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + + /* UART 2 */ + {7, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC6)}, + {7, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC6)}, + + /* CAN1 */ + {3, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + {3, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + + /* GPIO2 */ + {4, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 3, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 5, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 6, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 7, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + + /* GPIO5 */ + {4, 8, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + {4, 9, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + {4, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + + /* ENET Pin mux (RMII Pins) */ + {1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* RXD0 */ + {1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)}, /* CRS_DV */ + {1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* MDIO */ + {1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* TXD0 */ + {1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)}, /* REFCLK */ + {1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* TXD1 */ + {7, 7, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, /* MDC */ + {0, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, /* RXD1 */ + {0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, /* TXEN */ + +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Sets up system pin muxing */ +void Board_SetupMuxing(void) +{ + /* Setup system level pin muxing */ + Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); +} + +/* Set up and initialize clocking prior to call to main */ +void Board_SetupClocking(void) +{ + int i; + + /* Enable Flash acceleration and setup wait states */ + Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ); + + /* Setup System core frequency to MAX_CLOCK_FREQ */ + Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); + + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + + /* Reset and enable 32Khz oscillator */ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); + + /* Wait until stable */ + volatile unsigned int delay = 10000; + while (delay--); +} + +/* Set up and initialize hardware prior to call to main */ +void Board_SystemInit(void) +{ + /* Setup system clocking and memory. This is done early to allow the + application and tools to clear memory and use scatter loading to + external memory. */ + Board_SetupMuxing(); + Board_SetupClocking(); +} diff --git a/ports/lpc/chips/lpc_chip_43xx/README b/ports/lpc/chips/lpc_chip_43xx/README index f3a0855b909aa..aab28d9bf26df 100644 --- a/ports/lpc/chips/lpc_chip_43xx/README +++ b/ports/lpc/chips/lpc_chip_43xx/README @@ -1,2 +1 @@ -All files from LPCOpen v3.01 (Release Date: 03/24/2017), except: -- startup.c +LPCOpen v3.01 (Release Date: 03/24/2017) diff --git a/ports/lpc/chips/lpc_chip_43xx/chip.mk b/ports/lpc/chips/lpc_chip_43xx/chip.mk new file mode 100644 index 0000000000000..2bfe6b3cab1fd --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/chip.mk @@ -0,0 +1,2 @@ +INC += -Ichips/$(CHIP)/inc/config_43xx +CHIP_CFLAGS=-DCORE_M4 diff --git a/ports/lpc/chips/lpc_chip_43xx/linker.lds b/ports/lpc/chips/lpc_chip_43xx/linker.lds new file mode 100644 index 0000000000000..a4af7ef44be3e --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/linker.lds @@ -0,0 +1,60 @@ +/* + GNU linker script for LPC43xx +*/ + +INCLUDE memory.lds + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ + } >FLASH + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code */ + } >RAM + + /DISCARD/ : { + *(.ARM.attributes) + *(.ARM.exidx*) + } +} diff --git a/ports/lpc/chips/lpc_chip_43xx/src/startup_18xx_43xx.c b/ports/lpc/chips/lpc_chip_43xx/src/startup_18xx_43xx.c new file mode 100644 index 0000000000000..ee5c97557aa80 --- /dev/null +++ b/ports/lpc/chips/lpc_chip_43xx/src/startup_18xx_43xx.c @@ -0,0 +1,185 @@ +#include "chip.h" + +#define weak_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((weak, alias (#name))); + +void SysTick_Handler(void) { +} + +void Default_Handler(void) { + while (1); +} + +weak_alias(Default_Handler, NMI_Handler); +weak_alias(Default_Handler, HardFault_Handler); +weak_alias(Default_Handler, MemManage_Handler); +weak_alias(Default_Handler, BusFault_Handler); +weak_alias(Default_Handler, UsageFault_Handler); +weak_alias(Default_Handler, SVC_Handler); +weak_alias(Default_Handler, DebugMon_Handler); +weak_alias(Default_Handler, PendSV_Handler); +weak_alias(Default_Handler, IntDefaultHandler); + +weak_alias(Default_Handler, DAC_IRQHandler); +#if defined (__USE_LPCOPEN) +weak_alias(Default_Handler, M0APP_IRQHandler); +#else +weak_alias(Default_Handler, M0CORE_IRQHandler); +#endif +weak_alias(Default_Handler, DMA_IRQHandler); +weak_alias(Default_Handler, FLASH_EEPROM_IRQHandler); +weak_alias(Default_Handler, ETH_IRQHandler); +weak_alias(Default_Handler, SDIO_IRQHandler); +weak_alias(Default_Handler, LCD_IRQHandler); +weak_alias(Default_Handler, USB0_IRQHandler); +weak_alias(Default_Handler, USB1_IRQHandler); +weak_alias(Default_Handler, SCT_IRQHandler); +weak_alias(Default_Handler, RIT_IRQHandler); +weak_alias(Default_Handler, TIMER0_IRQHandler); +weak_alias(Default_Handler, TIMER1_IRQHandler); +weak_alias(Default_Handler, TIMER2_IRQHandler); +weak_alias(Default_Handler, TIMER3_IRQHandler); +weak_alias(Default_Handler, MCPWM_IRQHandler); +weak_alias(Default_Handler, ADC0_IRQHandler); +weak_alias(Default_Handler, I2C0_IRQHandler); +weak_alias(Default_Handler, SPI_IRQHandler); +weak_alias(Default_Handler, I2C1_IRQHandler); +weak_alias(Default_Handler, ADC1_IRQHandler); +weak_alias(Default_Handler, SSP0_IRQHandler); +weak_alias(Default_Handler, SSP1_IRQHandler); +weak_alias(Default_Handler, UART0_IRQHandler); +weak_alias(Default_Handler, UART1_IRQHandler); +weak_alias(Default_Handler, UART2_IRQHandler); +weak_alias(Default_Handler, UART3_IRQHandler); +weak_alias(Default_Handler, I2S0_IRQHandler); +weak_alias(Default_Handler, I2S1_IRQHandler); +weak_alias(Default_Handler, SPIFI_IRQHandler); +weak_alias(Default_Handler, SGPIO_IRQHandler); +weak_alias(Default_Handler, GPIO0_IRQHandler); +weak_alias(Default_Handler, GPIO1_IRQHandler); +weak_alias(Default_Handler, GPIO2_IRQHandler); +weak_alias(Default_Handler, GPIO3_IRQHandler); +weak_alias(Default_Handler, GPIO4_IRQHandler); +weak_alias(Default_Handler, GPIO5_IRQHandler); +weak_alias(Default_Handler, GPIO6_IRQHandler); +weak_alias(Default_Handler, GPIO7_IRQHandler); +weak_alias(Default_Handler, GINT0_IRQHandler); +weak_alias(Default_Handler, GINT1_IRQHandler); +weak_alias(Default_Handler, EVRT_IRQHandler); +weak_alias(Default_Handler, CAN1_IRQHandler); +#if defined (__USE_LPCOPEN) +weak_alias(Default_Handler, ADCHS_IRQHandler); +#else +weak_alias(Default_Handler, VADC_IRQHandler); +#endif +weak_alias(Default_Handler, ATIMER_IRQHandler); +weak_alias(Default_Handler, RTC_IRQHandler); +weak_alias(Default_Handler, WDT_IRQHandler); +weak_alias(Default_Handler, M0SUB_IRQHandler); +weak_alias(Default_Handler, CAN0_IRQHandler); +weak_alias(Default_Handler, QEI_IRQHandler); + +extern unsigned int _estack, _sidata, _sdata, _edata, _sbss, _ebss; + +void Reset_Handler(void) { + + __asm volatile ("cpsid i"); + Chip_RGU_TriggerResetAll(); + NVIC_ClearAll(); + __asm volatile ("cpsie i"); + + // copy .data section from flash to RAM + for (unsigned int *src = &_sidata, *dest = &_sdata; dest < &_edata;) { + *dest++ = *src++; + } + + // zero out .bss section + for (unsigned int *dest = &_sbss; dest < &_ebss;) { + *dest++ = 0; + } + + int main(void); + main(); +} + +extern void (* const g_pfnVectors[])(void); +__attribute__ ((used,section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + (void*)&_estack, // The initial stack pointer + Reset_Handler, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + 0, //__valid_user_code_checksum, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + DAC_IRQHandler, // 16 +#if defined (__USE_LPCOPEN) + M0APP_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY) +#else + M0CORE_IRQHandler, // 17 +#endif + DMA_IRQHandler, // 18 + 0, // 19 + FLASH_EEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts + ETH_IRQHandler, // 21 + SDIO_IRQHandler, // 22 + LCD_IRQHandler, // 23 + USB0_IRQHandler, // 24 + USB1_IRQHandler, // 25 + SCT_IRQHandler, // 26 + RIT_IRQHandler, // 27 + TIMER0_IRQHandler, // 28 + TIMER1_IRQHandler, // 29 + TIMER2_IRQHandler, // 30 + TIMER3_IRQHandler, // 31 + MCPWM_IRQHandler, // 32 + ADC0_IRQHandler, // 33 + I2C0_IRQHandler, // 34 + I2C1_IRQHandler, // 35 + SPI_IRQHandler, // 36 + ADC1_IRQHandler, // 37 + SSP0_IRQHandler, // 38 + SSP1_IRQHandler, // 39 + UART0_IRQHandler, // 40 + UART1_IRQHandler, // 41 + UART2_IRQHandler, // 42 + UART3_IRQHandler, // 43 + I2S0_IRQHandler, // 44 + I2S1_IRQHandler, // 45 + SPIFI_IRQHandler, // 46 + SGPIO_IRQHandler, // 47 + GPIO0_IRQHandler, // 48 + GPIO1_IRQHandler, // 49 + GPIO2_IRQHandler, // 50 + GPIO3_IRQHandler, // 51 + GPIO4_IRQHandler, // 52 + GPIO5_IRQHandler, // 53 + GPIO6_IRQHandler, // 54 + GPIO7_IRQHandler, // 55 + GINT0_IRQHandler, // 56 + GINT1_IRQHandler, // 57 + EVRT_IRQHandler, // 58 + CAN1_IRQHandler, // 59 + 0, // 60 +#if defined (__USE_LPCOPEN) + ADCHS_IRQHandler, // 61 ADCHS combined interrupt +#else + VADC_IRQHandler, // 61 +#endif + ATIMER_IRQHandler, // 62 + RTC_IRQHandler, // 63 + 0, // 64 + WDT_IRQHandler, // 65 + M0SUB_IRQHandler, // 66 + CAN0_IRQHandler, // 67 + QEI_IRQHandler, // 68 +}; diff --git a/ports/lpc/main.c b/ports/lpc/main.c new file mode 100644 index 0000000000000..2fb210cf5f9f8 --- /dev/null +++ b/ports/lpc/main.c @@ -0,0 +1,92 @@ +#include +#include +#include + +#include "py/nlr.h" +#include "py/compile.h" +#include "py/runtime.h" +#include "py/repl.h" +#include "py/gc.h" +#include "py/mperrno.h" +#include "lib/utils/pyexec.h" + +#include "board.h" + +void do_str(const char *src, mp_parse_input_kind_t input_kind) { + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); + qstr source_name = lex->source_name; + mp_parse_tree_t parse_tree = mp_parse(lex, input_kind); + mp_obj_t module_fun = mp_compile(&parse_tree, source_name, MP_EMIT_OPT_NONE, true); + mp_call_function_0(module_fun); + nlr_pop(); + } else { + // uncaught exception + mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val); + } +} + +static char *stack_top; +static char heap[2048]; + +int main(void) { + + while(1) { + int stack_dummy; + stack_top = (char*)&stack_dummy; + + Board_SystemInit(); + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock/1000); + Board_Init(); + + gc_init(heap, heap + sizeof(heap)); + + mp_init(); + + pyexec_friendly_repl(); + + mp_deinit(); + } + + return 0; +} + +void gc_collect(void) { + // WARNING: This gc_collect implementation doesn't try to get root + // pointers from CPU registers, and thus may function incorrectly. + void *dummy; + gc_collect_start(); + gc_collect_root(&dummy, ((mp_uint_t)stack_top - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); + gc_collect_end(); + gc_dump_info(); +} + +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + mp_raise_OSError(MP_ENOENT); +} + +mp_import_stat_t mp_import_stat(const char *path) { + return MP_IMPORT_STAT_NO_EXIST; +} + +mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); + +void nlr_jump_fail(void *val) { + while (1); +} + +void NORETURN __fatal_error(const char *msg) { + while (1); +} + +#ifndef NDEBUG +void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { + printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); + __fatal_error("Assertion failed"); +} +#endif diff --git a/ports/lpc/mpconfigport.h b/ports/lpc/mpconfigport.h new file mode 100644 index 0000000000000..13020b6a8a41a --- /dev/null +++ b/ports/lpc/mpconfigport.h @@ -0,0 +1,90 @@ +#include +#include "mpconfigboard.h" + +// options to control how MicroPython is built + +#define MICROPY_ENABLE_COMPILER (1) +#define MICROPY_QSTR_BYTES_IN_HASH (1) +#define MICROPY_ALLOC_PATH_MAX (256) +#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16) +#define MICROPY_EMIT_X64 (0) +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_COMP_MODULE_CONST (0) +#define MICROPY_COMP_CONST (0) +#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (0) +#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) +#define MICROPY_MEM_STATS (0) +#define MICROPY_DEBUG_PRINTERS (0) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_GC_ALLOC_THRESHOLD (0) +#define MICROPY_REPL_EVENT_DRIVEN (0) +#define MICROPY_HELPER_REPL (1) +#define MICROPY_HELPER_LEXER_UNIX (0) +#define MICROPY_ENABLE_SOURCE_LINE (0) +#define MICROPY_ENABLE_DOC_STRING (0) +#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_TERSE) +#define MICROPY_BUILTIN_METHOD_CHECK_SELF_ARG (0) +#define MICROPY_PY_ASYNC_AWAIT (0) +#define MICROPY_PY_BUILTINS_BYTEARRAY (1) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (1) +#define MICROPY_PY_BUILTINS_ENUMERATE (1) +#define MICROPY_PY_BUILTINS_FILTER (1) +#define MICROPY_PY_BUILTINS_FROZENSET (1) +#define MICROPY_PY_BUILTINS_REVERSED (1) +#define MICROPY_PY_BUILTINS_SET (1) +#define MICROPY_PY_BUILTINS_SLICE (1) +#define MICROPY_PY_BUILTINS_PROPERTY (1) +#define MICROPY_PY_BUILTINS_MIN_MAX (1) +#define MICROPY_PY___FILE__ (0) +#define MICROPY_PY_GC (1) +#define MICROPY_PY_ARRAY (1) +#define MICROPY_PY_ATTRTUPLE (1) +#define MICROPY_PY_COLLECTIONS (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_CMATH (1) +#define MICROPY_PY_IO (1) +#define MICROPY_PY_STRUCT (1) +#define MICROPY_PY_SYS (0) +#define MICROPY_MODULE_FROZEN_MPY (0) +#define MICROPY_CPYTHON_COMPAT (0) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_NONE) +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) + +// type definitions for the specific machine + +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) + +// This port is intended to be 32-bit, but unfortunately, int32_t for +// different targets may be defined in different ways - either as int +// or as long. This requires different printf formatting specifiers +// to print such value. So, we avoid int32_t and use int directly. +#define UINT_FMT "%u" +#define INT_FMT "%d" +typedef int mp_int_t; // must be pointer size +typedef unsigned mp_uint_t; // must be pointer size + +typedef long mp_off_t; + +#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) + +// extra built in names to add to the global namespace +#define MICROPY_PORT_BUILTINS \ + { MP_ROM_QSTR(MP_QSTR_open), MP_ROM_PTR(&mp_builtin_open_obj) }, + +// We need to provide a declaration/definition of alloca() +#include + +#ifdef __linux__ +#define MICROPY_MIN_USE_STDOUT (1) +#endif + +#ifdef __thumb__ +#define MICROPY_MIN_USE_CORTEX_CPU (1) +#define MICROPY_MIN_USE_STM32_MCU (1) +#endif + +#define MP_STATE_PORT MP_STATE_VM + +#define MICROPY_PORT_ROOT_POINTERS \ + const char *readline_hist[8]; diff --git a/ports/lpc/mphalport.c b/ports/lpc/mphalport.c new file mode 100644 index 0000000000000..b303b2d48ef1b --- /dev/null +++ b/ports/lpc/mphalport.c @@ -0,0 +1,17 @@ +#include "py/mphal.h" +#include "board.h" + +int mp_hal_stdin_rx_chr(void) { + int c; + do { + c = Board_UARTGetChar(); + } while (c == EOF); + return c; +} + +void mp_hal_stdout_tx_strn(const char *str, size_t len) { + for (; len > 0; --len) { + Board_UARTPutChar(*str++); + } +} + diff --git a/ports/lpc/mphalport.h b/ports/lpc/mphalport.h new file mode 100644 index 0000000000000..60d68bd2d6d50 --- /dev/null +++ b/ports/lpc/mphalport.h @@ -0,0 +1,2 @@ +static inline mp_uint_t mp_hal_ticks_ms(void) { return 0; } +static inline void mp_hal_set_interrupt_char(char c) {} diff --git a/ports/lpc/qstrdefsport.h b/ports/lpc/qstrdefsport.h new file mode 100644 index 0000000000000..de08c54f87f8f --- /dev/null +++ b/ports/lpc/qstrdefsport.h @@ -0,0 +1,4 @@ +// qstrs specific to this port +array +bytearray +memory diff --git a/tools/dfuheader.py b/tools/dfuheader.py new file mode 100755 index 0000000000000..434eb24df4d04 --- /dev/null +++ b/tools/dfuheader.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python +import os.path +import struct +import sys + +infile=sys.argv[1] +outfile=sys.argv[2] +with open(outfile, "wb") as fout: + x = struct.pack('