From 75414cb98405feafa884fd83baa14cfae7cecc08 Mon Sep 17 00:00:00 2001
From: Sayed Adel <seiko@imavr.com>
Date: Mon, 20 Nov 2023 03:06:59 +0200
Subject: [PATCH] BUG: Fix single to half-precision conversion on PPC64/VSX3

  This fix respects the lane order with regards to big/little-endians.
---
 numpy/core/src/common/half.hpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/numpy/core/src/common/half.hpp b/numpy/core/src/common/half.hpp
index ff9a547766d3..484750ad84cd 100644
--- a/numpy/core/src/common/half.hpp
+++ b/numpy/core/src/common/half.hpp
@@ -59,7 +59,11 @@ class Half final {
         __vector float vf32 = vec_splats(f);
         __vector unsigned short vf16;
         __asm__ __volatile__ ("xvcvsphp %x0,%x1" : "=wa" (vf16) : "wa" (vf32));
+        #ifdef __BIG_ENDIAN__
+        bits_ = vec_extract(vf16, 1);
+        #else
         bits_ = vec_extract(vf16, 0);
+        #endif
     #else
         bits_ = half_private::FromFloatBits(BitCast<uint32_t>(f));
     #endif