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oshears/README.md

About Osaze Shears ๐Ÿ˜Ž

Hi! I am a research computer engineer at University of Southern California's (USC) Information Sciences Institute (ISI) in Arlington, VA. I am is passionate about many engineering and computational concepts including embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Applications that interest me range from interactive technologies (Virtual and Mixed Reality) to bioinformatics!

I maintain a list of my professionala experiences and projects at my main website: oshears.github.io.

In my free time I work on game development projects with other artists and devs to develop multiplayer, VR, and 3D games. Updates are posted to my studio website: OSGames.


FPGA-ASIC Projects ๐Ÿ’ป

My FPGA-ASIC design projects include the following:

Experienced Open-Source Projects ๐Ÿง 

I have had experience working with the following open-source hardware development projects:

  • OpenFPGA: Used to create and analyze FPGA architectures and bitstreams for custom architectures.
  • BladeRF: An open-source software defined radio (SDR).
  • Project X-Ray: Reverse engineering Xilinx Series 7 bitstreams.
  • Embedded Scalable Platforms (ESP): Open-source NoC generator with an Arianne RISC-V CPU and FPGA emulation capability.
  • Xilinx FINN: A neural netork compiler for Xilinx FPGAs.
  • RapidWright: A Java-based placement and routing tool for Xilinx FPGAs.
  • CocoTB: A Python-based RTL verification framework using the Verilog programming interface (VPI).

Game Development Projects ๐ŸŽฎ

My game development projects include:


Collaborations ๐Ÿค๐Ÿฝ

I am actively seeking opportunities to collaborate on game design projects related to 3D, multiplayer, and virtual reality! Feel free to reach out by emailing [email protected].


My Website ๐ŸŒ

oshears.github.io


My YouTube Channel ๐ŸŽฅ

https://www.youtube.com/@osazeshears

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  1. BindsNET-Self-Documentation BindsNET-Self-Documentation Public archive

    Documentation created while learning BindsNET SNN Framework

    Jupyter Notebook 7 1

  2. neuromorphic_asic_bridge neuromorphic_asic_bridge Public

    The HDL FPGA Module to Interact with the MICS Neuromorphic Reservoir Computing ASIC

    VHDL 3

  3. fpga_snn_models fpga_snn_models Public archive

    A repository FPGA-friendly SNN models

    Python 35 6

  4. SNN-FPGA-Implementation SNN-FPGA-Implementation Public archive

    SystemVerilog 20 1

  5. bladerf_dfr_accelerator bladerf_dfr_accelerator Public

    A project to implement a delayed feedback reservoir on the bladeRF 2.0 micro software defined radio (SDR) FPGA.

    SystemVerilog 4 2

  6. hybrid_dfr_system hybrid_dfr_system Public archive

    The FPGA design for MICS' Hybrid DFR System

    VHDL 4 1