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Chun-Jie Chenmbgg
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soc: mediatek: pm-domains: Add support for mt8186
Add power domain control data in mt8186. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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‎drivers/soc/mediatek/mt8186-pm-domains.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chun-Jie Chen <[email protected]>
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*/
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#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8186-power.h>
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/*
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* MT8186 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
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[MT8186_POWER_DOMAIN_MFG0] = {
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.name = "mfg0",
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.sta_mask = BIT(2),
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.ctl_offs = 0x308,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8186_POWER_DOMAIN_MFG1] = {
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.name = "mfg1",
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.sta_mask = BIT(3),
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.ctl_offs = 0x30c,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_MFG2] = {
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.name = "mfg2",
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.sta_mask = BIT(4),
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.ctl_offs = 0x310,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_MFG3] = {
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.name = "mfg3",
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.sta_mask = BIT(5),
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.ctl_offs = 0x314,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_SSUSB] = {
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.name = "ssusb",
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.sta_mask = BIT(20),
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.ctl_offs = 0x9F0,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8186_POWER_DOMAIN_SSUSB_P1] = {
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.name = "ssusb_p1",
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.sta_mask = BIT(19),
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.ctl_offs = 0x9F4,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8186_POWER_DOMAIN_DIS] = {
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.name = "dis",
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.sta_mask = BIT(21),
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.ctl_offs = 0x354,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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},
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},
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[MT8186_POWER_DOMAIN_IMG] = {
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.name = "img",
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.sta_mask = BIT(13),
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.ctl_offs = 0x334,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_IMG2] = {
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.name = "img2",
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.sta_mask = BIT(14),
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.ctl_offs = 0x338,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_IPE] = {
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.name = "ipe",
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.sta_mask = BIT(15),
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.ctl_offs = 0x33C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM] = {
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.name = "cam",
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.sta_mask = BIT(23),
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.ctl_offs = 0x35C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM_RAWA] = {
186+
.name = "cam_rawa",
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.sta_mask = BIT(24),
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.ctl_offs = 0x360,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM_RAWB] = {
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.name = "cam_rawb",
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.sta_mask = BIT(25),
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.ctl_offs = 0x364,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_VENC] = {
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.name = "venc",
207+
.sta_mask = BIT(18),
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.ctl_offs = 0x348,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = BIT(16),
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.ctl_offs = 0x340,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
244+
},
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[MT8186_POWER_DOMAIN_WPE] = {
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.name = "wpe",
247+
.sta_mask = BIT(0),
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.ctl_offs = 0x3F8,
249+
.pwr_sta_offs = 0x16C,
250+
.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
253+
.bp_infracfg = {
254+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
255+
MT8186_TOP_AXI_PROT_EN_2_SET,
256+
MT8186_TOP_AXI_PROT_EN_2_CLR,
257+
MT8186_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
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MT8186_TOP_AXI_PROT_EN_2_SET,
260+
MT8186_TOP_AXI_PROT_EN_2_CLR,
261+
MT8186_TOP_AXI_PROT_EN_2_STA),
262+
},
263+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
264+
},
265+
[MT8186_POWER_DOMAIN_CONN_ON] = {
266+
.name = "conn_on",
267+
.sta_mask = BIT(1),
268+
.ctl_offs = 0x304,
269+
.pwr_sta_offs = 0x16C,
270+
.pwr_sta2nd_offs = 0x170,
271+
.bp_infracfg = {
272+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
273+
MT8186_TOP_AXI_PROT_EN_1_SET,
274+
MT8186_TOP_AXI_PROT_EN_1_CLR,
275+
MT8186_TOP_AXI_PROT_EN_1_STA),
276+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
277+
MT8186_TOP_AXI_PROT_EN_SET,
278+
MT8186_TOP_AXI_PROT_EN_CLR,
279+
MT8186_TOP_AXI_PROT_EN_STA),
280+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
281+
MT8186_TOP_AXI_PROT_EN_SET,
282+
MT8186_TOP_AXI_PROT_EN_CLR,
283+
MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
285+
MT8186_TOP_AXI_PROT_EN_SET,
286+
MT8186_TOP_AXI_PROT_EN_CLR,
287+
MT8186_TOP_AXI_PROT_EN_STA),
288+
},
289+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
290+
},
291+
[MT8186_POWER_DOMAIN_CSIRX_TOP] = {
292+
.name = "csirx_top",
293+
.sta_mask = BIT(6),
294+
.ctl_offs = 0x318,
295+
.pwr_sta_offs = 0x16C,
296+
.pwr_sta2nd_offs = 0x170,
297+
.sram_pdn_bits = BIT(8),
298+
.sram_pdn_ack_bits = BIT(12),
299+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
300+
},
301+
[MT8186_POWER_DOMAIN_ADSP_AO] = {
302+
.name = "adsp_ao",
303+
.sta_mask = BIT(17),
304+
.ctl_offs = 0x9FC,
305+
.pwr_sta_offs = 0x16C,
306+
.pwr_sta2nd_offs = 0x170,
307+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
308+
},
309+
[MT8186_POWER_DOMAIN_ADSP_INFRA] = {
310+
.name = "adsp_infra",
311+
.sta_mask = BIT(10),
312+
.ctl_offs = 0x9F8,
313+
.pwr_sta_offs = 0x16C,
314+
.pwr_sta2nd_offs = 0x170,
315+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
316+
},
317+
[MT8186_POWER_DOMAIN_ADSP_TOP] = {
318+
.name = "adsp_top",
319+
.sta_mask = BIT(31),
320+
.ctl_offs = 0x3E4,
321+
.pwr_sta_offs = 0x16C,
322+
.pwr_sta2nd_offs = 0x170,
323+
.sram_pdn_bits = BIT(8),
324+
.sram_pdn_ack_bits = BIT(12),
325+
.bp_infracfg = {
326+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
327+
MT8186_TOP_AXI_PROT_EN_3_SET,
328+
MT8186_TOP_AXI_PROT_EN_3_CLR,
329+
MT8186_TOP_AXI_PROT_EN_3_STA),
330+
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
331+
MT8186_TOP_AXI_PROT_EN_3_SET,
332+
MT8186_TOP_AXI_PROT_EN_3_CLR,
333+
MT8186_TOP_AXI_PROT_EN_3_STA),
334+
},
335+
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
336+
},
337+
};
338+
339+
static const struct scpsys_soc_data mt8186_scpsys_data = {
340+
.domains_data = scpsys_domain_data_mt8186,
341+
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),
342+
};
343+
344+
#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */

‎drivers/soc/mediatek/mtk-pm-domains.c‎

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Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "mt8167-pm-domains.h"
2020
#include "mt8173-pm-domains.h"
2121
#include "mt8183-pm-domains.h"
22+
#include "mt8186-pm-domains.h"
2223
#include "mt8192-pm-domains.h"
2324
#include "mt8195-pm-domains.h"
2425

@@ -566,6 +567,10 @@ static const struct of_device_id scpsys_of_match[] = {
566567
.compatible = "mediatek,mt8183-power-controller",
567568
.data = &mt8183_scpsys_data,
568569
},
570+
{
571+
.compatible = "mediatek,mt8186-power-controller",
572+
.data = &mt8186_scpsys_data,
573+
},
569574
{
570575
.compatible = "mediatek,mt8192-power-controller",
571576
.data = &mt8192_scpsys_data,

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