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Tariq Toukandavem330
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net/mlx5e: Added ICO SQs
Added ICO (Internal Control Operations) SQ per channel to be used for driver internal operations such as memory registration for fragmented memory and nop requests upon ifconfig up. Signed-off-by: Tariq Toukan <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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4 files changed

+174
-25
lines changed

4 files changed

+174
-25
lines changed

drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -488,6 +488,11 @@ enum {
488488
MLX5E_SQ_STATE_BF_ENABLE,
489489
};
490490

491+
struct mlx5e_ico_wqe_info {
492+
u8 opcode;
493+
u8 num_wqebbs;
494+
};
495+
491496
struct mlx5e_sq {
492497
/* data path */
493498

@@ -529,6 +534,7 @@ struct mlx5e_sq {
529534
struct mlx5_uar uar;
530535
struct mlx5e_channel *channel;
531536
int tc;
537+
struct mlx5e_ico_wqe_info *ico_wqe_info;
532538
} ____cacheline_aligned_in_smp;
533539

534540
static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
@@ -545,6 +551,7 @@ struct mlx5e_channel {
545551
/* data path */
546552
struct mlx5e_rq rq;
547553
struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
554+
struct mlx5e_sq icosq; /* internal control operations */
548555
struct napi_struct napi;
549556
struct device *pdev;
550557
struct net_device *netdev;

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 111 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ struct mlx5e_sq_param {
4848
u32 sqc[MLX5_ST_SZ_DW(sqc)];
4949
struct mlx5_wq_param wq;
5050
u16 max_inline;
51+
bool icosq;
5152
};
5253

5354
struct mlx5e_cq_param {
@@ -59,8 +60,10 @@ struct mlx5e_cq_param {
5960
struct mlx5e_channel_param {
6061
struct mlx5e_rq_param rq;
6162
struct mlx5e_sq_param sq;
63+
struct mlx5e_sq_param icosq;
6264
struct mlx5e_cq_param rx_cq;
6365
struct mlx5e_cq_param tx_cq;
66+
struct mlx5e_cq_param icosq_cq;
6467
};
6568

6669
static void mlx5e_update_carrier(struct mlx5e_priv *priv)
@@ -502,6 +505,8 @@ static int mlx5e_open_rq(struct mlx5e_channel *c,
502505
struct mlx5e_rq_param *param,
503506
struct mlx5e_rq *rq)
504507
{
508+
struct mlx5e_sq *sq = &c->icosq;
509+
u16 pi = sq->pc & sq->wq.sz_m1;
505510
int err;
506511

507512
err = mlx5e_create_rq(c, param, rq);
@@ -517,7 +522,10 @@ static int mlx5e_open_rq(struct mlx5e_channel *c,
517522
goto err_disable_rq;
518523

519524
set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
520-
mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
525+
526+
sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
527+
sq->ico_wqe_info[pi].num_wqebbs = 1;
528+
mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
521529

522530
return 0;
523531

@@ -583,7 +591,6 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
583591

584592
void *sqc = param->sqc;
585593
void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
586-
int txq_ix;
587594
int err;
588595

589596
err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
@@ -611,8 +618,24 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
611618
if (err)
612619
goto err_sq_wq_destroy;
613620

614-
txq_ix = c->ix + tc * priv->params.num_channels;
615-
sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
621+
if (param->icosq) {
622+
u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
623+
624+
sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
625+
wq_sz,
626+
GFP_KERNEL,
627+
cpu_to_node(c->cpu));
628+
if (!sq->ico_wqe_info) {
629+
err = -ENOMEM;
630+
goto err_free_sq_db;
631+
}
632+
} else {
633+
int txq_ix;
634+
635+
txq_ix = c->ix + tc * priv->params.num_channels;
636+
sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
637+
priv->txq_to_sq_map[txq_ix] = sq;
638+
}
616639

617640
sq->pdev = c->pdev;
618641
sq->tstamp = &priv->tstamp;
@@ -621,10 +644,12 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
621644
sq->tc = tc;
622645
sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
623646
sq->bf_budget = MLX5E_SQ_BF_BUDGET;
624-
priv->txq_to_sq_map[txq_ix] = sq;
625647

626648
return 0;
627649

650+
err_free_sq_db:
651+
mlx5e_free_sq_db(sq);
652+
628653
err_sq_wq_destroy:
629654
mlx5_wq_destroy(&sq->wq_ctrl);
630655

@@ -639,6 +664,7 @@ static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
639664
struct mlx5e_channel *c = sq->channel;
640665
struct mlx5e_priv *priv = c->priv;
641666

667+
kfree(sq->ico_wqe_info);
642668
mlx5e_free_sq_db(sq);
643669
mlx5_wq_destroy(&sq->wq_ctrl);
644670
mlx5_unmap_free_uar(priv->mdev, &sq->uar);
@@ -667,10 +693,10 @@ static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
667693

668694
memcpy(sqc, param->sqc, sizeof(param->sqc));
669695

670-
MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
671-
MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
696+
MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
697+
MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
672698
MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
673-
MLX5_SET(sqc, sqc, tis_lst_sz, 1);
699+
MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
674700
MLX5_SET(sqc, sqc, flush_in_error_en, 1);
675701

676702
MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
@@ -745,9 +771,11 @@ static int mlx5e_open_sq(struct mlx5e_channel *c,
745771
if (err)
746772
goto err_disable_sq;
747773

748-
set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
749-
netdev_tx_reset_queue(sq->txq);
750-
netif_tx_start_queue(sq->txq);
774+
if (sq->txq) {
775+
set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
776+
netdev_tx_reset_queue(sq->txq);
777+
netif_tx_start_queue(sq->txq);
778+
}
751779

752780
return 0;
753781

@@ -768,15 +796,19 @@ static inline void netif_tx_disable_queue(struct netdev_queue *txq)
768796

769797
static void mlx5e_close_sq(struct mlx5e_sq *sq)
770798
{
771-
clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
772-
napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
773-
netif_tx_disable_queue(sq->txq);
799+
if (sq->txq) {
800+
clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
801+
/* prevent netif_tx_wake_queue */
802+
napi_synchronize(&sq->channel->napi);
803+
netif_tx_disable_queue(sq->txq);
774804

775-
/* ensure hw is notified of all pending wqes */
776-
if (mlx5e_sq_has_room_for(sq, 1))
777-
mlx5e_send_nop(sq, true);
805+
/* ensure hw is notified of all pending wqes */
806+
if (mlx5e_sq_has_room_for(sq, 1))
807+
mlx5e_send_nop(sq, true);
808+
809+
mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
810+
}
778811

779-
mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
780812
while (sq->cc != sq->pc) /* wait till sq is empty */
781813
msleep(20);
782814

@@ -1030,10 +1062,14 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
10301062

10311063
netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
10321064

1033-
err = mlx5e_open_tx_cqs(c, cparam);
1065+
err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
10341066
if (err)
10351067
goto err_napi_del;
10361068

1069+
err = mlx5e_open_tx_cqs(c, cparam);
1070+
if (err)
1071+
goto err_close_icosq_cq;
1072+
10371073
err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
10381074
priv->params.rx_cq_moderation_usec,
10391075
priv->params.rx_cq_moderation_pkts);
@@ -1042,10 +1078,14 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
10421078

10431079
napi_enable(&c->napi);
10441080

1045-
err = mlx5e_open_sqs(c, cparam);
1081+
err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
10461082
if (err)
10471083
goto err_disable_napi;
10481084

1085+
err = mlx5e_open_sqs(c, cparam);
1086+
if (err)
1087+
goto err_close_icosq;
1088+
10491089
err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
10501090
if (err)
10511091
goto err_close_sqs;
@@ -1058,13 +1098,19 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
10581098
err_close_sqs:
10591099
mlx5e_close_sqs(c);
10601100

1101+
err_close_icosq:
1102+
mlx5e_close_sq(&c->icosq);
1103+
10611104
err_disable_napi:
10621105
napi_disable(&c->napi);
10631106
mlx5e_close_cq(&c->rq.cq);
10641107

10651108
err_close_tx_cqs:
10661109
mlx5e_close_tx_cqs(c);
10671110

1111+
err_close_icosq_cq:
1112+
mlx5e_close_cq(&c->icosq.cq);
1113+
10681114
err_napi_del:
10691115
netif_napi_del(&c->napi);
10701116
napi_hash_del(&c->napi);
@@ -1077,9 +1123,11 @@ static void mlx5e_close_channel(struct mlx5e_channel *c)
10771123
{
10781124
mlx5e_close_rq(&c->rq);
10791125
mlx5e_close_sqs(c);
1126+
mlx5e_close_sq(&c->icosq);
10801127
napi_disable(&c->napi);
10811128
mlx5e_close_cq(&c->rq.cq);
10821129
mlx5e_close_tx_cqs(c);
1130+
mlx5e_close_cq(&c->icosq.cq);
10831131
netif_napi_del(&c->napi);
10841132

10851133
napi_hash_del(&c->napi);
@@ -1125,17 +1173,27 @@ static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
11251173
MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
11261174
}
11271175

1128-
static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1129-
struct mlx5e_sq_param *param)
1176+
static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1177+
struct mlx5e_sq_param *param)
11301178
{
11311179
void *sqc = param->sqc;
11321180
void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
11331181

1134-
MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
11351182
MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
11361183
MLX5_SET(wq, wq, pd, priv->pdn);
11371184

11381185
param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1186+
}
1187+
1188+
static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1189+
struct mlx5e_sq_param *param)
1190+
{
1191+
void *sqc = param->sqc;
1192+
void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1193+
1194+
mlx5e_build_sq_param_common(priv, param);
1195+
MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1196+
11391197
param->max_inline = priv->params.tx_max_inline;
11401198
}
11411199

@@ -1172,20 +1230,49 @@ static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
11721230
{
11731231
void *cqc = param->cqc;
11741232

1175-
MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1233+
MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
11761234

11771235
mlx5e_build_common_cq_param(priv, param);
11781236
}
11791237

1238+
static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1239+
struct mlx5e_cq_param *param,
1240+
u8 log_wq_size)
1241+
{
1242+
void *cqc = param->cqc;
1243+
1244+
MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1245+
1246+
mlx5e_build_common_cq_param(priv, param);
1247+
}
1248+
1249+
static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1250+
struct mlx5e_sq_param *param,
1251+
u8 log_wq_size)
1252+
{
1253+
void *sqc = param->sqc;
1254+
void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1255+
1256+
mlx5e_build_sq_param_common(priv, param);
1257+
1258+
MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1259+
1260+
param->icosq = true;
1261+
}
1262+
11801263
static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
11811264
struct mlx5e_channel_param *cparam)
11821265
{
1266+
u8 icosq_log_wq_sz = 0;
1267+
11831268
memset(cparam, 0, sizeof(*cparam));
11841269

11851270
mlx5e_build_rq_param(priv, &cparam->rq);
11861271
mlx5e_build_sq_param(priv, &cparam->sq);
1272+
mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
11871273
mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
11881274
mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1275+
mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
11891276
}
11901277

11911278
static int mlx5e_open_channels(struct mlx5e_priv *priv)

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
5454

5555
sq->skb[pi] = NULL;
5656
sq->pc++;
57+
sq->stats.nop++;
5758

5859
if (notify_hw) {
5960
cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
@@ -387,7 +388,6 @@ bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
387388
wi = &sq->wqe_info[ci];
388389

389390
if (unlikely(!skb)) { /* nop */
390-
sq->stats.nop++;
391391
sqcc++;
392392
continue;
393393
}

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