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net: atlantic: HW bindings for basic A2 init/deinit hw_ops
This patch adds A2 register definitions for basic A2 HW initialization / deinitialization. Signed-off-by: Dmitry Bogdanov <[email protected]> Co-developed-by: Egor Pomozov <[email protected]> Signed-off-by: Egor Pomozov <[email protected]> Co-developed-by: Igor Russkikh <[email protected]> Signed-off-by: Igor Russkikh <[email protected]> Co-developed-by: Nikita Danilov <[email protected]> Signed-off-by: Nikita Danilov <[email protected]> Signed-off-by: Mark Starovoytov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,55 @@ void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
5858
tag);
5959
}
6060

61+
/* TX */
62+
63+
void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en)
64+
{
65+
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR,
66+
HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK,
67+
HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT,
68+
clk_gate_en);
69+
}
70+
71+
void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
72+
u32 max_credit,
73+
u32 tc)
74+
{
75+
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
76+
HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK,
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HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT,
78+
max_credit);
79+
}
80+
81+
void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
82+
u32 tx_pkt_shed_tc_data_weight,
83+
u32 tc)
84+
{
85+
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc),
86+
HW_ATL2_TPS_DATA_TCTWEIGHT_MSK,
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HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT,
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tx_pkt_shed_tc_data_weight);
89+
}
90+
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u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw)
92+
{
93+
return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR);
94+
}
95+
96+
void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw)
97+
{
98+
u32 hw_ver = hw_atl2_get_hw_version(aq_hw);
99+
100+
aq_hw_write_reg_bit(aq_hw, HW_ATL2_LT_CTRL_ADR,
101+
HW_ATL2_LT_CTRL_CLK_RATIO_MSK,
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HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT,
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hw_ver < HW_ATL2_FPGA_VER_U32(1, 0, 0, 0) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED :
105+
hw_ver >= HW_ATL2_FPGA_VER_U32(1, 0, 85, 2) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED :
107+
HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED);
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}
109+
61110
/* set action resolver record */
62111
void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
63112
u32 tag, u32 mask, u32 action)
@@ -128,3 +177,24 @@ u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw)
128177
HW_ATL2_MIF_MCP_FINISHED_READ_MSK,
129178
HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT);
130179
}
180+
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u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw)
182+
{
183+
return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR);
184+
}
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void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val)
187+
{
188+
return aq_hw_write_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR, val);
189+
}
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u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw)
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{
193+
return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR);
194+
}
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void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val)
197+
{
198+
return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR,
199+
val);
200+
}

‎drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,23 @@ void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,
2929
/* Set VLAN filter tag */
3030
void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter);
3131

32+
/* set tx buffer clock gate enable */
33+
void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en);
34+
35+
/* set tx packet scheduler tc data max credit */
36+
void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
37+
u32 max_credit,
38+
u32 tc);
39+
40+
/* set tx packet scheduler tc data weight */
41+
void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
42+
u32 tx_pkt_shed_tc_data_weight,
43+
u32 tc);
44+
45+
u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw);
46+
47+
void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw);
48+
3249
/* set action resolver record */
3350
void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
3451
u32 tag, u32 mask, u32 action);
@@ -54,4 +71,16 @@ void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish);
5471
/* get mcp finished read shared buffer indication */
5572
u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw);
5673

74+
/* get mcp boot register */
75+
u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw);
76+
77+
/* set mcp boot register */
78+
void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val);
79+
80+
/* get host interrupt request */
81+
u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw);
82+
83+
/* clear host interrupt request */
84+
void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val);
85+
5786
#endif /* HW_ATL2_LLH_H */

‎drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,105 @@
105105
/* default value of bitfield vlan_req_tag0{f}[3:0] */
106106
#define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0
107107

108+
/* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions
109+
* Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]".
110+
* Parameter: Queue {Q} | bit-level stride | range [0, 31]
111+
* PORT="pif_rx_q0_tc_map_i[2:0]"
112+
*/
113+
114+
/* Register address for bitfield rx_q{Q}_tc_map[2:0] */
115+
#define HW_ATL2_RX_Q_TC_MAP_ADR(queue) \
116+
(((queue) < 32) ? 0x00005900 + ((queue) / 8) * 4 : 0)
117+
/* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */
118+
#define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) \
119+
(((queue) < 32) ? ((queue) * 4) % 32 : 0)
120+
/* Width of bitfield rx_q{Q}_tc_map[2:0] */
121+
#define HW_ATL2_RX_Q_TC_MAP_WIDTH 3
122+
/* Default value of bitfield rx_q{Q}_tc_map[2:0] */
123+
#define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0
124+
125+
/* tx tx_buffer_clk_gate_en bitfield definitions
126+
* preprocessor definitions for the bitfield "tx_buffer_clk_gate_en".
127+
* port="pif_tpb_tx_buffer_clk_gate_en_i"
128+
*/
129+
130+
/* register address for bitfield tx_buffer_clk_gate_en */
131+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR 0x00007900
132+
/* bitmask for bitfield tx_buffer_clk_gate_en */
133+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK 0x00000020
134+
/* inverted bitmask for bitfield tx_buffer_clk_gate_en */
135+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN 0xffffffdf
136+
/* lower bit position of bitfield tx_buffer_clk_gate_en */
137+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT 5
138+
/* width of bitfield tx_buffer_clk_gate_en */
139+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH 1
140+
/* default value of bitfield tx_buffer_clk_gate_en */
141+
#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0
142+
143+
/* tx data_tc{t}_credit_max[b:0] bitfield definitions
144+
* preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
145+
* parameter: tc {t} | stride size 0x4 | range [0, 7]
146+
* port="pif_tps_data_tc0_credit_max_i[11:0]"
147+
*/
148+
149+
/* register address for bitfield data_tc{t}_credit_max[b:0] */
150+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
151+
/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
152+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000
153+
/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
154+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff
155+
/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
156+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
157+
/* width of bitfield data_tc{t}_credit_max[b:0] */
158+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 12
159+
/* default value of bitfield data_tc{t}_credit_max[b:0] */
160+
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
161+
162+
/* tx data_tc{t}_weight[8:0] bitfield definitions
163+
* preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
164+
* parameter: tc {t} | stride size 0x4 | range [0, 7]
165+
* port="pif_tps_data_tc0_weight_i[8:0]"
166+
*/
167+
168+
/* register address for bitfield data_tc{t}_weight[8:0] */
169+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
170+
/* bitmask for bitfield data_tc{t}_weight[8:0] */
171+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x000001ff
172+
/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
173+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00
174+
/* lower bit position of bitfield data_tc{t}_weight[8:0] */
175+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0
176+
/* width of bitfield data_tc{t}_weight[8:0] */
177+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 9
178+
/* default value of bitfield data_tc{t}_weight[8:0] */
179+
#define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
180+
181+
/* Launch time control register */
182+
#define HW_ATL2_LT_CTRL_ADR 0x00007a1c
183+
184+
#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK 0xFFFF0000
185+
#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT 16
186+
187+
#define HW_ATL2_LT_CTRL_CLK_RATIO_MSK 0x0000FF00
188+
#define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT 8
189+
#define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED 4
190+
#define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED 2
191+
#define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED 1
192+
193+
#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK 0x00000008
194+
#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT 3
195+
196+
#define HW_ATL2_LT_CTRL_LINK_SPEED_MSK 0x00000007
197+
#define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT 0
198+
199+
/* FPGA VER register */
200+
#define HW_ATL2_FPGA_VER_ADR 0x000000f4
201+
#define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) \
202+
((((mj) & 0xff) << 24) | \
203+
(((mi) & 0xff) << 16) | \
204+
(((bl) & 0xff) << 8) | \
205+
(((rv) & 0xff) << 0))
206+
108207
/* ahb_mem_addr{f}[31:0] Bitfield Definitions
109208
* Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]".
110209
* Parameter: filter {f} | stride size 0x10 | range [0, 127]
@@ -209,4 +308,13 @@
209308
/* Default value of bitfield pif_mcp_finished_buf_rd_i */
210309
#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0
211310

311+
/* Register address for bitfield pif_mcp_boot_reg */
312+
#define HW_ATL2_MIF_BOOT_REG_ADR 0x00003040u
313+
314+
#define HW_ATL2_MCP_HOST_REQ_INT_READY BIT(0)
315+
316+
#define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u
317+
#define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u
318+
#define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u
319+
212320
#endif /* HW_ATL2_LLH_INTERNAL_H */

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